diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 2e619cf..83b942e 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// +// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // +// On Fri Jun 5 17:48:02 BST 2020 // // // Ports: @@ -14,7 +14,7 @@ // dCacheToParent_rsToP_notEmpty O 1 // RDY_dCacheToParent_rsToP_notEmpty O 1 const // RDY_dCacheToParent_rsToP_deq O 1 -// dCacheToParent_rsToP_first O 579 +// dCacheToParent_rsToP_first O 583 // RDY_dCacheToParent_rsToP_first O 1 // dCacheToParent_rqToP_notEmpty O 1 // RDY_dCacheToParent_rqToP_notEmpty O 1 const @@ -27,7 +27,7 @@ // iCacheToParent_rsToP_notEmpty O 1 // RDY_iCacheToParent_rsToP_notEmpty O 1 const // RDY_iCacheToParent_rsToP_deq O 1 -// iCacheToParent_rsToP_first O 579 +// iCacheToParent_rsToP_first O 583 // RDY_iCacheToParent_rsToP_first O 1 // iCacheToParent_rqToP_notEmpty O 1 // RDY_iCacheToParent_rqToP_notEmpty O 1 const @@ -48,7 +48,7 @@ // mmioToPlatform_cRq_notEmpty O 1 // RDY_mmioToPlatform_cRq_notEmpty O 1 const // RDY_mmioToPlatform_cRq_deq O 1 -// mmioToPlatform_cRq_first O 142 +// mmioToPlatform_cRq_first O 215 // RDY_mmioToPlatform_cRq_first O 1 // mmioToPlatform_pRs_notFull O 1 // RDY_mmioToPlatform_pRs_notFull O 1 const @@ -77,16 +77,27 @@ // RDY_deadlock_renameInstStuck_get O 1 const // deadlock_renameCorrectPathStuck_get O 78 const // RDY_deadlock_renameCorrectPathStuck_get O 1 const -// deadlock_commitInstStuck_get O 163 const +// deadlock_commitInstStuck_get O 171 const // RDY_deadlock_commitInstStuck_get O 1 const -// deadlock_commitUserInstStuck_get O 163 const +// deadlock_commitUserInstStuck_get O 171 const // RDY_deadlock_commitUserInstStuck_get O 1 const // RDY_deadlock_checkStarted_get O 1 const -// renameDebug_renameErr_get O 89 const +// renameDebug_renameErr_get O 97 const // RDY_renameDebug_renameErr_get O 1 const // RDY_setMEIP O 1 const // RDY_setSEIP O 1 const -// RDY_setDEIP O 1 const +// RDY_hart0_run_halt_server_request_put O 1 reg +// hart0_run_halt_server_response_get O 1 reg +// RDY_hart0_run_halt_server_response_get O 1 reg +// RDY_hart0_gpr_mem_server_request_put O 1 reg +// hart0_gpr_mem_server_response_get O 65 reg +// RDY_hart0_gpr_mem_server_response_get O 1 reg +// RDY_hart0_fpr_mem_server_request_put O 1 reg +// hart0_fpr_mem_server_response_get O 65 reg +// RDY_hart0_fpr_mem_server_response_get O 1 reg +// RDY_hart0_csr_mem_server_request_put O 1 reg +// hart0_csr_mem_server_response_get O 65 reg +// RDY_hart0_csr_mem_server_response_get O 1 reg // CLK I 1 clock // RST_N I 1 reset // coreReq_start_startpc I 64 @@ -94,16 +105,19 @@ // coreReq_start_fromHostAddr I 64 reg // coreReq_perfReq_loc I 4 reg // coreReq_perfReq_t I 5 reg -// dCacheToParent_fromP_enq_x I 583 -// iCacheToParent_fromP_enq_x I 583 +// dCacheToParent_fromP_enq_x I 587 +// iCacheToParent_fromP_enq_x I 587 // tlbToMem_respLd_enq_x I 65 -// mmioToPlatform_pRs_enq_x I 67 +// mmioToPlatform_pRs_enq_x I 131 // mmioToPlatform_pRq_enq_x I 39 // mmioToPlatform_setTime_t I 64 reg // recvDoStats_x I 1 reg -// setMEIP_v I 1 +// setMEIP_v I 1 reg // setSEIP_v I 1 -// setDEIP_v I 1 +// hart0_run_halt_server_request_put I 1 reg +// hart0_gpr_mem_server_request_put I 70 reg +// hart0_fpr_mem_server_request_put I 70 reg +// hart0_csr_mem_server_request_put I 77 reg // EN_coreReq_start I 1 // EN_coreReq_perfReq I 1 // EN_coreIndInv_terminate I 1 @@ -124,7 +138,10 @@ // EN_deadlock_checkStarted_get I 1 unused // EN_setMEIP I 1 // EN_setSEIP I 1 -// EN_setDEIP I 1 +// EN_hart0_run_halt_server_request_put I 1 +// EN_hart0_gpr_mem_server_request_put I 1 +// EN_hart0_fpr_mem_server_request_put I 1 +// EN_hart0_csr_mem_server_request_put I 1 // EN_coreIndInv_perfResp I 1 // EN_sendDoStats I 1 // EN_deadlock_dCacheCRqStuck_get I 1 unused @@ -136,6 +153,10 @@ // EN_deadlock_commitInstStuck_get I 1 unused // EN_deadlock_commitUserInstStuck_get I 1 unused // EN_renameDebug_renameErr_get I 1 unused +// EN_hart0_run_halt_server_response_get I 1 +// EN_hart0_gpr_mem_server_response_get I 1 +// EN_hart0_fpr_mem_server_response_get I 1 +// EN_hart0_csr_mem_server_response_get I 1 // // No combinational paths from inputs to outputs // @@ -332,9 +353,37 @@ module mkCore(CLK, EN_setSEIP, RDY_setSEIP, - setDEIP_v, - EN_setDEIP, - RDY_setDEIP); + hart0_run_halt_server_request_put, + EN_hart0_run_halt_server_request_put, + RDY_hart0_run_halt_server_request_put, + + EN_hart0_run_halt_server_response_get, + hart0_run_halt_server_response_get, + RDY_hart0_run_halt_server_response_get, + + hart0_gpr_mem_server_request_put, + EN_hart0_gpr_mem_server_request_put, + RDY_hart0_gpr_mem_server_request_put, + + EN_hart0_gpr_mem_server_response_get, + hart0_gpr_mem_server_response_get, + RDY_hart0_gpr_mem_server_response_get, + + hart0_fpr_mem_server_request_put, + EN_hart0_fpr_mem_server_request_put, + RDY_hart0_fpr_mem_server_request_put, + + EN_hart0_fpr_mem_server_response_get, + hart0_fpr_mem_server_response_get, + RDY_hart0_fpr_mem_server_response_get, + + hart0_csr_mem_server_request_put, + EN_hart0_csr_mem_server_request_put, + RDY_hart0_csr_mem_server_request_put, + + EN_hart0_csr_mem_server_response_get, + hart0_csr_mem_server_response_get, + RDY_hart0_csr_mem_server_response_get); input CLK; input RST_N; @@ -369,7 +418,7 @@ module mkCore(CLK, output RDY_dCacheToParent_rsToP_deq; // value method dCacheToParent_rsToP_first - output [578 : 0] dCacheToParent_rsToP_first; + output [582 : 0] dCacheToParent_rsToP_first; output RDY_dCacheToParent_rsToP_first; // value method dCacheToParent_rqToP_notEmpty @@ -389,7 +438,7 @@ module mkCore(CLK, output RDY_dCacheToParent_fromP_notFull; // action method dCacheToParent_fromP_enq - input [582 : 0] dCacheToParent_fromP_enq_x; + input [586 : 0] dCacheToParent_fromP_enq_x; input EN_dCacheToParent_fromP_enq; output RDY_dCacheToParent_fromP_enq; @@ -402,7 +451,7 @@ module mkCore(CLK, output RDY_iCacheToParent_rsToP_deq; // value method iCacheToParent_rsToP_first - output [578 : 0] iCacheToParent_rsToP_first; + output [582 : 0] iCacheToParent_rsToP_first; output RDY_iCacheToParent_rsToP_first; // value method iCacheToParent_rqToP_notEmpty @@ -422,7 +471,7 @@ module mkCore(CLK, output RDY_iCacheToParent_fromP_notFull; // action method iCacheToParent_fromP_enq - input [582 : 0] iCacheToParent_fromP_enq_x; + input [586 : 0] iCacheToParent_fromP_enq_x; input EN_iCacheToParent_fromP_enq; output RDY_iCacheToParent_fromP_enq; @@ -456,7 +505,7 @@ module mkCore(CLK, output RDY_mmioToPlatform_cRq_deq; // value method mmioToPlatform_cRq_first - output [141 : 0] mmioToPlatform_cRq_first; + output [214 : 0] mmioToPlatform_cRq_first; output RDY_mmioToPlatform_cRq_first; // value method mmioToPlatform_pRs_notFull @@ -464,7 +513,7 @@ module mkCore(CLK, output RDY_mmioToPlatform_pRs_notFull; // action method mmioToPlatform_pRs_enq - input [66 : 0] mmioToPlatform_pRs_enq_x; + input [130 : 0] mmioToPlatform_pRs_enq_x; input EN_mmioToPlatform_pRs_enq; output RDY_mmioToPlatform_pRs_enq; @@ -536,12 +585,12 @@ module mkCore(CLK, // actionvalue method deadlock_commitInstStuck_get input EN_deadlock_commitInstStuck_get; - output [162 : 0] deadlock_commitInstStuck_get; + output [170 : 0] deadlock_commitInstStuck_get; output RDY_deadlock_commitInstStuck_get; // actionvalue method deadlock_commitUserInstStuck_get input EN_deadlock_commitUserInstStuck_get; - output [162 : 0] deadlock_commitUserInstStuck_get; + output [170 : 0] deadlock_commitUserInstStuck_get; output RDY_deadlock_commitUserInstStuck_get; // action method deadlock_checkStarted_get @@ -550,7 +599,7 @@ module mkCore(CLK, // actionvalue method renameDebug_renameErr_get input EN_renameDebug_renameErr_get; - output [88 : 0] renameDebug_renameErr_get; + output [96 : 0] renameDebug_renameErr_get; output RDY_renameDebug_renameErr_get; // action method setMEIP @@ -563,17 +612,52 @@ module mkCore(CLK, input EN_setSEIP; output RDY_setSEIP; - // action method setDEIP - input setDEIP_v; - input EN_setDEIP; - output RDY_setDEIP; + // action method hart0_run_halt_server_request_put + input hart0_run_halt_server_request_put; + input EN_hart0_run_halt_server_request_put; + output RDY_hart0_run_halt_server_request_put; + + // actionvalue method hart0_run_halt_server_response_get + input EN_hart0_run_halt_server_response_get; + output hart0_run_halt_server_response_get; + output RDY_hart0_run_halt_server_response_get; + + // action method hart0_gpr_mem_server_request_put + input [69 : 0] hart0_gpr_mem_server_request_put; + input EN_hart0_gpr_mem_server_request_put; + output RDY_hart0_gpr_mem_server_request_put; + + // actionvalue method hart0_gpr_mem_server_response_get + input EN_hart0_gpr_mem_server_response_get; + output [64 : 0] hart0_gpr_mem_server_response_get; + output RDY_hart0_gpr_mem_server_response_get; + + // action method hart0_fpr_mem_server_request_put + input [69 : 0] hart0_fpr_mem_server_request_put; + input EN_hart0_fpr_mem_server_request_put; + output RDY_hart0_fpr_mem_server_request_put; + + // actionvalue method hart0_fpr_mem_server_response_get + input EN_hart0_fpr_mem_server_response_get; + output [64 : 0] hart0_fpr_mem_server_response_get; + output RDY_hart0_fpr_mem_server_response_get; + + // action method hart0_csr_mem_server_request_put + input [76 : 0] hart0_csr_mem_server_request_put; + input EN_hart0_csr_mem_server_request_put; + output RDY_hart0_csr_mem_server_request_put; + + // actionvalue method hart0_csr_mem_server_response_get + input EN_hart0_csr_mem_server_response_get; + output [64 : 0] hart0_csr_mem_server_response_get; + output RDY_hart0_csr_mem_server_response_get; // signals for module outputs - wire [578 : 0] dCacheToParent_rsToP_first, iCacheToParent_rsToP_first; - wire [162 : 0] deadlock_commitInstStuck_get, + wire [582 : 0] dCacheToParent_rsToP_first, iCacheToParent_rsToP_first; + wire [214 : 0] mmioToPlatform_cRq_first; + wire [170 : 0] deadlock_commitInstStuck_get, deadlock_commitUserInstStuck_get; - wire [141 : 0] mmioToPlatform_cRq_first; - wire [88 : 0] renameDebug_renameErr_get; + wire [96 : 0] renameDebug_renameErr_get; wire [77 : 0] deadlock_renameCorrectPathStuck_get, deadlock_renameInstStuck_get; wire [72 : 0] coreIndInv_perfResp, deadlock_dCacheCRqStuck_get; @@ -581,7 +665,10 @@ module mkCore(CLK, wire [67 : 0] deadlock_dCachePRqStuck_get, deadlock_iCacheCRqStuck_get, deadlock_iCachePRqStuck_get; - wire [64 : 0] tlbToMem_memReq_first; + wire [64 : 0] hart0_csr_mem_server_response_get, + hart0_fpr_mem_server_response_get, + hart0_gpr_mem_server_response_get, + tlbToMem_memReq_first; wire RDY_coreIndInv_perfResp, RDY_coreIndInv_terminate, RDY_coreReq_perfReq, @@ -603,6 +690,14 @@ module mkCore(CLK, RDY_deadlock_iCachePRqStuck_get, RDY_deadlock_renameCorrectPathStuck_get, RDY_deadlock_renameInstStuck_get, + RDY_hart0_csr_mem_server_request_put, + RDY_hart0_csr_mem_server_response_get, + RDY_hart0_fpr_mem_server_request_put, + RDY_hart0_fpr_mem_server_response_get, + RDY_hart0_gpr_mem_server_request_put, + RDY_hart0_gpr_mem_server_response_get, + RDY_hart0_run_halt_server_request_put, + RDY_hart0_run_halt_server_response_get, RDY_iCacheToParent_fromP_enq, RDY_iCacheToParent_fromP_notFull, RDY_iCacheToParent_rqToP_deq, @@ -625,7 +720,6 @@ module mkCore(CLK, RDY_recvDoStats, RDY_renameDebug_renameErr_get, RDY_sendDoStats, - RDY_setDEIP, RDY_setMEIP, RDY_setSEIP, RDY_tlbToMem_memReq_deq, @@ -636,6 +730,7 @@ module mkCore(CLK, dCacheToParent_fromP_notFull, dCacheToParent_rqToP_notEmpty, dCacheToParent_rsToP_notEmpty, + hart0_run_halt_server_response_get, iCacheToParent_fromP_notFull, iCacheToParent_rqToP_notEmpty, iCacheToParent_rsToP_notEmpty, @@ -649,27 +744,31 @@ module mkCore(CLK, tlbToMem_respLd_notFull; // inlined wires - reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget; - reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget; + reg [226 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget; + reg [129 : 0] coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget; reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget; reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget; - wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget; - wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget; - wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget; - wire [142 : 0] mmio_cRqQ_enqReq_lat_0$wget, mmio_dataReqQ_enqReq_lat_0$wget; - wire [76 : 0] coreFix_memExe_issueLd$wget; + wire [587 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget; + wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget; + wire [226 : 0] coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget; + wire [215 : 0] mmio_cRqQ_enqReq_lat_0$wget, mmio_dataReqQ_enqReq_lat_0$wget; + wire [169 : 0] coreFix_aluExe_0_bypassWire_0$wget, + coreFix_aluExe_0_bypassWire_1$wget, + coreFix_aluExe_0_bypassWire_2$wget, + coreFix_aluExe_0_bypassWire_3$wget; + wire [152 : 0] csrf_sepcc_reg_data_lat_0$wget; + wire [134 : 0] coreFix_memExe_forwardQ_enqReq_lat_0$wget, + coreFix_memExe_memRespLdQ_enqReq_lat_0$wget; + wire [131 : 0] mmio_pRsQ_enqReq_lat_0$wget; + wire [130 : 0] mmio_dataRespQ_enqReq_lat_0$wget; + wire [84 : 0] coreFix_memExe_issueLd$wget; wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget; - wire [70 : 0] coreFix_aluExe_0_bypassWire_0$wget, - coreFix_aluExe_0_bypassWire_1$wget, - coreFix_aluExe_0_bypassWire_2$wget, - coreFix_aluExe_0_bypassWire_3$wget; - wire [69 : 0] coreFix_memExe_forwardQ_enqReq_lat_0$wget, - coreFix_memExe_memRespLdQ_enqReq_lat_0$wget; + wire [70 : 0] coreFix_fpuMulDivExe_0_bypassWire_0$wget, + coreFix_fpuMulDivExe_0_bypassWire_1$wget, + coreFix_fpuMulDivExe_0_bypassWire_2$wget, + coreFix_fpuMulDivExe_0_bypassWire_3$wget; wire [68 : 0] coreFix_memExe_reqLdQ_data_0_lat_0$wget; - wire [67 : 0] mmio_pRsQ_enqReq_lat_0$wget; - wire [65 : 0] coreFix_memExe_reqStQ_data_0_lat_0$wget, - mmio_dataRespQ_enqReq_lat_0$wget; - wire [63 : 0] csrf_mcycle_ehr_data_lat_0$wget; + wire [65 : 0] coreFix_memExe_reqStQ_data_0_lat_0$wget; wire [39 : 0] mmio_pRqQ_enqReq_lat_0$wget; wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget; wire [1 : 0] mmio_cRsQ_enqReq_lat_0$wget; @@ -703,11 +802,13 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas, coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas, coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas, + csrInstOrInterruptInflight_lat_0$whas, csrInstOrInterruptInflight_lat_1$whas, csrf_mcycle_ehr_data_lat_0$whas, - csrf_minstret_ehr_data_dummy_1_0$whas, + csrf_mepcc_reg_data_lat_1$whas, csrf_minstret_ehr_data_lat_0$whas, csrf_minstret_ehr_data_lat_1$whas, + csrf_sepcc_reg_data_lat_1$whas, mmio_cRqQ_enqReq_lat_0$whas, mmio_dataPendQ_enqReq_lat_0$whas, mmio_dataReqQ_enqReq_lat_0$whas, @@ -715,14 +816,18 @@ module mkCore(CLK, mmio_pRsQ_deqReq_lat_0$whas; // register commitStage_commitTrap - reg [133 : 0] commitStage_commitTrap; - wire [133 : 0] commitStage_commitTrap$D_IN; + reg [238 : 0] commitStage_commitTrap; + wire [238 : 0] commitStage_commitTrap$D_IN; wire commitStage_commitTrap$EN; - // register commitStage_rg_instret - reg [63 : 0] commitStage_rg_instret; - wire [63 : 0] commitStage_rg_instret$D_IN; - wire commitStage_rg_instret$EN; + // register commitStage_rg_run_state + reg commitStage_rg_run_state; + wire commitStage_rg_run_state$D_IN, commitStage_rg_run_state$EN; + + // register commitStage_rg_serial_num + reg [63 : 0] commitStage_rg_serial_num; + reg [63 : 0] commitStage_rg_serial_num$D_IN; + wire commitStage_rg_serial_num$EN; // register coreFix_doStatsReg reg coreFix_doStatsReg; @@ -834,13 +939,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 - reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0; - wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN; + reg [586 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0; + wire [586 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN; wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 - reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1; - wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN; + reg [586 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1; + wire [586 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN; wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP @@ -864,8 +969,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl - reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl; - wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN; + reg [587 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl; + wire [587 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN; wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full @@ -879,13 +984,13 @@ module mkCore(CLK, wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN; // register coreFix_memExe_dMem_cache_m_banks_0_processAmo - reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo; - reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN; + reg [234 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo; + reg [234 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN; wire coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN; // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl - reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl; - wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN; + reg [226 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl; + wire [226 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN; wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN; // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl @@ -949,13 +1054,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 - reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0; - wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN; + reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0; + wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN; wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 - reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1; - wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN; + reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1; + wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN; wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP @@ -979,8 +1084,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl - reg [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl; - wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN; + reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl; + wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN; wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full @@ -1024,13 +1129,13 @@ module mkCore(CLK, coreFix_memExe_forwardQ_clearReq_rl$EN; // register coreFix_memExe_forwardQ_data_0 - reg [68 : 0] coreFix_memExe_forwardQ_data_0; - wire [68 : 0] coreFix_memExe_forwardQ_data_0$D_IN; + reg [133 : 0] coreFix_memExe_forwardQ_data_0; + wire [133 : 0] coreFix_memExe_forwardQ_data_0$D_IN; wire coreFix_memExe_forwardQ_data_0$EN; // register coreFix_memExe_forwardQ_data_1 - reg [68 : 0] coreFix_memExe_forwardQ_data_1; - wire [68 : 0] coreFix_memExe_forwardQ_data_1$D_IN; + reg [133 : 0] coreFix_memExe_forwardQ_data_1; + wire [133 : 0] coreFix_memExe_forwardQ_data_1$D_IN; wire coreFix_memExe_forwardQ_data_1$EN; // register coreFix_memExe_forwardQ_deqP @@ -1051,8 +1156,8 @@ module mkCore(CLK, wire coreFix_memExe_forwardQ_enqP$D_IN, coreFix_memExe_forwardQ_enqP$EN; // register coreFix_memExe_forwardQ_enqReq_rl - reg [69 : 0] coreFix_memExe_forwardQ_enqReq_rl; - wire [69 : 0] coreFix_memExe_forwardQ_enqReq_rl$D_IN; + reg [134 : 0] coreFix_memExe_forwardQ_enqReq_rl; + wire [134 : 0] coreFix_memExe_forwardQ_enqReq_rl$D_IN; wire coreFix_memExe_forwardQ_enqReq_rl$EN; // register coreFix_memExe_forwardQ_full @@ -1065,13 +1170,13 @@ module mkCore(CLK, coreFix_memExe_memRespLdQ_clearReq_rl$EN; // register coreFix_memExe_memRespLdQ_data_0 - reg [68 : 0] coreFix_memExe_memRespLdQ_data_0; - wire [68 : 0] coreFix_memExe_memRespLdQ_data_0$D_IN; + reg [133 : 0] coreFix_memExe_memRespLdQ_data_0; + wire [133 : 0] coreFix_memExe_memRespLdQ_data_0$D_IN; wire coreFix_memExe_memRespLdQ_data_0$EN; // register coreFix_memExe_memRespLdQ_data_1 - reg [68 : 0] coreFix_memExe_memRespLdQ_data_1; - wire [68 : 0] coreFix_memExe_memRespLdQ_data_1$D_IN; + reg [133 : 0] coreFix_memExe_memRespLdQ_data_1; + wire [133 : 0] coreFix_memExe_memRespLdQ_data_1$D_IN; wire coreFix_memExe_memRespLdQ_data_1$EN; // register coreFix_memExe_memRespLdQ_deqP @@ -1093,8 +1198,8 @@ module mkCore(CLK, wire coreFix_memExe_memRespLdQ_enqP$D_IN, coreFix_memExe_memRespLdQ_enqP$EN; // register coreFix_memExe_memRespLdQ_enqReq_rl - reg [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl; - wire [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl$D_IN; + reg [134 : 0] coreFix_memExe_memRespLdQ_enqReq_rl; + wire [134 : 0] coreFix_memExe_memRespLdQ_enqReq_rl$D_IN; wire coreFix_memExe_memRespLdQ_enqReq_rl$EN; // register coreFix_memExe_memRespLdQ_full @@ -1115,8 +1220,8 @@ module mkCore(CLK, wire coreFix_memExe_reqLdQ_full_rl$D_IN, coreFix_memExe_reqLdQ_full_rl$EN; // register coreFix_memExe_reqLrScAmoQ_data_0_rl - reg [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl; - wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN; + reg [226 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl; + wire [226 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN; wire coreFix_memExe_reqLrScAmoQ_data_0_rl$EN; // register coreFix_memExe_reqLrScAmoQ_empty_rl @@ -1148,8 +1253,8 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_clearReq_rl$EN; // register coreFix_memExe_respLrScAmoQ_data_0 - reg [63 : 0] coreFix_memExe_respLrScAmoQ_data_0; - wire [63 : 0] coreFix_memExe_respLrScAmoQ_data_0$D_IN; + reg [128 : 0] coreFix_memExe_respLrScAmoQ_data_0; + wire [128 : 0] coreFix_memExe_respLrScAmoQ_data_0$D_IN; wire coreFix_memExe_respLrScAmoQ_data_0$EN; // register coreFix_memExe_respLrScAmoQ_deqReq_rl @@ -1163,8 +1268,8 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_empty$EN; // register coreFix_memExe_respLrScAmoQ_enqReq_rl - reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl; - wire [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN; + reg [129 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl; + wire [129 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN; wire coreFix_memExe_respLrScAmoQ_enqReq_rl$EN; // register coreFix_memExe_respLrScAmoQ_full @@ -1181,9 +1286,10 @@ module mkCore(CLK, reg csrInstOrInterruptInflight_rl; wire csrInstOrInterruptInflight_rl$D_IN, csrInstOrInterruptInflight_rl$EN; - // register csrf_debug_int_pend - reg csrf_debug_int_pend; - wire csrf_debug_int_pend$D_IN, csrf_debug_int_pend$EN; + // register csrf_ddc_reg + reg [152 : 0] csrf_ddc_reg; + wire [152 : 0] csrf_ddc_reg$D_IN; + wire csrf_ddc_reg$EN; // register csrf_external_int_en_vec_0 reg csrf_external_int_en_vec_0; @@ -1203,7 +1309,8 @@ module mkCore(CLK, // register csrf_external_int_pend_vec_1 reg csrf_external_int_pend_vec_1; - wire csrf_external_int_pend_vec_1$D_IN, csrf_external_int_pend_vec_1$EN; + reg csrf_external_int_pend_vec_1$D_IN; + wire csrf_external_int_pend_vec_1$EN; // register csrf_external_int_pend_vec_3 reg csrf_external_int_pend_vec_3; @@ -1211,7 +1318,7 @@ module mkCore(CLK, // register csrf_fflags_reg reg [4 : 0] csrf_fflags_reg; - wire [4 : 0] csrf_fflags_reg$D_IN; + reg [4 : 0] csrf_fflags_reg$D_IN; wire csrf_fflags_reg$EN; // register csrf_frm_reg @@ -1221,7 +1328,7 @@ module mkCore(CLK, // register csrf_fs_reg reg [1 : 0] csrf_fs_reg; - wire [1 : 0] csrf_fs_reg$D_IN; + reg [1 : 0] csrf_fs_reg$D_IN; wire csrf_fs_reg$EN; // register csrf_ie_vec_0 @@ -1230,20 +1337,33 @@ module mkCore(CLK, // register csrf_ie_vec_1 reg csrf_ie_vec_1; - wire csrf_ie_vec_1$D_IN, csrf_ie_vec_1$EN; + reg csrf_ie_vec_1$D_IN; + wire csrf_ie_vec_1$EN; // register csrf_ie_vec_3 reg csrf_ie_vec_3; - wire csrf_ie_vec_3$D_IN, csrf_ie_vec_3$EN; + reg csrf_ie_vec_3$D_IN; + wire csrf_ie_vec_3$EN; + + // register csrf_mScratchC_reg + reg [152 : 0] csrf_mScratchC_reg; + wire [152 : 0] csrf_mScratchC_reg$D_IN; + wire csrf_mScratchC_reg$EN; // register csrf_mcause_code_reg - reg [3 : 0] csrf_mcause_code_reg; - wire [3 : 0] csrf_mcause_code_reg$D_IN; + reg [4 : 0] csrf_mcause_code_reg; + reg [4 : 0] csrf_mcause_code_reg$D_IN; wire csrf_mcause_code_reg$EN; // register csrf_mcause_interrupt_reg reg csrf_mcause_interrupt_reg; - wire csrf_mcause_interrupt_reg$D_IN, csrf_mcause_interrupt_reg$EN; + reg csrf_mcause_interrupt_reg$D_IN; + wire csrf_mcause_interrupt_reg$EN; + + // register csrf_mccsr_reg + reg [10 : 0] csrf_mccsr_reg; + wire [10 : 0] csrf_mccsr_reg$D_IN; + wire csrf_mccsr_reg$EN; // register csrf_mcounteren_cy_reg reg csrf_mcounteren_cy_reg; @@ -1276,10 +1396,10 @@ module mkCore(CLK, wire [9 : 0] csrf_medeleg_9_0_reg$D_IN; wire csrf_medeleg_9_0_reg$EN; - // register csrf_mepc_csr - reg [63 : 0] csrf_mepc_csr; - wire [63 : 0] csrf_mepc_csr$D_IN; - wire csrf_mepc_csr$EN; + // register csrf_mepcc_reg_data_rl + reg [152 : 0] csrf_mepcc_reg_data_rl; + wire [152 : 0] csrf_mepcc_reg_data_rl$D_IN; + wire csrf_mepcc_reg_data_rl$EN; // register csrf_mideleg_11_reg reg csrf_mideleg_11_reg; @@ -1307,7 +1427,7 @@ module mkCore(CLK, // register csrf_mpp_reg reg [1 : 0] csrf_mpp_reg; - wire [1 : 0] csrf_mpp_reg$D_IN; + reg [1 : 0] csrf_mpp_reg$D_IN; wire csrf_mpp_reg$EN; // register csrf_mprv_reg @@ -1319,20 +1439,21 @@ module mkCore(CLK, wire [63 : 0] csrf_mscratch_csr$D_IN; wire csrf_mscratch_csr$EN; + // register csrf_mtcc_reg + reg [152 : 0] csrf_mtcc_reg; + wire [152 : 0] csrf_mtcc_reg$D_IN; + wire csrf_mtcc_reg$EN; + + // register csrf_mtdc_reg + reg [152 : 0] csrf_mtdc_reg; + wire [152 : 0] csrf_mtdc_reg$D_IN; + wire csrf_mtdc_reg$EN; + // register csrf_mtval_csr reg [63 : 0] csrf_mtval_csr; - wire [63 : 0] csrf_mtval_csr$D_IN; + reg [63 : 0] csrf_mtval_csr$D_IN; wire csrf_mtval_csr$EN; - // register csrf_mtvec_base_hi_reg - reg [61 : 0] csrf_mtvec_base_hi_reg; - wire [61 : 0] csrf_mtvec_base_hi_reg$D_IN; - wire csrf_mtvec_base_hi_reg$EN; - - // register csrf_mtvec_mode_low_reg - reg csrf_mtvec_mode_low_reg; - wire csrf_mtvec_mode_low_reg$D_IN, csrf_mtvec_mode_low_reg$EN; - // register csrf_mxr_reg reg csrf_mxr_reg; wire csrf_mxr_reg$D_IN, csrf_mxr_reg$EN; @@ -1348,25 +1469,77 @@ module mkCore(CLK, // register csrf_prev_ie_vec_1 reg csrf_prev_ie_vec_1; - wire csrf_prev_ie_vec_1$D_IN, csrf_prev_ie_vec_1$EN; + reg csrf_prev_ie_vec_1$D_IN; + wire csrf_prev_ie_vec_1$EN; // register csrf_prev_ie_vec_3 reg csrf_prev_ie_vec_3; - wire csrf_prev_ie_vec_3$D_IN, csrf_prev_ie_vec_3$EN; + reg csrf_prev_ie_vec_3$D_IN; + wire csrf_prev_ie_vec_3$EN; // register csrf_prv_reg reg [1 : 0] csrf_prv_reg; - wire [1 : 0] csrf_prv_reg$D_IN; + reg [1 : 0] csrf_prv_reg$D_IN; wire csrf_prv_reg$EN; + // register csrf_rg_dcsr + reg [63 : 0] csrf_rg_dcsr; + reg [63 : 0] csrf_rg_dcsr$D_IN; + wire csrf_rg_dcsr$EN; + + // register csrf_rg_dpc + reg [152 : 0] csrf_rg_dpc; + wire [152 : 0] csrf_rg_dpc$D_IN; + wire csrf_rg_dpc$EN; + + // register csrf_rg_dscratch0 + reg [63 : 0] csrf_rg_dscratch0; + wire [63 : 0] csrf_rg_dscratch0$D_IN; + wire csrf_rg_dscratch0$EN; + + // register csrf_rg_dscratch1 + reg [63 : 0] csrf_rg_dscratch1; + wire [63 : 0] csrf_rg_dscratch1$D_IN; + wire csrf_rg_dscratch1$EN; + + // register csrf_rg_tdata1_data + reg [58 : 0] csrf_rg_tdata1_data; + wire [58 : 0] csrf_rg_tdata1_data$D_IN; + wire csrf_rg_tdata1_data$EN; + + // register csrf_rg_tdata1_dmode + reg csrf_rg_tdata1_dmode; + wire csrf_rg_tdata1_dmode$D_IN, csrf_rg_tdata1_dmode$EN; + + // register csrf_rg_tdata2 + reg [63 : 0] csrf_rg_tdata2; + wire [63 : 0] csrf_rg_tdata2$D_IN; + wire csrf_rg_tdata2$EN; + + // register csrf_rg_tdata3 + reg [63 : 0] csrf_rg_tdata3; + wire [63 : 0] csrf_rg_tdata3$D_IN; + wire csrf_rg_tdata3$EN; + + // register csrf_rg_tselect + reg [63 : 0] csrf_rg_tselect; + wire [63 : 0] csrf_rg_tselect$D_IN; + wire csrf_rg_tselect$EN; + + // register csrf_sScratchC_reg + reg [152 : 0] csrf_sScratchC_reg; + wire [152 : 0] csrf_sScratchC_reg$D_IN; + wire csrf_sScratchC_reg$EN; + // register csrf_scause_code_reg - reg [3 : 0] csrf_scause_code_reg; - wire [3 : 0] csrf_scause_code_reg$D_IN; + reg [4 : 0] csrf_scause_code_reg; + reg [4 : 0] csrf_scause_code_reg$D_IN; wire csrf_scause_code_reg$EN; // register csrf_scause_interrupt_reg reg csrf_scause_interrupt_reg; - wire csrf_scause_interrupt_reg$D_IN, csrf_scause_interrupt_reg$EN; + reg csrf_scause_interrupt_reg$D_IN; + wire csrf_scause_interrupt_reg$EN; // register csrf_scounteren_cy_reg reg csrf_scounteren_cy_reg; @@ -1380,10 +1553,10 @@ module mkCore(CLK, reg csrf_scounteren_tm_reg; wire csrf_scounteren_tm_reg$D_IN, csrf_scounteren_tm_reg$EN; - // register csrf_sepc_csr - reg [63 : 0] csrf_sepc_csr; - wire [63 : 0] csrf_sepc_csr$D_IN; - wire csrf_sepc_csr$EN; + // register csrf_sepcc_reg_data_rl + reg [152 : 0] csrf_sepcc_reg_data_rl; + wire [152 : 0] csrf_sepcc_reg_data_rl$D_IN; + wire csrf_sepcc_reg_data_rl$EN; // register csrf_software_int_en_vec_0 reg csrf_software_int_en_vec_0; @@ -1411,7 +1584,8 @@ module mkCore(CLK, // register csrf_spp_reg reg csrf_spp_reg; - wire csrf_spp_reg$D_IN, csrf_spp_reg$EN; + reg csrf_spp_reg$D_IN; + wire csrf_spp_reg$EN; // register csrf_sscratch_csr reg [63 : 0] csrf_sscratch_csr; @@ -1422,20 +1596,21 @@ module mkCore(CLK, reg csrf_stats_module_doStats; wire csrf_stats_module_doStats$D_IN, csrf_stats_module_doStats$EN; + // register csrf_stcc_reg + reg [152 : 0] csrf_stcc_reg; + wire [152 : 0] csrf_stcc_reg$D_IN; + wire csrf_stcc_reg$EN; + + // register csrf_stdc_reg + reg [152 : 0] csrf_stdc_reg; + wire [152 : 0] csrf_stdc_reg$D_IN; + wire csrf_stdc_reg$EN; + // register csrf_stval_csr reg [63 : 0] csrf_stval_csr; - wire [63 : 0] csrf_stval_csr$D_IN; + reg [63 : 0] csrf_stval_csr$D_IN; wire csrf_stval_csr$EN; - // register csrf_stvec_base_hi_reg - reg [61 : 0] csrf_stvec_base_hi_reg; - wire [61 : 0] csrf_stvec_base_hi_reg$D_IN; - wire csrf_stvec_base_hi_reg$EN; - - // register csrf_stvec_mode_low_reg - reg csrf_stvec_mode_low_reg; - wire csrf_stvec_mode_low_reg$D_IN, csrf_stvec_mode_low_reg$EN; - // register csrf_sum_reg reg csrf_sum_reg; wire csrf_sum_reg$D_IN, csrf_sum_reg$EN; @@ -1485,6 +1660,14 @@ module mkCore(CLK, reg csrf_vm_mode_sv39_reg; wire csrf_vm_mode_sv39_reg$D_IN, csrf_vm_mode_sv39_reg$EN; + // register flush_brpred + reg flush_brpred; + wire flush_brpred$D_IN, flush_brpred$EN; + + // register flush_caches + reg flush_caches; + wire flush_caches$D_IN, flush_caches$EN; + // register flush_reservation reg flush_reservation; wire flush_reservation$D_IN, flush_reservation$EN; @@ -1498,8 +1681,8 @@ module mkCore(CLK, wire mmio_cRqQ_clearReq_rl$D_IN, mmio_cRqQ_clearReq_rl$EN; // register mmio_cRqQ_data_0 - reg [141 : 0] mmio_cRqQ_data_0; - wire [141 : 0] mmio_cRqQ_data_0$D_IN; + reg [214 : 0] mmio_cRqQ_data_0; + wire [214 : 0] mmio_cRqQ_data_0$D_IN; wire mmio_cRqQ_data_0$EN; // register mmio_cRqQ_deqReq_rl @@ -1511,8 +1694,8 @@ module mkCore(CLK, wire mmio_cRqQ_empty$D_IN, mmio_cRqQ_empty$EN; // register mmio_cRqQ_enqReq_rl - reg [142 : 0] mmio_cRqQ_enqReq_rl; - wire [142 : 0] mmio_cRqQ_enqReq_rl$D_IN; + reg [215 : 0] mmio_cRqQ_enqReq_rl; + wire [215 : 0] mmio_cRqQ_enqReq_rl$D_IN; wire mmio_cRqQ_enqReq_rl$EN; // register mmio_cRqQ_full @@ -1569,8 +1752,8 @@ module mkCore(CLK, wire mmio_dataReqQ_clearReq_rl$D_IN, mmio_dataReqQ_clearReq_rl$EN; // register mmio_dataReqQ_data_0 - reg [141 : 0] mmio_dataReqQ_data_0; - wire [141 : 0] mmio_dataReqQ_data_0$D_IN; + reg [214 : 0] mmio_dataReqQ_data_0; + wire [214 : 0] mmio_dataReqQ_data_0$D_IN; wire mmio_dataReqQ_data_0$EN; // register mmio_dataReqQ_deqReq_rl @@ -1582,8 +1765,8 @@ module mkCore(CLK, wire mmio_dataReqQ_empty$D_IN, mmio_dataReqQ_empty$EN; // register mmio_dataReqQ_enqReq_rl - reg [142 : 0] mmio_dataReqQ_enqReq_rl; - wire [142 : 0] mmio_dataReqQ_enqReq_rl$D_IN; + reg [215 : 0] mmio_dataReqQ_enqReq_rl; + wire [215 : 0] mmio_dataReqQ_enqReq_rl$D_IN; wire mmio_dataReqQ_enqReq_rl$EN; // register mmio_dataReqQ_full @@ -1595,8 +1778,8 @@ module mkCore(CLK, wire mmio_dataRespQ_clearReq_rl$D_IN, mmio_dataRespQ_clearReq_rl$EN; // register mmio_dataRespQ_data_0 - reg [64 : 0] mmio_dataRespQ_data_0; - wire [64 : 0] mmio_dataRespQ_data_0$D_IN; + reg [129 : 0] mmio_dataRespQ_data_0; + wire [129 : 0] mmio_dataRespQ_data_0$D_IN; wire mmio_dataRespQ_data_0$EN; // register mmio_dataRespQ_deqReq_rl @@ -1608,8 +1791,8 @@ module mkCore(CLK, wire mmio_dataRespQ_empty$D_IN, mmio_dataRespQ_empty$EN; // register mmio_dataRespQ_enqReq_rl - reg [65 : 0] mmio_dataRespQ_enqReq_rl; - wire [65 : 0] mmio_dataRespQ_enqReq_rl$D_IN; + reg [130 : 0] mmio_dataRespQ_enqReq_rl; + wire [130 : 0] mmio_dataRespQ_enqReq_rl$D_IN; wire mmio_dataRespQ_enqReq_rl$EN; // register mmio_dataRespQ_full @@ -1652,8 +1835,8 @@ module mkCore(CLK, wire mmio_pRsQ_clearReq_rl$D_IN, mmio_pRsQ_clearReq_rl$EN; // register mmio_pRsQ_data_0 - reg [66 : 0] mmio_pRsQ_data_0; - wire [66 : 0] mmio_pRsQ_data_0$D_IN; + reg [130 : 0] mmio_pRsQ_data_0; + wire [130 : 0] mmio_pRsQ_data_0$D_IN; wire mmio_pRsQ_data_0$EN; // register mmio_pRsQ_deqReq_rl @@ -1665,8 +1848,8 @@ module mkCore(CLK, wire mmio_pRsQ_empty$D_IN, mmio_pRsQ_empty$EN; // register mmio_pRsQ_enqReq_rl - reg [67 : 0] mmio_pRsQ_enqReq_rl; - wire [67 : 0] mmio_pRsQ_enqReq_rl$D_IN; + reg [131 : 0] mmio_pRsQ_enqReq_rl; + wire [131 : 0] mmio_pRsQ_enqReq_rl$D_IN; wire mmio_pRsQ_enqReq_rl$EN; // register mmio_pRsQ_full @@ -1682,6 +1865,16 @@ module mkCore(CLK, reg outOfReset; wire outOfReset$D_IN, outOfReset$EN; + // register renameStage_rg_m_halt_req + reg [4 : 0] renameStage_rg_m_halt_req; + reg [4 : 0] renameStage_rg_m_halt_req$D_IN; + wire renameStage_rg_m_halt_req$EN; + + // register rg_core_run_state + reg [1 : 0] rg_core_run_state; + reg [1 : 0] rg_core_run_state$D_IN; + wire rg_core_run_state$EN; + // register started reg started; wire started$D_IN, started$EN; @@ -1692,7 +1885,7 @@ module mkCore(CLK, // ports of submodule coreFix_aluExe_0_dispToRegQ reg [3 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag; - wire [157 : 0] coreFix_aluExe_0_dispToRegQ$enq_x, + wire [229 : 0] coreFix_aluExe_0_dispToRegQ$enq_x, coreFix_aluExe_0_dispToRegQ$first; wire [11 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask; wire coreFix_aluExe_0_dispToRegQ$EN_deq, @@ -1706,8 +1899,8 @@ module mkCore(CLK, // ports of submodule coreFix_aluExe_0_exeToFinQ reg [3 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag; - wire [325 : 0] coreFix_aluExe_0_exeToFinQ$enq_x, - coreFix_aluExe_0_exeToFinQ$first; + wire [1066 : 0] coreFix_aluExe_0_exeToFinQ$enq_x, + coreFix_aluExe_0_exeToFinQ$first; wire [11 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask; wire coreFix_aluExe_0_exeToFinQ$EN_deq, coreFix_aluExe_0_exeToFinQ$EN_enq, @@ -1720,7 +1913,7 @@ module mkCore(CLK, // ports of submodule coreFix_aluExe_0_regToExeQ reg [3 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag; - wire [421 : 0] coreFix_aluExe_0_regToExeQ$enq_x, + wire [821 : 0] coreFix_aluExe_0_regToExeQ$enq_x, coreFix_aluExe_0_regToExeQ$first; wire [11 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask; wire coreFix_aluExe_0_regToExeQ$EN_deq, @@ -1736,7 +1929,7 @@ module mkCore(CLK, reg [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_2_put, coreFix_aluExe_0_rsAlu$setRegReady_4_put; reg [3 : 0] coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag; - wire [161 : 0] coreFix_aluExe_0_rsAlu$dispatchData, + wire [233 : 0] coreFix_aluExe_0_rsAlu$dispatchData, coreFix_aluExe_0_rsAlu$enq_x; wire [11 : 0] coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask; wire [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_0_put, @@ -1762,7 +1955,7 @@ module mkCore(CLK, // ports of submodule coreFix_aluExe_1_dispToRegQ reg [3 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag; - wire [157 : 0] coreFix_aluExe_1_dispToRegQ$enq_x, + wire [229 : 0] coreFix_aluExe_1_dispToRegQ$enq_x, coreFix_aluExe_1_dispToRegQ$first; wire [11 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask; wire coreFix_aluExe_1_dispToRegQ$EN_deq, @@ -1776,8 +1969,8 @@ module mkCore(CLK, // ports of submodule coreFix_aluExe_1_exeToFinQ reg [3 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag; - wire [325 : 0] coreFix_aluExe_1_exeToFinQ$enq_x, - coreFix_aluExe_1_exeToFinQ$first; + wire [1066 : 0] coreFix_aluExe_1_exeToFinQ$enq_x, + coreFix_aluExe_1_exeToFinQ$first; wire [11 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask; wire coreFix_aluExe_1_exeToFinQ$EN_deq, coreFix_aluExe_1_exeToFinQ$EN_enq, @@ -1790,7 +1983,7 @@ module mkCore(CLK, // ports of submodule coreFix_aluExe_1_regToExeQ reg [3 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag; - wire [421 : 0] coreFix_aluExe_1_regToExeQ$enq_x, + wire [821 : 0] coreFix_aluExe_1_regToExeQ$enq_x, coreFix_aluExe_1_regToExeQ$first; wire [11 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask; wire coreFix_aluExe_1_regToExeQ$EN_deq, @@ -1806,7 +1999,7 @@ module mkCore(CLK, reg [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_2_put, coreFix_aluExe_1_rsAlu$setRegReady_4_put; reg [3 : 0] coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag; - wire [161 : 0] coreFix_aluExe_1_rsAlu$dispatchData, + wire [233 : 0] coreFix_aluExe_1_rsAlu$dispatchData, coreFix_aluExe_1_rsAlu$enq_x; wire [11 : 0] coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask; wire [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_0_put, @@ -1832,7 +2025,7 @@ module mkCore(CLK, // ports of submodule coreFix_fpuMulDivExe_0_dispToRegQ reg [3 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag; - wire [77 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$enq_x, + wire [86 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$enq_x, coreFix_fpuMulDivExe_0_dispToRegQ$first; wire [11 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask; wire coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq, @@ -2003,7 +2196,7 @@ module mkCore(CLK, // ports of submodule coreFix_fpuMulDivExe_0_regToExeQ reg [3 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag; - wire [245 : 0] coreFix_fpuMulDivExe_0_regToExeQ$enq_x, + wire [254 : 0] coreFix_fpuMulDivExe_0_regToExeQ$enq_x, coreFix_fpuMulDivExe_0_regToExeQ$first; wire [11 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask; wire coreFix_fpuMulDivExe_0_regToExeQ$EN_deq, @@ -2019,7 +2212,7 @@ module mkCore(CLK, reg [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put, coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put; reg [3 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag; - wire [86 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData, + wire [95 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData, coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x; wire [11 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask; wire [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put, @@ -2044,15 +2237,15 @@ module mkCore(CLK, // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n; - wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d, + wire [516 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData; - wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r, + wire [226 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq; wire [63 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr; - wire [57 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot, + wire [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot; @@ -2087,88 +2280,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry; - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN, - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2 - wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN, - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2 - wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN, - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN, - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2 - wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN, - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2 - wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN, - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN, - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN, - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT; - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr - wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d, + wire [516 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData; wire [65 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq, @@ -2191,71 +2304,17 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry; // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline - reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r; - reg [569 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam; + reg [587 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r; + reg [574 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam; reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq; reg coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep; - wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$first; + wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$first; wire coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite, coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send, coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite, coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first, coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send; - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2 - wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2 - wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT; - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN, coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT; @@ -2283,41 +2342,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ, coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N; - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN, - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2 - wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN, - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2 - wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN, - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT; - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN, coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT; @@ -2327,80 +2351,10 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ, coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N; - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN, - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2 - wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN, - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0 - wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1 - wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2 - wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN, - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN, - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0 - wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN, - coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1 - wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN, - coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN, - coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0 - wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN, - coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1 - wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN, - coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2 - wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN, - coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN, - coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0 - wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN, - coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1 - wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN, - coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2 - wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN, - coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN, - coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT; - // ports of submodule coreFix_memExe_dTlb reg [3 : 0] coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag; - wire [174 : 0] coreFix_memExe_dTlb$procResp; - wire [105 : 0] coreFix_memExe_dTlb$procReq_req; + wire [560 : 0] coreFix_memExe_dTlb$procResp; + wire [490 : 0] coreFix_memExe_dTlb$procReq_req; wire [82 : 0] coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x; wire [48 : 0] coreFix_memExe_dTlb$updateVMInfo_vm; wire [28 : 0] coreFix_memExe_dTlb$toParent_rqToP_first; @@ -2435,8 +2389,8 @@ module mkCore(CLK, // ports of submodule coreFix_memExe_dispToRegQ reg [3 : 0] coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag; - wire [97 : 0] coreFix_memExe_dispToRegQ$enq_x, - coreFix_memExe_dispToRegQ$first; + wire [144 : 0] coreFix_memExe_dispToRegQ$enq_x, + coreFix_memExe_dispToRegQ$first; wire [11 : 0] coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask; wire coreFix_memExe_dispToRegQ$EN_deq, coreFix_memExe_dispToRegQ$EN_enq, @@ -2447,55 +2401,24 @@ module mkCore(CLK, coreFix_memExe_dispToRegQ$RDY_first, coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all; - // ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_0 - wire coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN, - coreFix_memExe_forwardQ_clearReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_1 - wire coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN, - coreFix_memExe_forwardQ_clearReq_dummy2_1$EN, - coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_0 - wire coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN, - coreFix_memExe_forwardQ_deqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_1 - wire coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN, - coreFix_memExe_forwardQ_deqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_2 - wire coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN, - coreFix_memExe_forwardQ_deqReq_dummy2_2$EN, - coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_0 - wire coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN, - coreFix_memExe_forwardQ_enqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_1 - wire coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN, - coreFix_memExe_forwardQ_enqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_2 - wire coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN, - coreFix_memExe_forwardQ_enqReq_dummy2_2$EN, - coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT; - // ports of submodule coreFix_memExe_lsq reg [3 : 0] coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag; - wire [170 : 0] coreFix_memExe_lsq$firstSt; - wire [113 : 0] coreFix_memExe_lsq$firstLd; - wire [76 : 0] coreFix_memExe_lsq$getIssueLd; - wire [74 : 0] coreFix_memExe_lsq$issueLd; - wire [73 : 0] coreFix_memExe_lsq$respLd; - wire [67 : 0] coreFix_memExe_lsq$issueLd_sbRes; + wire [252 : 0] coreFix_memExe_lsq$firstSt; + wire [143 : 0] coreFix_memExe_lsq$firstLd; + wire [139 : 0] coreFix_memExe_lsq$issueLd; + wire [138 : 0] coreFix_memExe_lsq$respLd; + wire [132 : 0] coreFix_memExe_lsq$issueLd_sbRes; + wire [128 : 0] coreFix_memExe_lsq$respLd_alignedData, + coreFix_memExe_lsq$updateData_d; + wire [84 : 0] coreFix_memExe_lsq$getIssueLd; wire [63 : 0] coreFix_memExe_lsq$issueLd_paddr, - coreFix_memExe_lsq$respLd_alignedData, - coreFix_memExe_lsq$updateAddr_paddr, - coreFix_memExe_lsq$updateData_d; - wire [17 : 0] coreFix_memExe_lsq$enqLd_mem_inst, + coreFix_memExe_lsq$updateAddr_paddr; + wire [26 : 0] coreFix_memExe_lsq$enqLd_mem_inst, coreFix_memExe_lsq$enqSt_mem_inst; + wire [15 : 0] coreFix_memExe_lsq$getOrigBE, + coreFix_memExe_lsq$issueLd_shiftedBE, + coreFix_memExe_lsq$updateAddr_shiftedBE; + wire [13 : 0] coreFix_memExe_lsq$updateAddr_fault; wire [11 : 0] coreFix_memExe_lsq$enqLd_inst_tag, coreFix_memExe_lsq$enqLd_spec_bits, coreFix_memExe_lsq$enqSt_inst_tag, @@ -2503,18 +2426,13 @@ module mkCore(CLK, coreFix_memExe_lsq$specUpdate_correctSpeculation_mask; wire [9 : 0] coreFix_memExe_lsq$getHit; wire [8 : 0] coreFix_memExe_lsq$enqLd_dst, coreFix_memExe_lsq$enqSt_dst; - wire [7 : 0] coreFix_memExe_lsq$getOrigBE, - coreFix_memExe_lsq$issueLd_shiftedBE, - coreFix_memExe_lsq$updateAddr_shiftedBE; wire [6 : 0] coreFix_memExe_lsq$enqLdTag, coreFix_memExe_lsq$enqStTag; wire [5 : 0] coreFix_memExe_lsq$getHit_t, coreFix_memExe_lsq$getOrigBE_t, coreFix_memExe_lsq$setAtCommit_0_put, coreFix_memExe_lsq$setAtCommit_1_put, coreFix_memExe_lsq$updateAddr_lsqTag; - wire [4 : 0] coreFix_memExe_lsq$issueLd_lsqTag, - coreFix_memExe_lsq$respLd_t, - coreFix_memExe_lsq$updateAddr_fault; + wire [4 : 0] coreFix_memExe_lsq$issueLd_lsqTag, coreFix_memExe_lsq$respLd_t; wire [3 : 0] coreFix_memExe_lsq$updateData_t; wire [1 : 0] coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx; wire coreFix_memExe_lsq$EN_deqLd, @@ -2539,49 +2457,15 @@ module mkCore(CLK, coreFix_memExe_lsq$RDY_firstLd, coreFix_memExe_lsq$RDY_firstSt, coreFix_memExe_lsq$RDY_getIssueLd, + coreFix_memExe_lsq$noWrongPathLoads, coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all, coreFix_memExe_lsq$stqEmpty, coreFix_memExe_lsq$updateAddr, coreFix_memExe_lsq$updateAddr_isMMIO; - // ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0 - wire coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN, - coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1 - wire coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN, - coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN, - coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0 - wire coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN, - coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1 - wire coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN, - coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2 - wire coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN, - coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN, - coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0 - wire coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN, - coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1 - wire coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN, - coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2 - wire coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN, - coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN, - coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT; - // ports of submodule coreFix_memExe_regToExeQ reg [3 : 0] coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag; - wire [192 : 0] coreFix_memExe_regToExeQ$enq_x, + wire [436 : 0] coreFix_memExe_regToExeQ$enq_x, coreFix_memExe_regToExeQ$first; wire [11 : 0] coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask; wire coreFix_memExe_regToExeQ$EN_deq, @@ -2593,208 +2477,11 @@ module mkCore(CLK, coreFix_memExe_regToExeQ$RDY_first, coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all; - // ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_0 - wire coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN, - coreFix_memExe_reqLdQ_data_0_dummy2_0$EN; - - // ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_1 - wire coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN, - coreFix_memExe_reqLdQ_data_0_dummy2_1$EN, - coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_0 - wire coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN, - coreFix_memExe_reqLdQ_deqP_dummy2_0$EN; - - // ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_1 - wire coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN, - coreFix_memExe_reqLdQ_deqP_dummy2_1$EN; - - // ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_0 - wire coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN, - coreFix_memExe_reqLdQ_empty_dummy2_0$EN; - - // ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_1 - wire coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN, - coreFix_memExe_reqLdQ_empty_dummy2_1$EN, - coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_2 - wire coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN, - coreFix_memExe_reqLdQ_empty_dummy2_2$EN, - coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_0 - wire coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN, - coreFix_memExe_reqLdQ_enqP_dummy2_0$EN; - - // ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_1 - wire coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN, - coreFix_memExe_reqLdQ_enqP_dummy2_1$EN; - - // ports of submodule coreFix_memExe_reqLdQ_full_dummy2_0 - wire coreFix_memExe_reqLdQ_full_dummy2_0$D_IN, - coreFix_memExe_reqLdQ_full_dummy2_0$EN, - coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT; - - // ports of submodule coreFix_memExe_reqLdQ_full_dummy2_1 - wire coreFix_memExe_reqLdQ_full_dummy2_1$D_IN, - coreFix_memExe_reqLdQ_full_dummy2_1$EN, - coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_reqLdQ_full_dummy2_2 - wire coreFix_memExe_reqLdQ_full_dummy2_2$D_IN, - coreFix_memExe_reqLdQ_full_dummy2_2$EN, - coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0 - wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN; - - // ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1 - wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0 - wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN, - coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN; - - // ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1 - wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN, - coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN; - - // ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0 - wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN, - coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN; - - // ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1 - wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN, - coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN, - coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2 - wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN, - coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN, - coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0 - wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN, - coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN; - - // ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1 - wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN, - coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN; - - // ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0 - wire coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN, - coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN, - coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT; - - // ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1 - wire coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN, - coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN, - coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2 - wire coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN, - coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN, - coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_0 - wire coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN, - coreFix_memExe_reqStQ_data_0_dummy2_0$EN; - - // ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_1 - wire coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN, - coreFix_memExe_reqStQ_data_0_dummy2_1$EN, - coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_0 - wire coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN, - coreFix_memExe_reqStQ_deqP_dummy2_0$EN; - - // ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_1 - wire coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN, - coreFix_memExe_reqStQ_deqP_dummy2_1$EN; - - // ports of submodule coreFix_memExe_reqStQ_empty_dummy2_0 - wire coreFix_memExe_reqStQ_empty_dummy2_0$D_IN, - coreFix_memExe_reqStQ_empty_dummy2_0$EN; - - // ports of submodule coreFix_memExe_reqStQ_empty_dummy2_1 - wire coreFix_memExe_reqStQ_empty_dummy2_1$D_IN, - coreFix_memExe_reqStQ_empty_dummy2_1$EN, - coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_reqStQ_empty_dummy2_2 - wire coreFix_memExe_reqStQ_empty_dummy2_2$D_IN, - coreFix_memExe_reqStQ_empty_dummy2_2$EN, - coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_0 - wire coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN, - coreFix_memExe_reqStQ_enqP_dummy2_0$EN; - - // ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_1 - wire coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN, - coreFix_memExe_reqStQ_enqP_dummy2_1$EN; - - // ports of submodule coreFix_memExe_reqStQ_full_dummy2_0 - wire coreFix_memExe_reqStQ_full_dummy2_0$D_IN, - coreFix_memExe_reqStQ_full_dummy2_0$EN, - coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT; - - // ports of submodule coreFix_memExe_reqStQ_full_dummy2_1 - wire coreFix_memExe_reqStQ_full_dummy2_1$D_IN, - coreFix_memExe_reqStQ_full_dummy2_1$EN, - coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_reqStQ_full_dummy2_2 - wire coreFix_memExe_reqStQ_full_dummy2_2$D_IN, - coreFix_memExe_reqStQ_full_dummy2_2$EN, - coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0 - wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN, - coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1 - wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN, - coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN, - coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0 - wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN, - coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1 - wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN, - coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2 - wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN, - coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN, - coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0 - wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN, - coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN; - - // ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1 - wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN, - coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN; - - // ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2 - wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN, - coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN, - coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT; - // ports of submodule coreFix_memExe_rsMem reg [7 : 0] coreFix_memExe_rsMem$setRegReady_2_put, coreFix_memExe_rsMem$setRegReady_4_put; reg [3 : 0] coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag; - wire [106 : 0] coreFix_memExe_rsMem$dispatchData, + wire [153 : 0] coreFix_memExe_rsMem$dispatchData, coreFix_memExe_rsMem$enq_x; wire [11 : 0] coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask; wire [7 : 0] coreFix_memExe_rsMem$setRegReady_0_put, @@ -2818,19 +2505,19 @@ module mkCore(CLK, coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all; // ports of submodule coreFix_memExe_stb - wire [635 : 0] coreFix_memExe_stb$issue; - wire [633 : 0] coreFix_memExe_stb$deq; - wire [67 : 0] coreFix_memExe_stb$search; - wire [63 : 0] coreFix_memExe_stb$enq_data, - coreFix_memExe_stb$enq_paddr, + wire [639 : 0] coreFix_memExe_stb$issue; + wire [637 : 0] coreFix_memExe_stb$deq; + wire [132 : 0] coreFix_memExe_stb$search; + wire [128 : 0] coreFix_memExe_stb$enq_data; + wire [63 : 0] coreFix_memExe_stb$enq_paddr, coreFix_memExe_stb$getEnqIndex_paddr, coreFix_memExe_stb$noMatchLdQ_paddr, coreFix_memExe_stb$noMatchStQ_paddr, coreFix_memExe_stb$search_paddr; - wire [7 : 0] coreFix_memExe_stb$enq_be, - coreFix_memExe_stb$noMatchLdQ_be, - coreFix_memExe_stb$noMatchStQ_be, - coreFix_memExe_stb$search_be; + wire [15 : 0] coreFix_memExe_stb$enq_be, + coreFix_memExe_stb$noMatchLdQ_be, + coreFix_memExe_stb$noMatchStQ_be, + coreFix_memExe_stb$search_be; wire [2 : 0] coreFix_memExe_stb$getEnqIndex; wire [1 : 0] coreFix_memExe_stb$deq_idx, coreFix_memExe_stb$enq_idx; wire coreFix_memExe_stb$EN_deq, @@ -2844,7 +2531,7 @@ module mkCore(CLK, coreFix_memExe_stb$noMatchStQ; // ports of submodule coreFix_trainBPQ_0 - wire [158 : 0] coreFix_trainBPQ_0$D_IN, coreFix_trainBPQ_0$D_OUT; + wire [289 : 0] coreFix_trainBPQ_0$D_IN, coreFix_trainBPQ_0$D_OUT; wire coreFix_trainBPQ_0$CLR, coreFix_trainBPQ_0$DEQ, coreFix_trainBPQ_0$EMPTY_N, @@ -2852,43 +2539,13 @@ module mkCore(CLK, coreFix_trainBPQ_0$FULL_N; // ports of submodule coreFix_trainBPQ_1 - wire [158 : 0] coreFix_trainBPQ_1$D_IN, coreFix_trainBPQ_1$D_OUT; + wire [289 : 0] coreFix_trainBPQ_1$D_IN, coreFix_trainBPQ_1$D_OUT; wire coreFix_trainBPQ_1$CLR, coreFix_trainBPQ_1$DEQ, coreFix_trainBPQ_1$EMPTY_N, coreFix_trainBPQ_1$ENQ, coreFix_trainBPQ_1$FULL_N; - // ports of submodule csrInstOrInterruptInflight_dummy2_0 - wire csrInstOrInterruptInflight_dummy2_0$D_IN, - csrInstOrInterruptInflight_dummy2_0$EN, - csrInstOrInterruptInflight_dummy2_0$Q_OUT; - - // ports of submodule csrInstOrInterruptInflight_dummy2_1 - wire csrInstOrInterruptInflight_dummy2_1$D_IN, - csrInstOrInterruptInflight_dummy2_1$EN, - csrInstOrInterruptInflight_dummy2_1$Q_OUT; - - // ports of submodule csrf_mcycle_ehr_data_dummy2_0 - wire csrf_mcycle_ehr_data_dummy2_0$D_IN, - csrf_mcycle_ehr_data_dummy2_0$EN, - csrf_mcycle_ehr_data_dummy2_0$Q_OUT; - - // ports of submodule csrf_mcycle_ehr_data_dummy2_1 - wire csrf_mcycle_ehr_data_dummy2_1$D_IN, - csrf_mcycle_ehr_data_dummy2_1$EN, - csrf_mcycle_ehr_data_dummy2_1$Q_OUT; - - // ports of submodule csrf_minstret_ehr_data_dummy2_0 - wire csrf_minstret_ehr_data_dummy2_0$D_IN, - csrf_minstret_ehr_data_dummy2_0$EN, - csrf_minstret_ehr_data_dummy2_0$Q_OUT; - - // ports of submodule csrf_minstret_ehr_data_dummy2_1 - wire csrf_minstret_ehr_data_dummy2_1$D_IN, - csrf_minstret_ehr_data_dummy2_1$EN, - csrf_minstret_ehr_data_dummy2_1$Q_OUT; - // ports of submodule csrf_stats_module_writeQ wire csrf_stats_module_writeQ$CLR, csrf_stats_module_writeQ$DEQ, @@ -2917,11 +2574,83 @@ module mkCore(CLK, epochManager$checkEpoch_0_check, epochManager$checkEpoch_1_check; + // ports of submodule f_csr_reqs + wire [76 : 0] f_csr_reqs$D_IN, f_csr_reqs$D_OUT; + wire f_csr_reqs$CLR, + f_csr_reqs$DEQ, + f_csr_reqs$EMPTY_N, + f_csr_reqs$ENQ, + f_csr_reqs$FULL_N; + + // ports of submodule f_csr_rsps + reg [64 : 0] f_csr_rsps$D_IN; + wire [64 : 0] f_csr_rsps$D_OUT; + wire f_csr_rsps$CLR, + f_csr_rsps$DEQ, + f_csr_rsps$EMPTY_N, + f_csr_rsps$ENQ, + f_csr_rsps$FULL_N; + + // ports of submodule f_fpr_reqs + wire [69 : 0] f_fpr_reqs$D_IN, f_fpr_reqs$D_OUT; + wire f_fpr_reqs$CLR, + f_fpr_reqs$DEQ, + f_fpr_reqs$EMPTY_N, + f_fpr_reqs$ENQ, + f_fpr_reqs$FULL_N; + + // ports of submodule f_fpr_rsps + reg [64 : 0] f_fpr_rsps$D_IN; + wire [64 : 0] f_fpr_rsps$D_OUT; + wire f_fpr_rsps$CLR, + f_fpr_rsps$DEQ, + f_fpr_rsps$EMPTY_N, + f_fpr_rsps$ENQ, + f_fpr_rsps$FULL_N; + + // ports of submodule f_gpr_reqs + wire [69 : 0] f_gpr_reqs$D_IN, f_gpr_reqs$D_OUT; + wire f_gpr_reqs$CLR, + f_gpr_reqs$DEQ, + f_gpr_reqs$EMPTY_N, + f_gpr_reqs$ENQ, + f_gpr_reqs$FULL_N; + + // ports of submodule f_gpr_rsps + reg [64 : 0] f_gpr_rsps$D_IN; + wire [64 : 0] f_gpr_rsps$D_OUT; + wire f_gpr_rsps$CLR, + f_gpr_rsps$DEQ, + f_gpr_rsps$EMPTY_N, + f_gpr_rsps$ENQ, + f_gpr_rsps$FULL_N; + + // ports of submodule f_run_halt_reqs + wire f_run_halt_reqs$CLR, + f_run_halt_reqs$DEQ, + f_run_halt_reqs$D_IN, + f_run_halt_reqs$D_OUT, + f_run_halt_reqs$EMPTY_N, + f_run_halt_reqs$ENQ, + f_run_halt_reqs$FULL_N; + + // ports of submodule f_run_halt_rsps + wire f_run_halt_rsps$CLR, + f_run_halt_rsps$DEQ, + f_run_halt_rsps$D_IN, + f_run_halt_rsps$D_OUT, + f_run_halt_rsps$EMPTY_N, + f_run_halt_rsps$ENQ, + f_run_halt_rsps$FULL_N; + // ports of submodule fetchStage - reg [63 : 0] fetchStage$redirect_pc; - wire [582 : 0] fetchStage$iMemIfc_to_parent_fromP_enq_x; - wire [578 : 0] fetchStage$iMemIfc_to_parent_rsToP_first; - wire [387 : 0] fetchStage$pipelines_0_first, fetchStage$pipelines_1_first; + reg [128 : 0] fetchStage$redirect_pc; + wire [590 : 0] fetchStage$pipelines_0_first, fetchStage$pipelines_1_first; + wire [586 : 0] fetchStage$iMemIfc_to_parent_fromP_enq_x; + wire [582 : 0] fetchStage$iMemIfc_to_parent_rsToP_first; + wire [128 : 0] fetchStage$start_pc, + fetchStage$train_predictors_next_pc, + fetchStage$train_predictors_pc; wire [80 : 0] fetchStage$iTlbIfc_toParent_rsFromP_enq_x; wire [71 : 0] fetchStage$iMemIfc_to_parent_rqToP_first; wire [67 : 0] fetchStage$iMemIfc_cRqStuck_get, @@ -2931,10 +2660,7 @@ module mkCore(CLK, fetchStage$iTlbIfc_to_proc_request_put, fetchStage$mmioIfc_instReq_first_fst, fetchStage$mmioIfc_setHtifAddrs_fromHost, - fetchStage$mmioIfc_setHtifAddrs_toHost, - fetchStage$start_pc, - fetchStage$train_predictors_next_pc, - fetchStage$train_predictors_pc; + fetchStage$mmioIfc_setHtifAddrs_toHost; wire [48 : 0] fetchStage$iTlbIfc_updateVMInfo_vm; wire [26 : 0] fetchStage$iTlbIfc_toParent_rqToP_first; wire [23 : 0] fetchStage$train_predictors_dpTrain; @@ -2974,6 +2700,7 @@ module mkCore(CLK, fetchStage$EN_pipelines_0_deq, fetchStage$EN_pipelines_1_deq, fetchStage$EN_redirect, + fetchStage$EN_setWaitFlush, fetchStage$EN_setWaitRedirect, fetchStage$EN_start, fetchStage$EN_stop, @@ -3000,6 +2727,9 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first, fetchStage$RDY_pipelines_1_deq, fetchStage$RDY_pipelines_1_first, + fetchStage$emptyForFlush, + fetchStage$flush_predictors_done, + fetchStage$iMemIfc_flush_done, fetchStage$iMemIfc_perf_setStatus_doStats, fetchStage$iMemIfc_to_parent_fromP_notFull, fetchStage$iMemIfc_to_parent_rqToP_notEmpty, @@ -3011,6 +2741,7 @@ module mkCore(CLK, fetchStage$perf_setStatus_doStats, fetchStage$pipelines_0_canDeq, fetchStage$pipelines_1_canDeq, + fetchStage$train_predictors_isCompressed, fetchStage$train_predictors_mispred, fetchStage$train_predictors_taken; @@ -3044,219 +2775,6 @@ module mkCore(CLK, l2Tlb$toMem_memReq_notEmpty, l2Tlb$toMem_respLd_notFull; - // ports of submodule mmio_cRqQ_clearReq_dummy2_0 - wire mmio_cRqQ_clearReq_dummy2_0$D_IN, mmio_cRqQ_clearReq_dummy2_0$EN; - - // ports of submodule mmio_cRqQ_clearReq_dummy2_1 - wire mmio_cRqQ_clearReq_dummy2_1$D_IN, - mmio_cRqQ_clearReq_dummy2_1$EN, - mmio_cRqQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule mmio_cRqQ_deqReq_dummy2_0 - wire mmio_cRqQ_deqReq_dummy2_0$D_IN, mmio_cRqQ_deqReq_dummy2_0$EN; - - // ports of submodule mmio_cRqQ_deqReq_dummy2_1 - wire mmio_cRqQ_deqReq_dummy2_1$D_IN, mmio_cRqQ_deqReq_dummy2_1$EN; - - // ports of submodule mmio_cRqQ_deqReq_dummy2_2 - wire mmio_cRqQ_deqReq_dummy2_2$D_IN, - mmio_cRqQ_deqReq_dummy2_2$EN, - mmio_cRqQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule mmio_cRqQ_enqReq_dummy2_0 - wire mmio_cRqQ_enqReq_dummy2_0$D_IN, mmio_cRqQ_enqReq_dummy2_0$EN; - - // ports of submodule mmio_cRqQ_enqReq_dummy2_1 - wire mmio_cRqQ_enqReq_dummy2_1$D_IN, mmio_cRqQ_enqReq_dummy2_1$EN; - - // ports of submodule mmio_cRqQ_enqReq_dummy2_2 - wire mmio_cRqQ_enqReq_dummy2_2$D_IN, - mmio_cRqQ_enqReq_dummy2_2$EN, - mmio_cRqQ_enqReq_dummy2_2$Q_OUT; - - // ports of submodule mmio_cRsQ_clearReq_dummy2_0 - wire mmio_cRsQ_clearReq_dummy2_0$D_IN, mmio_cRsQ_clearReq_dummy2_0$EN; - - // ports of submodule mmio_cRsQ_clearReq_dummy2_1 - wire mmio_cRsQ_clearReq_dummy2_1$D_IN, - mmio_cRsQ_clearReq_dummy2_1$EN, - mmio_cRsQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule mmio_cRsQ_deqReq_dummy2_0 - wire mmio_cRsQ_deqReq_dummy2_0$D_IN, mmio_cRsQ_deqReq_dummy2_0$EN; - - // ports of submodule mmio_cRsQ_deqReq_dummy2_1 - wire mmio_cRsQ_deqReq_dummy2_1$D_IN, mmio_cRsQ_deqReq_dummy2_1$EN; - - // ports of submodule mmio_cRsQ_deqReq_dummy2_2 - wire mmio_cRsQ_deqReq_dummy2_2$D_IN, - mmio_cRsQ_deqReq_dummy2_2$EN, - mmio_cRsQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule mmio_cRsQ_enqReq_dummy2_0 - wire mmio_cRsQ_enqReq_dummy2_0$D_IN, mmio_cRsQ_enqReq_dummy2_0$EN; - - // ports of submodule mmio_cRsQ_enqReq_dummy2_1 - wire mmio_cRsQ_enqReq_dummy2_1$D_IN, mmio_cRsQ_enqReq_dummy2_1$EN; - - // ports of submodule mmio_cRsQ_enqReq_dummy2_2 - wire mmio_cRsQ_enqReq_dummy2_2$D_IN, - mmio_cRsQ_enqReq_dummy2_2$EN, - mmio_cRsQ_enqReq_dummy2_2$Q_OUT; - - // ports of submodule mmio_dataPendQ_clearReq_dummy2_0 - wire mmio_dataPendQ_clearReq_dummy2_0$D_IN, - mmio_dataPendQ_clearReq_dummy2_0$EN; - - // ports of submodule mmio_dataPendQ_clearReq_dummy2_1 - wire mmio_dataPendQ_clearReq_dummy2_1$D_IN, - mmio_dataPendQ_clearReq_dummy2_1$EN, - mmio_dataPendQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule mmio_dataPendQ_deqReq_dummy2_0 - wire mmio_dataPendQ_deqReq_dummy2_0$D_IN, mmio_dataPendQ_deqReq_dummy2_0$EN; - - // ports of submodule mmio_dataPendQ_deqReq_dummy2_1 - wire mmio_dataPendQ_deqReq_dummy2_1$D_IN, mmio_dataPendQ_deqReq_dummy2_1$EN; - - // ports of submodule mmio_dataPendQ_deqReq_dummy2_2 - wire mmio_dataPendQ_deqReq_dummy2_2$D_IN, - mmio_dataPendQ_deqReq_dummy2_2$EN, - mmio_dataPendQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule mmio_dataPendQ_enqReq_dummy2_0 - wire mmio_dataPendQ_enqReq_dummy2_0$D_IN, mmio_dataPendQ_enqReq_dummy2_0$EN; - - // ports of submodule mmio_dataPendQ_enqReq_dummy2_1 - wire mmio_dataPendQ_enqReq_dummy2_1$D_IN, mmio_dataPendQ_enqReq_dummy2_1$EN; - - // ports of submodule mmio_dataPendQ_enqReq_dummy2_2 - wire mmio_dataPendQ_enqReq_dummy2_2$D_IN, - mmio_dataPendQ_enqReq_dummy2_2$EN, - mmio_dataPendQ_enqReq_dummy2_2$Q_OUT; - - // ports of submodule mmio_dataReqQ_clearReq_dummy2_0 - wire mmio_dataReqQ_clearReq_dummy2_0$D_IN, - mmio_dataReqQ_clearReq_dummy2_0$EN; - - // ports of submodule mmio_dataReqQ_clearReq_dummy2_1 - wire mmio_dataReqQ_clearReq_dummy2_1$D_IN, - mmio_dataReqQ_clearReq_dummy2_1$EN, - mmio_dataReqQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule mmio_dataReqQ_deqReq_dummy2_0 - wire mmio_dataReqQ_deqReq_dummy2_0$D_IN, mmio_dataReqQ_deqReq_dummy2_0$EN; - - // ports of submodule mmio_dataReqQ_deqReq_dummy2_1 - wire mmio_dataReqQ_deqReq_dummy2_1$D_IN, mmio_dataReqQ_deqReq_dummy2_1$EN; - - // ports of submodule mmio_dataReqQ_deqReq_dummy2_2 - wire mmio_dataReqQ_deqReq_dummy2_2$D_IN, - mmio_dataReqQ_deqReq_dummy2_2$EN, - mmio_dataReqQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule mmio_dataReqQ_enqReq_dummy2_0 - wire mmio_dataReqQ_enqReq_dummy2_0$D_IN, mmio_dataReqQ_enqReq_dummy2_0$EN; - - // ports of submodule mmio_dataReqQ_enqReq_dummy2_1 - wire mmio_dataReqQ_enqReq_dummy2_1$D_IN, mmio_dataReqQ_enqReq_dummy2_1$EN; - - // ports of submodule mmio_dataReqQ_enqReq_dummy2_2 - wire mmio_dataReqQ_enqReq_dummy2_2$D_IN, - mmio_dataReqQ_enqReq_dummy2_2$EN, - mmio_dataReqQ_enqReq_dummy2_2$Q_OUT; - - // ports of submodule mmio_dataRespQ_clearReq_dummy2_0 - wire mmio_dataRespQ_clearReq_dummy2_0$D_IN, - mmio_dataRespQ_clearReq_dummy2_0$EN; - - // ports of submodule mmio_dataRespQ_clearReq_dummy2_1 - wire mmio_dataRespQ_clearReq_dummy2_1$D_IN, - mmio_dataRespQ_clearReq_dummy2_1$EN, - mmio_dataRespQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule mmio_dataRespQ_deqReq_dummy2_0 - wire mmio_dataRespQ_deqReq_dummy2_0$D_IN, mmio_dataRespQ_deqReq_dummy2_0$EN; - - // ports of submodule mmio_dataRespQ_deqReq_dummy2_1 - wire mmio_dataRespQ_deqReq_dummy2_1$D_IN, mmio_dataRespQ_deqReq_dummy2_1$EN; - - // ports of submodule mmio_dataRespQ_deqReq_dummy2_2 - wire mmio_dataRespQ_deqReq_dummy2_2$D_IN, - mmio_dataRespQ_deqReq_dummy2_2$EN, - mmio_dataRespQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule mmio_dataRespQ_enqReq_dummy2_0 - wire mmio_dataRespQ_enqReq_dummy2_0$D_IN, mmio_dataRespQ_enqReq_dummy2_0$EN; - - // ports of submodule mmio_dataRespQ_enqReq_dummy2_1 - wire mmio_dataRespQ_enqReq_dummy2_1$D_IN, mmio_dataRespQ_enqReq_dummy2_1$EN; - - // ports of submodule mmio_dataRespQ_enqReq_dummy2_2 - wire mmio_dataRespQ_enqReq_dummy2_2$D_IN, - mmio_dataRespQ_enqReq_dummy2_2$EN, - mmio_dataRespQ_enqReq_dummy2_2$Q_OUT; - - // ports of submodule mmio_pRqQ_clearReq_dummy2_0 - wire mmio_pRqQ_clearReq_dummy2_0$D_IN, mmio_pRqQ_clearReq_dummy2_0$EN; - - // ports of submodule mmio_pRqQ_clearReq_dummy2_1 - wire mmio_pRqQ_clearReq_dummy2_1$D_IN, - mmio_pRqQ_clearReq_dummy2_1$EN, - mmio_pRqQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule mmio_pRqQ_deqReq_dummy2_0 - wire mmio_pRqQ_deqReq_dummy2_0$D_IN, mmio_pRqQ_deqReq_dummy2_0$EN; - - // ports of submodule mmio_pRqQ_deqReq_dummy2_1 - wire mmio_pRqQ_deqReq_dummy2_1$D_IN, mmio_pRqQ_deqReq_dummy2_1$EN; - - // ports of submodule mmio_pRqQ_deqReq_dummy2_2 - wire mmio_pRqQ_deqReq_dummy2_2$D_IN, - mmio_pRqQ_deqReq_dummy2_2$EN, - mmio_pRqQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule mmio_pRqQ_enqReq_dummy2_0 - wire mmio_pRqQ_enqReq_dummy2_0$D_IN, mmio_pRqQ_enqReq_dummy2_0$EN; - - // ports of submodule mmio_pRqQ_enqReq_dummy2_1 - wire mmio_pRqQ_enqReq_dummy2_1$D_IN, mmio_pRqQ_enqReq_dummy2_1$EN; - - // ports of submodule mmio_pRqQ_enqReq_dummy2_2 - wire mmio_pRqQ_enqReq_dummy2_2$D_IN, - mmio_pRqQ_enqReq_dummy2_2$EN, - mmio_pRqQ_enqReq_dummy2_2$Q_OUT; - - // ports of submodule mmio_pRsQ_clearReq_dummy2_0 - wire mmio_pRsQ_clearReq_dummy2_0$D_IN, mmio_pRsQ_clearReq_dummy2_0$EN; - - // ports of submodule mmio_pRsQ_clearReq_dummy2_1 - wire mmio_pRsQ_clearReq_dummy2_1$D_IN, - mmio_pRsQ_clearReq_dummy2_1$EN, - mmio_pRsQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule mmio_pRsQ_deqReq_dummy2_0 - wire mmio_pRsQ_deqReq_dummy2_0$D_IN, mmio_pRsQ_deqReq_dummy2_0$EN; - - // ports of submodule mmio_pRsQ_deqReq_dummy2_1 - wire mmio_pRsQ_deqReq_dummy2_1$D_IN, mmio_pRsQ_deqReq_dummy2_1$EN; - - // ports of submodule mmio_pRsQ_deqReq_dummy2_2 - wire mmio_pRsQ_deqReq_dummy2_2$D_IN, - mmio_pRsQ_deqReq_dummy2_2$EN, - mmio_pRsQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule mmio_pRsQ_enqReq_dummy2_0 - wire mmio_pRsQ_enqReq_dummy2_0$D_IN, mmio_pRsQ_enqReq_dummy2_0$EN; - - // ports of submodule mmio_pRsQ_enqReq_dummy2_1 - wire mmio_pRsQ_enqReq_dummy2_1$D_IN, mmio_pRsQ_enqReq_dummy2_1$EN; - - // ports of submodule mmio_pRsQ_enqReq_dummy2_2 - wire mmio_pRsQ_enqReq_dummy2_2$D_IN, - mmio_pRsQ_enqReq_dummy2_2$EN, - mmio_pRsQ_enqReq_dummy2_2$Q_OUT; - // ports of submodule perfReqQ wire [8 : 0] perfReqQ$D_IN, perfReqQ$D_OUT; wire perfReqQ$CLR, @@ -3266,11 +2784,11 @@ module mkCore(CLK, perfReqQ$FULL_N; // ports of submodule regRenamingTable + reg [26 : 0] regRenamingTable$rename_0_getRename_r; reg [3 : 0] regRenamingTable$specUpdate_incorrectSpeculation_kill_tag; wire [32 : 0] regRenamingTable$rename_0_getRename, regRenamingTable$rename_1_getRename; wire [26 : 0] regRenamingTable$rename_0_claimRename_r, - regRenamingTable$rename_0_getRename_r, regRenamingTable$rename_1_claimRename_r, regRenamingTable$rename_1_getRename_r; wire [11 : 0] regRenamingTable$rename_0_claimRename_sb, @@ -3293,19 +2811,21 @@ module mkCore(CLK, regRenamingTable$specUpdate_incorrectSpeculation_kill_all; // ports of submodule rf - reg [63 : 0] rf$write_2_wr_data, rf$write_3_wr_data; + reg [152 : 0] rf$write_2_wr_data, rf$write_3_wr_data; reg [6 : 0] rf$write_2_wr_rindx, rf$write_3_wr_rindx; - wire [63 : 0] rf$read_0_rd1, - rf$read_0_rd2, - rf$read_1_rd1, - rf$read_1_rd2, - rf$read_2_rd1, - rf$read_2_rd2, - rf$read_2_rd3, - rf$read_3_rd1, - rf$read_3_rd2, - rf$write_0_wr_data, - rf$write_1_wr_data; + wire [152 : 0] rf$read_0_rd1, + rf$read_0_rd2, + rf$read_1_rd1, + rf$read_1_rd2, + rf$read_2_rd1, + rf$read_2_rd2, + rf$read_2_rd3, + rf$read_3_rd1, + rf$read_3_rd2, + rf$read_4_rd1, + rf$write_0_wr_data, + rf$write_1_wr_data, + rf$write_4_wr_data; wire [6 : 0] rf$read_0_rd1_rindx, rf$read_0_rd2_rindx, rf$read_0_rd3_rindx, @@ -3318,29 +2838,43 @@ module mkCore(CLK, rf$read_3_rd1_rindx, rf$read_3_rd2_rindx, rf$read_3_rd3_rindx, + rf$read_4_rd1_rindx, + rf$read_4_rd2_rindx, + rf$read_4_rd3_rindx, rf$write_0_wr_rindx, - rf$write_1_wr_rindx; - wire rf$EN_write_0_wr, rf$EN_write_1_wr, rf$EN_write_2_wr, rf$EN_write_3_wr; + rf$write_1_wr_rindx, + rf$write_4_wr_rindx; + wire rf$EN_write_0_wr, + rf$EN_write_1_wr, + rf$EN_write_2_wr, + rf$EN_write_3_wr, + rf$EN_write_4_wr; // ports of submodule rob - reg [282 : 0] rob$enqPort_0_enq_x; + reg [630 : 0] rob$enqPort_0_enq_x; + reg [63 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data; + reg [13 : 0] rob$setExecuted_deqLSQ_cause; reg [11 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_x, rob$specUpdate_incorrectSpeculation_inst_tag; - reg [4 : 0] rob$setExecuted_deqLSQ_cause, - rob$setExecuted_doFinishFpuMulDiv_0_set_fflags; + reg [4 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_fflags; reg [3 : 0] rob$specUpdate_incorrectSpeculation_spec_tag; - wire [282 : 0] rob$deqPort_0_deq_data, + wire [630 : 0] rob$deqPort_0_deq_data, rob$deqPort_1_deq_data, rob$enqPort_1_enq_x; - wire [129 : 0] rob$setExecuted_doFinishAlu_0_set_cf, + wire [328 : 0] rob$setExecuted_doFinishAlu_0_set_cf, rob$setExecuted_doFinishAlu_1_set_cf; + wire [163 : 0] rob$setExecuted_doFinishAlu_0_set_scrData, + rob$setExecuted_doFinishAlu_1_set_scrData; + wire [162 : 0] rob$setExecuted_doFinishAlu_0_set_dst_data, + rob$setExecuted_doFinishAlu_1_set_dst_data, + rob$setExecuted_doFinishMem_vaddr; + wire [128 : 0] rob$getOrigPC_0_get, + rob$getOrigPC_1_get, + rob$getOrigPredPC_0_get, + rob$getOrigPredPC_1_get; wire [64 : 0] rob$setExecuted_doFinishAlu_0_set_csrData, rob$setExecuted_doFinishAlu_1_set_csrData; - wire [63 : 0] rob$getOrigPC_0_get, - rob$getOrigPC_1_get, - rob$getOrigPredPC_0_get, - rob$getOrigPredPC_1_get, - rob$setExecuted_doFinishMem_vaddr; + wire [63 : 0] rob$setExecuted_doFinishMem_store_data; wire [31 : 0] rob$getOrig_Inst_0_get, rob$getOrig_Inst_1_get; wire [11 : 0] rob$deqPort_0_getDeqInstTag, rob$enqPort_0_getEnqInstTag, @@ -3353,12 +2887,15 @@ module mkCore(CLK, rob$getOrig_Inst_0_get_x, rob$getOrig_Inst_1_get_x, rob$setExecuted_deqLSQ_x, + rob$setExecuted_doFinishAlu_0_set_cause, rob$setExecuted_doFinishAlu_0_set_x, + rob$setExecuted_doFinishAlu_1_set_cause, rob$setExecuted_doFinishAlu_1_set_x, rob$setExecuted_doFinishMem_x, rob$setLSQAtCommitNotified_x, rob$specUpdate_correctSpeculation_mask; - wire [5 : 0] rob$getEnqTime; + wire [7 : 0] rob$setExecuted_doFinishMem_store_data_BE; + wire [5 : 0] rob$getEnqTime, rob$setExecuted_doFinishFpuMulDiv_0_set_cause; wire [2 : 0] rob$setExecuted_deqLSQ_ld_killed; wire rob$EN_deqPort_0_deq, rob$EN_deqPort_1_deq, @@ -3416,9 +2953,12 @@ module mkCore(CLK, sbCons$lazyLookup_0_get_r, sbCons$lazyLookup_1_get_r, sbCons$lazyLookup_2_get_r, - sbCons$lazyLookup_3_get_r; + sbCons$lazyLookup_3_get_r, + sbCons$lazyLookup_4_get_r; wire [8 : 0] sbCons$setBusy_0_set_dst, sbCons$setBusy_1_set_dst; - wire [6 : 0] sbCons$setReady_0_put, sbCons$setReady_1_put; + wire [6 : 0] sbCons$setReady_0_put, + sbCons$setReady_1_put, + sbCons$setReady_4_put; wire [3 : 0] sbCons$lazyLookup_0_get, sbCons$lazyLookup_1_get, sbCons$lazyLookup_2_get, @@ -3428,7 +2968,8 @@ module mkCore(CLK, sbCons$EN_setReady_0_put, sbCons$EN_setReady_1_put, sbCons$EN_setReady_2_put, - sbCons$EN_setReady_3_put; + sbCons$EN_setReady_3_put, + sbCons$EN_setReady_4_put; // ports of submodule specTagManager reg [3 : 0] specTagManager$specUpdate_incorrectSpeculation_kill_tag; @@ -3570,8 +3111,14 @@ module mkCore(CLK, CAN_FIRE_RL_csrf_incCycle, CAN_FIRE_RL_csrf_mcycle_ehr_data_canon, CAN_FIRE_RL_csrf_mcycle_ehr_setRead, + CAN_FIRE_RL_csrf_mepcc_reg_data_canon, + CAN_FIRE_RL_csrf_mepcc_reg_setRead, CAN_FIRE_RL_csrf_minstret_ehr_data_canon, CAN_FIRE_RL_csrf_minstret_ehr_setRead, + CAN_FIRE_RL_csrf_sepcc_reg_data_canon, + CAN_FIRE_RL_csrf_sepcc_reg_setRead, + CAN_FIRE_RL_flushBrPred, + CAN_FIRE_RL_flushCaches, CAN_FIRE_RL_mkConnectionGetPut, CAN_FIRE_RL_mkConnectionGetPut_1, CAN_FIRE_RL_mmio_cRqQ_canonicalize, @@ -3613,6 +3160,20 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming_SystemInst, CAN_FIRE_RL_renameStage_doRenaming_Trap, CAN_FIRE_RL_renameStage_doRenaming_wrongPath, + CAN_FIRE_RL_rl_debug_csr_access_busy, + CAN_FIRE_RL_rl_debug_csr_read, + CAN_FIRE_RL_rl_debug_csr_write, + CAN_FIRE_RL_rl_debug_fpr_access_busy, + CAN_FIRE_RL_rl_debug_fpr_read, + CAN_FIRE_RL_rl_debug_fpr_write, + CAN_FIRE_RL_rl_debug_gpr_access_busy, + CAN_FIRE_RL_rl_debug_gpr_read, + CAN_FIRE_RL_rl_debug_gpr_write, + CAN_FIRE_RL_rl_debug_halt_req, + CAN_FIRE_RL_rl_debug_halt_req_already_halted, + CAN_FIRE_RL_rl_debug_halted, + CAN_FIRE_RL_rl_debug_resume, + CAN_FIRE_RL_rl_debug_run_redundant, CAN_FIRE_RL_rl_outOfReset, CAN_FIRE_RL_sendDTlbReq, CAN_FIRE_RL_sendFlushDone, @@ -3620,6 +3181,8 @@ module mkCore(CLK, CAN_FIRE_RL_sendRobEnqTime, CAN_FIRE_RL_sendRsToDTlb, CAN_FIRE_RL_sendRsToITlb, + CAN_FIRE_RL_setDoFlushBrPred, + CAN_FIRE_RL_setDoFlushCaches, CAN_FIRE_coreIndInv_perfResp, CAN_FIRE_coreIndInv_terminate, CAN_FIRE_coreReq_perfReq, @@ -3636,6 +3199,14 @@ module mkCore(CLK, CAN_FIRE_deadlock_iCachePRqStuck_get, CAN_FIRE_deadlock_renameCorrectPathStuck_get, CAN_FIRE_deadlock_renameInstStuck_get, + CAN_FIRE_hart0_csr_mem_server_request_put, + CAN_FIRE_hart0_csr_mem_server_response_get, + CAN_FIRE_hart0_fpr_mem_server_request_put, + CAN_FIRE_hart0_fpr_mem_server_response_get, + CAN_FIRE_hart0_gpr_mem_server_request_put, + CAN_FIRE_hart0_gpr_mem_server_response_get, + CAN_FIRE_hart0_run_halt_server_request_put, + CAN_FIRE_hart0_run_halt_server_response_get, CAN_FIRE_iCacheToParent_fromP_enq, CAN_FIRE_iCacheToParent_rqToP_deq, CAN_FIRE_iCacheToParent_rsToP_deq, @@ -3647,7 +3218,6 @@ module mkCore(CLK, CAN_FIRE_recvDoStats, CAN_FIRE_renameDebug_renameErr_get, CAN_FIRE_sendDoStats, - CAN_FIRE_setDEIP, CAN_FIRE_setMEIP, CAN_FIRE_setSEIP, CAN_FIRE_tlbToMem_memReq_deq, @@ -3778,8 +3348,14 @@ module mkCore(CLK, WILL_FIRE_RL_csrf_incCycle, WILL_FIRE_RL_csrf_mcycle_ehr_data_canon, WILL_FIRE_RL_csrf_mcycle_ehr_setRead, + WILL_FIRE_RL_csrf_mepcc_reg_data_canon, + WILL_FIRE_RL_csrf_mepcc_reg_setRead, WILL_FIRE_RL_csrf_minstret_ehr_data_canon, WILL_FIRE_RL_csrf_minstret_ehr_setRead, + WILL_FIRE_RL_csrf_sepcc_reg_data_canon, + WILL_FIRE_RL_csrf_sepcc_reg_setRead, + WILL_FIRE_RL_flushBrPred, + WILL_FIRE_RL_flushCaches, WILL_FIRE_RL_mkConnectionGetPut, WILL_FIRE_RL_mkConnectionGetPut_1, WILL_FIRE_RL_mmio_cRqQ_canonicalize, @@ -3821,6 +3397,20 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_SystemInst, WILL_FIRE_RL_renameStage_doRenaming_Trap, WILL_FIRE_RL_renameStage_doRenaming_wrongPath, + WILL_FIRE_RL_rl_debug_csr_access_busy, + WILL_FIRE_RL_rl_debug_csr_read, + WILL_FIRE_RL_rl_debug_csr_write, + WILL_FIRE_RL_rl_debug_fpr_access_busy, + WILL_FIRE_RL_rl_debug_fpr_read, + WILL_FIRE_RL_rl_debug_fpr_write, + WILL_FIRE_RL_rl_debug_gpr_access_busy, + WILL_FIRE_RL_rl_debug_gpr_read, + WILL_FIRE_RL_rl_debug_gpr_write, + WILL_FIRE_RL_rl_debug_halt_req, + WILL_FIRE_RL_rl_debug_halt_req_already_halted, + WILL_FIRE_RL_rl_debug_halted, + WILL_FIRE_RL_rl_debug_resume, + WILL_FIRE_RL_rl_debug_run_redundant, WILL_FIRE_RL_rl_outOfReset, WILL_FIRE_RL_sendDTlbReq, WILL_FIRE_RL_sendFlushDone, @@ -3828,6 +3418,8 @@ module mkCore(CLK, WILL_FIRE_RL_sendRobEnqTime, WILL_FIRE_RL_sendRsToDTlb, WILL_FIRE_RL_sendRsToITlb, + WILL_FIRE_RL_setDoFlushBrPred, + WILL_FIRE_RL_setDoFlushCaches, WILL_FIRE_coreIndInv_perfResp, WILL_FIRE_coreIndInv_terminate, WILL_FIRE_coreReq_perfReq, @@ -3844,6 +3436,14 @@ module mkCore(CLK, WILL_FIRE_deadlock_iCachePRqStuck_get, WILL_FIRE_deadlock_renameCorrectPathStuck_get, WILL_FIRE_deadlock_renameInstStuck_get, + WILL_FIRE_hart0_csr_mem_server_request_put, + WILL_FIRE_hart0_csr_mem_server_response_get, + WILL_FIRE_hart0_fpr_mem_server_request_put, + WILL_FIRE_hart0_fpr_mem_server_response_get, + WILL_FIRE_hart0_gpr_mem_server_request_put, + WILL_FIRE_hart0_gpr_mem_server_response_get, + WILL_FIRE_hart0_run_halt_server_request_put, + WILL_FIRE_hart0_run_halt_server_response_get, WILL_FIRE_iCacheToParent_fromP_enq, WILL_FIRE_iCacheToParent_rqToP_deq, WILL_FIRE_iCacheToParent_rsToP_deq, @@ -3855,79 +3455,93 @@ module mkCore(CLK, WILL_FIRE_recvDoStats, WILL_FIRE_renameDebug_renameErr_get, WILL_FIRE_sendDoStats, - WILL_FIRE_setDEIP, WILL_FIRE_setMEIP, WILL_FIRE_setSEIP, WILL_FIRE_tlbToMem_memReq_deq, WILL_FIRE_tlbToMem_respLd_enq; // inputs to muxes for submodule ports - reg [63 : 0] MUX_coreFix_memExe_lsq$respLd_2__VAL_1, - MUX_coreFix_memExe_lsq$respLd_2__VAL_2, - MUX_fetchStage$redirect_1__VAL_5; - reg [4 : 0] MUX_coreFix_memExe_lsq$respLd_1__VAL_1, - MUX_coreFix_memExe_lsq$respLd_1__VAL_2; - reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_1; - wire [583 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1, + reg [128 : 0] MUX_fetchStage$redirect_1__VAL_5; + reg [63 : 0] MUX_csrf_mtval_csr$write_1__VAL_2; + reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_2, MUX_csrf_fs_reg$write_1__VAL_3; + wire [630 : 0] MUX_rob$enqPort_0_enq_1__VAL_1, + MUX_rob$enqPort_0_enq_1__VAL_2, + MUX_rob$enqPort_0_enq_1__VAL_3; + wire [587 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4; - wire [579 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1, + wire [583 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2; - wire [569 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1, + wire [574 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4; - wire [282 : 0] MUX_rob$enqPort_0_enq_1__VAL_1, - MUX_rob$enqPort_0_enq_1__VAL_2, - MUX_rob$enqPort_0_enq_1__VAL_3; - wire [161 : 0] MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1, - MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2; - wire [160 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1, - MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2; - wire [158 : 0] MUX_coreFix_trainBPQ_0$enq_1__VAL_1, + wire [289 : 0] MUX_coreFix_trainBPQ_0$enq_1__VAL_1, MUX_coreFix_trainBPQ_0$enq_1__VAL_2, MUX_coreFix_trainBPQ_1$enq_1__VAL_1, MUX_coreFix_trainBPQ_1$enq_1__VAL_2; - wire [152 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1, + wire [238 : 0] MUX_commitStage_commitTrap$write_1__VAL_2; + wire [234 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1, + MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2; + wire [233 : 0] MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1, + MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2; + wire [226 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2, MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3, MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1, MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2; - wire [142 : 0] MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1, + wire [215 : 0] MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1, MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2, MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1, MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2; - wire [133 : 0] MUX_commitStage_commitTrap$write_1__VAL_2; - wire [69 : 0] MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1, - MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2, - MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1; - wire [67 : 0] MUX_coreFix_memExe_lsq$issueLd_4__VAL_1; - wire [64 : 0] MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1, - MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2, - MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3; - wire [63 : 0] MUX_commitStage_rg_instret$write_1__VAL_1, - MUX_commitStage_rg_instret$write_1__VAL_2, - MUX_csrf_mepc_csr$write_1__VAL_2, + wire [152 : 0] MUX_rf$write_2_wr_2__VAL_1, + MUX_rf$write_2_wr_2__VAL_2, + MUX_rf$write_2_wr_2__VAL_3, + MUX_rf$write_2_wr_2__VAL_4, + MUX_rf$write_2_wr_2__VAL_5, + MUX_rf$write_2_wr_2__VAL_6, + MUX_rf$write_3_wr_2__VAL_1, + MUX_rf$write_3_wr_2__VAL_2, + MUX_rf$write_3_wr_2__VAL_3, + MUX_rf$write_3_wr_2__VAL_4, + MUX_rf$write_3_wr_2__VAL_5, + MUX_rf$write_4_wr_2__VAL_1, + MUX_rf$write_4_wr_2__VAL_2; + wire [134 : 0] MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1, + MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2, + MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1; + wire [132 : 0] MUX_coreFix_memExe_lsq$issueLd_4__VAL_1; + wire [129 : 0] MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1, + MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3; + wire [128 : 0] MUX_coreFix_memExe_lsq$respLd_2__VAL_1, + MUX_coreFix_memExe_lsq$respLd_2__VAL_2, + MUX_fetchStage$redirect_1__VAL_1, + MUX_fetchStage$redirect_1__VAL_6; + wire [64 : 0] MUX_f_csr_rsps$enq_1__VAL_3, MUX_f_fpr_rsps$enq_1__VAL_3; + wire [63 : 0] MUX_commitStage_rg_serial_num$write_1__VAL_1, + MUX_commitStage_rg_serial_num$write_1__VAL_3, + MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2, MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1, MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2, MUX_csrf_mtval_csr$write_1__VAL_1, - MUX_csrf_mtval_csr$write_1__VAL_2, - MUX_csrf_sepc_csr$write_1__VAL_2, - MUX_fetchStage$redirect_1__VAL_4, - MUX_rf$write_2_wr_2__VAL_1, - MUX_rf$write_2_wr_2__VAL_3, - MUX_rf$write_2_wr_2__VAL_4, - MUX_rf$write_2_wr_2__VAL_5, - MUX_rf$write_2_wr_2__VAL_6, - MUX_rf$write_3_wr_2__VAL_3, - MUX_rf$write_3_wr_2__VAL_4; - wire [58 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1, + MUX_csrf_rg_dcsr$write_1__VAL_2, + MUX_csrf_rg_tselect$write_1__VAL_2, + MUX_csrf_stval_csr$write_1__VAL_1; + wire [58 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1, + MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2, + MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2; - wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1, - MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2; + wire [48 : 0] MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1, + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1; wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2; + wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2, + MUX_regRenamingTable$rename_0_getRename_1__VAL_3; + wire [13 : 0] MUX_rob$setExecuted_deqLSQ_2__VAL_2, + MUX_rob$setExecuted_deqLSQ_2__VAL_6; + wire [10 : 0] MUX_csrf_mccsr_reg$write_1__VAL_1, + MUX_csrf_mccsr_reg$write_1__VAL_2; wire [7 : 0] MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1, MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2, MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3, @@ -3938,20 +3552,22 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1; - wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_2, - MUX_rob$setExecuted_deqLSQ_2__VAL_2, - MUX_rob$setExecuted_deqLSQ_2__VAL_6, - MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2, - MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3, - MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4; + wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_1, + MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2, + MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3, + MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4; wire [3 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2; - wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1; + wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1, + MUX_csrf_frm_reg$write_1__VAL_1, + MUX_csrf_frm_reg$write_1__VAL_2; wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1, MUX_csrf_prv_reg$write_1__VAL_1, MUX_csrf_prv_reg$write_1__VAL_2; - wire MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1, + wire MUX_commitStage_rg_run_state$write_1__SEL_1, + MUX_commitStage_rg_serial_num$write_1__SEL_1, + MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1, MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3, MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1, MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1, @@ -3973,54 +3589,92 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2, MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1, - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1, - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2, - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3, + MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_1, + MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_2, + MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_3, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2, + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1, MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1, - MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2, MUX_coreFix_memExe_lsq$getHit_1__SEL_1, - MUX_coreFix_memExe_lsq$getHit_1__SEL_2, MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1, MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1, - MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1, + MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__SEL_1, MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1, MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2, MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1, MUX_coreFix_trainBPQ_0$enq_1__SEL_1, MUX_coreFix_trainBPQ_1$enq_1__SEL_1, - MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1, - MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2, - MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2, - MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1, - MUX_csrf_debug_int_pend$write_1__SEL_1, + MUX_csrInstOrInterruptInflight_lat_1$wset_1__SEL_2, + MUX_csrf_external_int_en_vec_1$write_1__SEL_1, + MUX_csrf_external_int_en_vec_3$write_1__SEL_1, MUX_csrf_external_int_pend_vec_1$write_1__SEL_1, + MUX_csrf_external_int_pend_vec_1$write_1__SEL_2, MUX_csrf_fflags_reg$write_1__SEL_1, - MUX_csrf_fs_reg$write_1__SEL_1, + MUX_csrf_fflags_reg$write_1__SEL_2, + MUX_csrf_fflags_reg$write_1__SEL_3, + MUX_csrf_frm_reg$write_1__SEL_1, + MUX_csrf_fs_reg$write_1__SEL_2, + MUX_csrf_fs_reg$write_1__SEL_3, + MUX_csrf_ie_vec_0$write_1__SEL_1, + MUX_csrf_ie_vec_0$write_1__SEL_2, MUX_csrf_ie_vec_1$write_1__SEL_1, MUX_csrf_ie_vec_1$write_1__SEL_2, MUX_csrf_ie_vec_1$write_1__VAL_1, MUX_csrf_ie_vec_3$write_1__SEL_1, MUX_csrf_ie_vec_3$write_1__SEL_2, + MUX_csrf_ie_vec_3$write_1__SEL_3, MUX_csrf_ie_vec_3$write_1__VAL_1, + MUX_csrf_mcause_code_reg$write_1__SEL_1, + MUX_csrf_mcause_code_reg$write_1__SEL_3, + MUX_csrf_mccsr_reg$write_1__SEL_1, + MUX_csrf_mcounteren_cy_reg$write_1__SEL_1, + MUX_csrf_mcycle_ehr_data_lat_0$wset_1__SEL_1, + MUX_csrf_medeleg_13_11_reg$write_1__SEL_1, + MUX_csrf_mideleg_11_reg$write_1__SEL_1, + MUX_csrf_minstret_ehr_data_lat_0$wset_1__SEL_1, MUX_csrf_mpp_reg$write_1__SEL_1, + MUX_csrf_mscratch_csr$write_1__SEL_1, + MUX_csrf_mtval_csr$write_1__SEL_1, + MUX_csrf_mtval_csr$write_1__SEL_3, + MUX_csrf_ppn_reg$write_1__SEL_1, MUX_csrf_prev_ie_vec_1$write_1__SEL_1, MUX_csrf_prev_ie_vec_1$write_1__VAL_1, MUX_csrf_prev_ie_vec_3$write_1__SEL_1, MUX_csrf_prev_ie_vec_3$write_1__VAL_1, MUX_csrf_prv_reg$write_1__SEL_1, - MUX_csrf_software_int_pend_vec_3$write_1__VAL_2, + MUX_csrf_prv_reg$write_1__SEL_3, + MUX_csrf_rg_dcsr$write_1__SEL_1, + MUX_csrf_rg_dscratch0$write_1__SEL_1, + MUX_csrf_rg_dscratch1$write_1__SEL_1, + MUX_csrf_rg_tdata1_data$write_1__SEL_1, + MUX_csrf_rg_tdata2$write_1__SEL_1, + MUX_csrf_rg_tdata3$write_1__SEL_1, + MUX_csrf_rg_tselect$write_1__SEL_1, + MUX_csrf_scause_code_reg$write_1__SEL_1, + MUX_csrf_scause_code_reg$write_1__SEL_3, + MUX_csrf_scounteren_cy_reg$write_1__SEL_1, MUX_csrf_spp_reg$write_1__SEL_1, MUX_csrf_spp_reg$write_1__VAL_1, + MUX_csrf_sscratch_csr$write_1__SEL_1, + MUX_csrf_stats_module_writeQ$enq_1__SEL_1, + MUX_csrf_stval_csr$write_1__SEL_1, + MUX_csrf_stval_csr$write_1__SEL_3, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, - MUX_flush_reservation$write_1__SEL_1, + MUX_f_run_halt_rsps$enq_1__SEL_1, + MUX_flush_reservation$write_1__SEL_2, MUX_flush_tlbs$write_1__SEL_1, + MUX_regRenamingTable$rename_0_getRename_1__SEL_1, + MUX_regRenamingTable$rename_0_getRename_1__SEL_2, + MUX_regRenamingTable$rename_0_getRename_1__SEL_3, + MUX_renameStage_rg_m_halt_req$write_1__PSEL_1, + MUX_renameStage_rg_m_halt_req$write_1__SEL_1, + MUX_renameStage_rg_m_halt_req$write_1__SEL_2, MUX_rf$write_3_wr_1__PSEL_5, MUX_rf$write_3_wr_1__SEL_1, MUX_rf$write_3_wr_1__SEL_2, @@ -4028,1851 +3682,2850 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__SEL_4, MUX_rf$write_3_wr_1__SEL_5, MUX_rf$write_3_wr_2__SEL_5, + MUX_rg_core_run_state$write_1__SEL_4, MUX_rob$setExecuted_deqLSQ_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_1, MUX_sbCons$setReady_3_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_3, - MUX_update_vm_info$write_1__SEL_1; + MUX_started$write_1__SEL_1; + + // declarations used by system tasks + // synopsys translate_off + reg [63 : 0] v__h213381; + reg [63 : 0] v__h215650; + reg [63 : 0] v__h271867; + reg [63 : 0] v__h347385; + reg [63 : 0] v__h423711; + // synopsys translate_on // remaining internal signals - reg [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496; - reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q280, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q14, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9929, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871, - addr__h287287, - curData__h190137, - rVal1__h605871, - rVal1__h629404, - trap_val__h693218, - x__h194347; - reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9, - CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211, - CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212, - CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209, - CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210, - CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197, - CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198, - CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199, - CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200, - CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201, - CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202, - CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213, - CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214, - CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215, - CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216, - CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217, - CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218, - CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207, - CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861; - reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78, - CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79, - CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80, - CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81, - CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111, - CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112, - CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41, - CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42, - CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109, - CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110, - CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39, - CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40, - CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113, - CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114, - CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43, - CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44, - CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115, - CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116, - CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45, - CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46, - CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76, - CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77, - CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74, - CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75, - _theResult___fst_sfd__h343283, - _theResult___fst_sfd__h352006, - _theResult___fst_sfd__h360588, - _theResult___fst_sfd__h369772, - _theResult___fst_sfd__h378408, - _theResult___fst_sfd__h388975, - _theResult___fst_sfd__h397696, - _theResult___fst_sfd__h406278, - _theResult___fst_sfd__h415462, - _theResult___fst_sfd__h424098, - _theResult___fst_sfd__h434663, - _theResult___fst_sfd__h443384, - _theResult___fst_sfd__h451966, - _theResult___fst_sfd__h461150, - _theResult___fst_sfd__h469786; - reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q276, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273, - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283, - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279, - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361; - reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359, - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407; - reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274, - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228, - IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805; - reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8, - CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203, - CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204, - CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205, - CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206, - CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175, - CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176, - CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177, - CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178, - CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179, - CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180, - CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152, - CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153, - CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183, - CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184, - CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181, - CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182, - CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135, - CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790; - reg [7 : 0] CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67, - CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68, - CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72, - CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73, - CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96, - CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97, - CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26, - CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27, - CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94, - CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95, - CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24, - CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25, - CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102, - CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103, - CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32, - CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33, - CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107, - CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108, - CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37, - CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38, - CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61, - CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62, - CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59, - CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60, - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373, - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420, - _theResult___fst_exp__h343282, - _theResult___fst_exp__h352005, - _theResult___fst_exp__h360587, - _theResult___fst_exp__h369771, - _theResult___fst_exp__h378407, - _theResult___fst_exp__h388974, - _theResult___fst_exp__h397695, - _theResult___fst_exp__h406277, - _theResult___fst_exp__h415461, - _theResult___fst_exp__h424097, - _theResult___fst_exp__h434662, - _theResult___fst_exp__h443383, - _theResult___fst_exp__h451965, - _theResult___fst_exp__h461149, - _theResult___fst_exp__h469785; - reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q265, - CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q262, - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351; - reg [4 : 0] IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13865, - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13994; - reg [3 : 0] CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633__ETC__q227, - CASE_checkForException_2839_BITS_3_TO_0_0_chec_ETC__q226, - CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12, - CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q263, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q259, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260, - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13868, - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949, - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13995, - i__h692202, - i__h692362; - reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q275, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q272, - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q282, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242, - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q278, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254, - CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695, - x__h283066, - x__h288836; - reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q284, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248; - reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157, + reg [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5470; + reg [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4873; + reg [65 : 0] thin_address__h857109, thin_address__h896602; + reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q363, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q364, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q290, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q291, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q292, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q303, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q304, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q17, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q368, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q369, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q316, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q296, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q297, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q298, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q307, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308, + CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_coreF_ETC__q32, + CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_mmio__ETC__q34, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14077, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7038, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113, + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230, + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234, + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147, + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151, + addr__h505543, + addr__h843839, + addr__h886084, + data_out__h1014318, + trap_val__h993994, + x__h264659; + reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31, + CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232, + CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233, + CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234, + CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235, + CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236, + CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237, + CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226, + CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227, + CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q230, + CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q231, + CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q228, + CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q229, + CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216, + CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217, + CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218, + CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219, + CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220, + CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777; + reg [33 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19191, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17087; + reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872, + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040, + x__h264814; + reg [29 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q346, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_816_ETC__q285, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q340, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q357, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_816_ETC__q280, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q351, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q366, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q362, + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20171, + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21119; + reg [22 : 0] CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64, + CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65, + CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95, + CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96, + CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93, + CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94, + CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97, + CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98, + CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100, + CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99, + CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130, + CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131, + CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60, + CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61, + CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128, + CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129, + CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58, + CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59, + CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132, + CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133, + CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62, + CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63, + CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134, + CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135, + _theResult___fst_sfd__h576364, + _theResult___fst_sfd__h585087, + _theResult___fst_sfd__h593669, + _theResult___fst_sfd__h602853, + _theResult___fst_sfd__h611489, + _theResult___fst_sfd__h622115, + _theResult___fst_sfd__h630836, + _theResult___fst_sfd__h639418, + _theResult___fst_sfd__h648602, + _theResult___fst_sfd__h657238, + _theResult___fst_sfd__h667862, + _theResult___fst_sfd__h676583, + _theResult___fst_sfd__h685165, + _theResult___fst_sfd__h694349, + _theResult___fst_sfd__h702985; + reg [17 : 0] thin_otype__h857114, thin_otype__h896607; + reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885, + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052; + reg [13 : 0] thin_addrBits__h857110, + thin_addrBits__h896603, + thin_bounds_baseBits__h859108, + thin_bounds_baseBits__h898009, + thin_bounds_topBits__h859107, + thin_bounds_topBits__h898008; + reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337, + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333, + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q323; + reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q348, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q287, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q359, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q282, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353, + CASE_fetchStagepipelines_0_first_BITS_179_TO__ETC__q253, + CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q258; + reg [10 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_786_ETC__q286, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_786_ETC__q281, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q26, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30, + CASE_fetchStagepipelines_0_first_BITS_237_TO__ETC__q255, + CASE_fetchStagepipelines_1_first_BITS_237_TO__ETC__q263, + CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171, + CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172, + CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q200, + CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q201, + CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202, + CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203, + CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154, + CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155, + CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222, + CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223, + CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224, + CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225, + CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194, + CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195, + CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196, + CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197, + CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q198, + CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q199, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706; + reg [7 : 0] CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56, + CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57, + CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80, + CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81, + CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78, + CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79, + CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86, + CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87, + CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91, + CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92, + CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115, + CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116, + CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45, + CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46, + CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113, + CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114, + CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43, + CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44, + CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121, + CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122, + CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51, + CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52, + CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126, + CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127, + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907, + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073, + _theResult___fst_exp__h576363, + _theResult___fst_exp__h585086, + _theResult___fst_exp__h593668, + _theResult___fst_exp__h602852, + _theResult___fst_exp__h611488, + _theResult___fst_exp__h622114, + _theResult___fst_exp__h630835, + _theResult___fst_exp__h639417, + _theResult___fst_exp__h648601, + _theResult___fst_exp__h657237, + _theResult___fst_exp__h667861, + _theResult___fst_exp__h676582, + _theResult___fst_exp__h685164, + _theResult___fst_exp__h694348, + _theResult___fst_exp__h702984; + reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q338, + CASE_mmio_cRqQ_data_0_BITS_150_TO_149_0_mmio_c_ETC__q1, + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q329, + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785; + reg [4 : 0] CASE_basicExec_7570_BITS_270_TO_266_0_basicExe_ETC__q355, + CASE_basicExec_9648_BITS_270_TO_266_0_basicExe_ETC__q344, + CASE_capChecks_142_BITS_4_TO_0_0_capChecks_142_ETC__q289, + CASE_checkForException_0432_BITS_4_TO_0_0_chec_ETC__q256, + CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q24, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q349, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q288, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q360, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q283, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336, + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331, + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332, + CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q23, + CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q327, + CASE_fetchStagepipelines_0_first_BITS_166_TO__ETC__q252, + CASE_fetchStagepipelines_1_first_BITS_166_TO__ETC__q262, + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q321, + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q322, + CASE_robdeqPort_0_deq_data_BITS_95_TO_3226_BIT_ETC__q328, + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21807, + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21953, + cause_code__h992427, + i__h992443, + t__h212809, + t__h215095; + reg [3 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__819_ETC__q247, + CASE_IF_coreFix_aluExe_0_regToExeQ_first__9257_ETC__q249, + CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__7_ETC__q245, + CASE_IF_coreFix_aluExe_1_dispToRegQ_first__559_ETC__q239, + CASE_IF_coreFix_aluExe_1_regToExeQ_first__7179_ETC__q243, + CASE_IF_coreFix_aluExe_1_rsAlu_dispatchData__5_ETC__q241, + CASE_IF_fetchStage_pipelines_0_first__0045_BIT_ETC__q251, + CASE_IF_fetchStage_pipelines_1_first__0054_BIT_ETC__q260, + CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330, + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q320, + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18341, + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19313, + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17968, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15732, + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17235, + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15357, + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20197, + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21810, + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590, + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21145, + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21954, + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039, + i__h992617, + thin_perms_soft__h857361, + thin_perms_soft__h896782; + reg [2 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__819_ETC__q246, + CASE_IF_coreFix_aluExe_0_regToExeQ_first__9257_ETC__q248, + CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__7_ETC__q244, + CASE_IF_coreFix_aluExe_1_dispToRegQ_first__559_ETC__q238, + CASE_IF_coreFix_aluExe_1_regToExeQ_first__7179_ETC__q242, + CASE_IF_coreFix_aluExe_1_rsAlu_dispatchData__5_ETC__q240, + CASE_IF_fetchStage_pipelines_0_first__0045_BIT_ETC__q250, + CASE_IF_fetchStage_pipelines_1_first__0054_BIT_ETC__q259, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q345, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_790_ETC__q284, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q339, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q356, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_790_ETC__q279, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q350, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q365, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q278, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q361, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q315, + CASE_fetchStagepipelines_0_first_BITS_241_TO__ETC__q254, + CASE_fetchStagepipelines_1_first_BITS_241_TO__ETC__q261, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18370, + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19342, + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17997, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15761, + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17264, + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15386, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850, + IF_fetchStage_pipelines_0_first__0045_BITS_231_ETC___d20226, + IF_fetchStage_pipelines_1_first__0054_BITS_231_ETC___d21174, + x__h501025, + x__h508693; + reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q311, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q367, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q313, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309, + thin_reserved__h857113, + thin_reserved__h896606; + reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q257, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, - CASE_fetchStage_pipelines_0_canDeq__2603_AND_N_ETC__q234, - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233, - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230, - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231, - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235, - CASE_guard00025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, - CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87, - CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86, - CASE_guard09094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, - CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89, - CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88, - CASE_guard29514_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, - CASE_guard29514_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, - CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118, - CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117, - CASE_guard38826_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, - CASE_guard38826_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, - CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, - CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47, - CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, - CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, - CASE_guard47895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, - CASE_guard47895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, - CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50, - CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, - CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122, - CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121, - CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, - CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51, - CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124, - CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123, - CASE_guard68715_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, - CASE_guard68715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, - CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54, - CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, - CASE_guard78027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, - CASE_guard78027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, - CASE_guard87096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, - CASE_guard87096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83, - CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82, - CASE_guard90713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, - CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85, - CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84, - CASE_k61043_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442, - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455, - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459, - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472, - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485, - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498, - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505, - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508, - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515, - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522, - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050, - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063, - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067, - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080, - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093, - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106, - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113, - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116, - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123, - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130, - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834, - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847, - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851, - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864, - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877, - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890, - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897, - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900, - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907, - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10832, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10868, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10916, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10958, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d11000, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8425, - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240, - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296, - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13859, - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13862, - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13244, - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268, - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13301, - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13601, - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13622, - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13639, - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13692, - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13694, - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13708, - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13715, - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13784, - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13795, - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13992, - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13993, - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13650, - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13781, - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13806, - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261, - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__260_ETC___d13742, - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227, - SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13528; - wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3243; - wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2506, - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517, - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2519, - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2518; - wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941; - wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14864; - wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004; - wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2925, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14855; - wire [321 : 0] basicExec___d11860, basicExec___d12469; - wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999; - wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2916, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14846; - wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994; - wire [68 : 0] execFpuSimple___d11034; - wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627; - wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2566; - wire [63 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12316, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12317, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12328, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12329, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11707, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11708, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11719, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11720, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8333, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8344, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8355, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8356, - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1647, - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648, - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1658, - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659, - IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10634, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9165, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9166, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9925, - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563, - IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377, - IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424, - IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378, - IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425, - IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, - IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663, - _theResult___fst__h600259, - _theResult___snd__h600260, - a___1__h599978, - a___1__h600264, - a__h599837, - amoExec___d880, - b___1__h599979, - b___1__h600309, - b__h599838, - base__h694789, - base__h694992, - data___1__h472205, - data___1__h473013, - data__h472479, - fcsr_csr__read__h606149, - fflags_csr__read__h606124, - frm_csr__read__h606135, - mcause_csr__read__h607796, - mcounteren_csr__read__h607541, - medeleg_csr__read__h607141, - mideleg_csr__read__h607236, - mie_csr__read__h607367, - mip_csr__read__h608036, - mstatus_csr__read__h606993, - mtvec_csr__read__h607449, - n___1__h195750, - n__h191675, - n__read__h608140, - n__read__h608331, - n__read__h6134, - n__read__h703197, - next_pc__h702540, - q___1__h473078, - rVal1__h478959, - rVal2__h478960, - r___1__h473104, - res_data__h335087, - res_data__h335092, - res_data__h380782, - res_data__h380787, - res_data__h426470, - res_data__h426475, - resp_addr__h289191, - robdeqPort_0_deq_data_BITS_95_TO_32__q261, - satp_csr__read__h606850, - scause_csr__read__h606648, - scounteren_csr__read__h606510, - shiftData__h180514, - sie_csr__read__h606414, - sip_csr__read__h606787, - sstatus_csr__read__h606345, - stvec_csr__read__h606457, - upd__h3639, - upd__h4956, - v__h604755, - v__h628443, - vaddr__h180509, - x__h152890, - x__h156437, - x__h159251, - x__h161099, - x__h17672, - x__h180423, - x__h180424, - x__h20210, - x__h284511, - x__h286365, - x__h45579, - x__h478868, - x__h478869, - x__h478870, - x__h48115, - x__h613034, - x__h613035, - x__h634254, - x__h634255, - x__h688723, - x_addr__h311294, - x_quotient__h472393, - x_reg_ifc__read__h606254, - x_remainder__h472394, - y__h705648, - y_avValue__h179511, - y_avValue__h180117, - y_avValue__h476004, - y_avValue__h476612, - y_avValue__h477214, - y_avValue__h605661, - y_avValue__h610923, - y_avValue__h629196, - y_avValue__h632153, - y_avValue__h693065, - y_avValue__h694826, - y_avValue_snd_snd_snd_snd_snd__h705148, - y_avValue_snd_snd_snd_snd_snd__h705701, - y_avValue_snd_snd_snd_snd_snd__h705730; - wire [62 : 0] IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10632, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869, - r1__read__h608838, - r1__read__h609242, - r1__read__h609772, - r1__read__h609777, - r1__read__h609796, - r1__read__h610049, - r1__read__h610227, - r1__read__h610345, - r1__read__h610350, - r1__read__h610369; - wire [61 : 0] r1__read__h608840, - r1__read__h609244, - r1__read__h609779, - r1__read__h609798, - r1__read__h610051, - r1__read__h610203, - r1__read__h610229, - r1__read__h610352, - r1__read__h610371; - wire [60 : 0] r1__read__h610053, - r1__read__h610205, - r1__read__h610231, - r1__read__h610373; - wire [59 : 0] r1__read__h608842, - r1__read__h609246, - r1__read__h609790, - r1__read__h609800, - r1__read__h610055, - r1__read__h610233, - r1__read__h610363, - r1__read__h610375; - wire [58 : 0] r1__read__h608844, - r1__read__h609248, - r1__read__h609802, - r1__read__h610057, - r1__read__h610235, - r1__read__h610377; - wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546, - IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008, - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, - r1__read__h608846, - r1__read__h609250, - r1__read__h609804, - r1__read__h610059, - r1__read__h610207, - r1__read__h610237, - r1__read__h610379, - y__h252024; - wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20, - IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55, - IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173, - _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554, - _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946, - _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338, - _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118, - _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645, - _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355, - _theResult____h343300, - _theResult____h360939, - _theResult____h388992, - _theResult____h406629, - _theResult____h434680, - _theResult____h452317, - _theResult____h500015, - _theResult____h538816, - _theResult____h578017, - _theResult___snd__h351422, - _theResult___snd__h351433, - _theResult___snd__h351435, - _theResult___snd__h351445, - _theResult___snd__h351451, - _theResult___snd__h351474, - _theResult___snd__h360018, - _theResult___snd__h360020, - _theResult___snd__h360027, - _theResult___snd__h360033, - _theResult___snd__h360056, - _theResult___snd__h369188, - _theResult___snd__h369199, - _theResult___snd__h369201, - _theResult___snd__h369211, - _theResult___snd__h369217, - _theResult___snd__h369240, - _theResult___snd__h377808, - _theResult___snd__h377822, - _theResult___snd__h377828, - _theResult___snd__h377846, - _theResult___snd__h397112, - _theResult___snd__h397123, - _theResult___snd__h397125, - _theResult___snd__h397135, - _theResult___snd__h397141, - _theResult___snd__h397164, - _theResult___snd__h405708, - _theResult___snd__h405710, - _theResult___snd__h405717, - _theResult___snd__h405723, - _theResult___snd__h405746, - _theResult___snd__h414878, - _theResult___snd__h414889, - _theResult___snd__h414891, - _theResult___snd__h414901, - _theResult___snd__h414907, - _theResult___snd__h414930, - _theResult___snd__h423498, - _theResult___snd__h423512, - _theResult___snd__h423518, - _theResult___snd__h423536, - _theResult___snd__h442800, - _theResult___snd__h442811, - _theResult___snd__h442813, - _theResult___snd__h442823, - _theResult___snd__h442829, - _theResult___snd__h442852, - _theResult___snd__h451396, - _theResult___snd__h451398, - _theResult___snd__h451405, - _theResult___snd__h451411, - _theResult___snd__h451434, - _theResult___snd__h460566, - _theResult___snd__h460577, - _theResult___snd__h460579, - _theResult___snd__h460589, - _theResult___snd__h460595, - _theResult___snd__h460618, - _theResult___snd__h469186, - _theResult___snd__h469200, - _theResult___snd__h469206, - _theResult___snd__h469224, - _theResult___snd__h498625, - _theResult___snd__h498627, - _theResult___snd__h498634, - _theResult___snd__h498640, - _theResult___snd__h498663, - _theResult___snd__h508262, - _theResult___snd__h508273, - _theResult___snd__h508275, - _theResult___snd__h508285, - _theResult___snd__h508291, - _theResult___snd__h508314, - _theResult___snd__h517030, - _theResult___snd__h517044, - _theResult___snd__h517050, - _theResult___snd__h517068, - _theResult___snd__h537426, - _theResult___snd__h537428, - _theResult___snd__h537435, - _theResult___snd__h537441, - _theResult___snd__h537464, - _theResult___snd__h547063, - _theResult___snd__h547074, - _theResult___snd__h547076, - _theResult___snd__h547086, - _theResult___snd__h547092, - _theResult___snd__h547115, - _theResult___snd__h555831, - _theResult___snd__h555845, - _theResult___snd__h555851, - _theResult___snd__h555869, - _theResult___snd__h576627, - _theResult___snd__h576629, - _theResult___snd__h576636, - _theResult___snd__h576642, - _theResult___snd__h576665, - _theResult___snd__h586264, - _theResult___snd__h586275, - _theResult___snd__h586277, - _theResult___snd__h586287, - _theResult___snd__h586293, - _theResult___snd__h586316, - _theResult___snd__h595032, - _theResult___snd__h595046, - _theResult___snd__h595052, - _theResult___snd__h595070, - r1__read__h610061, - r1__read__h610209, - r1__read__h610239, - r1__read__h610381, - result__h361552, - result__h407242, - result__h452930, - result__h500628, - result__h539429, - result__h578630, - sfd__h335695, - sfd__h381390, - sfd__h427078, - sfd__h479673, - sfd__h518615, - sfd__h557816, - sfdin__h351405, - sfdin__h369171, - sfdin__h397095, - sfdin__h414861, - sfdin__h442783, - sfdin__h460549, - sfdin__h508245, - sfdin__h547046, - sfdin__h586247, - x__h361649, - x__h407339, - x__h453027, - x__h500723, - x__h539524, - x__h578725; - wire [55 : 0] r1__read__h608848, - r1__read__h609252, - r1__read__h609806, - r1__read__h610063, - r1__read__h610241, - r1__read__h610383; - wire [54 : 0] r1__read__h608850, - r1__read__h609254, - r1__read__h609808, - r1__read__h610065, - r1__read__h610243, - r1__read__h610385; - wire [53 : 0] r1__read__h610186, - r1__read__h610211, - r1__read__h610245, - r1__read__h610387, - sfd__h498692, - sfd__h508343, - sfd__h517103, - sfd__h537493, - sfd__h547144, - sfd__h555904, - sfd__h576694, - sfd__h586345, - sfd__h595105, - value__h343922, - value__h389612, - value__h435300; - wire [52 : 0] r1__read__h610067, - r1__read__h610188, - r1__read__h610213, - r1__read__h610247, - r1__read__h610389; - wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599, - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601, - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132, - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134, - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836, - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857, - _theResult___fst_sfd__h483602, - _theResult___fst_sfd__h499430, - _theResult___fst_sfd__h499433, - _theResult___fst_sfd__h509081, - _theResult___fst_sfd__h509084, - _theResult___fst_sfd__h517865, - _theResult___fst_sfd__h517868, - _theResult___fst_sfd__h517877, - _theResult___fst_sfd__h517883, - _theResult___fst_sfd__h522403, - _theResult___fst_sfd__h538231, - _theResult___fst_sfd__h538234, - _theResult___fst_sfd__h547882, - _theResult___fst_sfd__h547885, - _theResult___fst_sfd__h556666, - _theResult___fst_sfd__h556669, - _theResult___fst_sfd__h556678, - _theResult___fst_sfd__h556684, - _theResult___fst_sfd__h561604, - _theResult___fst_sfd__h577432, - _theResult___fst_sfd__h577435, - _theResult___fst_sfd__h587083, - _theResult___fst_sfd__h587086, - _theResult___fst_sfd__h595867, - _theResult___fst_sfd__h595870, - _theResult___fst_sfd__h595879, - _theResult___fst_sfd__h595885, - _theResult___sfd__h499330, - _theResult___sfd__h508981, - _theResult___sfd__h517765, - _theResult___sfd__h538131, - _theResult___sfd__h547782, - _theResult___sfd__h556566, - _theResult___sfd__h577332, - _theResult___sfd__h586983, - _theResult___sfd__h595767, - _theResult___snd_fst_sfd__h479627, - _theResult___snd_fst_sfd__h499436, - _theResult___snd_fst_sfd__h517871, - _theResult___snd_fst_sfd__h518569, - _theResult___snd_fst_sfd__h538237, - _theResult___snd_fst_sfd__h556672, - _theResult___snd_fst_sfd__h557770, - _theResult___snd_fst_sfd__h577438, - _theResult___snd_fst_sfd__h595873, - out___1_sfd__h479376, - out___1_sfd__h518318, - out___1_sfd__h557519, - out_sfd__h499333, - out_sfd__h508984, - out_sfd__h517768, - out_sfd__h538134, - out_sfd__h547785, - out_sfd__h556569, - out_sfd__h577335, - out_sfd__h586986, - out_sfd__h595770, - r1__read__h610391; - wire [50 : 0] r1__read__h608852, r1__read__h610069; - wire [49 : 0] r1__read__h610190, r1__read__h610393; - wire [48 : 0] r1__read__h608854, r1__read__h610071, r1__read__h610192; - wire [46 : 0] r1__read__h608856, r1__read__h610073; - wire [45 : 0] r1__read__h608858, r1__read__h610075; - wire [44 : 0] r1__read__h608860, r1__read__h610077; - wire [43 : 0] r1__read__h608862, r1__read__h610079; - wire [42 : 0] r1__read__h610081; - wire [41 : 0] r1__read__h610083; - wire [40 : 0] r1__read__h610085; - wire [37 : 0] IF_fetchStage_pipelines_0_first__2605_BIT_160__ETC___d13871, - IF_fetchStage_pipelines_1_first__2614_BIT_160__ETC___d13998; - wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2, - coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4, - data72479_BITS_31_TO_0__q5, - imm__h649452, - r1__read__h608864, - r1__read__h610087, - x__h190900, - x__h335099, - x__h380794, - x__h426482, - x__h75524, - x_data__h65373, - x_data_imm__h667947, - x_data_imm__h682690; - wire [29 : 0] r1__read__h608866, r1__read__h610089; - wire [27 : 0] r1__read__h610091; - wire [24 : 0] NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13903, - sfd__h351503, - sfd__h360085, - sfd__h369269, - sfd__h377881, - sfd__h397193, - sfd__h405775, - sfd__h414959, - sfd__h423571, - sfd__h442881, - sfd__h451463, - sfd__h460647, - sfd__h469259, - value__h484231, - value__h523032, - value__h562233; - wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953, - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955, - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345, - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347, - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737, - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739, - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999, - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001, - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391, - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393, - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783, - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804, - _theResult___fst_sfd__h352009, - _theResult___fst_sfd__h360591, - _theResult___fst_sfd__h369775, - _theResult___fst_sfd__h378411, - _theResult___fst_sfd__h378420, - _theResult___fst_sfd__h378426, - _theResult___fst_sfd__h397699, - _theResult___fst_sfd__h406281, - _theResult___fst_sfd__h415465, - _theResult___fst_sfd__h424101, - _theResult___fst_sfd__h424110, - _theResult___fst_sfd__h424116, - _theResult___fst_sfd__h443387, - _theResult___fst_sfd__h451969, - _theResult___fst_sfd__h461153, - _theResult___fst_sfd__h469789, - _theResult___fst_sfd__h469798, - _theResult___fst_sfd__h469804, - _theResult___sfd__h351928, - _theResult___sfd__h360510, - _theResult___sfd__h369694, - _theResult___sfd__h378330, - _theResult___sfd__h378432, - _theResult___sfd__h397618, - _theResult___sfd__h406200, - _theResult___sfd__h415384, - _theResult___sfd__h424020, - _theResult___sfd__h424122, - _theResult___sfd__h443306, - _theResult___sfd__h451888, - _theResult___sfd__h461072, - _theResult___sfd__h469708, - _theResult___sfd__h469810, - _theResult___snd_fst_sfd__h335645, - _theResult___snd_fst_sfd__h360594, - _theResult___snd_fst_sfd__h378414, - _theResult___snd_fst_sfd__h381340, - _theResult___snd_fst_sfd__h406284, - _theResult___snd_fst_sfd__h424104, - _theResult___snd_fst_sfd__h427028, - _theResult___snd_fst_sfd__h451972, - _theResult___snd_fst_sfd__h469792, - out_f_sfd__h378709, - out_f_sfd__h424399, - out_f_sfd__h470087, - out_sfd__h351931, - out_sfd__h360513, - out_sfd__h369697, - out_sfd__h378333, - out_sfd__h397621, - out_sfd__h406203, - out_sfd__h415387, - out_sfd__h424023, - out_sfd__h443309, - out_sfd__h451891, - out_sfd__h461075, - out_sfd__h469711; - wire [19 : 0] r1__read__h610026; - wire [14 : 0] IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674, - _theResult____h645396, - enabled_ints___1__h645893, - enabled_ints__h645940, - pend_ints__h645394, - y__h645905; - wire [12 : 0] fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437, - r1__read_BITS_12_TO_0___h645916; - wire [11 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9648, - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546, - IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99, - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10111, - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8638, - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9348, - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129, - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146, - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169, - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007, - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399, - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791, - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114, - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641, - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351, - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8501, - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9226, - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9989, - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550, - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942, - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334, - renaming_spec_bits__h675346, - result__h641103, - result__h641154, - spec_bits__h678441, - w__h641098, - x__h361682, - x__h407372, - x__h453060, - x__h500756, - x__h539557, - x__h578758, - x__h641102, - x__h641153, - y__h641132, - y__h678454, - y_avValue_fst__h671838, - y_avValue_snd_fst__h672112, - y_avValue_snd_fst__h672147; - wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516, - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518, - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048, - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050, - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753, - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784, - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786, - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132, - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149, - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172, - _theResult___exp__h499329, - _theResult___exp__h508980, - _theResult___exp__h517764, - _theResult___exp__h538130, - _theResult___exp__h547781, - _theResult___exp__h556565, - _theResult___exp__h577331, - _theResult___exp__h586982, - _theResult___exp__h595766, - _theResult___fst_exp__h483601, - _theResult___fst_exp__h498665, - _theResult___fst_exp__h498671, - _theResult___fst_exp__h498674, - _theResult___fst_exp__h499429, - _theResult___fst_exp__h499432, - _theResult___fst_exp__h508251, - _theResult___fst_exp__h508316, - _theResult___fst_exp__h508322, - _theResult___fst_exp__h508325, - _theResult___fst_exp__h509080, - _theResult___fst_exp__h509083, - _theResult___fst_exp__h517036, - _theResult___fst_exp__h517075, - _theResult___fst_exp__h517081, - _theResult___fst_exp__h517084, - _theResult___fst_exp__h517864, - _theResult___fst_exp__h517867, - _theResult___fst_exp__h517876, - _theResult___fst_exp__h517879, - _theResult___fst_exp__h522402, - _theResult___fst_exp__h537466, - _theResult___fst_exp__h537472, - _theResult___fst_exp__h537475, - _theResult___fst_exp__h538230, - _theResult___fst_exp__h538233, - _theResult___fst_exp__h547052, - _theResult___fst_exp__h547117, - _theResult___fst_exp__h547123, - _theResult___fst_exp__h547126, - _theResult___fst_exp__h547881, - _theResult___fst_exp__h547884, - _theResult___fst_exp__h555837, - _theResult___fst_exp__h555876, - _theResult___fst_exp__h555882, - _theResult___fst_exp__h555885, - _theResult___fst_exp__h556665, - _theResult___fst_exp__h556668, - _theResult___fst_exp__h556677, - _theResult___fst_exp__h556680, - _theResult___fst_exp__h561603, - _theResult___fst_exp__h576667, - _theResult___fst_exp__h576673, - _theResult___fst_exp__h576676, - _theResult___fst_exp__h577431, - _theResult___fst_exp__h577434, - _theResult___fst_exp__h586253, - _theResult___fst_exp__h586318, - _theResult___fst_exp__h586324, - _theResult___fst_exp__h586327, - _theResult___fst_exp__h587082, - _theResult___fst_exp__h587085, - _theResult___fst_exp__h595038, - _theResult___fst_exp__h595077, - _theResult___fst_exp__h595083, - _theResult___fst_exp__h595086, - _theResult___fst_exp__h595866, - _theResult___fst_exp__h595869, - _theResult___fst_exp__h595878, - _theResult___fst_exp__h595881, - _theResult___snd_fst_exp__h499435, - _theResult___snd_fst_exp__h517870, - _theResult___snd_fst_exp__h538236, - _theResult___snd_fst_exp__h556671, - _theResult___snd_fst_exp__h577437, - _theResult___snd_fst_exp__h595872, - coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63, - coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28, - coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98, - csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12647, - din_inc___2_exp__h517924, - din_inc___2_exp__h517959, - din_inc___2_exp__h517985, - din_inc___2_exp__h556725, - din_inc___2_exp__h556760, - din_inc___2_exp__h556786, - din_inc___2_exp__h595926, - din_inc___2_exp__h595961, - din_inc___2_exp__h595987, - out_exp__h499332, - out_exp__h508983, - out_exp__h517767, - out_exp__h538133, - out_exp__h547784, - out_exp__h556568, - out_exp__h577334, - out_exp__h586985, - out_exp__h595769; - wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652; - wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306, - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309, - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698, - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701, - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090, - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093, - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853, - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855, - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245, - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247, - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637, - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706, - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104, - _theResult___exp__h351927, - _theResult___exp__h360509, - _theResult___exp__h369693, - _theResult___exp__h378329, - _theResult___exp__h378431, - _theResult___exp__h397617, - _theResult___exp__h406199, - _theResult___exp__h415383, - _theResult___exp__h424019, - _theResult___exp__h424121, - _theResult___exp__h443305, - _theResult___exp__h451887, - _theResult___exp__h461071, - _theResult___exp__h469707, - _theResult___exp__h469809, - _theResult___fst_exp__h351411, - _theResult___fst_exp__h351476, - _theResult___fst_exp__h351482, - _theResult___fst_exp__h351485, - _theResult___fst_exp__h352008, - _theResult___fst_exp__h360058, - _theResult___fst_exp__h360064, - _theResult___fst_exp__h360067, - _theResult___fst_exp__h360590, - _theResult___fst_exp__h369177, - _theResult___fst_exp__h369242, - _theResult___fst_exp__h369248, - _theResult___fst_exp__h369251, - _theResult___fst_exp__h369774, - _theResult___fst_exp__h377814, - _theResult___fst_exp__h377853, - _theResult___fst_exp__h377859, - _theResult___fst_exp__h377862, - _theResult___fst_exp__h378410, - _theResult___fst_exp__h378419, - _theResult___fst_exp__h378422, - _theResult___fst_exp__h397101, - _theResult___fst_exp__h397166, - _theResult___fst_exp__h397172, - _theResult___fst_exp__h397175, - _theResult___fst_exp__h397698, - _theResult___fst_exp__h405748, - _theResult___fst_exp__h405754, - _theResult___fst_exp__h405757, - _theResult___fst_exp__h406280, - _theResult___fst_exp__h414867, - _theResult___fst_exp__h414932, - _theResult___fst_exp__h414938, - _theResult___fst_exp__h414941, - _theResult___fst_exp__h415464, - _theResult___fst_exp__h423504, - _theResult___fst_exp__h423543, - _theResult___fst_exp__h423549, - _theResult___fst_exp__h423552, - _theResult___fst_exp__h424100, - _theResult___fst_exp__h424109, - _theResult___fst_exp__h424112, - _theResult___fst_exp__h442789, - _theResult___fst_exp__h442854, - _theResult___fst_exp__h442860, - _theResult___fst_exp__h442863, - _theResult___fst_exp__h443386, - _theResult___fst_exp__h451436, - _theResult___fst_exp__h451442, - _theResult___fst_exp__h451445, - _theResult___fst_exp__h451968, - _theResult___fst_exp__h460555, - _theResult___fst_exp__h460620, - _theResult___fst_exp__h460626, - _theResult___fst_exp__h460629, - _theResult___fst_exp__h461152, - _theResult___fst_exp__h469192, - _theResult___fst_exp__h469231, - _theResult___fst_exp__h469237, - _theResult___fst_exp__h469240, - _theResult___fst_exp__h469788, - _theResult___fst_exp__h469797, - _theResult___fst_exp__h469800, - _theResult___snd_fst_exp__h360593, - _theResult___snd_fst_exp__h378413, - _theResult___snd_fst_exp__h406283, - _theResult___snd_fst_exp__h424103, - _theResult___snd_fst_exp__h451971, - _theResult___snd_fst_exp__h469791, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145, - din_inc___2_exp__h378444, - din_inc___2_exp__h378468, - din_inc___2_exp__h378498, - din_inc___2_exp__h378522, - din_inc___2_exp__h424134, - din_inc___2_exp__h424158, - din_inc___2_exp__h424188, - din_inc___2_exp__h424212, - din_inc___2_exp__h469822, - din_inc___2_exp__h469846, - din_inc___2_exp__h469876, - din_inc___2_exp__h469900, - out_exp__h351930, - out_exp__h360512, - out_exp__h369696, - out_exp__h378332, - out_exp__h397620, - out_exp__h406202, - out_exp__h415386, - out_exp__h424022, - out_exp__h443308, - out_exp__h451890, - out_exp__h461074, - out_exp__h469710, - out_f_exp__h378708, - out_f_exp__h424398, - out_f_exp__h470086, - x__h608823; - wire [6 : 0] csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12642; - wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243, - IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635, - IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027, - IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360, - IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887, - IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597, - IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794, - IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186, - IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578, - IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463, - IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172, - IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300, - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14890, - x__h180646, - x__h694804; - wire [4 : 0] IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d14039, - IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978, - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177, - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569, - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961, - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10719, - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10760, - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804, - checkForException___d12839, - checkForException___d13458, - fflags__h705625, - res_fflags__h335088, - res_fflags__h380783, - res_fflags__h426471, - rs1__h649451, - x__h152884, - x__h156431, - x__h159247, - x__h284499, - y_avValue_snd_fst__h705132, - y_avValue_snd_fst__h705685, - y_avValue_snd_fst__h705714; - wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847, - IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849, - IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851, - IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853, - IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1855, - IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1857, - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13017, - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13018, - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13019, - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13020, - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13021, - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13022, - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13023, - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13024, - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13025, - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13026, - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13027, - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13028, - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13029, - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3__ETC___d13055, - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791, - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978, - IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832, - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792, - IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d13074, - cause_code__h692187, - vm_mode_reg__read__h610032; - wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535, - IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, - IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, - _theResult_____2__h293741, - next_deqP___1__h294020, - v__h293161, - v__h293392, - x__h299371, - x_decodeInfo_frm__h649135; - wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, - IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, - IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771, - IF_sfdin08245_BIT_4_THEN_2_ELSE_0__q131, - IF_sfdin14861_BIT_33_THEN_2_ELSE_0__q66, - IF_sfdin42783_BIT_33_THEN_2_ELSE_0__q91, - IF_sfdin47046_BIT_4_THEN_2_ELSE_0__q171, - IF_sfdin51405_BIT_33_THEN_2_ELSE_0__q21, - IF_sfdin60549_BIT_33_THEN_2_ELSE_0__q101, - IF_sfdin69171_BIT_33_THEN_2_ELSE_0__q31, - IF_sfdin86247_BIT_4_THEN_2_ELSE_0__q148, - IF_sfdin97095_BIT_33_THEN_2_ELSE_0__q56, - IF_theResult___snd05708_BIT_33_THEN_2_ELSE_0__q58, - IF_theResult___snd17030_BIT_4_THEN_2_ELSE_0__q134, - IF_theResult___snd23498_BIT_33_THEN_2_ELSE_0__q71, - IF_theResult___snd37426_BIT_4_THEN_2_ELSE_0__q167, - IF_theResult___snd51396_BIT_33_THEN_2_ELSE_0__q93, - IF_theResult___snd55831_BIT_4_THEN_2_ELSE_0__q174, - IF_theResult___snd60018_BIT_33_THEN_2_ELSE_0__q23, - IF_theResult___snd69186_BIT_33_THEN_2_ELSE_0__q106, - IF_theResult___snd76627_BIT_4_THEN_2_ELSE_0__q144, - IF_theResult___snd77808_BIT_33_THEN_2_ELSE_0__q36, - IF_theResult___snd95032_BIT_4_THEN_2_ELSE_0__q151, - IF_theResult___snd98625_BIT_4_THEN_2_ELSE_0__q127, - guard__h343310, - guard__h352019, - guard__h360949, - guard__h369785, - guard__h389002, - guard__h397709, - guard__h406639, - guard__h415475, - guard__h434690, - guard__h443397, - guard__h452327, - guard__h461163, - guard__h490713, - guard__h500025, - guard__h509094, - guard__h529514, - guard__h538826, - guard__h547895, - guard__h568715, - guard__h578027, - guard__h587096, - prv__h707140, - prv__h707184, - r1__read_BITS_13_TO_12___h649320, - sbIdx__h156310, - v__h600772, - v__h600782, - v__h601417, - x__h702600, - x__h705873, - y_avValue_snd_snd_snd_fst__h705142, - y_avValue_snd_snd_snd_fst__h705695, - y_avValue_snd_snd_snd_fst__h705724; - wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065, - IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115, - IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457, - IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507, - IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849, - IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899, - IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10657, - IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9895, - IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10404, - IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10669, - IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d8931, - IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9641, - IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9907, - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12881, - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d13513, - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d13549, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10450, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10654, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10681, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8977, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9687, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9892, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9919, - IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10109, - IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8636, - IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9346, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12133, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12134, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12135, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12158, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12159, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12160, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11338, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11339, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11340, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11363, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11364, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11365, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8238, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8239, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8240, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8262, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8263, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8264, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8286, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8287, - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8288, - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1602, - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1603, - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1604, - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1626, - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1627, - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628, - IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2082, - IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2099, - IF_NOT_fetchStage_pipelines_0_canDeq__2603_260_ETC___d13656, - IF_NOT_fetchStage_pipelines_0_canDeq__2603_260_ETC___d13664, - IF_NOT_fetchStage_pipelines_1_first__2614_BITS_ETC___d13586, - IF_NOT_fetchStage_pipelines_1_first__2614_BITS_ETC___d13663, - IF_NOT_rob_deqPort_1_deq_data__4562_BIT_25_456_ETC___d14762, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020, - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10452, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10683, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10878, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10892, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10907, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10924, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10936, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10949, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10966, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10978, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10991, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8979, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9689, - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9921, - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2077_ETC___d12109, - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2077_ETC___d12143, - IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1282_ETC___d11314, - IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1282_ETC___d11348, - IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8214, - IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8247, - IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8271, - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6489, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6526, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6601, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6617, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6630, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5097, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5134, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5198, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5209, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5225, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5238, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7881, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7918, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7982, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7993, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8009, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8022, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035, - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136, - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10454, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10685, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10740, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10781, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10825, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10840, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10850, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10861, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10880, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10894, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10909, 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_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6597, - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6624, - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792, - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793, - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7964, - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7989, - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8016, - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502, - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504, - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227, - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229, - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990, - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q174, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q176, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q178, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q180, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q182, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q184, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q205, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q207, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q209, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q211, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q213, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q215, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q302, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q312, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q318, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q319, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q36, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q37, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q38, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q314, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q275, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q276, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q277, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310, + CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q325, + CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q324, + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q273, + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q274, + CASE_fetchStage_pipelines_0_canDeq__0043_AND_N_ETC__q269, + CASE_fetchStagepipelines_0_first_BITS_264_TO__ETC__q268, + CASE_fetchStagepipelines_0_first_BITS_267_TO__ETC__q265, + CASE_fetchStagepipelines_0_first_BITS_267_TO__ETC__q271, + CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q264, + CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q266, + CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q270, + CASE_fetchStagepipelines_1_first_BITS_267_TO__ETC__q272, + CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73, + CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71, + CASE_guard04409_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183, + CASE_guard04409_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173, + CASE_guard13721_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179, + CASE_guard13721_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175, + CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102, + CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101, + CASE_guard22790_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181, + CASE_guard22790_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177, + CASE_guard26252_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104, + CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103, + CASE_guard35564_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, + CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106, + CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105, + CASE_guard44633_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160, + CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108, + CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107, + CASE_guard65105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214, + CASE_guard65105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204, + CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q137, + CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q136, + CASE_guard74417_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210, + CASE_guard74417_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208, + CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q66, + CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67, + CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139, + CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138, + CASE_guard83486_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212, + CASE_guard83486_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206, + CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69, + CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68, + CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141, + CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140, + CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72, + CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70, + CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143, + CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142, + CASE_k42381_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19004, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19040, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19049, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19058, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19067, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19076, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19085, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19094, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19103, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19112, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19121, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19130, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19139, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19154, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19182, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16640, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16728, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16750, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16772, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16794, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16816, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16838, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16860, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16882, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16904, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16926, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16948, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16970, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16998, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17065, + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556, + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569, + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10573, + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586, + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599, + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612, + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619, + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10622, + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629, + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636, + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159, + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172, + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9176, + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189, + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202, + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215, + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222, + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9225, + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232, + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239, + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953, + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966, + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11970, + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983, + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996, + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009, + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016, + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12019, + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026, + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12529, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12542, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12561, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14987, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15023, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15071, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15113, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15155, + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992, + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051, + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21801, + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21804, + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20995, + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21019, + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21055, + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21526, + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21622, + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21951, + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21952, + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21579, + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21718, + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__096_ETC___d21013, + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4882, + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638, + SEL_ARR_NOT_coreFix_memExe_forwardQ_data_0_216_ETC___d2240, + SEL_ARR_NOT_coreFix_memExe_memRespLdQ_data_0_1_ETC___d2157, + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__004_ETC___d21680, + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4836, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5062, + SEL_ARR_fetchStage_pipelines_0_canDeq__0043_AN_ETC___d21447; + wire [1159 : 0] basicExec___d17570, basicExec___d19648; + wire [620 : 0] NOT_coreFix_aluExe_0_dispToRegQ_first__8199_BI_ETC___d19248, + NOT_coreFix_aluExe_1_dispToRegQ_first__5590_BI_ETC___d17170; + wire [585 : 0] IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7404; + wire [574 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d5480, + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5491, + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5493, + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5492; + wire [521 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7126; + wire [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5153, + IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d5154, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7119, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d23883; + wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4925; + wire [457 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4232; + wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5151, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7109, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d23873; + wire [294 : 0] fetchStage_pipelines_0_first__0045_BIT_167_037_ETC___d20923; + wire [278 : 0] IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4231; + wire [265 : 0] prepareBoundsCheck___d4226; + wire [162 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18991, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18992, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16608, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16609, + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18996, + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16613, + coreFix_aluExe_0_dispToRegQ_first__8199_BIT_12_ETC___d19237, + coreFix_aluExe_1_dispToRegQ_first__5590_BIT_12_ETC___d17159; + wire [152 : 0] coreFix_memExe_dispToRegQ_first__680_BIT_101_6_ETC___d3569; + wire [151 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19196, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17092, + IF_coreFix_memExe_dispToRegQ_first__680_BIT_12_ETC___d3303; + wire [129 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__15_THEN_NOT_ETC___d550, + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5540, + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5542; + wire [128 : 0] amoExec___d4904, + amoExec___d773, + new_pc__h871587, + new_pc__h909530, + next_pc__h1007056, + pc__h960508, + v__h1007095, + v__h1007548, + x__h878565, + x__h912077; + wire [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5147, + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4863, + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4871, + coreFix_memExe_regToExeQ_first__633_BITS_139_T_ETC___d4052, + x__h183367, + x__h199219; + wire [108 : 0] IF_fetchStage_pipelines_0_first__0045_BITS_237_ETC___d20400, + IF_fetchStage_pipelines_1_first__0054_BITS_237_ETC___d21348; + wire [85 : 0] IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3568; + wire [71 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19195, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17091; + wire [68 : 0] execFpuSimple___d15189; + wire [66 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7018; + wire [65 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18613, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18614, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16230, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16231, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3031, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3032, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3400, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3401, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18620, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16237, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16654, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16648, + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18618, + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16235, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3036, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3405, + addTop__h239914, + addTop__h241071, + addTop__h254680, + address__h996601, + address__h996945, + address__h997258, + address__h997602, + coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389, + coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754, + coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692, + cr_address__h865332, + cr_address__h865880, + cr_address__h903813, + cr_address__h904361, + data_address__h1013045, + data_address__h1013899, + in__h239745, + in__h240902, + in__h254511, + in__h994763, + pc_address__h991846, + pointer__h242569, + res_address__h126791, + res_address__h139703, + res_address__h178866, + res_address__h197631, + res_address__h216390, + res_address__h235267, + res_address__h567273, + res_address__h568125, + res_address__h613882, + res_address__h659629, + res_address__h705438, + res_address__h706298, + res_address__h848496, + res_address__h890733, + result__h240541, + result__h241698, + result__h255307, + result_d_address__h242780, + ret__h239918, + ret__h241075, + ret__h254684, + x__h235690, + x__h239763, + x__h239911, + x__h240920, + x__h241068, + x__h248052, + x__h254529, + x__h254677, + x__h994781, + x__h996795, + x__h997099, + x__h997452, + x__h997756, + y__h239762, + y__h240919, + y__h254528, + y__h994780; + wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13306, + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12467, + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12468, + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12479, + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12480, + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12491, + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12492, + IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d12190, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13307, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14017, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14073, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14787, + IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d5538, + IF_coreFix_memExe_lsq_firstLd__498_BIT_111_509_ETC___d1911, + IF_coreFix_memExe_lsq_firstLd__498_BIT_111_509_ETC___d2077, + IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d1912, + IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d2078, + IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d1913, + IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d2079, + IF_csrf_mtcc_reg_read__6624_BIT_86_2574_AND_NO_ETC___d22678, + IF_csrf_stcc_reg_read__6615_BIT_86_2497_AND_NO_ETC___d22677, + IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23272, + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22438, + _18446744073709551615_SL_csrf_mtcc_reg_read__66_ETC___d22592, + _18446744073709551615_SL_csrf_stcc_reg_read__66_ETC___d22517, + _theResult___fst__h836055, + _theResult___snd__h836056, + a___1__h835774, + a___1__h836060, + a__h835633, + addBase__h239805, + addBase__h240962, + addBase__h254571, + addr__h148408, + addr__h151984, + addr__h235261, + addr__h986843, + address__h1008010, + address__h996535, + address__h996585, + b___1__h835775, + b___1__h836105, + b__h835634, + base__h996496, + base__h996550, + csrf_mtcc_reg_read__6624_BITS_149_TO_86_2579_A_ETC___d22582, + csrf_stcc_reg_read__6615_BITS_149_TO_86_2502_A_ETC___d22505, + data___1__h705460, + data___1__h706320, + data__h567607, + data__h613367, + data__h659114, + data__h704928, + data__h705760, + data__h705791, + fcsr_csr__read__h849070, + fflags_csr__read__h849045, + frm_csr__read__h849056, + mask__h996607, + mask__h997264, + mcause_csr__read__h850486, + mcounteren_csr__read__h850307, + medeleg_csr__read__h849987, + mideleg_csr__read__h850085, + mie_csr__read__h850212, + mip_csr__read__h850725, + mstatus_csr__read__h849833, + n__read__h1008440, + n__read__h7877, + newAddrDiff__h996608, + newAddrDiff__h996952, + newAddrDiff__h997265, + newAddrDiff__h997609, + offset__h242559, + q___1__h706385, + rVal1__h714446, + rVal2__h714447, + r___1__h706411, + res_data__h568165, + res_data__h568170, + res_data__h613919, + res_data__h613924, + res_data__h659666, + res_data__h659671, + resp_addr__h509039, + rg_tdata1__read__h851826, + robdeqPort_0_deq_data_BITS_95_TO_32__q326, + satp_csr__read__h849687, + scause_csr__read__h849484, + scounteren_csr__read__h849389, + sie_csr__read__h849336, + sip_csr__read__h849624, + sstatus_csr__read__h849266, + thin_address__h996489, + tmpAddr__h242768, + trap_val__h994147, + upd__h1008516, + upd__h3035, + upd__h3645, + upd__h7946, + value__h239635, + value__h239799, + value__h240792, + value__h240956, + value__h254401, + value__h254565, + x__h127272, + x__h140188, + x__h183449, + x__h202200, + x__h216766, + x__h239653, + x__h239655, + x__h240810, + x__h240812, + x__h242708, + x__h254419, + x__h254421, + x__h714355, + x__h714356, + x__h714357, + x__h865509, + x__h866057, + x__h903990, + x__h904538, + x__h992018, + x__h994694, + x__h994696, + x_addr__h19852, + x_addr__h44221, + x_addr__h535302, + x_quotient__h705674, + x_reg_ifc__read__h849175, + x_remainder__h705675, + y__h1010667, + y__h996724, + y__h997381, + y_avValue__h710401, + y_avValue__h711034, + y_avValue__h711661, + y_avValue_snd_snd_snd_snd_snd__h1010138, + y_avValue_snd_snd_snd_snd_snd__h1010720, + y_avValue_snd_snd_snd_snd_snd__h1010749; + wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14015, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14785, + r1__read__h852568, + r1__read__h852972, + r1__read__h853482, + r1__read__h853501, + r1__read__h853734, + r1__read__h853900, + r1__read__h853993, + r1__read__h854012; + wire [61 : 0] r1__read__h852570, + r1__read__h852974, + r1__read__h853484, + r1__read__h853503, + r1__read__h853736, + r1__read__h853876, + r1__read__h853902, + r1__read__h853995, + r1__read__h854014; + wire [60 : 0] r1__read__h853738, + r1__read__h853878, + r1__read__h853904, + r1__read__h854016; + wire [59 : 0] r1__read__h852572, + r1__read__h852976, + r1__read__h853505, + r1__read__h853740, + r1__read__h853906, + r1__read__h854018; + wire [58 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5478, + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5520, + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d6956, + r1__read__h852574, + r1__read__h852978, + r1__read__h853494, + r1__read__h853507, + r1__read__h853742, + r1__read__h853908, + r1__read__h854005, + r1__read__h854020; + wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7193, + r1__read__h852576, + r1__read__h852980, + r1__read__h853509, + r1__read__h853744, + r1__read__h853880, + r1__read__h853910, + r1__read__h854022, + y__h422493; + wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q109, + IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q39, + IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q74, + IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q149, + IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q166, + IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q189, + IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q119, + IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q49, + IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q84, + IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q145, + IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q152, + IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q162, + IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q169, + IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q185, + IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q192, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q111, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q124, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q41, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q54, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q76, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q89, + _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12786, + _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13501, + _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14271, + _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10060, + _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11457, + _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8663, + _theResult____h576381, + _theResult____h594020, + _theResult____h622132, + _theResult____h639769, + _theResult____h667879, + _theResult____h685516, + _theResult____h735554, + _theResult____h774407, + _theResult____h813711, + _theResult___snd__h584503, + _theResult___snd__h584514, + _theResult___snd__h584516, + _theResult___snd__h584526, + _theResult___snd__h584532, + _theResult___snd__h584555, + _theResult___snd__h593099, + _theResult___snd__h593101, + _theResult___snd__h593108, + _theResult___snd__h593114, + _theResult___snd__h593137, + _theResult___snd__h602269, + _theResult___snd__h602280, + _theResult___snd__h602282, + _theResult___snd__h602292, + _theResult___snd__h602298, + _theResult___snd__h602321, + _theResult___snd__h610889, + _theResult___snd__h610903, + _theResult___snd__h610909, + _theResult___snd__h610927, + _theResult___snd__h630252, + _theResult___snd__h630263, + _theResult___snd__h630265, + _theResult___snd__h630275, + _theResult___snd__h630281, + _theResult___snd__h630304, + _theResult___snd__h638848, + _theResult___snd__h638850, + _theResult___snd__h638857, + _theResult___snd__h638863, + _theResult___snd__h638886, + _theResult___snd__h648018, + _theResult___snd__h648029, + _theResult___snd__h648031, + _theResult___snd__h648041, + _theResult___snd__h648047, + _theResult___snd__h648070, + _theResult___snd__h656638, + _theResult___snd__h656652, + _theResult___snd__h656658, + _theResult___snd__h656676, + _theResult___snd__h675999, + _theResult___snd__h676010, + _theResult___snd__h676012, + _theResult___snd__h676022, + _theResult___snd__h676028, + _theResult___snd__h676051, + _theResult___snd__h684595, + _theResult___snd__h684597, + _theResult___snd__h684604, + _theResult___snd__h684610, + _theResult___snd__h684633, + _theResult___snd__h693765, + _theResult___snd__h693776, + _theResult___snd__h693778, + _theResult___snd__h693788, + _theResult___snd__h693794, + _theResult___snd__h693817, + _theResult___snd__h702385, + _theResult___snd__h702399, + _theResult___snd__h702405, + _theResult___snd__h702423, + _theResult___snd__h734164, + _theResult___snd__h734166, + _theResult___snd__h734173, + _theResult___snd__h734179, + _theResult___snd__h734202, + _theResult___snd__h743801, + _theResult___snd__h743812, + _theResult___snd__h743814, + _theResult___snd__h743824, + _theResult___snd__h743830, + _theResult___snd__h743853, + _theResult___snd__h752569, + _theResult___snd__h752583, + _theResult___snd__h752589, + _theResult___snd__h752607, + _theResult___snd__h773017, + _theResult___snd__h773019, + _theResult___snd__h773026, + _theResult___snd__h773032, + _theResult___snd__h773055, + _theResult___snd__h782654, + _theResult___snd__h782665, + _theResult___snd__h782667, + _theResult___snd__h782677, + _theResult___snd__h782683, + _theResult___snd__h782706, + _theResult___snd__h791422, + _theResult___snd__h791436, + _theResult___snd__h791442, + _theResult___snd__h791460, + _theResult___snd__h812321, + _theResult___snd__h812323, + _theResult___snd__h812330, + _theResult___snd__h812336, + _theResult___snd__h812359, + _theResult___snd__h821958, + _theResult___snd__h821969, + _theResult___snd__h821971, + _theResult___snd__h821981, + _theResult___snd__h821987, + _theResult___snd__h822010, + _theResult___snd__h830726, + _theResult___snd__h830740, + _theResult___snd__h830746, + _theResult___snd__h830764, + r1__read__h853746, + r1__read__h853882, + r1__read__h853912, + r1__read__h854024, + result__h594633, + result__h640382, + result__h686129, + result__h736167, + result__h775020, + result__h814324, + sfd__h568776, + sfd__h614530, + sfd__h660277, + sfd__h715187, + sfd__h754181, + sfd__h793485, + sfdin__h584486, + sfdin__h602252, + sfdin__h630235, + sfdin__h648001, + sfdin__h675982, + sfdin__h693748, + sfdin__h743784, + sfdin__h782637, + sfdin__h821941, + x__h594730, + x__h640479, + x__h686226, + x__h736262, + x__h775115, + x__h814419; + wire [55 : 0] coreFix_memExe_dispToRegQ_first__680_BIT_101_6_ETC___d3567, + r1__read__h852578, + r1__read__h852982, + r1__read__h853511, + r1__read__h853748, + r1__read__h853914, + r1__read__h854026; + wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19194, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17090, + r1__read__h852580, + r1__read__h852984, + r1__read__h853513, + r1__read__h853750, + r1__read__h853916, + r1__read__h854028; + wire [53 : 0] r1__read__h853859, + r1__read__h853884, + r1__read__h853918, + r1__read__h854030, + sfd__h734231, + sfd__h743882, + sfd__h752642, + sfd__h773084, + sfd__h782735, + sfd__h791495, + sfd__h812388, + sfd__h822039, + sfd__h830799, + value__h577003, + value__h622752, + value__h668499; + wire [52 : 0] IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3566, + INV_coreFix_aluExe_0_regToExeQ_first__9257_BIT_ETC___d19560, + INV_coreFix_aluExe_0_regToExeQ_first__9257_BIT_ETC___d19624, + INV_coreFix_aluExe_1_regToExeQ_first__7179_BIT_ETC___d17482, + INV_coreFix_aluExe_1_regToExeQ_first__7179_BIT_ETC___d17546, + r1__read__h853752, + r1__read__h853861, + r1__read__h853886, + r1__read__h853920, + r1__read__h854032; + wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13273, + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13275, + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13982, + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13984, + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14752, + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14754, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13246, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13248, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13292, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13294, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13956, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13958, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14001, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14003, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14726, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14728, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14771, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14773, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13305, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14014, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14784, + _theResult___fst_sfd__h719141, + _theResult___fst_sfd__h734969, + _theResult___fst_sfd__h734972, + _theResult___fst_sfd__h744620, + _theResult___fst_sfd__h744623, + _theResult___fst_sfd__h753404, + _theResult___fst_sfd__h753407, + _theResult___fst_sfd__h753416, + _theResult___fst_sfd__h753422, + _theResult___fst_sfd__h757994, + _theResult___fst_sfd__h773822, + _theResult___fst_sfd__h773825, + _theResult___fst_sfd__h783473, + _theResult___fst_sfd__h783476, + _theResult___fst_sfd__h792257, + _theResult___fst_sfd__h792260, + _theResult___fst_sfd__h792269, + _theResult___fst_sfd__h792275, + _theResult___fst_sfd__h797298, + _theResult___fst_sfd__h813126, + _theResult___fst_sfd__h813129, + _theResult___fst_sfd__h822777, + _theResult___fst_sfd__h822780, + _theResult___fst_sfd__h831561, + _theResult___fst_sfd__h831564, + _theResult___fst_sfd__h831573, + _theResult___fst_sfd__h831579, + _theResult___sfd__h734869, + _theResult___sfd__h744520, + _theResult___sfd__h753304, + _theResult___sfd__h773722, + _theResult___sfd__h783373, + _theResult___sfd__h792157, + _theResult___sfd__h813026, + _theResult___sfd__h822677, + _theResult___sfd__h831461, + _theResult___snd_fst_sfd__h715141, + _theResult___snd_fst_sfd__h734975, + _theResult___snd_fst_sfd__h753410, + _theResult___snd_fst_sfd__h754135, + _theResult___snd_fst_sfd__h773828, + _theResult___snd_fst_sfd__h792263, + _theResult___snd_fst_sfd__h793439, + _theResult___snd_fst_sfd__h813132, + _theResult___snd_fst_sfd__h831567, + mask__h239915, + mask__h241072, + mask__h254681, + out___1_sfd__h714889, + out___1_sfd__h753883, + out___1_sfd__h793187, + out_sfd__h734872, + out_sfd__h744523, + out_sfd__h753307, + out_sfd__h773725, + out_sfd__h783376, + out_sfd__h792160, + out_sfd__h813029, + out_sfd__h822680, + out_sfd__h831464; + wire [50 : 0] r1__read__h852582, r1__read__h853754; + wire [49 : 0] coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q5, + coreFix_memExe_regToExeQfirst_BITS_217_TO_168_ETC__q7, + coreFix_memExe_regToExeQfirst_BITS_380_TO_331_ETC__q3, + highOffsetBits__h242578, + mask__h239806, + mask__h240963, + mask__h254572, + r1__read__h853863, + signBits__h242575, + x__h242605; + wire [48 : 0] r1__read__h852584, r1__read__h853756, r1__read__h853865; + wire [46 : 0] r1__read__h852586, r1__read__h853758; + wire [45 : 0] r1__read__h852588, r1__read__h853760; + wire [44 : 0] r1__read__h852590, r1__read__h853762; + wire [43 : 0] r1__read__h852592, r1__read__h853764; + wire [42 : 0] r1__read__h853766; + wire [41 : 0] r1__read__h853768; + wire [40 : 0] r1__read__h853770; + wire [38 : 0] IF_csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_c_ETC___d22649; + wire [33 : 0] IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954, + IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120, + IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210, + IF_INV_coreFix_memExe_respLrScAmoQ_data_0_233__ETC___d1273, + IF_INV_mmio_dataRespQ_data_0_389_BITS_108_TO_9_ETC___d1433, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18870, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18871, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16487, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16488, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3292, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3293, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3559, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3560, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17079, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17073, + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18875, + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16492, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3297, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3564; + wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q144, + coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q22, + coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q21, + coreFix_memExe_regToExeQfirst_BITS_433_TO_402__q16, + data05760_BITS_31_TO_0__q25, + r1__read__h852594, + r1__read__h853772, + x__h568180, + x__h613934, + x__h65608, + x__h659681, + x_data__h60109; + wire [29 : 0] r1__read__h852596, r1__read__h853774; + wire [27 : 0] r1__read__h853776; + wire [25 : 0] IF_IF_csrf_prv_reg_read__0075_ULE_1_2375_AND_I_ETC___d22667, + IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19900, + IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19931, + IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17823, + IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17854, + IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999, + IF_csrf_mepcc_reg_read_wget__3098_BIT_34_3107__ETC___d23115, + IF_csrf_rg_dpc_read__3776_BIT_34_3785_THEN_csr_ETC___d23793, + IF_csrf_sepcc_reg_read_wget__3069_BIT_34_3078__ETC___d23086; + wire [24 : 0] sfd__h584584, + sfd__h593166, + sfd__h602350, + sfd__h610962, + sfd__h630333, + sfd__h638915, + sfd__h648099, + sfd__h656711, + sfd__h676080, + sfd__h684662, + sfd__h693846, + sfd__h702458, + value__h719770, + value__h758623, + value__h797927; + wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10459, + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10461, + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11856, + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11858, + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9062, + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9064, + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505, + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507, + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11902, + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11904, + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9108, + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9110, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10478, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10480, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10524, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10526, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11875, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11877, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11921, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11923, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9081, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9083, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9127, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9129, + _theResult___fst_sfd__h585090, + _theResult___fst_sfd__h593672, + _theResult___fst_sfd__h602856, + _theResult___fst_sfd__h611492, + _theResult___fst_sfd__h611501, + _theResult___fst_sfd__h611507, + _theResult___fst_sfd__h630839, + _theResult___fst_sfd__h639421, + _theResult___fst_sfd__h648605, + _theResult___fst_sfd__h657241, + _theResult___fst_sfd__h657250, + _theResult___fst_sfd__h657256, + _theResult___fst_sfd__h676586, + _theResult___fst_sfd__h685168, + _theResult___fst_sfd__h694352, + _theResult___fst_sfd__h702988, + _theResult___fst_sfd__h702997, + _theResult___fst_sfd__h703003, + _theResult___sfd__h585009, + _theResult___sfd__h593591, + _theResult___sfd__h602775, + _theResult___sfd__h611411, + _theResult___sfd__h611513, + _theResult___sfd__h630758, + _theResult___sfd__h639340, + _theResult___sfd__h648524, + _theResult___sfd__h657160, + _theResult___sfd__h657262, + _theResult___sfd__h676505, + _theResult___sfd__h685087, + _theResult___sfd__h694271, + _theResult___sfd__h702907, + _theResult___sfd__h703009, + _theResult___snd_fst_sfd__h568726, + _theResult___snd_fst_sfd__h593675, + _theResult___snd_fst_sfd__h611495, + _theResult___snd_fst_sfd__h614480, + _theResult___snd_fst_sfd__h639424, + _theResult___snd_fst_sfd__h657244, + _theResult___snd_fst_sfd__h660227, + _theResult___snd_fst_sfd__h685171, + _theResult___snd_fst_sfd__h702991, + f1_sfd__h714826, + f2_sfd__h753820, + f3_sfd__h793124, + out_f_sfd__h611790, + out_f_sfd__h657539, + out_f_sfd__h703286, + out_sfd__h585012, + out_sfd__h593594, + out_sfd__h602778, + out_sfd__h611414, + out_sfd__h630761, + out_sfd__h639343, + out_sfd__h648527, + out_sfd__h657163, + out_sfd__h676508, + out_sfd__h685090, + out_sfd__h694274, + out_sfd__h702910; + wire [19 : 0] r1__read__h853711; + wire [18 : 0] INV_commitStage_commitTrap_BITS_217_TO_199__q15, + INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14, + INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13, + INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12, + INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11, + INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10, + INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8, + INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9, + INV_x83367_BITS_108_TO_90__q33, + INV_x99219_BITS_108_TO_90__q35; + wire [17 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18842, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18843, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16459, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16460, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3265, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3266, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3542, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3543, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17034, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17028, + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18847, + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16464, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3270, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3547; + wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112, + IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3524, + _theResult____h917689, + base__h239640, + base__h240797, + base__h254406, + base__h994681, + enabled_ints___1__h918214, + enabled_ints__h918260, + offset__h239641, + offset__h240798, + offset__h254407, + offset__h994682, + pend_ints__h917687, + x__h240013, + x__h241170, + x__h254779, + x__h894178, + y__h918226; + wire [13 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18628, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18629, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16245, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16246, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3051, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3052, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3408, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3409, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18635, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16252, + IF_coreFix_memExe_dispToRegQ_first__680_BIT_12_ETC___d3058, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16676, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17105, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17129, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16670, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17099, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17123, + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18633, + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16250, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3056, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3413, + b_base__h127497, + b_base__h140413, + b_base__h183674, + b_base__h202425, + b_base__h216991, + b_base__h865747, + b_base__h866295, + b_base__h904228, + b_base__h904776, + b_base__h992243, + checkForException___d20432, + checkForException___d21369, + cr_addrBits__h865333, + cr_addrBits__h865881, + cr_addrBits__h903814, + cr_addrBits__h904362, + data_addrBits__h1013046, + data_addrBits__h1013900, + pc_addrBits__h991847, + r1__read_BITS_13_TO_0___h918236, + repBoundBits__h242584, + res_addrBits__h126792, + res_addrBits__h139704, + res_addrBits__h178867, + res_addrBits__h197632, + res_addrBits__h216391, + res_addrBits__h235268, + res_addrBits__h567274, + res_addrBits__h568126, + res_addrBits__h613883, + res_addrBits__h659630, + res_addrBits__h705439, + res_addrBits__h706299, + res_addrBits__h848497, + res_addrBits__h890734, + toBoundsM1__h242588, + toBounds__h242587, + x1_avValue_new_pcc_capFat_bounds_baseBits__h997994, + x__h127470, + x__h127490, + x__h140386, + x__h140406, + x__h183647, + x__h183667, + x__h202398, + x__h202418, + x__h216964, + x__h216984, + x__h865720, + x__h865740, + x__h866268, + x__h866288, + x__h904201, + x__h904221, + x__h904749, + x__h904769, + x__h992216, + x__h992236, + x__h997991; + wire [12 : 0] IF_IF_coreFix_memExe_dTlb_procResp__239_BIT_27_ETC___d4739, + IF_NOT_renameStage_rg_m_halt_req_0072_BIT_4_00_ETC___d20765, + IF_NOT_renameStage_rg_m_halt_req_0072_BIT_4_00_ETC___d20766, + _0_CONCAT_IF_coreFix_memExe_dTlb_procResp__239__ETC___d4650, + fetchStage_pipelines_0_first__0045_BIT_180_027_ETC___d20370, + fetchStage_pipelines_1_first__0054_BIT_180_122_ETC___d21318; + wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13079, + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13794, + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14564, + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12779, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13494, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14264, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10053, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8656, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11450, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118, + _0_CONCAT_csrf_external_int_en_vec_3_read__6082_ETC___d20086, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10910, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8116, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9513, + _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12782, + _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13497, + _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14267, + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12642, + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13372, + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14142, + _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056, + _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453, + _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659, + b_top__h127496, + b_top__h140412, + b_top__h183673, + b_top__h202424, + b_top__h216990, + b_top__h865746, + b_top__h866294, + b_top__h904227, + b_top__h904775, + b_top__h992242, + capChecks___d4142, + renaming_spec_bits__h965955, + result__h913267, + result__h913318, + spec_bits__h970974, + topBits__h127399, + topBits__h140315, + topBits__h183576, + topBits__h202327, + topBits__h216893, + topBits__h865648, + topBits__h866196, + topBits__h904129, + topBits__h904677, + topBits__h992145, + w__h913262, + x__h594763, + x__h640512, + x__h686259, + x__h736295, + x__h775148, + x__h814452, + x__h913266, + x__h913317, + y__h913296, + y__h970987, + y_avValue_fst__h960364, + y_avValue_snd_fst__h960652, + y_avValue_snd_fst__h960694; + wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13189, + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13191, + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13899, + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13901, + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14669, + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14671, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13146, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13148, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13220, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13222, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13861, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13863, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13930, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13932, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14631, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14633, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14700, + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14702, + IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19881, + IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17804, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q151, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q168, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q191, + _theResult___exp__h734868, + _theResult___exp__h744519, + _theResult___exp__h753303, + _theResult___exp__h773721, + _theResult___exp__h783372, + _theResult___exp__h792156, + _theResult___exp__h813025, + _theResult___exp__h822676, + _theResult___exp__h831460, + _theResult___fst_exp__h719140, + _theResult___fst_exp__h734204, + _theResult___fst_exp__h734210, + _theResult___fst_exp__h734213, + _theResult___fst_exp__h734968, + _theResult___fst_exp__h734971, + _theResult___fst_exp__h743790, + _theResult___fst_exp__h743855, + _theResult___fst_exp__h743861, + _theResult___fst_exp__h743864, + _theResult___fst_exp__h744619, + _theResult___fst_exp__h744622, + _theResult___fst_exp__h752575, + _theResult___fst_exp__h752614, + _theResult___fst_exp__h752620, + _theResult___fst_exp__h752623, + _theResult___fst_exp__h753403, + _theResult___fst_exp__h753406, + _theResult___fst_exp__h753415, + _theResult___fst_exp__h753418, + _theResult___fst_exp__h757993, + _theResult___fst_exp__h773057, + _theResult___fst_exp__h773063, + _theResult___fst_exp__h773066, + _theResult___fst_exp__h773821, + _theResult___fst_exp__h773824, + _theResult___fst_exp__h782643, + _theResult___fst_exp__h782708, + _theResult___fst_exp__h782714, + _theResult___fst_exp__h782717, + _theResult___fst_exp__h783472, + _theResult___fst_exp__h783475, + _theResult___fst_exp__h791428, + _theResult___fst_exp__h791467, + _theResult___fst_exp__h791473, + _theResult___fst_exp__h791476, + _theResult___fst_exp__h792256, + _theResult___fst_exp__h792259, + _theResult___fst_exp__h792268, + _theResult___fst_exp__h792271, + _theResult___fst_exp__h797297, + _theResult___fst_exp__h812361, + _theResult___fst_exp__h812367, + _theResult___fst_exp__h812370, + _theResult___fst_exp__h813125, + _theResult___fst_exp__h813128, + _theResult___fst_exp__h821947, + _theResult___fst_exp__h822012, + _theResult___fst_exp__h822018, + _theResult___fst_exp__h822021, + _theResult___fst_exp__h822776, + _theResult___fst_exp__h822779, + _theResult___fst_exp__h830732, + _theResult___fst_exp__h830771, + _theResult___fst_exp__h830777, + _theResult___fst_exp__h830780, + _theResult___fst_exp__h831560, + _theResult___fst_exp__h831563, + _theResult___fst_exp__h831572, + _theResult___fst_exp__h831575, + _theResult___snd_fst_exp__h734974, + _theResult___snd_fst_exp__h753409, + _theResult___snd_fst_exp__h773827, + _theResult___snd_fst_exp__h792262, + _theResult___snd_fst_exp__h813131, + _theResult___snd_fst_exp__h831566, + coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q82, + coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q47, + coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q117, + din_inc___2_exp__h753463, + din_inc___2_exp__h753498, + din_inc___2_exp__h753524, + din_inc___2_exp__h792316, + din_inc___2_exp__h792351, + din_inc___2_exp__h792377, + din_inc___2_exp__h831620, + din_inc___2_exp__h831655, + din_inc___2_exp__h831681, + out_exp__h734871, + out_exp__h744522, + out_exp__h753306, + out_exp__h773724, + out_exp__h783375, + out_exp__h792159, + out_exp__h813028, + out_exp__h822679, + out_exp__h831463, + x__h995968; + wire [9 : 0] IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3623; + wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10374, + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11771, + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8977, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18412, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18413, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18414, + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19384, + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19385, + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19386, + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d18039, + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d18040, + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d18041, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15803, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15804, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15805, + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17306, + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17307, + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17308, + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15429, + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15430, + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15431, + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20268, + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20269, + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20270, + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21216, + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21217, + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21218; + wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11209, + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11212, + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8415, + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8418, + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9812, + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9815, + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10359, + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10361, + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11756, + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11758, + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8962, + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8964, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10034, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10036, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10428, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10430, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11431, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11433, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11825, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11827, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8637, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8639, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9031, + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9033, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q88, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q53, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q123, + _theResult___exp__h585008, + _theResult___exp__h593590, + _theResult___exp__h602774, + _theResult___exp__h611410, + _theResult___exp__h611512, + _theResult___exp__h630757, + _theResult___exp__h639339, + _theResult___exp__h648523, + _theResult___exp__h657159, + _theResult___exp__h657261, + _theResult___exp__h676504, + _theResult___exp__h685086, + _theResult___exp__h694270, + _theResult___exp__h702906, + _theResult___exp__h703008, + _theResult___fst_exp__h584492, + _theResult___fst_exp__h584557, + _theResult___fst_exp__h584563, + _theResult___fst_exp__h584566, + _theResult___fst_exp__h585089, + _theResult___fst_exp__h593139, + _theResult___fst_exp__h593145, + _theResult___fst_exp__h593148, + _theResult___fst_exp__h593671, + _theResult___fst_exp__h602258, + _theResult___fst_exp__h602323, + _theResult___fst_exp__h602329, + _theResult___fst_exp__h602332, + _theResult___fst_exp__h602855, + _theResult___fst_exp__h610895, + _theResult___fst_exp__h610934, + _theResult___fst_exp__h610940, + _theResult___fst_exp__h610943, + _theResult___fst_exp__h611491, + _theResult___fst_exp__h611500, + _theResult___fst_exp__h611503, + _theResult___fst_exp__h630241, + _theResult___fst_exp__h630306, + _theResult___fst_exp__h630312, + _theResult___fst_exp__h630315, + _theResult___fst_exp__h630838, + _theResult___fst_exp__h638888, + _theResult___fst_exp__h638894, + _theResult___fst_exp__h638897, + _theResult___fst_exp__h639420, + _theResult___fst_exp__h648007, + _theResult___fst_exp__h648072, + _theResult___fst_exp__h648078, + _theResult___fst_exp__h648081, + _theResult___fst_exp__h648604, + _theResult___fst_exp__h656644, + _theResult___fst_exp__h656683, + _theResult___fst_exp__h656689, + _theResult___fst_exp__h656692, + _theResult___fst_exp__h657240, + _theResult___fst_exp__h657249, + _theResult___fst_exp__h657252, + _theResult___fst_exp__h675988, + _theResult___fst_exp__h676053, + _theResult___fst_exp__h676059, + _theResult___fst_exp__h676062, + _theResult___fst_exp__h676585, + _theResult___fst_exp__h684635, + _theResult___fst_exp__h684641, + _theResult___fst_exp__h684644, + _theResult___fst_exp__h685167, + _theResult___fst_exp__h693754, + _theResult___fst_exp__h693819, + _theResult___fst_exp__h693825, + _theResult___fst_exp__h693828, + _theResult___fst_exp__h694351, + _theResult___fst_exp__h702391, + _theResult___fst_exp__h702430, + _theResult___fst_exp__h702436, + _theResult___fst_exp__h702439, + _theResult___fst_exp__h702987, + _theResult___fst_exp__h702996, + _theResult___fst_exp__h702999, + _theResult___snd_fst_exp__h593674, + _theResult___snd_fst_exp__h611494, + _theResult___snd_fst_exp__h639423, + _theResult___snd_fst_exp__h657243, + _theResult___snd_fst_exp__h685170, + _theResult___snd_fst_exp__h702990, + din_inc___2_exp__h611525, + din_inc___2_exp__h611549, + din_inc___2_exp__h611579, + din_inc___2_exp__h611603, + din_inc___2_exp__h657274, + din_inc___2_exp__h657298, + din_inc___2_exp__h657328, + din_inc___2_exp__h657352, + din_inc___2_exp__h703021, + din_inc___2_exp__h703045, + din_inc___2_exp__h703075, + din_inc___2_exp__h703099, + f1_exp14825_MINUS_127__q147, + f1_exp__h714825, + f2_exp53819_MINUS_127__q187, + f2_exp__h753819, + f3_exp93123_MINUS_127__q164, + f3_exp__h793123, + out_exp__h585011, + out_exp__h593593, + out_exp__h602777, + out_exp__h611413, + out_exp__h630760, + out_exp__h639342, + out_exp__h648526, + out_exp__h657162, + out_exp__h676507, + out_exp__h685089, + out_exp__h694273, + out_exp__h702909, + out_f_exp__h611789, + out_f_exp__h657538, + out_f_exp__h703285, + x__h852553; + wire [6 : 0] NOT_coreFix_aluExe_0_dispToRegQ_first__8199_BI_ETC___d19236, + NOT_coreFix_aluExe_1_dispToRegQ_first__5590_BI_ETC___d17158, + x__h244610, + x__h996694; + wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146, + IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352, + IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749, + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13028, + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13743, + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14513, + IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10300, + IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11697, + IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8903, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216, + IF_IF_mmio_cRqQ_enqReq_lat_1_whas__87_THEN_mmi_ETC___d408, + IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__2_THEN__ETC___d165, + IF_IF_mmio_pRqQ_enqReq_lat_1_whas__56_THEN_mmi_ETC___d677, + IF_INV_commitStage_commitTrap_2029_BITS_217_TO_ETC___d22341, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377, + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5053, + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21813, + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21957, + NOT_coreFix_memExe_dispToRegQ_first__680_BIT_1_ETC___d3622, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d23909, + fetchStage_pipelines_0_first__0045_BIT_167_037_ETC___d20394, + fetchStage_pipelines_1_first__0054_BIT_167_131_ETC___d21342, + x__h127310, + x__h140226, + x__h183487, + x__h202238, + x__h216804, + x__h865547, + x__h866095, + x__h904028, + x__h904576, + x__h992056, + x__h996668, + x__h997325, + x__h998012; + wire [4 : 0] IF_IF_coreFix_aluExe_0_exeToFinQ_first__9735_B_ETC___d19879, + IF_IF_coreFix_aluExe_0_exeToFinQ_first__9735_B_ETC___d19880, + IF_IF_coreFix_aluExe_1_exeToFinQ_first__7657_B_ETC___d17802, + IF_IF_coreFix_aluExe_1_exeToFinQ_first__7657_B_ETC___d17803, + IF_IF_coreFix_memExe_dTlb_procResp__239_BIT_27_ETC___d4648, + IF_IF_coreFix_memExe_dTlb_procResp__239_BIT_27_ETC___d4649, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20636, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20637, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20638, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20639, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20640, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20641, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20642, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20643, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20644, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20645, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20646, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20647, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20648, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20649, + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19580, + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19644, + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17502, + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17566, + IF_NOT_fetchStage_pipelines_0_first__0045_BITS_ETC___d21850, + IF_NOT_fetchStage_pipelines_1_first__0054_BITS_ETC___d22005, + IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23378, + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10676, + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12073, + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9279, + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891, + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932, + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976, + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705, + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102, + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308, + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874, + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915, + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959, + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10688, + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12085, + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9291, + cause_code__h993965, + coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4105, + csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4138, + fflags__h1010644, + r1__read__h854341, + res_fflags__h568166, + res_fflags__h613920, + res_fflags__h659667, + rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18981, + rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16598, + x__h148960, + x__h152094, + x__h249407, + x__h249419, + x__h249431, + x__h249443, + x__h249455, + x__h249467, + x__h249479, + x__h249491, + x__h249503, + x__h249515, + x__h249527, + x__h249539, + x__h249551, + x__h249563, + x__h249575, + y__h249408, + y__h249420, + y__h249432, + y__h249444, + y__h249456, + y__h249468, + y__h249480, + y__h249492, + y__h249504, + y__h249516, + y__h249528, + y__h249540, + y__h249552, + y__h249564, + y__h249576, + y_avValue_snd_fst__h1010122, + y_avValue_snd_fst__h1010704, + y_avValue_snd_fst__h1010733; + wire [3 : 0] IF_IF_coreFix_aluExe_0_dispToRegQ_first__8199__ETC___d19233, + IF_IF_coreFix_aluExe_1_dispToRegQ_first__5590__ETC___d17155, + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20755, + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20756, + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20757, + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20758, + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20759, + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20760, + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20761, + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20762, + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20763, + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3__ETC___d20683, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18641, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18642, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18951, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18952, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16258, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16259, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16568, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16569, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3064, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3065, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3373, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3374, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3416, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3417, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3615, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3616, + IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4914, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16698, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16692, + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20801, + IF_rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_f_ETC___d18946, + IF_rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_f_ETC___d16563, + IF_rf_read_3_rd1_coreFix_memExe_dispToRegQ_fir_ETC___d3368, + IF_rf_read_3_rd2_coreFix_memExe_dispToRegQ_fir_ETC___d3614, + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18646, + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18956, + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16263, + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16573, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3069, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3378, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3421, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3620, + vm_mode_reg__read__h853717; + wire [2 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18888, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18889, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16505, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16506, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3310, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3311, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3572, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3573, + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5072, + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5509, + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18893, + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16510, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3315, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3577, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7078, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d23842, + _theResult_____2__h515296, + dcsr_cause__h991471, + next_deqP___1__h515541, + repBound__h237262, + repBound__h238947, + repBound__h248150, + repBound__h248675, + repBound__h855893, + repBound__h859237, + repBound__h859255, + repBound__h865801, + repBound__h866349, + repBound__h895779, + repBound__h898106, + repBound__h898124, + repBound__h904282, + repBound__h904830, + repBound__h994706, + repBound__h996759, + repBound__h997416, + tb__h865798, + tb__h866346, + tb__h904279, + tb__h904827, + tmp_expBotHalf__h127265, + tmp_expBotHalf__h140181, + tmp_expBotHalf__h183442, + tmp_expBotHalf__h202193, + tmp_expBotHalf__h216759, + tmp_expBotHalf__h865501, + tmp_expBotHalf__h866049, + tmp_expBotHalf__h903982, + tmp_expBotHalf__h904530, + tmp_expBotHalf__h992011, + tmp_expTopHalf__h127263, + tmp_expTopHalf__h140179, + tmp_expTopHalf__h183440, + tmp_expTopHalf__h202191, + tmp_expTopHalf__h216757, + tmp_expTopHalf__h865499, + tmp_expTopHalf__h866047, + tmp_expTopHalf__h903980, + tmp_expTopHalf__h904528, + tmp_expTopHalf__h992009, + v__h514752, + v__h514947, + x__h521603, + x_decodeInfo_frm__h923668; + wire [1 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18829, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18830, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16446, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16447, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3252, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3253, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3534, + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3535, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17012, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17006, + IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23400, + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18834, + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16451, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3257, + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3539, + IF_sfdin02252_BIT_33_THEN_2_ELSE_0__q50, + IF_sfdin21941_BIT_4_THEN_2_ELSE_0__q167, + IF_sfdin30235_BIT_33_THEN_2_ELSE_0__q75, + IF_sfdin43784_BIT_4_THEN_2_ELSE_0__q150, + IF_sfdin48001_BIT_33_THEN_2_ELSE_0__q85, + IF_sfdin75982_BIT_33_THEN_2_ELSE_0__q110, + IF_sfdin82637_BIT_4_THEN_2_ELSE_0__q190, + IF_sfdin84486_BIT_33_THEN_2_ELSE_0__q40, + IF_sfdin93748_BIT_33_THEN_2_ELSE_0__q120, + IF_theResult___snd02385_BIT_33_THEN_2_ELSE_0__q125, + IF_theResult___snd10889_BIT_33_THEN_2_ELSE_0__q55, + IF_theResult___snd12321_BIT_4_THEN_2_ELSE_0__q163, + IF_theResult___snd30726_BIT_4_THEN_2_ELSE_0__q170, + IF_theResult___snd34164_BIT_4_THEN_2_ELSE_0__q146, + IF_theResult___snd38848_BIT_33_THEN_2_ELSE_0__q77, + IF_theResult___snd52569_BIT_4_THEN_2_ELSE_0__q153, + IF_theResult___snd56638_BIT_33_THEN_2_ELSE_0__q90, + IF_theResult___snd73017_BIT_4_THEN_2_ELSE_0__q186, + IF_theResult___snd84595_BIT_33_THEN_2_ELSE_0__q112, + IF_theResult___snd91422_BIT_4_THEN_2_ELSE_0__q193, + IF_theResult___snd93099_BIT_33_THEN_2_ELSE_0__q42, + carry_out__h127401, + carry_out__h140317, + carry_out__h183578, + carry_out__h202329, + carry_out__h216895, + carry_out__h865650, + carry_out__h866198, + carry_out__h904131, + carry_out__h904679, + carry_out__h992147, + coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q4, + coreFix_memExe_regToExeQfirst_BITS_222_TO_221__q2, + coreFix_memExe_regToExeQfirst_BITS_59_TO_58__q6, + cr_reserved__h865336, + cr_reserved__h865884, + cr_reserved__h903817, + cr_reserved__h904365, + guard__h576391, + guard__h585100, + guard__h594030, + guard__h602866, + guard__h622142, + guard__h630849, + guard__h639779, + guard__h648615, + guard__h667889, + guard__h676596, + guard__h685526, + guard__h694362, + guard__h726252, + guard__h735564, + guard__h744633, + guard__h765105, + guard__h774417, + guard__h783486, + guard__h804409, + guard__h813721, + guard__h822790, + impliedTopBits__h127403, + impliedTopBits__h140319, + impliedTopBits__h183580, + impliedTopBits__h202331, + impliedTopBits__h216897, + impliedTopBits__h865652, + impliedTopBits__h866200, + impliedTopBits__h904133, + impliedTopBits__h904681, + impliedTopBits__h992149, + len_correction__h127402, + len_correction__h140318, + len_correction__h183579, + len_correction__h202330, + len_correction__h216896, + len_correction__h865651, + len_correction__h866199, + len_correction__h904132, + len_correction__h904680, + len_correction__h992148, + prv__h1011737, + prv__h1011781, + r1__read_BITS_13_TO_12___h923870, + sbIdx__h151985, + v__h836568, + v__h836578, + v__h837213, + wordIdx__h263160, + x__h1007116, + x__h1010892, + x__h127487, + x__h140403, + x__h183664, + x__h202415, + x__h216981, + x__h865737, + x__h866285, + x__h904218, + x__h904766, + x__h992233, + y_avValue_snd_snd_snd_fst__h1010132, + y_avValue_snd_snd_snd_fst__h1010714, + y_avValue_snd_snd_snd_fst__h1010743; + wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10571, + IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10621, + IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d11968, + IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12018, + IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9174, + IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9224, + IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13072, + IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13787, + IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14055, + IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14557, + IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14824, + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20707, + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20712, + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20717, + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20722, + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20727, + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20732, + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20737, + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20742, + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20747, + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20752, + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13118, + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13833, + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14040, + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14067, + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14603, + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14809, + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14836, + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20454, + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d21429, + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d21469, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13122, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13837, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14070, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14071, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14607, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14839, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14840, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14895, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14936, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14980, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14995, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15005, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15016, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15035, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15049, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15064, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15081, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15093, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15106, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15123, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15135, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15148, + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7231, + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7239, + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7248, + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7322, + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7331, + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7482, + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7490, + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7501, + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7566, + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7574, + IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7852, + IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7860, + IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7870, + IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7770, + IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7778, + IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7788, + IF_INV_commitStage_commitTrap_2029_BITS_217_TO_ETC___d22422, + IF_INV_commitStage_commitTrap_2029_BITS_217_TO_ETC___d22424, + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19567, + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19568, + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19570, + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19631, + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19632, + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19634, + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17489, + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17490, + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17492, + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17553, + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17554, + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17556, + IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12777, + IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13492, + IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14262, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18254, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18255, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18256, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18279, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18280, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18281, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18559, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18560, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18654, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18655, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18667, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18668, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18680, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18681, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18693, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18694, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18706, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18707, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18719, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18720, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18732, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18733, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18745, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18746, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18758, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18759, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18771, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18772, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18784, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18785, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18797, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18798, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18816, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18817, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18857, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18858, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18902, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18903, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18915, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18916, + 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NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21675, + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21775, + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21777, + NOT_fetchStage_pipelines_0_first__0045_BIT_69__ETC___d20504, + NOT_fetchStage_pipelines_0_first__0045_BIT_69__ETC___d20784, + NOT_fetchStage_pipelines_0_first__0045_BIT_69__ETC___d21008, + NOT_fetchStage_pipelines_1_canDeq__0051_0052_O_ETC___d20060, + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21031, + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21410, + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21533, + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21891, + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21893, + NOT_fetchStage_pipelines_1_first__0054_BIT_69__ETC___d21888, + NOT_mmio_dataPendQ_empty_80_378_AND_rob_RDY_se_ETC___d1379, + NOT_mmio_dataPendQ_empty_80_378_AND_rob_RDY_se_ETC___d2026, + NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21434, + NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21514, + NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21870, + NOT_regRenamingTable_rename_1_canRename__1062__ETC___d21477, + NOT_renameStage_rg_m_halt_req_0072_BIT_4_0073__ETC___d20956, + NOT_renameStage_rg_m_halt_req_0072_BIT_4_0073__ETC___d21407, + NOT_renameStage_rg_m_halt_req_0072_BIT_4_0073__ETC___d21555, + NOT_renameStage_rg_m_halt_req_0072_BIT_4_0073__ETC___d21574, + NOT_rob_deqPort_0_canDeq__3151_3152_OR_regRena_ETC___d23192, + NOT_rob_deqPort_0_canDeq__3151_3152_OR_rob_deq_ETC___d23371, + NOT_rob_deqPort_0_deq_data__2022_BITS_469_TO_4_ETC___d22795, + NOT_rob_deqPort_1_deq_data__3158_BIT_25_3159_3_ETC___d23189, + NOT_specTagManager_canClaim__0927_1023_OR_NOT__ETC___d21685, + NOT_specTagManager_canClaim__0927_1023_OR_NOT__ETC___d21752, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452, + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11148, + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8354, + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9751, + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13030, + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13745, + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14515, + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10302, + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11699, + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8905, + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12718, + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13080, + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13448, + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13795, + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14218, + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14565, + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10375, + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11379, + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11772, + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8585, + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8978, + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9982, + _0_CONCAT_csrf_mtcc_reg_read__6624_BITS_149_TO__ETC___d22604, + _0_CONCAT_csrf_mtcc_reg_read__6624_BITS_149_TO__ETC___d22630, + _0_CONCAT_csrf_stcc_reg_read__6615_BITS_149_TO__ETC___d22529, + _0_CONCAT_csrf_stcc_reg_read__6615_BITS_149_TO__ETC___d22555, + _0_OR_NOT_fetchStage_pipelines_0_first__0045_BI_ETC___d21606, + _0_OR_NOT_fetchStage_pipelines_1_first__0054_BI_ETC___d21506, + _0_OR_NOT_fetchStage_pipelines_1_first__0054_BI_ETC___d21698, + _0b0_CONCAT_csrf_medeleg_15_reg_read__6063_6064_ETC___d22403, + _0b0_CONCAT_csrf_mideleg_11_reg_read__6071_6072_ETC___d22405, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10691, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10716, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10743, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d12088, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d12113, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d12140, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9294, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9319, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9346, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514, + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515, + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643, + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645, + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373, + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375, + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143, + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145, _dfoo12, + _dfoo14, + _dfoo16, _dfoo18, _dfoo2, _dfoo20, - _dfoo28, + _dfoo24, + _dfoo26, + _dfoo32, _dfoo7, _dor1coreFix_aluExe_0_bypassWire_2$EN_wset, _dor1coreFix_aluExe_0_bypassWire_3$EN_wset, @@ -5885,12 +6538,7 @@ module mkCore(CLK, _dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put, _dor1coreFix_memExe_bypassWire_2$EN_wset, _dor1coreFix_memExe_bypassWire_3$EN_wset, - _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write, - _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write, - _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write, _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset, - _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write, - _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write, _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset, _dor1coreFix_memExe_rsMem$EN_setRegReady_3_put, _dor1rf$EN_write_0_wr, @@ -5898,201 +6546,519 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h301737, - _theResult_____2__h307731, - _theResult_____2__h315585, - _theResult_____2__h325929, - _theResult_____2__h329154, - coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101, - coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12140, - coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12114, - coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12146, - coreFix_aluExe_0_bypassWire_2_wget__2120_BITS__ETC___d12122, - coreFix_aluExe_0_bypassWire_2_wget__2120_BITS__ETC___d12150, - coreFix_aluExe_0_dispToRegQ_first__2078_BIT_13_ETC___d12163, - coreFix_aluExe_0_exeToFinQ_RDY_first__2490_AND_ETC___d12528, - coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223, - coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11306, - coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11345, - coreFix_aluExe_1_bypassWire_1_wget__1317_BITS__ETC___d11319, - coreFix_aluExe_1_bypassWire_1_wget__1317_BITS__ETC___d11351, - coreFix_aluExe_1_bypassWire_2_wget__1325_BITS__ETC___d11327, - coreFix_aluExe_1_bypassWire_2_wget__1325_BITS__ETC___d11355, - coreFix_aluExe_1_dispToRegQ_first__1283_BIT_13_ETC___d11368, - coreFix_aluExe_1_exeToFinQ_RDY_first__1881_AND_ETC___d11920, - coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206, - coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244, - coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268, - coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8219, - coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8250, - coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8274, - coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8227, - coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8254, - coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8278, - coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5268, - coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3876, - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6660, - coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_fir_ETC___d8098, - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8101, - coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8052, - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10830, - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10866, - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10914, - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10956, - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10998, - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__36_ETC___d13767, - coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570, - coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608, - coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583, - coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614, - coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591, - coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618, - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2573, - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063, - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3166, - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2066, - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146, - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2723, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2527, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2556, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2561, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2578, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2595, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2615, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2639, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2645, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2647, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693, - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2806, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840, - 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coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6700, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6703, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6706, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6709, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6712, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6715, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6718, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6721, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6724, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6727, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6730, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6733, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6736, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6739, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6742, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6745, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6748, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6751, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6754, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6940, + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6943, + coreFix_memExe_dTlb_procResp__239_BITS_141_TO__ETC___d4529, + coreFix_memExe_dTlb_procResp__239_BITS_141_TO__ETC___d4570, + coreFix_memExe_dTlb_procResp__239_BITS_334_TO__ETC___d4402, + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4539, + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4540, + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4544, + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4547, + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548, + coreFix_memExe_dTlb_procResp__239_BITS_77_TO_1_ETC___d4531, + coreFix_memExe_dTlb_procResp__239_BITS_77_TO_1_ETC___d4532, + coreFix_memExe_regToExeQ_first__633_BITS_101_T_ETC___d3767, + coreFix_memExe_regToExeQ_first__633_BITS_244_T_ETC___d4093, + coreFix_memExe_regToExeQ_first__633_BITS_258_T_ETC___d4092, + coreFix_memExe_regToExeQ_first__633_BITS_264_T_ETC___d3705, + coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4095, + coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d22800, + cr_flags__h865335, + cr_flags__h865883, + cr_flags__h903816, + cr_flags__h904364, + csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126, + csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125, + csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4128, + csrf_fs_reg_read__5969_EQ_0_0418_AND_fetchStag_ETC___d20452, + csrf_fs_reg_read__5969_EQ_0_0418_AND_fetchStag_ETC___d21034, + csrf_fs_reg_read__5969_EQ_0_0418_AND_fetchStag_ETC___d21467, + csrf_mtcc_reg_read__6624_BITS_149_TO_86_2579_A_ETC___d22589, + csrf_mtcc_reg_read__6624_BITS_149_TO_86_2579_A_ETC___d22622, + csrf_mtcc_reg_read__6624_BITS_85_TO_83_2597_UL_ETC___d22600, + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408, + csrf_prv_reg_read__0075_ULE_1___d22375, + csrf_rg_dcsr_read__6184_BIT_2_0464_OR_NOT_fetc_ETC___d21029, + csrf_stcc_reg_read__6615_BITS_149_TO_86_2502_A_ETC___d22514, + csrf_stcc_reg_read__6615_BITS_149_TO_86_2502_A_ETC___d22547, + csrf_stcc_reg_read__6615_BITS_85_TO_83_2522_UL_ETC___d22525, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d21405, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d21553, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d21572, + f_csr_rsps_i_notFull__3520_AND_f_csr_reqs_firs_ETC___d23615, + fetchStage_RDY_pipelines_0_deq__0048_AND_regRe_ETC___d20817, + fetchStage_pipelines_0_canDeq__0043_AND_NOT_fe_ETC___d21696, + fetchStage_pipelines_0_canDeq__0043_AND_NOT_fe_ETC___d21862, + fetchStage_pipelines_0_canDeq__0043_AND_fetchS_ETC___d21766, + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21702, + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21709, + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21731, + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21743, + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21993, + fetchStage_pipelines_0_canDeq__0043_AND_specTa_ETC___d21836, + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21418, + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21424, + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21442, + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21634, + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21640, + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21657, + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21692, + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21872, + fetchStage_pipelines_0_first__0045_BITS_272_TO_ETC___d21041, + fetchStage_pipelines_0_first__0045_BIT_69_0074_ETC___d20559, + fetchStage_pipelines_0_first__0045_BIT_69_0074_ETC___d21512, + fetchStage_pipelines_1_first__0054_BITS_267_TO_ETC___d21651, + fetchStage_pipelines_1_first__0054_BITS_267_TO_ETC___d21937, + fetchStage_pipelines_1_first__0054_BITS_272_TO_ETC___d21663, + guard__h594628, + guard__h640377, + guard__h686124, + guard__h736162, + guard__h775015, + guard__h814319, + idx__h966094, + k__h942381, + mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20457, + mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20849, + mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20869, + mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21770, + mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21772, + next_deqP___1__h526318, + next_deqP___1__h533596, + next_deqP___1__h544231, + next_deqP___1__h557879, + next_deqP___1__h561658, + r1__read_BIT_20___h924376, + r__h852600, + r__h854087, + regRenamingTable_RDY_rename_0_getRename__0805__ETC___d21619, + regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958, + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21010, + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21024, + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21500, + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21648, + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21790, + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21797, + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21821, + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21830, + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21991, + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21409, + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21557, + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21576, + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21890, + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21432, + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21475, + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21517, + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21598, + rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18897, + rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18910, + rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18924, + rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18968, + rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18969, + rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18971, + rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16514, + rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16527, + rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16541, + rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16585, + rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16586, + rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16588, + rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3319, + rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3332, + rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3346, + rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3580, + rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3588, + rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3597, + rg_core_run_state_read__0460_EQ_2_0461_AND_NOT_ETC___d23446, + rob_RDY_enqPort_1_enq__1748_AND_NOT_fetchStage_ETC___d21756, + sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12424, + sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12425, + sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d2762, + v__h516772, + v__h517152, + v__h532491, + v__h532686, + v__h534940, + v__h535135, + v__h555960, + v__h556155, + v__h559739, + v__h559934, + x__h240082, + x__h241239, + x__h254848, + x__h836069; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -6130,10 +7096,10 @@ module mkCore(CLK, // value method dCacheToParent_rsToP_first assign dCacheToParent_rsToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14864 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d23883 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6151,9 +7117,9 @@ module mkCore(CLK, // value method dCacheToParent_rqToP_first assign dCacheToParent_rqToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14890 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q316, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d23909 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -6250,9 +7216,9 @@ module mkCore(CLK, // value method mmioToPlatform_cRq_first assign mmioToPlatform_cRq_first = - { mmio_cRqQ_data_0[141:78], - CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, - mmio_cRqQ_data_0[71:0] } ; + { mmio_cRqQ_data_0[214:151], + CASE_mmio_cRqQ_data_0_BITS_150_TO_149_0_mmio_c_ETC__q1, + mmio_cRqQ_data_0[144:0] } ; assign RDY_mmioToPlatform_cRq_first = !mmio_cRqQ_empty ; // value method mmioToPlatform_pRs_notFull @@ -6350,7 +7316,7 @@ module mkCore(CLK, // actionvalue method deadlock_commitInstStuck_get assign deadlock_commitInstStuck_get = - 163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; + 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign RDY_deadlock_commitInstStuck_get = 1'd0 ; assign CAN_FIRE_deadlock_commitInstStuck_get = 1'd0 ; assign WILL_FIRE_deadlock_commitInstStuck_get = @@ -6358,7 +7324,7 @@ module mkCore(CLK, // actionvalue method deadlock_commitUserInstStuck_get assign deadlock_commitUserInstStuck_get = - 163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; + 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign RDY_deadlock_commitUserInstStuck_get = 1'd0 ; assign CAN_FIRE_deadlock_commitUserInstStuck_get = 1'd0 ; assign WILL_FIRE_deadlock_commitUserInstStuck_get = @@ -6370,7 +7336,7 @@ module mkCore(CLK, assign WILL_FIRE_deadlock_checkStarted_get = EN_deadlock_checkStarted_get ; // actionvalue method renameDebug_renameErr_get - assign renameDebug_renameErr_get = 89'h0AAAAAAAAAAAAAAAAAAAAAA ; + assign renameDebug_renameErr_get = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA ; assign RDY_renameDebug_renameErr_get = 1'd0 ; assign CAN_FIRE_renameDebug_renameErr_get = 1'd0 ; assign WILL_FIRE_renameDebug_renameErr_get = EN_renameDebug_renameErr_get ; @@ -6385,10 +7351,58 @@ module mkCore(CLK, assign CAN_FIRE_setSEIP = 1'd1 ; assign WILL_FIRE_setSEIP = EN_setSEIP ; - // action method setDEIP - assign RDY_setDEIP = 1'd1 ; - assign CAN_FIRE_setDEIP = 1'd1 ; - assign WILL_FIRE_setDEIP = EN_setDEIP ; + // action method hart0_run_halt_server_request_put + assign RDY_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ; + assign CAN_FIRE_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ; + assign WILL_FIRE_hart0_run_halt_server_request_put = + EN_hart0_run_halt_server_request_put ; + + // actionvalue method hart0_run_halt_server_response_get + assign hart0_run_halt_server_response_get = f_run_halt_rsps$D_OUT ; + assign RDY_hart0_run_halt_server_response_get = f_run_halt_rsps$EMPTY_N ; + assign CAN_FIRE_hart0_run_halt_server_response_get = + f_run_halt_rsps$EMPTY_N ; + assign WILL_FIRE_hart0_run_halt_server_response_get = + EN_hart0_run_halt_server_response_get ; + + // action method hart0_gpr_mem_server_request_put + assign RDY_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ; + assign CAN_FIRE_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ; + assign WILL_FIRE_hart0_gpr_mem_server_request_put = + EN_hart0_gpr_mem_server_request_put ; + + // actionvalue method hart0_gpr_mem_server_response_get + assign hart0_gpr_mem_server_response_get = f_gpr_rsps$D_OUT ; + assign RDY_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ; + assign CAN_FIRE_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ; + assign WILL_FIRE_hart0_gpr_mem_server_response_get = + EN_hart0_gpr_mem_server_response_get ; + + // action method hart0_fpr_mem_server_request_put + assign RDY_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ; + assign CAN_FIRE_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ; + assign WILL_FIRE_hart0_fpr_mem_server_request_put = + EN_hart0_fpr_mem_server_request_put ; + + // actionvalue method hart0_fpr_mem_server_response_get + assign hart0_fpr_mem_server_response_get = f_fpr_rsps$D_OUT ; + assign RDY_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ; + assign CAN_FIRE_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ; + assign WILL_FIRE_hart0_fpr_mem_server_response_get = + EN_hart0_fpr_mem_server_response_get ; + + // action method hart0_csr_mem_server_request_put + assign RDY_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ; + assign CAN_FIRE_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ; + assign WILL_FIRE_hart0_csr_mem_server_request_put = + EN_hart0_csr_mem_server_request_put ; + + // actionvalue method hart0_csr_mem_server_response_get + assign hart0_csr_mem_server_response_get = f_csr_rsps$D_OUT ; + assign RDY_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ; + assign CAN_FIRE_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ; + assign WILL_FIRE_hart0_csr_mem_server_response_get = + EN_hart0_csr_mem_server_response_get ; // submodule coreFix_aluExe_0_dispToRegQ mkAluDispToRegFifo coreFix_aluExe_0_dispToRegQ(.CLK(CLK), @@ -6928,132 +7942,6 @@ module mkCore(CLK, .stuck_get(), .RDY_stuck_get()); - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT)); - // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr mkDPRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_pRqMshr(.CLK(CLK), .RST_N(RST_N), @@ -7101,90 +7989,6 @@ module mkCore(CLK, .RDY_first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first), .RDY_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite)); - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT)); - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ SizedFIFO #(.p1width(32'd3), .p2depth(32'd8), @@ -7223,62 +8027,6 @@ module mkCore(CLK, .FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N), .EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N)); - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT)); - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ SizedFIFO #(.p1width(32'd4), .p2depth(32'd12), @@ -7293,118 +8041,6 @@ module mkCore(CLK, .FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N), .EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N)); - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN), - .Q_OUT(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT)); - // submodule coreFix_memExe_dTlb mkDTlbSynth coreFix_memExe_dTlb(.CLK(CLK), .RST_N(RST_N), @@ -7476,62 +8112,6 @@ module mkCore(CLK, .RDY_specUpdate_incorrectSpeculation(), .RDY_specUpdate_correctSpeculation()); - // submodule coreFix_memExe_forwardQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN), - .EN(coreFix_memExe_forwardQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_forwardQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN), - .EN(coreFix_memExe_forwardQ_clearReq_dummy2_1$EN), - .Q_OUT(coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_forwardQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_forwardQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_forwardQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_forwardQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_forwardQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_forwardQ_deqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_forwardQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_forwardQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_forwardQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_forwardQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_forwardQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_forwardQ_enqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT)); - // submodule coreFix_memExe_lsq mkSplitLSQ coreFix_memExe_lsq(.CLK(CLK), .RST_N(RST_N), @@ -7615,65 +8195,9 @@ module mkCore(CLK, .RDY_stqFull_ehrPort0(), .ldqFull_ehrPort0(), .RDY_ldqFull_ehrPort0(), - .noWrongPathLoads(), + .noWrongPathLoads(coreFix_memExe_lsq$noWrongPathLoads), .RDY_noWrongPathLoads()); - // submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN), - .EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN), - .EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN), - .Q_OUT(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT)); - // submodule coreFix_memExe_regToExeQ mkMemRegToExeFifo coreFix_memExe_regToExeQ(.CLK(CLK), .RST_N(RST_N), @@ -7692,314 +8216,6 @@ module mkCore(CLK, .RDY_specUpdate_incorrectSpeculation(), .RDY_specUpdate_correctSpeculation()); - // submodule coreFix_memExe_reqLdQ_data_0_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN), - .EN(coreFix_memExe_reqLdQ_data_0_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqLdQ_data_0_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN), - .EN(coreFix_memExe_reqLdQ_data_0_dummy2_1$EN), - .Q_OUT(coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_reqLdQ_deqP_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN), - .EN(coreFix_memExe_reqLdQ_deqP_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqLdQ_deqP_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN), - .EN(coreFix_memExe_reqLdQ_deqP_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqLdQ_empty_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN), - .EN(coreFix_memExe_reqLdQ_empty_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqLdQ_empty_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN), - .EN(coreFix_memExe_reqLdQ_empty_dummy2_1$EN), - .Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_reqLdQ_empty_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN), - .EN(coreFix_memExe_reqLdQ_empty_dummy2_2$EN), - .Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_reqLdQ_enqP_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN), - .EN(coreFix_memExe_reqLdQ_enqP_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqLdQ_enqP_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN), - .EN(coreFix_memExe_reqLdQ_enqP_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqLdQ_full_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqLdQ_full_dummy2_0$D_IN), - .EN(coreFix_memExe_reqLdQ_full_dummy2_0$EN), - .Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT)); - - // submodule coreFix_memExe_reqLdQ_full_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqLdQ_full_dummy2_1$D_IN), - .EN(coreFix_memExe_reqLdQ_full_dummy2_1$EN), - .Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_reqLdQ_full_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_reqLdQ_full_dummy2_2$D_IN), - .EN(coreFix_memExe_reqLdQ_full_dummy2_2$EN), - .Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN), - .EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN), - .EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN), - .Q_OUT(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN), - .EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN), - .EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN), - .EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN), - .EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN), - .Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN), - .EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN), - .Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN), - .EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN), - .EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN), - .EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN), - .Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT)); - - // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN), - .EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN), - .Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN), - .EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN), - .Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_reqStQ_data_0_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN), - .EN(coreFix_memExe_reqStQ_data_0_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqStQ_data_0_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN), - .EN(coreFix_memExe_reqStQ_data_0_dummy2_1$EN), - .Q_OUT(coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_reqStQ_deqP_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN), - .EN(coreFix_memExe_reqStQ_deqP_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqStQ_deqP_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN), - .EN(coreFix_memExe_reqStQ_deqP_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqStQ_empty_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqStQ_empty_dummy2_0$D_IN), - .EN(coreFix_memExe_reqStQ_empty_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqStQ_empty_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqStQ_empty_dummy2_1$D_IN), - .EN(coreFix_memExe_reqStQ_empty_dummy2_1$EN), - .Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_reqStQ_empty_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_reqStQ_empty_dummy2_2$D_IN), - .EN(coreFix_memExe_reqStQ_empty_dummy2_2$EN), - .Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_reqStQ_enqP_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN), - .EN(coreFix_memExe_reqStQ_enqP_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqStQ_enqP_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN), - .EN(coreFix_memExe_reqStQ_enqP_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_reqStQ_full_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_reqStQ_full_dummy2_0$D_IN), - .EN(coreFix_memExe_reqStQ_full_dummy2_0$EN), - .Q_OUT(coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT)); - - // submodule coreFix_memExe_reqStQ_full_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_reqStQ_full_dummy2_1$D_IN), - .EN(coreFix_memExe_reqStQ_full_dummy2_1$EN), - .Q_OUT(coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_reqStQ_full_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_reqStQ_full_dummy2_2$D_IN), - .EN(coreFix_memExe_reqStQ_full_dummy2_2$EN), - .Q_OUT(coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN), - .EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN), - .EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN), - .Q_OUT(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT)); - - // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT)); - - // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN), - .EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN), - .EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN), - .EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN), - .Q_OUT(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT)); - // submodule coreFix_memExe_rsMem mkReservationStationMem coreFix_memExe_rsMem(.CLK(CLK), .RST_N(RST_N), @@ -8077,7 +8293,7 @@ module mkCore(CLK, .RDY_noMatchStQ()); // submodule coreFix_trainBPQ_0 - FIFO2 #(.width(32'd159), .guarded(32'd1)) coreFix_trainBPQ_0(.RST(RST_N), + FIFO2 #(.width(32'd290), .guarded(32'd1)) coreFix_trainBPQ_0(.RST(RST_N), .CLK(CLK), .D_IN(coreFix_trainBPQ_0$D_IN), .ENQ(coreFix_trainBPQ_0$ENQ), @@ -8088,7 +8304,7 @@ module mkCore(CLK, .EMPTY_N(coreFix_trainBPQ_0$EMPTY_N)); // submodule coreFix_trainBPQ_1 - FIFO2 #(.width(32'd159), .guarded(32'd1)) coreFix_trainBPQ_1(.RST(RST_N), + FIFO2 #(.width(32'd290), .guarded(32'd1)) coreFix_trainBPQ_1(.RST(RST_N), .CLK(CLK), .D_IN(coreFix_trainBPQ_1$D_IN), .ENQ(coreFix_trainBPQ_1$ENQ), @@ -8098,48 +8314,6 @@ module mkCore(CLK, .FULL_N(coreFix_trainBPQ_1$FULL_N), .EMPTY_N(coreFix_trainBPQ_1$EMPTY_N)); - // submodule csrInstOrInterruptInflight_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) csrInstOrInterruptInflight_dummy2_0(.CLK(CLK), - .D_IN(csrInstOrInterruptInflight_dummy2_0$D_IN), - .EN(csrInstOrInterruptInflight_dummy2_0$EN), - .Q_OUT(csrInstOrInterruptInflight_dummy2_0$Q_OUT)); - - // submodule csrInstOrInterruptInflight_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) csrInstOrInterruptInflight_dummy2_1(.CLK(CLK), - .D_IN(csrInstOrInterruptInflight_dummy2_1$D_IN), - .EN(csrInstOrInterruptInflight_dummy2_1$EN), - .Q_OUT(csrInstOrInterruptInflight_dummy2_1$Q_OUT)); - - // submodule csrf_mcycle_ehr_data_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) csrf_mcycle_ehr_data_dummy2_0(.CLK(CLK), - .D_IN(csrf_mcycle_ehr_data_dummy2_0$D_IN), - .EN(csrf_mcycle_ehr_data_dummy2_0$EN), - .Q_OUT(csrf_mcycle_ehr_data_dummy2_0$Q_OUT)); - - // submodule csrf_mcycle_ehr_data_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) csrf_mcycle_ehr_data_dummy2_1(.CLK(CLK), - .D_IN(csrf_mcycle_ehr_data_dummy2_1$D_IN), - .EN(csrf_mcycle_ehr_data_dummy2_1$EN), - .Q_OUT(csrf_mcycle_ehr_data_dummy2_1$Q_OUT)); - - // submodule csrf_minstret_ehr_data_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) csrf_minstret_ehr_data_dummy2_0(.CLK(CLK), - .D_IN(csrf_minstret_ehr_data_dummy2_0$D_IN), - .EN(csrf_minstret_ehr_data_dummy2_0$EN), - .Q_OUT(csrf_minstret_ehr_data_dummy2_0$Q_OUT)); - - // submodule csrf_minstret_ehr_data_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) csrf_minstret_ehr_data_dummy2_1(.CLK(CLK), - .D_IN(csrf_minstret_ehr_data_dummy2_1$D_IN), - .EN(csrf_minstret_ehr_data_dummy2_1$EN), - .Q_OUT(csrf_minstret_ehr_data_dummy2_1$Q_OUT)); - // submodule csrf_stats_module_writeQ FIFO1 #(.width(32'd1), .guarded(32'd1)) csrf_stats_module_writeQ(.RST(RST_N), @@ -8185,6 +8359,94 @@ module mkCore(CLK, .isFull_ehrPort0(), .RDY_isFull_ehrPort0()); + // submodule f_csr_reqs + FIFO1 #(.width(32'd77), .guarded(32'd1)) f_csr_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(f_csr_reqs$D_IN), + .ENQ(f_csr_reqs$ENQ), + .DEQ(f_csr_reqs$DEQ), + .CLR(f_csr_reqs$CLR), + .D_OUT(f_csr_reqs$D_OUT), + .FULL_N(f_csr_reqs$FULL_N), + .EMPTY_N(f_csr_reqs$EMPTY_N)); + + // submodule f_csr_rsps + FIFO1 #(.width(32'd65), .guarded(32'd1)) f_csr_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(f_csr_rsps$D_IN), + .ENQ(f_csr_rsps$ENQ), + .DEQ(f_csr_rsps$DEQ), + .CLR(f_csr_rsps$CLR), + .D_OUT(f_csr_rsps$D_OUT), + .FULL_N(f_csr_rsps$FULL_N), + .EMPTY_N(f_csr_rsps$EMPTY_N)); + + // submodule f_fpr_reqs + FIFO1 #(.width(32'd70), .guarded(32'd1)) f_fpr_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(f_fpr_reqs$D_IN), + .ENQ(f_fpr_reqs$ENQ), + .DEQ(f_fpr_reqs$DEQ), + .CLR(f_fpr_reqs$CLR), + .D_OUT(f_fpr_reqs$D_OUT), + .FULL_N(f_fpr_reqs$FULL_N), + .EMPTY_N(f_fpr_reqs$EMPTY_N)); + + // submodule f_fpr_rsps + FIFO1 #(.width(32'd65), .guarded(32'd1)) f_fpr_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(f_fpr_rsps$D_IN), + .ENQ(f_fpr_rsps$ENQ), + .DEQ(f_fpr_rsps$DEQ), + .CLR(f_fpr_rsps$CLR), + .D_OUT(f_fpr_rsps$D_OUT), + .FULL_N(f_fpr_rsps$FULL_N), + .EMPTY_N(f_fpr_rsps$EMPTY_N)); + + // submodule f_gpr_reqs + FIFO1 #(.width(32'd70), .guarded(32'd1)) f_gpr_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(f_gpr_reqs$D_IN), + .ENQ(f_gpr_reqs$ENQ), + .DEQ(f_gpr_reqs$DEQ), + .CLR(f_gpr_reqs$CLR), + .D_OUT(f_gpr_reqs$D_OUT), + .FULL_N(f_gpr_reqs$FULL_N), + .EMPTY_N(f_gpr_reqs$EMPTY_N)); + + // submodule f_gpr_rsps + FIFO1 #(.width(32'd65), .guarded(32'd1)) f_gpr_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(f_gpr_rsps$D_IN), + .ENQ(f_gpr_rsps$ENQ), + .DEQ(f_gpr_rsps$DEQ), + .CLR(f_gpr_rsps$CLR), + .D_OUT(f_gpr_rsps$D_OUT), + .FULL_N(f_gpr_rsps$FULL_N), + .EMPTY_N(f_gpr_rsps$EMPTY_N)); + + // submodule f_run_halt_reqs + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(f_run_halt_reqs$D_IN), + .ENQ(f_run_halt_reqs$ENQ), + .DEQ(f_run_halt_reqs$DEQ), + .CLR(f_run_halt_reqs$CLR), + .D_OUT(f_run_halt_reqs$D_OUT), + .FULL_N(f_run_halt_reqs$FULL_N), + .EMPTY_N(f_run_halt_reqs$EMPTY_N)); + + // submodule f_run_halt_rsps + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(f_run_halt_rsps$D_IN), + .ENQ(f_run_halt_rsps$ENQ), + .DEQ(f_run_halt_rsps$DEQ), + .CLR(f_run_halt_rsps$CLR), + .D_OUT(f_run_halt_rsps$D_OUT), + .FULL_N(f_run_halt_rsps$FULL_N), + .EMPTY_N(f_run_halt_rsps$EMPTY_N)); + // submodule fetchStage mkFetchStage fetchStage(.CLK(CLK), .RST_N(RST_N), @@ -8206,6 +8468,7 @@ module mkCore(CLK, .start_pc(fetchStage$start_pc), .train_predictors_dpTrain(fetchStage$train_predictors_dpTrain), .train_predictors_iType(fetchStage$train_predictors_iType), + .train_predictors_isCompressed(fetchStage$train_predictors_isCompressed), .train_predictors_mispred(fetchStage$train_predictors_mispred), .train_predictors_next_pc(fetchStage$train_predictors_next_pc), .train_predictors_pc(fetchStage$train_predictors_pc), @@ -8241,6 +8504,7 @@ module mkCore(CLK, .EN_stop(fetchStage$EN_stop), .EN_setWaitRedirect(fetchStage$EN_setWaitRedirect), .EN_redirect(fetchStage$EN_redirect), + .EN_setWaitFlush(fetchStage$EN_setWaitFlush), .EN_done_flushing(fetchStage$EN_done_flushing), .EN_train_predictors(fetchStage$EN_train_predictors), .EN_flush_predictors(fetchStage$EN_flush_predictors), @@ -8286,7 +8550,7 @@ module mkCore(CLK, .iMemIfc_to_proc_response_get(), .RDY_iMemIfc_to_proc_response_get(), .RDY_iMemIfc_flush(), - .iMemIfc_flush_done(), + .iMemIfc_flush_done(fetchStage$iMemIfc_flush_done), .RDY_iMemIfc_flush_done(), .RDY_iMemIfc_perf_setStatus(), .RDY_iMemIfc_perf_req(), @@ -8326,12 +8590,13 @@ module mkCore(CLK, .RDY_stop(), .RDY_setWaitRedirect(), .RDY_redirect(), + .RDY_setWaitFlush(), .RDY_done_flushing(fetchStage$RDY_done_flushing), .RDY_train_predictors(), - .emptyForFlush(), + .emptyForFlush(fetchStage$emptyForFlush), .RDY_emptyForFlush(), .RDY_flush_predictors(), - .flush_predictors_done(), + .flush_predictors_done(fetchStage$flush_predictors_done), .RDY_flush_predictors_done(), .getFetchState(), .RDY_getFetchState(), @@ -8387,374 +8652,6 @@ module mkCore(CLK, .perf_respValid(), .RDY_perf_respValid()); - // submodule mmio_cRqQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_cRqQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_cRqQ_clearReq_dummy2_0$D_IN), - .EN(mmio_cRqQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_cRqQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_cRqQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_cRqQ_clearReq_dummy2_1$D_IN), - .EN(mmio_cRqQ_clearReq_dummy2_1$EN), - .Q_OUT(mmio_cRqQ_clearReq_dummy2_1$Q_OUT)); - - // submodule mmio_cRqQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_cRqQ_deqReq_dummy2_0$D_IN), - .EN(mmio_cRqQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_cRqQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_cRqQ_deqReq_dummy2_1$D_IN), - .EN(mmio_cRqQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_cRqQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_cRqQ_deqReq_dummy2_2$D_IN), - .EN(mmio_cRqQ_deqReq_dummy2_2$EN), - .Q_OUT(mmio_cRqQ_deqReq_dummy2_2$Q_OUT)); - - // submodule mmio_cRqQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_cRqQ_enqReq_dummy2_0$D_IN), - .EN(mmio_cRqQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_cRqQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_cRqQ_enqReq_dummy2_1$D_IN), - .EN(mmio_cRqQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_cRqQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_cRqQ_enqReq_dummy2_2$D_IN), - .EN(mmio_cRqQ_enqReq_dummy2_2$EN), - .Q_OUT(mmio_cRqQ_enqReq_dummy2_2$Q_OUT)); - - // submodule mmio_cRsQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_cRsQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_cRsQ_clearReq_dummy2_0$D_IN), - .EN(mmio_cRsQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_cRsQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_cRsQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_cRsQ_clearReq_dummy2_1$D_IN), - .EN(mmio_cRsQ_clearReq_dummy2_1$EN), - .Q_OUT(mmio_cRsQ_clearReq_dummy2_1$Q_OUT)); - - // submodule mmio_cRsQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_cRsQ_deqReq_dummy2_0$D_IN), - .EN(mmio_cRsQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_cRsQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_cRsQ_deqReq_dummy2_1$D_IN), - .EN(mmio_cRsQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_cRsQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_cRsQ_deqReq_dummy2_2$D_IN), - .EN(mmio_cRsQ_deqReq_dummy2_2$EN), - .Q_OUT(mmio_cRsQ_deqReq_dummy2_2$Q_OUT)); - - // submodule mmio_cRsQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_cRsQ_enqReq_dummy2_0$D_IN), - .EN(mmio_cRsQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_cRsQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_cRsQ_enqReq_dummy2_1$D_IN), - .EN(mmio_cRsQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_cRsQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_cRsQ_enqReq_dummy2_2$D_IN), - .EN(mmio_cRsQ_enqReq_dummy2_2$EN), - .Q_OUT(mmio_cRsQ_enqReq_dummy2_2$Q_OUT)); - - // submodule mmio_dataPendQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataPendQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_dataPendQ_clearReq_dummy2_0$D_IN), - .EN(mmio_dataPendQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_dataPendQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataPendQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_dataPendQ_clearReq_dummy2_1$D_IN), - .EN(mmio_dataPendQ_clearReq_dummy2_1$EN), - .Q_OUT(mmio_dataPendQ_clearReq_dummy2_1$Q_OUT)); - - // submodule mmio_dataPendQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataPendQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_dataPendQ_deqReq_dummy2_0$D_IN), - .EN(mmio_dataPendQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_dataPendQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataPendQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_dataPendQ_deqReq_dummy2_1$D_IN), - .EN(mmio_dataPendQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_dataPendQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataPendQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_dataPendQ_deqReq_dummy2_2$D_IN), - .EN(mmio_dataPendQ_deqReq_dummy2_2$EN), - .Q_OUT(mmio_dataPendQ_deqReq_dummy2_2$Q_OUT)); - - // submodule mmio_dataPendQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataPendQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_dataPendQ_enqReq_dummy2_0$D_IN), - .EN(mmio_dataPendQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_dataPendQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataPendQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_dataPendQ_enqReq_dummy2_1$D_IN), - .EN(mmio_dataPendQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_dataPendQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataPendQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_dataPendQ_enqReq_dummy2_2$D_IN), - .EN(mmio_dataPendQ_enqReq_dummy2_2$EN), - .Q_OUT(mmio_dataPendQ_enqReq_dummy2_2$Q_OUT)); - - // submodule mmio_dataReqQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataReqQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_dataReqQ_clearReq_dummy2_0$D_IN), - .EN(mmio_dataReqQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_dataReqQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataReqQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_dataReqQ_clearReq_dummy2_1$D_IN), - .EN(mmio_dataReqQ_clearReq_dummy2_1$EN), - .Q_OUT(mmio_dataReqQ_clearReq_dummy2_1$Q_OUT)); - - // submodule mmio_dataReqQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataReqQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_dataReqQ_deqReq_dummy2_0$D_IN), - .EN(mmio_dataReqQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_dataReqQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataReqQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_dataReqQ_deqReq_dummy2_1$D_IN), - .EN(mmio_dataReqQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_dataReqQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataReqQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_dataReqQ_deqReq_dummy2_2$D_IN), - .EN(mmio_dataReqQ_deqReq_dummy2_2$EN), - .Q_OUT(mmio_dataReqQ_deqReq_dummy2_2$Q_OUT)); - - // submodule mmio_dataReqQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataReqQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_dataReqQ_enqReq_dummy2_0$D_IN), - .EN(mmio_dataReqQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_dataReqQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataReqQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_dataReqQ_enqReq_dummy2_1$D_IN), - .EN(mmio_dataReqQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_dataReqQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataReqQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_dataReqQ_enqReq_dummy2_2$D_IN), - .EN(mmio_dataReqQ_enqReq_dummy2_2$EN), - .Q_OUT(mmio_dataReqQ_enqReq_dummy2_2$Q_OUT)); - - // submodule mmio_dataRespQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataRespQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_dataRespQ_clearReq_dummy2_0$D_IN), - .EN(mmio_dataRespQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_dataRespQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataRespQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_dataRespQ_clearReq_dummy2_1$D_IN), - .EN(mmio_dataRespQ_clearReq_dummy2_1$EN), - .Q_OUT(mmio_dataRespQ_clearReq_dummy2_1$Q_OUT)); - - // submodule mmio_dataRespQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataRespQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_dataRespQ_deqReq_dummy2_0$D_IN), - .EN(mmio_dataRespQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_dataRespQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataRespQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_dataRespQ_deqReq_dummy2_1$D_IN), - .EN(mmio_dataRespQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_dataRespQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataRespQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_dataRespQ_deqReq_dummy2_2$D_IN), - .EN(mmio_dataRespQ_deqReq_dummy2_2$EN), - .Q_OUT(mmio_dataRespQ_deqReq_dummy2_2$Q_OUT)); - - // submodule mmio_dataRespQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataRespQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_dataRespQ_enqReq_dummy2_0$D_IN), - .EN(mmio_dataRespQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_dataRespQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataRespQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_dataRespQ_enqReq_dummy2_1$D_IN), - .EN(mmio_dataRespQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_dataRespQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_dataRespQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_dataRespQ_enqReq_dummy2_2$D_IN), - .EN(mmio_dataRespQ_enqReq_dummy2_2$EN), - .Q_OUT(mmio_dataRespQ_enqReq_dummy2_2$Q_OUT)); - - // submodule mmio_pRqQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_pRqQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_pRqQ_clearReq_dummy2_0$D_IN), - .EN(mmio_pRqQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_pRqQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_pRqQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_pRqQ_clearReq_dummy2_1$D_IN), - .EN(mmio_pRqQ_clearReq_dummy2_1$EN), - .Q_OUT(mmio_pRqQ_clearReq_dummy2_1$Q_OUT)); - - // submodule mmio_pRqQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_pRqQ_deqReq_dummy2_0$D_IN), - .EN(mmio_pRqQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_pRqQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_pRqQ_deqReq_dummy2_1$D_IN), - .EN(mmio_pRqQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_pRqQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_pRqQ_deqReq_dummy2_2$D_IN), - .EN(mmio_pRqQ_deqReq_dummy2_2$EN), - .Q_OUT(mmio_pRqQ_deqReq_dummy2_2$Q_OUT)); - - // submodule mmio_pRqQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_pRqQ_enqReq_dummy2_0$D_IN), - .EN(mmio_pRqQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_pRqQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_pRqQ_enqReq_dummy2_1$D_IN), - .EN(mmio_pRqQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_pRqQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_pRqQ_enqReq_dummy2_2$D_IN), - .EN(mmio_pRqQ_enqReq_dummy2_2$EN), - .Q_OUT(mmio_pRqQ_enqReq_dummy2_2$Q_OUT)); - - // submodule mmio_pRsQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_pRsQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_pRsQ_clearReq_dummy2_0$D_IN), - .EN(mmio_pRsQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_pRsQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmio_pRsQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_pRsQ_clearReq_dummy2_1$D_IN), - .EN(mmio_pRsQ_clearReq_dummy2_1$EN), - .Q_OUT(mmio_pRsQ_clearReq_dummy2_1$Q_OUT)); - - // submodule mmio_pRsQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_pRsQ_deqReq_dummy2_0$D_IN), - .EN(mmio_pRsQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_pRsQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_pRsQ_deqReq_dummy2_1$D_IN), - .EN(mmio_pRsQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_pRsQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_pRsQ_deqReq_dummy2_2$D_IN), - .EN(mmio_pRsQ_deqReq_dummy2_2$EN), - .Q_OUT(mmio_pRsQ_deqReq_dummy2_2$Q_OUT)); - - // submodule mmio_pRsQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(mmio_pRsQ_enqReq_dummy2_0$D_IN), - .EN(mmio_pRsQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmio_pRsQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(mmio_pRsQ_enqReq_dummy2_1$D_IN), - .EN(mmio_pRsQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmio_pRsQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(mmio_pRsQ_enqReq_dummy2_2$D_IN), - .EN(mmio_pRsQ_enqReq_dummy2_2$EN), - .Q_OUT(mmio_pRsQ_enqReq_dummy2_2$Q_OUT)); - // submodule perfReqQ FIFO1 #(.width(32'd9), .guarded(32'd1)) perfReqQ(.RST(RST_N), .CLK(CLK), @@ -8818,6 +8715,9 @@ module mkCore(CLK, .read_3_rd1_rindx(rf$read_3_rd1_rindx), .read_3_rd2_rindx(rf$read_3_rd2_rindx), .read_3_rd3_rindx(rf$read_3_rd3_rindx), + .read_4_rd1_rindx(rf$read_4_rd1_rindx), + .read_4_rd2_rindx(rf$read_4_rd2_rindx), + .read_4_rd3_rindx(rf$read_4_rd3_rindx), .write_0_wr_data(rf$write_0_wr_data), .write_0_wr_rindx(rf$write_0_wr_rindx), .write_1_wr_data(rf$write_1_wr_data), @@ -8826,14 +8726,18 @@ module mkCore(CLK, .write_2_wr_rindx(rf$write_2_wr_rindx), .write_3_wr_data(rf$write_3_wr_data), .write_3_wr_rindx(rf$write_3_wr_rindx), + .write_4_wr_data(rf$write_4_wr_data), + .write_4_wr_rindx(rf$write_4_wr_rindx), .EN_write_0_wr(rf$EN_write_0_wr), .EN_write_1_wr(rf$EN_write_1_wr), .EN_write_2_wr(rf$EN_write_2_wr), .EN_write_3_wr(rf$EN_write_3_wr), + .EN_write_4_wr(rf$EN_write_4_wr), .RDY_write_0_wr(), .RDY_write_1_wr(), .RDY_write_2_wr(), .RDY_write_3_wr(), + .RDY_write_4_wr(), .read_0_rd1(rf$read_0_rd1), .RDY_read_0_rd1(), .read_0_rd2(rf$read_0_rd2), @@ -8857,7 +8761,13 @@ module mkCore(CLK, .read_3_rd2(rf$read_3_rd2), .RDY_read_3_rd2(), .read_3_rd3(), - .RDY_read_3_rd3()); + .RDY_read_3_rd3(), + .read_4_rd1(rf$read_4_rd1), + .RDY_read_4_rd1(), + .read_4_rd2(), + .RDY_read_4_rd2(), + .read_4_rd3(), + .RDY_read_4_rd3()); // submodule rob mkReorderBufferSynth rob(.CLK(CLK), @@ -8874,16 +8784,26 @@ module mkCore(CLK, .setExecuted_deqLSQ_cause(rob$setExecuted_deqLSQ_cause), .setExecuted_deqLSQ_ld_killed(rob$setExecuted_deqLSQ_ld_killed), .setExecuted_deqLSQ_x(rob$setExecuted_deqLSQ_x), + .setExecuted_doFinishAlu_0_set_cause(rob$setExecuted_doFinishAlu_0_set_cause), .setExecuted_doFinishAlu_0_set_cf(rob$setExecuted_doFinishAlu_0_set_cf), .setExecuted_doFinishAlu_0_set_csrData(rob$setExecuted_doFinishAlu_0_set_csrData), + .setExecuted_doFinishAlu_0_set_dst_data(rob$setExecuted_doFinishAlu_0_set_dst_data), + .setExecuted_doFinishAlu_0_set_scrData(rob$setExecuted_doFinishAlu_0_set_scrData), .setExecuted_doFinishAlu_0_set_x(rob$setExecuted_doFinishAlu_0_set_x), + .setExecuted_doFinishAlu_1_set_cause(rob$setExecuted_doFinishAlu_1_set_cause), .setExecuted_doFinishAlu_1_set_cf(rob$setExecuted_doFinishAlu_1_set_cf), .setExecuted_doFinishAlu_1_set_csrData(rob$setExecuted_doFinishAlu_1_set_csrData), + .setExecuted_doFinishAlu_1_set_dst_data(rob$setExecuted_doFinishAlu_1_set_dst_data), + .setExecuted_doFinishAlu_1_set_scrData(rob$setExecuted_doFinishAlu_1_set_scrData), .setExecuted_doFinishAlu_1_set_x(rob$setExecuted_doFinishAlu_1_set_x), + .setExecuted_doFinishFpuMulDiv_0_set_cause(rob$setExecuted_doFinishFpuMulDiv_0_set_cause), + .setExecuted_doFinishFpuMulDiv_0_set_dst_data(rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data), .setExecuted_doFinishFpuMulDiv_0_set_fflags(rob$setExecuted_doFinishFpuMulDiv_0_set_fflags), .setExecuted_doFinishFpuMulDiv_0_set_x(rob$setExecuted_doFinishFpuMulDiv_0_set_x), .setExecuted_doFinishMem_access_at_commit(rob$setExecuted_doFinishMem_access_at_commit), .setExecuted_doFinishMem_non_mmio_st_done(rob$setExecuted_doFinishMem_non_mmio_st_done), + .setExecuted_doFinishMem_store_data(rob$setExecuted_doFinishMem_store_data), + .setExecuted_doFinishMem_store_data_BE(rob$setExecuted_doFinishMem_store_data_BE), .setExecuted_doFinishMem_vaddr(rob$setExecuted_doFinishMem_vaddr), .setExecuted_doFinishMem_x(rob$setExecuted_doFinishMem_x), .setLSQAtCommitNotified_x(rob$setLSQAtCommitNotified_x), @@ -8998,18 +8918,21 @@ module mkCore(CLK, .lazyLookup_1_get_r(sbCons$lazyLookup_1_get_r), .lazyLookup_2_get_r(sbCons$lazyLookup_2_get_r), .lazyLookup_3_get_r(sbCons$lazyLookup_3_get_r), + .lazyLookup_4_get_r(sbCons$lazyLookup_4_get_r), .setBusy_0_set_dst(sbCons$setBusy_0_set_dst), .setBusy_1_set_dst(sbCons$setBusy_1_set_dst), .setReady_0_put(sbCons$setReady_0_put), .setReady_1_put(sbCons$setReady_1_put), .setReady_2_put(sbCons$setReady_2_put), .setReady_3_put(sbCons$setReady_3_put), + .setReady_4_put(sbCons$setReady_4_put), .EN_setBusy_0_set(sbCons$EN_setBusy_0_set), .EN_setBusy_1_set(sbCons$EN_setBusy_1_set), .EN_setReady_0_put(sbCons$EN_setReady_0_put), .EN_setReady_1_put(sbCons$EN_setReady_1_put), .EN_setReady_2_put(sbCons$EN_setReady_2_put), .EN_setReady_3_put(sbCons$EN_setReady_3_put), + .EN_setReady_4_put(sbCons$EN_setReady_4_put), .eagerLookup_0_get(), .RDY_eagerLookup_0_get(), .eagerLookup_1_get(), @@ -9020,6 +8943,7 @@ module mkCore(CLK, .RDY_setReady_1_put(), .RDY_setReady_2_put(), .RDY_setReady_3_put(), + .RDY_setReady_4_put(), .lazyLookup_0_get(sbCons$lazyLookup_0_get), .RDY_lazyLookup_0_get(), .lazyLookup_1_get(sbCons$lazyLookup_1_get), @@ -9027,7 +8951,9 @@ module mkCore(CLK, .lazyLookup_2_get(sbCons$lazyLookup_2_get), .RDY_lazyLookup_2_get(), .lazyLookup_3_get(sbCons$lazyLookup_3_get), - .RDY_lazyLookup_3_get()); + .RDY_lazyLookup_3_get(), + .lazyLookup_4_get(), + .RDY_lazyLookup_4_get()); // submodule specTagManager mkSpecTagManager specTagManager(.CLK(CLK), @@ -9056,32 +8982,32 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - coreFix_memExe_dTlb$RDY_toParent_rqToP_first && coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && + coreFix_memExe_dTlb$RDY_toParent_rqToP_first && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - l2Tlb$RDY_toChildren_rqFromC_put && fetchStage$RDY_iTlbIfc_toParent_rqToP_first && - fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ; + fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && + l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; // rule RL_sendRsToDTlb assign CAN_FIRE_RL_sendRsToDTlb = - l2Tlb$RDY_toChildren_rsToC_first && l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq && l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ; // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - l2Tlb$RDY_toChildren_rsToC_first && - l2Tlb$RDY_toChildren_rsToC_deq && fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && + l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; @@ -9093,31 +9019,143 @@ module mkCore(CLK, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - l2Tlb$RDY_toChildren_iTlbReqFlush_put && - fetchStage$RDY_iTlbIfc_toParent_flush_request_get ; + fetchStage$RDY_iTlbIfc_toParent_flush_request_get && + l2Tlb$RDY_toChildren_iTlbReqFlush_put ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = coreFix_memExe_dTlb$RDY_toParent_flush_response_put && - l2Tlb$RDY_toChildren_flushDone_get && - fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; + fetchStage$RDY_iTlbIfc_toParent_flush_response_put && + l2Tlb$RDY_toChildren_flushDone_get ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; // rule RL_sendRobEnqTime assign CAN_FIRE_RL_sendRobEnqTime = 1'd1 ; assign WILL_FIRE_RL_sendRobEnqTime = 1'd1 ; + // rule RL_setDoFlushCaches + assign CAN_FIRE_RL_setDoFlushCaches = + flush_caches && fetchStage$emptyForFlush && + coreFix_memExe_lsq$noWrongPathLoads ; + assign WILL_FIRE_RL_setDoFlushCaches = CAN_FIRE_RL_setDoFlushCaches ; + + // rule RL_setDoFlushBrPred + assign CAN_FIRE_RL_setDoFlushBrPred = + flush_brpred && fetchStage$emptyForFlush ; + assign WILL_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_setDoFlushBrPred ; + // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = - fetchStage$RDY_done_flushing && !flush_reservation && - !flush_tlbs && - !update_vm_info && - fetchStage$iTlbIfc_flush_done && - coreFix_memExe_dTlb$flush_done ; + fetchStage$RDY_done_flushing && + rg_core_run_state_read__0460_EQ_2_0461_AND_NOT_ETC___d23446 && + !flush_brpred && + fetchStage$iMemIfc_flush_done && + fetchStage$flush_predictors_done ; assign WILL_FIRE_RL_readyToFetch = CAN_FIRE_RL_readyToFetch ; + // rule RL_flushCaches + assign CAN_FIRE_RL_flushCaches = CAN_FIRE_RL_setDoFlushCaches ; + assign WILL_FIRE_RL_flushCaches = CAN_FIRE_RL_setDoFlushCaches ; + + // rule RL_flushBrPred + assign CAN_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ; + assign WILL_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ; + + // rule RL_rl_debug_gpr_read + assign CAN_FIRE_RL_rl_debug_gpr_read = + regRenamingTable$RDY_rename_0_getRename && f_gpr_reqs$EMPTY_N && + f_gpr_rsps$FULL_N && + rg_core_run_state == 2'd1 && + !f_gpr_reqs$D_OUT[69] ; + assign WILL_FIRE_RL_rl_debug_gpr_read = CAN_FIRE_RL_rl_debug_gpr_read ; + + // rule RL_rl_debug_gpr_write + assign CAN_FIRE_RL_rl_debug_gpr_write = + regRenamingTable$RDY_rename_0_getRename && f_gpr_reqs$EMPTY_N && + f_gpr_rsps$FULL_N && + rg_core_run_state == 2'd1 && + f_gpr_reqs$D_OUT[69] ; + assign WILL_FIRE_RL_rl_debug_gpr_write = CAN_FIRE_RL_rl_debug_gpr_write ; + + // rule RL_rl_debug_gpr_access_busy + assign CAN_FIRE_RL_rl_debug_gpr_access_busy = + f_gpr_reqs$EMPTY_N && f_gpr_rsps$FULL_N && + rg_core_run_state == 2'd2 ; + assign WILL_FIRE_RL_rl_debug_gpr_access_busy = + CAN_FIRE_RL_rl_debug_gpr_access_busy ; + + // rule RL_rl_debug_fpr_read + assign CAN_FIRE_RL_rl_debug_fpr_read = + regRenamingTable$RDY_rename_0_getRename && f_fpr_reqs$EMPTY_N && + f_fpr_rsps$FULL_N && + rg_core_run_state == 2'd1 && + !f_gpr_reqs$EMPTY_N && + !f_fpr_reqs$D_OUT[69] ; + assign WILL_FIRE_RL_rl_debug_fpr_read = CAN_FIRE_RL_rl_debug_fpr_read ; + + // rule RL_rl_debug_fpr_write + assign CAN_FIRE_RL_rl_debug_fpr_write = + regRenamingTable$RDY_rename_0_getRename && f_fpr_reqs$EMPTY_N && + f_fpr_rsps$FULL_N && + rg_core_run_state == 2'd1 && + !f_gpr_reqs$EMPTY_N && + f_fpr_reqs$D_OUT[69] ; + assign WILL_FIRE_RL_rl_debug_fpr_write = CAN_FIRE_RL_rl_debug_fpr_write ; + + // rule RL_rl_debug_fpr_access_busy + assign CAN_FIRE_RL_rl_debug_fpr_access_busy = + f_fpr_reqs$EMPTY_N && f_fpr_rsps$FULL_N && + rg_core_run_state == 2'd2 ; + assign WILL_FIRE_RL_rl_debug_fpr_access_busy = + CAN_FIRE_RL_rl_debug_fpr_access_busy ; + + // rule RL_rl_debug_csr_write + assign CAN_FIRE_RL_rl_debug_csr_write = + f_csr_reqs$EMPTY_N && + f_csr_rsps_i_notFull__3520_AND_f_csr_reqs_firs_ETC___d23615 && + rg_core_run_state == 2'd1 && + f_csr_reqs$D_OUT[76] ; + assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ; + + // rule RL_rl_debug_csr_access_busy + assign CAN_FIRE_RL_rl_debug_csr_access_busy = + f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N && + rg_core_run_state == 2'd2 ; + assign WILL_FIRE_RL_rl_debug_csr_access_busy = + CAN_FIRE_RL_rl_debug_csr_access_busy ; + + // rule RL_rl_debug_halt_req + assign CAN_FIRE_RL_rl_debug_halt_req = + f_run_halt_reqs$EMPTY_N && !renameStage_rg_m_halt_req[4] && + rg_core_run_state == 2'd2 && + !f_run_halt_reqs$D_OUT ; + assign WILL_FIRE_RL_rl_debug_halt_req = CAN_FIRE_RL_rl_debug_halt_req ; + + // rule RL_rl_debug_halt_req_already_halted + assign CAN_FIRE_RL_rl_debug_halt_req_already_halted = + f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && + rg_core_run_state != 2'd2 && + !f_run_halt_reqs$D_OUT ; + assign WILL_FIRE_RL_rl_debug_halt_req_already_halted = + CAN_FIRE_RL_rl_debug_halt_req_already_halted ; + + // rule RL_rl_debug_halted + assign CAN_FIRE_RL_rl_debug_halted = + f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd0 ; + assign WILL_FIRE_RL_rl_debug_halted = + CAN_FIRE_RL_rl_debug_halted && + !WILL_FIRE_RL_rl_debug_halt_req_already_halted ; + + // rule RL_rl_debug_run_redundant + assign CAN_FIRE_RL_rl_debug_run_redundant = + f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && + rg_core_run_state == 2'd2 && + f_run_halt_reqs$D_OUT ; + assign WILL_FIRE_RL_rl_debug_run_redundant = + CAN_FIRE_RL_rl_debug_run_redundant ; + // rule RL_csrf_minstret_ehr_setRead assign CAN_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ; assign WILL_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ; @@ -9126,12 +9164,25 @@ module mkCore(CLK, assign CAN_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ; assign WILL_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ; + // rule RL_rl_debug_csr_read + assign CAN_FIRE_RL_rl_debug_csr_read = + f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N && + rg_core_run_state == 2'd1 && + !f_csr_reqs$D_OUT[76] ; + assign WILL_FIRE_RL_rl_debug_csr_read = CAN_FIRE_RL_rl_debug_csr_read ; + + // rule RL_csrf_sepcc_reg_setRead + assign CAN_FIRE_RL_csrf_sepcc_reg_setRead = 1'd1 ; + assign WILL_FIRE_RL_csrf_sepcc_reg_setRead = 1'd1 ; + + // rule RL_csrf_mepcc_reg_setRead + assign CAN_FIRE_RL_csrf_mepcc_reg_setRead = 1'd1 ; + assign WILL_FIRE_RL_csrf_mepcc_reg_setRead = 1'd1 ; + // rule RL_mmio_handlePRq assign CAN_FIRE_RL_mmio_handlePRq = !mmio_pRqQ_empty && !mmio_cRsQ_full && - (!csrInstOrInterruptInflight_dummy2_0$Q_OUT || - !csrInstOrInterruptInflight_dummy2_1$Q_OUT || - !csrInstOrInterruptInflight_rl) ; + !csrInstOrInterruptInflight_rl ; assign WILL_FIRE_RL_mmio_handlePRq = CAN_FIRE_RL_mmio_handlePRq ; // rule RL_mmio_sendDataReq @@ -9150,13 +9201,13 @@ module mkCore(CLK, // rule RL_mmio_sendDataResp assign CAN_FIRE_RL_mmio_sendDataResp = !mmio_dataRespQ_full && !mmio_pRsQ_empty && - mmio_pRsQ_data_0[66] ; + mmio_pRsQ_data_0[130] ; assign WILL_FIRE_RL_mmio_sendDataResp = CAN_FIRE_RL_mmio_sendDataResp ; // rule RL_mmio_sendInstResp assign CAN_FIRE_RL_mmio_sendInstResp = !mmio_pRsQ_empty && fetchStage$RDY_mmioIfc_instResp_enq && - !mmio_pRsQ_data_0[66] ; + !mmio_pRsQ_data_0[130] ; assign WILL_FIRE_RL_mmio_sendInstResp = CAN_FIRE_RL_mmio_sendInstResp ; // rule RL_mmio_cRqQ_canonicalize @@ -9218,24 +9269,39 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doIssueSB assign CAN_FIRE_RL_coreFix_memExe_doIssueSB = - (!coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT || - !coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT || - !coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT || - !coreFix_memExe_reqStQ_full_rl) && - coreFix_memExe_stb$RDY_issue ; + !coreFix_memExe_reqStQ_full_rl && coreFix_memExe_stb$RDY_issue ; assign WILL_FIRE_RL_coreFix_memExe_doIssueSB = CAN_FIRE_RL_coreFix_memExe_doIssueSB ; + // rule RL_coreFix_memExe_doDeqLdQ_fault + assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && + coreFix_memExe_lsq$firstLd[16] ; + assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = + CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; + + // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem + assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && + !coreFix_memExe_lsq$firstLd[16] && + !coreFix_memExe_lsq$firstLd[126] && + !coreFix_memExe_lsq$firstLd[33] ; + assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = + CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ; + // rule RL_coreFix_memExe_doDeqLdQ_Lr_issue assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue = - NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 && + !coreFix_memExe_reqLrScAmoQ_full_rl && coreFix_memExe_lsq$RDY_firstLd && - !coreFix_memExe_lsq$firstLd[7] && !coreFix_memExe_lsq$firstLd[16] && - coreFix_memExe_lsq$firstLd[101] && + !coreFix_memExe_lsq$firstLd[33] && + coreFix_memExe_lsq$firstLd[126] && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 && coreFix_memExe_stb$noMatchLdQ && - (!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ; + (!coreFix_memExe_lsq$firstLd[107] || + coreFix_memExe_stb$isEmpty) ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ; @@ -9243,13 +9309,28 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue = !mmio_dataReqQ_full && !mmio_dataPendQ_full && coreFix_memExe_lsq$RDY_firstLd && - !coreFix_memExe_lsq$firstLd[7] && - coreFix_memExe_lsq$firstLd[16] && + !coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[33] && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 && - (!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ; + (!coreFix_memExe_lsq$firstLd[107] || + coreFix_memExe_stb$isEmpty) ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ; + // rule RL_coreFix_memExe_doDeqLdQ_MMIO_fault + assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault = + !mmio_dataRespQ_empty && + NOT_mmio_dataPendQ_empty_80_378_AND_rob_RDY_se_ETC___d2026 && + coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 && + coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 && + coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 && + coreFix_memExe_waitLrScAmoMMIOResp[0] && + !mmio_dataRespQ_data_0[129] ; + assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault = + CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; + // rule RL_coreFix_memExe_dMem_perfReqQ_canonicalize assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ; @@ -9266,6 +9347,16 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ; + // rule RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo + assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo = + !coreFix_memExe_respLrScAmoQ_full && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite && + coreFix_memExe_dMem_cache_m_banks_0_processAmo[234] ; + assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo = + CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ; + // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp = coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N && @@ -9281,22 +9372,6 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ; - // rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq - assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq = - !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full && - coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry && - coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N && - coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ; - assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq = - CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ; - - // rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP - assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP = - !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full && - coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N ; - assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP = - CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ; - // rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full && @@ -9306,27 +9381,33 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ; - // rule RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo - assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo = - !coreFix_memExe_respLrScAmoQ_full && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite && - coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] ; - assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo = - CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ; + // rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq + assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq = + !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full && + coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry && + coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N && + coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ; + assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq = + CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ; // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq = coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite && - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2700 && - !coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d6947 && + !coreFix_memExe_dMem_cache_m_banks_0_processAmo[234] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[583:582] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ; + // rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP + assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP = + !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full && + coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N ; + assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP = + CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ; + // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize = 1'd1 ; @@ -9428,33 +9509,28 @@ module mkCore(CLK, (!fetchStage$pipelines_0_canDeq || epochManager$checkEpoch_0_check || fetchStage$RDY_pipelines_0_deq) && - NOT_fetchStage_pipelines_1_canDeq__2611_2612_O_ETC___d12620 && + NOT_fetchStage_pipelines_1_canDeq__0051_0052_O_ETC___d20060 && !epochManager$checkEpoch_0_check ; assign WILL_FIRE_RL_renameStage_doRenaming_wrongPath = CAN_FIRE_RL_renameStage_doRenaming_wrongPath ; // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && - !commitStage_commitTrap[133] && - rob$deqPort_0_deq_data[167] ; + !commitStage_rg_run_state && + !commitStage_commitTrap[238] && + rob$deqPort_0_deq_data[274] ; assign WILL_FIRE_RL_commitStage_doCommitTrap_flush = CAN_FIRE_RL_commitStage_doCommitTrap_flush && !WILL_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && @@ -9471,10 +9547,10 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_handle assign CAN_FIRE_RL_commitStage_doCommitTrap_handle = - coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - commitStage_commitTrap[133] ; + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22269 && + NOT_commitStage_commitTrap_2029_BITS_44_TO_43__ETC___d22296 && + commitStage_commitTrap[238] && + !commitStage_rg_run_state ; assign WILL_FIRE_RL_commitStage_doCommitTrap_handle = CAN_FIRE_RL_commitStage_doCommitTrap_handle && !WILL_FIRE_RL_renameStage_doRenaming_SystemInst && @@ -9485,10 +9561,11 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && - !commitStage_commitTrap[133] && - !rob$deqPort_0_deq_data[167] && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && + !commitStage_rg_run_state && + !commitStage_commitTrap[238] && + !rob$deqPort_0_deq_data[274] && rob$deqPort_0_deq_data[18] ; assign WILL_FIRE_RL_commitStage_doCommitKilledLd = CAN_FIRE_RL_commitStage_doCommitKilledLd && @@ -9496,15 +9573,9 @@ module mkCore(CLK, !WILL_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && @@ -9521,26 +9592,25 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = - coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14366 && - !commitStage_commitTrap[133] && - !rob$deqPort_0_deq_data[167] && - !rob$deqPort_0_deq_data[18] && - rob$deqPort_0_deq_data[25] && - (rob$deqPort_0_deq_data[186:182] == 5'd0 || - rob$deqPort_0_deq_data[186:182] == 5'd21 || - rob$deqPort_0_deq_data[186:182] == 5'd17 || - rob$deqPort_0_deq_data[186:182] == 5'd18 || - rob$deqPort_0_deq_data[186:182] == 5'd13 || - rob$deqPort_0_deq_data[186:182] == 5'd16 || - rob$deqPort_0_deq_data[186:182] == 5'd15 || - rob$deqPort_0_deq_data[186:182] == 5'd19 || - rob$deqPort_0_deq_data[186:182] == 5'd20) ; + coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d22800 && + NOT_commitStage_rg_run_state_2027_2028_AND_NOT_ETC___d22806 && + (rob$deqPort_0_deq_data[469:465] == 5'd0 || + rob$deqPort_0_deq_data[469:465] == 5'd26 || + rob$deqPort_0_deq_data[469:465] == 5'd22 || + rob$deqPort_0_deq_data[469:465] == 5'd23 || + rob$deqPort_0_deq_data[469:465] == 5'd17 || + rob$deqPort_0_deq_data[469:465] == 5'd18 || + rob$deqPort_0_deq_data[469:465] == 5'd21 || + rob$deqPort_0_deq_data[469:465] == 5'd20 || + rob$deqPort_0_deq_data[469:465] == 5'd24 || + rob$deqPort_0_deq_data[469:465] == 5'd25) ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && !WILL_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_rl_debug_csr_write && !WILL_FIRE_RL_prepareCachesAndTlbs ; // rule RL_csrf_incCycle @@ -9554,8 +9624,8 @@ module mkCore(CLK, // rule RL_commitStage_notifyLSQCommit assign CAN_FIRE_RL_commitStage_notifyLSQCommit = rob$RDY_setLSQAtCommitNotified && rob$RDY_deqPort_0_deq_data && - !commitStage_commitTrap[133] && - !rob$deqPort_0_deq_data[167] && + !commitStage_commitTrap[238] && + !rob$deqPort_0_deq_data[274] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[25] && rob$deqPort_0_deq_data[15] && @@ -9566,20 +9636,18 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_RDY_ETC___d14594 && - !commitStage_commitTrap[133] && - !rob$deqPort_0_deq_data[167] && - !rob$deqPort_0_deq_data[18] && - rob$deqPort_0_deq_data[25] && - rob$deqPort_0_deq_data[186:182] != 5'd0 && - rob$deqPort_0_deq_data[186:182] != 5'd21 && - rob$deqPort_0_deq_data[186:182] != 5'd17 && - rob$deqPort_0_deq_data[186:182] != 5'd18 && - rob$deqPort_0_deq_data[186:182] != 5'd13 && - rob$deqPort_0_deq_data[186:182] != 5'd16 && - rob$deqPort_0_deq_data[186:182] != 5'd15 && - rob$deqPort_0_deq_data[186:182] != 5'd19 && - rob$deqPort_0_deq_data[186:182] != 5'd20 ; + NOT_rob_deqPort_0_canDeq__3151_3152_OR_regRena_ETC___d23192 && + NOT_commitStage_rg_run_state_2027_2028_AND_NOT_ETC___d22806 && + rob$deqPort_0_deq_data[469:465] != 5'd0 && + rob$deqPort_0_deq_data[469:465] != 5'd26 && + rob$deqPort_0_deq_data[469:465] != 5'd22 && + rob$deqPort_0_deq_data[469:465] != 5'd23 && + rob$deqPort_0_deq_data[469:465] != 5'd17 && + rob$deqPort_0_deq_data[469:465] != 5'd18 && + rob$deqPort_0_deq_data[469:465] != 5'd21 && + rob$deqPort_0_deq_data[469:465] != 5'd20 && + rob$deqPort_0_deq_data[469:465] != 5'd24 && + rob$deqPort_0_deq_data[469:465] != 5'd25 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst ; @@ -9589,7 +9657,7 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_1_doFinishAlu_T assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T = - coreFix_aluExe_1_exeToFinQ$first[17] && + coreFix_aluExe_1_exeToFinQ$first[295] && coreFix_aluExe_1_exeToFinQ$RDY_deq && coreFix_aluExe_1_exeToFinQ$RDY_first && rob$RDY_setExecuted_doFinishAlu_1_set && @@ -9597,12 +9665,6 @@ module mkCore(CLK, coreFix_trainBPQ_1$FULL_N ; assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && @@ -9615,11 +9677,12 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !WILL_FIRE_RL_rl_debug_resume ; // rule RL_coreFix_aluExe_0_doFinishAlu_T assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T = - coreFix_aluExe_0_exeToFinQ$first[17] && + coreFix_aluExe_0_exeToFinQ$first[295] && coreFix_aluExe_0_exeToFinQ$RDY_deq && coreFix_aluExe_0_exeToFinQ$RDY_first && rob$RDY_setExecuted_doFinishAlu_0_set && @@ -9627,13 +9690,8 @@ module mkCore(CLK, coreFix_trainBPQ_0$FULL_N ; assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && @@ -9646,25 +9704,37 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !WILL_FIRE_RL_rl_debug_resume ; // rule RL_coreFix_aluExe_0_doFinishAlu_F assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F = - !coreFix_aluExe_0_exeToFinQ$first[17] && + !coreFix_aluExe_0_exeToFinQ$first[295] && coreFix_aluExe_0_exeToFinQ$RDY_deq && - coreFix_aluExe_0_exeToFinQ_RDY_first__2490_AND_ETC___d12528 ; + coreFix_aluExe_0_exeToFinQ$RDY_first && + rob$RDY_setExecuted_doFinishAlu_0_set && + (coreFix_aluExe_0_exeToFinQ$first[1066:1062] != 5'd9 && + coreFix_aluExe_0_exeToFinQ$first[1066:1062] != 5'd12 && + coreFix_aluExe_0_exeToFinQ$first[1066:1062] != 5'd11 && + coreFix_aluExe_0_exeToFinQ$first[1066:1062] != 5'd10 || + coreFix_trainBPQ_0$FULL_N) ; assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F = CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_aluExe_1_doFinishAlu_F assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F = - !coreFix_aluExe_1_exeToFinQ$first[17] && + !coreFix_aluExe_1_exeToFinQ$first[295] && coreFix_aluExe_1_exeToFinQ$RDY_deq && - coreFix_aluExe_1_exeToFinQ_RDY_first__1881_AND_ETC___d11920 ; + coreFix_aluExe_1_exeToFinQ$RDY_first && + rob$RDY_setExecuted_doFinishAlu_1_set && + (coreFix_aluExe_1_exeToFinQ$first[1066:1062] != 5'd9 && + coreFix_aluExe_1_exeToFinQ$first[1066:1062] != 5'd12 && + coreFix_aluExe_1_exeToFinQ$first[1066:1062] != 5'd11 && + coreFix_aluExe_1_exeToFinQ$first[1066:1062] != 5'd10 || + coreFix_trainBPQ_1$FULL_N) ; assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F = - CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ; // rule RL_coreFix_aluExe_1_doExeAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu = @@ -9695,7 +9765,7 @@ module mkCore(CLK, coreFix_aluExe_1_dispToRegQ$RDY_deq && coreFix_aluExe_1_regToExeQ$RDY_enq && coreFix_aluExe_1_dispToRegQ$RDY_first && - coreFix_aluExe_1_dispToRegQ_first__1283_BIT_13_ETC___d11368 ; + coreFix_aluExe_1_dispToRegQ_first__5590_BIT_13_ETC___d15675 ; assign WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu = CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -9708,7 +9778,7 @@ module mkCore(CLK, coreFix_aluExe_0_dispToRegQ$RDY_deq && coreFix_aluExe_0_regToExeQ$RDY_enq && coreFix_aluExe_0_dispToRegQ$RDY_first && - coreFix_aluExe_0_dispToRegQ_first__2078_BIT_13_ETC___d12163 ; + coreFix_aluExe_0_dispToRegQ_first__8199_BIT_13_ETC___d18284 ; assign WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu = CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -9716,11 +9786,19 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; + // rule RL_csrf_sepcc_reg_data_canon + assign CAN_FIRE_RL_csrf_sepcc_reg_data_canon = 1'd1 ; + assign WILL_FIRE_RL_csrf_sepcc_reg_data_canon = 1'd1 ; + + // rule RL_csrf_mepcc_reg_data_canon + assign CAN_FIRE_RL_csrf_mepcc_reg_data_canon = 1'd1 ; + assign WILL_FIRE_RL_csrf_mepcc_reg_data_canon = 1'd1 ; + // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = coreFix_aluExe_0_dispToRegQ$RDY_enq && - coreFix_aluExe_0_rsAlu$RDY_doDispatch && - coreFix_aluExe_0_rsAlu$RDY_dispatchData ; + coreFix_aluExe_0_rsAlu$RDY_dispatchData && + coreFix_aluExe_0_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -9731,8 +9809,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = coreFix_aluExe_1_dispToRegQ$RDY_enq && - coreFix_aluExe_1_rsAlu$RDY_doDispatch && - coreFix_aluExe_1_rsAlu$RDY_dispatchData ; + coreFix_aluExe_1_rsAlu$RDY_dispatchData && + coreFix_aluExe_1_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -9740,88 +9818,12 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - // rule RL_coreFix_fpuMulDivExe_0_doFinishFpSimple - assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple = - coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq && - coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first && - rob$RDY_setExecuted_doFinishFpuMulDiv_0_set ; - assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ; - - // rule RL_coreFix_fpuMulDivExe_0_doFinishFpFma - assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq && - coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3876 ; - assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ; - - // rule RL_coreFix_fpuMulDivExe_0_doFinishFpDiv - assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv = - coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq && - coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5268 ; - assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ; - - // rule RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt - assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq && - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6660 ; - assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ; - - // rule RL_coreFix_fpuMulDivExe_0_doFinishIntMul - assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul = - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq && - coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8052 ; - assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ; - - // rule RL_coreFix_fpuMulDivExe_0_doFinishIntDiv - assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv = - coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq && - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8101 ; - assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ; - - // rule RL_coreFix_memExe_doDeqLdQ_fault - assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && - coreFix_memExe_lsq$firstLd[7] ; - assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; - - // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem - assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && - !coreFix_memExe_lsq$firstLd[7] && - !coreFix_memExe_lsq$firstLd[101] && - !coreFix_memExe_lsq$firstLd[16] ; - assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ; - // rule RL_coreFix_memExe_doDeqLdQ_Lr_deq assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -9831,57 +9833,39 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqLdQ_MMIO_deq assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq = !mmio_dataRespQ_empty && - NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 && + NOT_mmio_dataPendQ_empty_80_378_AND_rob_RDY_se_ETC___d2026 && coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 && coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 && coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 && coreFix_memExe_waitLrScAmoMMIOResp[0] && - mmio_dataRespQ_data_0[64] ; + mmio_dataRespQ_data_0[129] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; - // rule RL_coreFix_memExe_doDeqLdQ_MMIO_fault - assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault = - !mmio_dataRespQ_empty && - NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 && - coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 && - coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 && - coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 && - coreFix_memExe_waitLrScAmoMMIOResp[0] && - !mmio_dataRespQ_data_0[64] ; - assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault = - CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; - // rule RL_coreFix_memExe_doFinishMem assign CAN_FIRE_RL_coreFix_memExe_doFinishMem = rob$RDY_setExecuted_doFinishMem && - coreFix_memExe_dTlb$RDY_deqProcResp && - coreFix_memExe_dTlb$RDY_procResp ; + coreFix_memExe_dTlb$RDY_procResp && + coreFix_memExe_dTlb$RDY_deqProcResp ; assign WILL_FIRE_RL_coreFix_memExe_doFinishMem = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; // rule RL_coreFix_memExe_doDeqStQ_ScAmo_issue assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue = - NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 && + !coreFix_memExe_reqLrScAmoQ_full_rl && coreFix_memExe_lsq$RDY_firstSt && - !coreFix_memExe_lsq$firstSt[4] && - !coreFix_memExe_lsq$firstSt[77] && - (coreFix_memExe_lsq$firstSt[158:157] == 2'd1 || - coreFix_memExe_lsq$firstSt[158:157] == 2'd2) && + !coreFix_memExe_lsq$firstSt[13] && + !coreFix_memExe_lsq$firstSt[159] && + (coreFix_memExe_lsq$firstSt[240:239] == 2'd1 || + coreFix_memExe_lsq$firstSt[240:239] == 2'd2) && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 && coreFix_memExe_stb$noMatchStQ && - (!coreFix_memExe_lsq$firstSt[151] || + (!coreFix_memExe_lsq$firstSt[233] || coreFix_memExe_stb$isEmpty) ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && - !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ; @@ -9889,18 +9873,14 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue = !mmio_dataReqQ_full && !mmio_dataPendQ_full && coreFix_memExe_lsq$RDY_firstSt && - !coreFix_memExe_lsq$firstSt[4] && - coreFix_memExe_lsq$firstSt[158:157] != 2'd3 && - coreFix_memExe_lsq$firstSt[77] && + !coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[240:239] != 2'd3 && + coreFix_memExe_lsq$firstSt[159] && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 && - (!coreFix_memExe_lsq$firstSt[151] || + (!coreFix_memExe_lsq$firstSt[233] || coreFix_memExe_stb$isEmpty) ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && - !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ; @@ -9922,19 +9902,189 @@ module mkCore(CLK, // rule RL_coreFix_memExe_sendLrScAmoToMem assign CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem = - NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 && - (!coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT || - !coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT || - coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas || + !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl && + (coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas || !coreFix_memExe_reqLrScAmoQ_empty_rl) ; assign WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem = CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ; + // rule RL_coreFix_memExe_doRespLdMem + assign CAN_FIRE_RL_coreFix_memExe_doRespLdMem = + !coreFix_memExe_memRespLdQ_empty ; + assign WILL_FIRE_RL_coreFix_memExe_doRespLdMem = + CAN_FIRE_RL_coreFix_memExe_doRespLdMem && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ; + + // rule RL_coreFix_memExe_doRespLdForward + assign CAN_FIRE_RL_coreFix_memExe_doRespLdForward = + !coreFix_memExe_forwardQ_empty ; + assign WILL_FIRE_RL_coreFix_memExe_doRespLdForward = + CAN_FIRE_RL_coreFix_memExe_doRespLdForward && + !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ; + + // rule RL_coreFix_memExe_doExeMem + assign CAN_FIRE_RL_coreFix_memExe_doExeMem = + coreFix_memExe_regToExeQ$RDY_deq && + coreFix_memExe_regToExeQ$RDY_first && + coreFix_memExe_dTlb$RDY_procReq ; + assign WILL_FIRE_RL_coreFix_memExe_doExeMem = + CAN_FIRE_RL_coreFix_memExe_doExeMem ; + + // rule RL_prepareCachesAndTlbs + assign CAN_FIRE_RL_prepareCachesAndTlbs = + (!flush_tlbs || + coreFix_memExe_dTlb$RDY_flush && + fetchStage$RDY_iTlbIfc_flush) && + (flush_reservation || flush_tlbs || update_vm_info) ; + assign WILL_FIRE_RL_prepareCachesAndTlbs = + CAN_FIRE_RL_prepareCachesAndTlbs ; + + // rule RL_rl_debug_resume + assign CAN_FIRE_RL_rl_debug_resume = + commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush && + fetchStage$RDY_iTlbIfc_flush && + f_run_halt_reqs$EMPTY_N && + f_run_halt_rsps$FULL_N && + rg_core_run_state == 2'd1 && + f_run_halt_reqs$D_OUT && + !f_gpr_reqs$EMPTY_N && + !f_fpr_reqs$EMPTY_N && + !f_csr_reqs$EMPTY_N ; + assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; + + // rule RL_coreFix_memExe_doRegReadMem + assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = + coreFix_memExe_dispToRegQ$RDY_deq && + coreFix_memExe_regToExeQ$RDY_enq && + coreFix_memExe_dispToRegQ$RDY_first && + sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d2762 ; + assign WILL_FIRE_RL_coreFix_memExe_doRegReadMem = + CAN_FIRE_RL_coreFix_memExe_doRegReadMem && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && + !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; + + // rule RL_coreFix_memExe_doDispatchMem + assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = + coreFix_memExe_dispToRegQ$RDY_enq && + coreFix_memExe_rsMem$RDY_dispatchData && + coreFix_memExe_rsMem$RDY_doDispatch ; + assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = + CAN_FIRE_RL_coreFix_memExe_doDispatchMem && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && + !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; + + // rule RL_coreFix_memExe_reqLrScAmoQ_full_canon + assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ; + + // rule RL_coreFix_memExe_reqLrScAmoQ_empty_canon + assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ; + + // rule RL_coreFix_memExe_reqLrScAmoQ_data_0_canon + assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ; + + // rule RL_coreFix_fpuMulDivExe_0_doFinishFpSimple + assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple = + coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq && + coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first && + rob$RDY_setExecuted_doFinishFpuMulDiv_0_set ; + assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple = + CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; + + // rule RL_coreFix_fpuMulDivExe_0_doFinishFpFma + assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq && + coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d7985 ; + assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma = + CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; + + // rule RL_coreFix_fpuMulDivExe_0_doFinishFpDiv + assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv = + coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq && + coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d9382 ; + assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv = + CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; + + // rule RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt + assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq && + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d10779 ; + assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt = + CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; + + // rule RL_coreFix_fpuMulDivExe_0_doFinishIntMul + assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul = + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq && + coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d12176 ; + assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul = + CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; + + // rule RL_coreFix_fpuMulDivExe_0_doFinishIntDiv + assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv = + coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq && + coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d12228 ; + assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv = + CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; + // rule RL_coreFix_memExe_doIssueLdFromIssueQ assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ = coreFix_memExe_lsq$RDY_getIssueLd && !coreFix_memExe_forwardQ_full && - NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473 ; + !coreFix_memExe_reqLdQ_full_rl ; assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ = CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -9943,7 +10093,7 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doIssueLdFromUpdate assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate = !coreFix_memExe_forwardQ_full && - NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473 && + !coreFix_memExe_reqLdQ_full_rl && coreFix_memExe_issueLd$whas ; assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate = CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && @@ -9957,16 +10107,21 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_lsq$firstSt[4] ; + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$firstSt[13] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -9975,11 +10130,11 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_Fence assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && - !coreFix_memExe_lsq$firstSt[4] && - coreFix_memExe_lsq$firstSt[158:157] == 2'd3 && - (!coreFix_memExe_lsq$firstSt[151] || + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && + !coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[240:239] == 2'd3 && + (!coreFix_memExe_lsq$firstSt[233] || coreFix_memExe_stb$isEmpty) ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && @@ -9987,7 +10142,12 @@ module mkCore(CLK, !WILL_FIRE_RL_commitStage_doCommitTrap_flush && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -9998,8 +10158,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -10009,9 +10169,14 @@ module mkCore(CLK, !WILL_FIRE_RL_commitStage_doCommitTrap_flush && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - !WILL_FIRE_RL_coreFix_memExe_doFinishMem && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && @@ -10020,12 +10185,12 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_MMIO_deq assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq = !mmio_dataRespQ_empty && - NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 && + NOT_mmio_dataPendQ_empty_80_378_AND_rob_RDY_se_ETC___d1379 && coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 && coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 && coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 && !coreFix_memExe_waitLrScAmoMMIOResp[0] && - mmio_dataRespQ_data_0[64] ; + mmio_dataRespQ_data_0[129] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && @@ -10034,9 +10199,14 @@ module mkCore(CLK, !WILL_FIRE_RL_commitStage_doCommitTrap_flush && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - !WILL_FIRE_RL_coreFix_memExe_doFinishMem && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && @@ -10045,12 +10215,12 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_MMIO_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault = !mmio_dataRespQ_empty && - NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 && + NOT_mmio_dataPendQ_empty_80_378_AND_rob_RDY_se_ETC___d1379 && coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 && coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 && coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 && !coreFix_memExe_waitLrScAmoMMIOResp[0] && - !mmio_dataRespQ_data_0[64] ; + !mmio_dataRespQ_data_0[129] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && @@ -10059,7 +10229,12 @@ module mkCore(CLK, !WILL_FIRE_RL_commitStage_doCommitTrap_flush && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; @@ -10097,21 +10272,17 @@ module mkCore(CLK, // rule RL_coreFix_memExe_sendLdToMem assign CAN_FIRE_RL_coreFix_memExe_sendLdToMem = - (!coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT || - !coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT || - coreFix_memExe_reqLdQ_empty_lat_0$whas || - !coreFix_memExe_reqLdQ_empty_rl) && - NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 ; + !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl && + (coreFix_memExe_reqLdQ_empty_lat_0$whas || + !coreFix_memExe_reqLdQ_empty_rl) ; assign WILL_FIRE_RL_coreFix_memExe_sendLdToMem = CAN_FIRE_RL_coreFix_memExe_sendLdToMem && !WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ; // rule RL_coreFix_memExe_sendStToMem assign CAN_FIRE_RL_coreFix_memExe_sendStToMem = - NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 && - (!coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT || - !coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT || - CAN_FIRE_RL_coreFix_memExe_doIssueSB || + !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl && + (CAN_FIRE_RL_coreFix_memExe_doIssueSB || !coreFix_memExe_reqStQ_empty_rl) ; assign WILL_FIRE_RL_coreFix_memExe_sendStToMem = CAN_FIRE_RL_coreFix_memExe_sendStToMem && @@ -10121,9 +10292,9 @@ module mkCore(CLK, // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq = coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first && - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2104 && - !coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5017 && + !coreFix_memExe_dMem_cache_m_banks_0_processAmo[234] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[583:582] == 2'd0 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && @@ -10133,11 +10304,11 @@ module mkCore(CLK, // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs = coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first && - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2673 && - !coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] != + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6771 && + !coreFix_memExe_dMem_cache_m_banks_0_processAmo[234] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[583:582] != 2'd0 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] != + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[583:582] != 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && @@ -10146,87 +10317,28 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_St_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = - coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && - !coreFix_memExe_lsq$firstSt[4] && - coreFix_memExe_lsq$firstSt[158:157] == 2'd0 && - !coreFix_memExe_lsq$firstSt[77] && + coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && + !coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[240:239] == 2'd0 && + !coreFix_memExe_lsq$firstSt[159] && coreFix_memExe_stb$getEnqIndex[2] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && - !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - // rule RL_coreFix_memExe_doRespLdMem - assign CAN_FIRE_RL_coreFix_memExe_doRespLdMem = - !coreFix_memExe_memRespLdQ_empty ; - assign WILL_FIRE_RL_coreFix_memExe_doRespLdMem = - CAN_FIRE_RL_coreFix_memExe_doRespLdMem && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ; - - // rule RL_coreFix_memExe_doRespLdForward - assign CAN_FIRE_RL_coreFix_memExe_doRespLdForward = - !coreFix_memExe_forwardQ_empty ; - assign WILL_FIRE_RL_coreFix_memExe_doRespLdForward = - CAN_FIRE_RL_coreFix_memExe_doRespLdForward && - !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ; - - // rule RL_coreFix_memExe_doExeMem - assign CAN_FIRE_RL_coreFix_memExe_doExeMem = - coreFix_memExe_regToExeQ$RDY_deq && - coreFix_memExe_regToExeQ$RDY_first && - coreFix_memExe_dTlb$RDY_procReq ; - assign WILL_FIRE_RL_coreFix_memExe_doExeMem = - CAN_FIRE_RL_coreFix_memExe_doExeMem ; - - // rule RL_prepareCachesAndTlbs - assign CAN_FIRE_RL_prepareCachesAndTlbs = - (!flush_tlbs || - coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush) && - (flush_reservation || flush_tlbs || update_vm_info) ; - assign WILL_FIRE_RL_prepareCachesAndTlbs = - CAN_FIRE_RL_prepareCachesAndTlbs ; - - // rule RL_coreFix_memExe_doRegReadMem - assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = - coreFix_memExe_dispToRegQ$RDY_deq && - coreFix_memExe_regToExeQ$RDY_enq && - coreFix_memExe_dispToRegQ$RDY_first && - sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631 ; - assign WILL_FIRE_RL_coreFix_memExe_doRegReadMem = - CAN_FIRE_RL_coreFix_memExe_doRegReadMem && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && - !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - - // rule RL_coreFix_memExe_doDispatchMem - assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = - coreFix_memExe_dispToRegQ$RDY_enq && - coreFix_memExe_rsMem$RDY_doDispatch && - coreFix_memExe_rsMem$RDY_dispatchData ; - assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = - CAN_FIRE_RL_coreFix_memExe_doDispatchMem && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && - !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q257 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q318 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ; @@ -10241,9 +10353,7 @@ module mkCore(CLK, // rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new = - (!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT || - !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT || - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas || + (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas || !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl) && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit && @@ -10257,7 +10367,7 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q319 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ; @@ -10393,44 +10503,36 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ; - // rule RL_coreFix_memExe_reqLrScAmoQ_full_canon - assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ; - - // rule RL_coreFix_memExe_reqLrScAmoQ_data_0_canon - assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ; - - // rule RL_coreFix_memExe_reqLrScAmoQ_empty_canon - assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ; - // rule RL_coreFix_memExe_reqLdQ_full_canon assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ; - // rule RL_coreFix_memExe_reqLdQ_empty_canon - assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ; - // rule RL_coreFix_memExe_reqLdQ_data_0_canon assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ; + // rule RL_coreFix_memExe_reqLdQ_empty_canon + assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ; + // rule RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv = coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq && coreFix_fpuMulDivExe_0_regToExeQ$RDY_first && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8427 ; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12563 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; + CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && + !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq && coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq && coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first && - sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8292 ; + sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12425 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10441,8 +10543,8 @@ module mkCore(CLK, // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ; + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10462,69 +10564,49 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && + epochManager$RDY_incrementEpoch && fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12885 ; + rob$RDY_enqPort_0_enq && + mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20457 && + rob$isEmpty && + rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_Trap = CAN_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_rl_debug_halt_req ; // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = epochManager$RDY_incrementEpoch && - rob_RDY_enqPort_0_enq__2627_AND_regRenamingTab_ETC___d13095 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13147 && - rob$isEmpty ; + fetchStage$RDY_pipelines_0_first && + fetchStage_RDY_pipelines_0_deq__0048_AND_regRe_ETC___d20817 && + mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20869 && + rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = CAN_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_rl_debug_halt_req ; // rule RL_csrInstOrInterruptInflight_canon assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ; assign WILL_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ; - // rule RL_commitStage_doSetLSQAtCommit - assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit = - MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 || - WILL_FIRE_RL_commitStage_notifyLSQCommit ; - assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit = - CAN_FIRE_RL_commitStage_doSetLSQAtCommit ; - - // rule RL_commitStage_doSetLSQAtCommit_1 - assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 = - WILL_FIRE_RL_commitStage_doCommitNormalInst && - rob$deqPort_1_canDeq && - rob$deqPort_1_deq_data[25] && - !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] != 5'd0 && - rob$deqPort_1_deq_data[186:182] != 5'd21 && - rob$deqPort_1_deq_data[186:182] != 5'd17 && - rob$deqPort_1_deq_data[186:182] != 5'd18 && - rob$deqPort_1_deq_data[186:182] != 5'd13 && - rob$deqPort_1_deq_data[186:182] != 5'd16 && - rob$deqPort_1_deq_data[186:182] != 5'd15 && - rob$deqPort_1_deq_data[186:182] != 5'd19 && - rob$deqPort_1_deq_data[186:182] != 5'd20 && - rob$deqPort_1_deq_data[13] ; - assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1 = - CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ; - // rule RL_renameStage_doRenaming assign CAN_FIRE_RL_renameStage_doRenaming = (!fetchStage$pipelines_0_canDeq || - IF_fetchStage_RDY_pipelines_0_first__2602_AND__ETC___d13214) && - IF_NOT_fetchStage_pipelines_0_canDeq__2603_260_ETC___d13656 && - IF_NOT_fetchStage_pipelines_0_canDeq__2603_260_ETC___d13664 && - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13828 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13831 ; + IF_fetchStage_RDY_pipelines_0_first__0042_AND__ETC___d20964) && + IF_NOT_fetchStage_pipelines_0_canDeq__0043_004_ETC___d21586 && + IF_NOT_fetchStage_pipelines_0_canDeq__0043_004_ETC___d21594 && + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21768 && + mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21772 ; assign WILL_FIRE_RL_renameStage_doRenaming = CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_rl_debug_halt_req ; // rule RL_mmio_pRqQ_canonicalize assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ; @@ -10546,7 +10628,50 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ; assign WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ; + // rule RL_commitStage_doSetLSQAtCommit + assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit = + MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 || + WILL_FIRE_RL_commitStage_notifyLSQCommit ; + assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit = + CAN_FIRE_RL_commitStage_doSetLSQAtCommit ; + + // rule RL_commitStage_doSetLSQAtCommit_1 + assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 = + WILL_FIRE_RL_commitStage_doCommitNormalInst && + rob$deqPort_1_canDeq && + rob$deqPort_1_deq_data[25] && + !rob$deqPort_1_deq_data[18] && + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] != 5'd0 && + rob$deqPort_1_deq_data[469:465] != 5'd26 && + rob$deqPort_1_deq_data[469:465] != 5'd22 && + rob$deqPort_1_deq_data[469:465] != 5'd23 && + rob$deqPort_1_deq_data[469:465] != 5'd17 && + rob$deqPort_1_deq_data[469:465] != 5'd18 && + rob$deqPort_1_deq_data[469:465] != 5'd21 && + rob$deqPort_1_deq_data[469:465] != 5'd20 && + rob$deqPort_1_deq_data[469:465] != 5'd24 && + rob$deqPort_1_deq_data[469:465] != 5'd25 && + rob$deqPort_1_deq_data[13] ; + assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1 = + CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ; + // inputs to muxes for submodule ports + assign MUX_regRenamingTable$rename_0_getRename_1__SEL_1 = + WILL_FIRE_RL_renameStage_doRenaming || + WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; + assign MUX_regRenamingTable$rename_0_getRename_1__SEL_2 = + WILL_FIRE_RL_rl_debug_gpr_write || + WILL_FIRE_RL_rl_debug_gpr_read ; + assign MUX_regRenamingTable$rename_0_getRename_1__SEL_3 = + WILL_FIRE_RL_rl_debug_fpr_write || + WILL_FIRE_RL_rl_debug_fpr_read ; + assign MUX_commitStage_rg_run_state$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + NOT_commitStage_commitTrap_2029_BITS_44_TO_43__ETC___d22295 ; + assign MUX_commitStage_rg_serial_num$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 ; assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && @@ -10557,160 +10682,140 @@ module mkCore(CLK, assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ; - assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; - assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 = + assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ; - assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 = + assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ; - assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 = + assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ; - assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 = + assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ; + assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 = + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 && - coreFix_memExe_lsq$firstSt[150] ; + coreFix_memExe_lsq$firstSt[232] ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 = WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 && - coreFix_memExe_lsq$firstLd[89] ; + coreFix_memExe_lsq$firstLd[106] ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5594 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0 && coreFix_memExe_lsq$getHit[8] && !coreFix_memExe_lsq$getHit[9] ; assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 && - coreFix_memExe_lsq$firstSt[150] ; + coreFix_memExe_lsq$firstSt[232] ; assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 && - coreFix_memExe_lsq$firstLd[89] ; + coreFix_memExe_lsq$firstLd[106] ; assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 && - coreFix_memExe_lsq$firstSt[150] ; + coreFix_memExe_lsq$firstSt[232] ; assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 && - coreFix_memExe_lsq$firstLd[89] ; + coreFix_memExe_lsq$firstLd[106] ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2595 ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5571 ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != 3'd4 ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2527 || - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2531) ; - assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5506 ; + assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2578 ; - assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5554 ; + assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_2 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd2 || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3) ; - assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 = + assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_3 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq && - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2723 && - coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] == - 2'd0 ; + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d6972 ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != 3'd4 || - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013) || - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2119) ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932) || + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5032) ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd4 || - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2634) ; + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5610) ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd4 ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696 ; + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575] && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6940 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6943 ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2662 ; + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6761 ; + assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 = + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ; assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && - coreFix_memExe_lsq$issueLd[74:73] != 2'd0 && - coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ; - assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 = - WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && - coreFix_memExe_lsq$issueLd[74:73] != 2'd0 && - coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ; + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 ; assign MUX_coreFix_memExe_lsq$getHit_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd0 || - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2601) ; - assign MUX_coreFix_memExe_lsq$getHit_1__SEL_2 = - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd0 ; + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573 || + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) ; assign MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd1 || - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2626) ; + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598 || + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) ; assign MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && - coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ; - assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 = + coreFix_memExe_lsq$issueLd[139:138] == 2'd0 ; + assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2561 ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5535 ; assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 && - coreFix_memExe_lsq$firstSt[150] ; + coreFix_memExe_lsq$firstSt[232] ; assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 && - coreFix_memExe_lsq$firstLd[89] ; + coreFix_memExe_lsq$firstLd[106] ; assign MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault || @@ -10720,575 +10825,718 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ; assign MUX_coreFix_trainBPQ_0$enq_1__SEL_1 = WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && - (coreFix_aluExe_0_exeToFinQ$first[325:321] == 5'd9 || - coreFix_aluExe_0_exeToFinQ$first[325:321] == 5'd10) ; + (coreFix_aluExe_0_exeToFinQ$first[1066:1062] == 5'd9 || + coreFix_aluExe_0_exeToFinQ$first[1066:1062] == 5'd12 || + coreFix_aluExe_0_exeToFinQ$first[1066:1062] == 5'd11 || + coreFix_aluExe_0_exeToFinQ$first[1066:1062] == 5'd10) ; assign MUX_coreFix_trainBPQ_1$enq_1__SEL_1 = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && - (coreFix_aluExe_1_exeToFinQ$first[325:321] == 5'd9 || - coreFix_aluExe_1_exeToFinQ$first[325:321] == 5'd10) ; - assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 ; - assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap[4] ; - assign MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2 = + (coreFix_aluExe_1_exeToFinQ$first[1066:1062] == 5'd9 || + coreFix_aluExe_1_exeToFinQ$first[1066:1062] == 5'd12 || + coreFix_aluExe_1_exeToFinQ$first[1066:1062] == 5'd11 || + coreFix_aluExe_1_exeToFinQ$first[1066:1062] == 5'd10) ; + assign MUX_csrInstOrInterruptInflight_lat_1$wset_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming_Trap && - !fetchStage$pipelines_0_first[68] && - (IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[12] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[13] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[14]) ; - assign MUX_csrf_debug_int_pend$write_1__SEL_1 = + (renameStage_rg_m_halt_req[4] || + NOT_fetchStage_pipelines_0_first__0045_BIT_69__ETC___d20784 || + fetchStage_pipelines_0_first__0045_BIT_69_0074_ETC___d20559 && + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20801 == + 4'd3) ; + assign MUX_csrf_external_int_en_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd29 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd9 || + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd23) ; + assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd772 ; assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd16 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd29) ; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd30) ; + assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 = + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd324 || + f_csr_reqs$D_OUT[75:64] == 12'd836) ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitNormalInst && + NOT_IF_NOT_rob_deqPort_0_canDeq__3151_3152_OR__ETC___d23397 ; + assign MUX_csrf_fflags_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd0 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd2) ; - assign MUX_csrf_fs_reg$write_1__SEL_1 = + assign MUX_csrf_fflags_reg$write_1__SEL_3 = + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd1 || + f_csr_reqs$D_OUT[75:64] == 12'd3) ; + assign MUX_csrf_frm_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd0 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd1 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd2) ; + assign MUX_csrf_fs_reg$write_1__SEL_2 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd0 || + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd1 || + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd2 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd8 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18) ; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd19) ; + assign MUX_csrf_fs_reg$write_1__SEL_3 = + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd1 || + f_csr_reqs$D_OUT[75:64] == 12'd2 || + f_csr_reqs$D_OUT[75:64] == 12'd3 || + f_csr_reqs$D_OUT[75:64] == 12'd256 || + f_csr_reqs$D_OUT[75:64] == 12'd768) ; + assign MUX_csrf_ie_vec_0$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd8 || + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd19) ; + assign MUX_csrf_ie_vec_0$write_1__SEL_2 = + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd256 || + f_csr_reqs$D_OUT[75:64] == 12'd768) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2633_ULE_1_4189_4253_OR_ETC___d14257 ; - assign MUX_csrf_mpp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; - assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_prv_reg$write_1__SEL_1 = + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + NOT_csrf_prv_reg_read__0075_ULE_1_2375_2490_OR_ETC___d22495 ; + assign MUX_csrf_ie_vec_3$write_1__SEL_3 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd768 ; + assign MUX_csrf_mcause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && - (rob$deqPort_0_deq_data[186:182] == 5'd19 || - rob$deqPort_0_deq_data[186:182] == 5'd20) ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd28 ; + assign MUX_csrf_mcause_code_reg$write_1__SEL_3 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd834 ; + assign MUX_csrf_mccsr_reg$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd3008 ; + assign MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd774 ; + assign MUX_csrf_mcycle_ehr_data_lat_0$wset_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd2816 ; + assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd770 ; + assign MUX_csrf_mideleg_11_reg$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd771 ; + assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd2818 ; + assign MUX_csrf_mpp_reg$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; + assign MUX_csrf_mscratch_csr$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd832 ; + assign MUX_csrf_mtval_csr$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd29 ; + assign MUX_csrf_mtval_csr$write_1__SEL_3 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd835 ; + assign MUX_csrf_ppn_reg$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd384 ; + assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; + assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; + assign MUX_csrf_prv_reg$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + assign MUX_csrf_prv_reg$write_1__SEL_3 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1968 ; + assign MUX_csrf_rg_dcsr$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd42 ; + assign MUX_csrf_rg_dscratch0$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1970 ; + assign MUX_csrf_rg_dscratch1$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1971 ; + assign MUX_csrf_rg_tdata1_data$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1953 ; + assign MUX_csrf_rg_tdata2$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1954 ; + assign MUX_csrf_rg_tdata3$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1955 ; + assign MUX_csrf_rg_tselect$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1952 ; + assign MUX_csrf_scause_code_reg$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd14 ; + assign MUX_csrf_scause_code_reg$write_1__SEL_3 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd322 ; + assign MUX_csrf_scounteren_cy_reg$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd262 ; assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; + assign MUX_csrf_sscratch_csr$write_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd320 ; + assign MUX_csrf_stats_module_writeQ$enq_1__SEL_1 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd2049 ; + assign MUX_csrf_stval_csr$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd15 ; + assign MUX_csrf_stval_csr$write_1__SEL_3 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd323 ; assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13834 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 ; + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21775 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21020 ; assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13928 && - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13938 && - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13650 ; - assign MUX_flush_reservation$write_1__SEL_1 = + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21880 && + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21891 && + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21580 ; + assign MUX_f_run_halt_rsps$enq_1__SEL_1 = + WILL_FIRE_RL_rl_debug_halted || + WILL_FIRE_RL_rl_debug_halt_req_already_halted ; + assign MUX_flush_reservation$write_1__SEL_2 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; + assign MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 = + WILL_FIRE_RL_renameStage_doRenaming_SystemInst || + WILL_FIRE_RL_renameStage_doRenaming_Trap ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_1 = + MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 && + csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = + WILL_FIRE_RL_renameStage_doRenaming && + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21880 && + csrf_rg_dcsr[2] ; assign MUX_rf$write_3_wr_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && - coreFix_memExe_lsq$firstSt[150] ; + coreFix_memExe_lsq$firstSt[232] ; assign MUX_rf$write_3_wr_1__SEL_2 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && - coreFix_memExe_lsq$firstSt[150] ; + coreFix_memExe_lsq$firstSt[232] ; assign MUX_rf$write_3_wr_1__SEL_3 = WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && - coreFix_memExe_lsq$firstLd[89] ; + coreFix_memExe_lsq$firstLd[106] ; assign MUX_rf$write_3_wr_1__SEL_4 = WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && - coreFix_memExe_lsq$firstLd[89] ; + coreFix_memExe_lsq$firstLd[106] ; assign MUX_rf$write_3_wr_1__PSEL_5 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || WILL_FIRE_RL_coreFix_memExe_doRespLdMem ; assign MUX_rf$write_3_wr_1__SEL_5 = - MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ; + MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[137] ; assign MUX_rf$write_3_wr_2__SEL_5 = - MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ; + MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[137] ; + assign MUX_rg_core_run_state$write_1__SEL_4 = + WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ; assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ; assign MUX_sbAggr$setReady_4_put_1__SEL_1 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 && - coreFix_memExe_lsq$firstSt[150] ; + coreFix_memExe_lsq$firstSt[232] ; assign MUX_sbAggr$setReady_4_put_1__SEL_2 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 && - coreFix_memExe_lsq$firstLd[89] ; + coreFix_memExe_lsq$firstLd[106] ; assign MUX_sbCons$setReady_3_put_1__SEL_1 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 && - coreFix_memExe_lsq$firstSt[150] ; + coreFix_memExe_lsq$firstSt[232] ; assign MUX_sbCons$setReady_3_put_1__SEL_2 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 && - coreFix_memExe_lsq$firstLd[89] ; + coreFix_memExe_lsq$firstLd[106] ; assign MUX_sbCons$setReady_3_put_1__SEL_3 = - MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ; - assign MUX_update_vm_info$write_1__SEL_1 = - WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ; + MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[137] ; + assign MUX_started$write_1__SEL_1 = + CAN_FIRE_RL_rl_debug_resume && + !WILL_FIRE_RL_prepareCachesAndTlbs ; + assign MUX_regRenamingTable$rename_0_getRename_1__VAL_2 = + { 2'd2, f_gpr_reqs$D_OUT[68:64], 20'd345386 } ; + assign MUX_regRenamingTable$rename_0_getRename_1__VAL_3 = + { 2'd3, f_fpr_reqs$D_OUT[68:64], 20'd345386 } ; assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, - rob$deqPort_0_deq_data[282:219], - x__h688723, - rob$deqPort_0_deq_data[166], - rob$deqPort_0_deq_data[166] ? - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q259 : - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 } ; - assign MUX_commitStage_rg_instret$write_1__VAL_1 = - commitStage_rg_instret + 64'd1 ; - assign MUX_commitStage_rg_instret$write_1__VAL_2 = - commitStage_rg_instret + y__h705648 ; + rob$deqPort_0_deq_data[630:502], + addr__h986843, + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q323, + rob$deqPort_0_deq_data[501:470] } ; + assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = + commitStage_rg_serial_num + 64'd1 ; + assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = + commitStage_rg_serial_num + y__h1010667 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h661043 == 1'd0 && - fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837) ? - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], + (k__h942381 == 1'd0 && fetchStage$pipelines_0_canDeq && + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21777) ? + { fetchStage$pipelines_0_first[272:268], + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20171, + IF_fetchStage_pipelines_0_first__0045_BITS_237_ETC___d20400, + fetchStage$pipelines_0_first[328:305], regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, - fetchStage$pipelines_0_first[194:192] == 3'd1, + fetchStage$pipelines_0_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : - { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361, - fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437, - fetchStage$pipelines_1_first[160:128], - fetchStage$pipelines_1_first[255:232], + { fetchStage$pipelines_1_first[272:268], + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21119, + IF_fetchStage_pipelines_1_first__0054_BITS_237_ETC___d21348, + fetchStage$pipelines_1_first[328:305], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675346, - fetchStage$pipelines_1_first[194:192] == 3'd1, + renaming_spec_bits__h965955, + fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], + { fetchStage$pipelines_0_first[272:268], + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20171, + IF_fetchStage_pipelines_0_first__0045_BITS_237_ETC___d20400, + fetchStage$pipelines_0_first[328:305], regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, 5'd10, sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = - { 1'd1, - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25] } ; - assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; - assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 = + assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25] } ; - assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 = + assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25] } ; - assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 = + assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25] } ; - assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6 = + assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 = { 1'd1, coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25] } ; + assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6 = + { 1'd1, + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 = - { 1'd1, coreFix_memExe_lsq$firstSt[149:143] } ; + { 1'd1, coreFix_memExe_lsq$firstSt[231:225] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 = - { 1'd1, coreFix_memExe_lsq$firstLd[88:82] } ; + { 1'd1, coreFix_memExe_lsq$firstLd[105:99] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 = { 1'd1, coreFix_memExe_lsq$getHit[7:1] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? - (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ? + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] ? + (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 ? 3'd3 : 3'd5) : - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535 ; + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5509 ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? - (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ? - { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571], - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516], - 53'h15555555555555 } : - 58'h155555555555554) : - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546 ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] ? + (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 ? + { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:576], + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520], + 54'h15555555555555 } : + 59'h295555555555554) : + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5520 ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 = - { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571], - 55'h15555555555555 } ; + { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:576], + 56'h15555555555555 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? - { (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] ? + { (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd2, - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } : - { coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd2, - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[221:164] } : + { coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5559, + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[221:164] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 = - { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd2, - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[221:164] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? - { coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] ? + { coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } : { (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != 3'd1) && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? - (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ? - IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2506 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0]) : - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2519 ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] ? + (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 ? + IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d5480 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:0]) : + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5493 ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 = - { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96], - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140, - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 } ; + { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[221:169], + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5053, + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5470 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 = - { coreFix_memExe_dMem_cache_m_banks_0_processAmo[151:100], + { coreFix_memExe_dMem_cache_m_banks_0_processAmo[225:173], 2'd3, coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0], - IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004, - (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == - 3'd0) ? - n__h191675 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; + IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4914, + IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4925 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = - { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ; + { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d6956, + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) : - NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2522 ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] ? + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) : + NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d5496 ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = - { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h283066 } ; + { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[221:158], + x__h501025 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = - { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h284511, - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; + { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, + IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7018 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = - { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871, + { 522'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7038, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h287287, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941 } ; + addr__h505543, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7126 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574], + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 = { 1'd1, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512], + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[518:516], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h152884, x__h152890, 84'h82AAAAAAAAAAAAAAAAAAA } ; + coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? + coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget : + coreFix_memExe_reqLrScAmoQ_data_0_rl ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h156431, x__h156437, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h148960, + addr__h148408, + 158'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h159247, - x__h159251, - IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, - IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247, - x__h161099, - IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 } ; + { x__h152094, + addr__h151984, + 158'h32AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 = { 1'd1, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 = { 1'd0, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h289191, + resp_addr__h509039, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; + assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = + { prv__h1011781, + prv__h1011781 != 2'd3 && csrf_vm_mode_sv39_reg, + csrf_mxr_reg, + csrf_sum_reg, + csrf_ppn_reg } ; assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - coreFix_memExe_lsq$getIssueLd[76:72], - coreFix_memExe_lsq$issueLd[63:0] } ; + coreFix_memExe_lsq$getIssueLd[84:80], + coreFix_memExe_lsq$issueLd[128:0] } ; assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, - coreFix_memExe_issueLd$wget[76:72], - coreFix_memExe_lsq$issueLd[63:0] } ; + coreFix_memExe_issueLd$wget[84:80], + coreFix_memExe_lsq$issueLd[128:0] } ; assign MUX_coreFix_memExe_lsq$getHit_1__VAL_1 = { 1'd0, - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148] } ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[226:222] } ; assign MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 = - { coreFix_memExe_stb$search[67], - coreFix_memExe_stb$search[67] ? - coreFix_memExe_stb$search[66:65] : + { coreFix_memExe_stb$search[132], + coreFix_memExe_stb$search[132] ? + coreFix_memExe_stb$search[131:130] : 2'h2, - coreFix_memExe_stb$search[64], - coreFix_memExe_stb$search[64] ? - coreFix_memExe_stb$search[63:0] : - 64'hAAAAAAAAAAAAAAAA } ; - always@(coreFix_memExe_memRespLdQ_deqP or - coreFix_memExe_memRespLdQ_data_0 or - coreFix_memExe_memRespLdQ_data_1) - begin - case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: - MUX_coreFix_memExe_lsq$respLd_1__VAL_1 = - coreFix_memExe_memRespLdQ_data_0[68:64]; - 1'd1: - MUX_coreFix_memExe_lsq$respLd_1__VAL_1 = - coreFix_memExe_memRespLdQ_data_1[68:64]; - endcase - end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - MUX_coreFix_memExe_lsq$respLd_1__VAL_2 = - coreFix_memExe_forwardQ_data_0[68:64]; - 1'd1: - MUX_coreFix_memExe_lsq$respLd_1__VAL_2 = - coreFix_memExe_forwardQ_data_1[68:64]; - endcase - end - always@(coreFix_memExe_memRespLdQ_deqP or - coreFix_memExe_memRespLdQ_data_0 or - coreFix_memExe_memRespLdQ_data_1) - begin - case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: - MUX_coreFix_memExe_lsq$respLd_2__VAL_1 = - coreFix_memExe_memRespLdQ_data_0[63:0]; - 1'd1: - MUX_coreFix_memExe_lsq$respLd_2__VAL_1 = - coreFix_memExe_memRespLdQ_data_1[63:0]; - endcase - end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - MUX_coreFix_memExe_lsq$respLd_2__VAL_2 = - coreFix_memExe_forwardQ_data_0[63:0]; - 1'd1: - MUX_coreFix_memExe_lsq$respLd_2__VAL_2 = - coreFix_memExe_forwardQ_data_1[63:0]; - endcase - end + coreFix_memExe_stb$search[129], + coreFix_memExe_stb$search[129] ? + coreFix_memExe_stb$search[128:0] : + 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + assign MUX_coreFix_memExe_lsq$respLd_2__VAL_1 = + { CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q324, + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147, + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 } ; + assign MUX_coreFix_memExe_lsq$respLd_2__VAL_2 = + { CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q325, + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230, + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 } ; assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h194347 } ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[226:222], + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5062, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, - coreFix_memExe_lsq$firstSt[141:78], + coreFix_memExe_lsq$firstSt[223:160], 2'd3, - (coreFix_memExe_lsq$firstSt[158:157] == 2'd1) ? 3'd3 : 3'd4, - coreFix_memExe_lsq$firstSt[76:5], - coreFix_memExe_lsq$firstSt[156:153], - coreFix_memExe_lsq$firstSt[69] && - coreFix_memExe_lsq$firstSt[70] && - coreFix_memExe_lsq$firstSt[71] && - coreFix_memExe_lsq$firstSt[72] && - coreFix_memExe_lsq$firstSt[73] && - coreFix_memExe_lsq$firstSt[74] && - coreFix_memExe_lsq$firstSt[75] && - coreFix_memExe_lsq$firstSt[76], - coreFix_memExe_lsq$firstSt[152:151] } ; + (coreFix_memExe_lsq$firstSt[240:239] == 2'd1) ? 3'd3 : 3'd4, + coreFix_memExe_lsq$firstSt[158:14], + coreFix_memExe_lsq$firstSt[238:235], + (coreFix_memExe_lsq$firstSt[158:143] == 16'd65535) ? + 2'd0 : + ((coreFix_memExe_lsq$firstSt[158:151] == 8'd255 || + coreFix_memExe_lsq$firstSt[150:143] == 8'd255) ? + 2'd1 : + 2'd2), + coreFix_memExe_lsq$firstSt[234:233] } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 = { 5'd0, - coreFix_memExe_lsq$firstLd[80:17], - 84'h92AAAAAAAAAAAAAAAAAAA } ; + coreFix_memExe_lsq$firstLd[97:34], + 158'h24AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? - ((!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ? - { 1'd1, - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 } : - 65'h10000000000000001) : - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2566 ; - assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 = - { 1'd1, - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 } ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] ? + ((!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5540 : + 130'h200000000000000000000000000000001) : + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5542 ; assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, - coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h190137 : - { {32{x__h190900[31]}}, x__h190900 } } ; + coreFix_memExe_dMem_cache_m_banks_0_processAmo[7:6] == 2'd0 && + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4836, + IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4873 } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = - { coreFix_aluExe_0_exeToFinQ$first[146:19], - coreFix_aluExe_0_exeToFinQ$first[325:321], - coreFix_aluExe_0_exeToFinQ$first[18], - coreFix_aluExe_0_exeToFinQ$first[299:276], - 1'd0 } ; + { x__h912077, + new_pc__h909530, + coreFix_aluExe_0_exeToFinQ$first[1066:1062], + coreFix_aluExe_0_exeToFinQ$first[297], + coreFix_aluExe_0_exeToFinQ$first[1040:1017], + 1'd0, + coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 = - { coreFix_aluExe_0_exeToFinQ$first[146:19], - coreFix_aluExe_0_exeToFinQ$first[325:321], - coreFix_aluExe_0_exeToFinQ$first[18], - coreFix_aluExe_0_exeToFinQ$first[299:276], - 1'd1 } ; + { x__h912077, + new_pc__h909530, + coreFix_aluExe_0_exeToFinQ$first[1066:1062], + coreFix_aluExe_0_exeToFinQ$first[297], + coreFix_aluExe_0_exeToFinQ$first[1040:1017], + 1'd1, + coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 = - { coreFix_aluExe_1_exeToFinQ$first[146:19], - coreFix_aluExe_1_exeToFinQ$first[325:321], - coreFix_aluExe_1_exeToFinQ$first[18], - coreFix_aluExe_1_exeToFinQ$first[299:276], - 1'd0 } ; + { x__h878565, + new_pc__h871587, + coreFix_aluExe_1_exeToFinQ$first[1066:1062], + coreFix_aluExe_1_exeToFinQ$first[297], + coreFix_aluExe_1_exeToFinQ$first[1040:1017], + 1'd0, + coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 = - { coreFix_aluExe_1_exeToFinQ$first[146:19], - coreFix_aluExe_1_exeToFinQ$first[325:321], - coreFix_aluExe_1_exeToFinQ$first[18], - coreFix_aluExe_1_exeToFinQ$first[299:276], - 1'd1 } ; - assign MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 = - MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || - MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; - assign MUX_csrf_fflags_reg$write_1__VAL_2 = - csrf_fflags_reg | fflags__h705625 ; - always@(IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 or - robdeqPort_0_deq_data_BITS_95_TO_32__q261) + { x__h878565, + new_pc__h871587, + coreFix_aluExe_1_exeToFinQ$first[1066:1062], + coreFix_aluExe_1_exeToFinQ$first[297], + coreFix_aluExe_1_exeToFinQ$first[1040:1017], + 1'd1, + coreFix_aluExe_1_exeToFinQ$first[1016] } ; + assign MUX_csrf_fflags_reg$write_1__VAL_1 = + csrf_fflags_reg | fflags__h1010644 ; + assign MUX_csrf_frm_reg$write_1__VAL_1 = + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd1) ? + robdeqPort_0_deq_data_BITS_95_TO_32__q326[2:0] : + robdeqPort_0_deq_data_BITS_95_TO_32__q326[7:5] ; + assign MUX_csrf_frm_reg$write_1__VAL_2 = + (f_csr_reqs$D_OUT[75:64] == 12'd2) ? + f_csr_reqs$D_OUT[2:0] : + f_csr_reqs$D_OUT[7:5] ; + always@(IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 or + robdeqPort_0_deq_data_BITS_95_TO_32__q326) begin - case (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351) - 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_1 = 2'b11; - default: MUX_csrf_fs_reg$write_1__VAL_1 = - robdeqPort_0_deq_data_BITS_95_TO_32__q261[14:13]; + case (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785) + 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; + default: MUX_csrf_fs_reg$write_1__VAL_2 = + robdeqPort_0_deq_data_BITS_95_TO_32__q326[14:13]; + endcase + end + always@(f_csr_reqs$D_OUT) + begin + case (f_csr_reqs$D_OUT[75:64]) + 12'd1, 12'd2, 12'd3: MUX_csrf_fs_reg$write_1__VAL_3 = 2'b11; + default: MUX_csrf_fs_reg$write_1__VAL_3 = f_csr_reqs$D_OUT[14:13]; endcase end assign MUX_csrf_ie_vec_1$write_1__VAL_1 = - (rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + (rob$deqPort_0_deq_data[469:465] == 5'd17 && + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd8 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18)) ? - robdeqPort_0_deq_data_BITS_95_TO_32__q261[1] : + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd19)) ? + robdeqPort_0_deq_data_BITS_95_TO_32__q326[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_1 = - (rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18) ? - robdeqPort_0_deq_data_BITS_95_TO_32__q261[3] : + (rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd19) ? + robdeqPort_0_deq_data_BITS_95_TO_32__q326[3] : csrf_prev_ie_vec_3 ; - assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; + assign MUX_csrf_mccsr_reg$write_1__VAL_1 = + { f_csr_reqs$D_OUT[15:10], + CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q327 } ; + assign MUX_csrf_mccsr_reg$write_1__VAL_2 = + { robdeqPort_0_deq_data_BITS_95_TO_32__q326[15:10], + CASE_robdeqPort_0_deq_data_BITS_95_TO_3226_BIT_ETC__q328 } ; + assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = + rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h703197 + 64'd1 ; + n__read__h1008440 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h703197 + { 62'd0, x__h705873 } ; + n__read__h1008440 + { 62'd0, x__h1010892 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = - (rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18) ? - MUX_csrf_mepc_csr$write_1__VAL_2[12:11] : + (rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd19) ? + MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; - assign MUX_csrf_mtval_csr$write_1__VAL_1 = - commitStage_commitTrap[4] ? 64'd0 : trap_val__h693218 ; - assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = - rob$deqPort_0_deq_data[186:182] != 5'd13 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 != - 6'd8 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 != - 6'd18 || - MUX_csrf_mtval_csr$write_1__VAL_2[5] ; - assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = - rob$deqPort_0_deq_data[186:182] != 5'd13 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 != - 6'd18 || - MUX_csrf_mtval_csr$write_1__VAL_2[7] ; - assign MUX_csrf_prv_reg$write_1__VAL_1 = - (rob$deqPort_0_deq_data[186:182] == 5'd19) ? - x__h702600 : - csrf_mpp_reg ; - assign MUX_csrf_prv_reg$write_1__VAL_2 = - csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ? - 2'd1 : - 2'd3 ; - assign MUX_csrf_sepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 = - (mmio_pRqQ_data_0[37:36] == 2'd2) ? - mmio_pRqQ_data_0[0] : - amoExec___d880[0] ; - assign MUX_csrf_spp_reg$write_1__VAL_1 = - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd8 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18) && - MUX_csrf_sepc_csr$write_1__VAL_2[8] ; - assign MUX_fetchStage$redirect_1__VAL_4 = - csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ? - y_avValue__h693065 : - y_avValue__h694826 ; - always@(rob$deqPort_0_deq_data or - next_pc__h702540 or csrf_sepc_csr or csrf_mepc_csr) + assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; + always@(commitStage_commitTrap or trap_val__h994147 or trap_val__h993994) begin - case (rob$deqPort_0_deq_data[186:182]) - 5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr; - 5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h702540; + case (commitStage_commitTrap[44:43]) + 2'd0: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h994147; + 2'd1: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h993994; + default: MUX_csrf_mtval_csr$write_1__VAL_2 = 64'd0; endcase end + assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = + rob$deqPort_0_deq_data[469:465] != 5'd17 || + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 != + 6'd8 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 != + 6'd19 || + MUX_csrf_mtval_csr$write_1__VAL_1[5] ; + assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = + rob$deqPort_0_deq_data[469:465] != 5'd17 || + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 != + 6'd19 || + MUX_csrf_mtval_csr$write_1__VAL_1[7] ; + assign MUX_csrf_prv_reg$write_1__VAL_1 = + (rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd42) ? + MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : + ((rob$deqPort_0_deq_data[469:465] == 5'd24) ? + x__h1007116 : + csrf_mpp_reg) ; + assign MUX_csrf_prv_reg$write_1__VAL_2 = + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 ? + 2'd1 : + 2'd3 ; + assign MUX_csrf_rg_dcsr$write_1__VAL_2 = + { 32'b0, + csrf_rg_dcsr[31:9], + dcsr_cause__h991471, + csrf_rg_dcsr[5:2], + csrf_prv_reg } ; + assign MUX_csrf_rg_tselect$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; + assign MUX_csrf_spp_reg$write_1__VAL_1 = + rob$deqPort_0_deq_data[469:465] == 5'd17 && + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd8 || + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd19) && + MUX_csrf_rg_tselect$write_1__VAL_2[8] ; + assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1014318 } ; + assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1[149:86] } ; + assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = + { csrf_prv_reg, + csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, + csrf_mxr_reg, + csrf_sum_reg, + csrf_ppn_reg } ; + assign MUX_fetchStage$redirect_1__VAL_1 = + { IF_csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_c_ETC___d22649[38:19], + ~IF_csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_c_ETC___d22649[18:0], + IF_IF_csrf_prv_reg_read__0075_ULE_1_2375_AND_I_ETC___d22667[25:17], + ~IF_IF_csrf_prv_reg_read__0075_ULE_1_2375_AND_I_ETC___d22667[16:15], + IF_IF_csrf_prv_reg_read__0075_ULE_1_2375_AND_I_ETC___d22667[14:3], + ~IF_IF_csrf_prv_reg_read__0075_ULE_1_2375_AND_I_ETC___d22667[2], + IF_IF_csrf_prv_reg_read__0075_ULE_1_2375_AND_I_ETC___d22667[1:0], + thin_address__h996489 } ; + always@(rob$deqPort_0_deq_data or + next_pc__h1007056 or v__h1007095 or v__h1007548) + begin + case (rob$deqPort_0_deq_data[469:465]) + 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1007095; + 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1007548; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1007056; + endcase + end + assign MUX_fetchStage$redirect_1__VAL_6 = + { csrf_rg_dpc[152], + csrf_rg_dpc[71:56], + csrf_rg_dpc[54:53], + csrf_rg_dpc[55], + ~csrf_rg_dpc[52:34], + IF_csrf_rg_dpc_read__3776_BIT_34_3785_THEN_csr_ETC___d23793[25:17], + ~IF_csrf_rg_dpc_read__3776_BIT_34_3785_THEN_csr_ETC___d23793[16:15], + IF_csrf_rg_dpc_read__3776_BIT_34_3785_THEN_csr_ETC___d23793[14:3], + ~IF_csrf_rg_dpc_read__3776_BIT_34_3785_THEN_csr_ETC___d23793[2], + IF_csrf_rg_dpc_read__3776_BIT_34_3785_THEN_csr_ETC___d23793[1:0], + csrf_rg_dpc[149:86] } ; assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = { 1'd1, coreFix_memExe_dTlb$toParent_rqToP_first[1:0], @@ -11297,157 +11545,236 @@ module mkCore(CLK, { 3'd2, fetchStage$iTlbIfc_toParent_rqToP_first } ; assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - mmio_dataReqQ_data_0[141:78], - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q262, - mmio_dataReqQ_data_0[71:0] } ; + mmio_dataReqQ_data_0[214:151], + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q329, + mmio_dataReqQ_data_0[144:0] } ; assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, fetchStage$mmioIfc_instReq_first_fst, 5'd2, fetchStage$mmioIfc_instReq_first_snd, - 72'hAAAAAAAAAAAAAAAAAA } ; + 145'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - coreFix_memExe_lsq$firstSt[141:78], - (coreFix_memExe_lsq$firstSt[158:157] == 2'd0) ? + coreFix_memExe_lsq$firstSt[223:160], + (coreFix_memExe_lsq$firstSt[240:239] == 2'd0) ? 6'd42 : - { 2'd3, coreFix_memExe_lsq$firstSt[156:153] }, - coreFix_memExe_lsq$firstSt[76:5] } ; + { 2'd3, coreFix_memExe_lsq$firstSt[238:235] }, + coreFix_memExe_lsq$firstSt[158:14] } ; assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, - coreFix_memExe_lsq$firstLd[80:17], + coreFix_memExe_lsq$firstLd[97:34], 6'd26, - coreFix_memExe_lsq$firstLd[15:0], - 56'hAAAAAAAAAAAAAA } ; + coreFix_memExe_lsq$firstLd[32:0], + 112'hAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h473013 : - data__h472479 ; + { 1'd0, + res_address__h567273, + res_addrBits__h567274, + 72'h00001FFFFF44000000 } ; + assign MUX_rf$write_2_wr_2__VAL_2 = + { 1'd0, + res_address__h568125, + res_addrBits__h568126, + 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_3 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h335092 : - res_data__h335087 ; + { 1'd0, + res_address__h613882, + res_addrBits__h613883, + 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_4 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h380787 : - res_data__h380782 ; + { 1'd0, + res_address__h659629, + res_addrBits__h659630, + 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_5 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h426475 : - res_data__h426470 ; + { 1'd0, + res_address__h705438, + res_addrBits__h705439, + 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_6 = - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h472205 : - IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066 ; + { 1'd0, + res_address__h706298, + res_addrBits__h706299, + 72'h00001FFFFF44000000 } ; + assign MUX_rf$write_3_wr_2__VAL_1 = + { coreFix_memExe_respLrScAmoQ_data_0[128], + res_address__h126791, + res_addrBits__h126792, + coreFix_memExe_respLrScAmoQ_data_0[127:112], + coreFix_memExe_respLrScAmoQ_data_0[109], + coreFix_memExe_respLrScAmoQ_data_0[111:110], + ~coreFix_memExe_respLrScAmoQ_data_0[108:90], + IF_INV_coreFix_memExe_respLrScAmoQ_data_0_233__ETC___d1273 } ; + assign MUX_rf$write_3_wr_2__VAL_2 = + { mmio_dataRespQ_data_0[128], + res_address__h139703, + res_addrBits__h139704, + mmio_dataRespQ_data_0[127:112], + mmio_dataRespQ_data_0[109], + mmio_dataRespQ_data_0[111:110], + ~mmio_dataRespQ_data_0[108:90], + IF_INV_mmio_dataRespQ_data_0_389_BITS_108_TO_9_ETC___d1433 } ; assign MUX_rf$write_3_wr_2__VAL_3 = - coreFix_memExe_lsq$firstLd[100] ? - coreFix_memExe_respLrScAmoQ_data_0 : - IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378 ; + { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && + coreFix_memExe_respLrScAmoQ_data_0[128], + res_address__h178866, + res_addrBits__h178867, + x__h183367[127:112], + x__h183367[109], + x__h183367[111:110], + ~x__h183367[108:90], + IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 } ; assign MUX_rf$write_3_wr_2__VAL_4 = - coreFix_memExe_lsq$firstLd[100] ? - mmio_dataRespQ_data_0[63:0] : - IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425 ; + { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && + mmio_dataRespQ_data_0[128], + res_address__h197631, + res_addrBits__h197632, + x__h199219[127:112], + x__h199219[109], + x__h199219[111:110], + ~x__h199219[108:90], + IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 } ; + assign MUX_rf$write_3_wr_2__VAL_5 = + { coreFix_memExe_lsq$respLd[128], + res_address__h216390, + res_addrBits__h216391, + coreFix_memExe_lsq$respLd[127:112], + coreFix_memExe_lsq$respLd[109], + coreFix_memExe_lsq$respLd[111:110], + ~coreFix_memExe_lsq$respLd[108:90], + IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 } ; + assign MUX_rf$write_4_wr_2__VAL_1 = + { 1'd1, + data_address__h1013045, + data_addrBits__h1013046, + 72'hFFFF1FFFFF44000000 } ; + assign MUX_rf$write_4_wr_2__VAL_2 = + { 1'd0, + data_address__h1013899, + data_addrBits__h1013900, + 72'h00001FFFFF44000000 } ; assign MUX_rob$enqPort_0_enq_1__VAL_1 = - { fetchStage$pipelines_0_first[387:324], - fetchStage$pipelines_0_first[127:96], - fetchStage$pipelines_0_first[199:195], - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805, - 73'h1280000000000000000, - fetchStage$pipelines_0_first[323:260], + { fetchStage$pipelines_0_first[590:462], + fetchStage$pipelines_0_first[128:97], + fetchStage$pipelines_0_first[272:268], + fetchStage$pipelines_0_first[76:70], + 163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, + fetchStage_pipelines_0_first__0045_BIT_167_037_ETC___d20394, + fetchStage_pipelines_0_first__0045_BIT_180_027_ETC___d20370, + 81'h12AA80000000000000000, + fetchStage$pipelines_0_first[495:333], 5'd0, - fetchStage$pipelines_0_first[75] && - fetchStage$pipelines_0_first[74], - fetchStage$pipelines_0_first[194:192] != 3'd0 && - fetchStage$pipelines_0_first[194:192] != 3'd1 && - fetchStage$pipelines_0_first[194:192] != 3'd2 && - fetchStage$pipelines_0_first[194:192] != 3'd3 && - fetchStage$pipelines_0_first[194:192] != 3'd4, - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13903 } ; + fetchStage$pipelines_0_first[76] && + fetchStage$pipelines_0_first[75], + fetchStage$pipelines_0_first[267:265] != 3'd0 && + fetchStage$pipelines_0_first[267:265] != 3'd1 && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 && + fetchStage$pipelines_0_first[267:265] != 3'd2 && + fetchStage$pipelines_0_first[267:265] != 3'd3 && + fetchStage$pipelines_0_first[267:265] != 3'd4, + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1 || + fetchStage$pipelines_0_first[267:265] != 3'd2 || + !coreFix_memExe_rsMem$canEnq || + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051 || + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21801, + IF_NOT_fetchStage_pipelines_0_first__0045_BITS_ETC___d21850, + 7'd32, + specTagManager$currentSpecBits } ; assign MUX_rob$enqPort_0_enq_1__VAL_2 = - { fetchStage$pipelines_0_first[387:324], - fetchStage$pipelines_0_first[127:96], - fetchStage$pipelines_0_first[199:195], - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805, + { fetchStage$pipelines_0_first[590:462], + fetchStage$pipelines_0_first[128:97], + fetchStage$pipelines_0_first[272:268], + fetchStage$pipelines_0_first[76:70], + 163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, + fetchStage_pipelines_0_first__0045_BIT_167_037_ETC___d20394, + fetchStage_pipelines_0_first__0045_BIT_180_027_ETC___d20370, 2'd1, - !fetchStage$pipelines_0_first[68] && - (IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[12] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[13] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[14]), - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d13074, + IF_NOT_renameStage_rg_m_halt_req_0072_BIT_4_00_ETC___d20766, fetchStage$pipelines_0_first[63:0], - 2'd0, - fetchStage$pipelines_0_first[323:260], + 36'h2AAAAAAAA, + fetchStage$pipelines_0_first[590:462], 20'd13601, specTagManager$currentSpecBits } ; assign MUX_rob$enqPort_0_enq_1__VAL_3 = - { fetchStage$pipelines_0_first[387:324], - fetchStage$pipelines_0_first[127:96], - fetchStage$pipelines_0_first[199:195], - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805, - 73'h1280000000000000000, - fetchStage$pipelines_0_first[323:260], - 5'd0, - fetchStage$pipelines_0_first[75] && - fetchStage$pipelines_0_first[74], - fetchStage$pipelines_0_first[194:192] != 3'd0, - 13'h1521, - specTagManager$currentSpecBits } ; + { fetchStage$pipelines_0_first[590:462], + fetchStage$pipelines_0_first[128:97], + fetchStage$pipelines_0_first[272:268], + fetchStage$pipelines_0_first[76:70], + 163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, + fetchStage_pipelines_0_first__0045_BIT_167_037_ETC___d20923 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q263 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264 } ; - assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 = + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337 } ; + assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h335088 ; - assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 = + res_fflags__h568166 ; + assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h380783 ; - assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 = + res_fflags__h613920 ; + assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h426471 ; + res_fflags__h659667 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd2818 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd31 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd32 ; assign csrf_minstret_ehr_data_lat_1$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst || WILL_FIRE_RL_commitStage_doCommitNormalInst ; - assign csrf_minstret_ehr_data_dummy_1_0$whas = - WILL_FIRE_RL_commitStage_doCommitNormalInst || - WILL_FIRE_RL_commitStage_doCommitSystemInst ; - assign csrf_mcycle_ehr_data_lat_0$wget = rob$deqPort_0_deq_data[95:32] ; assign csrf_mcycle_ehr_data_lat_0$whas = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd2816 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd30 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd31 ; + assign csrf_sepcc_reg_data_lat_0$wget = + { commitStage_commitTrap[237], + pc_address__h991846, + pc_addrBits__h991847, + commitStage_commitTrap[236:221], + commitStage_commitTrap[218], + commitStage_commitTrap[220:219], + ~commitStage_commitTrap[217:199], + IF_INV_commitStage_commitTrap_2029_BITS_217_TO_ETC___d22341, + x__h992216, + x__h992236 } ; + assign csrf_sepcc_reg_data_lat_1$whas = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd18 && + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 == + 4'd5 ; + assign csrf_mepcc_reg_data_lat_1$whas = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd18 && + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 == + 4'd9 ; + assign csrInstOrInterruptInflight_lat_0$whas = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + (commitStage_commitTrap[44:43] != 2'd0 && + commitStage_commitTrap[44:43] != 2'd1 || + commitStage_commitTrap[44:43] == 2'd1 && + commitStage_commitTrap[36:32] == 5'd3) ; assign csrInstOrInterruptInflight_lat_1$whas = WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[199:195] == 5'd13 || - MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2 ; + fetchStage$pipelines_0_first[272:268] == 5'd17 || + MUX_csrInstOrInterruptInflight_lat_1$wset_1__SEL_2 ; assign mmio_dataReqQ_enqReq_lat_0$wget = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ? MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 : @@ -11455,7 +11782,8 @@ module mkCore(CLK, assign mmio_dataReqQ_enqReq_lat_0$whas = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ; - assign mmio_dataRespQ_enqReq_lat_0$wget = { 1'd1, mmio_pRsQ_data_0[64:0] } ; + assign mmio_dataRespQ_enqReq_lat_0$wget = + { 1'd1, mmio_pRsQ_data_0[129:0] } ; assign mmio_dataRespQ_deqReq_lat_0$whas = WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault || @@ -11470,14 +11798,19 @@ module mkCore(CLK, MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 ; assign mmio_cRqQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmio_sendDataReq || WILL_FIRE_RL_mmio_sendInstReq ; - assign mmio_pRsQ_enqReq_lat_0$wget = { 1'd1, mmioToPlatform_pRs_enq_x } ; + assign mmio_pRsQ_enqReq_lat_0$wget = + { 1'd1, + mmioToPlatform_pRs_enq_x[130], + mmioToPlatform_pRs_enq_x[130] ? + mmioToPlatform_pRs_enq_x[129:0] : + { 64'hAAAAAAAAAAAAAAAA, mmioToPlatform_pRs_enq_x[65:0] } } ; assign mmio_pRsQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmio_sendInstResp || WILL_FIRE_RL_mmio_sendDataResp ; assign mmio_pRqQ_enqReq_lat_0$wget = { 1'd1, mmioToPlatform_pRq_enq_x[38], - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q265, + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q338, mmioToPlatform_pRq_enq_x[31:0] } ; assign mmio_cRsQ_enqReq_lat_0$wget = { 1'd1, csrf_software_int_pend_vec_3 } ; @@ -11488,41 +11821,53 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && coreFix_aluExe_1_exeToFinQ$first[16] ; assign coreFix_aluExe_0_bypassWire_0$wget = - { coreFix_aluExe_0_regToExeQ$first[348:342], - basicExec___d12469[321:258] } ; + { coreFix_aluExe_0_regToExeQ$first[676:670], + basicExec___d19648[1159:997] } ; assign coreFix_aluExe_0_bypassWire_0$whas = WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && - coreFix_aluExe_0_regToExeQ$first[349] ; + coreFix_aluExe_0_regToExeQ$first[677] ; assign coreFix_aluExe_0_bypassWire_1$wget = - { coreFix_aluExe_1_regToExeQ$first[348:342], - basicExec___d11860[321:258] } ; + { coreFix_aluExe_1_regToExeQ$first[676:670], + basicExec___d17570[1159:997] } ; assign coreFix_aluExe_0_bypassWire_1$whas = WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && - coreFix_aluExe_1_regToExeQ$first[349] ; + coreFix_aluExe_1_regToExeQ$first[677] ; assign coreFix_aluExe_0_bypassWire_2$wget = - { coreFix_aluExe_0_exeToFinQ$first[319:313], - coreFix_aluExe_0_exeToFinQ$first[275:212] } ; + { coreFix_aluExe_0_exeToFinQ$first[1060:1054], + coreFix_aluExe_0_exeToFinQ$first[1015:853] } ; assign coreFix_aluExe_0_bypassWire_2$whas = _dor1coreFix_aluExe_0_bypassWire_2$EN_wset && - coreFix_aluExe_0_exeToFinQ$first[320] ; + coreFix_aluExe_0_exeToFinQ$first[1061] ; assign coreFix_aluExe_0_bypassWire_3$wget = - { coreFix_aluExe_1_exeToFinQ$first[319:313], - coreFix_aluExe_1_exeToFinQ$first[275:212] } ; + { coreFix_aluExe_1_exeToFinQ$first[1060:1054], + coreFix_aluExe_1_exeToFinQ$first[1015:853] } ; assign coreFix_aluExe_0_bypassWire_3$whas = _dor1coreFix_aluExe_0_bypassWire_3$EN_wset && - coreFix_aluExe_1_exeToFinQ$first[320] ; + coreFix_aluExe_1_exeToFinQ$first[1061] ; assign coreFix_aluExe_1_bypassWire_2$whas = _dor1coreFix_aluExe_1_bypassWire_2$EN_wset && - coreFix_aluExe_0_exeToFinQ$first[320] ; + coreFix_aluExe_0_exeToFinQ$first[1061] ; assign coreFix_aluExe_1_bypassWire_3$whas = _dor1coreFix_aluExe_1_bypassWire_3$EN_wset && - coreFix_aluExe_1_exeToFinQ$first[320] ; + coreFix_aluExe_1_exeToFinQ$first[1061] ; + assign coreFix_fpuMulDivExe_0_bypassWire_0$wget = + { coreFix_aluExe_0_regToExeQ$first[676:670], + basicExec___d19648[1156:1093] } ; + assign coreFix_fpuMulDivExe_0_bypassWire_1$wget = + { coreFix_aluExe_1_regToExeQ$first[676:670], + basicExec___d17570[1156:1093] } ; + assign coreFix_fpuMulDivExe_0_bypassWire_2$wget = + { coreFix_aluExe_0_exeToFinQ$first[1060:1054], + coreFix_aluExe_0_exeToFinQ$first[1012:949] } ; assign coreFix_fpuMulDivExe_0_bypassWire_2$whas = _dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset && - coreFix_aluExe_0_exeToFinQ$first[320] ; + coreFix_aluExe_0_exeToFinQ$first[1061] ; + assign coreFix_fpuMulDivExe_0_bypassWire_3$wget = + { coreFix_aluExe_1_exeToFinQ$first[1060:1054], + coreFix_aluExe_1_exeToFinQ$first[1012:949] } ; assign coreFix_fpuMulDivExe_0_bypassWire_3$whas = _dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset && - coreFix_aluExe_1_exeToFinQ$first[320] ; + coreFix_aluExe_1_exeToFinQ$first[1061] ; always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225]) @@ -11534,40 +11879,40 @@ module mkCore(CLK, end assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd3 && (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 || coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ; assign coreFix_memExe_bypassWire_2$whas = _dor1coreFix_memExe_bypassWire_2$EN_wset && - coreFix_aluExe_0_exeToFinQ$first[320] ; + coreFix_aluExe_0_exeToFinQ$first[1061] ; assign coreFix_memExe_bypassWire_3$whas = _dor1coreFix_memExe_bypassWire_3$EN_wset && - coreFix_aluExe_1_exeToFinQ$first[320] ; + coreFix_aluExe_1_exeToFinQ$first[1061] ; assign coreFix_memExe_issueLd$wget = - { coreFix_memExe_dTlb$procResp[89:85], - coreFix_memExe_dTlb$procResp[174:111], - coreFix_memExe_dTlb$procResp[84:77] } ; + { coreFix_memExe_dTlb$procResp[474:470], + coreFix_memExe_dTlb$procResp[560:497], + coreFix_memExe_dTlb$procResp[469:454] } ; assign coreFix_memExe_issueLd$whas = WILL_FIRE_RL_coreFix_memExe_doFinishMem && - coreFix_memExe_dTlb$procResp[105:103] == 3'd0 && - NOT_coreFix_memExe_dTlb_procResp__712_BITS_174_ETC___d1751 && - IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740 && + coreFix_memExe_dTlb$procResp[490:488] == 3'd0 && + NOT_coreFix_memExe_dTlb_procResp__239_BITS_560_ETC___d4563 && + IF_coreFix_memExe_dTlb_procResp__239_BIT_277_5_ETC___d4553 && !coreFix_memExe_lsq$updateAddr ; assign coreFix_memExe_reqLdQ_data_0_lat_0$wget = MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 ? - coreFix_memExe_issueLd$wget[76:8] : - coreFix_memExe_lsq$getIssueLd[76:8] ; + coreFix_memExe_issueLd$wget[84:16] : + coreFix_memExe_lsq$getIssueLd[84:16] ; assign coreFix_memExe_reqLdQ_data_0_lat_0$whas = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && - coreFix_memExe_lsq$issueLd[74:73] == 2'd0 || + coreFix_memExe_lsq$issueLd[139:138] == 2'd0 || WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && - coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ; + coreFix_memExe_lsq$issueLd[139:138] == 2'd0 ; assign coreFix_memExe_reqLdQ_empty_lat_0$whas = _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset && - coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ; + coreFix_memExe_lsq$issueLd[139:138] == 2'd0 ; assign coreFix_memExe_reqLdQ_full_lat_0$whas = _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset && - coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ; + coreFix_memExe_lsq$issueLd[139:138] == 2'd0 ; assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ? MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 : @@ -11576,74 +11921,87 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ; assign coreFix_memExe_reqStQ_data_0_lat_0$wget = - { coreFix_memExe_stb$issue[635:576], 6'd0 } ; + { coreFix_memExe_stb$issue[639:580], 6'd0 } ; assign coreFix_memExe_forwardQ_enqReq_lat_0$wget = MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ? MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 : MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 ; assign coreFix_memExe_forwardQ_enqReq_lat_0$whas = - MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 || - MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 ; + WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 || + WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 ; assign coreFix_memExe_memRespLdQ_enqReq_lat_0$wget = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 : MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 ; assign coreFix_memExe_memRespLdQ_enqReq_lat_0$whas = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 || - MUX_coreFix_memExe_lsq$getHit_1__SEL_2 ; - always@(MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 or + WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 ; + always@(MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__SEL_1 or MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 or - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or - MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 or + MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_2 or + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5540 or WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3) begin case (1'b1) // synopsys parallel_case - MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1: + MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__SEL_1: coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget = MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1; - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2: + MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_2: coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget = - MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2; + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5540; WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo: coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget = MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3; default: coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget = - 65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ; + 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas = - MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 || - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 || + WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5535 || + WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2 || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3) || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ; assign coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ; - always@(WILL_FIRE_RL_coreFix_memExe_sendLdToMem or + always@(WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem or MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 or - WILL_FIRE_RL_coreFix_memExe_sendStToMem or + WILL_FIRE_RL_coreFix_memExe_sendLdToMem or MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 or - WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem or + WILL_FIRE_RL_coreFix_memExe_sendStToMem or MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_coreFix_memExe_sendLdToMem: + WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem: coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget = MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1; - WILL_FIRE_RL_coreFix_memExe_sendStToMem: + WILL_FIRE_RL_coreFix_memExe_sendLdToMem: coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget = MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2; - WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem: + WILL_FIRE_RL_coreFix_memExe_sendStToMem: coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget = MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3; default: coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget = - 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + 227'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas = + WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem || WILL_FIRE_RL_coreFix_memExe_sendLdToMem || - WILL_FIRE_RL_coreFix_memExe_sendStToMem || - WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ; + WILL_FIRE_RL_coreFix_memExe_sendStToMem ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ? MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 : @@ -11653,11 +12011,11 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget = { 1'd1, - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[147:84], - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[54:53], - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[83:82], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[221:158], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[55:54], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[157:156], 1'd1, - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[57:55] } ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[58:56] } ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget = { 1'd1, dCacheToParent_fromP_enq_x } ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas = @@ -11668,21 +12026,30 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2645 ; - always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 or + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942 && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5614 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5618) ; + always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_1 or MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 or - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or + MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_2 or MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 or - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3) + MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_3) begin case (1'b1) // synopsys parallel_case - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1: + MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_1: coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget = MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1; - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2: + MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_2: coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget = MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2; - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3: + MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__SEL_3: coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget = 59'h2AAAAAAAAAAAAAA; default: coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget = @@ -11690,9 +12057,16 @@ module mkCore(CLK, endcase end assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas = - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 || - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 || - MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 ; + WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5554 || + WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2 || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3) || + WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq && + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d6972 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ; @@ -11707,18 +12081,46 @@ module mkCore(CLK, // register commitStage_commitTrap assign commitStage_commitTrap$D_IN = WILL_FIRE_RL_commitStage_doCommitTrap_handle ? - 134'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : + 239'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : MUX_commitStage_commitTrap$write_1__VAL_2 ; assign commitStage_commitTrap$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; - // register commitStage_rg_instret - assign commitStage_rg_instret$D_IN = - WILL_FIRE_RL_commitStage_doCommitSystemInst ? - MUX_commitStage_rg_instret$write_1__VAL_1 : - MUX_commitStage_rg_instret$write_1__VAL_2 ; - assign commitStage_rg_instret$EN = csrf_minstret_ehr_data_lat_1$whas ; + // register commitStage_rg_run_state + assign commitStage_rg_run_state$D_IN = + MUX_commitStage_rg_run_state$write_1__SEL_1 ; + assign commitStage_rg_run_state$EN = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + NOT_commitStage_commitTrap_2029_BITS_44_TO_43__ETC___d22295 || + WILL_FIRE_RL_rl_debug_resume ; + + // register commitStage_rg_serial_num + always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or + MUX_commitStage_rg_serial_num$write_1__VAL_1 or + WILL_FIRE_RL_commitStage_doCommitSystemInst or + WILL_FIRE_RL_commitStage_doCommitNormalInst or + MUX_commitStage_rg_serial_num$write_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_commitStage_rg_serial_num$write_1__SEL_1: + commitStage_rg_serial_num$D_IN = + MUX_commitStage_rg_serial_num$write_1__VAL_1; + WILL_FIRE_RL_commitStage_doCommitSystemInst: + commitStage_rg_serial_num$D_IN = + MUX_commitStage_rg_serial_num$write_1__VAL_1; + WILL_FIRE_RL_commitStage_doCommitNormalInst: + commitStage_rg_serial_num$D_IN = + MUX_commitStage_rg_serial_num$write_1__VAL_3; + default: commitStage_rg_serial_num$D_IN = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign commitStage_rg_serial_num$EN = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 || + WILL_FIRE_RL_commitStage_doCommitSystemInst || + WILL_FIRE_RL_commitStage_doCommitNormalInst ; // register coreFix_doStatsReg assign coreFix_doStatsReg$D_IN = 1'b0 ; @@ -11739,8 +12141,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h601417 : - v__h600772 ; + v__h837213 : + v__h836568 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -11768,9 +12170,8 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd0 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 && - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ; + !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN = @@ -11778,9 +12179,8 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd1 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 && - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ; + !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN = @@ -11788,9 +12188,8 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd2 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 && - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ; + !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN = @@ -11798,9 +12197,8 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd3 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 && - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ; + !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN = @@ -11808,9 +12206,8 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd4 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 && - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ; + !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN = @@ -11818,9 +12215,8 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd5 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 && - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ; + !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN = @@ -11828,9 +12224,8 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd6 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 && - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ; + !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN = @@ -11838,16 +12233,14 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 && - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ; + !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN = - (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - _theResult_____2__h293741 ; + _theResult_____2__h515296 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -11858,18 +12251,15 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl || - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3074 ; + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7248 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN = - (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - v__h293161 ; + v__h514752 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -11880,9 +12270,8 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN = - NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 && - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063 ; + !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl && + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7239 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl @@ -11891,31 +12280,28 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN = - { !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT || - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 || + { IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7338 || (EN_dCacheToParent_fromP_enq ? - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] : - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582]), - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3243 } ; + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[586] : + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[586]), + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7404 } ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd0 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 ; + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7303 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd1 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 ; + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7303 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = - NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - _theResult_____2__h301737 ; + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && + _theResult_____2__h526073 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -11924,34 +12310,34 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl || - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3179 ; + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7322 && + IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7338 && + (IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7316 || + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty) ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = - NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - v__h296506 ; + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && + v__h516772 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN = - 584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; + 588'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN = - NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 && - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3166 ; + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7331 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN = - { IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000, - IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008 } ; + { IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7185, + IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7193 } ; assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_processAmo @@ -11970,16 +12356,16 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2; WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo: coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN = - 161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 235'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; default: coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN = - 161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + 235'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN = MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd4 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ; @@ -12015,9 +12401,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd0 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305 ; + !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7462 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN = @@ -12026,14 +12411,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd1 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305 ; + !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7462 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = - NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - _theResult_____2__h307731 ; + !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && + _theResult_____2__h533166 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12042,16 +12426,14 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl || - IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3351 ; + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7501 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = - NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - v__h307020 ; + !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && + v__h532491 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12061,9 +12443,8 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN = - NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 && - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3337 ; + !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7490 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl @@ -12072,37 +12453,34 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h311294, + { x_addr__h535302, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], - !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT || - IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443 || + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[518:517] : + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[518:517], + IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7581 || (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[512] : - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[512]), + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[516] : + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[516]), coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[511:0] : - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[511:0] } ; + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[515:0] : + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[515:0] } ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd0 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 ; + !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7546 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd1 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 ; + !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && + IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7546 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = - NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - _theResult_____2__h315585 ; + !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && + _theResult_____2__h543801 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12111,28 +12489,28 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl || - IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3447 ; + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7566 && + IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7581 && + (IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7559 || + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty) ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = - NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - v__h310896 ; + !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && + v__h534940 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN = - 580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; + 584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN = - NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 && - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3433 ; + !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7574 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN = 1'd1 ; // register coreFix_memExe_dMem_perfReqQ_clearReq_rl @@ -12143,8 +12521,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_perfReqQ_data_0$D_IN = coreFix_memExe_dMem_perfReqQ_enqReq_rl[3:0] ; assign coreFix_memExe_dMem_perfReqQ_data_0$EN = - NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1879 && - coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT && + !coreFix_memExe_dMem_perfReqQ_clearReq_rl && coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ; // register coreFix_memExe_dMem_perfReqQ_deqReq_rl @@ -12153,9 +12530,10 @@ module mkCore(CLK, // register coreFix_memExe_dMem_perfReqQ_empty assign coreFix_memExe_dMem_perfReqQ_empty$D_IN = - coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_perfReqQ_clearReq_rl || - NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1923 ; + !coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] && + (coreFix_memExe_dMem_perfReqQ_deqReq_rl || + coreFix_memExe_dMem_perfReqQ_empty) ; assign coreFix_memExe_dMem_perfReqQ_empty$EN = 1'd1 ; // register coreFix_memExe_dMem_perfReqQ_enqReq_rl @@ -12164,8 +12542,10 @@ module mkCore(CLK, // register coreFix_memExe_dMem_perfReqQ_full assign coreFix_memExe_dMem_perfReqQ_full$D_IN = - NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1879 && - coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1907 ; + !coreFix_memExe_dMem_perfReqQ_clearReq_rl && + (coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] || + !coreFix_memExe_dMem_perfReqQ_deqReq_rl && + coreFix_memExe_dMem_perfReqQ_full) ; assign coreFix_memExe_dMem_perfReqQ_full$EN = 1'd1 ; // register coreFix_memExe_forwardQ_clearReq_rl @@ -12175,29 +12555,27 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_data_0 assign coreFix_memExe_forwardQ_data_0$D_IN = coreFix_memExe_forwardQ_enqReq_lat_0$whas ? - coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] : - coreFix_memExe_forwardQ_enqReq_rl[68:0] ; + coreFix_memExe_forwardQ_enqReq_lat_0$wget[133:0] : + coreFix_memExe_forwardQ_enqReq_rl[133:0] ; assign coreFix_memExe_forwardQ_data_0$EN = coreFix_memExe_forwardQ_enqP == 1'd0 && - NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724 ; + !coreFix_memExe_forwardQ_clearReq_rl && + IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7833 ; // register coreFix_memExe_forwardQ_data_1 assign coreFix_memExe_forwardQ_data_1$D_IN = coreFix_memExe_forwardQ_enqReq_lat_0$whas ? - coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] : - coreFix_memExe_forwardQ_enqReq_rl[68:0] ; + coreFix_memExe_forwardQ_enqReq_lat_0$wget[133:0] : + coreFix_memExe_forwardQ_enqReq_rl[133:0] ; assign coreFix_memExe_forwardQ_data_1$EN = coreFix_memExe_forwardQ_enqP == 1'd1 && - NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724 ; + !coreFix_memExe_forwardQ_clearReq_rl && + IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7833 ; // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = - NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - _theResult_____2__h329154 ; + !coreFix_memExe_forwardQ_clearReq_rl && + _theResult_____2__h561413 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12206,27 +12584,24 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_empty assign coreFix_memExe_forwardQ_empty$D_IN = - coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_forwardQ_clearReq_rl || - IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 && - NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3768 ; + IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7870 ; assign coreFix_memExe_forwardQ_empty$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = - NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - v__h328722 ; + !coreFix_memExe_forwardQ_clearReq_rl && v__h559739 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl - assign coreFix_memExe_forwardQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ; + assign coreFix_memExe_forwardQ_enqReq_rl$D_IN = + 135'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign coreFix_memExe_forwardQ_enqReq_rl$EN = 1'd1 ; // register coreFix_memExe_forwardQ_full assign coreFix_memExe_forwardQ_full$D_IN = - NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 && - coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3755 ; + !coreFix_memExe_forwardQ_clearReq_rl && + IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7860 ; assign coreFix_memExe_forwardQ_full$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_clearReq_rl @@ -12236,29 +12611,27 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_data_0 assign coreFix_memExe_memRespLdQ_data_0$D_IN = coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ? - coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] : - coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ; + coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[133:0] : + coreFix_memExe_memRespLdQ_enqReq_rl[133:0] ; assign coreFix_memExe_memRespLdQ_data_0$EN = coreFix_memExe_memRespLdQ_enqP == 1'd0 && - NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && + IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7751 ; // register coreFix_memExe_memRespLdQ_data_1 assign coreFix_memExe_memRespLdQ_data_1$D_IN = coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ? - coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] : - coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ; + coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[133:0] : + coreFix_memExe_memRespLdQ_enqReq_rl[133:0] ; assign coreFix_memExe_memRespLdQ_data_1$EN = coreFix_memExe_memRespLdQ_enqP == 1'd1 && - NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && + IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7751 ; // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = - NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - _theResult_____2__h325929 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && + _theResult_____2__h557634 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12267,27 +12640,24 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_empty assign coreFix_memExe_memRespLdQ_empty$D_IN = - coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_memRespLdQ_clearReq_rl || - IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 && - NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3674 ; + IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7788 ; assign coreFix_memExe_memRespLdQ_empty$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = - NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - v__h325497 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && v__h555960 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl - assign coreFix_memExe_memRespLdQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ; + assign coreFix_memExe_memRespLdQ_enqReq_rl$D_IN = + 135'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign coreFix_memExe_memRespLdQ_enqReq_rl$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_full assign coreFix_memExe_memRespLdQ_full$D_IN = - NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 && - coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3661 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && + IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7778 ; assign coreFix_memExe_memRespLdQ_full$EN = 1'd1 ; // register coreFix_memExe_reqLdQ_data_0_rl @@ -12313,9 +12683,7 @@ module mkCore(CLK, // register coreFix_memExe_reqLrScAmoQ_data_0_rl assign coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN = - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget : - coreFix_memExe_reqLrScAmoQ_data_0_rl ; + MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 ; assign coreFix_memExe_reqLrScAmoQ_data_0_rl$EN = 1'd1 ; // register coreFix_memExe_reqLrScAmoQ_empty_rl @@ -12360,12 +12728,11 @@ module mkCore(CLK, // register coreFix_memExe_respLrScAmoQ_data_0 assign coreFix_memExe_respLrScAmoQ_data_0$D_IN = coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ? - coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[63:0] : - coreFix_memExe_respLrScAmoQ_enqReq_rl[63:0] ; + coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[128:0] : + coreFix_memExe_respLrScAmoQ_enqReq_rl[128:0] ; assign coreFix_memExe_respLrScAmoQ_data_0$EN = - NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3543 && - coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3554 ; + !coreFix_memExe_respLrScAmoQ_clearReq_rl && + IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d7687 ; // register coreFix_memExe_respLrScAmoQ_deqReq_rl assign coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN = 1'd0 ; @@ -12373,19 +12740,27 @@ module mkCore(CLK, // register coreFix_memExe_respLrScAmoQ_empty assign coreFix_memExe_respLrScAmoQ_empty$D_IN = - coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_respLrScAmoQ_clearReq_rl || - NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3585 ; + (coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ? + !coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[129] : + !coreFix_memExe_respLrScAmoQ_enqReq_rl[129]) && + (coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas || + coreFix_memExe_respLrScAmoQ_deqReq_rl || + coreFix_memExe_respLrScAmoQ_empty) ; assign coreFix_memExe_respLrScAmoQ_empty$EN = 1'd1 ; // register coreFix_memExe_respLrScAmoQ_enqReq_rl - assign coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ; + assign coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN = + 130'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign coreFix_memExe_respLrScAmoQ_enqReq_rl$EN = 1'd1 ; // register coreFix_memExe_respLrScAmoQ_full assign coreFix_memExe_respLrScAmoQ_full$D_IN = - NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3543 && - coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3570 ; + !coreFix_memExe_respLrScAmoQ_clearReq_rl && + (IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d7687 || + !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && + !coreFix_memExe_respLrScAmoQ_deqReq_rl && + coreFix_memExe_respLrScAmoQ_full) ; assign coreFix_memExe_respLrScAmoQ_full$EN = 1'd1 ; // register coreFix_memExe_waitLrScAmoMMIOResp @@ -12426,609 +12801,1038 @@ module mkCore(CLK, assign csrInstOrInterruptInflight_rl$D_IN = csrInstOrInterruptInflight_lat_1$whas ? 1'd1 : - (MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 ? + (csrInstOrInterruptInflight_lat_0$whas ? 1'd0 : csrInstOrInterruptInflight_rl) ; assign csrInstOrInterruptInflight_rl$EN = 1'd1 ; - // register csrf_debug_int_pend - assign csrf_debug_int_pend$D_IN = - MUX_csrf_debug_int_pend$write_1__SEL_1 ? - csrf_mcycle_ehr_data_lat_0$wget[14] : - setDEIP_v ; - assign csrf_debug_int_pend$EN = + // register csrf_ddc_reg + assign csrf_ddc_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; + assign csrf_ddc_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd29 || - EN_setDEIP ; + rob$deqPort_0_deq_data[469:465] == 5'd18 && + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 == + 4'd1 ; // register csrf_external_int_en_vec_0 - assign csrf_external_int_en_vec_0$D_IN = - csrf_mcycle_ehr_data_lat_0$wget[8] ; - assign csrf_external_int_en_vec_0$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd9 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd22) ; + assign csrf_external_int_en_vec_0$D_IN = 1'b0 ; + assign csrf_external_int_en_vec_0$EN = 1'b0 ; // register csrf_external_int_en_vec_1 assign csrf_external_int_en_vec_1$D_IN = - csrf_mcycle_ehr_data_lat_0$wget[9] ; + MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ? + MUX_csrf_stval_csr$write_1__VAL_1[9] : + f_csr_reqs$D_OUT[9] ; assign csrf_external_int_en_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd9 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd22) ; + MUX_csrf_external_int_en_vec_1$write_1__SEL_1 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd260 || + f_csr_reqs$D_OUT[75:64] == 12'd772) ; // register csrf_external_int_en_vec_3 assign csrf_external_int_en_vec_3$D_IN = - csrf_mcycle_ehr_data_lat_0$wget[11] ; + MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ? + f_csr_reqs$D_OUT[11] : + MUX_csrf_stval_csr$write_1__VAL_1[11] ; assign csrf_external_int_en_vec_3$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd22 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd23 ; // register csrf_external_int_pend_vec_0 - assign csrf_external_int_pend_vec_0$D_IN = - csrf_mcycle_ehr_data_lat_0$wget[8] ; - assign csrf_external_int_pend_vec_0$EN = - MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ; + assign csrf_external_int_pend_vec_0$D_IN = 1'b0 ; + assign csrf_external_int_pend_vec_0$EN = 1'b0 ; // register csrf_external_int_pend_vec_1 - assign csrf_external_int_pend_vec_1$D_IN = - MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ? - csrf_mcycle_ehr_data_lat_0$wget[9] : - setSEIP_v ; + always@(MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 or + MUX_csrf_stval_csr$write_1__VAL_1 or + MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 or + f_csr_reqs$D_OUT or EN_setSEIP or setSEIP_v) + case (1'b1) + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1: + csrf_external_int_pend_vec_1$D_IN = + MUX_csrf_stval_csr$write_1__VAL_1[9]; + MUX_csrf_external_int_pend_vec_1$write_1__SEL_2: + csrf_external_int_pend_vec_1$D_IN = f_csr_reqs$D_OUT[9]; + EN_setSEIP: csrf_external_int_pend_vec_1$D_IN = setSEIP_v; + default: csrf_external_int_pend_vec_1$D_IN = + 1'b0 /* unspecified value */ ; + endcase assign csrf_external_int_pend_vec_1$EN = - MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 || EN_setSEIP ; + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd324 || + f_csr_reqs$D_OUT[75:64] == 12'd836) || + EN_setSEIP ; // register csrf_external_int_pend_vec_3 - assign csrf_external_int_pend_vec_3$D_IN = - MUX_csrf_debug_int_pend$write_1__SEL_1 ? - csrf_mcycle_ehr_data_lat_0$wget[11] : - setMEIP_v ; - assign csrf_external_int_pend_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd29 || - EN_setMEIP ; + assign csrf_external_int_pend_vec_3$D_IN = setMEIP_v ; + assign csrf_external_int_pend_vec_3$EN = EN_setMEIP ; // register csrf_fflags_reg - assign csrf_fflags_reg$D_IN = - MUX_csrf_fflags_reg$write_1__SEL_1 ? - csrf_mcycle_ehr_data_lat_0$wget[4:0] : - MUX_csrf_fflags_reg$write_1__VAL_2 ; + always@(MUX_csrf_fflags_reg$write_1__SEL_1 or + MUX_csrf_fflags_reg$write_1__VAL_1 or + MUX_csrf_fflags_reg$write_1__SEL_2 or + MUX_csrf_stval_csr$write_1__VAL_1 or + MUX_csrf_fflags_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_fflags_reg$write_1__SEL_1: + csrf_fflags_reg$D_IN = MUX_csrf_fflags_reg$write_1__VAL_1; + MUX_csrf_fflags_reg$write_1__SEL_2: + csrf_fflags_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; + MUX_csrf_fflags_reg$write_1__SEL_3: + csrf_fflags_reg$D_IN = f_csr_reqs$D_OUT[4:0]; + default: csrf_fflags_reg$D_IN = 5'b01010 /* unspecified value */ ; + endcase assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd0 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4555_4556_OR__ETC___d14768 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__3151_3152_OR__ETC___d23397 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd1 || + f_csr_reqs$D_OUT[75:64] == 12'd3) ; // register csrf_frm_reg assign csrf_frm_reg$D_IN = - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd1) ? - csrf_mcycle_ehr_data_lat_0$wget[2:0] : - csrf_mcycle_ehr_data_lat_0$wget[7:5] ; + MUX_csrf_frm_reg$write_1__SEL_1 ? + MUX_csrf_frm_reg$write_1__VAL_1 : + MUX_csrf_frm_reg$write_1__VAL_2 ; assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd1 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd2) ; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd2) || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd2 || + f_csr_reqs$D_OUT[75:64] == 12'd3) ; // register csrf_fs_reg - assign csrf_fs_reg$D_IN = - MUX_csrf_fs_reg$write_1__SEL_1 ? - MUX_csrf_fs_reg$write_1__VAL_1 : - 2'b11 ; + always@(MUX_csrf_fflags_reg$write_1__SEL_1 or + MUX_csrf_fs_reg$write_1__SEL_2 or + MUX_csrf_fs_reg$write_1__VAL_2 or + MUX_csrf_fs_reg$write_1__SEL_3 or MUX_csrf_fs_reg$write_1__VAL_3) + case (1'b1) + MUX_csrf_fflags_reg$write_1__SEL_1: csrf_fs_reg$D_IN = 2'b11; + MUX_csrf_fs_reg$write_1__SEL_2: + csrf_fs_reg$D_IN = MUX_csrf_fs_reg$write_1__VAL_2; + MUX_csrf_fs_reg$write_1__SEL_3: + csrf_fs_reg$D_IN = MUX_csrf_fs_reg$write_1__VAL_3; + default: csrf_fs_reg$D_IN = 2'b10 /* unspecified value */ ; + endcase assign csrf_fs_reg$EN = - MUX_csrf_fs_reg$write_1__SEL_1 || + MUX_csrf_fs_reg$write_1__SEL_2 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4555_4556_OR__ETC___d14768 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__3151_3152_OR__ETC___d23397 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd1 || + f_csr_reqs$D_OUT[75:64] == 12'd2 || + f_csr_reqs$D_OUT[75:64] == 12'd3 || + f_csr_reqs$D_OUT[75:64] == 12'd256 || + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_ie_vec_0 - assign csrf_ie_vec_0$D_IN = csrf_mcycle_ehr_data_lat_0$wget[0] ; + assign csrf_ie_vec_0$D_IN = + MUX_csrf_ie_vec_0$write_1__SEL_1 ? + MUX_csrf_stval_csr$write_1__VAL_1[0] : + f_csr_reqs$D_OUT[0] ; assign csrf_ie_vec_0$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd8 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18) ; + MUX_csrf_ie_vec_0$write_1__SEL_1 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd256 || + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_ie_vec_1 - assign csrf_ie_vec_1$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_1 && - MUX_csrf_ie_vec_1$write_1__VAL_1 ; + always@(MUX_csrf_ie_vec_1$write_1__SEL_1 or + MUX_csrf_ie_vec_1$write_1__VAL_1 or + MUX_csrf_ie_vec_1$write_1__SEL_2 or + MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_ie_vec_1$write_1__SEL_1: + csrf_ie_vec_1$D_IN = MUX_csrf_ie_vec_1$write_1__VAL_1; + MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_ie_vec_1$D_IN = 1'd0; + MUX_csrf_ie_vec_0$write_1__SEL_2: + csrf_ie_vec_1$D_IN = f_csr_reqs$D_OUT[1]; + default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; + endcase assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd256 || + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_ie_vec_3 - assign csrf_ie_vec_3$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_1 && - MUX_csrf_ie_vec_3$write_1__VAL_1 ; + always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or + MUX_csrf_ie_vec_3$write_1__VAL_1 or + MUX_csrf_ie_vec_3$write_1__SEL_2 or + MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_ie_vec_3$write_1__SEL_1: + csrf_ie_vec_3$D_IN = MUX_csrf_ie_vec_3$write_1__VAL_1; + MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_ie_vec_3$D_IN = 1'd0; + MUX_csrf_ie_vec_3$write_1__SEL_3: + csrf_ie_vec_3$D_IN = f_csr_reqs$D_OUT[3]; + default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; + endcase assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2633_ULE_1_4189_4253_OR_ETC___d14257 ; + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + NOT_csrf_prv_reg_read__0075_ULE_1_2375_2490_OR_ETC___d22495 ; + + // register csrf_mScratchC_reg + assign csrf_mScratchC_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; + assign csrf_mScratchC_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd18 && + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 == + 4'd8 ; // register csrf_mcause_code_reg - assign csrf_mcause_code_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? - cause_code__h692187 : - csrf_mcycle_ehr_data_lat_0$wget[3:0] ; + always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or + MUX_csrf_stval_csr$write_1__VAL_1 or + MUX_csrf_ie_vec_3$write_1__SEL_2 or + cause_code__h992427 or + MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_mcause_code_reg$write_1__SEL_1: + csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; + MUX_csrf_ie_vec_3$write_1__SEL_2: + csrf_mcause_code_reg$D_IN = cause_code__h992427; + MUX_csrf_mcause_code_reg$write_1__SEL_3: + csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; + default: csrf_mcause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; + endcase assign csrf_mcause_code_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2633_ULE_1_4189_4253_OR_ETC___d14257 || + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + NOT_csrf_prv_reg_read__0075_ULE_1_2375_2490_OR_ETC___d22495 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd27 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd28 ; // register csrf_mcause_interrupt_reg - assign csrf_mcause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? - commitStage_commitTrap[4] : - csrf_mcycle_ehr_data_lat_0$wget[63] ; + always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or + MUX_csrf_stval_csr$write_1__VAL_1 or + MUX_csrf_ie_vec_3$write_1__SEL_2 or + cause_interrupt__h992425 or + MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_mcause_code_reg$write_1__SEL_1: + csrf_mcause_interrupt_reg$D_IN = + MUX_csrf_stval_csr$write_1__VAL_1[63]; + MUX_csrf_ie_vec_3$write_1__SEL_2: + csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h992425; + MUX_csrf_mcause_code_reg$write_1__SEL_3: + csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; + default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; + endcase assign csrf_mcause_interrupt_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2633_ULE_1_4189_4253_OR_ETC___d14257 || + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + NOT_csrf_prv_reg_read__0075_ULE_1_2375_2490_OR_ETC___d22495 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd27 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd28 ; + + // register csrf_mccsr_reg + assign csrf_mccsr_reg$D_IN = + MUX_csrf_mccsr_reg$write_1__SEL_1 ? + MUX_csrf_mccsr_reg$write_1__VAL_1 : + MUX_csrf_mccsr_reg$write_1__VAL_2 ; + assign csrf_mccsr_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd3008 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd37 ; // register csrf_mcounteren_cy_reg - assign csrf_mcounteren_cy_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[0] ; + assign csrf_mcounteren_cy_reg$D_IN = + MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[0] : + MUX_csrf_stval_csr$write_1__VAL_1[0] ; assign csrf_mcounteren_cy_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd24 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd25 ; // register csrf_mcounteren_ir_reg - assign csrf_mcounteren_ir_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[2] ; + assign csrf_mcounteren_ir_reg$D_IN = + MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[2] : + MUX_csrf_stval_csr$write_1__VAL_1[2] ; assign csrf_mcounteren_ir_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd24 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd25 ; // register csrf_mcounteren_tm_reg - assign csrf_mcounteren_tm_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[1] ; + assign csrf_mcounteren_tm_reg$D_IN = + MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[1] : + MUX_csrf_stval_csr$write_1__VAL_1[1] ; assign csrf_mcounteren_tm_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd24 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd25 ; // register csrf_mcycle_ehr_data_rl - assign csrf_mcycle_ehr_data_rl$D_IN = upd__h4956 ; + assign csrf_mcycle_ehr_data_rl$D_IN = upd__h3645 ; assign csrf_mcycle_ehr_data_rl$EN = 1'd1 ; // register csrf_medeleg_13_11_reg assign csrf_medeleg_13_11_reg$D_IN = - csrf_mcycle_ehr_data_lat_0$wget[13:11] ; + MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[13:11] : + MUX_csrf_stval_csr$write_1__VAL_1[13:11] ; assign csrf_medeleg_13_11_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd20 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd21 ; // register csrf_medeleg_15_reg - assign csrf_medeleg_15_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[15] ; + assign csrf_medeleg_15_reg$D_IN = + MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[15] : + MUX_csrf_stval_csr$write_1__VAL_1[15] ; assign csrf_medeleg_15_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd20 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd21 ; // register csrf_medeleg_9_0_reg - assign csrf_medeleg_9_0_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[9:0] ; + assign csrf_medeleg_9_0_reg$D_IN = + MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[9:0] : + MUX_csrf_stval_csr$write_1__VAL_1[9:0] ; assign csrf_medeleg_9_0_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd20 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd21 ; - // register csrf_mepc_csr - assign csrf_mepc_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? - commitStage_commitTrap[132:69] : - rob$deqPort_0_deq_data[95:32] ; - assign csrf_mepc_csr$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2633_ULE_1_4189_4253_OR_ETC___d14257 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd26 ; + // register csrf_mepcc_reg_data_rl + assign csrf_mepcc_reg_data_rl$D_IN = + csrf_mepcc_reg_data_lat_1$whas ? + rob$deqPort_0_deq_data[194:42] : + (MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget : + csrf_mepcc_reg_data_rl) ; + assign csrf_mepcc_reg_data_rl$EN = 1'd1 ; // register csrf_mideleg_11_reg - assign csrf_mideleg_11_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[11] ; + assign csrf_mideleg_11_reg$D_IN = + MUX_csrf_mideleg_11_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[11] : + MUX_csrf_stval_csr$write_1__VAL_1[11] ; assign csrf_mideleg_11_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd21 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd22 ; // register csrf_mideleg_1_0_reg - assign csrf_mideleg_1_0_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[1:0] ; + assign csrf_mideleg_1_0_reg$D_IN = + MUX_csrf_mideleg_11_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[1:0] : + MUX_csrf_stval_csr$write_1__VAL_1[1:0] ; assign csrf_mideleg_1_0_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd21 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd22 ; // register csrf_mideleg_5_3_reg - assign csrf_mideleg_5_3_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[5:3] ; + assign csrf_mideleg_5_3_reg$D_IN = + MUX_csrf_mideleg_11_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[5:3] : + MUX_csrf_stval_csr$write_1__VAL_1[5:3] ; assign csrf_mideleg_5_3_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd21 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd22 ; // register csrf_mideleg_9_7_reg - assign csrf_mideleg_9_7_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[9:7] ; + assign csrf_mideleg_9_7_reg$D_IN = + MUX_csrf_mideleg_11_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[9:7] : + MUX_csrf_stval_csr$write_1__VAL_1[9:7] ; assign csrf_mideleg_9_7_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd21 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd22 ; // register csrf_minstret_ehr_data_rl assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? - upd__h3639 : - IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 ; + upd__h3035 : + n__read__h1008440 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; // register csrf_mpp_reg - assign csrf_mpp_reg$D_IN = - MUX_csrf_mpp_reg$write_1__SEL_1 ? - MUX_csrf_mpp_reg$write_1__VAL_1 : - csrf_prv_reg ; + always@(MUX_csrf_mpp_reg$write_1__SEL_1 or + MUX_csrf_mpp_reg$write_1__VAL_1 or + MUX_csrf_ie_vec_3$write_1__SEL_2 or + csrf_prv_reg or + MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_mpp_reg$write_1__SEL_1: + csrf_mpp_reg$D_IN = MUX_csrf_mpp_reg$write_1__VAL_1; + MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mpp_reg$D_IN = csrf_prv_reg; + MUX_csrf_ie_vec_3$write_1__SEL_3: + csrf_mpp_reg$D_IN = f_csr_reqs$D_OUT[12:11]; + default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; + endcase assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2633_ULE_1_4189_4253_OR_ETC___d14257 ; + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + NOT_csrf_prv_reg_read__0075_ULE_1_2375_2490_OR_ETC___d22495 ; // register csrf_mprv_reg - assign csrf_mprv_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[17] ; + assign csrf_mprv_reg$D_IN = + MUX_csrf_ie_vec_3$write_1__SEL_3 ? + f_csr_reqs$D_OUT[17] : + MUX_csrf_stval_csr$write_1__VAL_1[17] ; assign csrf_mprv_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd19 ; // register csrf_mscratch_csr - assign csrf_mscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ; + assign csrf_mscratch_csr$D_IN = + MUX_csrf_mscratch_csr$write_1__SEL_1 ? + f_csr_reqs$D_OUT[63:0] : + rob$deqPort_0_deq_data[95:32] ; assign csrf_mscratch_csr$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd832 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd25 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd26 ; + + // register csrf_mtcc_reg + assign csrf_mtcc_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; + assign csrf_mtcc_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd18 && + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 == + 4'd6 ; + + // register csrf_mtdc_reg + assign csrf_mtdc_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; + assign csrf_mtdc_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd18 && + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 == + 4'd7 ; // register csrf_mtval_csr - assign csrf_mtval_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? - MUX_csrf_mtval_csr$write_1__VAL_1 : - rob$deqPort_0_deq_data[95:32] ; + always@(MUX_csrf_mtval_csr$write_1__SEL_1 or + rob$deqPort_0_deq_data or + MUX_csrf_ie_vec_3$write_1__SEL_2 or + MUX_csrf_mtval_csr$write_1__VAL_2 or + MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_mtval_csr$write_1__SEL_1: + csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; + MUX_csrf_ie_vec_3$write_1__SEL_2: + csrf_mtval_csr$D_IN = MUX_csrf_mtval_csr$write_1__VAL_2; + MUX_csrf_mtval_csr$write_1__SEL_3: + csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; + default: csrf_mtval_csr$D_IN = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase assign csrf_mtval_csr$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd835 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2633_ULE_1_4189_4253_OR_ETC___d14257 || + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + NOT_csrf_prv_reg_read__0075_ULE_1_2375_2490_OR_ETC___d22495 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd28 ; - - // register csrf_mtvec_base_hi_reg - assign csrf_mtvec_base_hi_reg$D_IN = csrf_mscratch_csr$D_IN[63:2] ; - assign csrf_mtvec_base_hi_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd23 ; - - // register csrf_mtvec_mode_low_reg - assign csrf_mtvec_mode_low_reg$D_IN = csrf_mscratch_csr$D_IN[0] ; - assign csrf_mtvec_mode_low_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd23 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd29 ; // register csrf_mxr_reg - assign csrf_mxr_reg$D_IN = csrf_mscratch_csr$D_IN[19] ; + assign csrf_mxr_reg$D_IN = + MUX_csrf_ie_vec_0$write_1__SEL_1 ? + MUX_csrf_stval_csr$write_1__VAL_1[19] : + f_csr_reqs$D_OUT[19] ; assign csrf_mxr_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd8 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18) ; + MUX_csrf_ie_vec_0$write_1__SEL_1 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd256 || + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_ppn_reg - assign csrf_ppn_reg$D_IN = csrf_mscratch_csr$D_IN[43:0] ; + assign csrf_ppn_reg$D_IN = + MUX_csrf_ppn_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[43:0] : + MUX_csrf_stval_csr$write_1__VAL_1[43:0] ; assign csrf_ppn_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd17 ; // register csrf_prev_ie_vec_0 - assign csrf_prev_ie_vec_0$D_IN = csrf_mscratch_csr$D_IN[4] ; + assign csrf_prev_ie_vec_0$D_IN = + MUX_csrf_ie_vec_0$write_1__SEL_1 ? + MUX_csrf_stval_csr$write_1__VAL_1[4] : + f_csr_reqs$D_OUT[4] ; assign csrf_prev_ie_vec_0$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd8 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18) ; + MUX_csrf_ie_vec_0$write_1__SEL_1 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd256 || + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_prev_ie_vec_1 - assign csrf_prev_ie_vec_1$D_IN = - MUX_csrf_prev_ie_vec_1$write_1__SEL_1 ? - MUX_csrf_prev_ie_vec_1$write_1__VAL_1 : - csrf_ie_vec_1 ; + always@(MUX_csrf_prev_ie_vec_1$write_1__SEL_1 or + MUX_csrf_prev_ie_vec_1$write_1__VAL_1 or + MUX_csrf_ie_vec_1$write_1__SEL_2 or + csrf_ie_vec_1 or + MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_prev_ie_vec_1$write_1__SEL_1: + csrf_prev_ie_vec_1$D_IN = MUX_csrf_prev_ie_vec_1$write_1__VAL_1; + MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_prev_ie_vec_1$D_IN = csrf_ie_vec_1; + MUX_csrf_ie_vec_0$write_1__SEL_2: + csrf_prev_ie_vec_1$D_IN = f_csr_reqs$D_OUT[5]; + default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; + endcase assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd256 || + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_prev_ie_vec_3 - assign csrf_prev_ie_vec_3$D_IN = - MUX_csrf_prev_ie_vec_3$write_1__SEL_1 ? - MUX_csrf_prev_ie_vec_3$write_1__VAL_1 : - csrf_ie_vec_3 ; + always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or + MUX_csrf_prev_ie_vec_3$write_1__VAL_1 or + MUX_csrf_ie_vec_3$write_1__SEL_2 or + csrf_ie_vec_3 or + MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_prev_ie_vec_3$write_1__SEL_1: + csrf_prev_ie_vec_3$D_IN = MUX_csrf_prev_ie_vec_3$write_1__VAL_1; + MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_prev_ie_vec_3$D_IN = csrf_ie_vec_3; + MUX_csrf_ie_vec_3$write_1__SEL_3: + csrf_prev_ie_vec_3$D_IN = f_csr_reqs$D_OUT[7]; + default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; + endcase assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2633_ULE_1_4189_4253_OR_ETC___d14257 ; + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + NOT_csrf_prv_reg_read__0075_ULE_1_2375_2490_OR_ETC___d22495 ; // register csrf_prv_reg - assign csrf_prv_reg$D_IN = - MUX_csrf_prv_reg$write_1__SEL_1 ? - MUX_csrf_prv_reg$write_1__VAL_1 : - MUX_csrf_prv_reg$write_1__VAL_2 ; + always@(MUX_csrf_prv_reg$write_1__SEL_1 or + MUX_csrf_prv_reg$write_1__VAL_1 or + MUX_commitStage_rg_serial_num$write_1__SEL_1 or + MUX_csrf_prv_reg$write_1__VAL_2 or + MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_prv_reg$write_1__SEL_1: + csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; + MUX_commitStage_rg_serial_num$write_1__SEL_1: + csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_2; + MUX_csrf_prv_reg$write_1__SEL_3: + csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0]; + default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; + endcase assign csrf_prv_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 || + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1968 ; + + // register csrf_rg_dcsr + always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or + rob$deqPort_0_deq_data or + MUX_commitStage_rg_run_state$write_1__SEL_1 or + MUX_csrf_rg_dcsr$write_1__VAL_2 or + MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_rg_dcsr$write_1__SEL_1: + csrf_rg_dcsr$D_IN = rob$deqPort_0_deq_data[95:32]; + MUX_commitStage_rg_run_state$write_1__SEL_1: + csrf_rg_dcsr$D_IN = MUX_csrf_rg_dcsr$write_1__VAL_2; + MUX_csrf_prv_reg$write_1__SEL_3: + csrf_rg_dcsr$D_IN = f_csr_reqs$D_OUT[63:0]; + default: csrf_rg_dcsr$D_IN = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + assign csrf_rg_dcsr$EN = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + NOT_commitStage_commitTrap_2029_BITS_44_TO_43__ETC___d22295 || + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - (rob$deqPort_0_deq_data[186:182] == 5'd19 || - rob$deqPort_0_deq_data[186:182] == 5'd20) || - WILL_FIRE_RL_commitStage_doCommitTrap_handle ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd42 ; + + // register csrf_rg_dpc + assign csrf_rg_dpc$D_IN = csrf_sepcc_reg_data_lat_0$wget ; + assign csrf_rg_dpc$EN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; + + // register csrf_rg_dscratch0 + assign csrf_rg_dscratch0$D_IN = + MUX_csrf_rg_dscratch0$write_1__SEL_1 ? + f_csr_reqs$D_OUT[63:0] : + rob$deqPort_0_deq_data[95:32] ; + assign csrf_rg_dscratch0$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1970 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd44 ; + + // register csrf_rg_dscratch1 + assign csrf_rg_dscratch1$D_IN = + MUX_csrf_rg_dscratch1$write_1__SEL_1 ? + f_csr_reqs$D_OUT[63:0] : + rob$deqPort_0_deq_data[95:32] ; + assign csrf_rg_dscratch1$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1971 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd45 ; + + // register csrf_rg_tdata1_data + assign csrf_rg_tdata1_data$D_IN = + MUX_csrf_rg_tdata1_data$write_1__SEL_1 ? + f_csr_reqs$D_OUT[58:0] : + MUX_csrf_stval_csr$write_1__VAL_1[58:0] ; + assign csrf_rg_tdata1_data$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1953 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd39 ; + + // register csrf_rg_tdata1_dmode + assign csrf_rg_tdata1_dmode$D_IN = + MUX_csrf_rg_tdata1_data$write_1__SEL_1 ? + f_csr_reqs$D_OUT[59] : + MUX_csrf_stval_csr$write_1__VAL_1[59] ; + assign csrf_rg_tdata1_dmode$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1953 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd39 ; + + // register csrf_rg_tdata2 + assign csrf_rg_tdata2$D_IN = + MUX_csrf_rg_tdata2$write_1__SEL_1 ? + f_csr_reqs$D_OUT[63:0] : + rob$deqPort_0_deq_data[95:32] ; + assign csrf_rg_tdata2$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1954 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd40 ; + + // register csrf_rg_tdata3 + assign csrf_rg_tdata3$D_IN = + MUX_csrf_rg_tdata3$write_1__SEL_1 ? + f_csr_reqs$D_OUT[63:0] : + rob$deqPort_0_deq_data[95:32] ; + assign csrf_rg_tdata3$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1955 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd41 ; + + // register csrf_rg_tselect + assign csrf_rg_tselect$D_IN = + MUX_csrf_rg_tselect$write_1__SEL_1 ? + f_csr_reqs$D_OUT[63:0] : + rob$deqPort_0_deq_data[95:32] ; + assign csrf_rg_tselect$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1952 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd38 ; + + // register csrf_sScratchC_reg + assign csrf_sScratchC_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; + assign csrf_sScratchC_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd18 && + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 == + 4'd4 ; // register csrf_scause_code_reg - assign csrf_scause_code_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? - cause_code__h692187 : - csrf_mscratch_csr$D_IN[3:0] ; + always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or + MUX_csrf_stval_csr$write_1__VAL_1 or + MUX_csrf_ie_vec_1$write_1__SEL_2 or + cause_code__h992427 or + MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_scause_code_reg$write_1__SEL_1: + csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; + MUX_csrf_ie_vec_1$write_1__SEL_2: + csrf_scause_code_reg$D_IN = cause_code__h992427; + MUX_csrf_scause_code_reg$write_1__SEL_3: + csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; + default: csrf_scause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; + endcase assign csrf_scause_code_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 || + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd14 ; // register csrf_scause_interrupt_reg - assign csrf_scause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? - commitStage_commitTrap[4] : - csrf_mscratch_csr$D_IN[63] ; + always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or + MUX_csrf_stval_csr$write_1__VAL_1 or + MUX_csrf_ie_vec_1$write_1__SEL_2 or + cause_interrupt__h992425 or + MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_scause_code_reg$write_1__SEL_1: + csrf_scause_interrupt_reg$D_IN = + MUX_csrf_stval_csr$write_1__VAL_1[63]; + MUX_csrf_ie_vec_1$write_1__SEL_2: + csrf_scause_interrupt_reg$D_IN = cause_interrupt__h992425; + MUX_csrf_scause_code_reg$write_1__SEL_3: + csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; + default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; + endcase assign csrf_scause_interrupt_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 || + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd14 ; // register csrf_scounteren_cy_reg - assign csrf_scounteren_cy_reg$D_IN = csrf_mscratch_csr$D_IN[0] ; + assign csrf_scounteren_cy_reg$D_IN = + MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[0] : + MUX_csrf_stval_csr$write_1__VAL_1[0] ; assign csrf_scounteren_cy_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd11 ; // register csrf_scounteren_ir_reg - assign csrf_scounteren_ir_reg$D_IN = csrf_mscratch_csr$D_IN[2] ; + assign csrf_scounteren_ir_reg$D_IN = + MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[2] : + MUX_csrf_stval_csr$write_1__VAL_1[2] ; assign csrf_scounteren_ir_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd11 ; // register csrf_scounteren_tm_reg - assign csrf_scounteren_tm_reg$D_IN = csrf_mscratch_csr$D_IN[1] ; + assign csrf_scounteren_tm_reg$D_IN = + MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[1] : + MUX_csrf_stval_csr$write_1__VAL_1[1] ; assign csrf_scounteren_tm_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd11 ; - // register csrf_sepc_csr - assign csrf_sepc_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? - commitStage_commitTrap[132:69] : - rob$deqPort_0_deq_data[95:32] ; - assign csrf_sepc_csr$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd13 ; + // register csrf_sepcc_reg_data_rl + assign csrf_sepcc_reg_data_rl$D_IN = + csrf_sepcc_reg_data_lat_1$whas ? + rob$deqPort_0_deq_data[194:42] : + (MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget : + csrf_sepcc_reg_data_rl) ; + assign csrf_sepcc_reg_data_rl$EN = 1'd1 ; // register csrf_software_int_en_vec_0 - assign csrf_software_int_en_vec_0$D_IN = csrf_mscratch_csr$D_IN[0] ; - assign csrf_software_int_en_vec_0$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd9 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd22) ; + assign csrf_software_int_en_vec_0$D_IN = 1'b0 ; + assign csrf_software_int_en_vec_0$EN = 1'b0 ; // register csrf_software_int_en_vec_1 - assign csrf_software_int_en_vec_1$D_IN = csrf_mscratch_csr$D_IN[1] ; + assign csrf_software_int_en_vec_1$D_IN = + MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ? + MUX_csrf_stval_csr$write_1__VAL_1[1] : + f_csr_reqs$D_OUT[1] ; assign csrf_software_int_en_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd9 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd22) ; + MUX_csrf_external_int_en_vec_1$write_1__SEL_1 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd260 || + f_csr_reqs$D_OUT[75:64] == 12'd772) ; // register csrf_software_int_en_vec_3 - assign csrf_software_int_en_vec_3$D_IN = csrf_mscratch_csr$D_IN[3] ; + assign csrf_software_int_en_vec_3$D_IN = + MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ? + f_csr_reqs$D_OUT[3] : + MUX_csrf_stval_csr$write_1__VAL_1[3] ; assign csrf_software_int_en_vec_3$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd22 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd23 ; // register csrf_software_int_pend_vec_0 - assign csrf_software_int_pend_vec_0$D_IN = csrf_mscratch_csr$D_IN[0] ; - assign csrf_software_int_pend_vec_0$EN = - MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ; + assign csrf_software_int_pend_vec_0$D_IN = 1'b0 ; + assign csrf_software_int_pend_vec_0$EN = 1'b0 ; // register csrf_software_int_pend_vec_1 - assign csrf_software_int_pend_vec_1$D_IN = csrf_mscratch_csr$D_IN[1] ; + assign csrf_software_int_pend_vec_1$D_IN = + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ? + MUX_csrf_stval_csr$write_1__VAL_1[1] : + f_csr_reqs$D_OUT[1] ; assign csrf_software_int_pend_vec_1$EN = - MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ; + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd324 || + f_csr_reqs$D_OUT[75:64] == 12'd836) ; // register csrf_software_int_pend_vec_3 assign csrf_software_int_pend_vec_3$D_IN = - MUX_csrf_debug_int_pend$write_1__SEL_1 ? - csrf_mscratch_csr$D_IN[3] : - MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 ; + (mmio_pRqQ_data_0[37:36] == 2'd2) ? + mmio_pRqQ_data_0[0] : + amoExec___d773[0] ; assign csrf_software_int_pend_vec_3$EN = WILL_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_data_0[38] && mmio_pRqQ_data_0[37:36] != 2'd0 && - mmio_pRqQ_data_0[37:36] != 2'd1 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd29 ; + mmio_pRqQ_data_0[37:36] != 2'd1 ; // register csrf_spp_reg - assign csrf_spp_reg$D_IN = - MUX_csrf_spp_reg$write_1__SEL_1 ? - MUX_csrf_spp_reg$write_1__VAL_1 : - csrf_prv_reg[0] ; + always@(MUX_csrf_spp_reg$write_1__SEL_1 or + MUX_csrf_spp_reg$write_1__VAL_1 or + MUX_csrf_ie_vec_1$write_1__SEL_2 or + csrf_prv_reg or + MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_spp_reg$write_1__SEL_1: + csrf_spp_reg$D_IN = MUX_csrf_spp_reg$write_1__VAL_1; + MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_spp_reg$D_IN = csrf_prv_reg[0]; + MUX_csrf_ie_vec_0$write_1__SEL_2: csrf_spp_reg$D_IN = f_csr_reqs$D_OUT[8]; + default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; + endcase assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd256 || + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_sscratch_csr - assign csrf_sscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ; + assign csrf_sscratch_csr$D_IN = + MUX_csrf_sscratch_csr$write_1__SEL_1 ? + f_csr_reqs$D_OUT[63:0] : + rob$deqPort_0_deq_data[95:32] ; assign csrf_sscratch_csr$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd320 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd12 ; // register csrf_stats_module_doStats assign csrf_stats_module_doStats$D_IN = recvDoStats_x ; assign csrf_stats_module_doStats$EN = EN_recvDoStats ; - // register csrf_stval_csr - assign csrf_stval_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? - MUX_csrf_mtval_csr$write_1__VAL_1 : - rob$deqPort_0_deq_data[95:32] ; - assign csrf_stval_csr$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 || + // register csrf_stcc_reg + assign csrf_stcc_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; + assign csrf_stcc_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd18 && + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 == + 4'd2 ; + + // register csrf_stdc_reg + assign csrf_stdc_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; + assign csrf_stdc_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd18 && + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 == + 4'd3 ; + + // register csrf_stval_csr + always@(MUX_csrf_stval_csr$write_1__SEL_1 or + rob$deqPort_0_deq_data or + MUX_csrf_ie_vec_1$write_1__SEL_2 or + MUX_csrf_mtval_csr$write_1__VAL_2 or + MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_stval_csr$write_1__SEL_1: + csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; + MUX_csrf_ie_vec_1$write_1__SEL_2: + csrf_stval_csr$D_IN = MUX_csrf_mtval_csr$write_1__VAL_2; + MUX_csrf_stval_csr$write_1__SEL_3: + csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; + default: csrf_stval_csr$D_IN = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + assign csrf_stval_csr$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd323 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 && + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd15 ; - // register csrf_stvec_base_hi_reg - assign csrf_stvec_base_hi_reg$D_IN = csrf_sscratch_csr$D_IN[63:2] ; - assign csrf_stvec_base_hi_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd10 ; - - // register csrf_stvec_mode_low_reg - assign csrf_stvec_mode_low_reg$D_IN = csrf_sscratch_csr$D_IN[0] ; - assign csrf_stvec_mode_low_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd10 ; - // register csrf_sum_reg - assign csrf_sum_reg$D_IN = csrf_sscratch_csr$D_IN[18] ; + assign csrf_sum_reg$D_IN = + MUX_csrf_ie_vec_0$write_1__SEL_1 ? + MUX_csrf_stval_csr$write_1__VAL_1[18] : + f_csr_reqs$D_OUT[18] ; assign csrf_sum_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd8 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18) ; + MUX_csrf_ie_vec_0$write_1__SEL_1 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd256 || + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_time_reg assign csrf_time_reg$D_IN = mmioToPlatform_setTime_t ; assign csrf_time_reg$EN = EN_mmioToPlatform_setTime ; // register csrf_timer_int_en_vec_0 - assign csrf_timer_int_en_vec_0$D_IN = csrf_sscratch_csr$D_IN[4] ; - assign csrf_timer_int_en_vec_0$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd9 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd22) ; + assign csrf_timer_int_en_vec_0$D_IN = 1'b0 ; + assign csrf_timer_int_en_vec_0$EN = 1'b0 ; // register csrf_timer_int_en_vec_1 - assign csrf_timer_int_en_vec_1$D_IN = csrf_sscratch_csr$D_IN[5] ; + assign csrf_timer_int_en_vec_1$D_IN = + MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ? + MUX_csrf_stval_csr$write_1__VAL_1[5] : + f_csr_reqs$D_OUT[5] ; assign csrf_timer_int_en_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd9 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd22) ; + MUX_csrf_external_int_en_vec_1$write_1__SEL_1 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd260 || + f_csr_reqs$D_OUT[75:64] == 12'd772) ; // register csrf_timer_int_en_vec_3 - assign csrf_timer_int_en_vec_3$D_IN = csrf_sscratch_csr$D_IN[7] ; + assign csrf_timer_int_en_vec_3$D_IN = + MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ? + f_csr_reqs$D_OUT[7] : + MUX_csrf_stval_csr$write_1__VAL_1[7] ; assign csrf_timer_int_en_vec_3$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd22 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd23 ; // register csrf_timer_int_pend_vec_0 - assign csrf_timer_int_pend_vec_0$D_IN = csrf_sscratch_csr$D_IN[4] ; - assign csrf_timer_int_pend_vec_0$EN = - MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ; + assign csrf_timer_int_pend_vec_0$D_IN = 1'b0 ; + assign csrf_timer_int_pend_vec_0$EN = 1'b0 ; // register csrf_timer_int_pend_vec_1 - assign csrf_timer_int_pend_vec_1$D_IN = csrf_sscratch_csr$D_IN[5] ; + assign csrf_timer_int_pend_vec_1$D_IN = + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ? + MUX_csrf_stval_csr$write_1__VAL_1[5] : + f_csr_reqs$D_OUT[5] ; assign csrf_timer_int_pend_vec_1$EN = - MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ; + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 || + WILL_FIRE_RL_rl_debug_csr_write && + (f_csr_reqs$D_OUT[75:64] == 12'd324 || + f_csr_reqs$D_OUT[75:64] == 12'd836) ; // register csrf_timer_int_pend_vec_3 assign csrf_timer_int_pend_vec_3$D_IN = mmio_pRqQ_data_0[0] ; @@ -13037,52 +13841,88 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] == 2'd2 ; // register csrf_tsr_reg - assign csrf_tsr_reg$D_IN = csrf_sscratch_csr$D_IN[22] ; + assign csrf_tsr_reg$D_IN = + MUX_csrf_ie_vec_3$write_1__SEL_3 ? + f_csr_reqs$D_OUT[22] : + MUX_csrf_stval_csr$write_1__VAL_1[22] ; assign csrf_tsr_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd19 ; // register csrf_tvm_reg - assign csrf_tvm_reg$D_IN = csrf_sscratch_csr$D_IN[20] ; + assign csrf_tvm_reg$D_IN = + MUX_csrf_ie_vec_3$write_1__SEL_3 ? + f_csr_reqs$D_OUT[20] : + MUX_csrf_stval_csr$write_1__VAL_1[20] ; assign csrf_tvm_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd19 ; // register csrf_tw_reg - assign csrf_tw_reg$D_IN = csrf_sscratch_csr$D_IN[21] ; + assign csrf_tw_reg$D_IN = + MUX_csrf_ie_vec_3$write_1__SEL_3 ? + f_csr_reqs$D_OUT[21] : + MUX_csrf_stval_csr$write_1__VAL_1[21] ; assign csrf_tw_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18 ; + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd19 ; // register csrf_vm_mode_sv39_reg - assign csrf_vm_mode_sv39_reg$D_IN = csrf_sscratch_csr$D_IN[63] ; + assign csrf_vm_mode_sv39_reg$D_IN = + MUX_csrf_ppn_reg$write_1__SEL_1 ? + f_csr_reqs$D_OUT[63] : + MUX_csrf_stval_csr$write_1__VAL_1[63] ; assign csrf_vm_mode_sv39_reg$EN = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd17 ; + // register flush_brpred + assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; + assign flush_brpred$EN = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + NOT_commitStage_commitTrap_2029_BITS_44_TO_43__ETC___d22295 || + WILL_FIRE_RL_flushBrPred ; + + // register flush_caches + assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; + assign flush_caches$EN = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + NOT_commitStage_commitTrap_2029_BITS_44_TO_43__ETC___d22295 || + WILL_FIRE_RL_flushCaches ; + // register flush_reservation - assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; + assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_2 ; assign flush_reservation$EN = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || - WILL_FIRE_RL_commitStage_doCommitSystemInst || - WILL_FIRE_RL_commitStage_doCommitTrap_handle ; + WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs assign flush_tlbs$D_IN = !MUX_flush_tlbs$write_1__SEL_1 ; assign flush_tlbs$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + NOT_commitStage_commitTrap_2029_BITS_44_TO_43__ETC___d22295 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - (rob$deqPort_0_deq_data[186:182] == 5'd16 || - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + (rob$deqPort_0_deq_data[469:465] == 5'd21 || + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -13091,23 +13931,21 @@ module mkCore(CLK, // register mmio_cRqQ_data_0 assign mmio_cRqQ_data_0$D_IN = - { x__h45579, + { x_addr__h44221, (mmio_cRqQ_enqReq_lat_0$whas ? - mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 : - mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ? + mmio_cRqQ_enqReq_lat_0$wget[150:149] == 2'd0 : + mmio_cRqQ_enqReq_rl[150:149] == 2'd0) ? { 5'd2, mmio_cRqQ_enqReq_lat_0$whas ? - mmio_cRqQ_enqReq_lat_0$wget[72] : - mmio_cRqQ_enqReq_rl[72] } : - IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463, + mmio_cRqQ_enqReq_lat_0$wget[145] : + mmio_cRqQ_enqReq_rl[145] } : + IF_IF_mmio_cRqQ_enqReq_lat_1_whas__87_THEN_mmi_ETC___d408, mmio_cRqQ_enqReq_lat_0$whas ? - mmio_cRqQ_enqReq_lat_0$wget[71:64] : - mmio_cRqQ_enqReq_rl[71:64], - x__h48115 } ; + mmio_cRqQ_enqReq_lat_0$wget[144:0] : + mmio_cRqQ_enqReq_rl[144:0] } ; assign mmio_cRqQ_data_0$EN = - NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 && - mmio_cRqQ_enqReq_dummy2_2$Q_OUT && - IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ; + !mmio_cRqQ_clearReq_rl && + IF_mmio_cRqQ_enqReq_lat_1_whas__87_THEN_mmio_c_ETC___d296 ; // register mmio_cRqQ_deqReq_rl assign mmio_cRqQ_deqReq_rl$D_IN = 1'd0 ; @@ -13115,19 +13953,25 @@ module mkCore(CLK, // register mmio_cRqQ_empty assign mmio_cRqQ_empty$D_IN = - mmio_cRqQ_clearReq_dummy2_1$Q_OUT && mmio_cRqQ_clearReq_rl || - NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 ; + mmio_cRqQ_clearReq_rl || + (mmio_cRqQ_enqReq_lat_0$whas ? + !mmio_cRqQ_enqReq_lat_0$wget[215] : + !mmio_cRqQ_enqReq_rl[215]) && + (EN_mmioToPlatform_cRq_deq || mmio_cRqQ_deqReq_rl || + mmio_cRqQ_empty) ; assign mmio_cRqQ_empty$EN = 1'd1 ; // register mmio_cRqQ_enqReq_rl assign mmio_cRqQ_enqReq_rl$D_IN = - 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; + 216'h2AAAAAAAAAAAAAAAB4AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign mmio_cRqQ_enqReq_rl$EN = 1'd1 ; // register mmio_cRqQ_full assign mmio_cRqQ_full$D_IN = - NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 && - mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 ; + !mmio_cRqQ_clearReq_rl && + (IF_mmio_cRqQ_enqReq_lat_1_whas__87_THEN_mmio_c_ETC___d296 || + !EN_mmioToPlatform_cRq_deq && !mmio_cRqQ_deqReq_rl && + mmio_cRqQ_full) ; assign mmio_cRqQ_full$EN = 1'd1 ; // register mmio_cRsQ_clearReq_rl @@ -13140,9 +13984,8 @@ module mkCore(CLK, mmio_cRsQ_enqReq_lat_0$wget[0] : mmio_cRsQ_enqReq_rl[0] ; assign mmio_cRsQ_data_0$EN = - NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 && - mmio_cRsQ_enqReq_dummy2_2$Q_OUT && - IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ; + !mmio_cRsQ_clearReq_rl && + IF_mmio_cRsQ_enqReq_lat_1_whas__85_THEN_mmio_c_ETC___d694 ; // register mmio_cRsQ_deqReq_rl assign mmio_cRsQ_deqReq_rl$D_IN = 1'd0 ; @@ -13150,8 +13993,12 @@ module mkCore(CLK, // register mmio_cRsQ_empty assign mmio_cRsQ_empty$D_IN = - mmio_cRsQ_clearReq_dummy2_1$Q_OUT && mmio_cRsQ_clearReq_rl || - NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 ; + mmio_cRsQ_clearReq_rl || + (CAN_FIRE_RL_mmio_handlePRq ? + !mmio_cRsQ_enqReq_lat_0$wget[1] : + !mmio_cRsQ_enqReq_rl[1]) && + (EN_mmioToPlatform_cRs_deq || mmio_cRsQ_deqReq_rl || + mmio_cRsQ_empty) ; assign mmio_cRsQ_empty$EN = 1'd1 ; // register mmio_cRsQ_enqReq_rl @@ -13160,8 +14007,10 @@ module mkCore(CLK, // register mmio_cRsQ_full assign mmio_cRsQ_full$D_IN = - NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 && - mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 ; + !mmio_cRsQ_clearReq_rl && + (IF_mmio_cRsQ_enqReq_lat_1_whas__85_THEN_mmio_c_ETC___d694 || + !EN_mmioToPlatform_cRs_deq && !mmio_cRsQ_deqReq_rl && + mmio_cRsQ_full) ; assign mmio_cRsQ_full$EN = 1'd1 ; // register mmio_dataPendQ_clearReq_rl @@ -13174,9 +14023,10 @@ module mkCore(CLK, // register mmio_dataPendQ_empty assign mmio_dataPendQ_empty$D_IN = - mmio_dataPendQ_clearReq_dummy2_1$Q_OUT && mmio_dataPendQ_clearReq_rl || - NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 ; + !mmio_dataPendQ_enqReq_lat_0$whas && !mmio_dataPendQ_enqReq_rl && + (mmio_dataRespQ_deqReq_lat_0$whas || mmio_dataPendQ_deqReq_rl || + mmio_dataPendQ_empty) ; assign mmio_dataPendQ_empty$EN = 1'd1 ; // register mmio_dataPendQ_enqReq_rl @@ -13185,9 +14035,11 @@ module mkCore(CLK, // register mmio_dataPendQ_full assign mmio_dataPendQ_full$D_IN = - (!mmio_dataPendQ_clearReq_dummy2_1$Q_OUT || - !mmio_dataPendQ_clearReq_rl) && - mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 ; + !mmio_dataPendQ_clearReq_rl && + (mmio_dataPendQ_enqReq_lat_0$whas || mmio_dataPendQ_enqReq_rl || + !mmio_dataRespQ_deqReq_lat_0$whas && + !mmio_dataPendQ_deqReq_rl && + mmio_dataPendQ_full) ; assign mmio_dataPendQ_full$EN = 1'd1 ; // register mmio_dataReqQ_clearReq_rl @@ -13196,23 +14048,21 @@ module mkCore(CLK, // register mmio_dataReqQ_data_0 assign mmio_dataReqQ_data_0$D_IN = - { x__h17672, + { x_addr__h19852, (mmio_dataReqQ_enqReq_lat_0$whas ? - mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 : - mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ? + mmio_dataReqQ_enqReq_lat_0$wget[150:149] == 2'd0 : + mmio_dataReqQ_enqReq_rl[150:149] == 2'd0) ? { 5'd2, mmio_dataReqQ_enqReq_lat_0$whas ? - mmio_dataReqQ_enqReq_lat_0$wget[72] : - mmio_dataReqQ_enqReq_rl[72] } : - IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172, + mmio_dataReqQ_enqReq_lat_0$wget[145] : + mmio_dataReqQ_enqReq_rl[145] } : + IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__2_THEN__ETC___d165, mmio_dataReqQ_enqReq_lat_0$whas ? - mmio_dataReqQ_enqReq_lat_0$wget[71:64] : - mmio_dataReqQ_enqReq_rl[71:64], - x__h20210 } ; + mmio_dataReqQ_enqReq_lat_0$wget[144:0] : + mmio_dataReqQ_enqReq_rl[144:0] } ; assign mmio_dataReqQ_data_0$EN = - NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 && - mmio_dataReqQ_enqReq_dummy2_2$Q_OUT && - IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ; + !mmio_dataReqQ_clearReq_rl && + IF_mmio_dataReqQ_enqReq_lat_1_whas__2_THEN_mmi_ETC___d51 ; // register mmio_dataReqQ_deqReq_rl assign mmio_dataReqQ_deqReq_rl$D_IN = 1'd0 ; @@ -13220,20 +14070,25 @@ module mkCore(CLK, // register mmio_dataReqQ_empty assign mmio_dataReqQ_empty$D_IN = - mmio_dataReqQ_clearReq_dummy2_1$Q_OUT && mmio_dataReqQ_clearReq_rl || - NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 ; + (mmio_dataReqQ_enqReq_lat_0$whas ? + !mmio_dataReqQ_enqReq_lat_0$wget[215] : + !mmio_dataReqQ_enqReq_rl[215]) && + (CAN_FIRE_RL_mmio_sendDataReq || mmio_dataReqQ_deqReq_rl || + mmio_dataReqQ_empty) ; assign mmio_dataReqQ_empty$EN = 1'd1 ; // register mmio_dataReqQ_enqReq_rl assign mmio_dataReqQ_enqReq_rl$D_IN = - 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; + 216'h2AAAAAAAAAAAAAAAB4AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign mmio_dataReqQ_enqReq_rl$EN = 1'd1 ; // register mmio_dataReqQ_full assign mmio_dataReqQ_full$D_IN = - NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 && - mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 ; + !mmio_dataReqQ_clearReq_rl && + (IF_mmio_dataReqQ_enqReq_lat_1_whas__2_THEN_mmi_ETC___d51 || + !CAN_FIRE_RL_mmio_sendDataReq && !mmio_dataReqQ_deqReq_rl && + mmio_dataReqQ_full) ; assign mmio_dataReqQ_full$EN = 1'd1 ; // register mmio_dataRespQ_clearReq_rl @@ -13243,12 +14098,11 @@ module mkCore(CLK, // register mmio_dataRespQ_data_0 assign mmio_dataRespQ_data_0$D_IN = CAN_FIRE_RL_mmio_sendDataResp ? - mmio_dataRespQ_enqReq_lat_0$wget[64:0] : - mmio_dataRespQ_enqReq_rl[64:0] ; + mmio_dataRespQ_enqReq_lat_0$wget[129:0] : + mmio_dataRespQ_enqReq_rl[129:0] ; assign mmio_dataRespQ_data_0$EN = - NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 && - mmio_dataRespQ_enqReq_dummy2_2$Q_OUT && - IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ; + !mmio_dataRespQ_clearReq_rl && + IF_mmio_dataRespQ_enqReq_lat_1_whas__73_THEN_m_ETC___d182 ; // register mmio_dataRespQ_deqReq_rl assign mmio_dataRespQ_deqReq_rl$D_IN = 1'd0 ; @@ -13256,19 +14110,26 @@ module mkCore(CLK, // register mmio_dataRespQ_empty assign mmio_dataRespQ_empty$D_IN = - mmio_dataRespQ_clearReq_dummy2_1$Q_OUT && mmio_dataRespQ_clearReq_rl || - NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 ; + (CAN_FIRE_RL_mmio_sendDataResp ? + !mmio_dataRespQ_enqReq_lat_0$wget[130] : + !mmio_dataRespQ_enqReq_rl[130]) && + (mmio_dataRespQ_deqReq_lat_0$whas || mmio_dataRespQ_deqReq_rl || + mmio_dataRespQ_empty) ; assign mmio_dataRespQ_empty$EN = 1'd1 ; // register mmio_dataRespQ_enqReq_rl - assign mmio_dataRespQ_enqReq_rl$D_IN = 66'h0AAAAAAAAAAAAAAAA ; + assign mmio_dataRespQ_enqReq_rl$D_IN = + 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign mmio_dataRespQ_enqReq_rl$EN = 1'd1 ; // register mmio_dataRespQ_full assign mmio_dataRespQ_full$D_IN = - NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 && - mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 ; + !mmio_dataRespQ_clearReq_rl && + (IF_mmio_dataRespQ_enqReq_lat_1_whas__73_THEN_m_ETC___d182 || + !mmio_dataRespQ_deqReq_lat_0$whas && + !mmio_dataRespQ_deqReq_rl && + mmio_dataRespQ_full) ; assign mmio_dataRespQ_full$EN = 1'd1 ; // register mmio_fromHostAddr @@ -13291,12 +14152,11 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[32] : mmio_pRqQ_enqReq_rl[32] } : - IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766, - x_data__h65373 } ; + IF_IF_mmio_pRqQ_enqReq_lat_1_whas__56_THEN_mmi_ETC___d677, + x_data__h60109 } ; assign mmio_pRqQ_data_0$EN = - NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 && - mmio_pRqQ_enqReq_dummy2_2$Q_OUT && - IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ; + !mmio_pRqQ_clearReq_rl && + IF_mmio_pRqQ_enqReq_lat_1_whas__56_THEN_mmio_p_ETC___d565 ; // register mmio_pRqQ_deqReq_rl assign mmio_pRqQ_deqReq_rl$D_IN = 1'd0 ; @@ -13304,8 +14164,12 @@ module mkCore(CLK, // register mmio_pRqQ_empty assign mmio_pRqQ_empty$D_IN = - mmio_pRqQ_clearReq_dummy2_1$Q_OUT && mmio_pRqQ_clearReq_rl || - NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 ; + mmio_pRqQ_clearReq_rl || + (EN_mmioToPlatform_pRq_enq ? + !mmio_pRqQ_enqReq_lat_0$wget[39] : + !mmio_pRqQ_enqReq_rl[39]) && + (CAN_FIRE_RL_mmio_handlePRq || mmio_pRqQ_deqReq_rl || + mmio_pRqQ_empty) ; assign mmio_pRqQ_empty$EN = 1'd1 ; // register mmio_pRqQ_enqReq_rl @@ -13314,8 +14178,10 @@ module mkCore(CLK, // register mmio_pRqQ_full assign mmio_pRqQ_full$D_IN = - NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 && - mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 ; + !mmio_pRqQ_clearReq_rl && + (IF_mmio_pRqQ_enqReq_lat_1_whas__56_THEN_mmio_p_ETC___d565 || + !CAN_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_deqReq_rl && + mmio_pRqQ_full) ; assign mmio_pRqQ_full$EN = 1'd1 ; // register mmio_pRsQ_clearReq_rl @@ -13325,13 +14191,12 @@ module mkCore(CLK, // register mmio_pRsQ_data_0 assign mmio_pRsQ_data_0$D_IN = { EN_mmioToPlatform_pRs_enq ? - mmio_pRsQ_enqReq_lat_0$wget[66] : - mmio_pRsQ_enqReq_rl[66], - IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 } ; + mmio_pRsQ_enqReq_lat_0$wget[130] : + mmio_pRsQ_enqReq_rl[130], + IF_IF_mmio_pRsQ_enqReq_lat_1_whas__15_THEN_NOT_ETC___d550 } ; assign mmio_pRsQ_data_0$EN = - NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 && - mmio_pRsQ_enqReq_dummy2_2$Q_OUT && - IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ; + !mmio_pRsQ_clearReq_rl && + IF_mmio_pRsQ_enqReq_lat_1_whas__15_THEN_mmio_p_ETC___d424 ; // register mmio_pRsQ_deqReq_rl assign mmio_pRsQ_deqReq_rl$D_IN = 1'd0 ; @@ -13339,18 +14204,24 @@ module mkCore(CLK, // register mmio_pRsQ_empty assign mmio_pRsQ_empty$D_IN = - mmio_pRsQ_clearReq_dummy2_1$Q_OUT && mmio_pRsQ_clearReq_rl || - NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 ; + mmio_pRsQ_clearReq_rl || + (EN_mmioToPlatform_pRs_enq ? + !mmio_pRsQ_enqReq_lat_0$wget[131] : + !mmio_pRsQ_enqReq_rl[131]) && + (mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl || + mmio_pRsQ_empty) ; assign mmio_pRsQ_empty$EN = 1'd1 ; // register mmio_pRsQ_enqReq_rl - assign mmio_pRsQ_enqReq_rl$D_IN = 68'h2AAAAAAAAAAAAAAAA ; + assign mmio_pRsQ_enqReq_rl$D_IN = 132'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign mmio_pRsQ_enqReq_rl$EN = 1'd1 ; // register mmio_pRsQ_full assign mmio_pRsQ_full$D_IN = - NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 && - mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 ; + !mmio_pRsQ_clearReq_rl && + (IF_mmio_pRsQ_enqReq_lat_1_whas__15_THEN_mmio_p_ETC___d424 || + !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl && + mmio_pRsQ_full) ; assign mmio_pRsQ_full$EN = 1'd1 ; // register mmio_toHostAddr @@ -13361,30 +14232,80 @@ module mkCore(CLK, assign outOfReset$D_IN = 1'd1 ; assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ; + // register renameStage_rg_m_halt_req + always@(WILL_FIRE_RL_rl_debug_resume or + WILL_FIRE_RL_rl_debug_halt_req or + MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or + MUX_renameStage_rg_m_halt_req$write_1__SEL_2) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10; + WILL_FIRE_RL_rl_debug_halt_req: renameStage_rg_m_halt_req$D_IN = 5'd30; + MUX_renameStage_rg_m_halt_req$write_1__SEL_1 || + MUX_renameStage_rg_m_halt_req$write_1__SEL_2: + renameStage_rg_m_halt_req$D_IN = 5'd31; + default: renameStage_rg_m_halt_req$D_IN = + 5'b01010 /* unspecified value */ ; + endcase + end + assign renameStage_rg_m_halt_req$EN = + (WILL_FIRE_RL_renameStage_doRenaming_SystemInst || + WILL_FIRE_RL_renameStage_doRenaming_Trap) && + csrf_rg_dcsr[2] || + WILL_FIRE_RL_renameStage_doRenaming && + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21880 && + csrf_rg_dcsr[2] || + WILL_FIRE_RL_rl_debug_resume || + WILL_FIRE_RL_rl_debug_halt_req ; + + // register rg_core_run_state + always@(WILL_FIRE_RL_rl_debug_resume or + WILL_FIRE_RL_rl_debug_halted or + EN_coreReq_start or MUX_rg_core_run_state$write_1__SEL_4) + case (1'b1) + WILL_FIRE_RL_rl_debug_resume: rg_core_run_state$D_IN = 2'd2; + WILL_FIRE_RL_rl_debug_halted: rg_core_run_state$D_IN = 2'd1; + EN_coreReq_start: rg_core_run_state$D_IN = 2'd2; + MUX_rg_core_run_state$write_1__SEL_4: rg_core_run_state$D_IN = 2'd0; + default: rg_core_run_state$D_IN = 2'b10 /* unspecified value */ ; + endcase + assign rg_core_run_state$EN = + WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state || + WILL_FIRE_RL_rl_debug_halted || + WILL_FIRE_RL_rl_debug_resume || + EN_coreReq_start ; + // register started - assign started$D_IN = 1'd1 ; - assign started$EN = EN_coreReq_start ; + assign started$D_IN = WILL_FIRE_RL_rl_debug_resume || EN_coreReq_start ; + assign started$EN = + WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state || + WILL_FIRE_RL_rl_debug_resume || + EN_coreReq_start ; // register update_vm_info - assign update_vm_info$D_IN = !MUX_update_vm_info$write_1__SEL_1 ; + assign update_vm_info$D_IN = + !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || - WILL_FIRE_RL_commitStage_doCommitSystemInst || - WILL_FIRE_RL_commitStage_doCommitTrap_handle ; + WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule coreFix_aluExe_0_dispToRegQ assign coreFix_aluExe_0_dispToRegQ$enq_x = - { coreFix_aluExe_0_rsAlu$dispatchData[161:157], - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267, - coreFix_aluExe_0_rsAlu$dispatchData[135], - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268, + { coreFix_aluExe_0_rsAlu$dispatchData[233:229], + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q340, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341, + coreFix_aluExe_0_rsAlu$dispatchData[187:141], + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342, + coreFix_aluExe_0_rsAlu$dispatchData[128], + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343, coreFix_aluExe_0_rsAlu$dispatchData[122:90], coreFix_aluExe_0_rsAlu$dispatchData[65:21], coreFix_aluExe_0_rsAlu$dispatchData[89:66], coreFix_aluExe_0_rsAlu$dispatchData[8:4], coreFix_aluExe_0_rsAlu$dispatchData[20:9] } ; assign coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -13421,15 +14342,21 @@ module mkCore(CLK, // submodule coreFix_aluExe_0_exeToFinQ assign coreFix_aluExe_0_exeToFinQ$enq_x = - { coreFix_aluExe_0_regToExeQ$first[421:417], - coreFix_aluExe_0_regToExeQ$first[349:305], - basicExec___d12469[321:258], - coreFix_aluExe_0_regToExeQ$first[395], - basicExec___d12469[257:194], - basicExec___d12469[129:0], + { coreFix_aluExe_0_regToExeQ$first[821:817], + coreFix_aluExe_0_regToExeQ$first[677:633], + coreFix_aluExe_0_regToExeQ$first[18:17] != 2'b11, + basicExec___d19648[1159:997], + coreFix_aluExe_0_regToExeQ$first[729], + basicExec___d19648[996:933], + coreFix_aluExe_0_regToExeQ$first[716] && + coreFix_aluExe_0_regToExeQ$first[821:817] == 5'd18, + basicExec___d19648[932:770], + basicExec___d19648[606:271], + CASE_basicExec_9648_BITS_270_TO_266_0_basicExe_ETC__q344, + basicExec___d19648[265:0], coreFix_aluExe_0_regToExeQ$first[16:0] } ; assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -13466,20 +14393,19 @@ module mkCore(CLK, // submodule coreFix_aluExe_0_regToExeQ assign coreFix_aluExe_0_regToExeQ$enq_x = - { coreFix_aluExe_0_dispToRegQ$first[157:153], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270, - coreFix_aluExe_0_dispToRegQ$first[131], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271, + { coreFix_aluExe_0_dispToRegQ$first[229:225], + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q346, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347, + coreFix_aluExe_0_dispToRegQ$first[183:137], + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q348, + coreFix_aluExe_0_dispToRegQ$first[124], + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q349, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h634254, - x__h634255, - rob$getOrigPC_0_get, - rob$getOrigPredPC_0_get, - rob$getOrig_Inst_0_get, - coreFix_aluExe_0_dispToRegQ$first[16:0] } ; + NOT_coreFix_aluExe_0_dispToRegQ_first__8199_BI_ETC___d19248, + coreFix_aluExe_0_dispToRegQ$first[11:0] } ; assign coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -13559,7 +14485,7 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$setRegReady_3_put = - { 1'd1, coreFix_memExe_lsq$issueLd[71:65] } ; + { 1'd1, coreFix_memExe_lsq$issueLd[136:130] } ; always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 or @@ -13587,7 +14513,7 @@ module mkCore(CLK, end assign coreFix_aluExe_0_rsAlu$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -13613,7 +14539,9 @@ module mkCore(CLK, assign coreFix_aluExe_0_rsAlu$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 ; + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0) ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -13624,8 +14552,6 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && coreFix_aluExe_1_rsAlu$dispatchData[41] ; assign coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put = - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && @@ -13635,24 +14561,26 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ; + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] || + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ; assign coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put = _dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put && - coreFix_memExe_lsq$issueLd[74:73] != 2'd0 && - coreFix_memExe_lsq$issueLd[74:73] != 2'd1 && - coreFix_memExe_lsq$issueLd[72] ; + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137] ; assign coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put = (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) && - coreFix_memExe_lsq$firstSt[150] || + coreFix_memExe_lsq$firstSt[232] || (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) && - coreFix_memExe_lsq$firstLd[89] || + coreFix_memExe_lsq$firstLd[106] || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5594 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0 && coreFix_memExe_lsq$getHit[8] && !coreFix_memExe_lsq$getHit[9] ; @@ -13665,17 +14593,20 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_dispToRegQ assign coreFix_aluExe_1_dispToRegQ$enq_x = - { coreFix_aluExe_1_rsAlu$dispatchData[161:157], - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273, - coreFix_aluExe_1_rsAlu$dispatchData[135], - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274, + { coreFix_aluExe_1_rsAlu$dispatchData[233:229], + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q351, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352, + coreFix_aluExe_1_rsAlu$dispatchData[187:141], + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353, + coreFix_aluExe_1_rsAlu$dispatchData[128], + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, coreFix_aluExe_1_rsAlu$dispatchData[122:90], coreFix_aluExe_1_rsAlu$dispatchData[65:21], coreFix_aluExe_1_rsAlu$dispatchData[89:66], coreFix_aluExe_1_rsAlu$dispatchData[8:4], coreFix_aluExe_1_rsAlu$dispatchData[20:9] } ; assign coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -13711,15 +14642,21 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_exeToFinQ assign coreFix_aluExe_1_exeToFinQ$enq_x = - { coreFix_aluExe_1_regToExeQ$first[421:417], - coreFix_aluExe_1_regToExeQ$first[349:305], - basicExec___d11860[321:258], - coreFix_aluExe_1_regToExeQ$first[395], - basicExec___d11860[257:194], - basicExec___d11860[129:0], + { coreFix_aluExe_1_regToExeQ$first[821:817], + coreFix_aluExe_1_regToExeQ$first[677:633], + coreFix_aluExe_1_regToExeQ$first[18:17] != 2'b11, + basicExec___d17570[1159:997], + coreFix_aluExe_1_regToExeQ$first[729], + basicExec___d17570[996:933], + coreFix_aluExe_1_regToExeQ$first[716] && + coreFix_aluExe_1_regToExeQ$first[821:817] == 5'd18, + basicExec___d17570[932:770], + basicExec___d17570[606:271], + CASE_basicExec_7570_BITS_270_TO_266_0_basicExe_ETC__q355, + basicExec___d17570[265:0], coreFix_aluExe_1_regToExeQ$first[16:0] } ; assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -13756,20 +14693,19 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_regToExeQ assign coreFix_aluExe_1_regToExeQ$enq_x = - { coreFix_aluExe_1_dispToRegQ$first[157:153], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q276, - coreFix_aluExe_1_dispToRegQ$first[131], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277, + { coreFix_aluExe_1_dispToRegQ$first[229:225], + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q357, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358, + coreFix_aluExe_1_dispToRegQ$first[183:137], + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q359, + coreFix_aluExe_1_dispToRegQ$first[124], + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q360, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h613034, - x__h613035, - rob$getOrigPC_1_get, - rob$getOrigPredPC_1_get, - rob$getOrig_Inst_1_get, - coreFix_aluExe_1_dispToRegQ$first[16:0] } ; + NOT_coreFix_aluExe_1_dispToRegQ_first__5590_BI_ETC___d17170, + coreFix_aluExe_1_dispToRegQ$first[11:0] } ; assign coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -13805,29 +14741,26 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h661043 == 1'd1 && - fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837) ? - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], + (k__h942381 == 1'd1 && fetchStage$pipelines_0_canDeq && + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21777) ? + { fetchStage$pipelines_0_first[272:268], + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20171, + IF_fetchStage_pipelines_0_first__0045_BITS_237_ETC___d20400, + fetchStage$pipelines_0_first[328:305], regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, - fetchStage$pipelines_0_first[194:192] == 3'd1, + fetchStage$pipelines_0_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : - { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361, - fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437, - fetchStage$pipelines_1_first[160:128], - fetchStage$pipelines_1_first[255:232], + { fetchStage$pipelines_1_first[272:268], + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21119, + IF_fetchStage_pipelines_1_first__0054_BITS_237_ETC___d21348, + fetchStage$pipelines_1_first[328:305], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675346, - fetchStage$pipelines_1_first[194:192] == 3'd1, + renaming_spec_bits__h965955, + fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; assign coreFix_aluExe_1_rsAlu$setRegReady_0_put = @@ -13899,7 +14832,7 @@ module mkCore(CLK, end assign coreFix_aluExe_1_rsAlu$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -13923,12 +14856,7 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_1_rsAlu$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && - (k__h661043 == 1'd1 && - fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837 || - fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13924 == - 1'd1 && - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13941) ; + WILL_FIRE_RL_renameStage_doRenaming && _dfoo16 ; assign coreFix_aluExe_1_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_1_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ; @@ -13939,8 +14867,6 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && coreFix_aluExe_1_rsAlu$dispatchData[41] ; assign coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put = - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && @@ -13950,24 +14876,26 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ; + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] || + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ; assign coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put = _dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put && - coreFix_memExe_lsq$issueLd[74:73] != 2'd0 && - coreFix_memExe_lsq$issueLd[74:73] != 2'd1 && - coreFix_memExe_lsq$issueLd[72] ; + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137] ; assign coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put = (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) && - coreFix_memExe_lsq$firstSt[150] || + coreFix_memExe_lsq$firstSt[232] || (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) && - coreFix_memExe_lsq$firstLd[89] || + coreFix_memExe_lsq$firstLd[106] || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5594 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0 && coreFix_memExe_lsq$getHit[8] && !coreFix_memExe_lsq$getHit[9] ; @@ -13980,10 +14908,10 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_dispToRegQ assign coreFix_fpuMulDivExe_0_dispToRegQ$enq_x = - { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279, + { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q362, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ; assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -14020,24 +14948,24 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_fpuExec_divQ assign coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x = - { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695, + { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850, coreFix_fpuMulDivExe_0_regToExeQ$first[225], !coreFix_fpuMulDivExe_0_regToExeQ$first[225] && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10832, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14987, !coreFix_fpuMulDivExe_0_regToExeQ$first[225] && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10868, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15023, !coreFix_fpuMulDivExe_0_regToExeQ$first[225] && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10916, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15071, !coreFix_fpuMulDivExe_0_regToExeQ$first[225] && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10958, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15113, !coreFix_fpuMulDivExe_0_regToExeQ$first[225] && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d11000, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15155, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -14062,7 +14990,7 @@ module mkCore(CLK, end assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 && + coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd4 && coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ; assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned || @@ -14077,12 +15005,12 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_fpuExec_double_div assign coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put = - { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9166, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10634, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695 } ; + { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13307, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14787, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 } ; assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 && + coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd4 && coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ; assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned || @@ -14091,13 +15019,13 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put = { coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9929, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q280, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695 } ; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14077, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q363, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q364, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 } ; assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 && + coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd4 && (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 || @@ -14111,11 +15039,11 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put = - { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9166, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695 } ; + { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13307, + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 } ; assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 && + coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd4 && coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ; assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned || @@ -14125,7 +15053,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x = coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ; assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -14150,7 +15078,7 @@ module mkCore(CLK, end assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 && + coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd4 && (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 || @@ -14171,11 +15099,11 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x = - { execFpuSimple___d11034, + { execFpuSimple___d15189, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -14200,7 +15128,7 @@ module mkCore(CLK, end assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 && + coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd4 && coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2 && @@ -14211,7 +15139,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd4 ; assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ; + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ; assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -14224,7 +15152,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x = coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ; assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -14249,7 +15177,7 @@ module mkCore(CLK, end assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 && + coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd4 && coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ; assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned || @@ -14268,7 +15196,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -14293,7 +15221,7 @@ module mkCore(CLK, end assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq = @@ -14310,27 +15238,27 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h600259 : - a__h599837 ; + _theResult___fst__h836055 : + a__h835633 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h599838 == 64'd0, - a__h599837, + { b__h835634 == 64'd0, + a__h835633, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h600273, - a__h599837[63], + x__h836069, + a__h835633[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h600260 : - b__h599838 ; + _theResult___snd__h836056 : + b__h835634 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tready = @@ -14343,7 +15271,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -14368,7 +15296,7 @@ module mkCore(CLK, end assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd3 && (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 || coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq = @@ -14383,20 +15311,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h599837 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h599838 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h835633 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h835634 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h599837 ; + a__h835633 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h599838 ; + b__h835634 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h599837 ; + a__h835633 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h599838 ; + b__h835634 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -14423,14 +15351,14 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_regToExeQ assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = - { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283, + { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q366, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h478868, - x__h478869, - x__h478870, + x__h714355, + x__h714356, + x__h714357, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -14456,7 +15384,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$EN_enq = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ; assign coreFix_fpuMulDivExe_0_regToExeQ$EN_deq = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -14468,19 +15396,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13849) ? - { IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21790) ? + { IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20171, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, - fetchStage$pipelines_0_first[194:192] == 3'd1, + fetchStage$pipelines_0_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : - { IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361, + { IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21119, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675346, - fetchStage$pipelines_1_first[194:192] == 3'd1, + renaming_spec_bits__h965955, + fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put = @@ -14552,7 +15480,7 @@ module mkCore(CLK, end assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -14576,11 +15504,7 @@ module mkCore(CLK, endcase end assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && - (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13849 || - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13928 && - regRenamingTable_rename_1_canRename__3307_AND__ETC___d13981) ; + WILL_FIRE_RL_renameStage_doRenaming && _dfoo14 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ; @@ -14591,8 +15515,6 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && coreFix_aluExe_1_rsAlu$dispatchData[41] ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put = - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && @@ -14602,24 +15524,26 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ; + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] || + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put = _dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put && - coreFix_memExe_lsq$issueLd[74:73] != 2'd0 && - coreFix_memExe_lsq$issueLd[74:73] != 2'd1 && - coreFix_memExe_lsq$issueLd[72] ; + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137] ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put = (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) && - coreFix_memExe_lsq$firstSt[150] || + coreFix_memExe_lsq$firstSt[232] || (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) && - coreFix_memExe_lsq$firstLd[89] || + coreFix_memExe_lsq$firstLd[106] || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5594 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0 && coreFix_memExe_lsq$getHit[8] && !coreFix_memExe_lsq$getHit[9] ; @@ -14633,31 +15557,17 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h284499, - x__h284511, - IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, - IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2806, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824, - x__h286365, - IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840, - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 } ; + coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? + coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget : + coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h283066 ; + x__h501025 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[583:582] == 2'd0) ? - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] : - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] : + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] ? + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[518:516] : 3'd0) ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n = 3'h0 ; @@ -14674,29 +15584,29 @@ module mkCore(CLK, case (1'b1) // synopsys parallel_case MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1: coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574]; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579]; MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2: coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512]; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[518:516]; WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo: coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n = - coreFix_memExe_dMem_cache_m_banks_0_processAmo[159:157]; + coreFix_memExe_dMem_cache_m_banks_0_processAmo[233:231]; default: coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n = 3'b010 /* unspecified value */ ; endcase end assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr = - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:84] ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[221:158] ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d = - { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] == + { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520] == 2'd3, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:0] } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n = MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ? - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[518:516] ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot = MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ? MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 : @@ -14724,175 +15634,57 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n = coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot = - { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[57:55], - 55'h15555555555555 } ; + { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[58:56], + 56'h15555555555555 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2595 || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5571 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != 3'd4 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData = MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot = - MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 || + WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5506 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ; + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575] && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6940 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6943 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState == 3'd1) ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get = 1'b0 ; - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN = - 1'd1 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN = - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2 - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN = - 1'd1 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2 - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN = - 1'd1 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN = - 1'd1 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2 - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN = - 1'd1 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN = - EN_dCacheToParent_fromP_enq ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2 - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN = - 1'd1 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN = - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2578 || - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd2 || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd3) || - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq && - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2723 && - coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] == - 2'd0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN = - MUX_flush_reservation$write_1__SEL_1 ; - // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q284 } ; + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7038, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q367 } ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[580:579] ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n = 2'h0 ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[580:579] ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d = - { !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] == + { !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520] == 2'd3, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:0] } ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[580:579] ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n = coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n = @@ -14905,9 +15697,9 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq && - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] || - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696) ; + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575] || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6943) ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData = MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get = 1'b0 ; @@ -14981,7 +15773,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam = MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4; default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam = - 570'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + 575'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end always@(WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry or @@ -15007,7 +15799,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r = MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4; default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r = - 584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + 588'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send = @@ -15018,84 +15810,12 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite = MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != 3'd4 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ; - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN = - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN = - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2 - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN = - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2 - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN = - 1'b0 ; - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ? @@ -15110,16 +15830,10 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2647 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != - 3'd1) && - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2651) ; + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5630 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR = @@ -15135,54 +15849,6 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR = 1'b0 ; - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN = - 1'd1 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN = - EN_dCacheToParent_rqToP_deq ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2 - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN = - 1'd1 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN = - CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2 - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN = - 1'd1 ; - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN = MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ? @@ -15190,114 +15856,26 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575] && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6940 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6943 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2662 ; + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6761 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR = 1'b0 ; - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN = - 1'd1 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN = - EN_dCacheToParent_rsToP_deq ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2 - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN = - 1'd1 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0 - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN = - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq || - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1 - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN = - 1'b0 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN = - 1'b0 ; - - // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2 - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN = - 1'd1 ; - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN = - 1'd1 ; - - // submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0 - assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1 - assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0 - assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN = 1'b0 ; - assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN = 1'b0 ; - - // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1 - assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2 - assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0 - assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN = 1'b0 ; - assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN = 1'b0 ; - - // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1 - assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2 - assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN = 1'd1 ; - // submodule coreFix_memExe_dTlb assign coreFix_memExe_dTlb$perf_req_r = 3'h0 ; assign coreFix_memExe_dTlb$perf_setStatus_doStats = 1'b0 ; assign coreFix_memExe_dTlb$procReq_req = - { coreFix_memExe_regToExeQ$first[192:190], - coreFix_memExe_regToExeQ$first[157:140], - coreFix_memExe_lsq$getOrigBE << vaddr__h180509[2:0], - vaddr__h180509, - coreFix_memExe_lsq$getOrigBE[7] ? - vaddr__h180509[2:0] != 3'd0 : - (coreFix_memExe_lsq$getOrigBE[3] ? - vaddr__h180509[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && vaddr__h180509[0]), + { coreFix_memExe_regToExeQ$first[436:434], + coreFix_memExe_regToExeQ$first[401:384], + coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4232, coreFix_memExe_regToExeQ$first[11:0] } ; assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15324,14 +15902,15 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h707184, - prv__h707184 != 2'd3 && csrf_vm_mode_sv39_reg, - csrf_mxr_reg, - csrf_sum_reg, - csrf_ppn_reg } ; - assign coreFix_memExe_dTlb$EN_flush = MUX_flush_tlbs$write_1__SEL_1 ; + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 : + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ; + assign coreFix_memExe_dTlb$EN_flush = + WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || + WILL_FIRE_RL_rl_debug_resume ; assign coreFix_memExe_dTlb$EN_updateVMInfo = - MUX_update_vm_info$write_1__SEL_1 ; + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_rl_debug_resume ; assign coreFix_memExe_dTlb$EN_procReq = CAN_FIRE_RL_coreFix_memExe_doExeMem ; assign coreFix_memExe_dTlb$EN_deqProcResp = @@ -15355,12 +15934,12 @@ module mkCore(CLK, // submodule coreFix_memExe_dispToRegQ assign coreFix_memExe_dispToRegQ$enq_x = - { coreFix_memExe_rsMem$dispatchData[106:72], + { coreFix_memExe_rsMem$dispatchData[153:119], coreFix_memExe_rsMem$dispatchData[65:21], - coreFix_memExe_rsMem$dispatchData[71:66], + coreFix_memExe_rsMem$dispatchData[118:66], coreFix_memExe_rsMem$dispatchData[20:9] } ; assign coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15394,119 +15973,83 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ; - // submodule coreFix_memExe_forwardQ_clearReq_dummy2_0 - assign coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign coreFix_memExe_forwardQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule coreFix_memExe_forwardQ_clearReq_dummy2_1 - assign coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign coreFix_memExe_forwardQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule coreFix_memExe_forwardQ_deqReq_dummy2_0 - assign coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_forwardQ_deqReq_dummy2_0$EN = - WILL_FIRE_RL_coreFix_memExe_doRespLdForward ; - - // submodule coreFix_memExe_forwardQ_deqReq_dummy2_1 - assign coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_forwardQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_forwardQ_deqReq_dummy2_2 - assign coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign coreFix_memExe_forwardQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule coreFix_memExe_forwardQ_enqReq_dummy2_0 - assign coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_forwardQ_enqReq_dummy2_0$EN = - _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write && - coreFix_memExe_lsq$issueLd[74:73] != 2'd0 && - coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ; - - // submodule coreFix_memExe_forwardQ_enqReq_dummy2_1 - assign coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_forwardQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_forwardQ_enqReq_dummy2_2 - assign coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign coreFix_memExe_forwardQ_enqReq_dummy2_2$EN = 1'd1 ; - // submodule coreFix_memExe_lsq assign coreFix_memExe_lsq$enqLd_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13875) ? + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21821) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqLd_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13875) ? + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21821) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqLd_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13875) ? - fetchStage$pipelines_0_first[191:174] : - fetchStage$pipelines_1_first[191:174] ; + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21821) ? + fetchStage$pipelines_0_first[264:238] : + fetchStage$pipelines_1_first[264:238] ; assign coreFix_memExe_lsq$enqLd_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13875) ? + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21821) ? specTagManager$currentSpecBits : - renaming_spec_bits__h675346 ; + renaming_spec_bits__h965955 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883) ? + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21830) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqSt_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883) ? + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21830) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqSt_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883) ? - fetchStage$pipelines_0_first[191:174] : - fetchStage$pipelines_1_first[191:174] ; + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21830) ? + fetchStage$pipelines_0_first[264:238] : + fetchStage$pipelines_1_first[264:238] ; assign coreFix_memExe_lsq$enqSt_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883) ? + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21830) ? specTagManager$currentSpecBits : - renaming_spec_bits__h675346 ; + renaming_spec_bits__h965955 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : MUX_coreFix_memExe_lsq$getHit_1__VAL_1 ; assign coreFix_memExe_lsq$getOrigBE_t = - coreFix_memExe_regToExeQ$first[145:140] ; + coreFix_memExe_regToExeQ$first[389:384] ; assign coreFix_memExe_lsq$issueLd_lsqTag = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ? - coreFix_memExe_lsq$getIssueLd[76:72] : - coreFix_memExe_issueLd$wget[76:72] ; + coreFix_memExe_lsq$getIssueLd[84:80] : + coreFix_memExe_issueLd$wget[84:80] ; assign coreFix_memExe_lsq$issueLd_paddr = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ? - coreFix_memExe_lsq$getIssueLd[71:8] : - coreFix_memExe_issueLd$wget[71:8] ; + coreFix_memExe_lsq$getIssueLd[79:16] : + coreFix_memExe_issueLd$wget[79:16] ; assign coreFix_memExe_lsq$issueLd_sbRes = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ? MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 : coreFix_memExe_stb$search ; assign coreFix_memExe_lsq$issueLd_shiftedBE = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ? - coreFix_memExe_lsq$getIssueLd[7:0] : - coreFix_memExe_issueLd$wget[7:0] ; + coreFix_memExe_lsq$getIssueLd[15:0] : + coreFix_memExe_issueLd$wget[15:0] ; assign coreFix_memExe_lsq$respLd_alignedData = WILL_FIRE_RL_coreFix_memExe_doRespLdMem ? MUX_coreFix_memExe_lsq$respLd_2__VAL_1 : MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ; assign coreFix_memExe_lsq$respLd_t = WILL_FIRE_RL_coreFix_memExe_doRespLdMem ? - MUX_coreFix_memExe_lsq$respLd_1__VAL_1 : - MUX_coreFix_memExe_lsq$respLd_1__VAL_2 ; + t__h212809 : + t__h215095 ; assign coreFix_memExe_lsq$setAtCommit_0_put = rob$deqPort_0_deq_data[24:19] ; assign coreFix_memExe_lsq$setAtCommit_1_put = rob$deqPort_1_deq_data[24:19] ; assign coreFix_memExe_lsq$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15530,31 +16073,52 @@ module mkCore(CLK, endcase end assign coreFix_memExe_lsq$updateAddr_fault = - { (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] == 3'd2 || - coreFix_memExe_dTlb$procResp[105:103] == 3'd3 || - coreFix_memExe_dTlb$procResp[12] : - coreFix_memExe_dTlb$procResp[12] || - coreFix_memExe_dTlb$procResp[110], - IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1857 } ; + { IF_coreFix_memExe_dTlb_procResp__239_BIT_277_5_ETC___d4576, + IF_IF_coreFix_memExe_dTlb_procResp__239_BIT_27_ETC___d4739 } ; assign coreFix_memExe_lsq$updateAddr_isMMIO = - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731 ; + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548 ; assign coreFix_memExe_lsq$updateAddr_lsqTag = - coreFix_memExe_dTlb$procResp[90:85] ; + coreFix_memExe_dTlb$procResp[475:470] ; assign coreFix_memExe_lsq$updateAddr_paddr = - coreFix_memExe_dTlb$procResp[174:111] ; + coreFix_memExe_dTlb$procResp[560:497] ; assign coreFix_memExe_lsq$updateAddr_shiftedBE = - coreFix_memExe_dTlb$procResp[84:77] ; + coreFix_memExe_dTlb$procResp[469:454] ; assign coreFix_memExe_lsq$updateData_d = - (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? - coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h180514 ; + (coreFix_memExe_regToExeQ$first[436:434] == 3'd4) ? + { coreFix_memExe_regToExeQ$first[220], + coreFix_memExe_regToExeQ$first[139:124], + coreFix_memExe_regToExeQ$first[122:121], + coreFix_memExe_regToExeQ$first[123], + ~coreFix_memExe_regToExeQ$first[120:102], + IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[25:17], + ~IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[16:15], + IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[14:3], + ~IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[2], + IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[1:0], + coreFix_memExe_regToExeQ$first[217:154] } : + { pointer__h242569[3:0] == 4'd0 && + coreFix_memExe_lsq$getOrigBE[0] && + coreFix_memExe_lsq$getOrigBE[1] && + coreFix_memExe_lsq$getOrigBE[2] && + coreFix_memExe_lsq$getOrigBE[3] && + coreFix_memExe_lsq$getOrigBE[4] && + coreFix_memExe_lsq$getOrigBE[5] && + coreFix_memExe_lsq$getOrigBE[6] && + coreFix_memExe_lsq$getOrigBE[7] && + coreFix_memExe_lsq$getOrigBE[8] && + coreFix_memExe_lsq$getOrigBE[9] && + coreFix_memExe_lsq$getOrigBE[10] && + coreFix_memExe_lsq$getOrigBE[11] && + coreFix_memExe_lsq$getOrigBE[12] && + coreFix_memExe_lsq$getOrigBE[13] && + coreFix_memExe_lsq$getOrigBE[14] && + coreFix_memExe_lsq$getOrigBE[15] && + coreFix_memExe_regToExeQ$first[220], + coreFix_memExe_regToExeQ_first__633_BITS_139_T_ETC___d4052 } ; assign coreFix_memExe_lsq$updateData_t = - coreFix_memExe_regToExeQ$first[143:140] ; + coreFix_memExe_regToExeQ$first[387:384] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[223:222] ; assign coreFix_memExe_lsq$EN_enqLd = WILL_FIRE_RL_renameStage_doRenaming && _dfoo7 ; assign coreFix_memExe_lsq$EN_enqSt = @@ -15562,12 +16126,12 @@ module mkCore(CLK, assign coreFix_memExe_lsq$EN_getHit = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0 ; assign coreFix_memExe_lsq$EN_updateData = WILL_FIRE_RL_coreFix_memExe_doExeMem && - coreFix_memExe_regToExeQ$first[145] ; + coreFix_memExe_regToExeQ$first[389] ; assign coreFix_memExe_lsq$EN_updateAddr = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; assign coreFix_memExe_lsq$EN_issueLd = @@ -15594,8 +16158,8 @@ module mkCore(CLK, assign coreFix_memExe_lsq$EN_wakeupLdStalledBySB = MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd1 ; assign coreFix_memExe_lsq$EN_setAtCommit_0_put = CAN_FIRE_RL_commitStage_doSetLSQAtCommit ; @@ -15608,53 +16172,45 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign coreFix_memExe_lsq$EN_specUpdate_correctSpeculation = 1'd1 ; - // submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0 - assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1 - assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0 - assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN = - WILL_FIRE_RL_coreFix_memExe_doRespLdMem ; - - // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1 - assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2 - assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0 - assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN = - MUX_coreFix_memExe_lsq$getHit_1__SEL_1 || - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd0 ; - - // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1 - assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2 - assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN = 1'd1 ; - // submodule coreFix_memExe_regToExeQ assign coreFix_memExe_regToExeQ$enq_x = - { coreFix_memExe_dispToRegQ$first[97:63], - coreFix_memExe_dispToRegQ$first[29:12], - x__h180423, - x__h180424, + { coreFix_memExe_dispToRegQ$first[144:110], + coreFix_memExe_dispToRegQ$first[76:59], + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3023, + IF_coreFix_memExe_dispToRegQ_first__680_BIT_12_ETC___d3303, + coreFix_memExe_dispToRegQ$first[12] ? + 3'd7 : + ((coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3315 : + 3'd7), + coreFix_memExe_dispToRegQ$first[12] || + !coreFix_memExe_dispToRegQ$first[109] || + coreFix_memExe_dispToRegQ$first[108:102] == 7'd0 || + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3329, + coreFix_memExe_dispToRegQ$first[12] || + !coreFix_memExe_dispToRegQ$first[109] || + coreFix_memExe_dispToRegQ$first[108:102] == 7'd0 || + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3342, + coreFix_memExe_dispToRegQ$first[12] || + !coreFix_memExe_dispToRegQ$first[109] || + coreFix_memExe_dispToRegQ$first[108:102] == 7'd0 || + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3356, + coreFix_memExe_dispToRegQ$first[12] ? + 4'd0 : + ((coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3378 : + 4'd0), + coreFix_memExe_dispToRegQ_first__680_BIT_101_6_ETC___d3569, + IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3623, + coreFix_memExe_dispToRegQ$first[58:13], coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15688,235 +16244,30 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ; - // submodule coreFix_memExe_reqLdQ_data_0_dummy2_0 - assign coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqLdQ_data_0_dummy2_0$EN = - _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write && - coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ; - - // submodule coreFix_memExe_reqLdQ_data_0_dummy2_1 - assign coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_reqLdQ_data_0_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_reqLdQ_deqP_dummy2_0 - assign coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqLdQ_deqP_dummy2_0$EN = - WILL_FIRE_RL_coreFix_memExe_sendLdToMem ; - - // submodule coreFix_memExe_reqLdQ_deqP_dummy2_1 - assign coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_reqLdQ_deqP_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_reqLdQ_empty_dummy2_0 - assign coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqLdQ_empty_dummy2_0$EN = - _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write && - coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ; - - // submodule coreFix_memExe_reqLdQ_empty_dummy2_1 - assign coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN = 1'd1 ; - assign coreFix_memExe_reqLdQ_empty_dummy2_1$EN = - WILL_FIRE_RL_coreFix_memExe_sendLdToMem ; - - // submodule coreFix_memExe_reqLdQ_empty_dummy2_2 - assign coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN = 1'b0 ; - assign coreFix_memExe_reqLdQ_empty_dummy2_2$EN = 1'b0 ; - - // submodule coreFix_memExe_reqLdQ_enqP_dummy2_0 - assign coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqLdQ_enqP_dummy2_0$EN = - _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write && - coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ; - - // submodule coreFix_memExe_reqLdQ_enqP_dummy2_1 - assign coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_reqLdQ_enqP_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_reqLdQ_full_dummy2_0 - assign coreFix_memExe_reqLdQ_full_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqLdQ_full_dummy2_0$EN = - _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write && - coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ; - - // submodule coreFix_memExe_reqLdQ_full_dummy2_1 - assign coreFix_memExe_reqLdQ_full_dummy2_1$D_IN = 1'd1 ; - assign coreFix_memExe_reqLdQ_full_dummy2_1$EN = - WILL_FIRE_RL_coreFix_memExe_sendLdToMem ; - - // submodule coreFix_memExe_reqLdQ_full_dummy2_2 - assign coreFix_memExe_reqLdQ_full_dummy2_2$D_IN = 1'b0 ; - assign coreFix_memExe_reqLdQ_full_dummy2_2$EN = 1'b0 ; - - // submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0 - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN = - coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ; - - // submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1 - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0 - assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN = - CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ; - - // submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1 - assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0 - assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN = - coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ; - - // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1 - assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN = 1'd1 ; - assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN = - CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ; - - // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2 - assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN = 1'b0 ; - assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN = 1'b0 ; - - // submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0 - assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN = - coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ; - - // submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1 - assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0 - assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN = - coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ; - - // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1 - assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN = 1'd1 ; - assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN = - CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ; - - // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2 - assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN = 1'b0 ; - assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN = 1'b0 ; - - // submodule coreFix_memExe_reqStQ_data_0_dummy2_0 - assign coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqStQ_data_0_dummy2_0$EN = - CAN_FIRE_RL_coreFix_memExe_doIssueSB ; - - // submodule coreFix_memExe_reqStQ_data_0_dummy2_1 - assign coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_reqStQ_data_0_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_reqStQ_deqP_dummy2_0 - assign coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqStQ_deqP_dummy2_0$EN = - WILL_FIRE_RL_coreFix_memExe_sendStToMem ; - - // submodule coreFix_memExe_reqStQ_deqP_dummy2_1 - assign coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_reqStQ_deqP_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_reqStQ_empty_dummy2_0 - assign coreFix_memExe_reqStQ_empty_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqStQ_empty_dummy2_0$EN = - CAN_FIRE_RL_coreFix_memExe_doIssueSB ; - - // submodule coreFix_memExe_reqStQ_empty_dummy2_1 - assign coreFix_memExe_reqStQ_empty_dummy2_1$D_IN = 1'd1 ; - assign coreFix_memExe_reqStQ_empty_dummy2_1$EN = - WILL_FIRE_RL_coreFix_memExe_sendStToMem ; - - // submodule coreFix_memExe_reqStQ_empty_dummy2_2 - assign coreFix_memExe_reqStQ_empty_dummy2_2$D_IN = 1'b0 ; - assign coreFix_memExe_reqStQ_empty_dummy2_2$EN = 1'b0 ; - - // submodule coreFix_memExe_reqStQ_enqP_dummy2_0 - assign coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqStQ_enqP_dummy2_0$EN = - CAN_FIRE_RL_coreFix_memExe_doIssueSB ; - - // submodule coreFix_memExe_reqStQ_enqP_dummy2_1 - assign coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_reqStQ_enqP_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_reqStQ_full_dummy2_0 - assign coreFix_memExe_reqStQ_full_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_reqStQ_full_dummy2_0$EN = - CAN_FIRE_RL_coreFix_memExe_doIssueSB ; - - // submodule coreFix_memExe_reqStQ_full_dummy2_1 - assign coreFix_memExe_reqStQ_full_dummy2_1$D_IN = 1'd1 ; - assign coreFix_memExe_reqStQ_full_dummy2_1$EN = - WILL_FIRE_RL_coreFix_memExe_sendStToMem ; - - // submodule coreFix_memExe_reqStQ_full_dummy2_2 - assign coreFix_memExe_reqStQ_full_dummy2_2$D_IN = 1'b0 ; - assign coreFix_memExe_reqStQ_full_dummy2_2$EN = 1'b0 ; - - // submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0 - assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1 - assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0 - assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN = - coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ; - - // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1 - assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2 - assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0 - assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN = - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2561 || - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd2 || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd3) || - WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ; - - // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1 - assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2 - assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN = 1'd1 ; - // submodule coreFix_memExe_rsMem assign coreFix_memExe_rsMem$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13855) ? - { fetchStage$pipelines_0_first[191:189], - IF_fetchStage_pipelines_0_first__2605_BIT_160__ETC___d13871, + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21797) ? + { fetchStage$pipelines_0_first[264:262], + fetchStage$pipelines_0_first[160:129], + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21813, + fetchStage$pipelines_0_first[226:181], + !fetchStage$pipelines_0_first[238], regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, - fetchStage$pipelines_0_first[194:192] == 3'd1, + fetchStage$pipelines_0_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : - { fetchStage$pipelines_1_first[191:189], - IF_fetchStage_pipelines_1_first__2614_BIT_160__ETC___d13998, + { fetchStage$pipelines_1_first[264:262], + fetchStage$pipelines_1_first[160:129], + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21957, + fetchStage$pipelines_1_first[226:181], + !fetchStage$pipelines_1_first[238], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675346, - fetchStage$pipelines_1_first[194:192] == 3'd1, + renaming_spec_bits__h965955, + fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; assign coreFix_memExe_rsMem$setRegReady_0_put = @@ -15988,7 +16339,7 @@ module mkCore(CLK, end assign coreFix_memExe_rsMem$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -16023,8 +16374,6 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && coreFix_aluExe_1_rsAlu$dispatchData[41] ; assign coreFix_memExe_rsMem$EN_setRegReady_2_put = - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && @@ -16034,24 +16383,26 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ; + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] || + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ; assign coreFix_memExe_rsMem$EN_setRegReady_3_put = _dor1coreFix_memExe_rsMem$EN_setRegReady_3_put && - coreFix_memExe_lsq$issueLd[74:73] != 2'd0 && - coreFix_memExe_lsq$issueLd[74:73] != 2'd1 && - coreFix_memExe_lsq$issueLd[72] ; + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137] ; assign coreFix_memExe_rsMem$EN_setRegReady_4_put = (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) && - coreFix_memExe_lsq$firstSt[150] || + coreFix_memExe_lsq$firstSt[232] || (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) && - coreFix_memExe_lsq$firstLd[89] || + coreFix_memExe_lsq$firstLd[106] || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5594 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0 && coreFix_memExe_lsq$getHit[8] && !coreFix_memExe_lsq$getHit[9] ; @@ -16064,35 +16415,36 @@ module mkCore(CLK, // submodule coreFix_memExe_stb assign coreFix_memExe_stb$deq_idx = - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ; - assign coreFix_memExe_stb$enq_be = coreFix_memExe_lsq$firstSt[76:69] ; - assign coreFix_memExe_stb$enq_data = coreFix_memExe_lsq$firstSt[68:5] ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[223:222] ; + assign coreFix_memExe_stb$enq_be = coreFix_memExe_lsq$firstSt[158:143] ; + assign coreFix_memExe_stb$enq_data = coreFix_memExe_lsq$firstSt[142:14] ; assign coreFix_memExe_stb$enq_idx = coreFix_memExe_stb$getEnqIndex[1:0] ; - assign coreFix_memExe_stb$enq_paddr = coreFix_memExe_lsq$firstSt[141:78] ; + assign coreFix_memExe_stb$enq_paddr = coreFix_memExe_lsq$firstSt[223:160] ; assign coreFix_memExe_stb$getEnqIndex_paddr = - coreFix_memExe_lsq$firstSt[141:78] ; - assign coreFix_memExe_stb$noMatchLdQ_be = coreFix_memExe_lsq$firstLd[15:8] ; + coreFix_memExe_lsq$firstSt[223:160] ; + assign coreFix_memExe_stb$noMatchLdQ_be = + coreFix_memExe_lsq$firstLd[32:17] ; assign coreFix_memExe_stb$noMatchLdQ_paddr = - coreFix_memExe_lsq$firstLd[80:17] ; + coreFix_memExe_lsq$firstLd[97:34] ; assign coreFix_memExe_stb$noMatchStQ_be = - coreFix_memExe_lsq$firstSt[76:69] ; + coreFix_memExe_lsq$firstSt[158:143] ; assign coreFix_memExe_stb$noMatchStQ_paddr = - coreFix_memExe_lsq$firstSt[141:78] ; + coreFix_memExe_lsq$firstSt[223:160] ; assign coreFix_memExe_stb$search_be = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ? - coreFix_memExe_lsq$getIssueLd[7:0] : - coreFix_memExe_issueLd$wget[7:0] ; + coreFix_memExe_lsq$getIssueLd[15:0] : + coreFix_memExe_issueLd$wget[15:0] ; assign coreFix_memExe_stb$search_paddr = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ? - coreFix_memExe_lsq$getIssueLd[71:8] : - coreFix_memExe_issueLd$wget[71:8] ; + coreFix_memExe_lsq$getIssueLd[79:16] : + coreFix_memExe_issueLd$wget[79:16] ; assign coreFix_memExe_stb$EN_enq = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ; assign coreFix_memExe_stb$EN_deq = MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd1 ; assign coreFix_memExe_stb$EN_issue = CAN_FIRE_RL_coreFix_memExe_doIssueSB ; @@ -16103,8 +16455,10 @@ module mkCore(CLK, MUX_coreFix_trainBPQ_0$enq_1__VAL_2 ; assign coreFix_trainBPQ_0$ENQ = WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && - (coreFix_aluExe_0_exeToFinQ$first[325:321] == 5'd9 || - coreFix_aluExe_0_exeToFinQ$first[325:321] == 5'd10) || + (coreFix_aluExe_0_exeToFinQ$first[1066:1062] == 5'd9 || + coreFix_aluExe_0_exeToFinQ$first[1066:1062] == 5'd12 || + coreFix_aluExe_0_exeToFinQ$first[1066:1062] == 5'd11 || + coreFix_aluExe_0_exeToFinQ$first[1066:1062] == 5'd10) || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; assign coreFix_trainBPQ_0$DEQ = WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ; assign coreFix_trainBPQ_0$CLR = 1'b0 ; @@ -16116,80 +16470,56 @@ module mkCore(CLK, MUX_coreFix_trainBPQ_1$enq_1__VAL_2 ; assign coreFix_trainBPQ_1$ENQ = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && - (coreFix_aluExe_1_exeToFinQ$first[325:321] == 5'd9 || - coreFix_aluExe_1_exeToFinQ$first[325:321] == 5'd10) || + (coreFix_aluExe_1_exeToFinQ$first[1066:1062] == 5'd9 || + coreFix_aluExe_1_exeToFinQ$first[1066:1062] == 5'd12 || + coreFix_aluExe_1_exeToFinQ$first[1066:1062] == 5'd11 || + coreFix_aluExe_1_exeToFinQ$first[1066:1062] == 5'd10) || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; assign coreFix_trainBPQ_1$DEQ = coreFix_trainBPQ_1$EMPTY_N ; assign coreFix_trainBPQ_1$CLR = 1'b0 ; - // submodule csrInstOrInterruptInflight_dummy2_0 - assign csrInstOrInterruptInflight_dummy2_0$D_IN = 1'd1 ; - assign csrInstOrInterruptInflight_dummy2_0$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap[4] ; - - // submodule csrInstOrInterruptInflight_dummy2_1 - assign csrInstOrInterruptInflight_dummy2_1$D_IN = 1'd1 ; - assign csrInstOrInterruptInflight_dummy2_1$EN = - WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[199:195] == 5'd13 || - MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2 ; - - // submodule csrf_mcycle_ehr_data_dummy2_0 - assign csrf_mcycle_ehr_data_dummy2_0$D_IN = 1'd1 ; - assign csrf_mcycle_ehr_data_dummy2_0$EN = csrf_mcycle_ehr_data_lat_0$whas ; - - // submodule csrf_mcycle_ehr_data_dummy2_1 - assign csrf_mcycle_ehr_data_dummy2_1$D_IN = 1'd1 ; - assign csrf_mcycle_ehr_data_dummy2_1$EN = 1'd1 ; - - // submodule csrf_minstret_ehr_data_dummy2_0 - assign csrf_minstret_ehr_data_dummy2_0$D_IN = 1'd1 ; - assign csrf_minstret_ehr_data_dummy2_0$EN = - csrf_minstret_ehr_data_lat_0$whas ; - - // submodule csrf_minstret_ehr_data_dummy2_1 - assign csrf_minstret_ehr_data_dummy2_1$D_IN = 1'd1 ; - assign csrf_minstret_ehr_data_dummy2_1$EN = - csrf_minstret_ehr_data_dummy_1_0$whas ; - // submodule csrf_stats_module_writeQ - assign csrf_stats_module_writeQ$D_IN = csrf_sscratch_csr$D_IN[0] ; + assign csrf_stats_module_writeQ$D_IN = + MUX_csrf_stats_module_writeQ$enq_1__SEL_1 ? + f_csr_reqs$D_OUT[0] : + MUX_csrf_stval_csr$write_1__VAL_1[0] ; assign csrf_stats_module_writeQ$ENQ = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd2049 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; // submodule csrf_terminate_module_terminateQ assign csrf_terminate_module_terminateQ$ENQ = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd2048 || WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; // submodule epochManager assign epochManager$checkEpoch_0_check_e = - fetchStage$pipelines_0_first[259:256] ; + fetchStage$pipelines_0_first[332:329] ; assign epochManager$checkEpoch_1_check_e = - fetchStage$pipelines_1_first[259:256] ; + fetchStage$pipelines_1_first[332:329] ; assign epochManager$updatePrevEpoch_0_update_e = - fetchStage$pipelines_0_first[259:256] ; + fetchStage$pipelines_0_first[332:329] ; assign epochManager$updatePrevEpoch_1_update_e = - fetchStage$pipelines_1_first[259:256] ; + fetchStage$pipelines_1_first[332:329] ; assign epochManager$EN_updatePrevEpoch_0_update = WILL_FIRE_RL_renameStage_doRenaming_wrongPath && fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13834 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 || + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21775 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21020 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign epochManager$EN_updatePrevEpoch_1_update = @@ -16197,9 +16527,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13928 && - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13938 && - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13650 ; + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21880 && + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21891 && + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21580 ; assign epochManager$EN_incrementEpoch = WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || @@ -16209,6 +16539,122 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; + // submodule f_csr_reqs + assign f_csr_reqs$D_IN = hart0_csr_mem_server_request_put ; + assign f_csr_reqs$ENQ = EN_hart0_csr_mem_server_request_put ; + assign f_csr_reqs$DEQ = + WILL_FIRE_RL_rl_debug_csr_access_busy || + WILL_FIRE_RL_rl_debug_csr_write || + WILL_FIRE_RL_rl_debug_csr_read ; + assign f_csr_reqs$CLR = 1'b0 ; + + // submodule f_csr_rsps + always@(WILL_FIRE_RL_rl_debug_csr_access_busy or + WILL_FIRE_RL_rl_debug_csr_write or + WILL_FIRE_RL_rl_debug_csr_read or MUX_f_csr_rsps$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_rl_debug_csr_access_busy: + f_csr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA; + WILL_FIRE_RL_rl_debug_csr_write: + f_csr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA; + WILL_FIRE_RL_rl_debug_csr_read: + f_csr_rsps$D_IN = MUX_f_csr_rsps$enq_1__VAL_3; + default: f_csr_rsps$D_IN = + 65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign f_csr_rsps$ENQ = + WILL_FIRE_RL_rl_debug_csr_access_busy || + WILL_FIRE_RL_rl_debug_csr_write || + WILL_FIRE_RL_rl_debug_csr_read ; + assign f_csr_rsps$DEQ = EN_hart0_csr_mem_server_response_get ; + assign f_csr_rsps$CLR = 1'b0 ; + + // submodule f_fpr_reqs + assign f_fpr_reqs$D_IN = hart0_fpr_mem_server_request_put ; + assign f_fpr_reqs$ENQ = EN_hart0_fpr_mem_server_request_put ; + assign f_fpr_reqs$DEQ = + WILL_FIRE_RL_rl_debug_fpr_access_busy || + WILL_FIRE_RL_rl_debug_fpr_write || + WILL_FIRE_RL_rl_debug_fpr_read ; + assign f_fpr_reqs$CLR = 1'b0 ; + + // submodule f_fpr_rsps + always@(WILL_FIRE_RL_rl_debug_fpr_access_busy or + WILL_FIRE_RL_rl_debug_fpr_write or + WILL_FIRE_RL_rl_debug_fpr_read or MUX_f_fpr_rsps$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_rl_debug_fpr_access_busy: + f_fpr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA; + WILL_FIRE_RL_rl_debug_fpr_write: + f_fpr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA; + WILL_FIRE_RL_rl_debug_fpr_read: + f_fpr_rsps$D_IN = MUX_f_fpr_rsps$enq_1__VAL_3; + default: f_fpr_rsps$D_IN = + 65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign f_fpr_rsps$ENQ = + WILL_FIRE_RL_rl_debug_fpr_access_busy || + WILL_FIRE_RL_rl_debug_fpr_write || + WILL_FIRE_RL_rl_debug_fpr_read ; + assign f_fpr_rsps$DEQ = EN_hart0_fpr_mem_server_response_get ; + assign f_fpr_rsps$CLR = 1'b0 ; + + // submodule f_gpr_reqs + assign f_gpr_reqs$D_IN = hart0_gpr_mem_server_request_put ; + assign f_gpr_reqs$ENQ = EN_hart0_gpr_mem_server_request_put ; + assign f_gpr_reqs$DEQ = + WILL_FIRE_RL_rl_debug_gpr_access_busy || + WILL_FIRE_RL_rl_debug_gpr_write || + WILL_FIRE_RL_rl_debug_gpr_read ; + assign f_gpr_reqs$CLR = 1'b0 ; + + // submodule f_gpr_rsps + always@(WILL_FIRE_RL_rl_debug_gpr_access_busy or + WILL_FIRE_RL_rl_debug_gpr_write or + WILL_FIRE_RL_rl_debug_gpr_read or MUX_f_fpr_rsps$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_rl_debug_gpr_access_busy: + f_gpr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA; + WILL_FIRE_RL_rl_debug_gpr_write: + f_gpr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA; + WILL_FIRE_RL_rl_debug_gpr_read: + f_gpr_rsps$D_IN = MUX_f_fpr_rsps$enq_1__VAL_3; + default: f_gpr_rsps$D_IN = + 65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign f_gpr_rsps$ENQ = + WILL_FIRE_RL_rl_debug_gpr_access_busy || + WILL_FIRE_RL_rl_debug_gpr_write || + WILL_FIRE_RL_rl_debug_gpr_read ; + assign f_gpr_rsps$DEQ = EN_hart0_gpr_mem_server_response_get ; + assign f_gpr_rsps$CLR = 1'b0 ; + + // submodule f_run_halt_reqs + assign f_run_halt_reqs$D_IN = hart0_run_halt_server_request_put ; + assign f_run_halt_reqs$ENQ = EN_hart0_run_halt_server_request_put ; + assign f_run_halt_reqs$DEQ = + WILL_FIRE_RL_rl_debug_run_redundant || + WILL_FIRE_RL_rl_debug_resume || + WILL_FIRE_RL_rl_debug_halt_req_already_halted || + WILL_FIRE_RL_rl_debug_halt_req ; + assign f_run_halt_reqs$CLR = 1'b0 ; + + // submodule f_run_halt_rsps + assign f_run_halt_rsps$D_IN = !MUX_f_run_halt_rsps$enq_1__SEL_1 ; + assign f_run_halt_rsps$ENQ = + WILL_FIRE_RL_rl_debug_halted || + WILL_FIRE_RL_rl_debug_halt_req_already_halted || + WILL_FIRE_RL_rl_debug_run_redundant || + WILL_FIRE_RL_rl_debug_resume ; + assign f_run_halt_rsps$DEQ = EN_hart0_run_halt_server_response_get ; + assign f_run_halt_rsps$CLR = 1'b0 ; + // submodule fetchStage assign fetchStage$iMemIfc_perf_req_r = 2'h0 ; assign fetchStage$iMemIfc_perf_setStatus_doStats = 1'b0 ; @@ -16221,75 +16667,81 @@ module mkCore(CLK, l2Tlb$toChildren_rsToC_first[80:0] ; assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ; assign fetchStage$iTlbIfc_updateVMInfo_vm = - { csrf_prv_reg, - csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, - csrf_mxr_reg, - csrf_sum_reg, - csrf_ppn_reg } ; + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ; assign fetchStage$mmioIfc_setHtifAddrs_fromHost = coreReq_start_fromHostAddr ; assign fetchStage$mmioIfc_setHtifAddrs_toHost = coreReq_start_toHostAddr ; assign fetchStage$perf_req_r = 2'h0 ; assign fetchStage$perf_setStatus_doStats = 1'b0 ; - always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or - coreFix_aluExe_1_exeToFinQ$first or + always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or + MUX_fetchStage$redirect_1__VAL_1 or + WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or + new_pc__h871587 or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or - coreFix_aluExe_0_exeToFinQ$first or + new_pc__h909530 or WILL_FIRE_RL_commitStage_doCommitKilledLd or rob$deqPort_0_deq_data or - WILL_FIRE_RL_commitStage_doCommitTrap_handle or - MUX_fetchStage$redirect_1__VAL_4 or WILL_FIRE_RL_commitStage_doCommitSystemInst or - MUX_fetchStage$redirect_1__VAL_5) + MUX_fetchStage$redirect_1__VAL_5 or + WILL_FIRE_RL_rl_debug_resume or MUX_fetchStage$redirect_1__VAL_6) begin case (1'b1) // synopsys parallel_case + MUX_commitStage_rg_serial_num$write_1__SEL_1: + fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: - fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19]; + fetchStage$redirect_pc = new_pc__h871587; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: - fetchStage$redirect_pc = coreFix_aluExe_0_exeToFinQ$first[82:19]; + fetchStage$redirect_pc = new_pc__h909530; WILL_FIRE_RL_commitStage_doCommitKilledLd: - fetchStage$redirect_pc = rob$deqPort_0_deq_data[282:219]; - WILL_FIRE_RL_commitStage_doCommitTrap_handle: - fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_4; + fetchStage$redirect_pc = rob$deqPort_0_deq_data[630:502]; WILL_FIRE_RL_commitStage_doCommitSystemInst: fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_5; + WILL_FIRE_RL_rl_debug_resume: + fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_6; default: fetchStage$redirect_pc = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign fetchStage$start_pc = coreReq_start_startpc ; + assign fetchStage$start_pc = + { 65'h1FFFF000000000000, coreReq_start_startpc } ; assign fetchStage$train_predictors_dpTrain = coreFix_trainBPQ_1$EMPTY_N ? - coreFix_trainBPQ_1$D_OUT[24:1] : - coreFix_trainBPQ_0$D_OUT[24:1] ; + coreFix_trainBPQ_1$D_OUT[25:2] : + coreFix_trainBPQ_0$D_OUT[25:2] ; assign fetchStage$train_predictors_iType = coreFix_trainBPQ_1$EMPTY_N ? - coreFix_trainBPQ_1$D_OUT[30:26] : - coreFix_trainBPQ_0$D_OUT[30:26] ; - assign fetchStage$train_predictors_mispred = + coreFix_trainBPQ_1$D_OUT[31:27] : + coreFix_trainBPQ_0$D_OUT[31:27] ; + assign fetchStage$train_predictors_isCompressed = coreFix_trainBPQ_1$EMPTY_N ? coreFix_trainBPQ_1$D_OUT[0] : coreFix_trainBPQ_0$D_OUT[0] ; + assign fetchStage$train_predictors_mispred = + coreFix_trainBPQ_1$EMPTY_N ? + coreFix_trainBPQ_1$D_OUT[1] : + coreFix_trainBPQ_0$D_OUT[1] ; assign fetchStage$train_predictors_next_pc = coreFix_trainBPQ_1$EMPTY_N ? - coreFix_trainBPQ_1$D_OUT[94:31] : - coreFix_trainBPQ_0$D_OUT[94:31] ; + coreFix_trainBPQ_1$D_OUT[160:32] : + coreFix_trainBPQ_0$D_OUT[160:32] ; assign fetchStage$train_predictors_pc = coreFix_trainBPQ_1$EMPTY_N ? - coreFix_trainBPQ_1$D_OUT[158:95] : - coreFix_trainBPQ_0$D_OUT[158:95] ; + coreFix_trainBPQ_1$D_OUT[289:161] : + coreFix_trainBPQ_0$D_OUT[289:161] ; assign fetchStage$train_predictors_taken = coreFix_trainBPQ_1$EMPTY_N ? - coreFix_trainBPQ_1$D_OUT[25] : - coreFix_trainBPQ_0$D_OUT[25] ; + coreFix_trainBPQ_1$D_OUT[26] : + coreFix_trainBPQ_0$D_OUT[26] ; assign fetchStage$EN_pipelines_0_deq = WILL_FIRE_RL_renameStage_doRenaming_wrongPath && fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13834 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 || + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21775 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21020 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_pipelines_1_deq = @@ -16297,12 +16749,15 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13928 && - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13938 && - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13650 ; - assign fetchStage$EN_iTlbIfc_flush = MUX_flush_tlbs$write_1__SEL_1 ; + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21880 && + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21891 && + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21580 ; + assign fetchStage$EN_iTlbIfc_flush = + WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || + WILL_FIRE_RL_rl_debug_resume ; assign fetchStage$EN_iTlbIfc_updateVMInfo = - MUX_update_vm_info$write_1__SEL_1 ; + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_rl_debug_resume ; assign fetchStage$EN_iTlbIfc_to_proc_request_put = 1'b0 ; assign fetchStage$EN_iTlbIfc_to_proc_response_get = 1'b0 ; assign fetchStage$EN_iTlbIfc_toParent_rqToP_deq = WILL_FIRE_RL_sendITlbReq ; @@ -16317,7 +16772,7 @@ module mkCore(CLK, assign fetchStage$EN_iTlbIfc_perf_resp = 1'b0 ; assign fetchStage$EN_iMemIfc_to_proc_request_put = 1'b0 ; assign fetchStage$EN_iMemIfc_to_proc_response_get = 1'b0 ; - assign fetchStage$EN_iMemIfc_flush = 1'b0 ; + assign fetchStage$EN_iMemIfc_flush = CAN_FIRE_RL_setDoFlushCaches ; assign fetchStage$EN_iMemIfc_perf_setStatus = 1'b0 ; assign fetchStage$EN_iMemIfc_perf_req = 1'b0 ; assign fetchStage$EN_iMemIfc_perf_resp = 1'b0 ; @@ -16335,21 +16790,27 @@ module mkCore(CLK, assign fetchStage$EN_start = EN_coreReq_start ; assign fetchStage$EN_stop = 1'b0 ; assign fetchStage$EN_setWaitRedirect = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + NOT_commitStage_commitTrap_2029_BITS_44_TO_43__ETC___d22295 || WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_redirect = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || WILL_FIRE_RL_commitStage_doCommitKilledLd || - WILL_FIRE_RL_commitStage_doCommitTrap_handle || - WILL_FIRE_RL_commitStage_doCommitSystemInst ; + WILL_FIRE_RL_commitStage_doCommitSystemInst || + WILL_FIRE_RL_rl_debug_resume ; + assign fetchStage$EN_setWaitFlush = + MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign fetchStage$EN_done_flushing = CAN_FIRE_RL_readyToFetch ; assign fetchStage$EN_train_predictors = coreFix_trainBPQ_1$EMPTY_N || WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ; - assign fetchStage$EN_flush_predictors = 1'b0 ; + assign fetchStage$EN_flush_predictors = CAN_FIRE_RL_setDoFlushBrPred ; assign fetchStage$EN_perf_setStatus = 1'b0 ; assign fetchStage$EN_perf_req = 1'b0 ; assign fetchStage$EN_perf_resp = 1'b0 ; @@ -16362,9 +16823,17 @@ module mkCore(CLK, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 : MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 ; assign l2Tlb$toMem_respLd_enq_x = tlbToMem_respLd_enq_x ; - assign l2Tlb$updateVMInfo_vmD = coreFix_memExe_dTlb$updateVMInfo_vm ; - assign l2Tlb$updateVMInfo_vmI = fetchStage$iTlbIfc_updateVMInfo_vm ; - assign l2Tlb$EN_updateVMInfo = MUX_update_vm_info$write_1__SEL_1 ; + assign l2Tlb$updateVMInfo_vmD = + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 : + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ; + assign l2Tlb$updateVMInfo_vmI = + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; + assign l2Tlb$EN_updateVMInfo = + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_rl_debug_resume ; assign l2Tlb$EN_toChildren_rqFromC_put = WILL_FIRE_RL_sendDTlbReq || WILL_FIRE_RL_sendITlbReq ; assign l2Tlb$EN_toChildren_rsToC_deq = @@ -16380,234 +16849,6 @@ module mkCore(CLK, assign l2Tlb$EN_perf_req = 1'b0 ; assign l2Tlb$EN_perf_resp = 1'b0 ; - // submodule mmio_cRqQ_clearReq_dummy2_0 - assign mmio_cRqQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign mmio_cRqQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule mmio_cRqQ_clearReq_dummy2_1 - assign mmio_cRqQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign mmio_cRqQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule mmio_cRqQ_deqReq_dummy2_0 - assign mmio_cRqQ_deqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_cRqQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRq_deq ; - - // submodule mmio_cRqQ_deqReq_dummy2_1 - assign mmio_cRqQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_cRqQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_cRqQ_deqReq_dummy2_2 - assign mmio_cRqQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_cRqQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmio_cRqQ_enqReq_dummy2_0 - assign mmio_cRqQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_cRqQ_enqReq_dummy2_0$EN = - WILL_FIRE_RL_mmio_sendInstReq || WILL_FIRE_RL_mmio_sendDataReq ; - - // submodule mmio_cRqQ_enqReq_dummy2_1 - assign mmio_cRqQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_cRqQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_cRqQ_enqReq_dummy2_2 - assign mmio_cRqQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_cRqQ_enqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmio_cRsQ_clearReq_dummy2_0 - assign mmio_cRsQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign mmio_cRsQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule mmio_cRsQ_clearReq_dummy2_1 - assign mmio_cRsQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign mmio_cRsQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule mmio_cRsQ_deqReq_dummy2_0 - assign mmio_cRsQ_deqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_cRsQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRs_deq ; - - // submodule mmio_cRsQ_deqReq_dummy2_1 - assign mmio_cRsQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_cRsQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_cRsQ_deqReq_dummy2_2 - assign mmio_cRsQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_cRsQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmio_cRsQ_enqReq_dummy2_0 - assign mmio_cRsQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_cRsQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ; - - // submodule mmio_cRsQ_enqReq_dummy2_1 - assign mmio_cRsQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_cRsQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_cRsQ_enqReq_dummy2_2 - assign mmio_cRsQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_cRsQ_enqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmio_dataPendQ_clearReq_dummy2_0 - assign mmio_dataPendQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign mmio_dataPendQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule mmio_dataPendQ_clearReq_dummy2_1 - assign mmio_dataPendQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign mmio_dataPendQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule mmio_dataPendQ_deqReq_dummy2_0 - assign mmio_dataPendQ_deqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_dataPendQ_deqReq_dummy2_0$EN = - mmio_dataRespQ_deqReq_lat_0$whas ; - - // submodule mmio_dataPendQ_deqReq_dummy2_1 - assign mmio_dataPendQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_dataPendQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_dataPendQ_deqReq_dummy2_2 - assign mmio_dataPendQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_dataPendQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmio_dataPendQ_enqReq_dummy2_0 - assign mmio_dataPendQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_dataPendQ_enqReq_dummy2_0$EN = - mmio_dataPendQ_enqReq_lat_0$whas ; - - // submodule mmio_dataPendQ_enqReq_dummy2_1 - assign mmio_dataPendQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_dataPendQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_dataPendQ_enqReq_dummy2_2 - assign mmio_dataPendQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_dataPendQ_enqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmio_dataReqQ_clearReq_dummy2_0 - assign mmio_dataReqQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign mmio_dataReqQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule mmio_dataReqQ_clearReq_dummy2_1 - assign mmio_dataReqQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign mmio_dataReqQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule mmio_dataReqQ_deqReq_dummy2_0 - assign mmio_dataReqQ_deqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_dataReqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataReq ; - - // submodule mmio_dataReqQ_deqReq_dummy2_1 - assign mmio_dataReqQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_dataReqQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_dataReqQ_deqReq_dummy2_2 - assign mmio_dataReqQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_dataReqQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmio_dataReqQ_enqReq_dummy2_0 - assign mmio_dataReqQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_dataReqQ_enqReq_dummy2_0$EN = mmio_dataPendQ_enqReq_lat_0$whas ; - - // submodule mmio_dataReqQ_enqReq_dummy2_1 - assign mmio_dataReqQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_dataReqQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_dataReqQ_enqReq_dummy2_2 - assign mmio_dataReqQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_dataReqQ_enqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmio_dataRespQ_clearReq_dummy2_0 - assign mmio_dataRespQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign mmio_dataRespQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule mmio_dataRespQ_clearReq_dummy2_1 - assign mmio_dataRespQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign mmio_dataRespQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule mmio_dataRespQ_deqReq_dummy2_0 - assign mmio_dataRespQ_deqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_dataRespQ_deqReq_dummy2_0$EN = - mmio_dataRespQ_deqReq_lat_0$whas ; - - // submodule mmio_dataRespQ_deqReq_dummy2_1 - assign mmio_dataRespQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_dataRespQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_dataRespQ_deqReq_dummy2_2 - assign mmio_dataRespQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_dataRespQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmio_dataRespQ_enqReq_dummy2_0 - assign mmio_dataRespQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_dataRespQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataResp ; - - // submodule mmio_dataRespQ_enqReq_dummy2_1 - assign mmio_dataRespQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_dataRespQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_dataRespQ_enqReq_dummy2_2 - assign mmio_dataRespQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_dataRespQ_enqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmio_pRqQ_clearReq_dummy2_0 - assign mmio_pRqQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign mmio_pRqQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule mmio_pRqQ_clearReq_dummy2_1 - assign mmio_pRqQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign mmio_pRqQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule mmio_pRqQ_deqReq_dummy2_0 - assign mmio_pRqQ_deqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_pRqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ; - - // submodule mmio_pRqQ_deqReq_dummy2_1 - assign mmio_pRqQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_pRqQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_pRqQ_deqReq_dummy2_2 - assign mmio_pRqQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_pRqQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmio_pRqQ_enqReq_dummy2_0 - assign mmio_pRqQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_pRqQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRq_enq ; - - // submodule mmio_pRqQ_enqReq_dummy2_1 - assign mmio_pRqQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_pRqQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_pRqQ_enqReq_dummy2_2 - assign mmio_pRqQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_pRqQ_enqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmio_pRsQ_clearReq_dummy2_0 - assign mmio_pRsQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign mmio_pRsQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule mmio_pRsQ_clearReq_dummy2_1 - assign mmio_pRsQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign mmio_pRsQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule mmio_pRsQ_deqReq_dummy2_0 - assign mmio_pRsQ_deqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_pRsQ_deqReq_dummy2_0$EN = mmio_pRsQ_deqReq_lat_0$whas ; - - // submodule mmio_pRsQ_deqReq_dummy2_1 - assign mmio_pRsQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_pRsQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_pRsQ_deqReq_dummy2_2 - assign mmio_pRsQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_pRsQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmio_pRsQ_enqReq_dummy2_0 - assign mmio_pRsQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign mmio_pRsQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRs_enq ; - - // submodule mmio_pRsQ_enqReq_dummy2_1 - assign mmio_pRsQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign mmio_pRsQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmio_pRsQ_enqReq_dummy2_2 - assign mmio_pRsQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign mmio_pRsQ_enqReq_dummy2_2$EN = 1'd1 ; - // submodule perfReqQ assign perfReqQ$D_IN = { coreReq_perfReq_loc, coreReq_perfReq_t } ; assign perfReqQ$ENQ = EN_coreReq_perfReq ; @@ -16616,19 +16857,38 @@ module mkCore(CLK, // submodule regRenamingTable assign regRenamingTable$rename_0_claimRename_r = - fetchStage$pipelines_0_first[95:69] ; + fetchStage$pipelines_0_first[96:70] ; assign regRenamingTable$rename_0_claimRename_sb = specTagManager$currentSpecBits ; - assign regRenamingTable$rename_0_getRename_r = - fetchStage$pipelines_0_first[95:69] ; + always@(MUX_regRenamingTable$rename_0_getRename_1__SEL_1 or + fetchStage$pipelines_0_first or + MUX_regRenamingTable$rename_0_getRename_1__SEL_2 or + MUX_regRenamingTable$rename_0_getRename_1__VAL_2 or + MUX_regRenamingTable$rename_0_getRename_1__SEL_3 or + MUX_regRenamingTable$rename_0_getRename_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_regRenamingTable$rename_0_getRename_1__SEL_1: + regRenamingTable$rename_0_getRename_r = + fetchStage$pipelines_0_first[96:70]; + MUX_regRenamingTable$rename_0_getRename_1__SEL_2: + regRenamingTable$rename_0_getRename_r = + MUX_regRenamingTable$rename_0_getRename_1__VAL_2; + MUX_regRenamingTable$rename_0_getRename_1__SEL_3: + regRenamingTable$rename_0_getRename_r = + MUX_regRenamingTable$rename_0_getRename_1__VAL_3; + default: regRenamingTable$rename_0_getRename_r = + 27'b010101010101010101010101010 /* unspecified value */ ; + endcase + end assign regRenamingTable$rename_1_claimRename_r = - fetchStage$pipelines_1_first[95:69] ; + fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h675346 ; + renaming_spec_bits__h965955 ; assign regRenamingTable$rename_1_getRename_r = - fetchStage$pipelines_1_first[95:69] ; + fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign regRenamingTable$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -16654,8 +16914,8 @@ module mkCore(CLK, assign regRenamingTable$EN_rename_0_claimRename = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13834 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 || + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21775 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21020 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign regRenamingTable$EN_rename_1_claimRename = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -16668,16 +16928,17 @@ module mkCore(CLK, rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] != 5'd0 && - rob$deqPort_1_deq_data[186:182] != 5'd21 && - rob$deqPort_1_deq_data[186:182] != 5'd17 && - rob$deqPort_1_deq_data[186:182] != 5'd18 && - rob$deqPort_1_deq_data[186:182] != 5'd13 && - rob$deqPort_1_deq_data[186:182] != 5'd16 && - rob$deqPort_1_deq_data[186:182] != 5'd15 && - rob$deqPort_1_deq_data[186:182] != 5'd19 && - rob$deqPort_1_deq_data[186:182] != 5'd20 ; + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] != 5'd0 && + rob$deqPort_1_deq_data[469:465] != 5'd26 && + rob$deqPort_1_deq_data[469:465] != 5'd22 && + rob$deqPort_1_deq_data[469:465] != 5'd23 && + rob$deqPort_1_deq_data[469:465] != 5'd17 && + rob$deqPort_1_deq_data[469:465] != 5'd18 && + rob$deqPort_1_deq_data[469:465] != 5'd21 && + rob$deqPort_1_deq_data[469:465] != 5'd20 && + rob$deqPort_1_deq_data[469:465] != 5'd24 && + rob$deqPort_1_deq_data[469:465] != 5'd25 ; assign regRenamingTable$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -16698,17 +16959,20 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ; assign rf$read_2_rd3_rindx = coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ; - assign rf$read_3_rd1_rindx = coreFix_memExe_dispToRegQ$first[61:55] ; - assign rf$read_3_rd2_rindx = coreFix_memExe_dispToRegQ$first[53:47] ; + assign rf$read_3_rd1_rindx = coreFix_memExe_dispToRegQ$first[108:102] ; + assign rf$read_3_rd2_rindx = coreFix_memExe_dispToRegQ$first[100:94] ; assign rf$read_3_rd3_rindx = 7'h0 ; - assign rf$write_0_wr_data = coreFix_aluExe_0_exeToFinQ$first[275:212] ; - assign rf$write_0_wr_rindx = coreFix_aluExe_0_exeToFinQ$first[319:313] ; - assign rf$write_1_wr_data = coreFix_aluExe_1_exeToFinQ$first[275:212] ; - assign rf$write_1_wr_rindx = coreFix_aluExe_1_exeToFinQ$first[319:313] ; + assign rf$read_4_rd1_rindx = regRenamingTable$rename_0_getRename[31:25] ; + assign rf$read_4_rd2_rindx = 7'h0 ; + assign rf$read_4_rd3_rindx = 7'h0 ; + assign rf$write_0_wr_data = coreFix_aluExe_0_exeToFinQ$first[1015:863] ; + assign rf$write_0_wr_rindx = coreFix_aluExe_0_exeToFinQ$first[1060:1054] ; + assign rf$write_1_wr_data = coreFix_aluExe_1_exeToFinQ$first[1015:863] ; + assign rf$write_1_wr_rindx = coreFix_aluExe_1_exeToFinQ$first[1060:1054] ; always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or MUX_rf$write_2_wr_2__VAL_1 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or - coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or + MUX_rf$write_2_wr_2__VAL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or MUX_rf$write_2_wr_2__VAL_3 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or @@ -16722,8 +16986,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1: rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_1; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2: - rf$write_2_wr_data = - coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38]; + rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_2; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3: rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_3; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4: @@ -16733,67 +16996,67 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6: rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_6; default: rf$write_2_wr_data = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data) + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data) begin case (1'b1) // synopsys parallel_case MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1: rf$write_2_wr_rindx = - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2: rf$write_2_wr_rindx = - coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25]; + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3: rf$write_2_wr_rindx = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4: rf$write_2_wr_rindx = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5: rf$write_2_wr_rindx = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6: rf$write_2_wr_rindx = - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25]; default: rf$write_2_wr_rindx = 7'b0101010 /* unspecified value */ ; endcase end always@(MUX_rf$write_3_wr_1__SEL_1 or - coreFix_memExe_respLrScAmoQ_data_0 or + MUX_rf$write_3_wr_2__VAL_1 or MUX_rf$write_3_wr_1__SEL_2 or - mmio_dataRespQ_data_0 or + MUX_rf$write_3_wr_2__VAL_2 or MUX_rf$write_3_wr_1__SEL_3 or MUX_rf$write_3_wr_2__VAL_3 or MUX_rf$write_3_wr_1__SEL_4 or MUX_rf$write_3_wr_2__VAL_4 or - MUX_rf$write_3_wr_2__SEL_5 or coreFix_memExe_lsq$respLd) + MUX_rf$write_3_wr_2__SEL_5 or MUX_rf$write_3_wr_2__VAL_5) begin case (1'b1) // synopsys parallel_case MUX_rf$write_3_wr_1__SEL_1: - rf$write_3_wr_data = coreFix_memExe_respLrScAmoQ_data_0; + rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_1; MUX_rf$write_3_wr_1__SEL_2: - rf$write_3_wr_data = mmio_dataRespQ_data_0[63:0]; + rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_2; MUX_rf$write_3_wr_1__SEL_3: rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_3; MUX_rf$write_3_wr_1__SEL_4: rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_4; MUX_rf$write_3_wr_2__SEL_5: - rf$write_3_wr_data = coreFix_memExe_lsq$respLd[63:0]; + rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_5; default: rf$write_3_wr_data = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end always@(MUX_rf$write_3_wr_1__SEL_5 or @@ -16806,21 +17069,24 @@ module mkCore(CLK, begin case (1'b1) // synopsys parallel_case MUX_rf$write_3_wr_1__SEL_5: - rf$write_3_wr_rindx = coreFix_memExe_lsq$respLd[71:65]; + rf$write_3_wr_rindx = coreFix_memExe_lsq$respLd[136:130]; MUX_rf$write_3_wr_1__SEL_3 || MUX_rf$write_3_wr_1__SEL_4: - rf$write_3_wr_rindx = coreFix_memExe_lsq$firstLd[88:82]; + rf$write_3_wr_rindx = coreFix_memExe_lsq$firstLd[105:99]; MUX_rf$write_3_wr_1__SEL_1 || MUX_rf$write_3_wr_1__SEL_2: - rf$write_3_wr_rindx = coreFix_memExe_lsq$firstSt[149:143]; + rf$write_3_wr_rindx = coreFix_memExe_lsq$firstSt[231:225]; default: rf$write_3_wr_rindx = 7'b0101010 /* unspecified value */ ; endcase end + assign rf$write_4_wr_data = + WILL_FIRE_RL_rl_debug_gpr_write ? + MUX_rf$write_4_wr_2__VAL_1 : + MUX_rf$write_4_wr_2__VAL_2 ; + assign rf$write_4_wr_rindx = regRenamingTable$rename_0_getRename[31:25] ; assign rf$EN_write_0_wr = - _dor1rf$EN_write_0_wr && coreFix_aluExe_0_exeToFinQ$first[320] ; + _dor1rf$EN_write_0_wr && coreFix_aluExe_0_exeToFinQ$first[1061] ; assign rf$EN_write_1_wr = - _dor1rf$EN_write_1_wr && coreFix_aluExe_1_exeToFinQ$first[320] ; + _dor1rf$EN_write_1_wr && coreFix_aluExe_1_exeToFinQ$first[1061] ; assign rf$EN_write_2_wr = - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && @@ -16830,19 +17096,24 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ; + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] || + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ; assign rf$EN_write_3_wr = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && - coreFix_memExe_lsq$firstSt[150] || + coreFix_memExe_lsq$firstSt[232] || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && - coreFix_memExe_lsq$firstSt[150] || + coreFix_memExe_lsq$firstSt[232] || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && - coreFix_memExe_lsq$firstLd[89] || + coreFix_memExe_lsq$firstLd[106] || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && - coreFix_memExe_lsq$firstLd[89] || + coreFix_memExe_lsq$firstLd[106] || (WILL_FIRE_RL_coreFix_memExe_doRespLdForward || WILL_FIRE_RL_coreFix_memExe_doRespLdMem) && - coreFix_memExe_lsq$respLd[72] ; + coreFix_memExe_lsq$respLd[137] ; + assign rf$EN_write_4_wr = + WILL_FIRE_RL_rl_debug_gpr_write || + WILL_FIRE_RL_rl_debug_fpr_write ; // submodule rob always@(MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 or @@ -16860,30 +17131,37 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_SystemInst: rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_3; default: rob$enqPort_0_enq_x = - 283'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + 631'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign rob$enqPort_1_enq_x = - { fetchStage$pipelines_1_first[387:324], - fetchStage$pipelines_1_first[127:96], - fetchStage$pipelines_1_first[199:195], - fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437, - 73'h1280000000000000000, - fetchStage$pipelines_1_first[323:260], + { fetchStage$pipelines_1_first[590:462], + fetchStage$pipelines_1_first[128:97], + fetchStage$pipelines_1_first[272:268], + fetchStage$pipelines_1_first[76:70], + 163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, + fetchStage_pipelines_1_first__0054_BIT_167_131_ETC___d21342, + fetchStage_pipelines_1_first__0054_BIT_180_122_ETC___d21318, + 81'h12AA80000000000000000, + fetchStage$pipelines_1_first[495:333], 5'd0, - fetchStage$pipelines_1_first[75] && - fetchStage$pipelines_1_first[74], - fetchStage$pipelines_1_first[194:192] != 3'd0 && - fetchStage$pipelines_1_first[194:192] != 3'd1 && - fetchStage$pipelines_1_first[194:192] != 3'd2 && - fetchStage$pipelines_1_first[194:192] != 3'd3 && - fetchStage$pipelines_1_first[194:192] != 3'd4, - fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d14029 || - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13992, - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d14039, + fetchStage$pipelines_1_first[76] && + fetchStage$pipelines_1_first[75], + fetchStage$pipelines_1_first[267:265] != 3'd0 && + fetchStage$pipelines_1_first[267:265] != 3'd1 && + fetchStage$pipelines_1_first[237:236] != 2'd0 && + fetchStage$pipelines_1_first[237:236] != 2'd1 && + fetchStage$pipelines_1_first[267:265] != 3'd2 && + fetchStage$pipelines_1_first[267:265] != 3'd3 && + fetchStage$pipelines_1_first[267:265] != 3'd4, + fetchStage$pipelines_1_first[237:236] == 2'd0 || + fetchStage$pipelines_1_first[237:236] == 2'd1 || + fetchStage$pipelines_1_first[267:265] != 3'd2 || + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21993 || + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21951, + IF_NOT_fetchStage_pipelines_1_first__0054_BITS_ETC___d22005, 7'd32, - renaming_spec_bits__h675346 } ; + renaming_spec_bits__h965955 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -16911,13 +17189,13 @@ module mkCore(CLK, MUX_rob$setExecuted_deqLSQ_1__SEL_1 || MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem: - rob$setExecuted_deqLSQ_cause = 5'd10; + rob$setExecuted_deqLSQ_cause = 14'd2730; WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault: - rob$setExecuted_deqLSQ_cause = 5'd21; + rob$setExecuted_deqLSQ_cause = 14'd11589; WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault: - rob$setExecuted_deqLSQ_cause = 5'd23; + rob$setExecuted_deqLSQ_cause = 14'd11591; default: rob$setExecuted_deqLSQ_cause = - 5'b01010 /* unspecified value */ ; + 14'b10101010101010 /* unspecified value */ ; endcase end assign rob$setExecuted_deqLSQ_ld_killed = @@ -16929,28 +17207,79 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) ? - coreFix_memExe_lsq$firstLd[113:102] : - coreFix_memExe_lsq$firstSt[170:159] ; + coreFix_memExe_lsq$firstLd[138:127] : + coreFix_memExe_lsq$firstSt[252:241] ; + assign rob$setExecuted_doFinishAlu_0_set_cause = + { (coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + coreFix_aluExe_0_exeToFinQ_first__9735_BITS_14_ETC___d19778 : + coreFix_aluExe_0_exeToFinQ$first[294], + IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19881 } ; assign rob$setExecuted_doFinishAlu_0_set_cf = - coreFix_aluExe_0_exeToFinQ$first[146:17] ; + coreFix_aluExe_0_exeToFinQ$first[623:295] ; assign rob$setExecuted_doFinishAlu_0_set_csrData = - coreFix_aluExe_0_exeToFinQ$first[211:147] ; + coreFix_aluExe_0_exeToFinQ$first[852:788] ; + assign rob$setExecuted_doFinishAlu_0_set_dst_data = + coreFix_aluExe_0_exeToFinQ$first[1015:853] ; + assign rob$setExecuted_doFinishAlu_0_set_scrData = + coreFix_aluExe_0_exeToFinQ$first[787:624] ; assign rob$setExecuted_doFinishAlu_0_set_x = - coreFix_aluExe_0_exeToFinQ$first[311:300] ; + coreFix_aluExe_0_exeToFinQ$first[1052:1041] ; + assign rob$setExecuted_doFinishAlu_1_set_cause = + { (coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + coreFix_aluExe_1_exeToFinQ_first__7657_BITS_14_ETC___d17701 : + coreFix_aluExe_1_exeToFinQ$first[294], + IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17804 } ; assign rob$setExecuted_doFinishAlu_1_set_cf = - coreFix_aluExe_1_exeToFinQ$first[146:17] ; + coreFix_aluExe_1_exeToFinQ$first[623:295] ; assign rob$setExecuted_doFinishAlu_1_set_csrData = - coreFix_aluExe_1_exeToFinQ$first[211:147] ; + coreFix_aluExe_1_exeToFinQ$first[852:788] ; + assign rob$setExecuted_doFinishAlu_1_set_dst_data = + coreFix_aluExe_1_exeToFinQ$first[1015:853] ; + assign rob$setExecuted_doFinishAlu_1_set_scrData = + coreFix_aluExe_1_exeToFinQ$first[787:624] ; assign rob$setExecuted_doFinishAlu_1_set_x = - coreFix_aluExe_1_exeToFinQ$first[311:300] ; + coreFix_aluExe_1_exeToFinQ$first[1052:1041] ; + assign rob$setExecuted_doFinishFpuMulDiv_0_set_cause = 6'd10 ; always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or - MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 or + data__h567607 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or - MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 or + data__h613367 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or - MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 or + data__h659114 or + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or + data__h704928 or + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or data__h705791) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple: + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = + coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38]; + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma: + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h567607; + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv: + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h613367; + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt: + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h659114; + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul: + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h704928; + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv: + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h705791; + default: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or + coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or + MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 or + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or + MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 or + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or + MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv) begin @@ -16960,13 +17289,13 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[37:33]; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma: rob$setExecuted_doFinishFpuMulDiv_0_set_fflags = - MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2; + MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv: rob$setExecuted_doFinishFpuMulDiv_0_set_fflags = - MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3; + MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt: rob$setExecuted_doFinishFpuMulDiv_0_set_fflags = - MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4; + MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv: rob$setExecuted_doFinishFpuMulDiv_0_set_fflags = 5'd0; @@ -17011,22 +17340,26 @@ module mkCore(CLK, endcase end assign rob$setExecuted_doFinishMem_access_at_commit = - IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740 && - (coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731 || - coreFix_memExe_dTlb$procResp[105:103] == 3'd2 || - coreFix_memExe_dTlb$procResp[105:103] == 3'd3 || - coreFix_memExe_dTlb$procResp[105:103] == 3'd4) ; + IF_coreFix_memExe_dTlb_procResp__239_BIT_277_5_ETC___d4553 && + (coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548 || + coreFix_memExe_dTlb$procResp[490:488] == 3'd2 || + coreFix_memExe_dTlb$procResp[490:488] == 3'd3 || + coreFix_memExe_dTlb$procResp[490:488] == 3'd4) ; assign rob$setExecuted_doFinishMem_non_mmio_st_done = - IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740 && - NOT_coreFix_memExe_dTlb_procResp__712_BITS_174_ETC___d1751 && - coreFix_memExe_dTlb$procResp[105:103] == 3'd1 ; + IF_coreFix_memExe_dTlb_procResp__239_BIT_277_5_ETC___d4553 && + NOT_coreFix_memExe_dTlb_procResp__239_BITS_560_ETC___d4563 && + coreFix_memExe_dTlb$procResp[490:488] == 3'd1 ; + assign rob$setExecuted_doFinishMem_store_data = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + assign rob$setExecuted_doFinishMem_store_data_BE = + 8'b10101010 /* unspecified value */ ; assign rob$setExecuted_doFinishMem_vaddr = - coreFix_memExe_dTlb$procResp[76:13] ; + coreFix_memExe_dTlb$procResp[453:291] ; assign rob$setExecuted_doFinishMem_x = - coreFix_memExe_dTlb$procResp[102:91] ; + coreFix_memExe_dTlb$procResp[487:476] ; assign rob$setLSQAtCommitNotified_x = rob$deqPort_0_getDeqInstTag ; assign rob$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or @@ -17036,10 +17369,10 @@ module mkCore(CLK, case (1'b1) // synopsys parallel_case WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: rob$specUpdate_incorrectSpeculation_inst_tag = - coreFix_aluExe_1_exeToFinQ$first[311:300]; + coreFix_aluExe_1_exeToFinQ$first[1052:1041]; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: rob$specUpdate_incorrectSpeculation_inst_tag = - coreFix_aluExe_0_exeToFinQ$first[311:300]; + coreFix_aluExe_0_exeToFinQ$first[1052:1041]; MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3: rob$specUpdate_incorrectSpeculation_inst_tag = 12'b101010101010 /* unspecified value */ ; @@ -17072,8 +17405,8 @@ module mkCore(CLK, assign rob$EN_enqPort_0_enq = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13834 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 || + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21775 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21020 || WILL_FIRE_RL_renameStage_doRenaming_Trap || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign rob$EN_enqPort_1_enq = @@ -17089,16 +17422,17 @@ module mkCore(CLK, rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] != 5'd0 && - rob$deqPort_1_deq_data[186:182] != 5'd21 && - rob$deqPort_1_deq_data[186:182] != 5'd17 && - rob$deqPort_1_deq_data[186:182] != 5'd18 && - rob$deqPort_1_deq_data[186:182] != 5'd13 && - rob$deqPort_1_deq_data[186:182] != 5'd16 && - rob$deqPort_1_deq_data[186:182] != 5'd15 && - rob$deqPort_1_deq_data[186:182] != 5'd19 && - rob$deqPort_1_deq_data[186:182] != 5'd20 ; + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] != 5'd0 && + rob$deqPort_1_deq_data[469:465] != 5'd26 && + rob$deqPort_1_deq_data[469:465] != 5'd22 && + rob$deqPort_1_deq_data[469:465] != 5'd23 && + rob$deqPort_1_deq_data[469:465] != 5'd17 && + rob$deqPort_1_deq_data[469:465] != 5'd18 && + rob$deqPort_1_deq_data[469:465] != 5'd21 && + rob$deqPort_1_deq_data[469:465] != 5'd20 && + rob$deqPort_1_deq_data[469:465] != 5'd24 && + rob$deqPort_1_deq_data[469:465] != 5'd25 ; assign rob$EN_setLSQAtCommitNotified = CAN_FIRE_RL_commitStage_notifyLSQCommit ; assign rob$EN_setExecuted_deqLSQ = @@ -17142,41 +17476,41 @@ module mkCore(CLK, assign sbAggr$setReady_0_put = coreFix_aluExe_0_rsAlu$dispatchData[40:34] ; assign sbAggr$setReady_1_put = coreFix_aluExe_1_rsAlu$dispatchData[40:34] ; always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data) + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data) begin case (1'b1) // synopsys parallel_case MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1: sbAggr$setReady_2_put = - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2: sbAggr$setReady_2_put = - coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25]; + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3: sbAggr$setReady_2_put = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4: sbAggr$setReady_2_put = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5: sbAggr$setReady_2_put = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6: sbAggr$setReady_2_put = - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25]; default: sbAggr$setReady_2_put = 7'b0101010 /* unspecified value */ ; endcase end - assign sbAggr$setReady_3_put = coreFix_memExe_lsq$issueLd[71:65] ; + assign sbAggr$setReady_3_put = coreFix_memExe_lsq$issueLd[136:130] ; always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 or coreFix_memExe_lsq$getHit or @@ -17189,17 +17523,17 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4: sbAggr$setReady_4_put = coreFix_memExe_lsq$getHit[7:1]; MUX_sbAggr$setReady_4_put_1__SEL_2: - sbAggr$setReady_4_put = coreFix_memExe_lsq$firstLd[88:82]; + sbAggr$setReady_4_put = coreFix_memExe_lsq$firstLd[105:99]; MUX_sbAggr$setReady_4_put_1__SEL_1: - sbAggr$setReady_4_put = coreFix_memExe_lsq$firstSt[149:143]; + sbAggr$setReady_4_put = coreFix_memExe_lsq$firstSt[231:225]; default: sbAggr$setReady_4_put = 7'b0101010 /* unspecified value */ ; endcase end assign sbAggr$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13834 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 || + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21775 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21020 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbAggr$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -17210,8 +17544,6 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && coreFix_aluExe_1_rsAlu$dispatchData[41] ; assign sbAggr$EN_setReady_2_put = - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && @@ -17221,24 +17553,26 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ; + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] || + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ; assign sbAggr$EN_setReady_3_put = _dor1sbAggr$EN_setReady_3_put && - coreFix_memExe_lsq$issueLd[74:73] != 2'd0 && - coreFix_memExe_lsq$issueLd[74:73] != 2'd1 && - coreFix_memExe_lsq$issueLd[72] ; + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137] ; assign sbAggr$EN_setReady_4_put = (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) && - coreFix_memExe_lsq$firstSt[150] || + coreFix_memExe_lsq$firstSt[232] || (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) && - coreFix_memExe_lsq$firstLd[89] || + coreFix_memExe_lsq$firstLd[106] || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5594 || WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0 && coreFix_memExe_lsq$getHit[8] && !coreFix_memExe_lsq$getHit[9] ; @@ -17252,43 +17586,44 @@ module mkCore(CLK, coreFix_aluExe_1_dispToRegQ$first[85:53] ; assign sbCons$lazyLookup_2_get_r = coreFix_fpuMulDivExe_0_dispToRegQ$first[56:24] ; - assign sbCons$lazyLookup_3_get_r = coreFix_memExe_dispToRegQ$first[62:30] ; + assign sbCons$lazyLookup_3_get_r = coreFix_memExe_dispToRegQ$first[109:77] ; + assign sbCons$lazyLookup_4_get_r = 33'h0 ; assign sbCons$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ; assign sbCons$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ; - assign sbCons$setReady_0_put = coreFix_aluExe_0_exeToFinQ$first[319:313] ; - assign sbCons$setReady_1_put = coreFix_aluExe_1_exeToFinQ$first[319:313] ; + assign sbCons$setReady_0_put = coreFix_aluExe_0_exeToFinQ$first[1060:1054] ; + assign sbCons$setReady_1_put = coreFix_aluExe_1_exeToFinQ$first[1060:1054] ; always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data) + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data) begin case (1'b1) // synopsys parallel_case MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1: sbCons$setReady_2_put = - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2: sbCons$setReady_2_put = - coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25]; + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3: sbCons$setReady_2_put = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4: sbCons$setReady_2_put = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5: sbCons$setReady_2_put = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25]; MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6: sbCons$setReady_2_put = - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25]; + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25]; default: sbCons$setReady_2_put = 7'b0101010 /* unspecified value */ ; endcase end @@ -17300,31 +17635,30 @@ module mkCore(CLK, begin case (1'b1) // synopsys parallel_case MUX_sbCons$setReady_3_put_1__SEL_1: - sbCons$setReady_3_put = coreFix_memExe_lsq$firstSt[149:143]; + sbCons$setReady_3_put = coreFix_memExe_lsq$firstSt[231:225]; MUX_sbCons$setReady_3_put_1__SEL_2: - sbCons$setReady_3_put = coreFix_memExe_lsq$firstLd[88:82]; + sbCons$setReady_3_put = coreFix_memExe_lsq$firstLd[105:99]; MUX_sbCons$setReady_3_put_1__SEL_3: - sbCons$setReady_3_put = coreFix_memExe_lsq$respLd[71:65]; + sbCons$setReady_3_put = coreFix_memExe_lsq$respLd[136:130]; default: sbCons$setReady_3_put = 7'b0101010 /* unspecified value */ ; endcase end + assign sbCons$setReady_4_put = 7'h0 ; assign sbCons$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13834 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 || + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21775 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21020 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbCons$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; assign sbCons$EN_setReady_0_put = _dor1sbCons$EN_setReady_0_put && - coreFix_aluExe_0_exeToFinQ$first[320] ; + coreFix_aluExe_0_exeToFinQ$first[1061] ; assign sbCons$EN_setReady_1_put = _dor1sbCons$EN_setReady_1_put && - coreFix_aluExe_1_exeToFinQ$first[320] ; + coreFix_aluExe_1_exeToFinQ$first[1061] ; assign sbCons$EN_setReady_2_put = - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && @@ -17334,21 +17668,24 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] || WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ; + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] || + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ; assign sbCons$EN_setReady_3_put = (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) && - coreFix_memExe_lsq$firstSt[150] || + coreFix_memExe_lsq$firstSt[232] || (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) && - coreFix_memExe_lsq$firstLd[89] || + coreFix_memExe_lsq$firstLd[106] || (WILL_FIRE_RL_coreFix_memExe_doRespLdForward || WILL_FIRE_RL_coreFix_memExe_doRespLdMem) && - coreFix_memExe_lsq$respLd[72] ; + coreFix_memExe_lsq$respLd[137] ; + assign sbCons$EN_setReady_4_put = 1'b0 ; // submodule specTagManager assign specTagManager$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 ; assign specTagManager$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17373,9 +17710,9 @@ module mkCore(CLK, end assign specTagManager$EN_claimSpecTag = WILL_FIRE_RL_renameStage_doRenaming && - (fetchStage_pipelines_0_canDeq__2603_AND_specTa_ETC___d13889 || - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13928 && - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d14016) ; + (fetchStage_pipelines_0_canDeq__0043_AND_specTa_ETC___d21836 || + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21880 && + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21980) ; assign specTagManager$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -17384,62 +17721,36 @@ module mkCore(CLK, assign specTagManager$EN_specUpdate_correctSpeculation = 1'd1 ; // remaining internal signals - module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h190137), - .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), - .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h191675)); - module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], - 3'd0 }), - .amoExec_current_data({ 63'd0, - msip__h75409 }), - .amoExec_in_data({ 32'd0, x__h75524 }), - .amoExec_upper_32_bits(1'd0), - .amoExec(amoExec___d880)); - module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220, - { coreFix_aluExe_1_regToExeQ$first[395], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221, - coreFix_aluExe_1_regToExeQ$first[382], - coreFix_aluExe_1_regToExeQ$first[381:350] } }), - .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[304:241]), - .basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[240:177]), - .basicExec_pc(coreFix_aluExe_1_regToExeQ$first[176:113]), - .basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]), - .basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]), - .basicExec(basicExec___d11860)); - module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223, - { coreFix_aluExe_0_regToExeQ$first[395], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224, - coreFix_aluExe_0_regToExeQ$first[382], - coreFix_aluExe_0_regToExeQ$first[381:350] } }), - .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]), - .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]), - .basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]), - .basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]), - .basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]), - .basicExec(basicExec___d12469)); - module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, - { { fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805 }, - fetchStage$pipelines_0_first[160], - x_data_imm__h667947 } }), - .checkForException_regs({ fetchStage$pipelines_0_first[95], - fetchStage$pipelines_0_first[94:89], - { fetchStage$pipelines_0_first[88], - fetchStage$pipelines_0_first[87:82] }, - { fetchStage$pipelines_0_first[81], - fetchStage$pipelines_0_first[80:76], - fetchStage$pipelines_0_first[75], - fetchStage$pipelines_0_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h649135, - r1__read_BITS_13_TO_12___h649320 != + module_amoExec instance_amoExec_5(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], + 4'd8 }), + .amoExec_wordIdx(2'd0), + .amoExec_current({ 128'd0, r__h854087 }), + .amoExec_inpt({ 97'd0, x__h65608 }), + .amoExec(amoExec___d773)); + module_amoExec instance_amoExec_4(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[11:4]), + .amoExec_wordIdx(wordIdx__h263160), + .amoExec_current({ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4836, + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849 } }), + .amoExec_inpt(coreFix_memExe_dMem_cache_m_banks_0_processAmo[140:12]), + .amoExec(amoExec___d4904)); + module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_0_first[272:268], + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20171, + IF_fetchStage_pipelines_0_first__0045_BITS_237_ETC___d20400 }), + .checkForException_regs({ fetchStage$pipelines_0_first[96], + fetchStage$pipelines_0_first[95:90], + { fetchStage$pipelines_0_first[89], + fetchStage$pipelines_0_first[88:83] }, + { fetchStage$pipelines_0_first[82], + fetchStage$pipelines_0_first[81:77], + { fetchStage$pipelines_0_first[76], + fetchStage$pipelines_0_first[75:70] } } }), + .checkForException_csrState({ x_decodeInfo_frm__h923668, + r1__read_BITS_13_TO_12___h923870 != 2'd0, - { prv__h707140, + { prv__h1011737, csrf_tvm_reg, - { r1__read_BIT_20___h649948, + { r1__read_BIT_20___h924376, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17450,26 +17761,27 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException(checkForException___d12839)); - module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361, - { fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437, - fetchStage$pipelines_1_first[160], - x_data_imm__h682690 } }), - .checkForException_regs({ fetchStage$pipelines_1_first[95], - fetchStage$pipelines_1_first[94:89], - { fetchStage$pipelines_1_first[88], - fetchStage$pipelines_1_first[87:82] }, - { fetchStage$pipelines_1_first[81], - fetchStage$pipelines_1_first[80:76], - fetchStage$pipelines_1_first[75], - fetchStage$pipelines_1_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h649135, - r1__read_BITS_13_TO_12___h649320 != + .checkForException_pcc(fetchStage$pipelines_0_first[590:462]), + .checkForException_fourByteInst(fetchStage$pipelines_0_first[98:97] == + 2'b11), + .checkForException(checkForException___d20432)); + module_checkForException instance_checkForException_2(.checkForException_dInst({ fetchStage$pipelines_1_first[272:268], + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21119, + IF_fetchStage_pipelines_1_first__0054_BITS_237_ETC___d21348 }), + .checkForException_regs({ fetchStage$pipelines_1_first[96], + fetchStage$pipelines_1_first[95:90], + { fetchStage$pipelines_1_first[89], + fetchStage$pipelines_1_first[88:83] }, + { fetchStage$pipelines_1_first[82], + fetchStage$pipelines_1_first[81:77], + { fetchStage$pipelines_1_first[76], + fetchStage$pipelines_1_first[75:70] } } }), + .checkForException_csrState({ x_decodeInfo_frm__h923668, + r1__read_BITS_13_TO_12___h923870 != 2'd0, - { prv__h707140, + { prv__h1011737, csrf_tvm_reg, - { r1__read_BIT_20___h649948, + { r1__read_BIT_20___h924376, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17480,2012 +17792,3606 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException(checkForException___d13458)); - module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242, + .checkForException_pcc(pc__h960508), + .checkForException_fourByteInst(fetchStage$pipelines_1_first[98:97] == + 2'b11), + .checkForException(checkForException___d21369)); + module_capChecks instance_capChecks_0(.capChecks_a(coreFix_memExe_regToExeQ$first[383:221]), + .capChecks_b(coreFix_memExe_regToExeQ$first[220:58]), + .capChecks_ddc({ csrf_ddc_reg, + repBound__h248675, + { csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125, + csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126, + csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4138 } }), + .capChecks_toCheck(coreFix_memExe_regToExeQ$first[57:12]), + .capChecks_cap_exact(1'h0), + .capChecks(capChecks___d4142)); + module_prepareBoundsCheck instance_prepareBoundsCheck_6(.prepareBoundsCheck_a(coreFix_memExe_regToExeQ$first[383:221]), + .prepareBoundsCheck_b(coreFix_memExe_regToExeQ$first[220:58]), + .prepareBoundsCheck_pcc(163'h400000000000000000003FFFC7FFFFD10000003F0), + .prepareBoundsCheck_ddc({ csrf_ddc_reg, + repBound__h248675, + { csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125, + csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126, + csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4138 } }), + .prepareBoundsCheck_vaddr(tmpAddr__h242768), + .prepareBoundsCheck_size(x__h249407 + + y__h249408), + .prepareBoundsCheck_toCheck(coreFix_memExe_regToExeQ$first[57:12]), + .prepareBoundsCheck(prepareBoundsCheck___d4226)); + module_execFpuSimple instance_execFpuSimple_3(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q278, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h478959), - .execFpuSimple_rVal2(rVal2__h478960), - .execFpuSimple(execFpuSimple___d11034)); - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20 = - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245 ? - _theResult___snd__h351474 : - _theResult____h343300 ; - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55 = - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 ? - _theResult___snd__h397164 : - _theResult____h388992 ; - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90 = - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 ? - _theResult___snd__h442852 : - _theResult____h434680 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889 ? - _theResult___snd__h508314 : - _theResult____h500015 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9599 ? - _theResult___snd__h586316 : - _theResult____h578017 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362 ? - _theResult___snd__h547115 : - _theResult____h538816 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100 = - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 ? - _theResult___snd__h460618 : - _theResult____h452317 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30 = - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796 ? - _theResult___snd__h369240 : - _theResult____h360939 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65 = - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 ? - _theResult___snd__h414930 : - _theResult____h406629 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105 = - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653 ? - _theResult___snd__h451434 : - _theResult___snd__h469224 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22 = - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 ? - _theResult___snd__h360056 : + .execFpuSimple_rVal1(rVal1__h714446), + .execFpuSimple_rVal2(rVal2__h714447), + .execFpuSimple(execFpuSimple___d15189)); + module_basicExec instance_basicExec_8(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[821:817], + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_816_ETC__q280, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_786_ETC__q281, + coreFix_aluExe_1_regToExeQ$first[775:729], + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q282, + coreFix_aluExe_1_regToExeQ$first[716], + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q283, + coreFix_aluExe_1_regToExeQ$first[710:678] }), + .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[632:470]), + .basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[469:307]), + .basicExec_pcc({ coreFix_aluExe_1_regToExeQ$first[306], + { cr_address__h865332, + cr_addrBits__h865333, + { coreFix_aluExe_1_regToExeQ$first[305:290], + { cr_flags__h865335, + cr_reserved__h865336 }, + INV_coreFix_aluExe_1_regToExeQ_first__7179_BIT_ETC___d17482 } }, + repBound__h865801, + { IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17489, + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17490, + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17502 } }), + .basicExec_ppc({ coreFix_aluExe_1_regToExeQ$first[177], + { cr_address__h865880, + cr_addrBits__h865881, + { coreFix_aluExe_1_regToExeQ$first[176:161], + { cr_flags__h865883, + cr_reserved__h865884 }, + INV_coreFix_aluExe_1_regToExeQ_first__7179_BIT_ETC___d17546 } }, + repBound__h866349, + { IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17553, + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17554, + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17566 } }), + .basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]), + .basicExec(basicExec___d17570)); + module_basicExec instance_basicExec_7(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[821:817], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_816_ETC__q285, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_786_ETC__q286, + coreFix_aluExe_0_regToExeQ$first[775:729], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q287, + coreFix_aluExe_0_regToExeQ$first[716], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q288, + coreFix_aluExe_0_regToExeQ$first[710:678] }), + .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[632:470]), + .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[469:307]), + .basicExec_pcc({ coreFix_aluExe_0_regToExeQ$first[306], + { cr_address__h903813, + cr_addrBits__h903814, + { coreFix_aluExe_0_regToExeQ$first[305:290], + { cr_flags__h903816, + cr_reserved__h903817 }, + INV_coreFix_aluExe_0_regToExeQ_first__9257_BIT_ETC___d19560 } }, + repBound__h904282, + { IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19567, + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19568, + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19580 } }), + .basicExec_ppc({ coreFix_aluExe_0_regToExeQ$first[177], + { cr_address__h904361, + cr_addrBits__h904362, + { coreFix_aluExe_0_regToExeQ$first[176:161], + { cr_flags__h904364, + cr_reserved__h904365 }, + INV_coreFix_aluExe_0_regToExeQ_first__9257_BIT_ETC___d19624 } }, + repBound__h904830, + { IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19631, + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19632, + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19644 } }), + .basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]), + .basicExec(basicExec___d19648)); + assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q109 = + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11148 ? + _theResult___snd__h676051 : + _theResult____h667879 ; + assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q39 = + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8354 ? + _theResult___snd__h584555 : + _theResult____h576381 ; + assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q74 = + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9751 ? + _theResult___snd__h630304 : + _theResult____h622132 ; + assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q149 = + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13030 ? + _theResult___snd__h743853 : + _theResult____h735554 ; + assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q166 = + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13745 ? + _theResult___snd__h822010 : + _theResult____h813711 ; + assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q189 = + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14515 ? + _theResult___snd__h782706 : + _theResult____h774407 ; + assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q119 = + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11699 ? + _theResult___snd__h693817 : + _theResult____h685516 ; + assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q49 = + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8905 ? + _theResult___snd__h602321 : + _theResult____h594020 ; + assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q84 = + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10302 ? + _theResult___snd__h648070 : + _theResult____h639769 ; + assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q145 = + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12718 ? + _theResult___snd__h734202 : 57'd0 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35 = - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869 ? - _theResult___snd__h360056 : - _theResult___snd__h377846 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57 = - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 ? - _theResult___snd__h405746 : + assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q152 = + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13080 ? + _theResult___snd__h734202 : + _theResult___snd__h752607 ; + assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q162 = + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13448 ? + _theResult___snd__h812359 : 57'd0 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70 = - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261 ? - _theResult___snd__h405746 : - _theResult___snd__h423536 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92 = - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 ? - _theResult___snd__h451434 : + assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q169 = + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13795 ? + _theResult___snd__h812359 : + _theResult___snd__h830764 ; + assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q185 = + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14218 ? + _theResult___snd__h773055 : 57'd0 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126 = - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577 ? - _theResult___snd__h498663 : + assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q192 = + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14565 ? + _theResult___snd__h773055 : + _theResult___snd__h791460 ; + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q111 = + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11379 ? + _theResult___snd__h684633 : 57'd0 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133 = - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8939 ? - _theResult___snd__h498663 : - _theResult___snd__h517068 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143 = - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9302 ? - _theResult___snd__h576665 : + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q124 = + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11772 ? + _theResult___snd__h684633 : + _theResult___snd__h702423 ; + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q41 = + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8585 ? + _theResult___snd__h593137 : 57'd0 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150 = - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9649 ? - _theResult___snd__h576665 : - _theResult___snd__h595070 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166 = - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065 ? - _theResult___snd__h537464 : + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q54 = + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8978 ? + _theResult___snd__h593137 : + _theResult___snd__h610927 ; + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q76 = + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9982 ? + _theResult___snd__h638886 : 57'd0 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173 = - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10412 ? - _theResult___snd__h537464 : - _theResult___snd__h555869 ; - assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h351411 == 8'd255) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050) : - ((_theResult___fst_exp__h360067 == 8'd255) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063) ; - assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h351411 == 8'd255) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106) : - ((_theResult___fst_exp__h360067 == 8'd255) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113) ; - assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397101 == 8'd255) ? + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q89 = + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10375 ? + _theResult___snd__h638886 : + _theResult___snd__h656676 ; + assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10571 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? + ((_theResult___fst_exp__h630241 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442) : - ((_theResult___fst_exp__h405757 == 8'd255) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556) : + ((_theResult___fst_exp__h638897 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455) ; - assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397101 == 8'd255) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569) ; + assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10621 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? + ((_theResult___fst_exp__h630241 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498) : - ((_theResult___fst_exp__h405757 == 8'd255) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612) : + ((_theResult___fst_exp__h638897 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505) ; - assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h442789 == 8'd255) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619) ; + assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d11968 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? + ((_theResult___fst_exp__h675988 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834) : - ((_theResult___fst_exp__h451445 == 8'd255) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953) : + ((_theResult___fst_exp__h684644 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847) ; - assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h442789 == 8'd255) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966) ; + assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12018 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? + ((_theResult___fst_exp__h675988 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890) : - ((_theResult___fst_exp__h451445 == 8'd255) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009) : + ((_theResult___fst_exp__h684644 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897) ; - assign IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10657 = - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 ? - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 ? - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10654) : - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; - assign IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9895 = - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 ? - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 ? - !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9892) : - !coreFix_fpuMulDivExe_0_regToExeQ$first[43] ; - assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 = - (_theResult____h343300[56] ? + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016) ; + assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9174 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? + ((_theResult___fst_exp__h584492 == 8'd255) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159) : + ((_theResult___fst_exp__h593148 == 8'd255) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172) ; + assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9224 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? + ((_theResult___fst_exp__h584492 == 8'd255) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215) : + ((_theResult___fst_exp__h593148 == 8'd255) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222) ; + assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146 = + (_theResult____h667879[56] ? 6'd0 : - (_theResult____h343300[55] ? + (_theResult____h667879[55] ? 6'd1 : - (_theResult____h343300[54] ? + (_theResult____h667879[54] ? 6'd2 : - (_theResult____h343300[53] ? + (_theResult____h667879[53] ? 6'd3 : - (_theResult____h343300[52] ? + (_theResult____h667879[52] ? 6'd4 : - (_theResult____h343300[51] ? + (_theResult____h667879[51] ? 6'd5 : - (_theResult____h343300[50] ? + (_theResult____h667879[50] ? 6'd6 : - (_theResult____h343300[49] ? + (_theResult____h667879[49] ? 6'd7 : - (_theResult____h343300[48] ? + (_theResult____h667879[48] ? 6'd8 : - (_theResult____h343300[47] ? + (_theResult____h667879[47] ? 6'd9 : - (_theResult____h343300[46] ? + (_theResult____h667879[46] ? 6'd10 : - (_theResult____h343300[45] ? + (_theResult____h667879[45] ? 6'd11 : - (_theResult____h343300[44] ? + (_theResult____h667879[44] ? 6'd12 : - (_theResult____h343300[43] ? + (_theResult____h667879[43] ? 6'd13 : - (_theResult____h343300[42] ? + (_theResult____h667879[42] ? 6'd14 : - (_theResult____h343300[41] ? + (_theResult____h667879[41] ? 6'd15 : - (_theResult____h343300[40] ? + (_theResult____h667879[40] ? 6'd16 : - (_theResult____h343300[39] ? + (_theResult____h667879[39] ? 6'd17 : - (_theResult____h343300[38] ? + (_theResult____h667879[38] ? 6'd18 : - (_theResult____h343300[37] ? + (_theResult____h667879[37] ? 6'd19 : - (_theResult____h343300[36] ? + (_theResult____h667879[36] ? 6'd20 : - (_theResult____h343300[35] ? + (_theResult____h667879[35] ? 6'd21 : - (_theResult____h343300[34] ? + (_theResult____h667879[34] ? 6'd22 : - (_theResult____h343300[33] ? + (_theResult____h667879[33] ? 6'd23 : - (_theResult____h343300[32] ? + (_theResult____h667879[32] ? 6'd24 : - (_theResult____h343300[31] ? + (_theResult____h667879[31] ? 6'd25 : - (_theResult____h343300[30] ? + (_theResult____h667879[30] ? 6'd26 : - (_theResult____h343300[29] ? + (_theResult____h667879[29] ? 6'd27 : - (_theResult____h343300[28] ? + (_theResult____h667879[28] ? 6'd28 : - (_theResult____h343300[27] ? + (_theResult____h667879[27] ? 6'd29 : - (_theResult____h343300[26] ? + (_theResult____h667879[26] ? 6'd30 : - (_theResult____h343300[25] ? + (_theResult____h667879[25] ? 6'd31 : - (_theResult____h343300[24] ? + (_theResult____h667879[24] ? 6'd32 : - (_theResult____h343300[23] ? + (_theResult____h667879[23] ? 6'd33 : - (_theResult____h343300[22] ? + (_theResult____h667879[22] ? 6'd34 : - (_theResult____h343300[21] ? + (_theResult____h667879[21] ? 6'd35 : - (_theResult____h343300[20] ? + (_theResult____h667879[20] ? 6'd36 : - (_theResult____h343300[19] ? + (_theResult____h667879[19] ? 6'd37 : - (_theResult____h343300[18] ? + (_theResult____h667879[18] ? 6'd38 : - (_theResult____h343300[17] ? + (_theResult____h667879[17] ? 6'd39 : - (_theResult____h343300[16] ? + (_theResult____h667879[16] ? 6'd40 : - (_theResult____h343300[15] ? + (_theResult____h667879[15] ? 6'd41 : - (_theResult____h343300[14] ? + (_theResult____h667879[14] ? 6'd42 : - (_theResult____h343300[13] ? + (_theResult____h667879[13] ? 6'd43 : - (_theResult____h343300[12] ? + (_theResult____h667879[12] ? 6'd44 : - (_theResult____h343300[11] ? + (_theResult____h667879[11] ? 6'd45 : - (_theResult____h343300[10] ? + (_theResult____h667879[10] ? 6'd46 : - (_theResult____h343300[9] ? + (_theResult____h667879[9] ? 6'd47 : - (_theResult____h343300[8] ? + (_theResult____h667879[8] ? 6'd48 : - (_theResult____h343300[7] ? + (_theResult____h667879[7] ? 6'd49 : - (_theResult____h343300[6] ? + (_theResult____h667879[6] ? 6'd50 : - (_theResult____h343300[5] ? + (_theResult____h667879[5] ? 6'd51 : - (_theResult____h343300[4] ? + (_theResult____h667879[4] ? 6'd52 : - (_theResult____h343300[3] ? + (_theResult____h667879[3] ? 6'd53 : - (_theResult____h343300[2] ? + (_theResult____h667879[2] ? 6'd54 : - (_theResult____h343300[1] ? + (_theResult____h667879[1] ? 6'd55 : - (_theResult____h343300[0] ? + (_theResult____h667879[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; - assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 = - (_theResult____h388992[56] ? + assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352 = + (_theResult____h576381[56] ? 6'd0 : - (_theResult____h388992[55] ? + (_theResult____h576381[55] ? 6'd1 : - (_theResult____h388992[54] ? + (_theResult____h576381[54] ? 6'd2 : - (_theResult____h388992[53] ? + (_theResult____h576381[53] ? 6'd3 : - (_theResult____h388992[52] ? + (_theResult____h576381[52] ? 6'd4 : - (_theResult____h388992[51] ? + (_theResult____h576381[51] ? 6'd5 : - (_theResult____h388992[50] ? + (_theResult____h576381[50] ? 6'd6 : - (_theResult____h388992[49] ? + (_theResult____h576381[49] ? 6'd7 : - (_theResult____h388992[48] ? + (_theResult____h576381[48] ? 6'd8 : - (_theResult____h388992[47] ? + (_theResult____h576381[47] ? 6'd9 : - (_theResult____h388992[46] ? + (_theResult____h576381[46] ? 6'd10 : - (_theResult____h388992[45] ? + (_theResult____h576381[45] ? 6'd11 : - (_theResult____h388992[44] ? + (_theResult____h576381[44] ? 6'd12 : - (_theResult____h388992[43] ? + (_theResult____h576381[43] ? 6'd13 : - (_theResult____h388992[42] ? + (_theResult____h576381[42] ? 6'd14 : - (_theResult____h388992[41] ? + (_theResult____h576381[41] ? 6'd15 : - (_theResult____h388992[40] ? + (_theResult____h576381[40] ? 6'd16 : - (_theResult____h388992[39] ? + (_theResult____h576381[39] ? 6'd17 : - (_theResult____h388992[38] ? + (_theResult____h576381[38] ? 6'd18 : - (_theResult____h388992[37] ? + (_theResult____h576381[37] ? 6'd19 : - (_theResult____h388992[36] ? + (_theResult____h576381[36] ? 6'd20 : - (_theResult____h388992[35] ? + (_theResult____h576381[35] ? 6'd21 : - (_theResult____h388992[34] ? + (_theResult____h576381[34] ? 6'd22 : - (_theResult____h388992[33] ? + (_theResult____h576381[33] ? 6'd23 : - (_theResult____h388992[32] ? + (_theResult____h576381[32] ? 6'd24 : - (_theResult____h388992[31] ? + (_theResult____h576381[31] ? 6'd25 : - (_theResult____h388992[30] ? + (_theResult____h576381[30] ? 6'd26 : - (_theResult____h388992[29] ? + (_theResult____h576381[29] ? 6'd27 : - (_theResult____h388992[28] ? + (_theResult____h576381[28] ? 6'd28 : - (_theResult____h388992[27] ? + (_theResult____h576381[27] ? 6'd29 : - (_theResult____h388992[26] ? + (_theResult____h576381[26] ? 6'd30 : - (_theResult____h388992[25] ? + (_theResult____h576381[25] ? 6'd31 : - (_theResult____h388992[24] ? + (_theResult____h576381[24] ? 6'd32 : - (_theResult____h388992[23] ? + (_theResult____h576381[23] ? 6'd33 : - (_theResult____h388992[22] ? + (_theResult____h576381[22] ? 6'd34 : - (_theResult____h388992[21] ? + (_theResult____h576381[21] ? 6'd35 : - (_theResult____h388992[20] ? + (_theResult____h576381[20] ? 6'd36 : - (_theResult____h388992[19] ? + (_theResult____h576381[19] ? 6'd37 : - (_theResult____h388992[18] ? + (_theResult____h576381[18] ? 6'd38 : - (_theResult____h388992[17] ? + (_theResult____h576381[17] ? 6'd39 : - (_theResult____h388992[16] ? + (_theResult____h576381[16] ? 6'd40 : - (_theResult____h388992[15] ? + (_theResult____h576381[15] ? 6'd41 : - (_theResult____h388992[14] ? + (_theResult____h576381[14] ? 6'd42 : - (_theResult____h388992[13] ? + (_theResult____h576381[13] ? 6'd43 : - (_theResult____h388992[12] ? + (_theResult____h576381[12] ? 6'd44 : - (_theResult____h388992[11] ? + (_theResult____h576381[11] ? 6'd45 : - (_theResult____h388992[10] ? + (_theResult____h576381[10] ? 6'd46 : - (_theResult____h388992[9] ? + (_theResult____h576381[9] ? 6'd47 : - (_theResult____h388992[8] ? + (_theResult____h576381[8] ? 6'd48 : - (_theResult____h388992[7] ? + (_theResult____h576381[7] ? 6'd49 : - (_theResult____h388992[6] ? + (_theResult____h576381[6] ? 6'd50 : - (_theResult____h388992[5] ? + (_theResult____h576381[5] ? 6'd51 : - (_theResult____h388992[4] ? + (_theResult____h576381[4] ? 6'd52 : - (_theResult____h388992[3] ? + (_theResult____h576381[3] ? 6'd53 : - (_theResult____h388992[2] ? + (_theResult____h576381[2] ? 6'd54 : - (_theResult____h388992[1] ? + (_theResult____h576381[1] ? 6'd55 : - (_theResult____h388992[0] ? + (_theResult____h576381[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; - assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 = - (_theResult____h434680[56] ? + assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749 = + (_theResult____h622132[56] ? 6'd0 : - (_theResult____h434680[55] ? + (_theResult____h622132[55] ? 6'd1 : - (_theResult____h434680[54] ? + (_theResult____h622132[54] ? 6'd2 : - (_theResult____h434680[53] ? + (_theResult____h622132[53] ? 6'd3 : - (_theResult____h434680[52] ? + (_theResult____h622132[52] ? 6'd4 : - (_theResult____h434680[51] ? + (_theResult____h622132[51] ? 6'd5 : - (_theResult____h434680[50] ? + (_theResult____h622132[50] ? 6'd6 : - (_theResult____h434680[49] ? + (_theResult____h622132[49] ? 6'd7 : - (_theResult____h434680[48] ? + (_theResult____h622132[48] ? 6'd8 : - (_theResult____h434680[47] ? + (_theResult____h622132[47] ? 6'd9 : - (_theResult____h434680[46] ? + (_theResult____h622132[46] ? 6'd10 : - (_theResult____h434680[45] ? + (_theResult____h622132[45] ? 6'd11 : - (_theResult____h434680[44] ? + (_theResult____h622132[44] ? 6'd12 : - (_theResult____h434680[43] ? + (_theResult____h622132[43] ? 6'd13 : - (_theResult____h434680[42] ? + (_theResult____h622132[42] ? 6'd14 : - (_theResult____h434680[41] ? + (_theResult____h622132[41] ? 6'd15 : - (_theResult____h434680[40] ? + (_theResult____h622132[40] ? 6'd16 : - (_theResult____h434680[39] ? + (_theResult____h622132[39] ? 6'd17 : - (_theResult____h434680[38] ? + (_theResult____h622132[38] ? 6'd18 : - (_theResult____h434680[37] ? + (_theResult____h622132[37] ? 6'd19 : - (_theResult____h434680[36] ? + (_theResult____h622132[36] ? 6'd20 : - (_theResult____h434680[35] ? + (_theResult____h622132[35] ? 6'd21 : - (_theResult____h434680[34] ? + (_theResult____h622132[34] ? 6'd22 : - (_theResult____h434680[33] ? + (_theResult____h622132[33] ? 6'd23 : - (_theResult____h434680[32] ? + (_theResult____h622132[32] ? 6'd24 : - (_theResult____h434680[31] ? + (_theResult____h622132[31] ? 6'd25 : - (_theResult____h434680[30] ? + (_theResult____h622132[30] ? 6'd26 : - (_theResult____h434680[29] ? + (_theResult____h622132[29] ? 6'd27 : - (_theResult____h434680[28] ? + (_theResult____h622132[28] ? 6'd28 : - (_theResult____h434680[27] ? + (_theResult____h622132[27] ? 6'd29 : - (_theResult____h434680[26] ? + (_theResult____h622132[26] ? 6'd30 : - (_theResult____h434680[25] ? + (_theResult____h622132[25] ? 6'd31 : - (_theResult____h434680[24] ? + (_theResult____h622132[24] ? 6'd32 : - (_theResult____h434680[23] ? + (_theResult____h622132[23] ? 6'd33 : - (_theResult____h434680[22] ? + (_theResult____h622132[22] ? 6'd34 : - (_theResult____h434680[21] ? + (_theResult____h622132[21] ? 6'd35 : - (_theResult____h434680[20] ? + (_theResult____h622132[20] ? 6'd36 : - (_theResult____h434680[19] ? + (_theResult____h622132[19] ? 6'd37 : - (_theResult____h434680[18] ? + (_theResult____h622132[18] ? 6'd38 : - (_theResult____h434680[17] ? + (_theResult____h622132[17] ? 6'd39 : - (_theResult____h434680[16] ? + (_theResult____h622132[16] ? 6'd40 : - (_theResult____h434680[15] ? + (_theResult____h622132[15] ? 6'd41 : - (_theResult____h434680[14] ? + (_theResult____h622132[14] ? 6'd42 : - (_theResult____h434680[13] ? + (_theResult____h622132[13] ? 6'd43 : - (_theResult____h434680[12] ? + (_theResult____h622132[12] ? 6'd44 : - (_theResult____h434680[11] ? + (_theResult____h622132[11] ? 6'd45 : - (_theResult____h434680[10] ? + (_theResult____h622132[10] ? 6'd46 : - (_theResult____h434680[9] ? + (_theResult____h622132[9] ? 6'd47 : - (_theResult____h434680[8] ? + (_theResult____h622132[8] ? 6'd48 : - (_theResult____h434680[7] ? + (_theResult____h622132[7] ? 6'd49 : - (_theResult____h434680[6] ? + (_theResult____h622132[6] ? 6'd50 : - (_theResult____h434680[5] ? + (_theResult____h622132[5] ? 6'd51 : - (_theResult____h434680[4] ? + (_theResult____h622132[4] ? 6'd52 : - (_theResult____h434680[3] ? + (_theResult____h622132[3] ? 6'd53 : - (_theResult____h434680[2] ? + (_theResult____h622132[2] ? 6'd54 : - (_theResult____h434680[1] ? + (_theResult____h622132[1] ? 6'd55 : - (_theResult____h434680[0] ? + (_theResult____h622132[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 = - (_theResult____h538816[56] ? + assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13028 = + (_theResult____h735554[56] ? 6'd0 : - (_theResult____h538816[55] ? + (_theResult____h735554[55] ? 6'd1 : - (_theResult____h538816[54] ? + (_theResult____h735554[54] ? 6'd2 : - (_theResult____h538816[53] ? + (_theResult____h735554[53] ? 6'd3 : - (_theResult____h538816[52] ? + (_theResult____h735554[52] ? 6'd4 : - (_theResult____h538816[51] ? + (_theResult____h735554[51] ? 6'd5 : - (_theResult____h538816[50] ? + (_theResult____h735554[50] ? 6'd6 : - (_theResult____h538816[49] ? + (_theResult____h735554[49] ? 6'd7 : - (_theResult____h538816[48] ? + (_theResult____h735554[48] ? 6'd8 : - (_theResult____h538816[47] ? + (_theResult____h735554[47] ? 6'd9 : - (_theResult____h538816[46] ? + (_theResult____h735554[46] ? 6'd10 : - (_theResult____h538816[45] ? + (_theResult____h735554[45] ? 6'd11 : - (_theResult____h538816[44] ? + (_theResult____h735554[44] ? 6'd12 : - (_theResult____h538816[43] ? + (_theResult____h735554[43] ? 6'd13 : - (_theResult____h538816[42] ? + (_theResult____h735554[42] ? 6'd14 : - (_theResult____h538816[41] ? + (_theResult____h735554[41] ? 6'd15 : - (_theResult____h538816[40] ? + (_theResult____h735554[40] ? 6'd16 : - (_theResult____h538816[39] ? + (_theResult____h735554[39] ? 6'd17 : - (_theResult____h538816[38] ? + (_theResult____h735554[38] ? 6'd18 : - (_theResult____h538816[37] ? + (_theResult____h735554[37] ? 6'd19 : - (_theResult____h538816[36] ? + (_theResult____h735554[36] ? 6'd20 : - (_theResult____h538816[35] ? + (_theResult____h735554[35] ? 6'd21 : - (_theResult____h538816[34] ? + (_theResult____h735554[34] ? 6'd22 : - (_theResult____h538816[33] ? + (_theResult____h735554[33] ? 6'd23 : - (_theResult____h538816[32] ? + (_theResult____h735554[32] ? 6'd24 : - (_theResult____h538816[31] ? + (_theResult____h735554[31] ? 6'd25 : - (_theResult____h538816[30] ? + (_theResult____h735554[30] ? 6'd26 : - (_theResult____h538816[29] ? + (_theResult____h735554[29] ? 6'd27 : - (_theResult____h538816[28] ? + (_theResult____h735554[28] ? 6'd28 : - (_theResult____h538816[27] ? + (_theResult____h735554[27] ? 6'd29 : - (_theResult____h538816[26] ? + (_theResult____h735554[26] ? 6'd30 : - (_theResult____h538816[25] ? + (_theResult____h735554[25] ? 6'd31 : - (_theResult____h538816[24] ? + (_theResult____h735554[24] ? 6'd32 : - (_theResult____h538816[23] ? + (_theResult____h735554[23] ? 6'd33 : - (_theResult____h538816[22] ? + (_theResult____h735554[22] ? 6'd34 : - (_theResult____h538816[21] ? + (_theResult____h735554[21] ? 6'd35 : - (_theResult____h538816[20] ? + (_theResult____h735554[20] ? 6'd36 : - (_theResult____h538816[19] ? + (_theResult____h735554[19] ? 6'd37 : - (_theResult____h538816[18] ? + (_theResult____h735554[18] ? 6'd38 : - (_theResult____h538816[17] ? + (_theResult____h735554[17] ? 6'd39 : - (_theResult____h538816[16] ? + (_theResult____h735554[16] ? 6'd40 : - (_theResult____h538816[15] ? + (_theResult____h735554[15] ? 6'd41 : - (_theResult____h538816[14] ? + (_theResult____h735554[14] ? 6'd42 : - (_theResult____h538816[13] ? + (_theResult____h735554[13] ? 6'd43 : - (_theResult____h538816[12] ? + (_theResult____h735554[12] ? 6'd44 : - (_theResult____h538816[11] ? + (_theResult____h735554[11] ? 6'd45 : - (_theResult____h538816[10] ? + (_theResult____h735554[10] ? 6'd46 : - (_theResult____h538816[9] ? + (_theResult____h735554[9] ? 6'd47 : - (_theResult____h538816[8] ? + (_theResult____h735554[8] ? 6'd48 : - (_theResult____h538816[7] ? + (_theResult____h735554[7] ? 6'd49 : - (_theResult____h538816[6] ? + (_theResult____h735554[6] ? 6'd50 : - (_theResult____h538816[5] ? + (_theResult____h735554[5] ? 6'd51 : - (_theResult____h538816[4] ? + (_theResult____h735554[4] ? 6'd52 : - (_theResult____h538816[3] ? + (_theResult____h735554[3] ? 6'd53 : - (_theResult____h538816[2] ? + (_theResult____h735554[2] ? 6'd54 : - (_theResult____h538816[1] ? + (_theResult____h735554[1] ? 6'd55 : - (_theResult____h538816[0] ? + (_theResult____h735554[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 = - (_theResult____h500015[56] ? + assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13743 = + (_theResult____h813711[56] ? 6'd0 : - (_theResult____h500015[55] ? + (_theResult____h813711[55] ? 6'd1 : - (_theResult____h500015[54] ? + (_theResult____h813711[54] ? 6'd2 : - (_theResult____h500015[53] ? + (_theResult____h813711[53] ? 6'd3 : - (_theResult____h500015[52] ? + (_theResult____h813711[52] ? 6'd4 : - (_theResult____h500015[51] ? + (_theResult____h813711[51] ? 6'd5 : - (_theResult____h500015[50] ? + (_theResult____h813711[50] ? 6'd6 : - (_theResult____h500015[49] ? + (_theResult____h813711[49] ? 6'd7 : - (_theResult____h500015[48] ? + (_theResult____h813711[48] ? 6'd8 : - (_theResult____h500015[47] ? + (_theResult____h813711[47] ? 6'd9 : - (_theResult____h500015[46] ? + (_theResult____h813711[46] ? 6'd10 : - (_theResult____h500015[45] ? + (_theResult____h813711[45] ? 6'd11 : - (_theResult____h500015[44] ? + (_theResult____h813711[44] ? 6'd12 : - (_theResult____h500015[43] ? + (_theResult____h813711[43] ? 6'd13 : - (_theResult____h500015[42] ? + (_theResult____h813711[42] ? 6'd14 : - (_theResult____h500015[41] ? + (_theResult____h813711[41] ? 6'd15 : - (_theResult____h500015[40] ? + (_theResult____h813711[40] ? 6'd16 : - (_theResult____h500015[39] ? + (_theResult____h813711[39] ? 6'd17 : - (_theResult____h500015[38] ? + (_theResult____h813711[38] ? 6'd18 : - (_theResult____h500015[37] ? + (_theResult____h813711[37] ? 6'd19 : - (_theResult____h500015[36] ? + (_theResult____h813711[36] ? 6'd20 : - (_theResult____h500015[35] ? + (_theResult____h813711[35] ? 6'd21 : - (_theResult____h500015[34] ? + (_theResult____h813711[34] ? 6'd22 : - (_theResult____h500015[33] ? + (_theResult____h813711[33] ? 6'd23 : - (_theResult____h500015[32] ? + (_theResult____h813711[32] ? 6'd24 : - (_theResult____h500015[31] ? + (_theResult____h813711[31] ? 6'd25 : - (_theResult____h500015[30] ? + (_theResult____h813711[30] ? 6'd26 : - (_theResult____h500015[29] ? + (_theResult____h813711[29] ? 6'd27 : - (_theResult____h500015[28] ? + (_theResult____h813711[28] ? 6'd28 : - (_theResult____h500015[27] ? + (_theResult____h813711[27] ? 6'd29 : - (_theResult____h500015[26] ? + (_theResult____h813711[26] ? 6'd30 : - (_theResult____h500015[25] ? + (_theResult____h813711[25] ? 6'd31 : - (_theResult____h500015[24] ? + (_theResult____h813711[24] ? 6'd32 : - (_theResult____h500015[23] ? + (_theResult____h813711[23] ? 6'd33 : - (_theResult____h500015[22] ? + (_theResult____h813711[22] ? 6'd34 : - (_theResult____h500015[21] ? + (_theResult____h813711[21] ? 6'd35 : - (_theResult____h500015[20] ? + (_theResult____h813711[20] ? 6'd36 : - (_theResult____h500015[19] ? + (_theResult____h813711[19] ? 6'd37 : - (_theResult____h500015[18] ? + (_theResult____h813711[18] ? 6'd38 : - (_theResult____h500015[17] ? + (_theResult____h813711[17] ? 6'd39 : - (_theResult____h500015[16] ? + (_theResult____h813711[16] ? 6'd40 : - (_theResult____h500015[15] ? + (_theResult____h813711[15] ? 6'd41 : - (_theResult____h500015[14] ? + (_theResult____h813711[14] ? 6'd42 : - (_theResult____h500015[13] ? + (_theResult____h813711[13] ? 6'd43 : - (_theResult____h500015[12] ? + (_theResult____h813711[12] ? 6'd44 : - (_theResult____h500015[11] ? + (_theResult____h813711[11] ? 6'd45 : - (_theResult____h500015[10] ? + (_theResult____h813711[10] ? 6'd46 : - (_theResult____h500015[9] ? + (_theResult____h813711[9] ? 6'd47 : - (_theResult____h500015[8] ? + (_theResult____h813711[8] ? 6'd48 : - (_theResult____h500015[7] ? + (_theResult____h813711[7] ? 6'd49 : - (_theResult____h500015[6] ? + (_theResult____h813711[6] ? 6'd50 : - (_theResult____h500015[5] ? + (_theResult____h813711[5] ? 6'd51 : - (_theResult____h500015[4] ? + (_theResult____h813711[4] ? 6'd52 : - (_theResult____h500015[3] ? + (_theResult____h813711[3] ? 6'd53 : - (_theResult____h500015[2] ? + (_theResult____h813711[2] ? 6'd54 : - (_theResult____h500015[1] ? + (_theResult____h813711[1] ? 6'd55 : - (_theResult____h500015[0] ? + (_theResult____h813711[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 = - (_theResult____h578017[56] ? + assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14513 = + (_theResult____h774407[56] ? 6'd0 : - (_theResult____h578017[55] ? + (_theResult____h774407[55] ? 6'd1 : - (_theResult____h578017[54] ? + (_theResult____h774407[54] ? 6'd2 : - (_theResult____h578017[53] ? + (_theResult____h774407[53] ? 6'd3 : - (_theResult____h578017[52] ? + (_theResult____h774407[52] ? 6'd4 : - (_theResult____h578017[51] ? + (_theResult____h774407[51] ? 6'd5 : - (_theResult____h578017[50] ? + (_theResult____h774407[50] ? 6'd6 : - (_theResult____h578017[49] ? + (_theResult____h774407[49] ? 6'd7 : - (_theResult____h578017[48] ? + (_theResult____h774407[48] ? 6'd8 : - (_theResult____h578017[47] ? + (_theResult____h774407[47] ? 6'd9 : - (_theResult____h578017[46] ? + (_theResult____h774407[46] ? 6'd10 : - (_theResult____h578017[45] ? + (_theResult____h774407[45] ? 6'd11 : - (_theResult____h578017[44] ? + (_theResult____h774407[44] ? 6'd12 : - (_theResult____h578017[43] ? + (_theResult____h774407[43] ? 6'd13 : - (_theResult____h578017[42] ? + (_theResult____h774407[42] ? 6'd14 : - (_theResult____h578017[41] ? + (_theResult____h774407[41] ? 6'd15 : - (_theResult____h578017[40] ? + (_theResult____h774407[40] ? 6'd16 : - (_theResult____h578017[39] ? + (_theResult____h774407[39] ? 6'd17 : - (_theResult____h578017[38] ? + (_theResult____h774407[38] ? 6'd18 : - (_theResult____h578017[37] ? + (_theResult____h774407[37] ? 6'd19 : - (_theResult____h578017[36] ? + (_theResult____h774407[36] ? 6'd20 : - (_theResult____h578017[35] ? + (_theResult____h774407[35] ? 6'd21 : - (_theResult____h578017[34] ? + (_theResult____h774407[34] ? 6'd22 : - (_theResult____h578017[33] ? + (_theResult____h774407[33] ? 6'd23 : - (_theResult____h578017[32] ? + (_theResult____h774407[32] ? 6'd24 : - (_theResult____h578017[31] ? + (_theResult____h774407[31] ? 6'd25 : - (_theResult____h578017[30] ? + (_theResult____h774407[30] ? 6'd26 : - (_theResult____h578017[29] ? + (_theResult____h774407[29] ? 6'd27 : - (_theResult____h578017[28] ? + (_theResult____h774407[28] ? 6'd28 : - (_theResult____h578017[27] ? + (_theResult____h774407[27] ? 6'd29 : - (_theResult____h578017[26] ? + (_theResult____h774407[26] ? 6'd30 : - (_theResult____h578017[25] ? + (_theResult____h774407[25] ? 6'd31 : - (_theResult____h578017[24] ? + (_theResult____h774407[24] ? 6'd32 : - (_theResult____h578017[23] ? + (_theResult____h774407[23] ? 6'd33 : - (_theResult____h578017[22] ? + (_theResult____h774407[22] ? 6'd34 : - (_theResult____h578017[21] ? + (_theResult____h774407[21] ? 6'd35 : - (_theResult____h578017[20] ? + (_theResult____h774407[20] ? 6'd36 : - (_theResult____h578017[19] ? + (_theResult____h774407[19] ? 6'd37 : - (_theResult____h578017[18] ? + (_theResult____h774407[18] ? 6'd38 : - (_theResult____h578017[17] ? + (_theResult____h774407[17] ? 6'd39 : - (_theResult____h578017[16] ? + (_theResult____h774407[16] ? 6'd40 : - (_theResult____h578017[15] ? + (_theResult____h774407[15] ? 6'd41 : - (_theResult____h578017[14] ? + (_theResult____h774407[14] ? 6'd42 : - (_theResult____h578017[13] ? + (_theResult____h774407[13] ? 6'd43 : - (_theResult____h578017[12] ? + (_theResult____h774407[12] ? 6'd44 : - (_theResult____h578017[11] ? + (_theResult____h774407[11] ? 6'd45 : - (_theResult____h578017[10] ? + (_theResult____h774407[10] ? 6'd46 : - (_theResult____h578017[9] ? + (_theResult____h774407[9] ? 6'd47 : - (_theResult____h578017[8] ? + (_theResult____h774407[8] ? 6'd48 : - (_theResult____h578017[7] ? + (_theResult____h774407[7] ? 6'd49 : - (_theResult____h578017[6] ? + (_theResult____h774407[6] ? 6'd50 : - (_theResult____h578017[5] ? + (_theResult____h774407[5] ? 6'd51 : - (_theResult____h578017[4] ? + (_theResult____h774407[4] ? 6'd52 : - (_theResult____h578017[3] ? + (_theResult____h774407[3] ? 6'd53 : - (_theResult____h578017[2] ? + (_theResult____h774407[2] ? 6'd54 : - (_theResult____h578017[1] ? + (_theResult____h774407[1] ? 6'd55 : - (_theResult____h578017[0] ? + (_theResult____h774407[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; - assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 = - (_theResult____h360939[56] ? + assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10300 = + (_theResult____h639769[56] ? 6'd0 : - (_theResult____h360939[55] ? + (_theResult____h639769[55] ? 6'd1 : - (_theResult____h360939[54] ? + (_theResult____h639769[54] ? 6'd2 : - (_theResult____h360939[53] ? + (_theResult____h639769[53] ? 6'd3 : - (_theResult____h360939[52] ? + (_theResult____h639769[52] ? 6'd4 : - (_theResult____h360939[51] ? + (_theResult____h639769[51] ? 6'd5 : - (_theResult____h360939[50] ? + (_theResult____h639769[50] ? 6'd6 : - (_theResult____h360939[49] ? + (_theResult____h639769[49] ? 6'd7 : - (_theResult____h360939[48] ? + (_theResult____h639769[48] ? 6'd8 : - (_theResult____h360939[47] ? + (_theResult____h639769[47] ? 6'd9 : - (_theResult____h360939[46] ? + (_theResult____h639769[46] ? 6'd10 : - (_theResult____h360939[45] ? + (_theResult____h639769[45] ? 6'd11 : - (_theResult____h360939[44] ? + (_theResult____h639769[44] ? 6'd12 : - (_theResult____h360939[43] ? + (_theResult____h639769[43] ? 6'd13 : - (_theResult____h360939[42] ? + (_theResult____h639769[42] ? 6'd14 : - (_theResult____h360939[41] ? + (_theResult____h639769[41] ? 6'd15 : - (_theResult____h360939[40] ? + (_theResult____h639769[40] ? 6'd16 : - (_theResult____h360939[39] ? + (_theResult____h639769[39] ? 6'd17 : - (_theResult____h360939[38] ? + (_theResult____h639769[38] ? 6'd18 : - (_theResult____h360939[37] ? + (_theResult____h639769[37] ? 6'd19 : - (_theResult____h360939[36] ? + (_theResult____h639769[36] ? 6'd20 : - (_theResult____h360939[35] ? + (_theResult____h639769[35] ? 6'd21 : - (_theResult____h360939[34] ? + (_theResult____h639769[34] ? 6'd22 : - (_theResult____h360939[33] ? + (_theResult____h639769[33] ? 6'd23 : - (_theResult____h360939[32] ? + (_theResult____h639769[32] ? 6'd24 : - (_theResult____h360939[31] ? + (_theResult____h639769[31] ? 6'd25 : - (_theResult____h360939[30] ? + (_theResult____h639769[30] ? 6'd26 : - (_theResult____h360939[29] ? + (_theResult____h639769[29] ? 6'd27 : - (_theResult____h360939[28] ? + (_theResult____h639769[28] ? 6'd28 : - (_theResult____h360939[27] ? + (_theResult____h639769[27] ? 6'd29 : - (_theResult____h360939[26] ? + (_theResult____h639769[26] ? 6'd30 : - (_theResult____h360939[25] ? + (_theResult____h639769[25] ? 6'd31 : - (_theResult____h360939[24] ? + (_theResult____h639769[24] ? 6'd32 : - (_theResult____h360939[23] ? + (_theResult____h639769[23] ? 6'd33 : - (_theResult____h360939[22] ? + (_theResult____h639769[22] ? 6'd34 : - (_theResult____h360939[21] ? + (_theResult____h639769[21] ? 6'd35 : - (_theResult____h360939[20] ? + (_theResult____h639769[20] ? 6'd36 : - (_theResult____h360939[19] ? + (_theResult____h639769[19] ? 6'd37 : - (_theResult____h360939[18] ? + (_theResult____h639769[18] ? 6'd38 : - (_theResult____h360939[17] ? + (_theResult____h639769[17] ? 6'd39 : - (_theResult____h360939[16] ? + (_theResult____h639769[16] ? 6'd40 : - (_theResult____h360939[15] ? + (_theResult____h639769[15] ? 6'd41 : - (_theResult____h360939[14] ? + (_theResult____h639769[14] ? 6'd42 : - (_theResult____h360939[13] ? + (_theResult____h639769[13] ? 6'd43 : - (_theResult____h360939[12] ? + (_theResult____h639769[12] ? 6'd44 : - (_theResult____h360939[11] ? + (_theResult____h639769[11] ? 6'd45 : - (_theResult____h360939[10] ? + (_theResult____h639769[10] ? 6'd46 : - (_theResult____h360939[9] ? + (_theResult____h639769[9] ? 6'd47 : - (_theResult____h360939[8] ? + (_theResult____h639769[8] ? 6'd48 : - (_theResult____h360939[7] ? + (_theResult____h639769[7] ? 6'd49 : - (_theResult____h360939[6] ? + (_theResult____h639769[6] ? 6'd50 : - (_theResult____h360939[5] ? + (_theResult____h639769[5] ? 6'd51 : - (_theResult____h360939[4] ? + (_theResult____h639769[4] ? 6'd52 : - (_theResult____h360939[3] ? + (_theResult____h639769[3] ? 6'd53 : - (_theResult____h360939[2] ? + (_theResult____h639769[2] ? 6'd54 : - (_theResult____h360939[1] ? + (_theResult____h639769[1] ? 6'd55 : - (_theResult____h360939[0] ? + (_theResult____h639769[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; - assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 = - (_theResult____h406629[56] ? + assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11697 = + (_theResult____h685516[56] ? 6'd0 : - (_theResult____h406629[55] ? + (_theResult____h685516[55] ? 6'd1 : - (_theResult____h406629[54] ? + (_theResult____h685516[54] ? 6'd2 : - (_theResult____h406629[53] ? + (_theResult____h685516[53] ? 6'd3 : - (_theResult____h406629[52] ? + (_theResult____h685516[52] ? 6'd4 : - (_theResult____h406629[51] ? + (_theResult____h685516[51] ? 6'd5 : - (_theResult____h406629[50] ? + (_theResult____h685516[50] ? 6'd6 : - (_theResult____h406629[49] ? + (_theResult____h685516[49] ? 6'd7 : - (_theResult____h406629[48] ? + (_theResult____h685516[48] ? 6'd8 : - (_theResult____h406629[47] ? + (_theResult____h685516[47] ? 6'd9 : - (_theResult____h406629[46] ? + (_theResult____h685516[46] ? 6'd10 : - (_theResult____h406629[45] ? + (_theResult____h685516[45] ? 6'd11 : - (_theResult____h406629[44] ? + (_theResult____h685516[44] ? 6'd12 : - (_theResult____h406629[43] ? + (_theResult____h685516[43] ? 6'd13 : - (_theResult____h406629[42] ? + (_theResult____h685516[42] ? 6'd14 : - (_theResult____h406629[41] ? + (_theResult____h685516[41] ? 6'd15 : - (_theResult____h406629[40] ? + (_theResult____h685516[40] ? 6'd16 : - (_theResult____h406629[39] ? + (_theResult____h685516[39] ? 6'd17 : - (_theResult____h406629[38] ? + (_theResult____h685516[38] ? 6'd18 : - (_theResult____h406629[37] ? + (_theResult____h685516[37] ? 6'd19 : - (_theResult____h406629[36] ? + (_theResult____h685516[36] ? 6'd20 : - (_theResult____h406629[35] ? + (_theResult____h685516[35] ? 6'd21 : - (_theResult____h406629[34] ? + (_theResult____h685516[34] ? 6'd22 : - (_theResult____h406629[33] ? + (_theResult____h685516[33] ? 6'd23 : - (_theResult____h406629[32] ? + (_theResult____h685516[32] ? 6'd24 : - (_theResult____h406629[31] ? + (_theResult____h685516[31] ? 6'd25 : - (_theResult____h406629[30] ? + (_theResult____h685516[30] ? 6'd26 : - (_theResult____h406629[29] ? + (_theResult____h685516[29] ? 6'd27 : - (_theResult____h406629[28] ? + (_theResult____h685516[28] ? 6'd28 : - (_theResult____h406629[27] ? + (_theResult____h685516[27] ? 6'd29 : - (_theResult____h406629[26] ? + (_theResult____h685516[26] ? 6'd30 : - (_theResult____h406629[25] ? + (_theResult____h685516[25] ? 6'd31 : - (_theResult____h406629[24] ? + (_theResult____h685516[24] ? 6'd32 : - (_theResult____h406629[23] ? + (_theResult____h685516[23] ? 6'd33 : - (_theResult____h406629[22] ? + (_theResult____h685516[22] ? 6'd34 : - (_theResult____h406629[21] ? + (_theResult____h685516[21] ? 6'd35 : - (_theResult____h406629[20] ? + (_theResult____h685516[20] ? 6'd36 : - (_theResult____h406629[19] ? + (_theResult____h685516[19] ? 6'd37 : - (_theResult____h406629[18] ? + (_theResult____h685516[18] ? 6'd38 : - (_theResult____h406629[17] ? + (_theResult____h685516[17] ? 6'd39 : - (_theResult____h406629[16] ? + (_theResult____h685516[16] ? 6'd40 : - (_theResult____h406629[15] ? + (_theResult____h685516[15] ? 6'd41 : - (_theResult____h406629[14] ? + (_theResult____h685516[14] ? 6'd42 : - (_theResult____h406629[13] ? + (_theResult____h685516[13] ? 6'd43 : - (_theResult____h406629[12] ? + (_theResult____h685516[12] ? 6'd44 : - (_theResult____h406629[11] ? + (_theResult____h685516[11] ? 6'd45 : - (_theResult____h406629[10] ? + (_theResult____h685516[10] ? 6'd46 : - (_theResult____h406629[9] ? + (_theResult____h685516[9] ? 6'd47 : - (_theResult____h406629[8] ? + (_theResult____h685516[8] ? 6'd48 : - (_theResult____h406629[7] ? + (_theResult____h685516[7] ? 6'd49 : - (_theResult____h406629[6] ? + (_theResult____h685516[6] ? 6'd50 : - (_theResult____h406629[5] ? + (_theResult____h685516[5] ? 6'd51 : - (_theResult____h406629[4] ? + (_theResult____h685516[4] ? 6'd52 : - (_theResult____h406629[3] ? + (_theResult____h685516[3] ? 6'd53 : - (_theResult____h406629[2] ? + (_theResult____h685516[2] ? 6'd54 : - (_theResult____h406629[1] ? + (_theResult____h685516[1] ? 6'd55 : - (_theResult____h406629[0] ? + (_theResult____h685516[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; - assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 = - (_theResult____h452317[56] ? + assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8903 = + (_theResult____h594020[56] ? 6'd0 : - (_theResult____h452317[55] ? + (_theResult____h594020[55] ? 6'd1 : - (_theResult____h452317[54] ? + (_theResult____h594020[54] ? 6'd2 : - (_theResult____h452317[53] ? + (_theResult____h594020[53] ? 6'd3 : - (_theResult____h452317[52] ? + (_theResult____h594020[52] ? 6'd4 : - (_theResult____h452317[51] ? + (_theResult____h594020[51] ? 6'd5 : - (_theResult____h452317[50] ? + (_theResult____h594020[50] ? 6'd6 : - (_theResult____h452317[49] ? + (_theResult____h594020[49] ? 6'd7 : - (_theResult____h452317[48] ? + (_theResult____h594020[48] ? 6'd8 : - (_theResult____h452317[47] ? + (_theResult____h594020[47] ? 6'd9 : - (_theResult____h452317[46] ? + (_theResult____h594020[46] ? 6'd10 : - (_theResult____h452317[45] ? + (_theResult____h594020[45] ? 6'd11 : - (_theResult____h452317[44] ? + (_theResult____h594020[44] ? 6'd12 : - (_theResult____h452317[43] ? + (_theResult____h594020[43] ? 6'd13 : - (_theResult____h452317[42] ? + (_theResult____h594020[42] ? 6'd14 : - (_theResult____h452317[41] ? + (_theResult____h594020[41] ? 6'd15 : - (_theResult____h452317[40] ? + (_theResult____h594020[40] ? 6'd16 : - (_theResult____h452317[39] ? + (_theResult____h594020[39] ? 6'd17 : - (_theResult____h452317[38] ? + (_theResult____h594020[38] ? 6'd18 : - (_theResult____h452317[37] ? + (_theResult____h594020[37] ? 6'd19 : - (_theResult____h452317[36] ? + (_theResult____h594020[36] ? 6'd20 : - (_theResult____h452317[35] ? + (_theResult____h594020[35] ? 6'd21 : - (_theResult____h452317[34] ? + (_theResult____h594020[34] ? 6'd22 : - (_theResult____h452317[33] ? + (_theResult____h594020[33] ? 6'd23 : - (_theResult____h452317[32] ? + (_theResult____h594020[32] ? 6'd24 : - (_theResult____h452317[31] ? + (_theResult____h594020[31] ? 6'd25 : - (_theResult____h452317[30] ? + (_theResult____h594020[30] ? 6'd26 : - (_theResult____h452317[29] ? + (_theResult____h594020[29] ? 6'd27 : - (_theResult____h452317[28] ? + (_theResult____h594020[28] ? 6'd28 : - (_theResult____h452317[27] ? + (_theResult____h594020[27] ? 6'd29 : - (_theResult____h452317[26] ? + (_theResult____h594020[26] ? 6'd30 : - (_theResult____h452317[25] ? + (_theResult____h594020[25] ? 6'd31 : - (_theResult____h452317[24] ? + (_theResult____h594020[24] ? 6'd32 : - (_theResult____h452317[23] ? + (_theResult____h594020[23] ? 6'd33 : - (_theResult____h452317[22] ? + (_theResult____h594020[22] ? 6'd34 : - (_theResult____h452317[21] ? + (_theResult____h594020[21] ? 6'd35 : - (_theResult____h452317[20] ? + (_theResult____h594020[20] ? 6'd36 : - (_theResult____h452317[19] ? + (_theResult____h594020[19] ? 6'd37 : - (_theResult____h452317[18] ? + (_theResult____h594020[18] ? 6'd38 : - (_theResult____h452317[17] ? + (_theResult____h594020[17] ? 6'd39 : - (_theResult____h452317[16] ? + (_theResult____h594020[16] ? 6'd40 : - (_theResult____h452317[15] ? + (_theResult____h594020[15] ? 6'd41 : - (_theResult____h452317[14] ? + (_theResult____h594020[14] ? 6'd42 : - (_theResult____h452317[13] ? + (_theResult____h594020[13] ? 6'd43 : - (_theResult____h452317[12] ? + (_theResult____h594020[12] ? 6'd44 : - (_theResult____h452317[11] ? + (_theResult____h594020[11] ? 6'd45 : - (_theResult____h452317[10] ? + (_theResult____h594020[10] ? 6'd46 : - (_theResult____h452317[9] ? + (_theResult____h594020[9] ? 6'd47 : - (_theResult____h452317[8] ? + (_theResult____h594020[8] ? 6'd48 : - (_theResult____h452317[7] ? + (_theResult____h594020[7] ? 6'd49 : - (_theResult____h452317[6] ? + (_theResult____h594020[6] ? 6'd50 : - (_theResult____h452317[5] ? + (_theResult____h594020[5] ? 6'd51 : - (_theResult____h452317[4] ? + (_theResult____h594020[4] ? 6'd52 : - (_theResult____h452317[3] ? + (_theResult____h594020[3] ? 6'd53 : - (_theResult____h452317[2] ? + (_theResult____h594020[2] ? 6'd54 : - (_theResult____h452317[1] ? + (_theResult____h594020[1] ? 6'd55 : - (_theResult____h452317[0] ? + (_theResult____h594020[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; - assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10404 = - (_theResult___fst_exp__h547052 == 11'd2047) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38826_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; - assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10669 = - (_theResult___fst_exp__h547052 == 11'd2047) ? - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38826_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; - assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d8931 = - (_theResult___fst_exp__h508251 == 11'd2047) ? + assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13072 = + (_theResult___fst_exp__h743790 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140) ; - assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9641 = - (_theResult___fst_exp__h586253 == 11'd2047) ? + CASE_guard35564_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; + assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13787 = + (_theResult___fst_exp__h821947 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; - assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9907 = - (_theResult___fst_exp__h586253 == 11'd2047) ? + CASE_guard13721_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q176) ; + assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14055 = + (_theResult___fst_exp__h821947 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : + CASE_guard13721_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q180) ; + assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14557 = + (_theResult___fst_exp__h782643 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard74417_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q209) ; + assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14824 = + (_theResult___fst_exp__h782643 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard74417_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q211) ; + assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10459 = + (guard__h622142 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? + sfdin__h630235[56:34] : + _theResult___sfd__h630758 ; + assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10461 = + (guard__h622142 == 2'b0) ? + sfdin__h630235[56:34] : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___sfd__h630758 : + sfdin__h630235[56:34]) ; + assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11209 = + (guard__h667889 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? + _theResult___fst_exp__h675988 : + _theResult___exp__h676504 ; + assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11212 = + (guard__h667889 == 2'b0) ? + _theResult___fst_exp__h675988 : + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + _theResult___exp__h676504 : + _theResult___fst_exp__h675988) ; + assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11856 = + (guard__h667889 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? + sfdin__h675982[56:34] : + _theResult___sfd__h676505 ; + assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11858 = + (guard__h667889 == 2'b0) ? + sfdin__h675982[56:34] : + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + _theResult___sfd__h676505 : + sfdin__h675982[56:34]) ; + assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8415 = + (guard__h576391 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? + _theResult___fst_exp__h584492 : + _theResult___exp__h585008 ; + assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8418 = + (guard__h576391 == 2'b0) ? + _theResult___fst_exp__h584492 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + _theResult___exp__h585008 : + _theResult___fst_exp__h584492) ; + assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9062 = + (guard__h576391 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? + sfdin__h584486[56:34] : + _theResult___sfd__h585009 ; + assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9064 = + (guard__h576391 == 2'b0) ? + sfdin__h584486[56:34] : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + _theResult___sfd__h585009 : + sfdin__h584486[56:34]) ; + assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9812 = + (guard__h622142 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? + _theResult___fst_exp__h630241 : + _theResult___exp__h630757 ; + assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9815 = + (guard__h622142 == 2'b0) ? + _theResult___fst_exp__h630241 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___exp__h630757 : + _theResult___fst_exp__h630241) ; + assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13189 = + (guard__h735564 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? + _theResult___fst_exp__h743790 : + _theResult___exp__h744519 ; + assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13191 = + (guard__h735564 == 2'b0) ? + _theResult___fst_exp__h743790 : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? + _theResult___exp__h744519 : + _theResult___fst_exp__h743790) ; + assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13273 = + (guard__h735564 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? + sfdin__h743784[56:5] : + _theResult___sfd__h744520 ; + assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13275 = + (guard__h735564 == 2'b0) ? + sfdin__h743784[56:5] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? + _theResult___sfd__h744520 : + sfdin__h743784[56:5]) ; + assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13899 = + (guard__h813721 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + _theResult___fst_exp__h821947 : + _theResult___exp__h822676 ; + assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13901 = + (guard__h813721 == 2'b0) ? + _theResult___fst_exp__h821947 : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + _theResult___exp__h822676 : + _theResult___fst_exp__h821947) ; + assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13982 = + (guard__h813721 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + sfdin__h821941[56:5] : + _theResult___sfd__h822677 ; + assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13984 = + (guard__h813721 == 2'b0) ? + sfdin__h821941[56:5] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + _theResult___sfd__h822677 : + sfdin__h821941[56:5]) ; + assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14669 = + (guard__h774417 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + _theResult___fst_exp__h782643 : + _theResult___exp__h783372 ; + assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14671 = + (guard__h774417 == 2'b0) ? + _theResult___fst_exp__h782643 : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + _theResult___exp__h783372 : + _theResult___fst_exp__h782643) ; + assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14752 = + (guard__h774417 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + sfdin__h782637[56:5] : + _theResult___sfd__h783373 ; + assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14754 = + (guard__h774417 == 2'b0) ? + sfdin__h782637[56:5] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + _theResult___sfd__h783373 : + sfdin__h782637[56:5]) ; + assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10359 = + (guard__h639779 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? + _theResult___fst_exp__h648007 : + _theResult___exp__h648523 ; + assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10361 = + (guard__h639779 == 2'b0) ? + _theResult___fst_exp__h648007 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___exp__h648523 : + _theResult___fst_exp__h648007) ; + assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505 = + (guard__h639779 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? + sfdin__h648001[56:34] : + _theResult___sfd__h648524 ; + assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507 = + (guard__h639779 == 2'b0) ? + sfdin__h648001[56:34] : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___sfd__h648524 : + sfdin__h648001[56:34]) ; + assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11756 = + (guard__h685526 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? + _theResult___fst_exp__h693754 : + _theResult___exp__h694270 ; + assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11758 = + (guard__h685526 == 2'b0) ? + _theResult___fst_exp__h693754 : + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + _theResult___exp__h694270 : + _theResult___fst_exp__h693754) ; + assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11902 = + (guard__h685526 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? + sfdin__h693748[56:34] : + _theResult___sfd__h694271 ; + assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11904 = + (guard__h685526 == 2'b0) ? + sfdin__h693748[56:34] : + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + _theResult___sfd__h694271 : + sfdin__h693748[56:34]) ; + assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8962 = + (guard__h594030 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? + _theResult___fst_exp__h602258 : + _theResult___exp__h602774 ; + assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8964 = + (guard__h594030 == 2'b0) ? + _theResult___fst_exp__h602258 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + _theResult___exp__h602774 : + _theResult___fst_exp__h602258) ; + assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9108 = + (guard__h594030 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? + sfdin__h602252[56:34] : + _theResult___sfd__h602775 ; + assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9110 = + (guard__h594030 == 2'b0) ? + sfdin__h602252[56:34] : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + _theResult___sfd__h602775 : + sfdin__h602252[56:34]) ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13146 = + (guard__h726252 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? + _theResult___fst_exp__h734213 : + _theResult___exp__h734868 ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13148 = + (guard__h726252 == 2'b0) ? + _theResult___fst_exp__h734213 : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? + _theResult___exp__h734868 : + _theResult___fst_exp__h734213) ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13220 = + (guard__h744633 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? + _theResult___fst_exp__h752623 : + _theResult___exp__h753303 ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13222 = + (guard__h744633 == 2'b0) ? + _theResult___fst_exp__h752623 : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? + _theResult___exp__h753303 : + _theResult___fst_exp__h752623) ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13246 = + (guard__h726252 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? + _theResult___snd__h734164[56:5] : + _theResult___sfd__h734869 ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13248 = + (guard__h726252 == 2'b0) ? + _theResult___snd__h734164[56:5] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? + _theResult___sfd__h734869 : + _theResult___snd__h734164[56:5]) ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13292 = + (guard__h744633 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? + _theResult___snd__h752569[56:5] : + _theResult___sfd__h753304 ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13294 = + (guard__h744633 == 2'b0) ? + _theResult___snd__h752569[56:5] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? + _theResult___sfd__h753304 : + _theResult___snd__h752569[56:5]) ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13861 = + (guard__h804409 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + _theResult___fst_exp__h812370 : + _theResult___exp__h813025 ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13863 = + (guard__h804409 == 2'b0) ? + _theResult___fst_exp__h812370 : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + _theResult___exp__h813025 : + _theResult___fst_exp__h812370) ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13930 = + (guard__h822790 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + _theResult___fst_exp__h830780 : + _theResult___exp__h831460 ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13932 = + (guard__h822790 == 2'b0) ? + _theResult___fst_exp__h830780 : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + _theResult___exp__h831460 : + _theResult___fst_exp__h830780) ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13956 = + (guard__h804409 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + _theResult___snd__h812321[56:5] : + _theResult___sfd__h813026 ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13958 = + (guard__h804409 == 2'b0) ? + _theResult___snd__h812321[56:5] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + _theResult___sfd__h813026 : + _theResult___snd__h812321[56:5]) ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14001 = + (guard__h822790 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + _theResult___snd__h830726[56:5] : + _theResult___sfd__h831461 ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14003 = + (guard__h822790 == 2'b0) ? + _theResult___snd__h830726[56:5] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + _theResult___sfd__h831461 : + _theResult___snd__h830726[56:5]) ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14631 = + (guard__h765105 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + _theResult___fst_exp__h773066 : + _theResult___exp__h773721 ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14633 = + (guard__h765105 == 2'b0) ? + _theResult___fst_exp__h773066 : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + _theResult___exp__h773721 : + _theResult___fst_exp__h773066) ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14700 = + (guard__h783486 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + _theResult___fst_exp__h791476 : + _theResult___exp__h792156 ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14702 = + (guard__h783486 == 2'b0) ? + _theResult___fst_exp__h791476 : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + _theResult___exp__h792156 : + _theResult___fst_exp__h791476) ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14726 = + (guard__h765105 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + _theResult___snd__h773017[56:5] : + _theResult___sfd__h773722 ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14728 = + (guard__h765105 == 2'b0) ? + _theResult___snd__h773017[56:5] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + _theResult___sfd__h773722 : + _theResult___snd__h773017[56:5]) ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14771 = + (guard__h783486 == 2'b0 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + _theResult___snd__h791422[56:5] : + _theResult___sfd__h792157 ; + assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14773 = + (guard__h783486 == 2'b0) ? + _theResult___snd__h791422[56:5] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + _theResult___sfd__h792157 : + _theResult___snd__h791422[56:5]) ; + assign IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20707 = + (IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15]) ? + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3__ETC___d20683 == + 4'd0 : + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 == + 4'd0 ; + assign IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20712 = + (IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15]) ? + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3__ETC___d20683 == + 4'd1 : + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 == + 4'd1 ; + assign IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20717 = + (IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15]) ? + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3__ETC___d20683 == + 4'd2 : + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 == + 4'd2 ; + assign IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20722 = + (IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15]) ? + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3__ETC___d20683 == + 4'd3 : + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 == + 4'd3 ; + assign IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20727 = + (IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15]) ? + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3__ETC___d20683 == + 4'd4 : + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 == + 4'd4 ; + assign IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20732 = + (IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15]) ? + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3__ETC___d20683 == + 4'd5 : + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 == + 4'd5 ; + assign IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20737 = + (IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15]) ? + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3__ETC___d20683 == + 4'd6 : + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 == + 4'd6 ; + assign IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20742 = + (IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15]) ? + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3__ETC___d20683 == + 4'd7 : + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 == + 4'd7 ; + assign IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20747 = + (IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15]) ? + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3__ETC___d20683 == + 4'd8 : + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 == + 4'd8 ; + assign IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20752 = + (IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15]) ? + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3__ETC___d20683 == + 4'd9 : + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 == + 4'd9 ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10034 = + (guard__h630849 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? + _theResult___fst_exp__h638897 : + _theResult___exp__h639339 ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10036 = + (guard__h630849 == 2'b0) ? + _theResult___fst_exp__h638897 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___exp__h639339 : + _theResult___fst_exp__h638897) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10428 = + (guard__h648615 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? + _theResult___fst_exp__h656692 : + _theResult___exp__h657159 ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10430 = + (guard__h648615 == 2'b0) ? + _theResult___fst_exp__h656692 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___exp__h657159 : + _theResult___fst_exp__h656692) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10478 = + (guard__h630849 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? + _theResult___snd__h638848[56:34] : + _theResult___sfd__h639340 ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10480 = + (guard__h630849 == 2'b0) ? + _theResult___snd__h638848[56:34] : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___sfd__h639340 : + _theResult___snd__h638848[56:34]) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10524 = + (guard__h648615 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? + _theResult___snd__h656638[56:34] : + _theResult___sfd__h657160 ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10526 = + (guard__h648615 == 2'b0) ? + _theResult___snd__h656638[56:34] : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___sfd__h657160 : + _theResult___snd__h656638[56:34]) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11431 = + (guard__h676596 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? + _theResult___fst_exp__h684644 : + _theResult___exp__h685086 ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11433 = + (guard__h676596 == 2'b0) ? + _theResult___fst_exp__h684644 : + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + _theResult___exp__h685086 : + _theResult___fst_exp__h684644) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11825 = + (guard__h694362 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? + _theResult___fst_exp__h702439 : + _theResult___exp__h702906 ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11827 = + (guard__h694362 == 2'b0) ? + _theResult___fst_exp__h702439 : + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + _theResult___exp__h702906 : + _theResult___fst_exp__h702439) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11875 = + (guard__h676596 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? + _theResult___snd__h684595[56:34] : + _theResult___sfd__h685087 ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11877 = + (guard__h676596 == 2'b0) ? + _theResult___snd__h684595[56:34] : + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + _theResult___sfd__h685087 : + _theResult___snd__h684595[56:34]) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11921 = + (guard__h694362 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? + _theResult___snd__h702385[56:34] : + _theResult___sfd__h702907 ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11923 = + (guard__h694362 == 2'b0) ? + _theResult___snd__h702385[56:34] : + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + _theResult___sfd__h702907 : + _theResult___snd__h702385[56:34]) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8637 = + (guard__h585100 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? + _theResult___fst_exp__h593148 : + _theResult___exp__h593590 ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8639 = + (guard__h585100 == 2'b0) ? + _theResult___fst_exp__h593148 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + _theResult___exp__h593590 : + _theResult___fst_exp__h593148) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9031 = + (guard__h602866 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? + _theResult___fst_exp__h610943 : + _theResult___exp__h611410 ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9033 = + (guard__h602866 == 2'b0) ? + _theResult___fst_exp__h610943 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + _theResult___exp__h611410 : + _theResult___fst_exp__h610943) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9081 = + (guard__h585100 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? + _theResult___snd__h593099[56:34] : + _theResult___sfd__h593591 ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9083 = + (guard__h585100 == 2'b0) ? + _theResult___snd__h593099[56:34] : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + _theResult___sfd__h593591 : + _theResult___snd__h593099[56:34]) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9127 = + (guard__h602866 == 2'b0 || + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? + _theResult___snd__h610889[56:34] : + _theResult___sfd__h611411 ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9129 = + (guard__h602866 == 2'b0) ? + _theResult___snd__h610889[56:34] : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + _theResult___sfd__h611411 : + _theResult___snd__h610889[56:34]) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13118 = + (_theResult___fst_exp__h752623 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard44633_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 = - (guard__h343310 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h351411 : - _theResult___exp__h351927 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 = - (guard__h343310 == 2'b0) ? - _theResult___fst_exp__h351411 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h351927 : - _theResult___fst_exp__h351411) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 = - (guard__h343310 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h351405[56:34] : - _theResult___sfd__h351928 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 = - (guard__h343310 == 2'b0) ? - sfdin__h351405[56:34] : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h351928 : - sfdin__h351405[56:34]) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 = - (guard__h389002 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h397101 : - _theResult___exp__h397617 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 = - (guard__h389002 == 2'b0) ? - _theResult___fst_exp__h397101 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h397617 : - _theResult___fst_exp__h397101) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 = - (guard__h389002 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h397095[56:34] : - _theResult___sfd__h397618 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 = - (guard__h389002 == 2'b0) ? - sfdin__h397095[56:34] : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h397618 : - sfdin__h397095[56:34]) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 = - (guard__h434690 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h442789 : - _theResult___exp__h443305 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 = - (guard__h434690 == 2'b0) ? - _theResult___fst_exp__h442789 : - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h443305 : - _theResult___fst_exp__h442789) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 = - (guard__h434690 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h442783[56:34] : - _theResult___sfd__h443306 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 = - (guard__h434690 == 2'b0) ? - sfdin__h442783[56:34] : - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h443306 : - sfdin__h442783[56:34]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516 = - (guard__h538826 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h547052 : - _theResult___exp__h547781 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518 = - (guard__h538826 == 2'b0) ? - _theResult___fst_exp__h547052 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h547781 : - _theResult___fst_exp__h547052) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599 = - (guard__h538826 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h547046[56:5] : - _theResult___sfd__h547782 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601 = - (guard__h538826 == 2'b0) ? - sfdin__h547046[56:5] : - (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h547782 : - sfdin__h547046[56:5]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048 = - (guard__h500025 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h508251 : - _theResult___exp__h508980 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050 = - (guard__h500025 == 2'b0) ? - _theResult___fst_exp__h508251 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h508980 : - _theResult___fst_exp__h508251) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132 = - (guard__h500025 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h508245[56:5] : - _theResult___sfd__h508981 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134 = - (guard__h500025 == 2'b0) ? - sfdin__h508245[56:5] : - (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h508981 : - sfdin__h508245[56:5]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753 = - (guard__h578027 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h586253 : - _theResult___exp__h586982 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755 = - (guard__h578027 == 2'b0) ? - _theResult___fst_exp__h586253 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h586982 : - _theResult___fst_exp__h586253) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836 = - (guard__h578027 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h586247[56:5] : - _theResult___sfd__h586983 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838 = - (guard__h578027 == 2'b0) ? - sfdin__h586247[56:5] : - (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h586983 : - sfdin__h586247[56:5]) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 = - (guard__h360949 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h369177 : - _theResult___exp__h369693 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 = - (guard__h360949 == 2'b0) ? - _theResult___fst_exp__h369177 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h369693 : - _theResult___fst_exp__h369177) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 = - (guard__h360949 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h369171[56:34] : - _theResult___sfd__h369694 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 = - (guard__h360949 == 2'b0) ? - sfdin__h369171[56:34] : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h369694 : - sfdin__h369171[56:34]) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 = - (guard__h406639 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h414867 : - _theResult___exp__h415383 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 = - (guard__h406639 == 2'b0) ? - _theResult___fst_exp__h414867 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h415383 : - _theResult___fst_exp__h414867) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 = - (guard__h406639 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h414861[56:34] : - _theResult___sfd__h415384 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 = - (guard__h406639 == 2'b0) ? - sfdin__h414861[56:34] : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h415384 : - sfdin__h414861[56:34]) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 = - (guard__h452327 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h460555 : - _theResult___exp__h461071 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 = - (guard__h452327 == 2'b0) ? - _theResult___fst_exp__h460555 : - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h461071 : - _theResult___fst_exp__h460555) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 = - (guard__h452327 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h460549[56:34] : - _theResult___sfd__h461072 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 = - (guard__h452327 == 2'b0) ? - sfdin__h460549[56:34] : - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h461072 : - sfdin__h460549[56:34]) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 = - (guard__h352019 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h360067 : - _theResult___exp__h360509 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 = - (guard__h352019 == 2'b0) ? - _theResult___fst_exp__h360067 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h360509 : - _theResult___fst_exp__h360067) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 = - (guard__h369785 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h377862 : - _theResult___exp__h378329 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 = - (guard__h369785 == 2'b0) ? - _theResult___fst_exp__h377862 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h378329 : - _theResult___fst_exp__h377862) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 = - (guard__h352019 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h360018[56:34] : - _theResult___sfd__h360510 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 = - (guard__h352019 == 2'b0) ? - _theResult___snd__h360018[56:34] : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h360510 : - _theResult___snd__h360018[56:34]) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 = - (guard__h369785 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h377808[56:34] : - _theResult___sfd__h378330 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 = - (guard__h369785 == 2'b0) ? - _theResult___snd__h377808[56:34] : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h378330 : - _theResult___snd__h377808[56:34]) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 = - (guard__h397709 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h405757 : - _theResult___exp__h406199 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 = - (guard__h397709 == 2'b0) ? - _theResult___fst_exp__h405757 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h406199 : - _theResult___fst_exp__h405757) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 = - (guard__h415475 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h423552 : - _theResult___exp__h424019 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 = - (guard__h415475 == 2'b0) ? - _theResult___fst_exp__h423552 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h424019 : - _theResult___fst_exp__h423552) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 = - (guard__h397709 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h405708[56:34] : - _theResult___sfd__h406200 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 = - (guard__h397709 == 2'b0) ? - _theResult___snd__h405708[56:34] : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h406200 : - _theResult___snd__h405708[56:34]) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 = - (guard__h415475 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h423498[56:34] : - _theResult___sfd__h424020 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 = - (guard__h415475 == 2'b0) ? - _theResult___snd__h423498[56:34] : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h424020 : - _theResult___snd__h423498[56:34]) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 = - (guard__h443397 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h451445 : - _theResult___exp__h451887 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 = - (guard__h443397 == 2'b0) ? - _theResult___fst_exp__h451445 : - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h451887 : - _theResult___fst_exp__h451445) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 = - (guard__h461163 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h469240 : - _theResult___exp__h469707 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 = - (guard__h461163 == 2'b0) ? - _theResult___fst_exp__h469240 : - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h469707 : - _theResult___fst_exp__h469240) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 = - (guard__h443397 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h451396[56:34] : - _theResult___sfd__h451888 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 = - (guard__h443397 == 2'b0) ? - _theResult___snd__h451396[56:34] : - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h451888 : - _theResult___snd__h451396[56:34]) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 = - (guard__h461163 == 2'b0 || - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h469186[56:34] : - _theResult___sfd__h469708 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 = - (guard__h461163 == 2'b0) ? - _theResult___snd__h469186[56:34] : - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h469708 : - _theResult___snd__h469186[56:34]) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478 = - (guard__h529514 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h537475 : - _theResult___exp__h538130 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480 = - (guard__h529514 == 2'b0) ? - _theResult___fst_exp__h537475 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h538130 : - _theResult___fst_exp__h537475) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547 = - (guard__h547895 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h555885 : - _theResult___exp__h556565 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549 = - (guard__h547895 == 2'b0) ? - _theResult___fst_exp__h555885 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h556565 : - _theResult___fst_exp__h555885) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573 = - (guard__h529514 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h537426[56:5] : - _theResult___sfd__h538131 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575 = - (guard__h529514 == 2'b0) ? - _theResult___snd__h537426[56:5] : - (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h538131 : - _theResult___snd__h537426[56:5]) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618 = - (guard__h547895 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h555831[56:5] : - _theResult___sfd__h556566 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620 = - (guard__h547895 == 2'b0) ? - _theResult___snd__h555831[56:5] : - (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h556566 : - _theResult___snd__h555831[56:5]) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005 = - (guard__h490713 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h498674 : - _theResult___exp__h499329 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007 = - (guard__h490713 == 2'b0) ? - _theResult___fst_exp__h498674 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h499329 : - _theResult___fst_exp__h498674) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079 = - (guard__h509094 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h517084 : - _theResult___exp__h517764 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081 = - (guard__h509094 == 2'b0) ? - _theResult___fst_exp__h517084 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h517764 : - _theResult___fst_exp__h517084) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105 = - (guard__h490713 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h498625[56:5] : - _theResult___sfd__h499330 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107 = - (guard__h490713 == 2'b0) ? - _theResult___snd__h498625[56:5] : - (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h499330 : - _theResult___snd__h498625[56:5]) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151 = - (guard__h509094 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h517030[56:5] : - _theResult___sfd__h517765 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153 = - (guard__h509094 == 2'b0) ? - _theResult___snd__h517030[56:5] : - (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h517765 : - _theResult___snd__h517030[56:5]) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715 = - (guard__h568715 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h576676 : - _theResult___exp__h577331 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717 = - (guard__h568715 == 2'b0) ? - _theResult___fst_exp__h576676 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h577331 : - _theResult___fst_exp__h576676) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784 = - (guard__h587096 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h595086 : - _theResult___exp__h595766 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786 = - (guard__h587096 == 2'b0) ? - _theResult___fst_exp__h595086 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h595766 : - _theResult___fst_exp__h595086) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810 = - (guard__h568715 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h576627[56:5] : - _theResult___sfd__h577332 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812 = - (guard__h568715 == 2'b0) ? - _theResult___snd__h576627[56:5] : - (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h577332 : - _theResult___snd__h576627[56:5]) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855 = - (guard__h587096 == 2'b0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h595032[56:5] : - _theResult___sfd__h595767 ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857 = - (guard__h587096 == 2'b0) ? - _theResult___snd__h595032[56:5] : - (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h595767 : - _theResult___snd__h595032[56:5]) ; - assign IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674 = - (_theResult____h645396 == 15'd0 && + assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13833 = + (_theResult___fst_exp__h830780 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard22790_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q178) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14040 = + (_theResult___fst_exp__h812370 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard04409_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q184) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14067 = + (_theResult___fst_exp__h830780 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard22790_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q182) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14603 = + (_theResult___fst_exp__h791476 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard83486_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q207) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14809 = + (_theResult___fst_exp__h773066 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard65105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q215) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14836 = + (_theResult___fst_exp__h791476 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard83486_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q213) ; + assign IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112 = + (_theResult____h917689 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h645940 : - _theResult____h645396 ; - assign IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12881 = - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[12] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[13] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[14] || - checkForException___d12839[4] || - csrf_fs_reg_read__1491_EQ_0_2828_AND_fetchStag_ETC___d12874 || - fetchStage$pipelines_0_first[231:200] == 32'h10500073 && - csrf_tw_reg && - csrf_prv_reg != 2'd3 ; - assign IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d13513 = - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[12] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[13] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[14] || - checkForException___d12839[4] || - csrf_fs_reg_read__1491_EQ_0_2828_AND_fetchStag_ETC___d13280 ; - assign IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d13549 = - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[12] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[13] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[14] || - checkForException___d13458[4] || - csrf_fs_reg_read__1491_EQ_0_2828_AND_fetchStag_ETC___d13547 ; - assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10450 = - (_theResult___fst_exp__h555885 == 11'd2047) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ; - assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10654 = - (_theResult___fst_exp__h537475 == 11'd2047) ? - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29514_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; - assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10681 = - (_theResult___fst_exp__h555885 == 11'd2047) ? - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; - assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8977 = - (_theResult___fst_exp__h517084 == 11'd2047) ? + enabled_ints__h918260 : + _theResult____h917689 ; + assign IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20454 = + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15] || + checkForException___d20432[13] || + csrf_fs_reg_read__5969_EQ_0_0418_AND_fetchStag_ETC___d20452 ; + assign IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d21429 = + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15] || + checkForException___d20432[13] || + csrf_fs_reg_read__5969_EQ_0_0418_AND_fetchStag_ETC___d21034 ; + assign IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d21469 = + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15] || + checkForException___d21369[13] || + csrf_fs_reg_read__5969_EQ_0_0418_AND_fetchStag_ETC___d21467 ; + assign IF_IF_coreFix_aluExe_0_dispToRegQ_first__8199__ETC___d19233 = + { (IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19217 == + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19222) ? + 2'd0 : + ((IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19217 && + !IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19222) ? + 2'd1 : + 2'd3), + (IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19219 == + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19222) ? + 2'd0 : + ((IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19219 && + !IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19222) ? + 2'd1 : + 2'd3) } ; + assign IF_IF_coreFix_aluExe_0_exeToFinQ_first__9735_B_ETC___d19879 = + ((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + coreFix_aluExe_0_exeToFinQ_first__9735_BITS_14_ETC___d19778 || + coreFix_aluExe_0_exeToFinQ$first[287:283] == 5'd1 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == 5'd1) ? + 5'd1 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == 5'd2 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == 5'd2) ? + 5'd2 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == 5'd3 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == 5'd3) ? + 5'd3 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == 5'd4 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == 5'd4) ? + 5'd4 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd5 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd5) ? + 5'd5 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd6 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd6) ? + 5'd6 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd7 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd7) ? + 5'd7 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd8 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd8) ? + 5'd8 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd9 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd9) ? + 5'd9 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd10 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd10) ? + 5'd10 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd11 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd11) ? + 5'd11 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd16 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd16) ? + 5'd16 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd17 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd17) ? + 5'd17 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd18 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd18) ? + 5'd18 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd19 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd19) ? + 5'd19 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd20 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd20) ? + 5'd20 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd21 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd21) ? + 5'd21 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd22 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd22) ? + 5'd22 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd23 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd23) ? + 5'd23 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd24 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd24) ? + 5'd24 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd25 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd25) ? + 5'd25 : + (((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd26 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == + 5'd26) ? + 5'd26 : + 5'd27))))))))))))))))))))) ; + assign IF_IF_coreFix_aluExe_0_exeToFinQ_first__9735_B_ETC___d19880 = + ((coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 && + coreFix_aluExe_0_exeToFinQ$first[287:283] == 5'd0 : + coreFix_aluExe_0_exeToFinQ$first[287:283] == 5'd0) ? + 5'd0 : + IF_IF_coreFix_aluExe_0_exeToFinQ_first__9735_B_ETC___d19879 ; + assign IF_IF_coreFix_aluExe_1_dispToRegQ_first__5590__ETC___d17155 = + { (IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17139 == + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17144) ? + 2'd0 : + ((IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17139 && + !IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17144) ? + 2'd1 : + 2'd3), + (IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17141 == + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17144) ? + 2'd0 : + ((IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17141 && + !IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17144) ? + 2'd1 : + 2'd3) } ; + assign IF_IF_coreFix_aluExe_1_exeToFinQ_first__7657_B_ETC___d17802 = + ((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + coreFix_aluExe_1_exeToFinQ_first__7657_BITS_14_ETC___d17701 || + coreFix_aluExe_1_exeToFinQ$first[287:283] == 5'd1 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == 5'd1) ? + 5'd1 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == 5'd2 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == 5'd2) ? + 5'd2 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == 5'd3 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == 5'd3) ? + 5'd3 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == 5'd4 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == 5'd4) ? + 5'd4 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd5 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd5) ? + 5'd5 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd6 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd6) ? + 5'd6 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd7 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd7) ? + 5'd7 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd8 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd8) ? + 5'd8 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd9 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd9) ? + 5'd9 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd10 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd10) ? + 5'd10 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd11 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd11) ? + 5'd11 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd16 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd16) ? + 5'd16 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd17 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd17) ? + 5'd17 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd18 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd18) ? + 5'd18 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd19 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd19) ? + 5'd19 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd20 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd20) ? + 5'd20 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd21 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd21) ? + 5'd21 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd22 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd22) ? + 5'd22 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd23 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd23) ? + 5'd23 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd24 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd24) ? + 5'd24 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd25 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd25) ? + 5'd25 : + (((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd26 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == + 5'd26) ? + 5'd26 : + 5'd27))))))))))))))))))))) ; + assign IF_IF_coreFix_aluExe_1_exeToFinQ_first__7657_B_ETC___d17803 = + ((coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 && + coreFix_aluExe_1_exeToFinQ$first[287:283] == 5'd0 : + coreFix_aluExe_1_exeToFinQ$first[287:283] == 5'd0) ? + 5'd0 : + IF_IF_coreFix_aluExe_1_exeToFinQ_first__7657_B_ETC___d17802 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 = + ((f1_exp__h714825 == 8'd0) ? + (f1_sfd__h714826[22] ? + 6'd2 : + (f1_sfd__h714826[21] ? + 6'd3 : + (f1_sfd__h714826[20] ? + 6'd4 : + (f1_sfd__h714826[19] ? + 6'd5 : + (f1_sfd__h714826[18] ? + 6'd6 : + (f1_sfd__h714826[17] ? + 6'd7 : + (f1_sfd__h714826[16] ? + 6'd8 : + (f1_sfd__h714826[15] ? + 6'd9 : + (f1_sfd__h714826[14] ? + 6'd10 : + (f1_sfd__h714826[13] ? + 6'd11 : + (f1_sfd__h714826[12] ? + 6'd12 : + (f1_sfd__h714826[11] ? + 6'd13 : + (f1_sfd__h714826[10] ? + 6'd14 : + (f1_sfd__h714826[9] ? + 6'd15 : + (f1_sfd__h714826[8] ? + 6'd16 : + (f1_sfd__h714826[7] ? + 6'd17 : + (f1_sfd__h714826[6] ? + 6'd18 : + (f1_sfd__h714826[5] ? + 6'd19 : + (f1_sfd__h714826[4] ? + 6'd20 : + (f1_sfd__h714826[3] ? + 6'd21 : + (f1_sfd__h714826[2] ? + 6'd22 : + (f1_sfd__h714826[1] ? + 6'd23 : + (f1_sfd__h714826[0] ? + 6'd24 : + 6'd57))))))))))))))))))))))) : + 6'd1) - + 6'd1 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13122 = + (f1_exp__h714825 == 8'd255 && f1_sfd__h714826 != 23'd0 || + (f1_exp__h714825 == 8'd255 || f1_exp__h714825 == 8'd0) && + f1_sfd__h714826 == 23'd0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142) ; - assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9687 = - (_theResult___fst_exp__h595086 == 11'd2047) ? + ((f1_exp__h714825 == 8'd0) ? + IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12777 : + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13120) ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13305 = + (f1_exp__h714825 == 8'd255 && f1_sfd__h714826 != 23'd0) ? + _theResult___snd_fst_sfd__h715141 : + _theResult___fst_sfd__h753422 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13306 = + { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13122, + (f1_exp__h714825 == 8'd255) ? + 11'd2047 : + _theResult___fst_exp__h753418, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13305 } ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 = + ((f3_exp__h793123 == 8'd0) ? + (f3_sfd__h793124[22] ? + 6'd2 : + (f3_sfd__h793124[21] ? + 6'd3 : + (f3_sfd__h793124[20] ? + 6'd4 : + (f3_sfd__h793124[19] ? + 6'd5 : + (f3_sfd__h793124[18] ? + 6'd6 : + (f3_sfd__h793124[17] ? + 6'd7 : + (f3_sfd__h793124[16] ? + 6'd8 : + (f3_sfd__h793124[15] ? + 6'd9 : + (f3_sfd__h793124[14] ? + 6'd10 : + (f3_sfd__h793124[13] ? + 6'd11 : + (f3_sfd__h793124[12] ? + 6'd12 : + (f3_sfd__h793124[11] ? + 6'd13 : + (f3_sfd__h793124[10] ? + 6'd14 : + (f3_sfd__h793124[9] ? + 6'd15 : + (f3_sfd__h793124[8] ? + 6'd16 : + (f3_sfd__h793124[7] ? + 6'd17 : + (f3_sfd__h793124[6] ? + 6'd18 : + (f3_sfd__h793124[5] ? + 6'd19 : + (f3_sfd__h793124[4] ? + 6'd20 : + (f3_sfd__h793124[3] ? + 6'd21 : + (f3_sfd__h793124[2] ? + 6'd22 : + (f3_sfd__h793124[1] ? + 6'd23 : + (f3_sfd__h793124[0] ? + 6'd24 : + 6'd57))))))))))))))))))))))) : + 6'd1) - + 6'd1 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13837 = + (f3_exp__h793123 == 8'd255 && f3_sfd__h793124 != 23'd0 || + (f3_exp__h793123 == 8'd255 || f3_exp__h793123 == 8'd0) && + f3_sfd__h793124 == 23'd0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; - assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9892 = - (_theResult___fst_exp__h576676 == 11'd2047) ? + ((f3_exp__h793123 == 8'd0) ? + IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13492 : + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13835) ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14014 = + (f3_exp__h793123 == 8'd255 && f3_sfd__h793124 != 23'd0) ? + _theResult___snd_fst_sfd__h793439 : + _theResult___fst_sfd__h831579 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14015 = + { (f3_exp__h793123 == 8'd255) ? + 11'd2047 : + _theResult___fst_exp__h831575, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14014 } ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14070 = + (f3_exp__h793123 == 8'd0) ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14040) : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14042) : + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14069 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14071 = + (f3_exp__h793123 == 8'd255 && f3_sfd__h793124 != 23'd0 || + (f3_exp__h793123 == 8'd255 || f3_exp__h793123 == 8'd0) && + f3_sfd__h793124 == 23'd0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68715_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; - assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9919 = - (_theResult___fst_exp__h595086 == 11'd2047) ? - !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; - assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847 = - IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836 ? - 4'd11 : - (IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1840 ? - 4'd12 : - (IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1844 ? - 4'd13 : - 4'd15)) ; - assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849 = - IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1828 ? - 4'd8 : - (IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1832 ? - 4'd9 : - IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847) ; - assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851 = - IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1820 ? - 4'd6 : - (IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1824 ? - 4'd7 : - IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849) ; - assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853 = - IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1812 ? - 4'd4 : - (IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1816 ? - 4'd5 : - IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851) ; - assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1855 = - IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1804 ? - 4'd2 : - (IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1808 ? - 4'd3 : - IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853) ; - assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1857 = - IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1796 ? - 4'd0 : - (IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1800 ? - 4'd1 : - IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1855) ; - assign IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13017 = - (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 == + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14070 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 = + ((f2_exp__h753819 == 8'd0) ? + (f2_sfd__h753820[22] ? + 6'd2 : + (f2_sfd__h753820[21] ? + 6'd3 : + (f2_sfd__h753820[20] ? + 6'd4 : + (f2_sfd__h753820[19] ? + 6'd5 : + (f2_sfd__h753820[18] ? + 6'd6 : + (f2_sfd__h753820[17] ? + 6'd7 : + (f2_sfd__h753820[16] ? + 6'd8 : + (f2_sfd__h753820[15] ? + 6'd9 : + (f2_sfd__h753820[14] ? + 6'd10 : + (f2_sfd__h753820[13] ? + 6'd11 : + (f2_sfd__h753820[12] ? + 6'd12 : + (f2_sfd__h753820[11] ? + 6'd13 : + (f2_sfd__h753820[10] ? + 6'd14 : + (f2_sfd__h753820[9] ? + 6'd15 : + (f2_sfd__h753820[8] ? + 6'd16 : + (f2_sfd__h753820[7] ? + 6'd17 : + (f2_sfd__h753820[6] ? + 6'd18 : + (f2_sfd__h753820[5] ? + 6'd19 : + (f2_sfd__h753820[4] ? + 6'd20 : + (f2_sfd__h753820[3] ? + 6'd21 : + (f2_sfd__h753820[2] ? + 6'd22 : + (f2_sfd__h753820[1] ? + 6'd23 : + (f2_sfd__h753820[0] ? + 6'd24 : + 6'd57))))))))))))))))))))))) : + 6'd1) - + 6'd1 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14607 = + (f2_exp__h753819 == 8'd255 && f2_sfd__h753820 != 23'd0 || + (f2_exp__h753819 == 8'd255 || f2_exp__h753819 == 8'd0) && + f2_sfd__h753820 == 23'd0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + ((f2_exp__h753819 == 8'd0) ? + IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14262 : + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14605) ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14784 = + (f2_exp__h753819 == 8'd255 && f2_sfd__h753820 != 23'd0) ? + _theResult___snd_fst_sfd__h754135 : + _theResult___fst_sfd__h792275 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14785 = + { (f2_exp__h753819 == 8'd255) ? + 11'd2047 : + _theResult___fst_exp__h792271, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14784 } ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14839 = + (f2_exp__h753819 == 8'd0) ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14809) : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14811) : + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14838 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14840 = + (f2_exp__h753819 == 8'd255 && f2_sfd__h753820 != 23'd0 || + (f2_exp__h753819 == 8'd255 || f2_exp__h753819 == 8'd0) && + f2_sfd__h753820 == 23'd0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14839 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14895 = + (f1_exp__h714825 == 8'd0) ? + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 && + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 && + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[4] : + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 && + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 && + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[4] ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14936 = + (f2_exp__h753819 == 8'd0) ? + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 && + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 && + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[4] : + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 && + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 && + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[4] ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14980 = + (f3_exp__h793123 == 8'd0) ? + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 && + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 && + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[4] : + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 && + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 && + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[4] ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14995 = + (f1_exp__h714825 == 8'd0) ? + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 && + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 && + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[3] : + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 && + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 && + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[3] ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15005 = + (f2_exp__h753819 == 8'd0) ? + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 && + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 && + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[3] : + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 && + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 && + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[3] ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15016 = + (f3_exp__h793123 == 8'd0) ? + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 && + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 && + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[3] : + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 && + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 && + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[3] ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15035 = + (f1_exp__h714825 == 8'd0) ? + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 || + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 && + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[2] : + !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 || + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15033 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15049 = + (f2_exp__h753819 == 8'd0) ? + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 || + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 && + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[2] : + !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 || + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15047 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15064 = + (f3_exp__h793123 == 8'd0) ? + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 || + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 && + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[2] : + !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 || + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15062 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15081 = + (f1_exp__h714825 == 8'd0) ? + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 && + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 || + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[1]) : + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 && + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15079 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15093 = + (f2_exp__h753819 == 8'd0) ? + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 && + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 || + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[1]) : + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 && + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15091 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15106 = + (f3_exp__h793123 == 8'd0) ? + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 && + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 || + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[1]) : + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 && + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15104 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15123 = + (f1_exp__h714825 == 8'd0) ? + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 || + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 && + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[0] : + !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 || + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15121 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15135 = + (f2_exp__h753819 == 8'd0) ? + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 || + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 && + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[0] : + !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 || + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15133 ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15148 = + (f3_exp__h793123 == 8'd0) ? + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 || + !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 && + _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[0] : + !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 || + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15146 ; + assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7231 = + _theResult_____2__h515296 == v__h514752 ; + assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7239 = + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7231 && + (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 || + !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry && + !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl && + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ; + assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7248 = + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7231 && + (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ? + !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] : + !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3]) && + (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7222 || + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ; + assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7322 = + _theResult_____2__h526073 == v__h516772 ; + assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7331 = + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7322 && + (IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7303 || + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas && + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl && + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full) ; + assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7404 = + (IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7303 && + (EN_dCacheToParent_fromP_enq ? + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[586] : + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[586])) ? + { 520'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, + EN_dCacheToParent_fromP_enq ? + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[65:0] : + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[65:0] } : + { EN_dCacheToParent_fromP_enq ? + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[585:522] : + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[585:522], + EN_dCacheToParent_fromP_enq ? + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[521:520] : + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[521:520], + IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7338 || + (EN_dCacheToParent_fromP_enq ? + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[519] : + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[519]), + EN_dCacheToParent_fromP_enq ? + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[518:3] : + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[518:3], + x__h521603 } ; + assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7482 = + _theResult_____2__h533166 == v__h532491 ; + assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7490 = + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7482 && + (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7462 || + !EN_dCacheToParent_rqToP_deq && + !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl && + coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full) ; + assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7501 = + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7482 && + (CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ? + !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] : + !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72]) && + (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7475 || + coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ; + assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7566 = + _theResult_____2__h543801 == v__h534940 ; + assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7574 = + IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7566 && + (IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7546 || + !EN_dCacheToParent_rsToP_deq && + !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl && + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full) ; + assign IF_IF_coreFix_memExe_dTlb_procResp__239_BIT_27_ETC___d4648 = + ((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + coreFix_memExe_dTlb_procResp__239_BITS_141_TO__ETC___d4570 || + coreFix_memExe_dTlb$procResp[282:278] == 5'd1 : + coreFix_memExe_dTlb$procResp[282:278] == 5'd1) ? + 5'd1 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == 5'd2 : + coreFix_memExe_dTlb$procResp[282:278] == 5'd2) ? + 5'd2 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == 5'd3 : + coreFix_memExe_dTlb$procResp[282:278] == 5'd3) ? + 5'd3 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == 5'd4 : + coreFix_memExe_dTlb$procResp[282:278] == 5'd4) ? + 5'd4 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == 5'd5 : + coreFix_memExe_dTlb$procResp[282:278] == 5'd5) ? + 5'd5 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == 5'd6 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd6) ? + 5'd6 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd7 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd7) ? + 5'd7 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd8 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd8) ? + 5'd8 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd9 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd9) ? + 5'd9 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd10 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd10) ? + 5'd10 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd11 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd11) ? + 5'd11 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd16 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd16) ? + 5'd16 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd17 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd17) ? + 5'd17 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd18 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd18) ? + 5'd18 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd19 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd19) ? + 5'd19 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd20 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd20) ? + 5'd20 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd21 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd21) ? + 5'd21 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd22 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd22) ? + 5'd22 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd23 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd23) ? + 5'd23 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd24 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd24) ? + 5'd24 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd25 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd25) ? + 5'd25 : + (((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == + 5'd26 : + coreFix_memExe_dTlb$procResp[282:278] == + 5'd26) ? + 5'd26 : + 5'd27))))))))))))))))))))) ; + assign IF_IF_coreFix_memExe_dTlb_procResp__239_BIT_27_ETC___d4649 = + ((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 && + coreFix_memExe_dTlb$procResp[282:278] == 5'd0 : + coreFix_memExe_dTlb$procResp[282:278] == 5'd0) ? + 5'd0 : + IF_IF_coreFix_memExe_dTlb_procResp__239_BIT_27_ETC___d4648 ; + assign IF_IF_coreFix_memExe_dTlb_procResp__239_BIT_27_ETC___d4739 = + ((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + coreFix_memExe_dTlb_procResp__239_BITS_141_TO__ETC___d4570 : + coreFix_memExe_dTlb$procResp[289]) ? + _0_CONCAT_IF_coreFix_memExe_dTlb_procResp__239__ETC___d4650 : + { 8'd106, + ((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != 3'd3 && + !coreFix_memExe_dTlb$procResp[290] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd0 : + (coreFix_memExe_dTlb$procResp[496] || + !coreFix_memExe_dTlb$procResp[290]) && + coreFix_memExe_dTlb$procResp[495:491] == 5'd0) ? + 5'd0 : + (((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != 3'd3 && + !coreFix_memExe_dTlb$procResp[290] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd1 : + (coreFix_memExe_dTlb$procResp[496] || + !coreFix_memExe_dTlb$procResp[290]) && + coreFix_memExe_dTlb$procResp[495:491] == 5'd1) ? + 5'd1 : + (((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != 3'd3 && + !coreFix_memExe_dTlb$procResp[290] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd2 : + (coreFix_memExe_dTlb$procResp[496] || + !coreFix_memExe_dTlb$procResp[290]) && + coreFix_memExe_dTlb$procResp[495:491] == 5'd2) ? + 5'd2 : + (((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != 3'd3 && + !coreFix_memExe_dTlb$procResp[290] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd3 : + (coreFix_memExe_dTlb$procResp[496] || + !coreFix_memExe_dTlb$procResp[290]) && + coreFix_memExe_dTlb$procResp[495:491] == 5'd3) ? + 5'd3 : + (((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != + 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != + 3'd3 && + (coreFix_memExe_dTlb$procResp[290] ? + coreFix_memExe_dTlb$procResp[490:488] == + 3'd0 : + coreFix_memExe_dTlb$procResp[495:491] == + 5'd4) : + ((!coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[290]) ? + coreFix_memExe_dTlb$procResp[490:488] == + 3'd0 || + coreFix_memExe_dTlb$procResp[490:488] == + 3'd2 : + coreFix_memExe_dTlb$procResp[495:491] == + 5'd4)) ? + 5'd4 : + (((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] == + 3'd2 || + coreFix_memExe_dTlb$procResp[490:488] != + 3'd3 && + !coreFix_memExe_dTlb$procResp[290] && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd5 : + (coreFix_memExe_dTlb$procResp[496] || + !coreFix_memExe_dTlb$procResp[290]) && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd5) ? + 5'd5 : + (((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != + 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != + 3'd3 && + (coreFix_memExe_dTlb$procResp[290] ? + coreFix_memExe_dTlb$procResp[490:488] != + 3'd0 : + coreFix_memExe_dTlb$procResp[495:491] == + 5'd6) : + ((!coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[290]) ? + coreFix_memExe_dTlb$procResp[490:488] != + 3'd0 && + coreFix_memExe_dTlb$procResp[490:488] != + 3'd2 : + coreFix_memExe_dTlb$procResp[495:491] == + 5'd6)) ? + 5'd6 : + (((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != + 3'd2 && + (coreFix_memExe_dTlb$procResp[490:488] == + 3'd3 || + !coreFix_memExe_dTlb$procResp[290] && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd7) : + (coreFix_memExe_dTlb$procResp[496] || + !coreFix_memExe_dTlb$procResp[290]) && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd7) ? + 5'd7 : + (((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != + 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != + 3'd3 && + !coreFix_memExe_dTlb$procResp[290] && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd8 : + (coreFix_memExe_dTlb$procResp[496] || + !coreFix_memExe_dTlb$procResp[290]) && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd8) ? + 5'd8 : + (((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != + 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != + 3'd3 && + !coreFix_memExe_dTlb$procResp[290] && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd9 : + (coreFix_memExe_dTlb$procResp[496] || + !coreFix_memExe_dTlb$procResp[290]) && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd9) ? + 5'd9 : + (((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != + 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != + 3'd3 && + !coreFix_memExe_dTlb$procResp[290] && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd11 : + (coreFix_memExe_dTlb$procResp[496] || + !coreFix_memExe_dTlb$procResp[290]) && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd11) ? + 5'd11 : + (((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != + 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != + 3'd3 && + !coreFix_memExe_dTlb$procResp[290] && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd12 : + (coreFix_memExe_dTlb$procResp[496] || + !coreFix_memExe_dTlb$procResp[290]) && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd12) ? + 5'd12 : + (((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != + 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != + 3'd3 && + !coreFix_memExe_dTlb$procResp[290] && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd13 : + (coreFix_memExe_dTlb$procResp[496] || + !coreFix_memExe_dTlb$procResp[290]) && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd13) ? + 5'd13 : + (((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != + 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != + 3'd3 && + !coreFix_memExe_dTlb$procResp[290] && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd15 : + (coreFix_memExe_dTlb$procResp[496] || + !coreFix_memExe_dTlb$procResp[290]) && + coreFix_memExe_dTlb$procResp[495:491] == + 5'd15) ? + 5'd15 : + 5'd28))))))))))))) } ; + assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7852 = + _theResult_____2__h561413 == v__h559739 ; + assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7860 = + IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7852 && + (IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7833 || + !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + !coreFix_memExe_forwardQ_deqReq_rl && + coreFix_memExe_forwardQ_full) ; + assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7870 = + IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7852 && + (coreFix_memExe_forwardQ_enqReq_lat_0$whas ? + !coreFix_memExe_forwardQ_enqReq_lat_0$wget[134] : + !coreFix_memExe_forwardQ_enqReq_rl[134]) && + (IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7846 || + coreFix_memExe_forwardQ_empty) ; + assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7770 = + _theResult_____2__h557634 == v__h555960 ; + assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7778 = + IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7770 && + (IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7751 || + !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + !coreFix_memExe_memRespLdQ_deqReq_rl && + coreFix_memExe_memRespLdQ_full) ; + assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7788 = + IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7770 && + (coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ? + !coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[134] : + !coreFix_memExe_memRespLdQ_enqReq_rl[134]) && + (IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7764 || + coreFix_memExe_memRespLdQ_empty) ; + assign IF_IF_csrf_prv_reg_read__0075_ULE_1_2375_AND_I_ETC___d22667 = + (csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 ? + !csrf_stcc_reg[34] : + !csrf_mtcc_reg[34]) ? + { x__h997991[11:0], + x1_avValue_new_pcc_capFat_bounds_baseBits__h997994 } : + { x__h997991[11:3], + x__h998012[5:3], + x1_avValue_new_pcc_capFat_bounds_baseBits__h997994[13:3], + x__h998012[2:0] } ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20636 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == + 4'd13 : + checkForException___d20432[13] && + checkForException___d20432[4:0] == 5'd15) ? + 5'd15 : + 5'd28 ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20637 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == 4'd12 : - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 == - 4'd12) ? - 4'd13 : - 4'd15 ; - assign IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13018 = - (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 == + checkForException___d20432[13] && + checkForException___d20432[4:0] == 5'd13) ? + 5'd13 : + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20636 ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20638 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == 4'd11 : - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 == - 4'd11) ? - 4'd12 : - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13017 ; - assign IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13019 = - (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 == + checkForException___d20432[13] && + checkForException___d20432[4:0] == 5'd12) ? + 5'd12 : + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20637 ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20639 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == 4'd10 : - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 == - 4'd10) ? - 4'd11 : - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13018 ; - assign IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13020 = - (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 == + checkForException___d20432[13] && + checkForException___d20432[4:0] == 5'd11) ? + 5'd11 : + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20638 ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20640 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == 4'd9 : - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 == - 4'd9) ? - 4'd9 : - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13019 ; - assign IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13021 = - (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 == + checkForException___d20432[13] && + checkForException___d20432[4:0] == 5'd9) ? + 5'd9 : + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20639 ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20641 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == 4'd8 : - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 == - 4'd8) ? - 4'd8 : - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13020 ; - assign IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13022 = - (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 == + checkForException___d20432[13] && + checkForException___d20432[4:0] == 5'd8) ? + 5'd8 : + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20640 ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20642 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == 4'd7 : - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 == - 4'd7) ? - 4'd7 : - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13021 ; - assign IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13023 = - (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 == + checkForException___d20432[13] && + checkForException___d20432[4:0] == 5'd7) ? + 5'd7 : + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20641 ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20643 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == 4'd6 : - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 == - 4'd6) ? - 4'd6 : - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13022 ; - assign IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13024 = - (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 == + checkForException___d20432[13] && + checkForException___d20432[4:0] == 5'd6) ? + 5'd6 : + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20642 ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20644 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == 4'd5 : - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 == - 4'd5) ? - 4'd5 : - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13023 ; - assign IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13025 = - (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 == + checkForException___d20432[13] && + checkForException___d20432[4:0] == 5'd5) ? + 5'd5 : + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20643 ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20645 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == 4'd4 : - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 == - 4'd4) ? - 4'd4 : - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13024 ; - assign IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13026 = - (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 == + checkForException___d20432[13] && + checkForException___d20432[4:0] == 5'd4) ? + 5'd4 : + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20644 ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20646 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == 4'd3 : - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 == - 4'd3) ? - 4'd3 : - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13025 ; - assign IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13027 = - (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 == + checkForException___d20432[13] && + checkForException___d20432[4:0] == 5'd3) ? + 5'd3 : + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20645 ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20647 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == 4'd2 : - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 == - 4'd2) ? - 4'd2 : - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13026 ; - assign IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13028 = - (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 == + !checkForException___d20432[13] || + checkForException___d20432[4:0] == 5'd2) ? + 5'd2 : + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20646 ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20648 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == 4'd1 : - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 == - 4'd1) ? - 4'd1 : - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13027 ; - assign IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13029 = - (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 == + checkForException___d20432[13] && + checkForException___d20432[4:0] == 5'd1) ? + 5'd1 : + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20647 ; + assign IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20649 = + (fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 == 4'd0 : - IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 == - 4'd0) ? - 4'd0 : - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13028 ; - assign IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463 = + checkForException___d20432[13] && + checkForException___d20432[4:0] == 5'd0) ? + 5'd0 : + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20648 ; + assign IF_IF_mmio_cRqQ_enqReq_lat_1_whas__87_THEN_mmi_ETC___d408 = { (mmio_cRqQ_enqReq_lat_0$whas ? - mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd1 : - mmio_cRqQ_enqReq_rl[77:76] == 2'd1) ? + mmio_cRqQ_enqReq_lat_0$wget[150:149] == 2'd1 : + mmio_cRqQ_enqReq_rl[150:149] == 2'd1) ? 2'd1 : ((mmio_cRqQ_enqReq_lat_0$whas ? - mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd2 : - mmio_cRqQ_enqReq_rl[77:76] == 2'd2) ? + mmio_cRqQ_enqReq_lat_0$wget[150:149] == 2'd2 : + mmio_cRqQ_enqReq_rl[150:149] == 2'd2) ? 2'd2 : 2'd3), mmio_cRqQ_enqReq_lat_0$whas ? - mmio_cRqQ_enqReq_lat_0$wget[75:72] : - mmio_cRqQ_enqReq_rl[75:72] } ; - assign IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172 = + mmio_cRqQ_enqReq_lat_0$wget[148:145] : + mmio_cRqQ_enqReq_rl[148:145] } ; + assign IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__2_THEN__ETC___d165 = { (mmio_dataReqQ_enqReq_lat_0$whas ? - mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd1 : - mmio_dataReqQ_enqReq_rl[77:76] == 2'd1) ? + mmio_dataReqQ_enqReq_lat_0$wget[150:149] == 2'd1 : + mmio_dataReqQ_enqReq_rl[150:149] == 2'd1) ? 2'd1 : ((mmio_dataReqQ_enqReq_lat_0$whas ? - mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd2 : - mmio_dataReqQ_enqReq_rl[77:76] == 2'd2) ? + mmio_dataReqQ_enqReq_lat_0$wget[150:149] == 2'd2 : + mmio_dataReqQ_enqReq_rl[150:149] == 2'd2) ? 2'd2 : 2'd3), mmio_dataReqQ_enqReq_lat_0$whas ? - mmio_dataReqQ_enqReq_lat_0$wget[75:72] : - mmio_dataReqQ_enqReq_rl[75:72] } ; - assign IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766 = + mmio_dataReqQ_enqReq_lat_0$wget[148:145] : + mmio_dataReqQ_enqReq_rl[148:145] } ; + assign IF_IF_mmio_pRqQ_enqReq_lat_1_whas__56_THEN_mmi_ETC___d677 = { (EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd1 : mmio_pRqQ_enqReq_rl[37:36] == 2'd1) ? @@ -19498,11 +21404,12 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[35:32] : mmio_pRqQ_enqReq_rl[35:32] } ; - assign IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 = + assign IF_IF_mmio_pRsQ_enqReq_lat_1_whas__15_THEN_NOT_ETC___d550 = (EN_mmioToPlatform_pRs_enq ? - !mmio_pRsQ_enqReq_lat_0$wget[66] : - !mmio_pRsQ_enqReq_rl[66]) ? - { EN_mmioToPlatform_pRs_enq ? + !mmio_pRsQ_enqReq_lat_0$wget[130] : + !mmio_pRsQ_enqReq_rl[130]) ? + { 64'hAAAAAAAAAAAAAAAA, + EN_mmioToPlatform_pRs_enq ? mmio_pRsQ_enqReq_lat_0$wget[65] : mmio_pRsQ_enqReq_rl[65], EN_mmioToPlatform_pRs_enq ? @@ -19514,741 +21421,2699 @@ module mkCore(CLK, EN_mmioToPlatform_pRs_enq ? mmio_pRsQ_enqReq_lat_0$wget[31:0] : mmio_pRsQ_enqReq_rl[31:0] } : - { 1'h0, - EN_mmioToPlatform_pRs_enq ? - mmio_pRsQ_enqReq_lat_0$wget[64:0] : - mmio_pRsQ_enqReq_rl[64:0] } ; - assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10109 = - (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 || - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 || - _theResult___fst_exp__h537475 == 11'd2047) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29514_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ; - assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8636 = - (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 || - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 || - _theResult___fst_exp__h498674 == 11'd2047) ? + (EN_mmioToPlatform_pRs_enq ? + mmio_pRsQ_enqReq_lat_0$wget[129:0] : + mmio_pRsQ_enqReq_rl[129:0]) ; + assign IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20755 = + (renameStage_rg_m_halt_req[4] ? + renameStage_rg_m_halt_req[3:0] == 4'd11 : + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20747) ? + 4'd11 : + ((renameStage_rg_m_halt_req[4] ? + renameStage_rg_m_halt_req[3:0] == 4'd14 : + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20752) ? + 4'd14 : + 4'd15) ; + assign IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20756 = + (renameStage_rg_m_halt_req[4] ? + renameStage_rg_m_halt_req[3:0] == 4'd9 : + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20742) ? + 4'd9 : + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20755 ; + assign IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20757 = + (renameStage_rg_m_halt_req[4] ? + renameStage_rg_m_halt_req[3:0] == 4'd8 : + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20737) ? + 4'd8 : + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20756 ; + assign IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20758 = + (renameStage_rg_m_halt_req[4] ? + renameStage_rg_m_halt_req[3:0] == 4'd7 : + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20732) ? + 4'd7 : + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20757 ; + assign IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20759 = + (renameStage_rg_m_halt_req[4] ? + renameStage_rg_m_halt_req[3:0] == 4'd5 : + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20727) ? + 4'd5 : + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20758 ; + assign IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20760 = + (renameStage_rg_m_halt_req[4] ? + renameStage_rg_m_halt_req[3:0] == 4'd4 : + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20722) ? + 4'd4 : + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20759 ; + assign IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20761 = + (renameStage_rg_m_halt_req[4] ? + renameStage_rg_m_halt_req[3:0] == 4'd3 : + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20717) ? + 4'd3 : + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20760 ; + assign IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20762 = + (renameStage_rg_m_halt_req[4] ? + renameStage_rg_m_halt_req[3:0] == 4'd1 : + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20712) ? + 4'd1 : + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20761 ; + assign IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20763 = + (renameStage_rg_m_halt_req[4] ? + renameStage_rg_m_halt_req[3:0] == 4'd0 : + IF_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_ETC___d20707) ? + 4'd0 : + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20762 ; + assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 = + { INV_x83367_BITS_108_TO_90__q33[0] ? x__h183487 : 6'd0, + x__h183647, + x__h183667 } ; + assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 = + { INV_x99219_BITS_108_TO_90__q35[0] ? x__h202238 : 6'd0, + x__h202398, + x__h202418 } ; + assign IF_INV_commitStage_commitTrap_2029_BITS_217_TO_ETC___d22341 = + INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? + x__h992056 : + 6'd0 ; + assign IF_INV_commitStage_commitTrap_2029_BITS_217_TO_ETC___d22422 = + x__h992236[13:11] < repBound__h994706 ; + assign IF_INV_commitStage_commitTrap_2029_BITS_217_TO_ETC___d22424 = + pc_addrBits__h991847[13:11] < repBound__h994706 ; + assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19567 = + tb__h904279 < repBound__h904282 ; + assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19568 = + x__h904221[13:11] < repBound__h904282 ; + assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19570 = + cr_addrBits__h903814[13:11] < repBound__h904282 ; + assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19580 = + { IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19570, + (IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19567 == + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19570) ? + 2'd0 : + ((IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19567 && + !IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19570) ? + 2'd1 : + 2'd3), + (IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19568 == + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19570) ? + 2'd0 : + ((IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19568 && + !IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19570) ? + 2'd1 : + 2'd3) } ; + assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19631 = + tb__h904827 < repBound__h904830 ; + assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19632 = + x__h904769[13:11] < repBound__h904830 ; + assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19634 = + cr_addrBits__h904362[13:11] < repBound__h904830 ; + assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19644 = + { IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19634, + (IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19631 == + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19634) ? + 2'd0 : + ((IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19631 && + !IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19634) ? + 2'd1 : + 2'd3), + (IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19632 == + IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19634) ? + 2'd0 : + ((IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19632 && + !IF_INV_coreFix_aluExe_0_regToExeQ_first__9257__ETC___d19634) ? + 2'd1 : + 2'd3) } ; + assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17489 = + tb__h865798 < repBound__h865801 ; + assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17490 = + x__h865740[13:11] < repBound__h865801 ; + assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17492 = + cr_addrBits__h865333[13:11] < repBound__h865801 ; + assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17502 = + { IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17492, + (IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17489 == + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17492) ? + 2'd0 : + ((IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17489 && + !IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17492) ? + 2'd1 : + 2'd3), + (IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17490 == + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17492) ? + 2'd0 : + ((IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17490 && + !IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17492) ? + 2'd1 : + 2'd3) } ; + assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17553 = + tb__h866346 < repBound__h866349 ; + assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17554 = + x__h866288[13:11] < repBound__h866349 ; + assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17556 = + cr_addrBits__h865881[13:11] < repBound__h866349 ; + assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17566 = + { IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17556, + (IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17553 == + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17556) ? + 2'd0 : + ((IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17553 && + !IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17556) ? + 2'd1 : + 2'd3), + (IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17554 == + IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17556) ? + 2'd0 : + ((IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17554 && + !IF_INV_coreFix_aluExe_1_regToExeQ_first__7179__ETC___d17556) ? + 2'd1 : + 2'd3) } ; + assign IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 = + { INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? + x__h216804 : + 6'd0, + x__h216964, + x__h216984 } ; + assign IF_INV_coreFix_memExe_respLrScAmoQ_data_0_233__ETC___d1273 = + { INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? + x__h127310 : + 6'd0, + x__h127470, + x__h127490 } ; + assign IF_INV_mmio_dataRespQ_data_0_389_BITS_108_TO_9_ETC___d1433 = + { INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? + x__h140226 : + 6'd0, + x__h140386, + x__h140406 } ; + assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12777 = + (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 || + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 || + _theResult___fst_exp__h734213 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138) ; - assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9346 = - (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 || - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 || - _theResult___fst_exp__h576676 == 11'd2047) ? + CASE_guard26252_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; + assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13492 = + (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 || + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 || + _theResult___fst_exp__h812370 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; - assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3__ETC___d13055 = - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] ? + CASE_guard04409_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q174) ; + assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14262 = + (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 || + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 || + _theResult___fst_exp__h773066 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard65105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q205) ; + assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3__ETC___d20683 = + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] ? 4'd0 : - (IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] ? + (IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] ? 4'd1 : - ((IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2]) ? + ((IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2]) ? 4'd2 : - ((IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3]) ? + ((IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3]) ? 4'd3 : - ((IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4]) ? + ((IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4]) ? 4'd4 : - ((IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6]) ? + ((IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6]) ? 4'd5 : - ((IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7]) ? + ((IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7]) ? 4'd6 : - ((IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8]) ? + ((IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8]) ? 4'd7 : - ((IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10]) ? + ((IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10]) ? 4'd8 : - 4'd9)))))))) ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12133 = + ((IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13]) ? + 4'd9 : + 4'd10))))))))) ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18254 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101) ? + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12114 : + coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12134 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18255 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101) && + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12114)) ? + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? coreFix_aluExe_0_bypassWire_2$whas && - coreFix_aluExe_0_bypassWire_2_wget__2120_BITS__ETC___d12122 : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12133 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12135 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12125 ? + coreFix_aluExe_0_bypassWire_2_wget__8241_BITS__ETC___d18243 : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18254 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18256 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? coreFix_aluExe_0_bypassWire_3$whas && - coreFix_aluExe_0_bypassWire_3$wget[70:64] == + coreFix_aluExe_0_bypassWire_3$wget[169:163] == coreFix_aluExe_0_dispToRegQ$first[84:78] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12134 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12158 = + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18255 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18279 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12140) ? + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18261) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12146 : + coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18267 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12159 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18280 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12140) && + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18261) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12146)) ? + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18267)) ? coreFix_aluExe_0_bypassWire_2$whas && - coreFix_aluExe_0_bypassWire_2_wget__2120_BITS__ETC___d12150 : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12158 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12160 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12153 ? + coreFix_aluExe_0_bypassWire_2_wget__8241_BITS__ETC___d18271 : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18279 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18281 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18274 ? coreFix_aluExe_0_bypassWire_3$whas && - coreFix_aluExe_0_bypassWire_3$wget[70:64] == + coreFix_aluExe_0_bypassWire_3$wget[169:163] == coreFix_aluExe_0_dispToRegQ$first[76:70] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12159 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12316 = + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18280 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18559 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101) ? - coreFix_aluExe_0_bypassWire_1$wget[63:0] : - coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12317 = + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[162] : + coreFix_aluExe_0_bypassWire_0$wget[162] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18560 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101) && + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12114)) ? - coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12316 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12328 = + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[162] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18559 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18613 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12140) ? - coreFix_aluExe_0_bypassWire_1$wget[63:0] : - coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12329 = + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[161:96] : + coreFix_aluExe_0_bypassWire_0$wget[161:96] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18614 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12140) && + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12146)) ? - coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12328 ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11338 = + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[161:96] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18613 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18628 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11306) ? + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[95:82] : + coreFix_aluExe_0_bypassWire_0$wget[95:82] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18629 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[95:82] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18628 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18641 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[81:78] : + coreFix_aluExe_0_bypassWire_0$wget[81:78] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18642 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[81:78] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18641 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18654 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[77] : + coreFix_aluExe_0_bypassWire_0$wget[77] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18655 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[77] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18654 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18667 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[76] : + coreFix_aluExe_0_bypassWire_0$wget[76] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18668 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[76] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18667 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18680 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[75] : + coreFix_aluExe_0_bypassWire_0$wget[75] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18681 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[75] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18680 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18693 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[74] : + coreFix_aluExe_0_bypassWire_0$wget[74] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18694 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[74] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18693 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18706 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[73] : + coreFix_aluExe_0_bypassWire_0$wget[73] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18707 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[73] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18706 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18719 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[72] : + coreFix_aluExe_0_bypassWire_0$wget[72] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18720 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[72] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18719 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18732 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[71] : + coreFix_aluExe_0_bypassWire_0$wget[71] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18733 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[71] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18732 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18745 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[70] : + coreFix_aluExe_0_bypassWire_0$wget[70] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18746 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[70] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18745 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18758 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[69] : + coreFix_aluExe_0_bypassWire_0$wget[69] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18759 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[69] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18758 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18771 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[68] : + coreFix_aluExe_0_bypassWire_0$wget[68] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18772 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[68] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18771 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18784 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[67] : + coreFix_aluExe_0_bypassWire_0$wget[67] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18785 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[67] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18784 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18797 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[66] : + coreFix_aluExe_0_bypassWire_0$wget[66] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18798 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[66] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18797 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18816 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[65] : + coreFix_aluExe_0_bypassWire_0$wget[65] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18817 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[65] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18816 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18829 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[64:63] : + coreFix_aluExe_0_bypassWire_0$wget[64:63] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18830 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[64:63] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18829 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18842 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[62:45] : + coreFix_aluExe_0_bypassWire_0$wget[62:45] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18843 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[62:45] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18842 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18857 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[44] : + coreFix_aluExe_0_bypassWire_0$wget[44] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18858 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[44] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18857 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18870 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[43:10] : + coreFix_aluExe_0_bypassWire_0$wget[43:10] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18871 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[43:10] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18870 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18888 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[9:7] : + coreFix_aluExe_0_bypassWire_0$wget[9:7] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18889 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[9:7] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18888 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18902 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[6] : + coreFix_aluExe_0_bypassWire_0$wget[6] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18903 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[6] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18902 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18915 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[5] : + coreFix_aluExe_0_bypassWire_0$wget[5] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18916 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[5] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18915 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18929 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[4] : + coreFix_aluExe_0_bypassWire_0$wget[4] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18930 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[4] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18929 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18951 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? + coreFix_aluExe_0_bypassWire_1$wget[3:0] : + coreFix_aluExe_0_bypassWire_0$wget[3:0] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18952 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235)) ? + coreFix_aluExe_0_bypassWire_2$wget[3:0] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18951 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18991 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18261) ? + coreFix_aluExe_0_bypassWire_1$wget[162:0] : + coreFix_aluExe_0_bypassWire_0$wget[162:0] ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18992 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18261) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18267)) ? + coreFix_aluExe_0_bypassWire_2$wget[162:0] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18991 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15645 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_aluExe_1_bypassWire_1_wget__1317_BITS__ETC___d11319 : + coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11339 = + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15646 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11306) && + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_1_bypassWire_1_wget__1317_BITS__ETC___d11319)) ? + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? coreFix_aluExe_1_bypassWire_2$whas && - coreFix_aluExe_1_bypassWire_2_wget__1325_BITS__ETC___d11327 : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11338 ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11340 = - NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11330 ? + coreFix_aluExe_1_bypassWire_2_wget__5632_BITS__ETC___d15634 : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15645 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15647 = + NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? coreFix_aluExe_1_bypassWire_3$whas && - coreFix_aluExe_0_bypassWire_3$wget[70:64] == + coreFix_aluExe_0_bypassWire_3$wget[169:163] == coreFix_aluExe_1_dispToRegQ$first[84:78] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11339 ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11363 = + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15646 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15670 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11345) ? + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15652) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_aluExe_1_bypassWire_1_wget__1317_BITS__ETC___d11351 : + coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15658 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11364 = + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15671 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11345) && + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15652) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_1_bypassWire_1_wget__1317_BITS__ETC___d11351)) ? + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15658)) ? coreFix_aluExe_1_bypassWire_2$whas && - coreFix_aluExe_1_bypassWire_2_wget__1325_BITS__ETC___d11355 : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11363 ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11365 = - NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11358 ? + coreFix_aluExe_1_bypassWire_2_wget__5632_BITS__ETC___d15662 : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15670 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15672 = + NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15665 ? coreFix_aluExe_1_bypassWire_3$whas && - coreFix_aluExe_0_bypassWire_3$wget[70:64] == + coreFix_aluExe_0_bypassWire_3$wget[169:163] == coreFix_aluExe_1_dispToRegQ$first[76:70] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11364 ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11707 = + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15671 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15950 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11306) ? - coreFix_aluExe_0_bypassWire_1$wget[63:0] : - coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11708 = + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[162] : + coreFix_aluExe_0_bypassWire_0$wget[162] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15951 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11306) && + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_1_bypassWire_1_wget__1317_BITS__ETC___d11319)) ? - coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11707 ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11719 = + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[162] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15950 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16230 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11345) ? - coreFix_aluExe_0_bypassWire_1$wget[63:0] : - coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11720 = + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[161:96] : + coreFix_aluExe_0_bypassWire_0$wget[161:96] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16231 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11345) && + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_1_bypassWire_1_wget__1317_BITS__ETC___d11351)) ? - coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11719 ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8238 = + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[161:96] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16230 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16245 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) ? + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[95:82] : + coreFix_aluExe_0_bypassWire_0$wget[95:82] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16246 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[95:82] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16245 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16258 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[81:78] : + coreFix_aluExe_0_bypassWire_0$wget[81:78] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16259 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[81:78] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16258 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16271 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[77] : + coreFix_aluExe_0_bypassWire_0$wget[77] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16272 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[77] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16271 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16284 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[76] : + coreFix_aluExe_0_bypassWire_0$wget[76] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16285 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[76] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16284 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16297 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[75] : + coreFix_aluExe_0_bypassWire_0$wget[75] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16298 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[75] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16297 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16310 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[74] : + coreFix_aluExe_0_bypassWire_0$wget[74] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16311 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[74] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16310 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16323 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[73] : + coreFix_aluExe_0_bypassWire_0$wget[73] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16324 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[73] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16323 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16336 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[72] : + coreFix_aluExe_0_bypassWire_0$wget[72] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16337 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[72] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16336 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16349 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[71] : + coreFix_aluExe_0_bypassWire_0$wget[71] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16350 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[71] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16349 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16362 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[70] : + coreFix_aluExe_0_bypassWire_0$wget[70] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16363 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[70] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16362 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16375 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[69] : + coreFix_aluExe_0_bypassWire_0$wget[69] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16376 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[69] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16375 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16388 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[68] : + coreFix_aluExe_0_bypassWire_0$wget[68] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16389 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[68] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16388 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16401 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[67] : + coreFix_aluExe_0_bypassWire_0$wget[67] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16402 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[67] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16401 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16414 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[66] : + coreFix_aluExe_0_bypassWire_0$wget[66] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16415 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[66] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16414 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16433 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[65] : + coreFix_aluExe_0_bypassWire_0$wget[65] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16434 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[65] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16433 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16446 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[64:63] : + coreFix_aluExe_0_bypassWire_0$wget[64:63] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16447 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[64:63] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16446 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16459 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[62:45] : + coreFix_aluExe_0_bypassWire_0$wget[62:45] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16460 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[62:45] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16459 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16474 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[44] : + coreFix_aluExe_0_bypassWire_0$wget[44] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16475 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[44] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16474 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16487 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[43:10] : + coreFix_aluExe_0_bypassWire_0$wget[43:10] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16488 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[43:10] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16487 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16505 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[9:7] : + coreFix_aluExe_0_bypassWire_0$wget[9:7] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16506 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[9:7] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16505 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16519 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[6] : + coreFix_aluExe_0_bypassWire_0$wget[6] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16520 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[6] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16519 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16532 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[5] : + coreFix_aluExe_0_bypassWire_0$wget[5] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16533 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[5] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16532 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16546 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[4] : + coreFix_aluExe_0_bypassWire_0$wget[4] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16547 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[4] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16546 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16568 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? + coreFix_aluExe_0_bypassWire_1$wget[3:0] : + coreFix_aluExe_0_bypassWire_0$wget[3:0] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16569 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626)) ? + coreFix_aluExe_0_bypassWire_2$wget[3:0] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16568 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16608 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15652) ? + coreFix_aluExe_0_bypassWire_1$wget[162:0] : + coreFix_aluExe_0_bypassWire_0$wget[162:0] ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16609 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15652) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15658)) ? + coreFix_aluExe_0_bypassWire_2$wget[162:0] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16608 ; + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12371 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12339) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8219 : + coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12352 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8239 = + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12372 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) && + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12339) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8219)) ? + !coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12352)) ? coreFix_fpuMulDivExe_0_bypassWire_2$whas && - coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8227 : - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8238 ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8240 = - NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230 ? + coreFix_fpuMulDivExe_0_bypassWire_2_wget__2358_ETC___d12360 : + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12371 ; + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12373 = + NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12363 ? coreFix_fpuMulDivExe_0_bypassWire_3$whas && - coreFix_aluExe_0_bypassWire_3$wget[70:64] == + coreFix_fpuMulDivExe_0_bypassWire_3$wget[70:64] == coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] : - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8239 ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8262 = + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12372 ; + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12395 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244) ? + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12377) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8250 : + coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12383 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8263 = + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12396 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244) && + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12377) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8250)) ? + !coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12383)) ? coreFix_fpuMulDivExe_0_bypassWire_2$whas && - coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8254 : - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8262 ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8264 = - NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8257 ? + coreFix_fpuMulDivExe_0_bypassWire_2_wget__2358_ETC___d12387 : + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12395 ; + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12397 = + NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12390 ? coreFix_fpuMulDivExe_0_bypassWire_3$whas && - coreFix_aluExe_0_bypassWire_3$wget[70:64] == + coreFix_fpuMulDivExe_0_bypassWire_3$wget[70:64] == coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] : - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8263 ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8286 = + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12396 ; + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12419 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268) ? + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12401) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8274 : + coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12407 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8287 = + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12420 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268) && + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12401) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8274)) ? + !coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12407)) ? coreFix_fpuMulDivExe_0_bypassWire_2$whas && - coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8278 : - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8286 ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8288 = - NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8281 ? + coreFix_fpuMulDivExe_0_bypassWire_2_wget__2358_ETC___d12411 : + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12419 ; + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12421 = + NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12414 ? coreFix_fpuMulDivExe_0_bypassWire_3$whas && - coreFix_aluExe_0_bypassWire_3$wget[70:64] == + coreFix_fpuMulDivExe_0_bypassWire_3$wget[70:64] == coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] : - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8287 ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8333 = + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12420 ; + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12467 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) ? - coreFix_aluExe_0_bypassWire_1$wget[63:0] : - coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334 = + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12339) ? + coreFix_fpuMulDivExe_0_bypassWire_1$wget[63:0] : + coreFix_fpuMulDivExe_0_bypassWire_0$wget[63:0] ; + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12468 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) && + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12339) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8219)) ? - coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8333 ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8344 = + !coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12352)) ? + coreFix_fpuMulDivExe_0_bypassWire_2$wget[63:0] : + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12467 ; + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12479 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244) ? - coreFix_aluExe_0_bypassWire_1$wget[63:0] : - coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345 = + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12377) ? + coreFix_fpuMulDivExe_0_bypassWire_1$wget[63:0] : + coreFix_fpuMulDivExe_0_bypassWire_0$wget[63:0] ; + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12480 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244) && + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12377) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8250)) ? - coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8344 ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8355 = + !coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12383)) ? + coreFix_fpuMulDivExe_0_bypassWire_2$wget[63:0] : + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12479 ; + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12491 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268) ? - coreFix_aluExe_0_bypassWire_1$wget[63:0] : - coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8356 = + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12401) ? + coreFix_fpuMulDivExe_0_bypassWire_1$wget[63:0] : + coreFix_fpuMulDivExe_0_bypassWire_0$wget[63:0] ; + assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12492 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268) && + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12401) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8274)) ? - coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8355 ; - assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1602 = + !coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12407)) ? + coreFix_fpuMulDivExe_0_bypassWire_2$wget[63:0] : + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12491 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2733 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) ? + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583 : + coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1603 = + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2734 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) && + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583)) ? + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? coreFix_memExe_bypassWire_2$whas && - coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591 : - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1602 ; - assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1604 = - NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ? + coreFix_memExe_bypassWire_2_wget__720_BITS_169_ETC___d2722 : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2733 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2735 = + NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? coreFix_memExe_bypassWire_3$whas && - coreFix_aluExe_0_bypassWire_3$wget[70:64] == - coreFix_memExe_dispToRegQ$first[61:55] : - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1603 ; - assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1626 = + coreFix_aluExe_0_bypassWire_3$wget[169:163] == + coreFix_memExe_dispToRegQ$first[108:102] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2734 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2757 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) ? + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614 : + coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1627 = + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2758 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) && + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614)) ? + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? coreFix_memExe_bypassWire_2$whas && - coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618 : - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1626 ; - assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628 = - NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ? + coreFix_memExe_bypassWire_2_wget__720_BITS_169_ETC___d2749 : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2757 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2759 = + NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? coreFix_memExe_bypassWire_3$whas && - coreFix_aluExe_0_bypassWire_3$wget[70:64] == - coreFix_memExe_dispToRegQ$first[53:47] : - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1627 ; - assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1647 = + coreFix_aluExe_0_bypassWire_3$wget[169:163] == + coreFix_memExe_dispToRegQ$first[100:94] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2758 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3018 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) ? - coreFix_aluExe_0_bypassWire_1$wget[63:0] : - coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 = + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[162] : + coreFix_aluExe_0_bypassWire_0$wget[162] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3019 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) && + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583)) ? - coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1647 ; - assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1658 = + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[162] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3018 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3031 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) ? - coreFix_aluExe_0_bypassWire_1$wget[63:0] : - coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 = + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[161:96] : + coreFix_aluExe_0_bypassWire_0$wget[161:96] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3032 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) && + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614)) ? - coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1658 ; - assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2082 = - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ? - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2054 : + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[161:96] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3031 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3051 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[95:82] : + coreFix_aluExe_0_bypassWire_0$wget[95:82] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3052 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[95:82] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3051 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3064 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[81:78] : + coreFix_aluExe_0_bypassWire_0$wget[81:78] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3065 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[81:78] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3064 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3077 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[77] : + coreFix_aluExe_0_bypassWire_0$wget[77] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3078 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[77] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3077 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3090 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[76] : + coreFix_aluExe_0_bypassWire_0$wget[76] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3091 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[76] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3090 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3103 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[75] : + coreFix_aluExe_0_bypassWire_0$wget[75] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3104 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[75] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3103 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3116 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[74] : + coreFix_aluExe_0_bypassWire_0$wget[74] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3117 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[74] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3116 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3129 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[73] : + coreFix_aluExe_0_bypassWire_0$wget[73] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3130 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[73] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3129 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3142 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[72] : + coreFix_aluExe_0_bypassWire_0$wget[72] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3143 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[72] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3142 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3155 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[71] : + coreFix_aluExe_0_bypassWire_0$wget[71] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3156 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[71] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3155 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3168 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[70] : + coreFix_aluExe_0_bypassWire_0$wget[70] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3169 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[70] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3168 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3181 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[69] : + coreFix_aluExe_0_bypassWire_0$wget[69] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3182 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[69] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3181 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3194 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[68] : + coreFix_aluExe_0_bypassWire_0$wget[68] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3195 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[68] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3194 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3207 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[67] : + coreFix_aluExe_0_bypassWire_0$wget[67] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3208 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[67] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3207 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3220 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[66] : + coreFix_aluExe_0_bypassWire_0$wget[66] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3221 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[66] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3220 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3239 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[65] : + coreFix_aluExe_0_bypassWire_0$wget[65] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3240 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[65] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3239 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3252 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[64:63] : + coreFix_aluExe_0_bypassWire_0$wget[64:63] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3253 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[64:63] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3252 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3265 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[62:45] : + coreFix_aluExe_0_bypassWire_0$wget[62:45] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3266 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[62:45] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3265 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3279 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[44] : + coreFix_aluExe_0_bypassWire_0$wget[44] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3280 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[44] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3279 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3292 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[43:10] : + coreFix_aluExe_0_bypassWire_0$wget[43:10] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3293 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[43:10] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3292 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3310 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[9:7] : + coreFix_aluExe_0_bypassWire_0$wget[9:7] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3311 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[9:7] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3310 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3324 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[6] : + coreFix_aluExe_0_bypassWire_0$wget[6] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3325 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[6] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3324 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3337 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[5] : + coreFix_aluExe_0_bypassWire_0$wget[5] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3338 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[5] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3337 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3351 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[4] : + coreFix_aluExe_0_bypassWire_0$wget[4] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3352 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[4] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3351 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3373 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? + coreFix_aluExe_0_bypassWire_1$wget[3:0] : + coreFix_aluExe_0_bypassWire_0$wget[3:0] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3374 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714)) ? + coreFix_aluExe_0_bypassWire_2$wget[3:0] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3373 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3392 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[162] : + coreFix_aluExe_0_bypassWire_0$wget[162] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3393 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[162] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3392 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3400 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[161:96] : + coreFix_aluExe_0_bypassWire_0$wget[161:96] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3401 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[161:96] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3400 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3408 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[95:82] : + coreFix_aluExe_0_bypassWire_0$wget[95:82] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3409 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[95:82] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3408 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3416 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[81:78] : + coreFix_aluExe_0_bypassWire_0$wget[81:78] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3417 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[81:78] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3416 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3424 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[77] : + coreFix_aluExe_0_bypassWire_0$wget[77] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3425 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[77] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3424 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3432 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[76] : + coreFix_aluExe_0_bypassWire_0$wget[76] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3433 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[76] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3432 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3440 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[75] : + coreFix_aluExe_0_bypassWire_0$wget[75] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3441 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[75] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3440 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3448 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[74] : + coreFix_aluExe_0_bypassWire_0$wget[74] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3449 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[74] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3448 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3456 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[73] : + coreFix_aluExe_0_bypassWire_0$wget[73] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3457 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[73] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3456 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3464 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[72] : + coreFix_aluExe_0_bypassWire_0$wget[72] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3465 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[72] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3464 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3472 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[71] : + coreFix_aluExe_0_bypassWire_0$wget[71] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3473 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[71] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3472 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3480 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[70] : + coreFix_aluExe_0_bypassWire_0$wget[70] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3481 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[70] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3480 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3488 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[69] : + coreFix_aluExe_0_bypassWire_0$wget[69] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3489 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[69] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3488 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3496 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[68] : + coreFix_aluExe_0_bypassWire_0$wget[68] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3497 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[68] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3496 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3504 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[67] : + coreFix_aluExe_0_bypassWire_0$wget[67] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3505 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[67] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3504 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3512 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[66] : + coreFix_aluExe_0_bypassWire_0$wget[66] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3513 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[66] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3512 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3526 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[65] : + coreFix_aluExe_0_bypassWire_0$wget[65] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3527 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[65] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3526 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3534 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[64:63] : + coreFix_aluExe_0_bypassWire_0$wget[64:63] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3535 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[64:63] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3534 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3542 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[62:45] : + coreFix_aluExe_0_bypassWire_0$wget[62:45] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3543 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[62:45] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3542 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3551 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[44] : + coreFix_aluExe_0_bypassWire_0$wget[44] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3552 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[44] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3551 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3559 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[43:10] : + coreFix_aluExe_0_bypassWire_0$wget[43:10] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3560 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[43:10] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3559 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3572 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[9:7] : + coreFix_aluExe_0_bypassWire_0$wget[9:7] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3573 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[9:7] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3572 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3581 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[6] : + coreFix_aluExe_0_bypassWire_0$wget[6] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3582 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[6] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3581 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3589 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[5] : + coreFix_aluExe_0_bypassWire_0$wget[5] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3590 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[5] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3589 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3598 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[4] : + coreFix_aluExe_0_bypassWire_0$wget[4] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3599 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[4] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3598 ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3615 = + (!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? + coreFix_aluExe_0_bypassWire_1$wget[3:0] : + coreFix_aluExe_0_bypassWire_0$wget[3:0] ; + assign IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3616 = + ((!coreFix_aluExe_0_bypassWire_0$whas || + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && + (!coreFix_aluExe_0_bypassWire_1$whas || + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745)) ? + coreFix_aluExe_0_bypassWire_2$wget[3:0] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3615 ; + assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d4995 = + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) ? + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d4973 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080 ; - assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2099 = - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] != + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d4993 ; + assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d5012 = + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520] != 2'd0 && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ? + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005) ? coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N : coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ; - assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2506 = - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ? - { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96], - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140, - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 } : - { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd3 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068) ? - { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516], - 4'd2 } : - { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96], - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516], - 1'd1, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] }, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ; - assign IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 = - (!coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb$procResp[12]) ? - CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12 : - CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2603_260_ETC___d13656 = + assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d5480 = + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) ? + { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[221:169], + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5053, + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5470 } : + { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5478, + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:0] } ; + assign IF_NOT_fetchStage_pipelines_0_canDeq__0043_004_ETC___d21586 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13245) && + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d20997) && fetchStage$pipelines_1_canDeq) ? fetchStage$RDY_pipelines_1_first && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || + (fetchStage$pipelines_1_first[267:265] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - IF_fetchStage_RDY_pipelines_1_first__2613_AND__ETC___d13653 : + IF_fetchStage_RDY_pipelines_1_first__0053_AND__ETC___d21583 : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2603_260_ETC___d13664 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__0043_004_ETC___d21594 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13245) && + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d20997) && fetchStage$pipelines_1_canDeq) ? - IF_NOT_fetchStage_pipelines_1_first__2614_BITS_ETC___d13663 : + IF_NOT_fetchStage_pipelines_1_first__0054_BITS_ETC___d21593 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13661 ; - assign IF_NOT_fetchStage_pipelines_1_first__2614_BITS_ETC___d13586 = - (fetchStage$pipelines_1_first[194:192] == 3'd3 || - fetchStage$pipelines_1_first[194:192] == 3'd4) ? - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13569 : - ((fetchStage$pipelines_1_first[194:192] == 3'd2) ? - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13580 : - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - !fetchStage$pipelines_0_canDeq || + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21591 ; + assign IF_NOT_fetchStage_pipelines_0_first__0045_BITS_ETC___d21850 = + (fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 && + fetchStage$pipelines_0_first[267:265] == 3'd2 && + coreFix_memExe_rsMem$canEnq && + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 && + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21804) ? + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21807 : + { 1'h0, + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21810 } ; + assign IF_NOT_fetchStage_pipelines_1_first__0054_BITS_ETC___d21508 = + (fetchStage$pipelines_1_first[267:265] == 3'd3 || + fetchStage$pipelines_1_first[267:265] == 3'd4) ? + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21490 : + ((fetchStage$pipelines_1_first[267:265] == 3'd2) ? + (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - _0_OR_fetchStage_RDY_pipelines_0_first__2602_35_ETC___d13583) ; - assign IF_NOT_fetchStage_pipelines_1_first__2614_BITS_ETC___d13663 = - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13496 ? - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13650 || + (regRenamingTable_rename_0_canRename__0929_AND__ETC___d21500 || + NOT_regRenamingTable_rename_1_canRename__1062__ETC___d21477) : + _0_OR_NOT_fetchStage_pipelines_1_first__0054_BI_ETC___d21506) ; + assign IF_NOT_fetchStage_pipelines_1_first__0054_BITS_ETC___d21593 = + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21410 ? + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21580 || fetchStage$pipelines_0_canDeq && - (fetchStage$pipelines_0_first[194:192] != 3'd1 || + (fetchStage$pipelines_0_first[267:265] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 : + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21010 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21020 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13661 ; - assign IF_NOT_rob_deqPort_1_deq_data__4562_BIT_25_456_ETC___d14762 = + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21591 ; + assign IF_NOT_fetchStage_pipelines_1_first__0054_BITS_ETC___d22005 = + (fetchStage$pipelines_1_first[237:236] != 2'd0 && + fetchStage$pipelines_1_first[237:236] != 2'd1 && + fetchStage$pipelines_1_first[267:265] == 3'd2 && + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21944 && + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21952) ? + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21953 : + { 1'h0, + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21954 } ; + assign IF_NOT_renameStage_rg_m_halt_req_0072_BIT_4_00_ETC___d20765 = + (!renameStage_rg_m_halt_req[4] && + fetchStage_pipelines_0_first__0045_BIT_69_0074_ETC___d20559) ? + { 8'd106, + IF_IF_fetchStage_pipelines_0_first__0045_BIT_6_ETC___d20649 } : + { 9'd298, + IF_IF_renameStage_rg_m_halt_req_0072_BIT_4_007_ETC___d20763 } ; + assign IF_NOT_renameStage_rg_m_halt_req_0072_BIT_4_00_ETC___d20766 = + (!renameStage_rg_m_halt_req[4] && + NOT_fetchStage_pipelines_0_first__0045_BIT_69__ETC___d20504) ? + { 2'd0, + checkForException___d20432[10:5], + CASE_checkForException_0432_BITS_4_TO_0_0_chec_ETC__q256 } : + IF_NOT_renameStage_rg_m_halt_req_0072_BIT_4_00_ETC___d20765 ; + assign IF_NOT_rob_deqPort_1_deq_data__3158_BIT_25_315_ETC___d23391 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || - rob$deqPort_1_deq_data[167] || - rob$deqPort_1_deq_data[186:182] == 5'd0 || - rob$deqPort_1_deq_data[186:182] == 5'd21 || - rob$deqPort_1_deq_data[186:182] == 5'd17 || - rob$deqPort_1_deq_data[186:182] == 5'd18 || - rob$deqPort_1_deq_data[186:182] == 5'd13 || - rob$deqPort_1_deq_data[186:182] == 5'd16 || - rob$deqPort_1_deq_data[186:182] == 5'd15 || - rob$deqPort_1_deq_data[186:182] == 5'd19 || - rob$deqPort_1_deq_data[186:182] == 5'd20) ? + rob$deqPort_1_deq_data[274] || + rob$deqPort_1_deq_data[469:465] == 5'd0 || + rob$deqPort_1_deq_data[469:465] == 5'd26 || + rob$deqPort_1_deq_data[469:465] == 5'd22 || + rob$deqPort_1_deq_data[469:465] == 5'd23 || + rob$deqPort_1_deq_data[469:465] == 5'd17 || + rob$deqPort_1_deq_data[469:465] == 5'd18 || + rob$deqPort_1_deq_data[469:465] == 5'd21 || + rob$deqPort_1_deq_data[469:465] == 5'd20 || + rob$deqPort_1_deq_data[469:465] == 5'd24 || + rob$deqPort_1_deq_data[469:465] == 5'd25) ? rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] || rob$deqPort_1_deq_data[26] ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868 = - ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] == - 8'd0) ? - 9'd386 : - { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34[7], - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34 }) - - 9'd386 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369177 == 8'd255) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080) : - ((_theResult___fst_exp__h377862 == 8'd255) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093) ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369177 == 8'd255) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123) : - ((_theResult___fst_exp__h377862 == 8'd255) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130) ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[2] : - _theResult___fst_exp__h378410 == 8'd255 && - _theResult___fst_sfd__h378411 == 23'd0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[1] : - _theResult___fst_exp__h377862 == 8'd0 && - guard__h369785 != 2'b0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[0] : - _theResult___fst_exp__h377862 != 8'd255 && - guard__h369785 != 2'b0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260 = - ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] == - 8'd0) ? - 9'd386 : - { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69[7], - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69 }) - - 9'd386 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h414867 == 8'd255) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472) : - ((_theResult___fst_exp__h423552 == 8'd255) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485) ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h414867 == 8'd255) ? - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515) : - ((_theResult___fst_exp__h423552 == 8'd255) ? - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522) ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[2] : - _theResult___fst_exp__h424100 == 8'd255 && - _theResult___fst_sfd__h424101 == 23'd0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[1] : - _theResult___fst_exp__h423552 == 8'd0 && - guard__h415475 != 2'b0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[0] : - _theResult___fst_exp__h423552 != 8'd255 && - guard__h415475 != 2'b0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652 = - ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] == - 8'd0) ? - 9'd386 : - { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104[7], - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104 }) - - 9'd386 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h460555 == 8'd255) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864) : - ((_theResult___fst_exp__h469240 == 8'd255) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877) ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h460555 == 8'd255) ? - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907) : - ((_theResult___fst_exp__h469240 == 8'd255) ? - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914) ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[2] : - _theResult___fst_exp__h469788 == 8'd255 && - _theResult___fst_sfd__h469789 == 23'd0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[1] : - _theResult___fst_exp__h469240 == 8'd0 && - guard__h461163 != 2'b0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[0] : - _theResult___fst_exp__h469240 != 8'd255 && - guard__h461163 != 2'b0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411 = - ((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] == + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13079 = + ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] == 11'd0) ? 12'd3074 : - { SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172[10], - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172 }) - + { SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q151[10], + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q151 }) - 12'd3074 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10452 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 ? - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10404 : - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10450) : - coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10683 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 ? - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10669 : - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10681) : - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10878 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[2] : - _theResult___fst_exp__h517867 == 11'd2047 && - _theResult___fst_sfd__h517868 == 52'd0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10892 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[2] : - _theResult___fst_exp__h556668 == 11'd2047 && - _theResult___fst_sfd__h556669 == 52'd0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10907 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[2] : - _theResult___fst_exp__h595869 == 11'd2047 && - _theResult___fst_sfd__h595870 == 52'd0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10924 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[1] : - _theResult___fst_exp__h517084 == 11'd0 && - guard__h509094 != 2'b0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10936 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[1] : - _theResult___fst_exp__h555885 == 11'd0 && - guard__h547895 != 2'b0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10949 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[1] : - _theResult___fst_exp__h595086 == 11'd0 && - guard__h587096 != 2'b0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10966 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[0] : - _theResult___fst_exp__h517084 != 11'd2047 && - guard__h509094 != 2'b0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10978 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[0] : - _theResult___fst_exp__h555885 != 11'd2047 && - guard__h547895 != 2'b0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10991 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[0] : - _theResult___fst_exp__h595086 != 11'd2047 && - guard__h587096 != 2'b0 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938 = - ((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132[10], - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132 }) - - 12'd3074 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8979 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 ? - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d8931 : - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8977) : + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13120 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 ? + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? + IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13072 : + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13118) : + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9648 = - ((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] == + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13794 = + ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] == 11'd0) ? 12'd3074 : - { SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149[10], - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149 }) - + { SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q168[10], + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q168 }) - 12'd3074 ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9689 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 ? - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9641 : - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9687) : + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13835 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 ? + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? + IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13787 : + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13833) : + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] ; - assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9921 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 ? - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9907 : - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9919) : - !coreFix_fpuMulDivExe_0_regToExeQ$first[43] ; - assign IF_checkForException_2839_BIT_4_2840_THEN_IF_c_ETC___d12978 = - checkForException___d12839[4] ? - CASE_checkForException_2839_BITS_3_TO_0_0_chec_ETC__q226 : - 4'd2 ; - assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2077_ETC___d12109 = + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14069 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 ? + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? + IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14055 : + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14067) : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14042 ; + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14564 = + ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] == + 11'd0) ? + 12'd3074 : + { SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q191[10], + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q191 }) - + 12'd3074 ; + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14605 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 ? + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? + IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14557 : + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14603) : + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14838 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 ? + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? + IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14824 : + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14836) : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14811 ; + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15033 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[2] : + _theResult___fst_exp__h753406 == 11'd2047 && + _theResult___fst_sfd__h753407 == 52'd0 ; + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15047 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[2] : + _theResult___fst_exp__h792259 == 11'd2047 && + _theResult___fst_sfd__h792260 == 52'd0 ; + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15062 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[2] : + _theResult___fst_exp__h831563 == 11'd2047 && + _theResult___fst_sfd__h831564 == 52'd0 ; + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15079 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[1] : + _theResult___fst_exp__h752623 == 11'd0 && + guard__h744633 != 2'b0 ; + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15091 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[1] : + _theResult___fst_exp__h791476 == 11'd0 && + guard__h783486 != 2'b0 ; + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15104 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[1] : + _theResult___fst_exp__h830780 == 11'd0 && + guard__h822790 != 2'b0 ; + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15121 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[0] : + _theResult___fst_exp__h752623 != 11'd2047 && + guard__h744633 != 2'b0 ; + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15133 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[0] : + _theResult___fst_exp__h791476 != 11'd2047 && + guard__h783486 != 2'b0 ; + assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15146 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? + _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[0] : + _theResult___fst_exp__h830780 != 11'd2047 && + guard__h822790 != 2'b0 ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10374 = + ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83[7:0] == + 8'd0) ? + 9'd386 : + { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q88[7], + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q88 }) - + 9'd386 ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10601 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? + ((_theResult___fst_exp__h648007 == 8'd255) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586) : + ((_theResult___fst_exp__h656692 == 8'd255) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599) ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10638 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? + ((_theResult___fst_exp__h648007 == 8'd255) ? + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629) : + ((_theResult___fst_exp__h656692 == 8'd255) ? + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636) ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10734 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705[2] : + _theResult___fst_exp__h657240 == 8'd255 && + _theResult___fst_sfd__h657241 == 23'd0 ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10747 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705[1] : + _theResult___fst_exp__h656692 == 8'd0 && + guard__h648615 != 2'b0 ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10760 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705[0] : + _theResult___fst_exp__h656692 != 8'd255 && + guard__h648615 != 2'b0 ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11771 = + ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118[7:0] == + 8'd0) ? + 9'd386 : + { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q123[7], + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q123 }) - + 9'd386 ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11998 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? + ((_theResult___fst_exp__h693754 == 8'd255) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983) : + ((_theResult___fst_exp__h702439 == 8'd255) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996) ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12035 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? + ((_theResult___fst_exp__h693754 == 8'd255) ? + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026) : + ((_theResult___fst_exp__h702439 == 8'd255) ? + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033) ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12131 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102[2] : + _theResult___fst_exp__h702987 == 8'd255 && + _theResult___fst_sfd__h702988 == 23'd0 ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12144 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102[1] : + _theResult___fst_exp__h702439 == 8'd0 && + guard__h694362 != 2'b0 ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12157 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102[0] : + _theResult___fst_exp__h702439 != 8'd255 && + guard__h694362 != 2'b0 ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8977 = + ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48[7:0] == + 8'd0) ? + 9'd386 : + { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q53[7], + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q53 }) - + 9'd386 ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9204 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? + ((_theResult___fst_exp__h602258 == 8'd255) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189) : + ((_theResult___fst_exp__h610943 == 8'd255) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202) ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9241 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? + ((_theResult___fst_exp__h602258 == 8'd255) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232) : + ((_theResult___fst_exp__h610943 == 8'd255) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239) ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9337 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308[2] : + _theResult___fst_exp__h611491 == 8'd255 && + _theResult___fst_sfd__h611492 == 23'd0 ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9350 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308[1] : + _theResult___fst_exp__h610943 == 8'd0 && + guard__h602866 != 2'b0 ; + assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9363 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308[0] : + _theResult___fst_exp__h610943 != 8'd255 && + guard__h602866 != 2'b0 ; + assign IF_SEXT_coreFix_memExe_regToExeQ_first__633_BI_ETC___d4077 = + offset__h242559[63] ? + x__h242708[13:0] >= toBounds__h242587 && + repBoundBits__h242584 != + coreFix_memExe_regToExeQ$first[316:303] : + x__h242708[13:0] < toBoundsM1__h242588 ; + assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__8198_ETC___d18230 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101) ? + coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_aluExe_0_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || coreFix_aluExe_0_dispToRegQ$RDY_first ; - assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2077_ETC___d12143 = + assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__8198_ETC___d18264 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12140) ? + coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18261) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_aluExe_0_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || coreFix_aluExe_0_dispToRegQ$RDY_first ; - assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1282_ETC___d11314 = + assign IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18412 = + (coreFix_aluExe_0_dispToRegQ$first[192:189] == 4'd2 || + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd3 && + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd4 && + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd5 && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18341 == + 4'd2) ? + { 4'd2, + (coreFix_aluExe_0_dispToRegQ$first[188:186] == 3'd0 || + coreFix_aluExe_0_dispToRegQ$first[188:186] != 3'd1 && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18370 == + 3'd0) ? + { 3'd0, coreFix_aluExe_0_dispToRegQ$first[185:184] } : + ((coreFix_aluExe_0_dispToRegQ$first[188:186] == 3'd1 || + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18370 == + 3'd1) ? + { 3'd1, coreFix_aluExe_0_dispToRegQ$first[185:184] } : + { CASE_IF_coreFix_aluExe_0_dispToRegQ_first__819_ETC__q246, + 2'h2 }) } : + ((coreFix_aluExe_0_dispToRegQ$first[192:189] == 4'd3 || + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd4 && + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd5 && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18341 == + 4'd3) ? + { 4'd3, coreFix_aluExe_0_dispToRegQ$first[188:184] } : + ((coreFix_aluExe_0_dispToRegQ$first[192:189] == 4'd4 || + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd5 && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18341 == + 4'd4) ? + 9'd138 : + ((coreFix_aluExe_0_dispToRegQ$first[192:189] == 4'd5 || + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18341 == + 4'd5) ? + { 4'd5, coreFix_aluExe_0_dispToRegQ$first[188:184] } : + { CASE_IF_coreFix_aluExe_0_dispToRegQ_first__819_ETC__q247, + 5'h0A }))) ; + assign IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18413 = + (coreFix_aluExe_0_dispToRegQ$first[192:189] == 4'd1 || + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd2 && + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd3 && + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd4 && + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd5 && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18341 == + 4'd1) ? + { 4'd1, coreFix_aluExe_0_dispToRegQ$first[188:184] } : + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18412 ; + assign IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18414 = + (coreFix_aluExe_0_dispToRegQ$first[192:189] == 4'd0 || + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd1 && + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd2 && + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd3 && + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd4 && + coreFix_aluExe_0_dispToRegQ$first[192:189] != 4'd5 && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18341 == + 4'd0) ? + { 4'd0, coreFix_aluExe_0_dispToRegQ$first[188:184] } : + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18413 ; + assign IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18620 = + coreFix_aluExe_0_dispToRegQ$first[137] ? + res_address__h890733 : + ((coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18618 : + 66'd0) ; + assign IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18635 = + coreFix_aluExe_0_dispToRegQ$first[137] ? + res_addrBits__h890734 : + ((coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18633 : + 14'd0) ; + assign IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19194 = + { coreFix_aluExe_0_dispToRegQ$first[124] ? + thin_reserved__h896606 : + 2'd0, + coreFix_aluExe_0_dispToRegQ$first[124] ? + thin_otype__h896607 : + 18'd262143, + !coreFix_aluExe_0_dispToRegQ$first[124] || + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19182, + coreFix_aluExe_0_dispToRegQ$first[124] ? + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19191 : + 34'h344000000 } ; + assign IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19195 = + { coreFix_aluExe_0_dispToRegQ$first[124] ? + thin_perms_soft__h896782 : + 4'd0, + coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19040, + coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19049, + coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19058, + coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19067, + coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19076, + coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19085, + coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19094, + coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19103, + coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19112, + coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19121, + coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19130, + coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19139, + coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19154, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19194 } ; + assign IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19196 = + { coreFix_aluExe_0_dispToRegQ$first[124] ? + thin_address__h896602 : + 66'd0, + coreFix_aluExe_0_dispToRegQ$first[124] ? + thin_addrBits__h896603 : + 14'd0, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19195 } ; + assign IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19217 = + thin_bounds_topBits__h898008[13:11] < repBound__h898124 ; + assign IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19219 = + thin_bounds_baseBits__h898009[13:11] < repBound__h898124 ; + assign IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19222 = + thin_addrBits__h896603[13:11] < repBound__h898124 ; + assign IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19881 = + { (coreFix_aluExe_0_exeToFinQ$first[282] && + !coreFix_aluExe_0_exeToFinQ$first[294]) ? + (coreFix_aluExe_0_exeToFinQ_first__9735_BITS_14_ETC___d19778 ? + coreFix_aluExe_0_exeToFinQ$first[152:147] : + coreFix_aluExe_0_exeToFinQ$first[293:288]) : + coreFix_aluExe_0_exeToFinQ$first[293:288], + IF_IF_coreFix_aluExe_0_exeToFinQ_first__9735_B_ETC___d19880 } ; + assign IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19900 = + coreFix_aluExe_0_exeToFinQ$first[342] ? + { coreFix_aluExe_0_exeToFinQ$first[333:325], + coreFix_aluExe_0_exeToFinQ$first[341:339], + coreFix_aluExe_0_exeToFinQ$first[321:311], + coreFix_aluExe_0_exeToFinQ$first[338:336] } : + coreFix_aluExe_0_exeToFinQ$first[333:308] ; + assign IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19931 = + coreFix_aluExe_0_exeToFinQ$first[505] ? + { coreFix_aluExe_0_exeToFinQ$first[496:488], + coreFix_aluExe_0_exeToFinQ$first[504:502], + coreFix_aluExe_0_exeToFinQ$first[484:474], + coreFix_aluExe_0_exeToFinQ$first[501:499] } : + coreFix_aluExe_0_exeToFinQ$first[496:471] ; + assign IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19384 = + (coreFix_aluExe_0_regToExeQ$first[784:781] == 4'd2 || + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd3 && + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd4 && + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd5 && + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19313 == + 4'd2) ? + { 4'd2, + (coreFix_aluExe_0_regToExeQ$first[780:778] == 3'd0 || + coreFix_aluExe_0_regToExeQ$first[780:778] != 3'd1 && + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19342 == + 3'd0) ? + { 3'd0, coreFix_aluExe_0_regToExeQ$first[777:776] } : + ((coreFix_aluExe_0_regToExeQ$first[780:778] == 3'd1 || + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19342 == + 3'd1) ? + { 3'd1, coreFix_aluExe_0_regToExeQ$first[777:776] } : + { CASE_IF_coreFix_aluExe_0_regToExeQ_first__9257_ETC__q248, + 2'h2 }) } : + ((coreFix_aluExe_0_regToExeQ$first[784:781] == 4'd3 || + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd4 && + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd5 && + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19313 == + 4'd3) ? + { 4'd3, coreFix_aluExe_0_regToExeQ$first[780:776] } : + ((coreFix_aluExe_0_regToExeQ$first[784:781] == 4'd4 || + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd5 && + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19313 == + 4'd4) ? + 9'd138 : + ((coreFix_aluExe_0_regToExeQ$first[784:781] == 4'd5 || + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19313 == + 4'd5) ? + { 4'd5, coreFix_aluExe_0_regToExeQ$first[780:776] } : + { CASE_IF_coreFix_aluExe_0_regToExeQ_first__9257_ETC__q249, + 5'h0A }))) ; + assign IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19385 = + (coreFix_aluExe_0_regToExeQ$first[784:781] == 4'd1 || + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd2 && + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd3 && + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd4 && + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd5 && + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19313 == + 4'd1) ? + { 4'd1, coreFix_aluExe_0_regToExeQ$first[780:776] } : + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19384 ; + assign IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19386 = + (coreFix_aluExe_0_regToExeQ$first[784:781] == 4'd0 || + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd1 && + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd2 && + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd3 && + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd4 && + coreFix_aluExe_0_regToExeQ$first[784:781] != 4'd5 && + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19313 == + 4'd0) ? + { 4'd0, coreFix_aluExe_0_regToExeQ$first[780:776] } : + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19385 ; + assign IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d18039 = + (coreFix_aluExe_0_rsAlu$dispatchData[196:193] == 4'd2 || + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd3 && + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd4 && + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd5 && + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17968 == + 4'd2) ? + { 4'd2, + (coreFix_aluExe_0_rsAlu$dispatchData[192:190] == 3'd0 || + coreFix_aluExe_0_rsAlu$dispatchData[192:190] != 3'd1 && + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17997 == + 3'd0) ? + { 3'd0, coreFix_aluExe_0_rsAlu$dispatchData[189:188] } : + ((coreFix_aluExe_0_rsAlu$dispatchData[192:190] == 3'd1 || + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17997 == + 3'd1) ? + { 3'd1, coreFix_aluExe_0_rsAlu$dispatchData[189:188] } : + { CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__7_ETC__q244, + 2'h2 }) } : + ((coreFix_aluExe_0_rsAlu$dispatchData[196:193] == 4'd3 || + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd4 && + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd5 && + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17968 == + 4'd3) ? + { 4'd3, coreFix_aluExe_0_rsAlu$dispatchData[192:188] } : + ((coreFix_aluExe_0_rsAlu$dispatchData[196:193] == 4'd4 || + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd5 && + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17968 == + 4'd4) ? + 9'd138 : + ((coreFix_aluExe_0_rsAlu$dispatchData[196:193] == 4'd5 || + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17968 == + 4'd5) ? + { 4'd5, + coreFix_aluExe_0_rsAlu$dispatchData[192:188] } : + { CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__7_ETC__q245, + 5'h0A }))) ; + assign IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d18040 = + (coreFix_aluExe_0_rsAlu$dispatchData[196:193] == 4'd1 || + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd2 && + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd3 && + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd4 && + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd5 && + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17968 == + 4'd1) ? + { 4'd1, coreFix_aluExe_0_rsAlu$dispatchData[192:188] } : + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d18039 ; + assign IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d18041 = + (coreFix_aluExe_0_rsAlu$dispatchData[196:193] == 4'd0 || + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd1 && + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd2 && + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd3 && + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd4 && + coreFix_aluExe_0_rsAlu$dispatchData[196:193] != 4'd5 && + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17968 == + 4'd0) ? + { 4'd0, coreFix_aluExe_0_rsAlu$dispatchData[192:188] } : + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d18040 ; + assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__5589_ETC___d15621 = (coreFix_aluExe_1_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11306) ? + coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_aluExe_1_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || coreFix_aluExe_1_dispToRegQ$RDY_first ; - assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1282_ETC___d11348 = + assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__5589_ETC___d15655 = (coreFix_aluExe_1_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11345) ? + coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15652) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_aluExe_1_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || coreFix_aluExe_1_dispToRegQ$RDY_first ; - assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8214 = + assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15803 = + (coreFix_aluExe_1_dispToRegQ$first[192:189] == 4'd2 || + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd3 && + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd4 && + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd5 && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15732 == + 4'd2) ? + { 4'd2, + (coreFix_aluExe_1_dispToRegQ$first[188:186] == 3'd0 || + coreFix_aluExe_1_dispToRegQ$first[188:186] != 3'd1 && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15761 == + 3'd0) ? + { 3'd0, coreFix_aluExe_1_dispToRegQ$first[185:184] } : + ((coreFix_aluExe_1_dispToRegQ$first[188:186] == 3'd1 || + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15761 == + 3'd1) ? + { 3'd1, coreFix_aluExe_1_dispToRegQ$first[185:184] } : + { CASE_IF_coreFix_aluExe_1_dispToRegQ_first__559_ETC__q238, + 2'h2 }) } : + ((coreFix_aluExe_1_dispToRegQ$first[192:189] == 4'd3 || + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd4 && + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd5 && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15732 == + 4'd3) ? + { 4'd3, coreFix_aluExe_1_dispToRegQ$first[188:184] } : + ((coreFix_aluExe_1_dispToRegQ$first[192:189] == 4'd4 || + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd5 && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15732 == + 4'd4) ? + 9'd138 : + ((coreFix_aluExe_1_dispToRegQ$first[192:189] == 4'd5 || + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15732 == + 4'd5) ? + { 4'd5, coreFix_aluExe_1_dispToRegQ$first[188:184] } : + { CASE_IF_coreFix_aluExe_1_dispToRegQ_first__559_ETC__q239, + 5'h0A }))) ; + assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15804 = + (coreFix_aluExe_1_dispToRegQ$first[192:189] == 4'd1 || + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd2 && + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd3 && + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd4 && + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd5 && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15732 == + 4'd1) ? + { 4'd1, coreFix_aluExe_1_dispToRegQ$first[188:184] } : + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15803 ; + assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15805 = + (coreFix_aluExe_1_dispToRegQ$first[192:189] == 4'd0 || + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd1 && + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd2 && + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd3 && + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd4 && + coreFix_aluExe_1_dispToRegQ$first[192:189] != 4'd5 && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15732 == + 4'd0) ? + { 4'd0, coreFix_aluExe_1_dispToRegQ$first[188:184] } : + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15804 ; + assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16237 = + coreFix_aluExe_1_dispToRegQ$first[137] ? + res_address__h848496 : + ((coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16235 : + 66'd0) ; + assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16252 = + coreFix_aluExe_1_dispToRegQ$first[137] ? + res_addrBits__h848497 : + ((coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16250 : + 14'd0) ; + assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17090 = + { coreFix_aluExe_1_dispToRegQ$first[124] ? + thin_reserved__h857113 : + 2'd0, + coreFix_aluExe_1_dispToRegQ$first[124] ? + thin_otype__h857114 : + 18'd262143, + !coreFix_aluExe_1_dispToRegQ$first[124] || + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17065, + coreFix_aluExe_1_dispToRegQ$first[124] ? + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17087 : + 34'h344000000 } ; + assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17091 = + { coreFix_aluExe_1_dispToRegQ$first[124] ? + thin_perms_soft__h857361 : + 4'd0, + coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16728, + coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16750, + coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16772, + coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16794, + coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16816, + coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16838, + coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16860, + coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16882, + coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16904, + coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16926, + coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16948, + coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16970, + coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16998, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17090 } ; + assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17092 = + { coreFix_aluExe_1_dispToRegQ$first[124] ? + thin_address__h857109 : + 66'd0, + coreFix_aluExe_1_dispToRegQ$first[124] ? + thin_addrBits__h857110 : + 14'd0, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17091 } ; + assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17139 = + thin_bounds_topBits__h859107[13:11] < repBound__h859255 ; + assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17141 = + thin_bounds_baseBits__h859108[13:11] < repBound__h859255 ; + assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17144 = + thin_addrBits__h857110[13:11] < repBound__h859255 ; + assign IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17804 = + { (coreFix_aluExe_1_exeToFinQ$first[282] && + !coreFix_aluExe_1_exeToFinQ$first[294]) ? + (coreFix_aluExe_1_exeToFinQ_first__7657_BITS_14_ETC___d17701 ? + coreFix_aluExe_1_exeToFinQ$first[152:147] : + coreFix_aluExe_1_exeToFinQ$first[293:288]) : + coreFix_aluExe_1_exeToFinQ$first[293:288], + IF_IF_coreFix_aluExe_1_exeToFinQ_first__7657_B_ETC___d17803 } ; + assign IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17823 = + coreFix_aluExe_1_exeToFinQ$first[342] ? + { coreFix_aluExe_1_exeToFinQ$first[333:325], + coreFix_aluExe_1_exeToFinQ$first[341:339], + coreFix_aluExe_1_exeToFinQ$first[321:311], + coreFix_aluExe_1_exeToFinQ$first[338:336] } : + coreFix_aluExe_1_exeToFinQ$first[333:308] ; + assign IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17854 = + coreFix_aluExe_1_exeToFinQ$first[505] ? + { coreFix_aluExe_1_exeToFinQ$first[496:488], + coreFix_aluExe_1_exeToFinQ$first[504:502], + coreFix_aluExe_1_exeToFinQ$first[484:474], + coreFix_aluExe_1_exeToFinQ$first[501:499] } : + coreFix_aluExe_1_exeToFinQ$first[496:471] ; + assign IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17306 = + (coreFix_aluExe_1_regToExeQ$first[784:781] == 4'd2 || + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd3 && + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd4 && + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd5 && + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17235 == + 4'd2) ? + { 4'd2, + (coreFix_aluExe_1_regToExeQ$first[780:778] == 3'd0 || + coreFix_aluExe_1_regToExeQ$first[780:778] != 3'd1 && + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17264 == + 3'd0) ? + { 3'd0, coreFix_aluExe_1_regToExeQ$first[777:776] } : + ((coreFix_aluExe_1_regToExeQ$first[780:778] == 3'd1 || + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17264 == + 3'd1) ? + { 3'd1, coreFix_aluExe_1_regToExeQ$first[777:776] } : + { CASE_IF_coreFix_aluExe_1_regToExeQ_first__7179_ETC__q242, + 2'h2 }) } : + ((coreFix_aluExe_1_regToExeQ$first[784:781] == 4'd3 || + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd4 && + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd5 && + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17235 == + 4'd3) ? + { 4'd3, coreFix_aluExe_1_regToExeQ$first[780:776] } : + ((coreFix_aluExe_1_regToExeQ$first[784:781] == 4'd4 || + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd5 && + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17235 == + 4'd4) ? + 9'd138 : + ((coreFix_aluExe_1_regToExeQ$first[784:781] == 4'd5 || + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17235 == + 4'd5) ? + { 4'd5, coreFix_aluExe_1_regToExeQ$first[780:776] } : + { CASE_IF_coreFix_aluExe_1_regToExeQ_first__7179_ETC__q243, + 5'h0A }))) ; + assign IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17307 = + (coreFix_aluExe_1_regToExeQ$first[784:781] == 4'd1 || + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd2 && + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd3 && + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd4 && + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd5 && + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17235 == + 4'd1) ? + { 4'd1, coreFix_aluExe_1_regToExeQ$first[780:776] } : + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17306 ; + assign IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17308 = + (coreFix_aluExe_1_regToExeQ$first[784:781] == 4'd0 || + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd1 && + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd2 && + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd3 && + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd4 && + coreFix_aluExe_1_regToExeQ$first[784:781] != 4'd5 && + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17235 == + 4'd0) ? + { 4'd0, coreFix_aluExe_1_regToExeQ$first[780:776] } : + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17307 ; + assign IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15429 = + (coreFix_aluExe_1_rsAlu$dispatchData[196:193] == 4'd2 || + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd3 && + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd4 && + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd5 && + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15357 == + 4'd2) ? + { 4'd2, + (coreFix_aluExe_1_rsAlu$dispatchData[192:190] == 3'd0 || + coreFix_aluExe_1_rsAlu$dispatchData[192:190] != 3'd1 && + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15386 == + 3'd0) ? + { 3'd0, coreFix_aluExe_1_rsAlu$dispatchData[189:188] } : + ((coreFix_aluExe_1_rsAlu$dispatchData[192:190] == 3'd1 || + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15386 == + 3'd1) ? + { 3'd1, coreFix_aluExe_1_rsAlu$dispatchData[189:188] } : + { CASE_IF_coreFix_aluExe_1_rsAlu_dispatchData__5_ETC__q240, + 2'h2 }) } : + ((coreFix_aluExe_1_rsAlu$dispatchData[196:193] == 4'd3 || + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd4 && + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd5 && + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15357 == + 4'd3) ? + { 4'd3, coreFix_aluExe_1_rsAlu$dispatchData[192:188] } : + ((coreFix_aluExe_1_rsAlu$dispatchData[196:193] == 4'd4 || + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd5 && + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15357 == + 4'd4) ? + 9'd138 : + ((coreFix_aluExe_1_rsAlu$dispatchData[196:193] == 4'd5 || + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15357 == + 4'd5) ? + { 4'd5, + coreFix_aluExe_1_rsAlu$dispatchData[192:188] } : + { CASE_IF_coreFix_aluExe_1_rsAlu_dispatchData__5_ETC__q241, + 5'h0A }))) ; + assign IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15430 = + (coreFix_aluExe_1_rsAlu$dispatchData[196:193] == 4'd1 || + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd2 && + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd3 && + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd4 && + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd5 && + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15357 == + 4'd1) ? + { 4'd1, coreFix_aluExe_1_rsAlu$dispatchData[192:188] } : + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15429 ; + assign IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15431 = + (coreFix_aluExe_1_rsAlu$dispatchData[196:193] == 4'd0 || + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd1 && + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd2 && + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd3 && + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd4 && + coreFix_aluExe_1_rsAlu$dispatchData[196:193] != 4'd5 && + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15357 == + 4'd0) ? + { 4'd0, coreFix_aluExe_1_rsAlu$dispatchData[192:188] } : + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15430 ; + assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d12347 = (coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) ? + coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12339) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ; - assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8247 = + assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d12380 = (coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244) ? + coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12377) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ; - assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8271 = + assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d12404 = (coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268) ? + coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12401) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528 = + assign IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10642 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ? ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && @@ -20261,7 +24126,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6489) : + IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10603) : ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != @@ -20273,8 +24138,58 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6526) ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 = + IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10640) ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10603 = + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == + 11'd0) ? + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 ? + IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10571 : + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10573) : + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 ? + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10601 : + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10573) ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10640 = + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == + 11'd0) ? + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 ? + IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10621 : + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10622) : + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 ? + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10638 : + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10622) ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10709 = + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == + 11'd0) ? + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10691 : + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 && + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 && + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705[4] ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10720 = + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == + 11'd0) ? + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10716 : + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 && + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 && + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705[3] ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10736 = + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == + 11'd0) ? + NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d10728 : + !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 || + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10734 ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10749 = + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == + 11'd0) ? + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10743 : + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 && + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10747 ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10762 = + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == + 11'd0) ? + NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d10756 : + !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 || + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10760 ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ? @@ -20384,57 +24299,7 @@ module mkCore(CLK, 6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) : 6'd1) - 6'd1 ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6489 = - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == - 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457 : - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459) : - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487 : - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459) ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6526 = - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == - 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507 : - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508) : - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524 : - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508) ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590 = - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == - 11'd0) ? - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6572 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 && - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[4] ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6601 = - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == - 11'd0) ? - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6597 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 && - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[3] ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6617 = - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == - 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6609 : - !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 || - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615 ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6630 = - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == - 11'd0) ? - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6624 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 && - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643 = - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == - 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6637 : - !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 || - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641 ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 = + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ? @@ -20544,57 +24409,57 @@ module mkCore(CLK, 6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) : 6'd1) - 6'd1 ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5097 = + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9206 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065 : - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067) : - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095 : - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067) ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5134 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 ? + IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9174 : + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9176) : + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 ? + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9204 : + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9176) ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9243 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115 : - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116) : - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132 : - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116) ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5198 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 ? + IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9224 : + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9225) : + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 ? + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9241 : + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9225) ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9312 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5180 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 && - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[4] ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5209 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9294 : + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 && + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 && + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308[4] ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9323 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5205 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 && - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[3] ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5225 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9319 : + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 && + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 && + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308[3] ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9339 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217 : - !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 || - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223 ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5238 = + NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d9331 : + !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 || + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9337 ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9352 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5232 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 && - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9346 : + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 && + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9350 ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9365 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5245 : - !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 || - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249 ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 = + NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d9359 : + !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 || + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9363 ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ? @@ -20704,57 +24569,57 @@ module mkCore(CLK, 6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) : 6'd1) - 6'd1 ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7881 = + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12000 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849 : - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851) : - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879 : - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851) ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7918 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 ? + IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d11968 : + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11970) : + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 ? + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11998 : + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11970) ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12037 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899 : - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900) : - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916 : - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900) ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7982 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 ? + IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12018 : + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12019) : + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 ? + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12035 : + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12019) ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12106 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7964 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 && - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[4] ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7993 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d12088 : + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 && + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 && + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102[4] ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12117 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7989 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 && - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[3] ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8009 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d12113 : + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 && + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 && + _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102[3] ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12133 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8001 : - !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 || - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007 ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8022 = + NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d12125 : + !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 || + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12131 ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12146 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8016 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 && - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d12140 : + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 && + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12144 ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12159 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8029 : - !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 || - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033 ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136 = + NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d12153 : + !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 || + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12157 ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9245 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ? ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && @@ -20767,7 +24632,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5097) : + IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9206) : ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != @@ -20779,8 +24644,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5134) ; - assign IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920 = + IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9243) ; + assign IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12039 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ? ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && @@ -20793,7 +24658,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7881) : + IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12000) : ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != @@ -20805,1252 +24670,2732 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7918) ; - assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066 = + IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12037) ; + assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d12190 = (coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] == 2'd0) ? coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ; - assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125 = - IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066[31:0] ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 = - ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - (coreFix_fpuMulDivExe_0_regToExeQ$first[98] ? - 6'd2 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[97] ? - 6'd3 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[96] ? - 6'd4 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[95] ? - 6'd5 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[94] ? - 6'd6 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[93] ? - 6'd7 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[92] ? - 6'd8 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[91] ? - 6'd9 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[90] ? - 6'd10 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[89] ? - 6'd11 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[88] ? - 6'd12 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[87] ? - 6'd13 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[86] ? - 6'd14 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[85] ? - 6'd15 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[84] ? - 6'd16 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[83] ? - 6'd17 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[82] ? - 6'd18 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[81] ? - 6'd19 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[80] ? - 6'd20 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[79] ? - 6'd21 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[78] ? - 6'd22 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[77] ? - 6'd23 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[76] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10454 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 && - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0 || - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) && - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10109 : - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10452) ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10632 = - { (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h556680, - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 && - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) ? - _theResult___snd_fst_sfd__h518569 : - _theResult___fst_sfd__h556684 } ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10634 = - coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] : - { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10454, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10632 } ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10685 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 && - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0 || - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) && - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10657 : - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10683) ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10740 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 && - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 && - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10719[4] : - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 && - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[4] ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10781 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 && - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 && - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10760[4] : - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 && - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[4] ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10825 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 && - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 && - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804[4] : - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 && - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[4] ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10840 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 && - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 && - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10719[3] : - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 && - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[3] ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10850 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 && - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 && - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10760[3] : - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 && - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[3] ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10861 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 && - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 && - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804[3] : - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 && - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[3] ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10880 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 || - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 && - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10719[2] : - !SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 || - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10878 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10894 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 || - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 && - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10760[2] : - !SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 || - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10892 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10909 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 || - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 && - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804[2] : - !SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 || - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10907 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10926 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 && - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 || - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10719[1]) : - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 && - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10924 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10938 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 && - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 || - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10760[1]) : - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 && - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10936 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10951 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 && - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 || - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804[1]) : - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 && - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10949 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10968 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 || - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 && - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10719[0] : - !SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 || - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10966 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10980 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 || - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 && - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10760[0] : - !SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 || - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10978 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10993 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 || - !_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 && - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804[0] : - !SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 || - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10991 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8427 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4) ? - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393 && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406 : - coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3 || - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8425 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 = - ((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - (coreFix_fpuMulDivExe_0_regToExeQ$first[162] ? - 6'd2 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[161] ? - 6'd3 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[160] ? - 6'd4 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[159] ? - 6'd5 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[158] ? - 6'd6 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[157] ? - 6'd7 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[156] ? - 6'd8 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[155] ? - 6'd9 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[154] ? - 6'd10 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[153] ? - 6'd11 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[152] ? - 6'd12 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[151] ? - 6'd13 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[150] ? - 6'd14 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[149] ? - 6'd15 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[148] ? - 6'd16 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[147] ? - 6'd17 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[146] ? - 6'd18 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[145] ? - 6'd19 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[144] ? - 6'd20 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[143] ? - 6'd21 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[142] ? - 6'd22 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[141] ? - 6'd23 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[140] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8981 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 && - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0 || - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) && - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8636 : - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8979) ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9165 = - { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8981, - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h517879, - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 && - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) ? - _theResult___snd_fst_sfd__h479627 : - _theResult___fst_sfd__h517883 } ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9166 = + assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q144 = + IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d12190[31:0] ; + assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12563 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd4) ? + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12529 && + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12542 : + coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] != 3'd3 || + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12561 ; + assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13307 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9165 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 = - ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - (coreFix_fpuMulDivExe_0_regToExeQ$first[34] ? - 6'd2 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[33] ? - 6'd3 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[32] ? - 6'd4 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[31] ? - 6'd5 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[30] ? - 6'd6 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[29] ? - 6'd7 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[28] ? - 6'd8 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[27] ? - 6'd9 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[26] ? - 6'd10 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[25] ? - 6'd11 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[24] ? - 6'd12 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[23] ? - 6'd13 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[22] ? - 6'd14 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[21] ? - 6'd15 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[20] ? - 6'd16 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[19] ? - 6'd17 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[18] ? - 6'd18 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[17] ? - 6'd19 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[16] ? - 6'd20 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[15] ? - 6'd21 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[14] ? - 6'd22 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[13] ? - 6'd23 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[12] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9691 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 && - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0 || - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) && - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9346 : - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9689) ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869 = - { (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h595881, - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 && - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) ? - _theResult___snd_fst_sfd__h557770 : - _theResult___fst_sfd__h595885 } ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 = + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13306 ; + assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14017 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] : - { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9691, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869 } ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9923 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 && - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0 || - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) && - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? - !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9895 : - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9921) ; - assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9925 = + { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13837, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14015 } ; + assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14042 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43] ; + assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14073 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? { !coreFix_fpuMulDivExe_0_regToExeQ$first[75], coreFix_fpuMulDivExe_0_regToExeQ$first[74:12] } : - { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9923, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869 } ; - assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 = + { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14071, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14015 } ; + assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14787 = + coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] : + { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14607, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14785 } ; + assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14811 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; + assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19986 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h641103 : - w__h641098 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080 = - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + result__h913267 : + w__h913262 ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d4993 = + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068) ? - NOT_coreFix_memExe_respLrScAmoQ_full_948_949_A_ETC___d2078 : + (!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] || + !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979)) ? + NOT_coreFix_memExe_respLrScAmoQ_full_816_817_A_ETC___d4991 : coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2100 = - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5013 = + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068) ? - NOT_coreFix_memExe_respLrScAmoQ_full_948_949_A_ETC___d2078 : - IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2099 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2103 = + (!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] || + !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979)) ? + NOT_coreFix_memExe_respLrScAmoQ_full_816_817_A_ETC___d4991 : + IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d5012 ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5016 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState == 3'd1) ? coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite : - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2102 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194 = - { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == - 3'd7) ? - n___1__h195750 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == - 3'd6) ? - n___1__h195750 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == - 3'd5) ? - n___1__h195750 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == - 3'd4) ? - n___1__h195750 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199 = - { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194, - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == - 3'd3) ? - n___1__h195750 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == - 3'd2) ? - n___1__h195750 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204 = - { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199, - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == - 3'd1) ? - n___1__h195750 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == - 3'd0) ? - n___1__h195750 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517 = - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5015 ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5066 = + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:137] == + 16'd0) ? + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5062 : + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:137] == + 16'd65535 && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[136] ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5072 = + { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[163:162] == + 2'd3) ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5066 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515], + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[163:162] == + 2'd2) ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5066 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514], + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[163:162] == + 2'd1) ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5066 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[513] } ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5147 = + { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[135:128] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077[63:56], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[151] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[127:120] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077[55:48], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[150] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[119:112] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077[47:40], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[111:104] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077[39:32], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[148] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[103:96] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077[31:24], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:88] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077[23:16], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[146] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[87:80] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077[15:8], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[145] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[79:72] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077[7:0], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[144] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71:64] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113[63:56], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[143] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[63:56] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113[55:48], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[142] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[55:48] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113[47:40], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[141] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[47:40] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113[39:32], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[140] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[39:32] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113[31:24], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[139] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[31:24] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113[23:16], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[138] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[23:16] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113[15:8], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[137] ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[15:8] : + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113[7:0] } ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5151 = + { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[163:162] == + 2'd3) ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5147 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:384], + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[163:162] == + 2'd2) ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5147 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:256], + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[163:162] == + 2'd1) ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5147 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:128] } ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5153 = + { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5072, + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[163:162] == + 2'd0) ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5066 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[512], + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5151, + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[163:162] == + 2'd0) ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5147 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:0] } ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5478 = + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068) ? - { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516], + (!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] || + !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979)) ? + { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:520], + 4'd2 } : + { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[221:169], + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520], + 1'd1, + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] } ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5491 = + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3 && + (!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] || + !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979)) ? + { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:520], 4'd2, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } : - { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96], - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] != + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:0] } : + { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[221:169], + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520] != 2'd0 && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ? + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005) ? { 3'd1, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } : - { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516], + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] } : + { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520], 1'd1, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] }, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2519 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] }, + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:0] } ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5493 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState == 3'd1) ? - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0] : - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2518 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:0] : + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5492 ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5509 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState == 3'd1) ? 3'd5 : - ((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] != + ((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520] != 2'd0 && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ? + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005) ? 3'd2 : 3'd3) ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546 = + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5520 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState == 3'd1) ? - 58'h155555555555554 : - ((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] != + 59'h295555555555554 : + ((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520] != 2'd0 && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ? - { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571], + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005) ? + { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:576], 2'd0, - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:522], 1'd0 } : - { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571], - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516], - 53'h15555555555555 }) ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 = - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:576], + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520], + 54'h15555555555555 }) ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5540 = + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd2) ? - x__h194347 : - (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 ? - 64'd0 : - 64'd1) ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 = + { 1'd1, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5062, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113 } : + { 66'h20000000000000000, + IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d5538 } ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3] ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042 = + assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7222 = WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 = - _theResult_____2__h293741 == v__h293161 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 = + assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7303 = EN_dCacheToParent_fromP_enq ? - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[587] : + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[587] ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7316 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 = - _theResult_____2__h301737 == v__h296506 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 = + assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7338 = EN_dCacheToParent_fromP_enq ? - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3243 = - (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 && - (EN_dCacheToParent_fromP_enq ? - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] : - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582])) ? - { 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - EN_dCacheToParent_fromP_enq ? - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[65:0] : - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[65:0] } : - { EN_dCacheToParent_fromP_enq ? - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[581:518] : - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[581:518], - EN_dCacheToParent_fromP_enq ? - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[517:516] : - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[517:516], - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT || - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 || - (EN_dCacheToParent_fromP_enq ? - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[515] : - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[515]), - EN_dCacheToParent_fromP_enq ? - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h299371 } ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000 = - !MUX_flush_reservation$write_1__SEL_1 && + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[587] : + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[587] ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d5154 = + (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979) ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5153 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:0] ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d5538 = + (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979) ? + 64'd0 : + 64'd1 ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7185 = + !MUX_flush_reservation$write_1__SEL_2 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] : coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008 = - MUX_flush_reservation$write_1__SEL_1 ? + assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7193 = + MUX_flush_reservation$write_1__SEL_2 ? 58'h2AAAAAAAAAAAAAA : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] : coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0]) ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2043 = + assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d4962 = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3) ? !coreFix_memExe_respLrScAmoQ_full : !coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != 3'd1 || coreFix_memExe_stb$RDY_deq ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2045 = + assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d4964 = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd2) ? !coreFix_memExe_respLrScAmoQ_full : coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd4 || - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2043 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2046 = + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d4962 ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d4965 = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) ? !coreFix_memExe_memRespLdQ_full : - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2045 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2054 = - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2046 && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d4964 ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d4973 = + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d4965 && + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd4 || coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != 3'd1 || coreFix_memExe_stb$RDY_deq)) ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2102 = - (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023)) ? - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2054 : + assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5015 = + (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942)) ? + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d4973 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2100 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2104 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? - (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ? - IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2082 : + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5013 ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5017 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] ? + (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 ? + IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d4995 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite) : - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2103 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140 = - { (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <= - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82]) ? - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516], + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5016 ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5053 = + { (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520] <= + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[157:156]) ? + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[157:156] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2518 = - (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023)) ? - { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96], - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140, - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 } : - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2566 = - (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023)) ? - { 1'd1, - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 } : - 65'h10000000000000001 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2700 = - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] || - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696) ? + assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5492 = + (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942)) ? + { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[221:169], + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5053, + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5470 } : + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5491 ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5542 = + (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942)) ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5540 : + 130'h200000000000000000000000000000001 ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d6947 = + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575] || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6943) ? coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry : coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709 = - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] || - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696) ? - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:512] : - { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? + assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d6956 = + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575] || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6943) ? + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:516] : + { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:522], + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] ? 2'd0 : coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0], - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:512] } ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994 = - { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == - 3'd7) ? - n__h191675 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], - (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == - 3'd6) ? - n__h191675 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], - (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == - 3'd5) ? - n__h191675 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999 = - { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994, - (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == - 3'd4) ? - n__h191675 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], - (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == - 3'd3) ? - n__h191675 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004 = - { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999, - (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == - 3'd2) ? - n__h191675 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], - (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == - 3'd1) ? - n__h191675 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[83:82] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[83:82]) : - 2'd0 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[81:79] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[81:79]) : - 3'd0 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[6:3] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[6:3]) : - 4'd0 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519:516] } ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4914 = + { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166] == + 2'd3) ? + amoExec___d4904[128] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515], + (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166] == + 2'd2) ? + amoExec___d4904[128] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514], + (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166] == + 2'd1) ? + amoExec___d4904[128] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[513], + (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166] == + 2'd0) ? + amoExec___d4904[128] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[512] } ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4925 = + { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166] == + 2'd3) ? + amoExec___d4904[127:0] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:384], + (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166] == + 2'd2) ? + amoExec___d4904[127:0] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:256], + (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166] == + 2'd1) ? + amoExec___d4904[127:0] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:128], + (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166] == + 2'd0) ? + amoExec___d4904[127:0] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:0] } ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7018 = + { coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? + coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[221:158] : + coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[221:158], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7462 = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ? coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72] ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320 = + assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7475 = EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 = - _theResult_____2__h307731 == v__h307020 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 = + assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7546 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[583] : + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[583] ; + assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7559 = EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 = - _theResult_____2__h315585 == v__h310896 ; - assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443 = + assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7581 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? - !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : - !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ; - assign IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 = - (coreFix_memExe_dTlb$procResp[105:103] == 3'd3) ? - 4'd7 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] != 3'd2 && - coreFix_memExe_dTlb$procResp[105:103] != 3'd3 && - !coreFix_memExe_dTlb$procResp[12] : - !coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1796 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] != 3'd2 && - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 == - 4'd0 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 == - 4'd0 ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1800 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] != 3'd2 && - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 == - 4'd1 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 == - 4'd1 ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1804 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] != 3'd2 && - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 == - 4'd2 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 == - 4'd2 ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1808 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] != 3'd2 && - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 == - 4'd3 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 == - 4'd3 ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1812 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] != 3'd2 && - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 == - 4'd4 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 == - 4'd4 ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1816 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] == 3'd2 || - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 == - 4'd5 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 == - 4'd5 ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1820 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] != 3'd2 && - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 == - 4'd6 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 == - 4'd6 ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1824 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] != 3'd2 && - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 == - 4'd7 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 == - 4'd7 ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1828 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] != 3'd2 && - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 == - 4'd8 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 == - 4'd8 ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1832 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] != 3'd2 && - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 == - 4'd9 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 == - 4'd9 ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] != 3'd2 && - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 == - 4'd10 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 == - 4'd10 ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1840 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] != 3'd2 && - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 == - 4'd11 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 == - 4'd11 ; - assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1844 = - (!coreFix_memExe_dTlb$procResp[12] && - !coreFix_memExe_dTlb$procResp[110] && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ? - coreFix_memExe_dTlb$procResp[105:103] != 3'd2 && - IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 == - 4'd12 : - IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 == - 4'd12 ; - assign IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1578 = + !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[583] : + !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[583] ; + assign IF_coreFix_memExe_dTlb_procResp__239_BIT_277_5_ETC___d4553 = + ((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 : + !coreFix_memExe_dTlb$procResp[289]) && + ((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] != 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != 3'd3 && + !coreFix_memExe_dTlb$procResp[290] : + !coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496]) ; + assign IF_coreFix_memExe_dTlb_procResp__239_BIT_277_5_ETC___d4576 = + ((coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + coreFix_memExe_dTlb_procResp__239_BITS_141_TO__ETC___d4570 : + coreFix_memExe_dTlb$procResp[289]) || + ((!coreFix_memExe_dTlb$procResp[290] && + !coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548) ? + coreFix_memExe_dTlb$procResp[490:488] == 3'd2 || + coreFix_memExe_dTlb$procResp[490:488] == 3'd3 || + coreFix_memExe_dTlb$procResp[290] : + coreFix_memExe_dTlb$procResp[290] || + coreFix_memExe_dTlb$procResp[496]) ; + assign IF_coreFix_memExe_dispToRegQ_RDY_first__679_AN_ETC___d2709 = (coreFix_memExe_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) ? + coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_memExe_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; - assign IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611 = + assign IF_coreFix_memExe_dispToRegQ_RDY_first__679_AN_ETC___d2742 = (coreFix_memExe_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) ? + coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_memExe_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; - assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 = - _theResult_____2__h329154 == v__h328722 ; - assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739 = + assign IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3524 = + { (coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3421 : + 4'd0, + coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3429, + coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3437, + coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3445, + coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3453, + coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3461, + coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3469, + coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3477, + coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3485, + coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3493, + coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3501, + coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3509, + coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3517 } ; + assign IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3566 = + { (coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3547 : + 18'd262143, + !coreFix_memExe_dispToRegQ$first[101] || + coreFix_memExe_dispToRegQ$first[100:94] == 7'd0 || + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3556, + (coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3564 : + 34'h344000000 } ; + assign IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3568 = + { (coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3413 : + 14'd0, + IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3524, + coreFix_memExe_dispToRegQ_first__680_BIT_101_6_ETC___d3567 } ; + assign IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3623 = + { (coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3577 : + 3'd7, + !coreFix_memExe_dispToRegQ$first[101] || + coreFix_memExe_dispToRegQ$first[100:94] == 7'd0 || + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3586, + NOT_coreFix_memExe_dispToRegQ_first__680_BIT_1_ETC___d3622 } ; + assign IF_coreFix_memExe_dispToRegQ_first__680_BIT_12_ETC___d3058 = + coreFix_memExe_dispToRegQ$first[12] ? + res_addrBits__h235268 : + ((coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3056 : + 14'd0) ; + assign IF_coreFix_memExe_dispToRegQ_first__680_BIT_12_ETC___d3303 = + { coreFix_memExe_dispToRegQ$first[12] ? + res_address__h235267 : + x__h235690, + IF_coreFix_memExe_dispToRegQ_first__680_BIT_12_ETC___d3058, + coreFix_memExe_dispToRegQ$first[12] ? + 4'd0 : + ((coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3069 : + 4'd0), + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3082, + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3095, + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3108, + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3121, + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3134, + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3147, + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3160, + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3173, + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3186, + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3199, + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3212, + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3225, + !coreFix_memExe_dispToRegQ$first[12] && + coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3244, + coreFix_memExe_dispToRegQ$first[12] ? + 2'd0 : + ((coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3257 : + 2'd0), + coreFix_memExe_dispToRegQ$first[12] ? + 18'd262143 : + ((coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3270 : + 18'd262143), + coreFix_memExe_dispToRegQ$first[12] || + !coreFix_memExe_dispToRegQ$first[109] || + coreFix_memExe_dispToRegQ$first[108:102] == 7'd0 || + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3284, + coreFix_memExe_dispToRegQ$first[12] ? + 34'h344000000 : + ((coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3297 : + 34'h344000000) } ; + assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7846 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; - assign IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724 = + assign IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7833 = coreFix_memExe_forwardQ_enqReq_lat_0$whas ? - coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] : - coreFix_memExe_forwardQ_enqReq_rl[69] ; - assign IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377 = - coreFix_memExe_lsq$firstLd[94] ? - (coreFix_memExe_lsq$firstLd[92] ? + coreFix_memExe_forwardQ_enqReq_lat_0$wget[134] : + coreFix_memExe_forwardQ_enqReq_rl[134] ; + assign IF_coreFix_memExe_lsq_firstLd__498_BIT_111_509_ETC___d1911 = + coreFix_memExe_lsq$firstLd[111] ? + (coreFix_memExe_lsq$firstLd[109] ? { 48'd0, - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 } : - { {48{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359[15]}}, - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 }) : - (coreFix_memExe_lsq$firstLd[92] ? + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 } : + { {48{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885[15]}}, + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 }) : + (coreFix_memExe_lsq$firstLd[109] ? { 56'd0, - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 } : - { {56{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373[7]}}, - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 }) ; - assign IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 = - coreFix_memExe_lsq$firstLd[94] ? - (coreFix_memExe_lsq$firstLd[92] ? + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 } : + { {56{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907[7]}}, + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 }) ; + assign IF_coreFix_memExe_lsq_firstLd__498_BIT_111_509_ETC___d2077 = + coreFix_memExe_lsq$firstLd[111] ? + (coreFix_memExe_lsq$firstLd[109] ? { 48'd0, - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 } : - { {48{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407[15]}}, - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 }) : - (coreFix_memExe_lsq$firstLd[92] ? + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052 } : + { {48{SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052[15]}}, + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052 }) : + (coreFix_memExe_lsq$firstLd[109] ? { 56'd0, - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 } : - { {56{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420[7]}}, - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 }) ; - assign IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378 = - coreFix_memExe_lsq$firstLd[96] ? - (coreFix_memExe_lsq$firstLd[92] ? + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 } : + { {56{SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073[7]}}, + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 }) ; + assign IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d1912 = + coreFix_memExe_lsq$firstLd[113] ? + (coreFix_memExe_lsq$firstLd[109] ? { 32'd0, - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 } : - { {32{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348[31]}}, - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 }) : - IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377 ; - assign IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425 = - coreFix_memExe_lsq$firstLd[96] ? - (coreFix_memExe_lsq$firstLd[92] ? + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 } : + { {32{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872[31]}}, + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 }) : + IF_coreFix_memExe_lsq_firstLd__498_BIT_111_509_ETC___d1911 ; + assign IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d2078 = + coreFix_memExe_lsq$firstLd[113] ? + (coreFix_memExe_lsq$firstLd[109] ? { 32'd0, - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 } : - { {32{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398[31]}}, - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) : - IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ; - assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 = - _theResult_____2__h325929 == v__h325497 ; - assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645 = + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040 } : + { {32{SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040[31]}}, + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040 }) : + IF_coreFix_memExe_lsq_firstLd__498_BIT_111_509_ETC___d2077 ; + assign IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d1913 = + coreFix_memExe_lsq$firstLd[117] ? + CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_coreF_ETC__q32 : + IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d1912 ; + assign IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d2079 = + coreFix_memExe_lsq$firstLd[117] ? + CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_mmio__ETC__q34 : + IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d2078 ; + assign IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4231 = + { coreFix_memExe_lsq$getOrigBE[15] ? + pointer__h242569[3:0] != 4'd0 : + (coreFix_memExe_lsq$getOrigBE[7] ? + pointer__h242569[2:0] != 3'd0 : + (coreFix_memExe_lsq$getOrigBE[3] ? + pointer__h242569[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && + pointer__h242569[0])), + capChecks___d4142[11:5], + CASE_capChecks_142_BITS_4_TO_0_0_capChecks_142_ETC__q289, + prepareBoundsCheck___d4226 } ; + assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7764 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; - assign IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630 = + assign IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7751 = coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ? - coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] : - coreFix_memExe_memRespLdQ_enqReq_rl[69] ; - assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[83:82] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[83:82]) : - 2'd0 ; - assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[81:79] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[81:79]) : - 3'd0 ; - assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[6:3] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[6:3]) : - 4'd0 ; - assign IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3554 = + coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[134] : + coreFix_memExe_memRespLdQ_enqReq_rl[134] ; + assign IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999 = + coreFix_memExe_regToExeQ$first[102] ? + { coreFix_memExe_regToExeQ$first[93:85], + coreFix_memExe_regToExeQ$first[101:99], + coreFix_memExe_regToExeQ$first[81:71], + coreFix_memExe_regToExeQ$first[98:96] } : + coreFix_memExe_regToExeQ$first[93:68] ; + assign IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d7687 = coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ? - coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] : - coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; - assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = - csrf_minstret_ehr_data_lat_0$whas ? - rob$deqPort_0_deq_data[95:32] : - csrf_minstret_ehr_data_rl ; - assign IF_fetchStage_RDY_pipelines_0_first__2602_AND__ETC___d13214 = - fetchStage_RDY_pipelines_0_first__2602_AND_NOT_ETC___d13210 ? + coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[129] : + coreFix_memExe_respLrScAmoQ_enqReq_rl[129] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16632 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[152] : + csrf_mepcc_reg_data_rl[152] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16654 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[151:86] : + csrf_mepcc_reg_data_rl[151:86] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16676 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[85:72] : + csrf_mepcc_reg_data_rl[85:72] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16698 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[71:68] : + csrf_mepcc_reg_data_rl[71:68] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16720 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[67] : + csrf_mepcc_reg_data_rl[67] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16742 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[66] : + csrf_mepcc_reg_data_rl[66] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16764 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[65] : + csrf_mepcc_reg_data_rl[65] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16786 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[64] : + csrf_mepcc_reg_data_rl[64] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16808 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[63] : + csrf_mepcc_reg_data_rl[63] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16830 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[62] : + csrf_mepcc_reg_data_rl[62] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16852 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[61] : + csrf_mepcc_reg_data_rl[61] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16874 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[60] : + csrf_mepcc_reg_data_rl[60] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16896 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[59] : + csrf_mepcc_reg_data_rl[59] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16918 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[58] : + csrf_mepcc_reg_data_rl[58] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16940 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[57] : + csrf_mepcc_reg_data_rl[57] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16962 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[56] : + csrf_mepcc_reg_data_rl[56] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16990 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[55] : + csrf_mepcc_reg_data_rl[55] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17012 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[54:53] : + csrf_mepcc_reg_data_rl[54:53] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17034 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[52:35] : + csrf_mepcc_reg_data_rl[52:35] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17057 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[34] : + csrf_mepcc_reg_data_rl[34] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17079 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[33:0] : + csrf_mepcc_reg_data_rl[33:0] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17105 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[13:0] : + csrf_mepcc_reg_data_rl[13:0] ; + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17129 = + MUX_csrf_ie_vec_3$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[27:14] : + csrf_mepcc_reg_data_rl[27:14] ; + assign IF_csrf_mepcc_reg_read_wget__3098_BIT_34_3107__ETC___d23115 = + csrf_mepcc_reg_data_rl[34] ? + { csrf_mepcc_reg_data_rl[25:17], + csrf_mepcc_reg_data_rl[33:31], + csrf_mepcc_reg_data_rl[13:3], + csrf_mepcc_reg_data_rl[30:28] } : + csrf_mepcc_reg_data_rl[25:0] ; + assign IF_csrf_mtcc_reg_read__6624_BITS_149_TO_86_257_ETC___d22613 = + ((newAddrDiff__h997265 == 64'd0) ? + 2'd0 : + (csrf_mtcc_reg_read__6624_BITS_149_TO_86_2579_A_ETC___d22589 ? + 2'd3 : + 2'd1)) == + ((csrf_mtcc_reg_read__6624_BITS_85_TO_83_2597_UL_ETC___d22600 && + _0_CONCAT_csrf_mtcc_reg_read__6624_BITS_149_TO__ETC___d22604) ? + 2'd0 : + ((csrf_mtcc_reg_read__6624_BITS_85_TO_83_2597_UL_ETC___d22600 && + !_0_CONCAT_csrf_mtcc_reg_read__6624_BITS_149_TO__ETC___d22604) ? + 2'd1 : + ((!csrf_mtcc_reg_read__6624_BITS_85_TO_83_2597_UL_ETC___d22600 && + _0_CONCAT_csrf_mtcc_reg_read__6624_BITS_149_TO__ETC___d22604) ? + 2'd3 : + 2'd0))) ; + assign IF_csrf_mtcc_reg_read__6624_BITS_149_TO_86_257_ETC___d22616 = + IF_csrf_mtcc_reg_read__6624_BITS_149_TO_86_257_ETC___d22613 && + (newAddrDiff__h997265 == 64'd0 || + csrf_mtcc_reg_read__6624_BITS_149_TO_86_2579_A_ETC___d22589 || + newAddrDiff__h997265 == + _18446744073709551615_SL_csrf_mtcc_reg_read__66_ETC___d22592) ; + assign IF_csrf_mtcc_reg_read__6624_BITS_149_TO_86_257_ETC___d22638 = + ((newAddrDiff__h997609 == 64'd0) ? + 2'd0 : + (csrf_mtcc_reg_read__6624_BITS_149_TO_86_2579_A_ETC___d22622 ? + 2'd3 : + 2'd1)) == + ((csrf_mtcc_reg_read__6624_BITS_85_TO_83_2597_UL_ETC___d22600 && + _0_CONCAT_csrf_mtcc_reg_read__6624_BITS_149_TO__ETC___d22630) ? + 2'd0 : + ((csrf_mtcc_reg_read__6624_BITS_85_TO_83_2597_UL_ETC___d22600 && + !_0_CONCAT_csrf_mtcc_reg_read__6624_BITS_149_TO__ETC___d22630) ? + 2'd1 : + ((!csrf_mtcc_reg_read__6624_BITS_85_TO_83_2597_UL_ETC___d22600 && + _0_CONCAT_csrf_mtcc_reg_read__6624_BITS_149_TO__ETC___d22630) ? + 2'd3 : + 2'd0))) ; + assign IF_csrf_mtcc_reg_read__6624_BITS_149_TO_86_257_ETC___d22641 = + IF_csrf_mtcc_reg_read__6624_BITS_149_TO_86_257_ETC___d22638 && + (newAddrDiff__h997609 == 64'd0 || + csrf_mtcc_reg_read__6624_BITS_149_TO_86_2579_A_ETC___d22622 || + newAddrDiff__h997609 == + _18446744073709551615_SL_csrf_mtcc_reg_read__66_ETC___d22592) ; + assign IF_csrf_mtcc_reg_read__6624_BIT_86_2574_AND_NO_ETC___d22644 = + (csrf_mtcc_reg[86] && cause_interrupt__h992425) ? + (NOT_csrf_mtcc_reg_read__6624_BITS_33_TO_28_257_ETC___d22578 || + IF_csrf_mtcc_reg_read__6624_BITS_149_TO_86_257_ETC___d22616) && + csrf_mtcc_reg[152] : + (NOT_csrf_mtcc_reg_read__6624_BITS_33_TO_28_257_ETC___d22578 || + IF_csrf_mtcc_reg_read__6624_BITS_149_TO_86_257_ETC___d22641) && + csrf_mtcc_reg[152] ; + assign IF_csrf_mtcc_reg_read__6624_BIT_86_2574_AND_NO_ETC___d22678 = + (csrf_mtcc_reg[86] && cause_interrupt__h992425) ? + address__h996585 : + base__h996550 ; + assign IF_csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_c_ETC___d22649 = + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 ? + { IF_csrf_stcc_reg_read__6615_BIT_86_2497_AND_NO_ETC___d22569, + csrf_stcc_reg[71:56], + csrf_stcc_reg[54:53], + csrf_stcc_reg[55], + csrf_stcc_reg[52:34] } : + { IF_csrf_mtcc_reg_read__6624_BIT_86_2574_AND_NO_ETC___d22644, + csrf_mtcc_reg[71:56], + csrf_mtcc_reg[54:53], + csrf_mtcc_reg[55], + csrf_mtcc_reg[52:34] } ; + assign IF_csrf_rg_dpc_read__3776_BIT_34_3785_THEN_csr_ETC___d23793 = + csrf_rg_dpc[34] ? + { csrf_rg_dpc[25:17], + csrf_rg_dpc[33:31], + csrf_rg_dpc[13:3], + csrf_rg_dpc[30:28] } : + csrf_rg_dpc[25:0] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16623 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[152] : + csrf_sepcc_reg_data_rl[152] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16648 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[151:86] : + csrf_sepcc_reg_data_rl[151:86] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16670 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[85:72] : + csrf_sepcc_reg_data_rl[85:72] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16692 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[71:68] : + csrf_sepcc_reg_data_rl[71:68] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16714 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[67] : + csrf_sepcc_reg_data_rl[67] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16736 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[66] : + csrf_sepcc_reg_data_rl[66] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16758 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[65] : + csrf_sepcc_reg_data_rl[65] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16780 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[64] : + csrf_sepcc_reg_data_rl[64] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16802 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[63] : + csrf_sepcc_reg_data_rl[63] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16824 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[62] : + csrf_sepcc_reg_data_rl[62] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16846 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[61] : + csrf_sepcc_reg_data_rl[61] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16868 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[60] : + csrf_sepcc_reg_data_rl[60] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16890 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[59] : + csrf_sepcc_reg_data_rl[59] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16912 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[58] : + csrf_sepcc_reg_data_rl[58] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16934 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[57] : + csrf_sepcc_reg_data_rl[57] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16956 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[56] : + csrf_sepcc_reg_data_rl[56] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16984 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[55] : + csrf_sepcc_reg_data_rl[55] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17006 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[54:53] : + csrf_sepcc_reg_data_rl[54:53] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17028 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[52:35] : + csrf_sepcc_reg_data_rl[52:35] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17051 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[34] : + csrf_sepcc_reg_data_rl[34] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17073 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[33:0] : + csrf_sepcc_reg_data_rl[33:0] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17099 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[13:0] : + csrf_sepcc_reg_data_rl[13:0] ; + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17123 = + MUX_csrf_ie_vec_1$write_1__SEL_2 ? + csrf_sepcc_reg_data_lat_0$wget[27:14] : + csrf_sepcc_reg_data_rl[27:14] ; + assign IF_csrf_sepcc_reg_read_wget__3069_BIT_34_3078__ETC___d23086 = + csrf_sepcc_reg_data_rl[34] ? + { csrf_sepcc_reg_data_rl[25:17], + csrf_sepcc_reg_data_rl[33:31], + csrf_sepcc_reg_data_rl[13:3], + csrf_sepcc_reg_data_rl[30:28] } : + csrf_sepcc_reg_data_rl[25:0] ; + assign IF_csrf_stcc_reg_read__6615_BITS_149_TO_86_250_ETC___d22538 = + ((newAddrDiff__h996608 == 64'd0) ? + 2'd0 : + (csrf_stcc_reg_read__6615_BITS_149_TO_86_2502_A_ETC___d22514 ? + 2'd3 : + 2'd1)) == + ((csrf_stcc_reg_read__6615_BITS_85_TO_83_2522_UL_ETC___d22525 && + _0_CONCAT_csrf_stcc_reg_read__6615_BITS_149_TO__ETC___d22529) ? + 2'd0 : + ((csrf_stcc_reg_read__6615_BITS_85_TO_83_2522_UL_ETC___d22525 && + !_0_CONCAT_csrf_stcc_reg_read__6615_BITS_149_TO__ETC___d22529) ? + 2'd1 : + ((!csrf_stcc_reg_read__6615_BITS_85_TO_83_2522_UL_ETC___d22525 && + _0_CONCAT_csrf_stcc_reg_read__6615_BITS_149_TO__ETC___d22529) ? + 2'd3 : + 2'd0))) ; + assign IF_csrf_stcc_reg_read__6615_BITS_149_TO_86_250_ETC___d22541 = + IF_csrf_stcc_reg_read__6615_BITS_149_TO_86_250_ETC___d22538 && + (newAddrDiff__h996608 == 64'd0 || + csrf_stcc_reg_read__6615_BITS_149_TO_86_2502_A_ETC___d22514 || + newAddrDiff__h996608 == + _18446744073709551615_SL_csrf_stcc_reg_read__66_ETC___d22517) ; + assign IF_csrf_stcc_reg_read__6615_BITS_149_TO_86_250_ETC___d22563 = + ((newAddrDiff__h996952 == 64'd0) ? + 2'd0 : + (csrf_stcc_reg_read__6615_BITS_149_TO_86_2502_A_ETC___d22547 ? + 2'd3 : + 2'd1)) == + ((csrf_stcc_reg_read__6615_BITS_85_TO_83_2522_UL_ETC___d22525 && + _0_CONCAT_csrf_stcc_reg_read__6615_BITS_149_TO__ETC___d22555) ? + 2'd0 : + ((csrf_stcc_reg_read__6615_BITS_85_TO_83_2522_UL_ETC___d22525 && + !_0_CONCAT_csrf_stcc_reg_read__6615_BITS_149_TO__ETC___d22555) ? + 2'd1 : + ((!csrf_stcc_reg_read__6615_BITS_85_TO_83_2522_UL_ETC___d22525 && + _0_CONCAT_csrf_stcc_reg_read__6615_BITS_149_TO__ETC___d22555) ? + 2'd3 : + 2'd0))) ; + assign IF_csrf_stcc_reg_read__6615_BITS_149_TO_86_250_ETC___d22566 = + IF_csrf_stcc_reg_read__6615_BITS_149_TO_86_250_ETC___d22563 && + (newAddrDiff__h996952 == 64'd0 || + csrf_stcc_reg_read__6615_BITS_149_TO_86_2502_A_ETC___d22547 || + newAddrDiff__h996952 == + _18446744073709551615_SL_csrf_stcc_reg_read__66_ETC___d22517) ; + assign IF_csrf_stcc_reg_read__6615_BIT_86_2497_AND_NO_ETC___d22569 = + (csrf_stcc_reg[86] && cause_interrupt__h992425) ? + (NOT_csrf_stcc_reg_read__6615_BITS_33_TO_28_249_ETC___d22501 || + IF_csrf_stcc_reg_read__6615_BITS_149_TO_86_250_ETC___d22541) && + csrf_stcc_reg[152] : + (NOT_csrf_stcc_reg_read__6615_BITS_33_TO_28_249_ETC___d22501 || + IF_csrf_stcc_reg_read__6615_BITS_149_TO_86_250_ETC___d22566) && + csrf_stcc_reg[152] ; + assign IF_csrf_stcc_reg_read__6615_BIT_86_2497_AND_NO_ETC___d22677 = + (csrf_stcc_reg[86] && cause_interrupt__h992425) ? + address__h996535 : + base__h996496 ; + assign IF_fetchStage_RDY_pipelines_0_first__0042_AND__ETC___d20964 = + (fetchStage$RDY_pipelines_0_first && + (fetchStage$pipelines_0_first[267:265] != 3'd1 || + specTagManager$canClaim) && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958) ? fetchStage$RDY_pipelines_0_first : !regRenamingTable$rename_0_canRename || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_RDY_pipelines_1_first__2613_AND__ETC___d13588 = + assign IF_fetchStage_RDY_pipelines_1_first__0053_AND__ETC___d21510 = (fetchStage$RDY_pipelines_1_first && - (fetchStage$pipelines_1_first[194:192] == 3'd0 || - fetchStage$pipelines_1_first[194:192] == 3'd1)) ? + (fetchStage$pipelines_1_first[267:265] == 3'd0 || + fetchStage$pipelines_1_first[267:265] == 3'd1 || + fetchStage$pipelines_1_first[237:236] == 2'd0 || + fetchStage$pipelines_1_first[237:236] == 2'd1)) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13558 : + (SEL_ARR_fetchStage_pipelines_0_canDeq__0043_AN_ETC___d21447 || + fetchStage$pipelines_1_first[267:265] == 3'd1 && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21024 || + NOT_regRenamingTable_rename_1_canRename__1062__ETC___d21477) : fetchStage$RDY_pipelines_1_first && - IF_NOT_fetchStage_pipelines_1_first__2614_BITS_ETC___d13586 ; - assign IF_fetchStage_RDY_pipelines_1_first__2613_AND__ETC___d13653 = + IF_NOT_fetchStage_pipelines_1_first__0054_BITS_ETC___d21508 ; + assign IF_fetchStage_RDY_pipelines_1_first__0053_AND__ETC___d21583 = (fetchStage$RDY_pipelines_1_first && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - !fetchStage$pipelines_0_canDeq || - fetchStage$RDY_pipelines_0_first) && - fetchStage_RDY_pipelines_0_first__2602_AND_fet_ETC___d13277 && - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13496) ? - IF_fetchStage_RDY_pipelines_1_first__2613_AND__ETC___d13588 && - (IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13650 || + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21031 && + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21410) ? + IF_fetchStage_RDY_pipelines_1_first__0053_AND__ETC___d21510 && + (IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21580 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13701 = - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13694 || - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && + assign IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20268 = + (fetchStage$pipelines_0_first[235:232] == 4'd2 || + fetchStage$pipelines_0_first[235:232] != 4'd3 && + fetchStage$pipelines_0_first[235:232] != 4'd4 && + fetchStage$pipelines_0_first[235:232] != 4'd5 && + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20197 == + 4'd2) ? + { 4'd2, + (fetchStage$pipelines_0_first[231:229] == 3'd0 || + fetchStage$pipelines_0_first[231:229] != 3'd1 && + IF_fetchStage_pipelines_0_first__0045_BITS_231_ETC___d20226 == + 3'd0) ? + { 3'd0, fetchStage$pipelines_0_first[228:227] } : + ((fetchStage$pipelines_0_first[231:229] == 3'd1 || + IF_fetchStage_pipelines_0_first__0045_BITS_231_ETC___d20226 == + 3'd1) ? + { 3'd1, fetchStage$pipelines_0_first[228:227] } : + { CASE_IF_fetchStage_pipelines_0_first__0045_BIT_ETC__q250, + 2'h2 }) } : + ((fetchStage$pipelines_0_first[235:232] == 4'd3 || + fetchStage$pipelines_0_first[235:232] != 4'd4 && + fetchStage$pipelines_0_first[235:232] != 4'd5 && + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20197 == + 4'd3) ? + { 4'd3, fetchStage$pipelines_0_first[231:227] } : + ((fetchStage$pipelines_0_first[235:232] == 4'd4 || + fetchStage$pipelines_0_first[235:232] != 4'd5 && + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20197 == + 4'd4) ? + 9'd138 : + ((fetchStage$pipelines_0_first[235:232] == 4'd5 || + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20197 == + 4'd5) ? + { 4'd5, fetchStage$pipelines_0_first[231:227] } : + { CASE_IF_fetchStage_pipelines_0_first__0045_BIT_ETC__q251, + 5'h0A }))) ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20269 = + (fetchStage$pipelines_0_first[235:232] == 4'd1 || + fetchStage$pipelines_0_first[235:232] != 4'd2 && + fetchStage$pipelines_0_first[235:232] != 4'd3 && + fetchStage$pipelines_0_first[235:232] != 4'd4 && + fetchStage$pipelines_0_first[235:232] != 4'd5 && + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20197 == + 4'd1) ? + { 4'd1, fetchStage$pipelines_0_first[231:227] } : + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20268 ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20270 = + (fetchStage$pipelines_0_first[235:232] == 4'd0 || + fetchStage$pipelines_0_first[235:232] != 4'd1 && + fetchStage$pipelines_0_first[235:232] != 4'd2 && + fetchStage$pipelines_0_first[235:232] != 4'd3 && + fetchStage$pipelines_0_first[235:232] != 4'd4 && + fetchStage$pipelines_0_first[235:232] != 4'd5 && + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20197 == + 4'd0) ? + { 4'd0, fetchStage$pipelines_0_first[231:227] } : + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20269 ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_237_ETC___d20400 = + { CASE_fetchStagepipelines_0_first_BITS_237_TO__ETC__q255, + fetchStage$pipelines_0_first[226:181], + fetchStage_pipelines_0_first__0045_BIT_180_027_ETC___d20370, + fetchStage_pipelines_0_first__0045_BIT_167_037_ETC___d20394, + fetchStage$pipelines_0_first[161:129] } ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21813 = + { IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21801, + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21804 ? + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21807 : + { 1'h0, + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21810 } } ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20996 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) ? + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 : + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20995 ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21020 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) ? + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__096_ETC___d21013 && + (fetchStage$pipelines_0_first[267:265] != 3'd1 || + specTagManager$canClaim) && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958 : + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21019 ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21056 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) ? + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__096_ETC___d21013 || + fetchStage$pipelines_0_first[267:265] == 3'd1 && + !specTagManager$canClaim : + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21055 ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21527 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) ? + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__096_ETC___d21013 || + fetchStage$pipelines_0_first[267:265] == 3'd1 && + !specTagManager$canClaim || + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21517 : + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21526 ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21549 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) ? + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 : + fetchStage$pipelines_0_first[267:265] != 3'd2 || + coreFix_memExe_rsMem$canEnq && + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21568 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) ? + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 : + CASE_fetchStagepipelines_0_first_BITS_267_TO__ETC__q265 ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21623 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) ? + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 || + regRenamingTable$RDY_rename_0_getRename && + _0_OR_NOT_fetchStage_pipelines_0_first__0045_BI_ETC___d21606 : + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21622 ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21625 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) ? + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__096_ETC___d21013 : + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21055 ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21632 = + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21625 || fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[194:192] != 3'd1 || + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[267:265] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign IF_fetchStage_pipelines_0_first__2605_BIT_160__ETC___d13871 = - { fetchStage$pipelines_0_first[159:128], - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13859, - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13862 ? - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13865 : + assign IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21639 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) ? + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 : + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21055 ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21646 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) ? + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__096_ETC___d21013 && + (fetchStage$pipelines_0_first[267:265] != 3'd1 || + specTagManager$canClaim) : + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20995 ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21722 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) ? + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 : + fetchStage$pipelines_0_first[267:265] == 3'd2 && + (!coreFix_memExe_rsMem$canEnq || + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051) ; + assign IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21734 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) ? + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 : + CASE_fetchStagepipelines_0_first_BITS_267_TO__ETC__q271 ; + assign IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20801 = + fetchStage$pipelines_0_first[69] ? + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 : + (checkForException___d20432[13] ? + CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 : + 4'd2) ; + assign IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21216 = + (fetchStage$pipelines_1_first[235:232] == 4'd2 || + fetchStage$pipelines_1_first[235:232] != 4'd3 && + fetchStage$pipelines_1_first[235:232] != 4'd4 && + fetchStage$pipelines_1_first[235:232] != 4'd5 && + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21145 == + 4'd2) ? + { 4'd2, + (fetchStage$pipelines_1_first[231:229] == 3'd0 || + fetchStage$pipelines_1_first[231:229] != 3'd1 && + IF_fetchStage_pipelines_1_first__0054_BITS_231_ETC___d21174 == + 3'd0) ? + { 3'd0, fetchStage$pipelines_1_first[228:227] } : + ((fetchStage$pipelines_1_first[231:229] == 3'd1 || + IF_fetchStage_pipelines_1_first__0054_BITS_231_ETC___d21174 == + 3'd1) ? + { 3'd1, fetchStage$pipelines_1_first[228:227] } : + { CASE_IF_fetchStage_pipelines_1_first__0054_BIT_ETC__q259, + 2'h2 }) } : + ((fetchStage$pipelines_1_first[235:232] == 4'd3 || + fetchStage$pipelines_1_first[235:232] != 4'd4 && + fetchStage$pipelines_1_first[235:232] != 4'd5 && + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21145 == + 4'd3) ? + { 4'd3, fetchStage$pipelines_1_first[231:227] } : + ((fetchStage$pipelines_1_first[235:232] == 4'd4 || + fetchStage$pipelines_1_first[235:232] != 4'd5 && + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21145 == + 4'd4) ? + 9'd138 : + ((fetchStage$pipelines_1_first[235:232] == 4'd5 || + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21145 == + 4'd5) ? + { 4'd5, fetchStage$pipelines_1_first[231:227] } : + { CASE_IF_fetchStage_pipelines_1_first__0054_BIT_ETC__q260, + 5'h0A }))) ; + assign IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21217 = + (fetchStage$pipelines_1_first[235:232] == 4'd1 || + fetchStage$pipelines_1_first[235:232] != 4'd2 && + fetchStage$pipelines_1_first[235:232] != 4'd3 && + fetchStage$pipelines_1_first[235:232] != 4'd4 && + fetchStage$pipelines_1_first[235:232] != 4'd5 && + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21145 == + 4'd1) ? + { 4'd1, fetchStage$pipelines_1_first[231:227] } : + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21216 ; + assign IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21218 = + (fetchStage$pipelines_1_first[235:232] == 4'd0 || + fetchStage$pipelines_1_first[235:232] != 4'd1 && + fetchStage$pipelines_1_first[235:232] != 4'd2 && + fetchStage$pipelines_1_first[235:232] != 4'd3 && + fetchStage$pipelines_1_first[235:232] != 4'd4 && + fetchStage$pipelines_1_first[235:232] != 4'd5 && + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21145 == + 4'd0) ? + { 4'd0, fetchStage$pipelines_1_first[231:227] } : + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21217 ; + assign IF_fetchStage_pipelines_1_first__0054_BITS_237_ETC___d21348 = + { CASE_fetchStagepipelines_1_first_BITS_237_TO__ETC__q263, + fetchStage$pipelines_1_first[226:181], + fetchStage_pipelines_1_first__0054_BIT_180_122_ETC___d21318, + fetchStage_pipelines_1_first__0054_BIT_167_131_ETC___d21342, + fetchStage$pipelines_1_first[161:129] } ; + assign IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21957 = + { IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21951, + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21952 ? + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21953 : { 1'h0, - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13868 } } ; - assign IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866 = - fetchStage$pipelines_0_first[173] ? - IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805 : - 12'hCFF ; - assign IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d13074 = - (fetchStage$pipelines_0_first[68] || - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[12] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[13] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[14]) ? - IF_IF_fetchStage_pipelines_0_first__2605_BIT_6_ETC___d13029 : - CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633__ETC__q227 ; - assign IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13822 = - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13781 && - IF_fetchStage_RDY_pipelines_1_first__2613_AND__ETC___d13588 && - (IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13806 || - rob$RDY_enqPort_1_enq && - regRenamingTable$RDY_rename_1_claimRename && + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21954 } } ; + assign IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21580 = + (fetchStage$pipelines_1_first[267:265] == 3'd0 || + fetchStage$pipelines_1_first[267:265] == 3'd1 || + fetchStage$pipelines_1_first[237:236] == 2'd0 || + fetchStage$pipelines_1_first[237:236] == 2'd1) ? + !SEL_ARR_fetchStage_pipelines_0_canDeq__0043_AN_ETC___d21447 && + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21533 : + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21579 ; + assign IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21719 = + (fetchStage$pipelines_1_first[267:265] == 3'd0 || + fetchStage$pipelines_1_first[267:265] == 3'd1 || + fetchStage$pipelines_1_first[237:236] == 2'd0 || + fetchStage$pipelines_1_first[237:236] == 2'd1) ? + !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__004_ETC___d21680 || + regRenamingTable$RDY_rename_1_getRename && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__0927_1023_OR_NOT__ETC___d21685) && + _0_OR_NOT_fetchStage_pipelines_1_first__0054_BI_ETC___d21698 : + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21718 ; + assign IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21746 = + (fetchStage$pipelines_1_first[267:265] == 3'd0 || + fetchStage$pipelines_1_first[267:265] == 3'd1 || + fetchStage$pipelines_1_first[237:236] == 2'd0 || + fetchStage$pipelines_1_first[237:236] == 2'd1) ? + SEL_ARR_fetchStage_pipelines_0_canDeq__0043_AN_ETC___d21447 : + CASE_fetchStagepipelines_1_first_BITS_267_TO__ETC__q272 ; + assign IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21762 = + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21719 && + IF_fetchStage_RDY_pipelines_1_first__0053_AND__ETC___d21510 && + (IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21746 || + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && - fetchStage_RDY_pipelines_1_deq__2617_AND_NOT_f_ETC___d13816) ; - assign IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d14039 = - (fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13986 && - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13993) ? - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13994 : - { 1'h0, - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13995 } ; - assign IF_fetchStage_pipelines_1_first__2614_BIT_160__ETC___d13998 = - { fetchStage$pipelines_1_first[159:128], - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13992, - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13993 ? - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13994 : - { 1'h0, - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13995 } } ; - assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 = + regRenamingTable$RDY_rename_1_claimRename && + rob_RDY_enqPort_1_enq__1748_AND_NOT_fetchStage_ETC___d21756) ; + assign IF_mmio_cRqQ_enqReq_lat_1_whas__87_THEN_mmio_c_ETC___d296 = mmio_cRqQ_enqReq_lat_0$whas ? - mmio_cRqQ_enqReq_lat_0$wget[142] : - mmio_cRqQ_enqReq_rl[142] ; - assign IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 = + mmio_cRqQ_enqReq_lat_0$wget[215] : + mmio_cRqQ_enqReq_rl[215] ; + assign IF_mmio_cRsQ_enqReq_lat_1_whas__85_THEN_mmio_c_ETC___d694 = CAN_FIRE_RL_mmio_handlePRq ? mmio_cRsQ_enqReq_lat_0$wget[1] : mmio_cRsQ_enqReq_rl[1] ; - assign IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 = + assign IF_mmio_dataReqQ_enqReq_lat_1_whas__2_THEN_mmi_ETC___d51 = mmio_dataReqQ_enqReq_lat_0$whas ? - mmio_dataReqQ_enqReq_lat_0$wget[142] : - mmio_dataReqQ_enqReq_rl[142] ; - assign IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 = + mmio_dataReqQ_enqReq_lat_0$wget[215] : + mmio_dataReqQ_enqReq_rl[215] ; + assign IF_mmio_dataRespQ_enqReq_lat_1_whas__73_THEN_m_ETC___d182 = CAN_FIRE_RL_mmio_sendDataResp ? - mmio_dataRespQ_enqReq_lat_0$wget[65] : - mmio_dataRespQ_enqReq_rl[65] ; - assign IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 = + mmio_dataRespQ_enqReq_lat_0$wget[130] : + mmio_dataRespQ_enqReq_rl[130] ; + assign IF_mmio_pRqQ_enqReq_lat_1_whas__56_THEN_mmio_p_ETC___d565 = EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[39] : mmio_pRqQ_enqReq_rl[39] ; - assign IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 = + assign IF_mmio_pRsQ_enqReq_lat_1_whas__15_THEN_mmio_p_ETC___d424 = EN_mmioToPlatform_pRs_enq ? - mmio_pRsQ_enqReq_lat_0$wget[67] : - mmio_pRsQ_enqReq_rl[67] ; - assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 = + mmio_pRsQ_enqReq_lat_0$wget[131] : + mmio_pRsQ_enqReq_rl[131] ; + assign IF_rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_f_ETC___d18946 = + { (rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18897 == + rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18924) ? + 2'd0 : + ((rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18897 && + !rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18924) ? + 2'd1 : + 2'd3), + (rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18910 == + rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18924) ? + 2'd0 : + ((rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18910 && + !rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18924) ? + 2'd1 : + 2'd3) } ; + assign IF_rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_f_ETC___d16563 = + { (rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16514 == + rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16541) ? + 2'd0 : + ((rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16514 && + !rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16541) ? + 2'd1 : + 2'd3), + (rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16527 == + rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16541) ? + 2'd0 : + ((rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16527 && + !rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16541) ? + 2'd1 : + 2'd3) } ; + assign IF_rf_read_3_rd1_coreFix_memExe_dispToRegQ_fir_ETC___d3368 = + { (rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3319 == + rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3346) ? + 2'd0 : + ((rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3319 && + !rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3346) ? + 2'd1 : + 2'd3), + (rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3332 == + rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3346) ? + 2'd0 : + ((rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3332 && + !rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3346) ? + 2'd1 : + 2'd3) } ; + assign IF_rf_read_3_rd2_coreFix_memExe_dispToRegQ_fir_ETC___d3614 = + { (rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3580 == + rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3597) ? + 2'd0 : + ((rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3580 && + !rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3597) ? + 2'd1 : + 2'd3), + (rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3588 == + rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3597) ? + 2'd0 : + ((rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3588 && + !rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3597) ? + 2'd1 : + 2'd3) } ; + assign IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23272 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h705148 : + y_avValue_snd_snd_snd_snd_snd__h1010138 : 64'd0 ; - assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h705132 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 = + assign IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23378 = + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1010122 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23400 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h705142 : + y_avValue_snd_snd_snd_fst__h1010132 : 2'd0 ; - assign IF_rob_deqPort_1_canDeq__4559_THEN_IF_NOT_rob__ETC___d14763 = + assign IF_rob_deqPort_1_canDeq__3155_THEN_IF_NOT_rob__ETC___d23392 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__4562_BIT_25_456_ETC___d14762 : + IF_NOT_rob_deqPort_1_deq_data__3158_BIT_25_315_ETC___d23391 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin08245_BIT_4_THEN_2_ELSE_0__q131 = - sfdin__h508245[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin14861_BIT_33_THEN_2_ELSE_0__q66 = - sfdin__h414861[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin42783_BIT_33_THEN_2_ELSE_0__q91 = - sfdin__h442783[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin47046_BIT_4_THEN_2_ELSE_0__q171 = - sfdin__h547046[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin51405_BIT_33_THEN_2_ELSE_0__q21 = - sfdin__h351405[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin60549_BIT_33_THEN_2_ELSE_0__q101 = - sfdin__h460549[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin69171_BIT_33_THEN_2_ELSE_0__q31 = - sfdin__h369171[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin86247_BIT_4_THEN_2_ELSE_0__q148 = - sfdin__h586247[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin97095_BIT_33_THEN_2_ELSE_0__q56 = - sfdin__h397095[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd05708_BIT_33_THEN_2_ELSE_0__q58 = - _theResult___snd__h405708[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd17030_BIT_4_THEN_2_ELSE_0__q134 = - _theResult___snd__h517030[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd23498_BIT_33_THEN_2_ELSE_0__q71 = - _theResult___snd__h423498[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd37426_BIT_4_THEN_2_ELSE_0__q167 = - _theResult___snd__h537426[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd51396_BIT_33_THEN_2_ELSE_0__q93 = - _theResult___snd__h451396[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd55831_BIT_4_THEN_2_ELSE_0__q174 = - _theResult___snd__h555831[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd60018_BIT_33_THEN_2_ELSE_0__q23 = - _theResult___snd__h360018[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd69186_BIT_33_THEN_2_ELSE_0__q106 = - _theResult___snd__h469186[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd76627_BIT_4_THEN_2_ELSE_0__q144 = - _theResult___snd__h576627[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd77808_BIT_33_THEN_2_ELSE_0__q36 = - _theResult___snd__h377808[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd95032_BIT_4_THEN_2_ELSE_0__q151 = - _theResult___snd__h595032[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd98625_BIT_4_THEN_2_ELSE_0__q127 = - _theResult___snd__h498625[4] ? 2'd2 : 2'd0 ; - assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217 = - !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 || - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[2] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[2]) ; - assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5245 = - !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 || - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[0] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[0]) ; - assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6609 = - !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 || - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[2] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[2]) ; - assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6637 = - !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 || - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[0] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[0]) ; - assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8001 = - !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 || - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[2] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[2]) ; - assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8029 = - !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 || - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[0] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[0]) ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_263_ETC___d13128 = - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[12] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[13] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[14] && - !checkForException___d12839[4] && - NOT_csrf_fs_reg_read__1491_EQ_0_2828_2829_OR_N_ETC___d13121 && - (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || - !csrf_tw_reg || - csrf_prv_reg == 2'd3) ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_263_ETC___d13202 = - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[12] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[13] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[14] && - !checkForException___d12839[4] && - NOT_csrf_fs_reg_read__1491_EQ_0_2828_2829_OR_N_ETC___d13200 ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_263_ETC___d13485 = - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[12] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[13] && - !IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[14] && - !checkForException___d13458[4] && - NOT_csrf_fs_reg_read__1491_EQ_0_2828_2829_OR_N_ETC___d13483 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__4555_4556_OR__ETC___d14768 = - (fflags__h705625 & csrf_fflags_reg) != fflags__h705625 || - !r__h608870 && - (IF_rob_deqPort_1_canDeq__4559_THEN_IF_NOT_rob__ETC___d14763 || - fflags__h705625 != 5'd0) ; - assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13263 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 && - (fetchStage$pipelines_0_first[194:192] != 3'd1 || - specTagManager$canClaim) && - regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207 ; - assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12125 = + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18564 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[152] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[162] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18560) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18618 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[151:86] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[161:96] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18614) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18633 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[85:72] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[95:82] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18629) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18646 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[71:68] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[81:78] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18642) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18659 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[67] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[77] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18655) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18672 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[66] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[76] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18668) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18685 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[65] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[75] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18681) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18698 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[64] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[74] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18694) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18711 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[63] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[73] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18707) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18724 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[62] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[72] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18720) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18737 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[61] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[71] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18733) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18750 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[60] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[70] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18746) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18763 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[59] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[69] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18759) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18776 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[58] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[68] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18772) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18789 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[57] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[67] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18785) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18802 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[56] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[66] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18798) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18821 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[55] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[65] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18817) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18834 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[54:53] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[64:63] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18830) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18847 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[52:35] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[62:45] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18843) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18862 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[34] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[44] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18858) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18875 = + sbCons$lazyLookup_0_get[3] ? + rf$read_0_rd1[33:0] : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[43:10] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18871) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18893 = + sbCons$lazyLookup_0_get[3] ? + repBound__h895779 : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[9:7] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18889) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18907 = + sbCons$lazyLookup_0_get[3] ? + rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18897 : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[6] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18903) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18920 = + sbCons$lazyLookup_0_get[3] ? + rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18910 : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[5] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18916) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18934 = + sbCons$lazyLookup_0_get[3] ? + rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18924 : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[4] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18930) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18956 = + sbCons$lazyLookup_0_get[3] ? + IF_rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_f_ETC___d18946 : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 ? + coreFix_aluExe_0_bypassWire_3$wget[3:0] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18952) ; + assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18996 = + sbCons$lazyLookup_0_get[2] ? + { rf$read_0_rd2, + repBound__h898106, + rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18968, + rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18969, + rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18981 } : + (NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18274 ? + coreFix_aluExe_0_bypassWire_3$wget[162:0] : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18992) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d15955 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[152] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[162] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15951) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16235 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[151:86] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[161:96] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16231) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16250 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[85:72] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[95:82] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16246) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16263 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[71:68] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[81:78] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16259) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16276 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[67] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[77] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16272) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16289 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[66] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[76] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16285) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16302 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[65] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[75] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16298) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16315 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[64] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[74] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16311) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16328 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[63] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[73] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16324) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16341 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[62] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[72] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16337) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16354 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[61] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[71] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16350) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16367 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[60] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[70] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16363) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16380 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[59] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[69] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16376) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16393 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[58] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[68] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16389) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16406 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[57] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[67] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16402) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16419 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[56] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[66] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16415) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16438 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[55] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[65] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16434) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16451 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[54:53] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[64:63] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16447) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16464 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[52:35] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[62:45] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16460) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16479 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[34] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[44] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16475) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16492 = + sbCons$lazyLookup_1_get[3] ? + rf$read_1_rd1[33:0] : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[43:10] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16488) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16510 = + sbCons$lazyLookup_1_get[3] ? + repBound__h855893 : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[9:7] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16506) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16524 = + sbCons$lazyLookup_1_get[3] ? + rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16514 : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[6] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16520) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16537 = + sbCons$lazyLookup_1_get[3] ? + rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16527 : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[5] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16533) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16551 = + sbCons$lazyLookup_1_get[3] ? + rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16541 : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[4] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16547) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16573 = + sbCons$lazyLookup_1_get[3] ? + IF_rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_f_ETC___d16563 : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? + coreFix_aluExe_0_bypassWire_3$wget[3:0] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16569) ; + assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16613 = + sbCons$lazyLookup_1_get[2] ? + { rf$read_1_rd2, + repBound__h859237, + rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16585, + rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16586, + rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16598 } : + (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15665 ? + coreFix_aluExe_0_bypassWire_3$wget[162:0] : + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16609) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3023 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[152] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[162] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3019) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3036 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[151:86] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[161:96] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3032) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3056 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[85:72] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[95:82] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3052) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3069 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[71:68] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[81:78] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3065) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3082 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[67] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[77] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3078) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3095 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[66] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[76] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3091) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3108 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[65] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[75] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3104) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3121 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[64] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[74] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3117) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3134 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[63] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[73] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3130) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3147 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[62] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[72] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3143) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3160 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[61] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[71] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3156) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3173 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[60] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[70] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3169) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3186 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[59] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[69] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3182) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3199 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[58] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[68] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3195) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3212 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[57] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[67] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3208) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3225 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[56] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[66] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3221) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3244 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[55] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[65] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3240) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3257 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[54:53] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[64:63] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3253) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3270 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[52:35] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[62:45] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3266) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3284 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[34] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[44] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3280) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3297 = + sbCons$lazyLookup_3_get[3] ? + rf$read_3_rd1[33:0] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[43:10] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3293) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3315 = + sbCons$lazyLookup_3_get[3] ? + repBound__h237262 : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[9:7] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3311) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3329 = + sbCons$lazyLookup_3_get[3] ? + rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3319 : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[6] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3325) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3342 = + sbCons$lazyLookup_3_get[3] ? + rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3332 : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[5] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3338) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3356 = + sbCons$lazyLookup_3_get[3] ? + rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3346 : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[4] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3352) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3378 = + sbCons$lazyLookup_3_get[3] ? + IF_rf_read_3_rd1_coreFix_memExe_dispToRegQ_fir_ETC___d3368 : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? + coreFix_aluExe_0_bypassWire_3$wget[3:0] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3374) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3397 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[152] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[162] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3393) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3405 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[151:86] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[161:96] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3401) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3413 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[85:72] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[95:82] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3409) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3421 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[71:68] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[81:78] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3417) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3429 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[67] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[77] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3425) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3437 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[66] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[76] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3433) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3445 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[65] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[75] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3441) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3453 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[64] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[74] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3449) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3461 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[63] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[73] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3457) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3469 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[62] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[72] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3465) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3477 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[61] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[71] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3473) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3485 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[60] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[70] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3481) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3493 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[59] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[69] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3489) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3501 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[58] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[68] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3497) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3509 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[57] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[67] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3505) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3517 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[56] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[66] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3513) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3531 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[55] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[65] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3527) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3539 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[54:53] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[64:63] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3535) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3547 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[52:35] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[62:45] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3543) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3556 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[34] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[44] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3552) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3564 = + sbCons$lazyLookup_3_get[2] ? + rf$read_3_rd2[33:0] : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[43:10] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3560) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3577 = + sbCons$lazyLookup_3_get[2] ? + repBound__h238947 : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[9:7] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3573) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3586 = + sbCons$lazyLookup_3_get[2] ? + rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3580 : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[6] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3582) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3594 = + sbCons$lazyLookup_3_get[2] ? + rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3588 : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[5] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3590) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3603 = + sbCons$lazyLookup_3_get[2] ? + rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3597 : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[4] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3599) ; + assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3620 = + sbCons$lazyLookup_3_get[2] ? + IF_rf_read_3_rd2_coreFix_memExe_dispToRegQ_fir_ETC___d3614 : + (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? + coreFix_aluExe_0_bypassWire_3$wget[3:0] : + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3616) ; + assign IF_sfdin02252_BIT_33_THEN_2_ELSE_0__q50 = + sfdin__h602252[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin21941_BIT_4_THEN_2_ELSE_0__q167 = + sfdin__h821941[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin30235_BIT_33_THEN_2_ELSE_0__q75 = + sfdin__h630235[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin43784_BIT_4_THEN_2_ELSE_0__q150 = + sfdin__h743784[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin48001_BIT_33_THEN_2_ELSE_0__q85 = + sfdin__h648001[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin75982_BIT_33_THEN_2_ELSE_0__q110 = + sfdin__h675982[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin82637_BIT_4_THEN_2_ELSE_0__q190 = + sfdin__h782637[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin84486_BIT_33_THEN_2_ELSE_0__q40 = + sfdin__h584486[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin93748_BIT_33_THEN_2_ELSE_0__q120 = + sfdin__h693748[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd02385_BIT_33_THEN_2_ELSE_0__q125 = + _theResult___snd__h702385[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd10889_BIT_33_THEN_2_ELSE_0__q55 = + _theResult___snd__h610889[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd12321_BIT_4_THEN_2_ELSE_0__q163 = + _theResult___snd__h812321[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd30726_BIT_4_THEN_2_ELSE_0__q170 = + _theResult___snd__h830726[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd34164_BIT_4_THEN_2_ELSE_0__q146 = + _theResult___snd__h734164[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd38848_BIT_33_THEN_2_ELSE_0__q77 = + _theResult___snd__h638848[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd52569_BIT_4_THEN_2_ELSE_0__q153 = + _theResult___snd__h752569[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd56638_BIT_33_THEN_2_ELSE_0__q90 = + _theResult___snd__h656638[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd73017_BIT_4_THEN_2_ELSE_0__q186 = + _theResult___snd__h773017[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd84595_BIT_33_THEN_2_ELSE_0__q112 = + _theResult___snd__h684595[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd91422_BIT_4_THEN_2_ELSE_0__q193 = + _theResult___snd__h791422[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd93099_BIT_33_THEN_2_ELSE_0__q42 = + _theResult___snd__h593099[33] ? 2'd2 : 2'd0 ; + assign INV_commitStage_commitTrap_BITS_217_TO_199__q15 = + ~commitStage_commitTrap[217:199] ; + assign INV_coreFix_aluExe_0_regToExeQ_first__9257_BIT_ETC___d19560 = + { ~coreFix_aluExe_0_regToExeQ$first[286:268], + INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? + x__h904028 : + 6'd0, + x__h904201, + x__h904221 } ; + assign INV_coreFix_aluExe_0_regToExeQ_first__9257_BIT_ETC___d19624 = + { ~coreFix_aluExe_0_regToExeQ$first[157:139], + INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? + x__h904576 : + 6'd0, + x__h904749, + x__h904769 } ; + assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14 = + ~coreFix_aluExe_0_regToExeQ$first[157:139] ; + assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13 = + ~coreFix_aluExe_0_regToExeQ$first[286:268] ; + assign INV_coreFix_aluExe_1_regToExeQ_first__7179_BIT_ETC___d17482 = + { ~coreFix_aluExe_1_regToExeQ$first[286:268], + INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? + x__h865547 : + 6'd0, + x__h865720, + x__h865740 } ; + assign INV_coreFix_aluExe_1_regToExeQ_first__7179_BIT_ETC___d17546 = + { ~coreFix_aluExe_1_regToExeQ$first[157:139], + INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? + x__h866095 : + 6'd0, + x__h866268, + x__h866288 } ; + assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12 = + ~coreFix_aluExe_1_regToExeQ$first[157:139] ; + assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11 = + ~coreFix_aluExe_1_regToExeQ$first[286:268] ; + assign INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10 = + ~coreFix_memExe_lsq$respLd[108:90] ; + assign INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8 = + ~coreFix_memExe_respLrScAmoQ_data_0[108:90] ; + assign INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9 = + ~mmio_dataRespQ_data_0[108:90] ; + assign INV_x83367_BITS_108_TO_90__q33 = ~x__h183367[108:90] ; + assign INV_x99219_BITS_108_TO_90__q35 = ~x__h199219[108:90] ; + assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d10728 = + !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 || + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10676[2] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10688[2]) ; + assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d10756 = + !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 || + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10676[0] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10688[0]) ; + assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d12125 = + !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 || + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12073[2] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12085[2]) ; + assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d12153 = + !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 || + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12073[0] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12085[0]) ; + assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d9331 = + !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 || + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9279[2] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9291[2]) ; + assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d9359 = + !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 || + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9279[0] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9291[0]) ; + assign NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_007_ETC___d20846 = + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15] && + !checkForException___d20432[13] && + NOT_csrf_fs_reg_read__5969_EQ_0_0418_0419_OR_N_ETC___d20844 ; + assign NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_007_ETC___d20951 = + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15] && + !checkForException___d20432[13] && + NOT_csrf_fs_reg_read__5969_EQ_0_0418_0419_OR_N_ETC___d20949 ; + assign NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_007_ETC___d21396 = + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15] && + !checkForException___d21369[13] && + NOT_csrf_fs_reg_read__5969_EQ_0_0418_0419_OR_N_ETC___d21394 ; + assign NOT_IF_NOT_rob_deqPort_0_canDeq__3151_3152_OR__ETC___d23397 = + (fflags__h1010644 & csrf_fflags_reg) != fflags__h1010644 || + !r__h852600 && + (IF_rob_deqPort_1_canDeq__3155_THEN_IF_NOT_rob__ETC___d23392 || + fflags__h1010644 != 5'd0) ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689 = + !f1_sfd__h714826[21] && !f1_sfd__h714826[20] && + !f1_sfd__h714826[19] && + !f1_sfd__h714826[18] && + !f1_sfd__h714826[17] && + !f1_sfd__h714826[16] && + !f1_sfd__h714826[15] && + !f1_sfd__h714826[14] && + !f1_sfd__h714826[13] && + !f1_sfd__h714826[12] && + !f1_sfd__h714826[11] && + !f1_sfd__h714826[10] && + !f1_sfd__h714826[9] && + !f1_sfd__h714826[8] && + !f1_sfd__h714826[7] && + !f1_sfd__h714826[6] && + !f1_sfd__h714826[5] && + !f1_sfd__h714826[4] && + !f1_sfd__h714826[3] && + !f1_sfd__h714826[2] && + !f1_sfd__h714826[1] && + !f1_sfd__h714826[0] ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419 = + !f3_sfd__h793124[21] && !f3_sfd__h793124[20] && + !f3_sfd__h793124[19] && + !f3_sfd__h793124[18] && + !f3_sfd__h793124[17] && + !f3_sfd__h793124[16] && + !f3_sfd__h793124[15] && + !f3_sfd__h793124[14] && + !f3_sfd__h793124[13] && + !f3_sfd__h793124[12] && + !f3_sfd__h793124[11] && + !f3_sfd__h793124[10] && + !f3_sfd__h793124[9] && + !f3_sfd__h793124[8] && + !f3_sfd__h793124[7] && + !f3_sfd__h793124[6] && + !f3_sfd__h793124[5] && + !f3_sfd__h793124[4] && + !f3_sfd__h793124[3] && + !f3_sfd__h793124[2] && + !f3_sfd__h793124[1] && + !f3_sfd__h793124[0] ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189 = + !f2_sfd__h753820[21] && !f2_sfd__h753820[20] && + !f2_sfd__h753820[19] && + !f2_sfd__h753820[18] && + !f2_sfd__h753820[17] && + !f2_sfd__h753820[16] && + !f2_sfd__h753820[15] && + !f2_sfd__h753820[14] && + !f2_sfd__h753820[13] && + !f2_sfd__h753820[12] && + !f2_sfd__h753820[11] && + !f2_sfd__h753820[10] && + !f2_sfd__h753820[9] && + !f2_sfd__h753820[8] && + !f2_sfd__h753820[7] && + !f2_sfd__h753820[6] && + !f2_sfd__h753820[5] && + !f2_sfd__h753820[4] && + !f2_sfd__h753820[3] && + !f2_sfd__h753820[2] && + !f2_sfd__h753820[1] && + !f2_sfd__h753820[0] ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14898 = + (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && + (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14895 ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14940 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14898 | + ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && + (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && + (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14936) ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14998 = + (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && + (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14995 ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15009 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14998 | + ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && + (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && + (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15005) ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15038 = + (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && + (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15035 ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15053 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15038 | + ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && + (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && + (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15049) ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15084 = + (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && + (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15081 ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15097 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15084 | + ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && + (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && + (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15093) ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15126 = + (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && + (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15123 ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15139 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15126 | + ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && + (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && + (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15135) ; + assign NOT_commitStage_commitTrap_2029_BITS_44_TO_43__ETC___d22295 = + commitStage_commitTrap[44:43] != 2'd0 && + commitStage_commitTrap[44:43] != 2'd1 && + commitStage_commitTrap[35:32] != 4'd0 && + commitStage_commitTrap[35:32] != 4'd1 && + commitStage_commitTrap[35:32] != 4'd3 && + commitStage_commitTrap[35:32] != 4'd4 && + commitStage_commitTrap[35:32] != 4'd5 && + commitStage_commitTrap[35:32] != 4'd7 && + commitStage_commitTrap[35:32] != 4'd8 && + commitStage_commitTrap[35:32] != 4'd9 && + commitStage_commitTrap[35:32] != 4'd11 || + commitStage_commitTrap[44:43] == 2'd1 && + commitStage_commitTrap[36:32] == 5'd3 && + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q274 ; + assign NOT_commitStage_commitTrap_2029_BITS_44_TO_43__ETC___d22296 = + NOT_commitStage_commitTrap_2029_BITS_44_TO_43__ETC___d22295 || + coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq ; + assign NOT_commitStage_rg_run_state_2027_2028_AND_NOT_ETC___d22806 = + !commitStage_rg_run_state && !commitStage_commitTrap[238] && + !rob$deqPort_0_deq_data[274] && + !rob$deqPort_0_deq_data[18] && + rob$deqPort_0_deq_data[25] ; + assign NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18246 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101) && + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12114) && + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235) && (!coreFix_aluExe_0_bypassWire_2$whas || - !coreFix_aluExe_0_bypassWire_2_wget__2120_BITS__ETC___d12122) ; - assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12153 = + !coreFix_aluExe_0_bypassWire_2_wget__8241_BITS__ETC___d18243) ; + assign NOT_coreFix_aluExe_0_bypassWire_0_whas__8219_8_ETC___d18274 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12140) && + !coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18261) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12146) && + !coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18267) && (!coreFix_aluExe_0_bypassWire_2$whas || - !coreFix_aluExe_0_bypassWire_2_wget__2120_BITS__ETC___d12150) ; - assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11330 = + !coreFix_aluExe_0_bypassWire_2_wget__8241_BITS__ETC___d18271) ; + assign NOT_coreFix_aluExe_0_dispToRegQ_first__8199_BI_ETC___d19236 = + { !coreFix_aluExe_0_dispToRegQ$first[124] || + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19217, + !coreFix_aluExe_0_dispToRegQ$first[124] || + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19219, + !coreFix_aluExe_0_dispToRegQ$first[124] || + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19222, + coreFix_aluExe_0_dispToRegQ$first[124] ? + IF_IF_coreFix_aluExe_0_dispToRegQ_first__8199__ETC___d19233 : + 4'd0 } ; + assign NOT_coreFix_aluExe_0_dispToRegQ_first__8199_BI_ETC___d19248 = + { !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18564, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18620, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18635, + coreFix_aluExe_0_dispToRegQ$first[137] ? + 4'd0 : + ((coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18646 : + 4'd0), + !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18659, + !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18672, + !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18685, + !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18698, + !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18711, + !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18724, + !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18737, + !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18750, + !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18763, + !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18776, + !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18789, + !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18802, + !coreFix_aluExe_0_dispToRegQ$first[137] && + coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18821, + coreFix_aluExe_0_dispToRegQ$first[137] ? + 2'd0 : + ((coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18834 : + 2'd0), + coreFix_aluExe_0_dispToRegQ$first[137] ? + 18'd262143 : + ((coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18847 : + 18'd262143), + coreFix_aluExe_0_dispToRegQ$first[137] || + !coreFix_aluExe_0_dispToRegQ$first[85] || + coreFix_aluExe_0_dispToRegQ$first[84:78] == 7'd0 || + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18862, + coreFix_aluExe_0_dispToRegQ$first[137] ? + 34'h344000000 : + ((coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18875 : + 34'h344000000), + coreFix_aluExe_0_dispToRegQ$first[137] ? + 3'd7 : + ((coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18893 : + 3'd7), + coreFix_aluExe_0_dispToRegQ$first[137] || + !coreFix_aluExe_0_dispToRegQ$first[85] || + coreFix_aluExe_0_dispToRegQ$first[84:78] == 7'd0 || + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18907, + coreFix_aluExe_0_dispToRegQ$first[137] || + !coreFix_aluExe_0_dispToRegQ$first[85] || + coreFix_aluExe_0_dispToRegQ$first[84:78] == 7'd0 || + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18920, + coreFix_aluExe_0_dispToRegQ$first[137] || + !coreFix_aluExe_0_dispToRegQ$first[85] || + coreFix_aluExe_0_dispToRegQ$first[84:78] == 7'd0 || + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18934, + coreFix_aluExe_0_dispToRegQ$first[137] ? + 4'd0 : + ((coreFix_aluExe_0_dispToRegQ$first[85] && + coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18956 : + 4'd0), + (coreFix_aluExe_0_dispToRegQ$first[77] && + coreFix_aluExe_0_dispToRegQ$first[76:70] != 7'd0) ? + IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18996 : + coreFix_aluExe_0_dispToRegQ_first__8199_BIT_12_ETC___d19237, + rob$getOrigPC_0_get, + rob$getOrigPredPC_0_get, + rob$getOrig_Inst_0_get, + coreFix_aluExe_0_dispToRegQ$first[16:12] } ; + assign NOT_coreFix_aluExe_0_exeToFinQ_first__9735_BIT_ETC___d19782 = + !coreFix_aluExe_0_exeToFinQ_first__9735_BITS_14_ETC___d19769 && + (coreFix_aluExe_0_exeToFinQ$first[17] ? + coreFix_aluExe_0_exeToFinQ_first__9735_BITS_82_ETC___d19773 : + coreFix_aluExe_0_exeToFinQ_first__9735_BITS_82_ETC___d19775) ; + assign NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11306) && + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_1_bypassWire_1_wget__1317_BITS__ETC___d11319) && + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626) && (!coreFix_aluExe_1_bypassWire_2$whas || - !coreFix_aluExe_1_bypassWire_2_wget__1325_BITS__ETC___d11327) ; - assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11358 = + !coreFix_aluExe_1_bypassWire_2_wget__5632_BITS__ETC___d15634) ; + assign NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15665 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11345) && + !coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15652) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_1_bypassWire_1_wget__1317_BITS__ETC___d11351) && + !coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15658) && (!coreFix_aluExe_1_bypassWire_2$whas || - !coreFix_aluExe_1_bypassWire_2_wget__1325_BITS__ETC___d11355) ; - assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230 = + !coreFix_aluExe_1_bypassWire_2_wget__5632_BITS__ETC___d15662) ; + assign NOT_coreFix_aluExe_1_dispToRegQ_first__5590_BI_ETC___d17158 = + { !coreFix_aluExe_1_dispToRegQ$first[124] || + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17139, + !coreFix_aluExe_1_dispToRegQ$first[124] || + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17141, + !coreFix_aluExe_1_dispToRegQ$first[124] || + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17144, + coreFix_aluExe_1_dispToRegQ$first[124] ? + IF_IF_coreFix_aluExe_1_dispToRegQ_first__5590__ETC___d17155 : + 4'd0 } ; + assign NOT_coreFix_aluExe_1_dispToRegQ_first__5590_BI_ETC___d17170 = + { !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d15955, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16237, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16252, + coreFix_aluExe_1_dispToRegQ$first[137] ? + 4'd0 : + ((coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16263 : + 4'd0), + !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16276, + !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16289, + !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16302, + !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16315, + !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16328, + !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16341, + !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16354, + !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16367, + !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16380, + !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16393, + !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16406, + !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16419, + !coreFix_aluExe_1_dispToRegQ$first[137] && + coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0 && + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16438, + coreFix_aluExe_1_dispToRegQ$first[137] ? + 2'd0 : + ((coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16451 : + 2'd0), + coreFix_aluExe_1_dispToRegQ$first[137] ? + 18'd262143 : + ((coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16464 : + 18'd262143), + coreFix_aluExe_1_dispToRegQ$first[137] || + !coreFix_aluExe_1_dispToRegQ$first[85] || + coreFix_aluExe_1_dispToRegQ$first[84:78] == 7'd0 || + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16479, + coreFix_aluExe_1_dispToRegQ$first[137] ? + 34'h344000000 : + ((coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16492 : + 34'h344000000), + coreFix_aluExe_1_dispToRegQ$first[137] ? + 3'd7 : + ((coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16510 : + 3'd7), + coreFix_aluExe_1_dispToRegQ$first[137] || + !coreFix_aluExe_1_dispToRegQ$first[85] || + coreFix_aluExe_1_dispToRegQ$first[84:78] == 7'd0 || + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16524, + coreFix_aluExe_1_dispToRegQ$first[137] || + !coreFix_aluExe_1_dispToRegQ$first[85] || + coreFix_aluExe_1_dispToRegQ$first[84:78] == 7'd0 || + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16537, + coreFix_aluExe_1_dispToRegQ$first[137] || + !coreFix_aluExe_1_dispToRegQ$first[85] || + coreFix_aluExe_1_dispToRegQ$first[84:78] == 7'd0 || + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16551, + coreFix_aluExe_1_dispToRegQ$first[137] ? + 4'd0 : + ((coreFix_aluExe_1_dispToRegQ$first[85] && + coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16573 : + 4'd0), + (coreFix_aluExe_1_dispToRegQ$first[77] && + coreFix_aluExe_1_dispToRegQ$first[76:70] != 7'd0) ? + IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16613 : + coreFix_aluExe_1_dispToRegQ_first__5590_BIT_12_ETC___d17159, + rob$getOrigPC_1_get, + rob$getOrigPredPC_1_get, + rob$getOrig_Inst_1_get, + coreFix_aluExe_1_dispToRegQ$first[16:12] } ; + assign NOT_coreFix_aluExe_1_exeToFinQ_first__7657_BIT_ETC___d17705 = + !coreFix_aluExe_1_exeToFinQ_first__7657_BITS_14_ETC___d17692 && + (coreFix_aluExe_1_exeToFinQ$first[17] ? + coreFix_aluExe_1_exeToFinQ_first__7657_BITS_82_ETC___d17696 : + coreFix_aluExe_1_exeToFinQ_first__7657_BITS_82_ETC___d17698) ; + assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12363 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) && + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12339) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8219) && + !coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12352) && (!coreFix_fpuMulDivExe_0_bypassWire_2$whas || - !coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8227) ; - assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8257 = + !coreFix_fpuMulDivExe_0_bypassWire_2_wget__2358_ETC___d12360) ; + assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12390 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244) && + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12377) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8250) && + !coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12383) && (!coreFix_fpuMulDivExe_0_bypassWire_2$whas || - !coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8254) ; - assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8281 = + !coreFix_fpuMulDivExe_0_bypassWire_2_wget__2358_ETC___d12387) ; + assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12414 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268) && + !coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12401) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8274) && + !coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12407) && (!coreFix_fpuMulDivExe_0_bypassWire_2$whas || - !coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8278) ; - assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 = + !coreFix_fpuMulDivExe_0_bypassWire_2_wget__2358_ETC___d12411) ; + assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9925 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] && !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] && !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] && @@ -22103,7 +27448,7 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] && !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] && !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ; - assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 = + assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8528 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] && !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] && !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] && @@ -22156,7 +27501,7 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] && !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] && !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ; - assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 = + assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11322 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] && !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] && !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] && @@ -22209,1646 +27554,1152 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] && !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] && !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ; - assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036 = - !coreFix_fpuMulDivExe_0_regToExeQ$first[97] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[96] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[95] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[94] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[93] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[92] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[91] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[90] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[89] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[88] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[87] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[86] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[85] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[84] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[83] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[82] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[81] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[80] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[79] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[78] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[77] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[76] ; - assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10743 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10740 ; - assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10785 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10743 | - ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10781) ; - assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10843 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10840 ; - assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10854 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10843 | - ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10850) ; - assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10883 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10880 ; - assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10898 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10883 | - ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10894) ; - assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10929 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10926 ; - assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10942 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10929 | - ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10938) ; - assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10971 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10968 ; - assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10984 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10971 | - ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10980) ; - assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548 = - !coreFix_fpuMulDivExe_0_regToExeQ$first[161] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[160] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[159] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[158] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[157] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[156] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[155] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[154] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[153] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[152] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[151] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[150] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[149] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[148] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[147] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[146] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[145] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[144] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[143] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[142] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[141] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[140] ; - assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273 = - !coreFix_fpuMulDivExe_0_regToExeQ$first[33] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[32] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[31] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[30] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[29] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[28] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[27] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[26] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[25] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[24] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[23] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[22] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[21] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[20] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[19] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[18] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[17] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[16] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[15] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[14] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[13] && - !coreFix_fpuMulDivExe_0_regToExeQ$first[12] ; - assign NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13597 = - !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[12] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[13] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[14] ; - assign NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 = + assign NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) && + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583) && + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714) && (!coreFix_memExe_bypassWire_2$whas || - !coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591) ; - assign NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 = + !coreFix_memExe_bypassWire_2_wget__720_BITS_169_ETC___d2722) ; + assign NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) && + !coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614) && + !coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745) && (!coreFix_memExe_bypassWire_2$whas || - !coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618) ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2522 = + !coreFix_memExe_bypassWire_2_wget__720_BITS_169_ETC___d2749) ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d5496 = (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != 3'd1) && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2662 = - (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != - 3'd1) && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d5626 = + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != 3'd3 || - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) && - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] != - 2'd0 && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 = - !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT || - !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3074 = - (!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT || - (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ? - !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] : - !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3])) && - (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042 || - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 = - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT || - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3179 = - (!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT || - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176) && - (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149 || - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty) ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 = - !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT || - !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT || - !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] || - !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2066 ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2119 = - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState == - 3'd1 || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != - 3'd4 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 || - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2529 = - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 || - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != - 3'd3 || - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2531 = - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState == - 3'd1 || - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2529) ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553 = - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd2 || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd3) || - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd3 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557 = - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 || - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd3 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2560 = - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != - 3'd1) && - (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2556 || - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557) ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2574 = - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 || - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2573 ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2577 = - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != - 3'd1) && - (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2556 || - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2574) ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2588 = - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != - 3'd4 || - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd3 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2594 = - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != - 3'd1) && - (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != - 3'd4 || - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557) ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2601 = - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != - 3'd1) && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd0 ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2626 = - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != - 3'd1) && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd1 ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2634 = - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != - 3'd1) && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd4 ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2642 = - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 || - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd3 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2651 = - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 || - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != - 3'd3 || - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) && - (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] == + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979) && + (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520] == 2'd0 || - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2673 = - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] || - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2046 && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005) ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d6759 = + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != + 3'd3 || + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520] != + 2'd0 && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5032 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState == + 3'd1 || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != + 3'd4 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5503 = + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != + 3'd3 || + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979) ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5505 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState == + 3'd1 || + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5503) ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5527 = + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2 || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3) || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5526 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5531 = + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3 && + (!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] || + !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979) ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5534 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5530 || + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5531) ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5550 = + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5549 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5553 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5530 || + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5550) ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5564 = + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != + 3'd4 || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5526 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5570 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != + 3'd4 || + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5531) ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5610 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd4 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5618 = + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5614 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5627 = + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 || + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d5626 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6328 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6326 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6331 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6329 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6339 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5559 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6348 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6758 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5531 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6761 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d6759 ; + assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6771 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] || + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d4965 && + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd4 || coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != 3'd1 || coreFix_memExe_stb$RDY_deq)) ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 = - !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT || - !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT || - !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT || - !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 = - !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT || - !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3351 = - (!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT || - (CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ? - !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] : - !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72])) && - (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320 || - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 = - !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT || - !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ; - assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3447 = - (!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT || - IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443) && - (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416 || - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty) ; - assign NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1879 = - !coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT || - !coreFix_memExe_dMem_perfReqQ_clearReq_rl ; - assign NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1923 = - (!coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT || - !coreFix_memExe_dMem_perfReqQ_enqReq_rl[4]) && - (coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT && - coreFix_memExe_dMem_perfReqQ_deqReq_rl || - coreFix_memExe_dMem_perfReqQ_empty) ; - assign NOT_coreFix_memExe_dTlb_procResp__712_BITS_174_ETC___d1751 = - !coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 && - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1723 && - !coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 && - !coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1730 ; - assign NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 = - !coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT || - !coreFix_memExe_forwardQ_clearReq_rl ; - assign NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3768 = - (!coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT || - (coreFix_memExe_forwardQ_enqReq_lat_0$whas ? - !coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] : - !coreFix_memExe_forwardQ_enqReq_rl[69])) && - (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739 || - coreFix_memExe_forwardQ_empty) ; - assign NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 = - !coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT || - !coreFix_memExe_memRespLdQ_clearReq_rl ; - assign NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3674 = - (!coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT || - (coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ? - !coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] : - !coreFix_memExe_memRespLdQ_enqReq_rl[69])) && - (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645 || - coreFix_memExe_memRespLdQ_empty) ; - assign NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473 = - !coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT || - !coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT || - !coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT || - !coreFix_memExe_reqLdQ_full_rl ; - assign NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 = - !coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT || - !coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT || - !coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT || - !coreFix_memExe_reqLrScAmoQ_full_rl ; - assign NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3543 = - !coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT || - !coreFix_memExe_respLrScAmoQ_clearReq_rl ; - assign NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3585 = - (!coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT || - (coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ? - !coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] : - !coreFix_memExe_respLrScAmoQ_enqReq_rl[64])) && - (coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT && - (coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas || - coreFix_memExe_respLrScAmoQ_deqReq_rl) || - coreFix_memExe_respLrScAmoQ_empty) ; - assign NOT_coreFix_memExe_respLrScAmoQ_full_948_949_A_ETC___d2078 = + assign NOT_coreFix_memExe_dTlb_procResp__239_BITS_141_ETC___d4534 = + !coreFix_memExe_dTlb_procResp__239_BITS_141_TO__ETC___d4529 && + (coreFix_memExe_dTlb$procResp[12] ? + coreFix_memExe_dTlb_procResp__239_BITS_77_TO_1_ETC___d4531 : + coreFix_memExe_dTlb_procResp__239_BITS_77_TO_1_ETC___d4532) ; + assign NOT_coreFix_memExe_dTlb_procResp__239_BITS_560_ETC___d4563 = + !coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4539 && + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4540 && + !coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4544 && + !coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4547 ; + assign NOT_coreFix_memExe_dispToRegQ_first__680_BIT_1_ETC___d3622 = + { !coreFix_memExe_dispToRegQ$first[101] || + coreFix_memExe_dispToRegQ$first[100:94] == 7'd0 || + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3594, + !coreFix_memExe_dispToRegQ$first[101] || + coreFix_memExe_dispToRegQ$first[100:94] == 7'd0 || + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3603, + (coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3620 : + 4'd0 } ; + assign NOT_coreFix_memExe_respLrScAmoQ_full_816_817_A_ETC___d4991 = !coreFix_memExe_respLrScAmoQ_full && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry && (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] || !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ; - assign NOT_coreFix_memExe_rsMem_canEnq__3231_3293_OR__ETC___d13598 = - !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296 || - fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[12] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[13] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[14] ; - assign NOT_csrf_fs_reg_read__1491_EQ_0_2828_2829_OR_N_ETC___d13121 = + assign NOT_csrf_fs_reg_read__5969_EQ_0_0418_0419_OR_N_ETC___d20844 = (csrf_fs_reg != 2'd0 || - (!fetchStage$pipelines_0_first[95] || - !fetchStage$pipelines_0_first[94]) && - (!fetchStage$pipelines_0_first[88] || - !fetchStage$pipelines_0_first[87]) && - !fetchStage$pipelines_0_first[81] && - (!fetchStage$pipelines_0_first[75] || - !fetchStage$pipelines_0_first[74])) && - (fetchStage$pipelines_0_first[199:195] != 5'd13 || - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13117 && - !csrf_prv_reg_read__2633_ULT_IF_fetchStage_pipe_ETC___d12871) ; - assign NOT_csrf_fs_reg_read__1491_EQ_0_2828_2829_OR_N_ETC___d13200 = - (csrf_fs_reg != 2'd0 || - (!fetchStage$pipelines_0_first[95] || - !fetchStage$pipelines_0_first[94]) && - (!fetchStage$pipelines_0_first[88] || - !fetchStage$pipelines_0_first[87]) && - !fetchStage$pipelines_0_first[81] && - (!fetchStage$pipelines_0_first[75] || - !fetchStage$pipelines_0_first[74])) && - (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || + (!fetchStage$pipelines_0_first[180] || + fetchStage$pipelines_0_first[179:168] != 12'd3 || + fetchStage$pipelines_0_first[272:268] != 5'd17) && + (!fetchStage$pipelines_0_first[96] || + !fetchStage$pipelines_0_first[95]) && + (!fetchStage$pipelines_0_first[89] || + !fetchStage$pipelines_0_first[88]) && + !fetchStage$pipelines_0_first[82] && + (!fetchStage$pipelines_0_first[76] || + !fetchStage$pipelines_0_first[75])) && + (fetchStage$pipelines_0_first[304:273] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_fs_reg_read__1491_EQ_0_2828_2829_OR_N_ETC___d13483 = + assign NOT_csrf_fs_reg_read__5969_EQ_0_0418_0419_OR_N_ETC___d20949 = (csrf_fs_reg != 2'd0 || - (!fetchStage$pipelines_1_first[95] || - !fetchStage$pipelines_1_first[94]) && - (!fetchStage$pipelines_1_first[88] || - !fetchStage$pipelines_1_first[87]) && - !fetchStage$pipelines_1_first[81] && - (!fetchStage$pipelines_1_first[75] || - !fetchStage$pipelines_1_first[74])) && - (fetchStage$pipelines_1_first[231:200] != 32'h10500073 || + (!fetchStage$pipelines_0_first[96] || + !fetchStage$pipelines_0_first[95]) && + (!fetchStage$pipelines_0_first[89] || + !fetchStage$pipelines_0_first[88]) && + !fetchStage$pipelines_0_first[82] && + (!fetchStage$pipelines_0_first[76] || + !fetchStage$pipelines_0_first[75])) && + (fetchStage$pipelines_0_first[304:273] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_prv_reg_read__2633_ULE_1_4189_4253_OR_ETC___d14257 = - !csrf_prv_reg_read__2633_ULE_1___d14189 || - (commitStage_commitTrap[4] ? - !_0b0_CONCAT_csrf_mideleg_11_reg_read__1606_1607_ETC___d14209 : - !_0b0_CONCAT_csrf_medeleg_15_reg_read__1598_1599_ETC___d14227) ; - assign NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13569 = + assign NOT_csrf_fs_reg_read__5969_EQ_0_0418_0419_OR_N_ETC___d21394 = + (csrf_fs_reg != 2'd0 || + (!fetchStage$pipelines_1_first[96] || + !fetchStage$pipelines_1_first[95]) && + (!fetchStage$pipelines_1_first[89] || + !fetchStage$pipelines_1_first[88]) && + !fetchStage$pipelines_1_first[82] && + (!fetchStage$pipelines_1_first[76] || + !fetchStage$pipelines_1_first[75])) && + (fetchStage$pipelines_1_first[304:273] != 32'h10500073 || + !csrf_tw_reg || + csrf_prv_reg == 2'd3) ; + assign NOT_csrf_mtcc_reg_read__6624_BITS_33_TO_28_257_ETC___d22578 = + csrf_mtcc_reg[33:28] >= 6'd50 ; + assign NOT_csrf_prv_reg_read__0075_ULE_1_2375_2490_OR_ETC___d22495 = + !csrf_prv_reg_read__0075_ULE_1___d22375 || + ((commitStage_commitTrap[44:43] == 2'd1) ? + !_0b0_CONCAT_csrf_medeleg_15_reg_read__6063_6064_ETC___d22403 : + commitStage_commitTrap[44:43] == 2'd0 || + !_0b0_CONCAT_csrf_mideleg_11_reg_read__6071_6072_ETC___d22405) ; + assign NOT_csrf_stcc_reg_read__6615_BITS_33_TO_28_249_ETC___d22501 = + csrf_stcc_reg[33:28] >= 6'd50 ; + assign NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21059 = + !fetchStage$pipelines_0_canDeq || + !regRenamingTable$rename_0_canRename || + fetchStage_pipelines_0_first__0045_BITS_272_TO_ETC___d21041 || + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21056 || + fetchStage$pipelines_0_first[267:265] != 3'd1 ; + assign NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21490 = (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258 && - (fetchStage$pipelines_0_first[194:192] == 3'd3 || - fetchStage$pipelines_0_first[194:192] == 3'd4) || + (regRenamingTable_rename_0_canRename__0929_AND__ETC___d21010 && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 && + (fetchStage$pipelines_0_first[267:265] == 3'd3 || + fetchStage$pipelines_0_first[267:265] == 3'd4) || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2614_BITS_199_TO_ETC___d13555) ; - assign NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13580 = + NOT_regRenamingTable_rename_1_canRename__1062__ETC___d21477) ; + assign NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21558 = (!fetchStage$pipelines_0_canDeq || - fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3183_AND__ETC___d13578 || - !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2614_BITS_199_TO_ETC___d13555) ; - assign NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13619 = - !fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13613 || - fetchStage$pipelines_0_first[194:192] != 3'd3 && - fetchStage$pipelines_0_first[194:192] != 3'd4 ; - assign NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13636 = + !regRenamingTable$rename_0_canRename || + fetchStage_pipelines_0_first__0045_BITS_272_TO_ETC___d21041 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1 || + fetchStage$pipelines_0_first[267:265] != 3'd3 && + fetchStage$pipelines_0_first[267:265] != 3'd4) && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21557 ; + assign NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21565 = (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13287 || - fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296) && + NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21514 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1 || + fetchStage$pipelines_0_first[267:265] != 3'd2 || + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051) && coreFix_memExe_rsMem$canEnq && - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 ; - assign NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13757 = + CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q266 ; + assign NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21714 = (!fetchStage$pipelines_0_canDeq || - fetchStage$pipelines_0_first[194:192] == 3'd1 && - !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13613 || - fetchStage$pipelines_0_first[194:192] != 3'd0 && - fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227) && - coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13776 = - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3181_3271_OR_NOT__ETC___d13747) && - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 && - (fetchStage$pipelines_1_first[199:195] == 5'd14 || + NOT_specTagManager_canClaim__0927_1023_OR_NOT__ETC___d21685) && + CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q270 && + (fetchStage$pipelines_1_first[272:268] == 5'd19 || coreFix_memExe_rsMem$RDY_enq) ; - assign NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13828 = + assign NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21768 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13703 && - IF_fetchStage_RDY_pipelines_0_first__2602_AND__ETC___d13214) && + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21634 && + IF_fetchStage_RDY_pipelines_0_first__0042_AND__ETC___d20964) && fetchStage$RDY_pipelines_0_first && - fetchStage_pipelines_0_canDeq__2603_AND_fetchS_ETC___d13826 ; - assign NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13928 = + fetchStage_pipelines_0_canDeq__0043_AND_fetchS_ETC___d21766 ; + assign NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21875 = (!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13834 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13244) && + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21872) && + coreFix_aluExe_1_rsAlu$canEnq && + !coreFix_aluExe_0_rsAlu_approximateCount__0973__ETC___d20975 ; + assign NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21880 = + (!fetchStage$pipelines_0_canDeq || + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21775 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20996) && fetchStage$pipelines_1_canDeq ; - assign NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13930 = + assign NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21882 = !fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13668 || - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13301 || - fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13941 = - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13928 && - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13938 && - (fetchStage$pipelines_1_first[194:192] == 3'd0 || - fetchStage$pipelines_1_first[194:192] == 3'd1) && - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__260_ETC___d13742 ; - assign NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13986 = + !regRenamingTable$rename_0_canRename || + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21598 || + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21056 || + fetchStage$pipelines_0_first[267:265] != 3'd1 ; + assign NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21944 = (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13668 || - fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296) && + !regRenamingTable$rename_0_canRename || + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21598 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1 || + fetchStage$pipelines_0_first[267:265] != 3'd2 || + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051) && coreFix_memExe_rsMem$canEnq && - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 ; - assign NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d14016 = - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13930 && + CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q266 ; + assign NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21980 = + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21882 && specTagManager$canClaim && - regRenamingTable_rename_1_canRename__3307_AND__ETC___d13937 && - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13650 && - fetchStage$pipelines_1_first[194:192] == 3'd1 ; - assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13117 = - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h649451 == 5'd0 && - imm__h649452 == 32'd0 || - IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[11:10] != - 2'b11 ; - assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207 = - fetchStage$pipelines_0_first[199:195] != 5'd0 && - fetchStage$pipelines_0_first[199:195] != 5'd21 && - fetchStage$pipelines_0_first[199:195] != 5'd17 && - fetchStage$pipelines_0_first[199:195] != 5'd18 && - fetchStage$pipelines_0_first[199:195] != 5'd13 && - fetchStage$pipelines_0_first[199:195] != 5'd16 && - fetchStage$pipelines_0_first[199:195] != 5'd15 && - fetchStage$pipelines_0_first[199:195] != 5'd19 && - fetchStage$pipelines_0_first[199:195] != 5'd20 && - !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_263_ETC___d13202 && - rob$enqPort_0_canEnq && - epochManager$checkEpoch_0_check ; - assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13245 = - (fetchStage$pipelines_0_first[194:192] != 3'd1 || + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21890 && + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21580 && + fetchStage$pipelines_1_first[267:265] == 3'd1 ; + assign NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d20997 = + (fetchStage$pipelines_0_first[267:265] != 3'd1 || + specTagManager$canClaim) && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20996 ; + assign NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21419 = + (fetchStage$pipelines_0_first[267:265] != 3'd1 || + specTagManager$canClaim) && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958 && + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21418 ; + assign NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21591 = + (fetchStage$pipelines_0_first[267:265] != 3'd1 || + specTagManager$canClaim) && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21020 ; + assign NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21668 = + fetchStage$pipelines_0_first[267:265] != 3'd0 && + fetchStage$pipelines_0_first[267:265] != 3'd1 && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 || + coreFix_aluExe_1_rsAlu$canEnq && + !coreFix_aluExe_0_rsAlu_approximateCount__0973__ETC___d20975 ; + assign NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21675 = + fetchStage$pipelines_0_first[267:265] != 3'd0 && + fetchStage$pipelines_0_first[267:265] != 3'd1 && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 || + coreFix_aluExe_0_rsAlu$canEnq && + coreFix_aluExe_0_rsAlu_approximateCount__0973__ETC___d20975 ; + assign NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21775 = + (fetchStage$pipelines_0_first[267:265] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13244 ; - assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13503 = - (fetchStage$pipelines_0_first[194:192] != 3'd1 || - specTagManager$canClaim) && - regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207 && - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13502 ; - assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13509 = - (fetchStage$pipelines_0_first[194:192] != 3'd1 || - specTagManager$canClaim) && - regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207 && - (fetchStage$pipelines_0_first[194:192] == 3'd0 || - fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 && - (!coreFix_aluExe_0_rsAlu$canEnq || - !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223) ; - assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13661 = - (fetchStage$pipelines_0_first[194:192] != 3'd1 || - specTagManager$canClaim) && - regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 ; - assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13834 = - (fetchStage$pipelines_0_first[194:192] != 3'd1 || - specTagManager$canClaim) && - regRenamingTable$rename_0_canRename && - !checkForException___d12839[4] && + !checkForException___d20432[13] && rob$enqPort_0_canEnq ; - assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13903 = - { fetchStage$pipelines_0_first[194:192] != 3'd2 || - !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296 || - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13859, - (fetchStage$pipelines_0_first[194:192] == 3'd2 && - coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 && - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13862) ? - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13865 : - { 1'h0, - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13868 }, - 7'd32, - specTagManager$currentSpecBits } ; - assign NOT_fetchStage_pipelines_0_first__2605_BIT_68__ETC___d13256 = - !fetchStage$pipelines_0_first[68] && - !checkForException___d12839[4] && - NOT_csrf_fs_reg_read__1491_EQ_0_2828_2829_OR_N_ETC___d13200 && + assign NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21777 = + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21775 && + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 ; + assign NOT_fetchStage_pipelines_0_first__0045_BIT_69__ETC___d20504 = + !fetchStage$pipelines_0_first[69] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15] && + checkForException___d20432[13] && + checkForException___d20432[12:11] == 2'd0 ; + assign NOT_fetchStage_pipelines_0_first__0045_BIT_69__ETC___d20784 = + !fetchStage$pipelines_0_first[69] && + (IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15] || + checkForException___d20432[13] && + checkForException___d20432[12:11] != 2'd0 && + checkForException___d20432[12:11] != 2'd1) ; + assign NOT_fetchStage_pipelines_0_first__0045_BIT_69__ETC___d21008 = + !fetchStage$pipelines_0_first[69] && + !checkForException___d20432[13] && + NOT_csrf_fs_reg_read__5969_EQ_0_0418_0419_OR_N_ETC___d20949 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; - assign NOT_fetchStage_pipelines_1_canDeq__2611_2612_O_ETC___d12620 = + assign NOT_fetchStage_pipelines_1_canDeq__0051_0052_O_ETC___d20060 = !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && (epochManager$checkEpoch_1_check || fetchStage$RDY_pipelines_1_deq) ; - assign NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13494 = - fetchStage$pipelines_1_first[199:195] != 5'd0 && - fetchStage$pipelines_1_first[199:195] != 5'd21 && - fetchStage$pipelines_1_first[199:195] != 5'd17 && - fetchStage$pipelines_1_first[199:195] != 5'd18 && - fetchStage$pipelines_1_first[199:195] != 5'd13 && - fetchStage$pipelines_1_first[199:195] != 5'd16 && - fetchStage$pipelines_1_first[199:195] != 5'd15 && - fetchStage$pipelines_1_first[199:195] != 5'd19 && - fetchStage$pipelines_1_first[199:195] != 5'd20 && - !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_263_ETC___d13485 && - rob_enqPort_1_canEnq__3487_AND_epochManager_ch_ETC___d13492 ; - assign NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13496 = - (fetchStage$pipelines_1_first[194:192] != 3'd1 || + assign NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21031 = + (fetchStage$pipelines_1_first[267:265] != 3'd1 || + !fetchStage$pipelines_0_canDeq || + fetchStage$RDY_pipelines_0_first) && + (fetchStage$RDY_pipelines_0_first && + fetchStage$pipelines_1_first[267:265] == 3'd1 && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21024 || + csrf_rg_dcsr_read__6184_BIT_2_0464_OR_NOT_fetc_ETC___d21029) ; + assign NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21410 = + (fetchStage$pipelines_1_first[267:265] != 3'd1 || + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21059 && + specTagManager$canClaim) && + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21409 ; + assign NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21533 = + (fetchStage$pipelines_1_first[267:265] != 3'd1 || (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13287 || - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13301 || - fetchStage$pipelines_0_first[194:192] != 3'd1) && + NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21514 || + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21527 || + fetchStage$pipelines_0_first[267:265] != 3'd1) && specTagManager$canClaim) && - regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13494 ; - assign NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13607 = - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13287 || - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13601 || - fetchStage$pipelines_0_first[194:192] != 3'd1) && + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21409 ; + assign NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21891 = + (fetchStage$pipelines_1_first[267:265] != 3'd1 || + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21882 && specTagManager$canClaim) && - regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13494 ; - assign NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13628 = - fetchStage$pipelines_1_first[199:195] != 5'd0 && - fetchStage$pipelines_1_first[199:195] != 5'd21 && - fetchStage$pipelines_1_first[199:195] != 5'd17 && - fetchStage$pipelines_1_first[199:195] != 5'd18 && - fetchStage$pipelines_1_first[199:195] != 5'd13 && - fetchStage$pipelines_1_first[199:195] != 5'd16 && - fetchStage$pipelines_1_first[199:195] != 5'd15 && - fetchStage$pipelines_1_first[199:195] != 5'd19 && - fetchStage$pipelines_1_first[199:195] != 5'd20 && - !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_263_ETC___d13485 && - rob_enqPort_1_canEnq__3487_AND_epochManager_ch_ETC___d13626 ; - assign NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13645 = - fetchStage$pipelines_1_first[199:195] != 5'd0 && - fetchStage$pipelines_1_first[199:195] != 5'd21 && - fetchStage$pipelines_1_first[199:195] != 5'd17 && - fetchStage$pipelines_1_first[199:195] != 5'd18 && - fetchStage$pipelines_1_first[199:195] != 5'd13 && - fetchStage$pipelines_1_first[199:195] != 5'd16 && - fetchStage$pipelines_1_first[199:195] != 5'd15 && - fetchStage$pipelines_1_first[199:195] != 5'd19 && - fetchStage$pipelines_1_first[199:195] != 5'd20 && - !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_263_ETC___d13485 && - rob_enqPort_1_canEnq__3487_AND_epochManager_ch_ETC___d13643 ; - assign NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13938 = - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13930 && - specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3307_AND__ETC___d13937 ; - assign NOT_fetchStage_pipelines_1_first__2614_BIT_68__ETC___d13935 = - !fetchStage$pipelines_1_first[68] && - !checkForException___d13458[4] && - NOT_csrf_fs_reg_read__1491_EQ_0_2828_2829_OR_N_ETC___d13483 && + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21890 ; + assign NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21893 = + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21891 && + (fetchStage$pipelines_1_first[267:265] == 3'd0 || + fetchStage$pipelines_1_first[267:265] == 3'd1 || + fetchStage$pipelines_1_first[237:236] == 2'd0 || + fetchStage$pipelines_1_first[237:236] == 2'd1) && + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__004_ETC___d21680 ; + assign NOT_fetchStage_pipelines_1_first__0054_BIT_69__ETC___d21888 = + !fetchStage$pipelines_1_first[69] && + !checkForException___d21369[13] && + NOT_csrf_fs_reg_read__5969_EQ_0_0418_0419_OR_N_ETC___d21394 && rob$enqPort_1_canEnq && - epochManager$checkEpoch_1_check ; - assign NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 = - !mmio_cRqQ_clearReq_dummy2_1$Q_OUT || !mmio_cRqQ_clearReq_rl ; - assign NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 = - (!mmio_cRqQ_enqReq_dummy2_2$Q_OUT || - (mmio_cRqQ_enqReq_lat_0$whas ? - !mmio_cRqQ_enqReq_lat_0$wget[142] : - !mmio_cRqQ_enqReq_rl[142])) && - (mmio_cRqQ_deqReq_dummy2_2$Q_OUT && - (EN_mmioToPlatform_cRq_deq || mmio_cRqQ_deqReq_rl) || - mmio_cRqQ_empty) ; - assign NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 = - !mmio_cRsQ_clearReq_dummy2_1$Q_OUT || !mmio_cRsQ_clearReq_rl ; - assign NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 = - (!mmio_cRsQ_enqReq_dummy2_2$Q_OUT || - (CAN_FIRE_RL_mmio_handlePRq ? - !mmio_cRsQ_enqReq_lat_0$wget[1] : - !mmio_cRsQ_enqReq_rl[1])) && - (mmio_cRsQ_deqReq_dummy2_2$Q_OUT && - (EN_mmioToPlatform_cRs_deq || mmio_cRsQ_deqReq_rl) || - mmio_cRsQ_empty) ; - assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 = + epochManager$checkEpoch_1_check && + !csrf_rg_dcsr[2] ; + assign NOT_mmio_dataPendQ_empty_80_378_AND_rob_RDY_se_ETC___d1379 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt ; - assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 = + coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt ; + assign NOT_mmio_dataPendQ_empty_80_378_AND_rob_RDY_se_ETC___d2026 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd ; - assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 = - (!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT || - !mmio_dataPendQ_enqReq_lat_0$whas && - !mmio_dataPendQ_enqReq_rl) && - (mmio_dataPendQ_deqReq_dummy2_2$Q_OUT && - (mmio_dataRespQ_deqReq_lat_0$whas || - mmio_dataPendQ_deqReq_rl) || - mmio_dataPendQ_empty) ; - assign NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 = - !mmio_dataReqQ_clearReq_dummy2_1$Q_OUT || - !mmio_dataReqQ_clearReq_rl ; - assign NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 = - (!mmio_dataReqQ_enqReq_dummy2_2$Q_OUT || - (mmio_dataReqQ_enqReq_lat_0$whas ? - !mmio_dataReqQ_enqReq_lat_0$wget[142] : - !mmio_dataReqQ_enqReq_rl[142])) && - (mmio_dataReqQ_deqReq_dummy2_2$Q_OUT && - (CAN_FIRE_RL_mmio_sendDataReq || mmio_dataReqQ_deqReq_rl) || - mmio_dataReqQ_empty) ; - assign NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 = - !mmio_dataRespQ_clearReq_dummy2_1$Q_OUT || - !mmio_dataRespQ_clearReq_rl ; - assign NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 = - (!mmio_dataRespQ_enqReq_dummy2_2$Q_OUT || - (CAN_FIRE_RL_mmio_sendDataResp ? - !mmio_dataRespQ_enqReq_lat_0$wget[65] : - !mmio_dataRespQ_enqReq_rl[65])) && - (mmio_dataRespQ_deqReq_dummy2_2$Q_OUT && - (mmio_dataRespQ_deqReq_lat_0$whas || - mmio_dataRespQ_deqReq_rl) || - mmio_dataRespQ_empty) ; - assign NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 = - !mmio_pRqQ_clearReq_dummy2_1$Q_OUT || !mmio_pRqQ_clearReq_rl ; - assign NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 = - (!mmio_pRqQ_enqReq_dummy2_2$Q_OUT || - (EN_mmioToPlatform_pRq_enq ? - !mmio_pRqQ_enqReq_lat_0$wget[39] : - !mmio_pRqQ_enqReq_rl[39])) && - (mmio_pRqQ_deqReq_dummy2_2$Q_OUT && - (CAN_FIRE_RL_mmio_handlePRq || mmio_pRqQ_deqReq_rl) || - mmio_pRqQ_empty) ; - assign NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 = - !mmio_pRsQ_clearReq_dummy2_1$Q_OUT || !mmio_pRsQ_clearReq_rl ; - assign NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 = - (!mmio_pRsQ_enqReq_dummy2_2$Q_OUT || - (EN_mmioToPlatform_pRs_enq ? - !mmio_pRsQ_enqReq_lat_0$wget[67] : - !mmio_pRsQ_enqReq_rl[67])) && - (mmio_pRsQ_deqReq_dummy2_2$Q_OUT && - (mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) || - mmio_pRsQ_empty) ; - assign NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13287 = + coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd ; + assign NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21434 = !regRenamingTable$rename_0_canRename || - fetchStage$pipelines_0_first[199:195] == 5'd0 || - fetchStage$pipelines_0_first[199:195] == 5'd21 || - fetchStage$pipelines_0_first[199:195] == 5'd17 || - fetchStage$pipelines_0_first[199:195] == 5'd18 || - fetchStage$pipelines_0_first[199:195] == 5'd13 || - fetchStage$pipelines_0_first[199:195] == 5'd16 || - fetchStage$pipelines_0_first[199:195] == 5'd15 || - fetchStage$pipelines_0_first[199:195] == 5'd19 || - fetchStage$pipelines_0_first[199:195] == 5'd20 || - fetchStage_pipelines_0_first__2605_BIT_68_2632_ETC___d13285 ; - assign NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13613 = + fetchStage$pipelines_0_first[272:268] == 5'd0 || + fetchStage$pipelines_0_first[272:268] == 5'd26 || + fetchStage$pipelines_0_first[272:268] == 5'd22 || + fetchStage$pipelines_0_first[272:268] == 5'd23 || + fetchStage$pipelines_0_first[272:268] == 5'd17 || + fetchStage$pipelines_0_first[272:268] == 5'd18 || + fetchStage$pipelines_0_first[272:268] == 5'd21 || + fetchStage$pipelines_0_first[272:268] == 5'd20 || + fetchStage$pipelines_0_first[272:268] == 5'd24 || + fetchStage$pipelines_0_first[272:268] == 5'd25 || + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21432 ; + assign NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21514 = !regRenamingTable$rename_0_canRename || - fetchStage$pipelines_0_first[199:195] == 5'd0 || - fetchStage$pipelines_0_first[199:195] == 5'd21 || - fetchStage$pipelines_0_first[199:195] == 5'd17 || - fetchStage$pipelines_0_first[199:195] == 5'd18 || - fetchStage$pipelines_0_first[199:195] == 5'd13 || - fetchStage$pipelines_0_first[199:195] == 5'd16 || - fetchStage$pipelines_0_first[199:195] == 5'd15 || - fetchStage$pipelines_0_first[199:195] == 5'd19 || - fetchStage$pipelines_0_first[199:195] == 5'd20 || - fetchStage_pipelines_0_first__2605_BIT_68_2632_ETC___d13285 ; - assign NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13668 = + fetchStage$pipelines_0_first[272:268] == 5'd0 || + fetchStage$pipelines_0_first[272:268] == 5'd26 || + fetchStage$pipelines_0_first[272:268] == 5'd22 || + fetchStage$pipelines_0_first[272:268] == 5'd23 || + fetchStage$pipelines_0_first[272:268] == 5'd17 || + fetchStage$pipelines_0_first[272:268] == 5'd18 || + fetchStage$pipelines_0_first[272:268] == 5'd21 || + fetchStage$pipelines_0_first[272:268] == 5'd20 || + fetchStage$pipelines_0_first[272:268] == 5'd24 || + fetchStage$pipelines_0_first[272:268] == 5'd25 || + fetchStage_pipelines_0_first__0045_BIT_69_0074_ETC___d21512 ; + assign NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21870 = !regRenamingTable$rename_0_canRename || - fetchStage$pipelines_0_first[68] || - checkForException___d12839[4] || + renameStage_rg_m_halt_req[4] || + fetchStage$pipelines_0_first[69] || + checkForException___d20432[13] || !rob$enqPort_0_canEnq ; - assign NOT_regRenamingTable_rename_1_canRename__3307__ETC___d13726 = + assign NOT_regRenamingTable_rename_1_canRename__1062__ETC___d21477 = !regRenamingTable$rename_1_canRename || - fetchStage$pipelines_1_first[199:195] == 5'd0 || - fetchStage$pipelines_1_first[199:195] == 5'd21 || - fetchStage$pipelines_1_first[199:195] == 5'd17 || - fetchStage$pipelines_1_first[199:195] == 5'd18 || - fetchStage$pipelines_1_first[199:195] == 5'd13 || - fetchStage$pipelines_1_first[199:195] == 5'd16 || - fetchStage$pipelines_1_first[199:195] == 5'd15 || - fetchStage$pipelines_1_first[199:195] == 5'd19 || - fetchStage$pipelines_1_first[199:195] == 5'd20 || - fetchStage_pipelines_1_first__2614_BIT_68_3335_ETC___d13724 ; - assign NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_RDY_ETC___d14594 = + fetchStage$pipelines_1_first[272:268] == 5'd0 || + fetchStage$pipelines_1_first[272:268] == 5'd26 || + fetchStage$pipelines_1_first[272:268] == 5'd22 || + fetchStage$pipelines_1_first[272:268] == 5'd23 || + fetchStage$pipelines_1_first[272:268] == 5'd17 || + fetchStage$pipelines_1_first[272:268] == 5'd18 || + fetchStage$pipelines_1_first[272:268] == 5'd21 || + fetchStage$pipelines_1_first[272:268] == 5'd20 || + fetchStage$pipelines_1_first[272:268] == 5'd24 || + fetchStage$pipelines_1_first[272:268] == 5'd25 || + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21475 ; + assign NOT_renameStage_rg_m_halt_req_0072_BIT_4_0073__ETC___d20956 = + !renameStage_rg_m_halt_req[4] && + !fetchStage$pipelines_0_first[69] && + NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_007_ETC___d20951 && + rob$enqPort_0_canEnq && + epochManager$checkEpoch_0_check ; + assign NOT_renameStage_rg_m_halt_req_0072_BIT_4_0073__ETC___d21407 = + !renameStage_rg_m_halt_req[4] && + !fetchStage$pipelines_1_first[69] && + NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_007_ETC___d21396 && + rob$enqPort_1_canEnq && + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d21405 ; + assign NOT_renameStage_rg_m_halt_req_0072_BIT_4_0073__ETC___d21555 = + !renameStage_rg_m_halt_req[4] && + !fetchStage$pipelines_1_first[69] && + NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_007_ETC___d21396 && + rob$enqPort_1_canEnq && + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d21553 ; + assign NOT_renameStage_rg_m_halt_req_0072_BIT_4_0073__ETC___d21574 = + !renameStage_rg_m_halt_req[4] && + !fetchStage$pipelines_1_first[69] && + NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_007_ETC___d21396 && + rob$enqPort_1_canEnq && + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d21572 ; + assign NOT_rob_deqPort_0_canDeq__3151_3152_OR_regRena_ETC___d23192 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && - regRenamingTable$RDY_commit_0_commit) && + regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__4562_BIT_25_4563_4_ETC___d14591) ; - assign NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 = + NOT_rob_deqPort_1_deq_data__3158_BIT_25_3159_3_ETC___d23189) ; + assign NOT_rob_deqPort_0_canDeq__3151_3152_OR_rob_deq_ETC___d23371 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && - !rob$deqPort_0_deq_data[167] && - rob$deqPort_0_deq_data[186:182] != 5'd0 && - rob$deqPort_0_deq_data[186:182] != 5'd21 && - rob$deqPort_0_deq_data[186:182] != 5'd17 && - rob$deqPort_0_deq_data[186:182] != 5'd18 && - rob$deqPort_0_deq_data[186:182] != 5'd13 && - rob$deqPort_0_deq_data[186:182] != 5'd16 && - rob$deqPort_0_deq_data[186:182] != 5'd15 && - rob$deqPort_0_deq_data[186:182] != 5'd19 && - rob$deqPort_0_deq_data[186:182] != 5'd20) && + !rob$deqPort_0_deq_data[274] && + rob$deqPort_0_deq_data[469:465] != 5'd0 && + rob$deqPort_0_deq_data[469:465] != 5'd26 && + rob$deqPort_0_deq_data[469:465] != 5'd22 && + rob$deqPort_0_deq_data[469:465] != 5'd23 && + rob$deqPort_0_deq_data[469:465] != 5'd17 && + rob$deqPort_0_deq_data[469:465] != 5'd18 && + rob$deqPort_0_deq_data[469:465] != 5'd21 && + rob$deqPort_0_deq_data[469:465] != 5'd20 && + rob$deqPort_0_deq_data[469:465] != 5'd24 && + rob$deqPort_0_deq_data[469:465] != 5'd25) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__4053_BITS_186_TO_1_ETC___d14361 = - rob$deqPort_0_deq_data[186:182] != 5'd13 || - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 != + assign NOT_rob_deqPort_0_deq_data__2022_BITS_469_TO_4_ETC___d22795 = + rob$deqPort_0_deq_data[469:465] != 5'd17 || + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 != + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_1_deq_data__4562_BIT_25_4563_4_ETC___d14591 = + assign NOT_rob_deqPort_1_deq_data__3158_BIT_25_3159_3_ETC___d23189 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || - rob$deqPort_1_deq_data[167] || - rob$deqPort_1_deq_data[186:182] == 5'd0 || - rob$deqPort_1_deq_data[186:182] == 5'd21 || - rob$deqPort_1_deq_data[186:182] == 5'd17 || - rob$deqPort_1_deq_data[186:182] == 5'd18 || - rob$deqPort_1_deq_data[186:182] == 5'd13 || - rob$deqPort_1_deq_data[186:182] == 5'd16 || - rob$deqPort_1_deq_data[186:182] == 5'd15 || - rob$deqPort_1_deq_data[186:182] == 5'd19 || - rob$deqPort_1_deq_data[186:182] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ; - assign NOT_specTagManager_canClaim__3181_3271_OR_NOT__ETC___d13747 = + rob$deqPort_1_deq_data[274] || + rob$deqPort_1_deq_data[469:465] == 5'd0 || + rob$deqPort_1_deq_data[469:465] == 5'd26 || + rob$deqPort_1_deq_data[469:465] == 5'd22 || + rob$deqPort_1_deq_data[469:465] == 5'd23 || + rob$deqPort_1_deq_data[469:465] == 5'd17 || + rob$deqPort_1_deq_data[469:465] == 5'd18 || + rob$deqPort_1_deq_data[469:465] == 5'd21 || + rob$deqPort_1_deq_data[469:465] == 5'd20 || + rob$deqPort_1_deq_data[469:465] == 5'd24 || + rob$deqPort_1_deq_data[469:465] == 5'd25 || + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; + assign NOT_specTagManager_canClaim__0927_1023_OR_NOT__ETC___d21685 = !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13613 || - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13694 || - fetchStage$pipelines_0_first[194:192] != 3'd1 || + !regRenamingTable$rename_0_canRename || + fetchStage_pipelines_0_first__0045_BITS_272_TO_ETC___d21041 || + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21625 || + fetchStage$pipelines_0_first[267:265] != 3'd1 || specTagManager$RDY_nextSpecTag ; - assign NOT_specTagManager_canClaim__3181_3271_OR_NOT__ETC___d13812 = + assign NOT_specTagManager_canClaim__0927_1023_OR_NOT__ETC___d21752 = !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13668 || - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13694 || - fetchStage$pipelines_0_first[194:192] != 3'd1 || + !regRenamingTable$rename_0_canRename || + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21598 || + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21625 || + fetchStage$pipelines_0_first[267:265] != 3'd1 || specTagManager$RDY_nextSpecTag ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2916 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q14, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2925 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2916, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2925, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934, - x__h288836 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14890 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14846 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14855 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14846, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14864 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14855, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 } ; - assign SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13558 = - SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13528 || - fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13272 || - !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2614_BITS_199_TO_ETC___d13555 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 = - { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63[10], - coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63 } ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 ^ - 12'h800) <= - 12'd2175 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 ^ - 12'h800) < - 12'd1922 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 + - 12'd127 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] - - 8'd127 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 = - { coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28[10], - coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28 } ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 ^ - 12'h800) <= - 12'd2175 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 ^ - 12'h800) < - 12'd1922 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 + - 12'd127 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] - - 8'd127 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 = - { coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98[10], - coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98 } ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 ^ - 12'h800) <= - 12'd2175 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 ^ - 12'h800) < - 12'd1922 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] - - 8'd127 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 + - 12'd127 ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10111 = - { {4{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168[7]}}, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168 } ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 = - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10111 ^ + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7078 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q36, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q37, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q38 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7109 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q290, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q291, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q292, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7119 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7078, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q302, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7109, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q303, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q304 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7126 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q311, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q312, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7119, + x__h508693 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d23909 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q313, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q314, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q315 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d23842 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q275, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q276, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q277 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d23873 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q296, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q297, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q298, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d23883 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d23842, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d23873, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q307 } ; + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12779 = + { {4{f1_exp14825_MINUS_127__q147[7]}}, + f1_exp14825_MINUS_127__q147 } ; + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12779 ^ 12'h800) <= 12'd3071 ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 = - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10111 ^ + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12779 ^ 12'h800) < 12'd1026 ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8638 = - { {4{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128[7]}}, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128 } ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 = - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8638 ^ + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13494 = + { {4{f3_exp93123_MINUS_127__q164[7]}}, + f3_exp93123_MINUS_127__q164 } ; + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13494 ^ 12'h800) <= 12'd3071 ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 = - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8638 ^ + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13494 ^ 12'h800) < 12'd1026 ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9348 = - { {4{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145[7]}}, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145 } ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 = - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9348 ^ + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14264 = + { {4{f2_exp53819_MINUS_127__q187[7]}}, + f2_exp53819_MINUS_127__q187 } ; + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14264 ^ 12'h800) <= 12'd3071 ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 = - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9348 ^ + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14264 ^ 12'h800) < 12'd1026 ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8638 + + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12779 + 12'd1023 ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] - + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q151 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] - 11'd1023 ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9348 + + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13494 + 12'd1023 ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] - + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q168 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] - 11'd1023 ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10111 + + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14264 + 12'd1023 ; - assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] - + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q191 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] - 11'd1023 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245 = - ({ 3'd0, - IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165 = + assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4863 = + { {64{x__h264659[63]}}, x__h264659 } ; + assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4871 = + { {96{x__h264814[31]}}, x__h264814 } ; + assign SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22438 = + x__h994694 | in__h994763[63:0] ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10053 = + { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q82[10], + coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q82 } ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 = + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10053 ^ + 12'h800) <= + 12'd2175 ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 = + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10053 ^ + 12'h800) < + 12'd1922 ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10053 + + 12'd127 ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q88 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83[7:0] - + 8'd127 ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8656 = + { coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q47[10], + coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q47 } ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 = + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8656 ^ + 12'h800) <= + 12'd2175 ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 = + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8656 ^ + 12'h800) < + 12'd1922 ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8656 + + 12'd127 ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q53 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48[7:0] - + 8'd127 ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11450 = + { coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q117[10], + coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q117 } ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 = + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11450 ^ + 12'h800) <= + 12'd2175 ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 = + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11450 ^ + 12'h800) < + 12'd1922 ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11450 + + 12'd127 ; + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q123 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118[7:0] - + 8'd127 ; + assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10676 = { 3'd0, - _theResult___fst_exp__h351411 == 8'd0 && - (sfdin__h351405[56:34] == 23'd0 || guard__h343310 != 2'b0), + _theResult___fst_exp__h630241 == 8'd0 && + (sfdin__h630235[56:34] == 23'd0 || guard__h622142 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h352008 == 8'd255 && - _theResult___fst_sfd__h352009 == 23'd0, + _theResult___fst_exp__h630838 == 8'd255 && + _theResult___fst_sfd__h630839 == 23'd0, 1'd0, - _theResult___fst_exp__h351411 != 8'd255 && - guard__h343310 != 2'b0 } ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 = + _theResult___fst_exp__h630241 != 8'd255 && + guard__h622142 != 2'b0 } ; + assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11148 = ({ 3'd0, - IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ^ + IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146 } ^ 9'h100) <= 9'd256 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557 = + assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12073 = { 3'd0, - _theResult___fst_exp__h397101 == 8'd0 && - (sfdin__h397095[56:34] == 23'd0 || guard__h389002 != 2'b0), + _theResult___fst_exp__h675988 == 8'd0 && + (sfdin__h675982[56:34] == 23'd0 || guard__h667889 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h397698 == 8'd255 && - _theResult___fst_sfd__h397699 == 23'd0, + _theResult___fst_exp__h676585 == 8'd255 && + _theResult___fst_sfd__h676586 == 23'd0, 1'd0, - _theResult___fst_exp__h397101 != 8'd255 && - guard__h389002 != 2'b0 } ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 = + _theResult___fst_exp__h675988 != 8'd255 && + guard__h667889 != 2'b0 } ; + assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8354 = ({ 3'd0, - IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ^ + IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352 } ^ 9'h100) <= 9'd256 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949 = + assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9279 = { 3'd0, - _theResult___fst_exp__h442789 == 8'd0 && - (sfdin__h442783[56:34] == 23'd0 || guard__h434690 != 2'b0), + _theResult___fst_exp__h584492 == 8'd0 && + (sfdin__h584486[56:34] == 23'd0 || guard__h576391 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h443386 == 8'd255 && - _theResult___fst_sfd__h443387 == 23'd0, + _theResult___fst_exp__h585089 == 8'd255 && + _theResult___fst_sfd__h585090 == 23'd0, 1'd0, - _theResult___fst_exp__h442789 != 8'd255 && - guard__h434690 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362 = + _theResult___fst_exp__h584492 != 8'd255 && + guard__h576391 != 2'b0 } ; + assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9751 = + ({ 3'd0, + IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749 } ^ + 9'h100) <= + 9'd256 ; + assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13030 = ({ 6'd0, - IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 } ^ + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13028 } ^ 12'h800) <= 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736 = - { 3'd0, - _theResult___fst_exp__h508251 == 11'd0 && - (sfdin__h508245[56:5] == 52'd0 || guard__h500025 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h509083 == 11'd2047 && - _theResult___fst_sfd__h509084 == 52'd0, - 1'd0, - _theResult___fst_exp__h508251 != 11'd2047 && - guard__h500025 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777 = - { 3'd0, - _theResult___fst_exp__h547052 == 11'd0 && - (sfdin__h547046[56:5] == 52'd0 || guard__h538826 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h547884 == 11'd2047 && - _theResult___fst_sfd__h547885 == 52'd0, - 1'd0, - _theResult___fst_exp__h547052 != 11'd2047 && - guard__h538826 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821 = - { 3'd0, - _theResult___fst_exp__h586253 == 11'd0 && - (sfdin__h586247[56:5] == 52'd0 || guard__h578027 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h587085 == 11'd2047 && - _theResult___fst_sfd__h587086 == 52'd0, - 1'd0, - _theResult___fst_exp__h586253 != 11'd2047 && - guard__h578027 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889 = + assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13745 = ({ 6'd0, - IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 } ^ + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13743 } ^ 12'h800) <= 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9599 = + assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14515 = ({ 6'd0, - IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 } ^ + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14513 } ^ 12'h800) <= 12'd2048 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796 = + assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891 = + { 3'd0, + _theResult___fst_exp__h743790 == 11'd0 && + (sfdin__h743784[56:5] == 52'd0 || guard__h735564 != 2'b0), + 1'd0 } | + { 2'd0, + _theResult___fst_exp__h744622 == 11'd2047 && + _theResult___fst_sfd__h744623 == 52'd0, + 1'd0, + _theResult___fst_exp__h743790 != 11'd2047 && + guard__h735564 != 2'b0 } ; + assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932 = + { 3'd0, + _theResult___fst_exp__h782643 == 11'd0 && + (sfdin__h782637[56:5] == 52'd0 || guard__h774417 != 2'b0), + 1'd0 } | + { 2'd0, + _theResult___fst_exp__h783475 == 11'd2047 && + _theResult___fst_sfd__h783476 == 52'd0, + 1'd0, + _theResult___fst_exp__h782643 != 11'd2047 && + guard__h774417 != 2'b0 } ; + assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976 = + { 3'd0, + _theResult___fst_exp__h821947 == 11'd0 && + (sfdin__h821941[56:5] == 52'd0 || guard__h813721 != 2'b0), + 1'd0 } | + { 2'd0, + _theResult___fst_exp__h822779 == 11'd2047 && + _theResult___fst_sfd__h822780 == 52'd0, + 1'd0, + _theResult___fst_exp__h821947 != 11'd2047 && + guard__h813721 != 2'b0 } ; + assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10302 = ({ 3'd0, - IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 } ^ + IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10300 } ^ 9'h100) <= 9'd256 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194 = + assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705 = { 3'd0, - _theResult___fst_exp__h369177 == 8'd0 && - (sfdin__h369171[56:34] == 23'd0 || guard__h360949 != 2'b0), + _theResult___fst_exp__h648007 == 8'd0 && + (sfdin__h648001[56:34] == 23'd0 || guard__h639779 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h369774 == 8'd255 && - _theResult___fst_sfd__h369775 == 23'd0, + _theResult___fst_exp__h648604 == 8'd255 && + _theResult___fst_sfd__h648605 == 23'd0, 1'd0, - _theResult___fst_exp__h369177 != 8'd255 && - guard__h360949 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 = + _theResult___fst_exp__h648007 != 8'd255 && + guard__h639779 != 2'b0 } ; + assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11699 = ({ 3'd0, - IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ^ + IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11697 } ^ 9'h100) <= 9'd256 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586 = + assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102 = { 3'd0, - _theResult___fst_exp__h414867 == 8'd0 && - (sfdin__h414861[56:34] == 23'd0 || guard__h406639 != 2'b0), + _theResult___fst_exp__h693754 == 8'd0 && + (sfdin__h693748[56:34] == 23'd0 || guard__h685526 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h415464 == 8'd255 && - _theResult___fst_sfd__h415465 == 23'd0, + _theResult___fst_exp__h694351 == 8'd255 && + _theResult___fst_sfd__h694352 == 23'd0, 1'd0, - _theResult___fst_exp__h414867 != 8'd255 && - guard__h406639 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 = + _theResult___fst_exp__h693754 != 8'd255 && + guard__h685526 != 2'b0 } ; + assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8905 = ({ 3'd0, - IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ^ + IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8903 } ^ 9'h100) <= 9'd256 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978 = + assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308 = { 3'd0, - _theResult___fst_exp__h460555 == 8'd0 && - (sfdin__h460549[56:34] == 23'd0 || guard__h452327 != 2'b0), + _theResult___fst_exp__h602258 == 8'd0 && + (sfdin__h602252[56:34] == 23'd0 || guard__h594030 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h461152 == 8'd255 && - _theResult___fst_sfd__h461153 == 23'd0, + _theResult___fst_exp__h602855 == 8'd255 && + _theResult___fst_sfd__h602856 == 23'd0, 1'd0, - _theResult___fst_exp__h460555 != 8'd255 && - guard__h452327 != 2'b0 } ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 = - ({ 3'd0, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ^ - 9'h100) <= - 9'd384 ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869 = - ({ 3'd0, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ^ - 9'h100) <= - (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868 ^ - 9'h100) ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177 = - { 3'd0, - _theResult___fst_exp__h360067 == 8'd0 && - guard__h352019 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h360590 == 8'd255 && - _theResult___fst_sfd__h360591 == 23'd0, - 1'd0, - _theResult___fst_exp__h360067 != 8'd255 && - guard__h352019 != 2'b0 } ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 = - ({ 3'd0, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ^ - 9'h100) <= - 9'd384 ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261 = - ({ 3'd0, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ^ - 9'h100) <= - (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260 ^ - 9'h100) ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569 = - { 3'd0, - _theResult___fst_exp__h405757 == 8'd0 && - guard__h397709 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h406280 == 8'd255 && - _theResult___fst_sfd__h406281 == 23'd0, - 1'd0, - _theResult___fst_exp__h405757 != 8'd255 && - guard__h397709 != 2'b0 } ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 = - ({ 3'd0, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ^ - 9'h100) <= - 9'd384 ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653 = - ({ 3'd0, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ^ - 9'h100) <= - (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652 ^ - 9'h100) ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961 = - { 3'd0, - _theResult___fst_exp__h451445 == 8'd0 && - guard__h443397 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h451968 == 8'd255 && - _theResult___fst_sfd__h451969 == 23'd0, - 1'd0, - _theResult___fst_exp__h451445 != 8'd255 && - guard__h443397 != 2'b0 } ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065 = + _theResult___fst_exp__h602258 != 8'd255 && + guard__h594030 != 2'b0 } ; + assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12718 = ({ 6'd0, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ^ + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 } ^ 12'h800) <= 12'd2944 ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10412 = + assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13080 = ({ 6'd0, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ^ + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 } ^ 12'h800) <= - (IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411 ^ + (IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13079 ^ 12'h800) ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10719 = - { 3'd0, - _theResult___fst_exp__h498674 == 11'd0 && - guard__h490713 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h499432 == 11'd2047 && - _theResult___fst_sfd__h499433 == 52'd0, - 1'd0, - _theResult___fst_exp__h498674 != 11'd2047 && - guard__h490713 != 2'b0 } ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10760 = - { 3'd0, - _theResult___fst_exp__h537475 == 11'd0 && - guard__h529514 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h538233 == 11'd2047 && - _theResult___fst_sfd__h538234 == 52'd0, - 1'd0, - _theResult___fst_exp__h537475 != 11'd2047 && - guard__h529514 != 2'b0 } ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804 = - { 3'd0, - _theResult___fst_exp__h576676 == 11'd0 && - guard__h568715 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h577434 == 11'd2047 && - _theResult___fst_sfd__h577435 == 52'd0, - 1'd0, - _theResult___fst_exp__h576676 != 11'd2047 && - guard__h568715 != 2'b0 } ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577 = + assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13448 = ({ 6'd0, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ^ + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 } ^ 12'h800) <= 12'd2944 ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8939 = + assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13795 = ({ 6'd0, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ^ + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 } ^ 12'h800) <= - (IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938 ^ + (IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13794 ^ 12'h800) ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9302 = + assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14218 = ({ 6'd0, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 } ^ + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 } ^ 12'h800) <= 12'd2944 ; - assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9649 = + assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14565 = ({ 6'd0, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 } ^ + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 } ^ 12'h800) <= - (IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9648 ^ + (IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14564 ^ 12'h800) ; - assign _0_OR_NOT_fetchStage_pipelines_0_first__2605_BI_ETC___d13675 = - (fetchStage$pipelines_0_first[194:192] != 3'd1 || + assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874 = + { 3'd0, + _theResult___fst_exp__h734213 == 11'd0 && + guard__h726252 != 2'b0, + 1'd0 } | + { 2'd0, + _theResult___fst_exp__h734971 == 11'd2047 && + _theResult___fst_sfd__h734972 == 52'd0, + 1'd0, + _theResult___fst_exp__h734213 != 11'd2047 && + guard__h726252 != 2'b0 } ; + assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915 = + { 3'd0, + _theResult___fst_exp__h773066 == 11'd0 && + guard__h765105 != 2'b0, + 1'd0 } | + { 2'd0, + _theResult___fst_exp__h773824 == 11'd2047 && + _theResult___fst_sfd__h773825 == 52'd0, + 1'd0, + _theResult___fst_exp__h773066 != 11'd2047 && + guard__h765105 != 2'b0 } ; + assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959 = + { 3'd0, + _theResult___fst_exp__h812370 == 11'd0 && + guard__h804409 != 2'b0, + 1'd0 } | + { 2'd0, + _theResult___fst_exp__h813128 == 11'd2047 && + _theResult___fst_sfd__h813129 == 52'd0, + 1'd0, + _theResult___fst_exp__h812370 != 11'd2047 && + guard__h804409 != 2'b0 } ; + assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10375 = + ({ 3'd0, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 } ^ + 9'h100) <= + (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10374 ^ + 9'h100) ; + assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10688 = + { 3'd0, + _theResult___fst_exp__h638897 == 8'd0 && + guard__h630849 != 2'b0, + 1'd0 } | + { 2'd0, + _theResult___fst_exp__h639420 == 8'd255 && + _theResult___fst_sfd__h639421 == 23'd0, + 1'd0, + _theResult___fst_exp__h638897 != 8'd255 && + guard__h630849 != 2'b0 } ; + assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11379 = + ({ 3'd0, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 } ^ + 9'h100) <= + 9'd384 ; + assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11772 = + ({ 3'd0, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 } ^ + 9'h100) <= + (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11771 ^ + 9'h100) ; + assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12085 = + { 3'd0, + _theResult___fst_exp__h684644 == 8'd0 && + guard__h676596 != 2'b0, + 1'd0 } | + { 2'd0, + _theResult___fst_exp__h685167 == 8'd255 && + _theResult___fst_sfd__h685168 == 23'd0, + 1'd0, + _theResult___fst_exp__h684644 != 8'd255 && + guard__h676596 != 2'b0 } ; + assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8585 = + ({ 3'd0, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 } ^ + 9'h100) <= + 9'd384 ; + assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8978 = + ({ 3'd0, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 } ^ + 9'h100) <= + (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8977 ^ + 9'h100) ; + assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9291 = + { 3'd0, + _theResult___fst_exp__h593148 == 8'd0 && + guard__h585100 != 2'b0, + 1'd0 } | + { 2'd0, + _theResult___fst_exp__h593671 == 8'd255 && + _theResult___fst_sfd__h593672 == 23'd0, + 1'd0, + _theResult___fst_exp__h593148 != 8'd255 && + guard__h585100 != 2'b0 } ; + assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9982 = + ({ 3'd0, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 } ^ + 9'h100) <= + 9'd384 ; + assign _0_CONCAT_IF_coreFix_memExe_dTlb_procResp__239__ETC___d4650 = + { 2'd0, + (coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[289]) ? + (coreFix_memExe_dTlb_procResp__239_BITS_141_TO__ETC___d4570 ? + coreFix_memExe_dTlb$procResp[147:142] : + coreFix_memExe_dTlb$procResp[288:283]) : + coreFix_memExe_dTlb$procResp[288:283], + IF_IF_coreFix_memExe_dTlb_procResp__239_BIT_27_ETC___d4649 } ; + assign _0_CONCAT_csrf_external_int_en_vec_3_read__6082_ETC___d20086 = + { 4'd0, + csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3, + 1'd0, + csrf_external_int_en_vec_1 & csrf_external_int_pend_vec_1, + 1'd0, + csrf_timer_int_en_vec_3 & csrf_timer_int_pend_vec_3, + 1'd0, + csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, + 1'd0 } ; + assign _0_CONCAT_csrf_mtcc_reg_read__6624_BITS_149_TO__ETC___d22604 = + x__h997452[13:11] < repBound__h997416 ; + assign _0_CONCAT_csrf_mtcc_reg_read__6624_BITS_149_TO__ETC___d22630 = + x__h997756[13:11] < repBound__h997416 ; + assign _0_CONCAT_csrf_stcc_reg_read__6615_BITS_149_TO__ETC___d22529 = + x__h996795[13:11] < repBound__h996759 ; + assign _0_CONCAT_csrf_stcc_reg_read__6615_BITS_149_TO__ETC___d22555 = + x__h997099[13:11] < repBound__h996759 ; + assign _0_OR_NOT_fetchStage_pipelines_0_first__0045_BI_ETC___d21606 = + (fetchStage$pipelines_0_first[267:265] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k61043_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__2614_BI_ETC___d13760 = - (fetchStage$pipelines_1_first[194:192] != 3'd1 || + CASE_k42381_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__0054_BI_ETC___d21506 = + (fetchStage$pipelines_1_first[267:265] != 3'd1 || + !fetchStage$pipelines_0_canDeq || + fetchStage$RDY_pipelines_0_first) && + (fetchStage$RDY_pipelines_0_first && + fetchStage$pipelines_1_first[267:265] == 3'd1 && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21024 || + NOT_regRenamingTable_rename_1_canRename__1062__ETC___d21477) ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__0054_BI_ETC___d21698 = + (fetchStage$pipelines_1_first[267:265] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_fetchStage_pipelines_0_canDeq__2603_AND_N_ETC__q234 ; - assign _0_OR_fetchStage_RDY_pipelines_0_first__2602_35_ETC___d13583 = - fetchStage$RDY_pipelines_0_first && - fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13272 || - !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2614_BITS_199_TO_ETC___d13555 ; - assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554 = - sfd__h335695 >> - (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550[11] ? + CASE_fetchStage_pipelines_0_canDeq__0043_AND_N_ETC__q269 ; + assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12786 = + sfd__h715187 >> + _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12782 ; + assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13501 = + sfd__h793485 >> + _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13497 ; + assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14271 = + sfd__h754181 >> + _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14267 ; + assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10060 = + sfd__h614530 >> + (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056[11] ? 12'hAAA : - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550) ; - assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946 = - sfd__h381390 >> - (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942[11] ? + _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056) ; + assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11457 = + sfd__h660277 >> + (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453[11] ? 12'hAAA : - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942) ; - assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338 = - sfd__h427078 >> - (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334[11] ? + _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453) ; + assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8663 = + sfd__h568776 >> + (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659[11] ? 12'hAAA : - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334) ; - assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118 = - sfd__h518615 >> - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ; - assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645 = - sfd__h479673 >> - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ; - assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355 = - sfd__h557816 >> - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ; - assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1598_1599_ETC___d14227 = - medeleg_csr__read__h607141[i__h692202] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1606_1607_ETC___d14209 = - mideleg_csr__read__h607236[i__h692362] ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 = - 12'd3074 - - { 6'd0, - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ? - 6'd0 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ? - 6'd1 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ? - 6'd2 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ? - 6'd3 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ? - 6'd4 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ? - 6'd5 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ? - 6'd6 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ? - 6'd7 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ? - 6'd8 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ? - 6'd9 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ? - 6'd10 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ? - 6'd11 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ? - 6'd12 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ? - 6'd13 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ? - 6'd14 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ? - 6'd15 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ? - 6'd16 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ? - 6'd17 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ? - 6'd18 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ? - 6'd19 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ? - 6'd20 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ? - 6'd21 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ? - 6'd22 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ? - 6'd23 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ? - 6'd24 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ? - 6'd25 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ? - 6'd26 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ? - 6'd27 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ? - 6'd28 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ? - 6'd29 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ? - 6'd30 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ? - 6'd31 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ? - 6'd32 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ? - 6'd33 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ? - 6'd34 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ? - 6'd35 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ? - 6'd36 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ? - 6'd37 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ? - 6'd38 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ? - 6'd39 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ? - 6'd40 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ? - 6'd41 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ? - 6'd42 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ? - 6'd43 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ? - 6'd44 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ? - 6'd45 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ? - 6'd46 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ? - 6'd47 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ? - 6'd48 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ? - 6'd49 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ? - 6'd50 : - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ? - 6'd51 : - 6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 = - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 ^ - 12'h800) <= - 12'd2175 ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 = - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 ^ - 12'h800) < - 12'd1922 ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5180 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 && - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[4] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[4]) ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5205 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 && - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[3] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[3]) ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5232 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 && - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[1] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[1]) ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399 = - 12'd3074 - - { 6'd0, - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ? - 6'd0 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ? - 6'd1 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ? - 6'd2 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ? - 6'd3 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ? - 6'd4 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ? - 6'd5 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ? - 6'd6 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ? - 6'd7 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ? - 6'd8 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ? - 6'd9 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ? - 6'd10 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ? - 6'd11 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ? - 6'd12 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ? - 6'd13 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ? - 6'd14 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ? - 6'd15 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ? - 6'd16 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ? - 6'd17 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ? - 6'd18 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ? - 6'd19 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ? - 6'd20 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ? - 6'd21 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ? - 6'd22 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ? - 6'd23 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ? - 6'd24 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ? - 6'd25 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ? - 6'd26 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ? - 6'd27 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ? - 6'd28 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ? - 6'd29 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ? - 6'd30 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ? - 6'd31 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ? - 6'd32 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ? - 6'd33 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ? - 6'd34 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ? - 6'd35 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ? - 6'd36 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ? - 6'd37 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ? - 6'd38 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ? - 6'd39 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ? - 6'd40 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ? - 6'd41 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ? - 6'd42 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ? - 6'd43 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ? - 6'd44 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ? - 6'd45 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ? - 6'd46 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ? - 6'd47 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ? - 6'd48 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ? - 6'd49 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ? - 6'd50 : - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ? - 6'd51 : - 6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 = - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399 ^ - 12'h800) <= - 12'd2175 ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 = - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399 ^ - 12'h800) < - 12'd1922 ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6572 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 && - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[4] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[4]) ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6597 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 && - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[3] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[3]) ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6624 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 && - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[1] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[1]) ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791 = + _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659) ; + assign _0b0_CONCAT_csrf_medeleg_15_reg_read__6063_6064_ETC___d22403 = + medeleg_csr__read__h849987[i__h992443] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__6071_6072_ETC___d22405 = + mideleg_csr__read__h850085[i__h992617] ; + assign _18446744073709551615_SL_csrf_mtcc_reg_read__66_ETC___d22592 = + mask__h997264 ^ y__h997381 ; + assign _18446744073709551615_SL_csrf_stcc_reg_read__66_ETC___d22517 = + mask__h996607 ^ y__h996724 ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10691 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 && + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10676[4] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10688[4]) ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10716 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 && + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10676[3] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10688[3]) ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10743 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 && + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10676[1] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10688[1]) ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10910 = 12'd3074 - { 6'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ? @@ -23956,265 +28807,547 @@ module mkCore(CLK, (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ? 6'd51 : 6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 = - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791 ^ + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10910 ^ 12'h800) <= 12'd2175 ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 = - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791 ^ + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10910 ^ 12'h800) < 12'd1922 ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7964 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 && - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[4] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[4]) ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7989 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 && - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[3] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[3]) ; - assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8016 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 && - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[1] : - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[1]) ; - assign _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 = + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d12088 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 && + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12073[4] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12085[4]) ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d12113 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 && + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12073[3] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12085[3]) ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d12140 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 && + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12073[1] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12085[1]) ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8116 = 12'd3074 - - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10111 ; - assign _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 = + { 6'd0, + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ? + 6'd0 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ? + 6'd1 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ? + 6'd2 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ? + 6'd3 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ? + 6'd4 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ? + 6'd5 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ? + 6'd6 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ? + 6'd7 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ? + 6'd8 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ? + 6'd9 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ? + 6'd10 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ? + 6'd11 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ? + 6'd12 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ? + 6'd13 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ? + 6'd14 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ? + 6'd15 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ? + 6'd16 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ? + 6'd17 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ? + 6'd18 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ? + 6'd19 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ? + 6'd20 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ? + 6'd21 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ? + 6'd22 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ? + 6'd23 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ? + 6'd24 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ? + 6'd25 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ? + 6'd26 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ? + 6'd27 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ? + 6'd28 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ? + 6'd29 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ? + 6'd30 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ? + 6'd31 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ? + 6'd32 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ? + 6'd33 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ? + 6'd34 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ? + 6'd35 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ? + 6'd36 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ? + 6'd37 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ? + 6'd38 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ? + 6'd39 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ? + 6'd40 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ? + 6'd41 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ? + 6'd42 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ? + 6'd43 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ? + 6'd44 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ? + 6'd45 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ? + 6'd46 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ? + 6'd47 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ? + 6'd48 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ? + 6'd49 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ? + 6'd50 : + (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ? + 6'd51 : + 6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8116 ^ + 12'h800) <= + 12'd2175 ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8116 ^ + 12'h800) < + 12'd1922 ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9294 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 && + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9279[4] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9291[4]) ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9319 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 && + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9279[3] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9291[3]) ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9346 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 && + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? + _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9279[1] : + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9291[1]) ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9513 = 12'd3074 - - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8638 ; - assign _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 = + { 6'd0, + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ? + 6'd0 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ? + 6'd1 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ? + 6'd2 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ? + 6'd3 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ? + 6'd4 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ? + 6'd5 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ? + 6'd6 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ? + 6'd7 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ? + 6'd8 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ? + 6'd9 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ? + 6'd10 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ? + 6'd11 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ? + 6'd12 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ? + 6'd13 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ? + 6'd14 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ? + 6'd15 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ? + 6'd16 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ? + 6'd17 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ? + 6'd18 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ? + 6'd19 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ? + 6'd20 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ? + 6'd21 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ? + 6'd22 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ? + 6'd23 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ? + 6'd24 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ? + 6'd25 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ? + 6'd26 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ? + 6'd27 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ? + 6'd28 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ? + 6'd29 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ? + 6'd30 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ? + 6'd31 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ? + 6'd32 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ? + 6'd33 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ? + 6'd34 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ? + 6'd35 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ? + 6'd36 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ? + 6'd37 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ? + 6'd38 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ? + 6'd39 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ? + 6'd40 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ? + 6'd41 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ? + 6'd42 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ? + 6'd43 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ? + 6'd44 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ? + 6'd45 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ? + 6'd46 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ? + 6'd47 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ? + 6'd48 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ? + 6'd49 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ? + 6'd50 : + (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ? + 6'd51 : + 6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9513 ^ + 12'h800) <= + 12'd2175 ; + assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9513 ^ + 12'h800) < + 12'd1922 ; + assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12782 = 12'd3074 - - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9348 ; - assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8501 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12779 ; + assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13497 = + 12'd3074 - + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13494 ; + assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14267 = + 12'd3074 - + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14264 ; + assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12642 = 12'd3970 - { 7'd0, - coreFix_fpuMulDivExe_0_regToExeQ$first[162] ? + f1_sfd__h714826[22] ? 5'd0 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[161] ? + (f1_sfd__h714826[21] ? 5'd1 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[160] ? + (f1_sfd__h714826[20] ? 5'd2 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[159] ? + (f1_sfd__h714826[19] ? 5'd3 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[158] ? + (f1_sfd__h714826[18] ? 5'd4 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[157] ? + (f1_sfd__h714826[17] ? 5'd5 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[156] ? + (f1_sfd__h714826[16] ? 5'd6 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[155] ? + (f1_sfd__h714826[15] ? 5'd7 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[154] ? + (f1_sfd__h714826[14] ? 5'd8 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[153] ? + (f1_sfd__h714826[13] ? 5'd9 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[152] ? + (f1_sfd__h714826[12] ? 5'd10 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[151] ? + (f1_sfd__h714826[11] ? 5'd11 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[150] ? + (f1_sfd__h714826[10] ? 5'd12 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[149] ? + (f1_sfd__h714826[9] ? 5'd13 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[148] ? + (f1_sfd__h714826[8] ? 5'd14 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[147] ? + (f1_sfd__h714826[7] ? 5'd15 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[146] ? + (f1_sfd__h714826[6] ? 5'd16 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[145] ? + (f1_sfd__h714826[5] ? 5'd17 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[144] ? + (f1_sfd__h714826[4] ? 5'd18 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[143] ? + (f1_sfd__h714826[3] ? 5'd19 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[142] ? + (f1_sfd__h714826[2] ? 5'd20 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[141] ? + (f1_sfd__h714826[1] ? 5'd21 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[140] ? + (f1_sfd__h714826[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 = - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8501 ^ + assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 = + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12642 ^ 12'h800) <= 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 = - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8501 ^ + assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 = + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12642 ^ 12'h800) < 12'd1026 ; - assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9226 = + assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13372 = 12'd3970 - { 7'd0, - coreFix_fpuMulDivExe_0_regToExeQ$first[34] ? + f3_sfd__h793124[22] ? 5'd0 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[33] ? + (f3_sfd__h793124[21] ? 5'd1 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[32] ? + (f3_sfd__h793124[20] ? 5'd2 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[31] ? + (f3_sfd__h793124[19] ? 5'd3 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[30] ? + (f3_sfd__h793124[18] ? 5'd4 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[29] ? + (f3_sfd__h793124[17] ? 5'd5 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[28] ? + (f3_sfd__h793124[16] ? 5'd6 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[27] ? + (f3_sfd__h793124[15] ? 5'd7 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[26] ? + (f3_sfd__h793124[14] ? 5'd8 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[25] ? + (f3_sfd__h793124[13] ? 5'd9 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[24] ? + (f3_sfd__h793124[12] ? 5'd10 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[23] ? + (f3_sfd__h793124[11] ? 5'd11 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[22] ? + (f3_sfd__h793124[10] ? 5'd12 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[21] ? + (f3_sfd__h793124[9] ? 5'd13 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[20] ? + (f3_sfd__h793124[8] ? 5'd14 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[19] ? + (f3_sfd__h793124[7] ? 5'd15 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[18] ? + (f3_sfd__h793124[6] ? 5'd16 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[17] ? + (f3_sfd__h793124[5] ? 5'd17 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[16] ? + (f3_sfd__h793124[4] ? 5'd18 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[15] ? + (f3_sfd__h793124[3] ? 5'd19 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[14] ? + (f3_sfd__h793124[2] ? 5'd20 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[13] ? + (f3_sfd__h793124[1] ? 5'd21 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[12] ? + (f3_sfd__h793124[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 = - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9226 ^ + assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 = + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13372 ^ 12'h800) <= 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 = - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9226 ^ + assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 = + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13372 ^ 12'h800) < 12'd1026 ; - assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9989 = + assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14142 = 12'd3970 - { 7'd0, - coreFix_fpuMulDivExe_0_regToExeQ$first[98] ? + f2_sfd__h753820[22] ? 5'd0 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[97] ? + (f2_sfd__h753820[21] ? 5'd1 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[96] ? + (f2_sfd__h753820[20] ? 5'd2 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[95] ? + (f2_sfd__h753820[19] ? 5'd3 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[94] ? + (f2_sfd__h753820[18] ? 5'd4 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[93] ? + (f2_sfd__h753820[17] ? 5'd5 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[92] ? + (f2_sfd__h753820[16] ? 5'd6 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[91] ? + (f2_sfd__h753820[15] ? 5'd7 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[90] ? + (f2_sfd__h753820[14] ? 5'd8 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[89] ? + (f2_sfd__h753820[13] ? 5'd9 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[88] ? + (f2_sfd__h753820[12] ? 5'd10 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[87] ? + (f2_sfd__h753820[11] ? 5'd11 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[86] ? + (f2_sfd__h753820[10] ? 5'd12 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[85] ? + (f2_sfd__h753820[9] ? 5'd13 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[84] ? + (f2_sfd__h753820[8] ? 5'd14 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[83] ? + (f2_sfd__h753820[7] ? 5'd15 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[82] ? + (f2_sfd__h753820[6] ? 5'd16 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[81] ? + (f2_sfd__h753820[5] ? 5'd17 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[80] ? + (f2_sfd__h753820[4] ? 5'd18 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[79] ? + (f2_sfd__h753820[3] ? 5'd19 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[78] ? + (f2_sfd__h753820[2] ? 5'd20 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[77] ? + (f2_sfd__h753820[1] ? 5'd21 : - (coreFix_fpuMulDivExe_0_regToExeQ$first[76] ? + (f2_sfd__h753820[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 = - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9989 ^ + assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 = + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14142 ^ 12'h800) <= 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 = - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9989 ^ + assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 = + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14142 ^ 12'h800) < 12'd1026 ; - assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 = + assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056 = 12'd3970 - - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 ; - assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10053 ; + assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453 = 12'd3970 - - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 ; - assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11450 ; + assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659 = 12'd3970 - - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 ; + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8656 ; assign _dfoo12 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13855 || - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13928 && - regRenamingTable_rename_1_canRename__3307_AND__ETC___d13937 && - fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13986 && - fetchStage$pipelines_1_first[199:195] != 5'd14 ; + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21797 || + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21880 && + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21890 && + fetchStage$pipelines_1_first[237:236] != 2'd0 && + fetchStage$pipelines_1_first[237:236] != 2'd1 && + fetchStage$pipelines_1_first[267:265] == 3'd2 && + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21944 && + fetchStage$pipelines_1_first[272:268] != 5'd19 ; + assign _dfoo14 = + fetchStage$pipelines_0_canDeq && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21790 || + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21880 && + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21890 && + fetchStage$pipelines_1_first[267:265] != 3'd0 && + fetchStage$pipelines_1_first[267:265] != 3'd1 && + fetchStage$pipelines_1_first[237:236] != 2'd0 && + fetchStage$pipelines_1_first[237:236] != 2'd1 && + fetchStage_pipelines_1_first__0054_BITS_267_TO_ETC___d21937 ; + assign _dfoo16 = + k__h942381 == 1'd1 && fetchStage$pipelines_0_canDeq && + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21777 || + (fetchStage_pipelines_0_canDeq__0043_AND_NOT_fe_ETC___d21862 || + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21875) == + 1'd1 && + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21880 && + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21893 ; assign _dfoo18 = - k__h661043 == 1'd0 && - fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837 || - fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13924 == + k__h942381 == 1'd0 && fetchStage$pipelines_0_canDeq && + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21777 || + (fetchStage_pipelines_0_canDeq__0043_AND_NOT_fe_ETC___d21862 || + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21875) == 1'd0 && - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13941 ; + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21880 && + NOT_fetchStage_pipelines_1_first__0054_BITS_26_ETC___d21893 ; assign _dfoo2 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883 || - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13928 && - regRenamingTable_rename_1_canRename__3307_AND__ETC___d13937 && - fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13986 && - fetchStage$pipelines_1_first[191:189] != 3'd0 && - fetchStage$pipelines_1_first[191:189] != 3'd2 ; + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21830 || + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21880 && + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21890 && + fetchStage$pipelines_1_first[237:236] != 2'd0 && + fetchStage$pipelines_1_first[237:236] != 2'd1 && + fetchStage$pipelines_1_first[267:265] == 3'd2 && + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21944 && + fetchStage$pipelines_1_first[264:262] != 3'd0 && + fetchStage$pipelines_1_first[264:262] != 3'd2 ; assign _dfoo20 = - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18 || - rob$deqPort_0_deq_data[186:182] == 5'd20 ; - assign _dfoo28 = - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == + NOT_commitStage_commitTrap_2029_BITS_44_TO_43__ETC___d22295 || + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 ; + assign _dfoo24 = + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd42 || + rob$deqPort_0_deq_data[469:465] == 5'd24 || + rob$deqPort_0_deq_data[469:465] == 5'd25 ; + assign _dfoo26 = + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd19 || + rob$deqPort_0_deq_data[469:465] == 5'd25 ; + assign _dfoo32 = + rob$deqPort_0_deq_data[469:465] == 5'd17 && + (IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd8 || - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == - 6'd18) || - rob$deqPort_0_deq_data[186:182] == 5'd19 ; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == + 6'd19) || + rob$deqPort_0_deq_data[469:465] == 5'd24 ; assign _dfoo7 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13875 || - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13928 && - regRenamingTable_rename_1_canRename__3307_AND__ETC___d13937 && - fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13986 && - (fetchStage$pipelines_1_first[191:189] == 3'd0 || - fetchStage$pipelines_1_first[191:189] == 3'd2) ; + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21821 || + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21880 && + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21890 && + fetchStage$pipelines_1_first[237:236] != 2'd0 && + fetchStage$pipelines_1_first[237:236] != 2'd1 && + fetchStage$pipelines_1_first[267:265] == 3'd2 && + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21944 && + (fetchStage$pipelines_1_first[264:262] == 3'd0 || + fetchStage$pipelines_1_first[264:262] == 3'd2) ; assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset = WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -24248,24 +29381,9 @@ module mkCore(CLK, assign _dor1coreFix_memExe_bypassWire_3$EN_wset = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write = - WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ || - WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ; - assign _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write = - WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ || - WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ; - assign _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write = - WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ || - WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ; assign _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ || WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ; - assign _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write = - WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ || - WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ; - assign _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write = - WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ || - WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ; assign _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ || WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ; @@ -24287,1430 +29405,1415 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h293741 = - (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042) ? - next_deqP___1__h294020 : + assign _theResult_____2__h515296 = + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7222 ? + next_deqP___1__h515541 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h301737 = - (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149) ? - next_deqP___1__h302016 : + assign _theResult_____2__h526073 = + IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7316 ? + next_deqP___1__h526318 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h307731 = - (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320) ? - next_deqP___1__h308297 : + assign _theResult_____2__h533166 = + IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7475 ? + next_deqP___1__h533596 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h315585 = - (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416) ? - next_deqP___1__h316151 : + assign _theResult_____2__h543801 = + IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7559 ? + next_deqP___1__h544231 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h325929 = - (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645) ? - next_deqP___1__h326208 : + assign _theResult_____2__h557634 = + IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7764 ? + next_deqP___1__h557879 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h329154 = - (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739) ? - next_deqP___1__h329433 : + assign _theResult_____2__h561413 = + IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7846 ? + next_deqP___1__h561658 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h343300 = - (value__h343922 == 54'd0) ? sfd__h335695 : 57'd1 ; - assign _theResult____h360939 = - ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ^ + assign _theResult____h576381 = + (value__h577003 == 54'd0) ? sfd__h568776 : 57'd1 ; + assign _theResult____h594020 = + ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659 ^ 12'h800) < 12'd2105) ? - result__h361552 : - _theResult____h343300 ; - assign _theResult____h388992 = - (value__h389612 == 54'd0) ? sfd__h381390 : 57'd1 ; - assign _theResult____h406629 = - ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ^ + result__h594633 : + _theResult____h576381 ; + assign _theResult____h622132 = + (value__h622752 == 54'd0) ? sfd__h614530 : 57'd1 ; + assign _theResult____h639769 = + ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056 ^ 12'h800) < 12'd2105) ? - result__h407242 : - _theResult____h388992 ; - assign _theResult____h434680 = - (value__h435300 == 54'd0) ? sfd__h427078 : 57'd1 ; - assign _theResult____h452317 = - ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ^ + result__h640382 : + _theResult____h622132 ; + assign _theResult____h667879 = + (value__h668499 == 54'd0) ? sfd__h660277 : 57'd1 ; + assign _theResult____h685516 = + ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453 ^ 12'h800) < 12'd2105) ? - result__h452930 : - _theResult____h434680 ; - assign _theResult____h500015 = - ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ^ + result__h686129 : + _theResult____h667879 ; + assign _theResult____h735554 = + ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12782 ^ 12'h800) < 12'd2105) ? - result__h500628 : - ((value__h484231 == 25'd0) ? sfd__h479673 : 57'd1) ; - assign _theResult____h538816 = - ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ^ + result__h736167 : + ((value__h719770 == 25'd0) ? sfd__h715187 : 57'd1) ; + assign _theResult____h774407 = + ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14267 ^ 12'h800) < 12'd2105) ? - result__h539429 : - ((value__h523032 == 25'd0) ? sfd__h518615 : 57'd1) ; - assign _theResult____h578017 = - ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ^ + result__h775020 : + ((value__h758623 == 25'd0) ? sfd__h754181 : 57'd1) ; + assign _theResult____h813711 = + ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13497 ^ 12'h800) < 12'd2105) ? - result__h578630 : - ((value__h562233 == 25'd0) ? sfd__h557816 : 57'd1) ; - assign _theResult____h645396 = + result__h814324 : + ((value__h797927 == 25'd0) ? sfd__h793485 : 57'd1) ; + assign _theResult____h917689 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h645893 : - 15'd0 ; - assign _theResult___exp__h351927 = - sfd__h351503[24] ? - ((_theResult___fst_exp__h351411 == 8'd254) ? + enabled_ints___1__h918214 : + 16'd0 ; + assign _theResult___exp__h585008 = + sfd__h584584[24] ? + ((_theResult___fst_exp__h584492 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378444) : - ((_theResult___fst_exp__h351411 == 8'd0 && - sfd__h351503[24:23] == 2'b01) ? + din_inc___2_exp__h611525) : + ((_theResult___fst_exp__h584492 == 8'd0 && + sfd__h584584[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h351411) ; - assign _theResult___exp__h360509 = - sfd__h360085[24] ? - ((_theResult___fst_exp__h360067 == 8'd254) ? + _theResult___fst_exp__h584492) ; + assign _theResult___exp__h593590 = + sfd__h593166[24] ? + ((_theResult___fst_exp__h593148 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378468) : - ((_theResult___fst_exp__h360067 == 8'd0 && - sfd__h360085[24:23] == 2'b01) ? + din_inc___2_exp__h611549) : + ((_theResult___fst_exp__h593148 == 8'd0 && + sfd__h593166[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h360067) ; - assign _theResult___exp__h369693 = - sfd__h369269[24] ? - ((_theResult___fst_exp__h369177 == 8'd254) ? + _theResult___fst_exp__h593148) ; + assign _theResult___exp__h602774 = + sfd__h602350[24] ? + ((_theResult___fst_exp__h602258 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378498) : - ((_theResult___fst_exp__h369177 == 8'd0 && - sfd__h369269[24:23] == 2'b01) ? + din_inc___2_exp__h611579) : + ((_theResult___fst_exp__h602258 == 8'd0 && + sfd__h602350[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h369177) ; - assign _theResult___exp__h378329 = - sfd__h377881[24] ? - ((_theResult___fst_exp__h377862 == 8'd254) ? + _theResult___fst_exp__h602258) ; + assign _theResult___exp__h611410 = + sfd__h610962[24] ? + ((_theResult___fst_exp__h610943 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378522) : - ((_theResult___fst_exp__h377862 == 8'd0 && - sfd__h377881[24:23] == 2'b01) ? + din_inc___2_exp__h611603) : + ((_theResult___fst_exp__h610943 == 8'd0 && + sfd__h610962[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h377862) ; - assign _theResult___exp__h378431 = + _theResult___fst_exp__h610943) ; + assign _theResult___exp__h611512 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h378422 ; - assign _theResult___exp__h397617 = - sfd__h397193[24] ? - ((_theResult___fst_exp__h397101 == 8'd254) ? + _theResult___fst_exp__h611503 ; + assign _theResult___exp__h630757 = + sfd__h630333[24] ? + ((_theResult___fst_exp__h630241 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424134) : - ((_theResult___fst_exp__h397101 == 8'd0 && - sfd__h397193[24:23] == 2'b01) ? + din_inc___2_exp__h657274) : + ((_theResult___fst_exp__h630241 == 8'd0 && + sfd__h630333[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h397101) ; - assign _theResult___exp__h406199 = - sfd__h405775[24] ? - ((_theResult___fst_exp__h405757 == 8'd254) ? + _theResult___fst_exp__h630241) ; + assign _theResult___exp__h639339 = + sfd__h638915[24] ? + ((_theResult___fst_exp__h638897 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424158) : - ((_theResult___fst_exp__h405757 == 8'd0 && - sfd__h405775[24:23] == 2'b01) ? + din_inc___2_exp__h657298) : + ((_theResult___fst_exp__h638897 == 8'd0 && + sfd__h638915[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h405757) ; - assign _theResult___exp__h415383 = - sfd__h414959[24] ? - ((_theResult___fst_exp__h414867 == 8'd254) ? + _theResult___fst_exp__h638897) ; + assign _theResult___exp__h648523 = + sfd__h648099[24] ? + ((_theResult___fst_exp__h648007 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424188) : - ((_theResult___fst_exp__h414867 == 8'd0 && - sfd__h414959[24:23] == 2'b01) ? + din_inc___2_exp__h657328) : + ((_theResult___fst_exp__h648007 == 8'd0 && + sfd__h648099[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h414867) ; - assign _theResult___exp__h424019 = - sfd__h423571[24] ? - ((_theResult___fst_exp__h423552 == 8'd254) ? + _theResult___fst_exp__h648007) ; + assign _theResult___exp__h657159 = + sfd__h656711[24] ? + ((_theResult___fst_exp__h656692 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424212) : - ((_theResult___fst_exp__h423552 == 8'd0 && - sfd__h423571[24:23] == 2'b01) ? + din_inc___2_exp__h657352) : + ((_theResult___fst_exp__h656692 == 8'd0 && + sfd__h656711[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h423552) ; - assign _theResult___exp__h424121 = + _theResult___fst_exp__h656692) ; + assign _theResult___exp__h657261 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424112 ; - assign _theResult___exp__h443305 = - sfd__h442881[24] ? - ((_theResult___fst_exp__h442789 == 8'd254) ? + _theResult___fst_exp__h657252 ; + assign _theResult___exp__h676504 = + sfd__h676080[24] ? + ((_theResult___fst_exp__h675988 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469822) : - ((_theResult___fst_exp__h442789 == 8'd0 && - sfd__h442881[24:23] == 2'b01) ? + din_inc___2_exp__h703021) : + ((_theResult___fst_exp__h675988 == 8'd0 && + sfd__h676080[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h442789) ; - assign _theResult___exp__h451887 = - sfd__h451463[24] ? - ((_theResult___fst_exp__h451445 == 8'd254) ? + _theResult___fst_exp__h675988) ; + assign _theResult___exp__h685086 = + sfd__h684662[24] ? + ((_theResult___fst_exp__h684644 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469846) : - ((_theResult___fst_exp__h451445 == 8'd0 && - sfd__h451463[24:23] == 2'b01) ? + din_inc___2_exp__h703045) : + ((_theResult___fst_exp__h684644 == 8'd0 && + sfd__h684662[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h451445) ; - assign _theResult___exp__h461071 = - sfd__h460647[24] ? - ((_theResult___fst_exp__h460555 == 8'd254) ? + _theResult___fst_exp__h684644) ; + assign _theResult___exp__h694270 = + sfd__h693846[24] ? + ((_theResult___fst_exp__h693754 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469876) : - ((_theResult___fst_exp__h460555 == 8'd0 && - sfd__h460647[24:23] == 2'b01) ? + din_inc___2_exp__h703075) : + ((_theResult___fst_exp__h693754 == 8'd0 && + sfd__h693846[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h460555) ; - assign _theResult___exp__h469707 = - sfd__h469259[24] ? - ((_theResult___fst_exp__h469240 == 8'd254) ? + _theResult___fst_exp__h693754) ; + assign _theResult___exp__h702906 = + sfd__h702458[24] ? + ((_theResult___fst_exp__h702439 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469900) : - ((_theResult___fst_exp__h469240 == 8'd0 && - sfd__h469259[24:23] == 2'b01) ? + din_inc___2_exp__h703099) : + ((_theResult___fst_exp__h702439 == 8'd0 && + sfd__h702458[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h469240) ; - assign _theResult___exp__h469809 = + _theResult___fst_exp__h702439) ; + assign _theResult___exp__h703008 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h469800 ; - assign _theResult___exp__h499329 = - sfd__h498692[53] ? - ((_theResult___fst_exp__h498674 == 11'd2046) ? + _theResult___fst_exp__h702999 ; + assign _theResult___exp__h734868 = + sfd__h734231[53] ? + ((_theResult___fst_exp__h734213 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517924) : - ((_theResult___fst_exp__h498674 == 11'd0 && - sfd__h498692[53:52] == 2'b01) ? + din_inc___2_exp__h753463) : + ((_theResult___fst_exp__h734213 == 11'd0 && + sfd__h734231[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h498674) ; - assign _theResult___exp__h508980 = - sfd__h508343[53] ? - ((_theResult___fst_exp__h508251 == 11'd2046) ? + _theResult___fst_exp__h734213) ; + assign _theResult___exp__h744519 = + sfd__h743882[53] ? + ((_theResult___fst_exp__h743790 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517959) : - ((_theResult___fst_exp__h508251 == 11'd0 && - sfd__h508343[53:52] == 2'b01) ? + din_inc___2_exp__h753498) : + ((_theResult___fst_exp__h743790 == 11'd0 && + sfd__h743882[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h508251) ; - assign _theResult___exp__h517764 = - sfd__h517103[53] ? - ((_theResult___fst_exp__h517084 == 11'd2046) ? + _theResult___fst_exp__h743790) ; + assign _theResult___exp__h753303 = + sfd__h752642[53] ? + ((_theResult___fst_exp__h752623 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517985) : - ((_theResult___fst_exp__h517084 == 11'd0 && - sfd__h517103[53:52] == 2'b01) ? + din_inc___2_exp__h753524) : + ((_theResult___fst_exp__h752623 == 11'd0 && + sfd__h752642[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h517084) ; - assign _theResult___exp__h538130 = - sfd__h537493[53] ? - ((_theResult___fst_exp__h537475 == 11'd2046) ? + _theResult___fst_exp__h752623) ; + assign _theResult___exp__h773721 = + sfd__h773084[53] ? + ((_theResult___fst_exp__h773066 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556725) : - ((_theResult___fst_exp__h537475 == 11'd0 && - sfd__h537493[53:52] == 2'b01) ? + din_inc___2_exp__h792316) : + ((_theResult___fst_exp__h773066 == 11'd0 && + sfd__h773084[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h537475) ; - assign _theResult___exp__h547781 = - sfd__h547144[53] ? - ((_theResult___fst_exp__h547052 == 11'd2046) ? + _theResult___fst_exp__h773066) ; + assign _theResult___exp__h783372 = + sfd__h782735[53] ? + ((_theResult___fst_exp__h782643 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556760) : - ((_theResult___fst_exp__h547052 == 11'd0 && - sfd__h547144[53:52] == 2'b01) ? + din_inc___2_exp__h792351) : + ((_theResult___fst_exp__h782643 == 11'd0 && + sfd__h782735[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h547052) ; - assign _theResult___exp__h556565 = - sfd__h555904[53] ? - ((_theResult___fst_exp__h555885 == 11'd2046) ? + _theResult___fst_exp__h782643) ; + assign _theResult___exp__h792156 = + sfd__h791495[53] ? + ((_theResult___fst_exp__h791476 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556786) : - ((_theResult___fst_exp__h555885 == 11'd0 && - sfd__h555904[53:52] == 2'b01) ? + din_inc___2_exp__h792377) : + ((_theResult___fst_exp__h791476 == 11'd0 && + sfd__h791495[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h555885) ; - assign _theResult___exp__h577331 = - sfd__h576694[53] ? - ((_theResult___fst_exp__h576676 == 11'd2046) ? + _theResult___fst_exp__h791476) ; + assign _theResult___exp__h813025 = + sfd__h812388[53] ? + ((_theResult___fst_exp__h812370 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595926) : - ((_theResult___fst_exp__h576676 == 11'd0 && - sfd__h576694[53:52] == 2'b01) ? + din_inc___2_exp__h831620) : + ((_theResult___fst_exp__h812370 == 11'd0 && + sfd__h812388[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h576676) ; - assign _theResult___exp__h586982 = - sfd__h586345[53] ? - ((_theResult___fst_exp__h586253 == 11'd2046) ? + _theResult___fst_exp__h812370) ; + assign _theResult___exp__h822676 = + sfd__h822039[53] ? + ((_theResult___fst_exp__h821947 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595961) : - ((_theResult___fst_exp__h586253 == 11'd0 && - sfd__h586345[53:52] == 2'b01) ? + din_inc___2_exp__h831655) : + ((_theResult___fst_exp__h821947 == 11'd0 && + sfd__h822039[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h586253) ; - assign _theResult___exp__h595766 = - sfd__h595105[53] ? - ((_theResult___fst_exp__h595086 == 11'd2046) ? + _theResult___fst_exp__h821947) ; + assign _theResult___exp__h831460 = + sfd__h830799[53] ? + ((_theResult___fst_exp__h830780 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595987) : - ((_theResult___fst_exp__h595086 == 11'd0 && - sfd__h595105[53:52] == 2'b01) ? + din_inc___2_exp__h831681) : + ((_theResult___fst_exp__h830780 == 11'd0 && + sfd__h830799[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h595086) ; - assign _theResult___fst__h600259 = - a__h599837[63] ? a___1__h600264 : a__h599837 ; - assign _theResult___fst_exp__h351411 = - _theResult____h343300[56] ? + _theResult___fst_exp__h830780) ; + assign _theResult___fst__h836055 = + a__h835633[63] ? a___1__h836060 : a__h835633 ; + assign _theResult___fst_exp__h584492 = + _theResult____h576381[56] ? 8'd2 : - _theResult___fst_exp__h351485 ; - assign _theResult___fst_exp__h351476 = + _theResult___fst_exp__h584566 ; + assign _theResult___fst_exp__h584557 = 8'd0 - { 2'd0, - IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 } ; - assign _theResult___fst_exp__h351482 = - (!_theResult____h343300[56] && !_theResult____h343300[55] && - !_theResult____h343300[54] && - !_theResult____h343300[53] && - !_theResult____h343300[52] && - !_theResult____h343300[51] && - !_theResult____h343300[50] && - !_theResult____h343300[49] && - !_theResult____h343300[48] && - !_theResult____h343300[47] && - !_theResult____h343300[46] && - !_theResult____h343300[45] && - !_theResult____h343300[44] && - !_theResult____h343300[43] && - !_theResult____h343300[42] && - !_theResult____h343300[41] && - !_theResult____h343300[40] && - !_theResult____h343300[39] && - !_theResult____h343300[38] && - !_theResult____h343300[37] && - !_theResult____h343300[36] && - !_theResult____h343300[35] && - !_theResult____h343300[34] && - !_theResult____h343300[33] && - !_theResult____h343300[32] && - !_theResult____h343300[31] && - !_theResult____h343300[30] && - !_theResult____h343300[29] && - !_theResult____h343300[28] && - !_theResult____h343300[27] && - !_theResult____h343300[26] && - !_theResult____h343300[25] && - !_theResult____h343300[24] && - !_theResult____h343300[23] && - !_theResult____h343300[22] && - !_theResult____h343300[21] && - !_theResult____h343300[20] && - !_theResult____h343300[19] && - !_theResult____h343300[18] && - !_theResult____h343300[17] && - !_theResult____h343300[16] && - !_theResult____h343300[15] && - !_theResult____h343300[14] && - !_theResult____h343300[13] && - !_theResult____h343300[12] && - !_theResult____h343300[11] && - !_theResult____h343300[10] && - !_theResult____h343300[9] && - !_theResult____h343300[8] && - !_theResult____h343300[7] && - !_theResult____h343300[6] && - !_theResult____h343300[5] && - !_theResult____h343300[4] && - !_theResult____h343300[3] && - !_theResult____h343300[2] && - !_theResult____h343300[1] && - !_theResult____h343300[0] || - !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245) ? + IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352 } ; + assign _theResult___fst_exp__h584563 = + (!_theResult____h576381[56] && !_theResult____h576381[55] && + !_theResult____h576381[54] && + !_theResult____h576381[53] && + !_theResult____h576381[52] && + !_theResult____h576381[51] && + !_theResult____h576381[50] && + !_theResult____h576381[49] && + !_theResult____h576381[48] && + !_theResult____h576381[47] && + !_theResult____h576381[46] && + !_theResult____h576381[45] && + !_theResult____h576381[44] && + !_theResult____h576381[43] && + !_theResult____h576381[42] && + !_theResult____h576381[41] && + !_theResult____h576381[40] && + !_theResult____h576381[39] && + !_theResult____h576381[38] && + !_theResult____h576381[37] && + !_theResult____h576381[36] && + !_theResult____h576381[35] && + !_theResult____h576381[34] && + !_theResult____h576381[33] && + !_theResult____h576381[32] && + !_theResult____h576381[31] && + !_theResult____h576381[30] && + !_theResult____h576381[29] && + !_theResult____h576381[28] && + !_theResult____h576381[27] && + !_theResult____h576381[26] && + !_theResult____h576381[25] && + !_theResult____h576381[24] && + !_theResult____h576381[23] && + !_theResult____h576381[22] && + !_theResult____h576381[21] && + !_theResult____h576381[20] && + !_theResult____h576381[19] && + !_theResult____h576381[18] && + !_theResult____h576381[17] && + !_theResult____h576381[16] && + !_theResult____h576381[15] && + !_theResult____h576381[14] && + !_theResult____h576381[13] && + !_theResult____h576381[12] && + !_theResult____h576381[11] && + !_theResult____h576381[10] && + !_theResult____h576381[9] && + !_theResult____h576381[8] && + !_theResult____h576381[7] && + !_theResult____h576381[6] && + !_theResult____h576381[5] && + !_theResult____h576381[4] && + !_theResult____h576381[3] && + !_theResult____h576381[2] && + !_theResult____h576381[1] && + !_theResult____h576381[0] || + !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8354) ? 8'd0 : - _theResult___fst_exp__h351476 ; - assign _theResult___fst_exp__h351485 = - (!_theResult____h343300[56] && _theResult____h343300[55]) ? + _theResult___fst_exp__h584557 ; + assign _theResult___fst_exp__h584566 = + (!_theResult____h576381[56] && _theResult____h576381[55]) ? 8'd1 : - _theResult___fst_exp__h351482 ; - assign _theResult___fst_exp__h352008 = - (_theResult___fst_exp__h351411 == 8'd255) ? - _theResult___fst_exp__h351411 : - _theResult___fst_exp__h352005 ; - assign _theResult___fst_exp__h360058 = + _theResult___fst_exp__h584563 ; + assign _theResult___fst_exp__h585089 = + (_theResult___fst_exp__h584492 == 8'd255) ? + _theResult___fst_exp__h584492 : + _theResult___fst_exp__h585086 ; + assign _theResult___fst_exp__h593139 = 8'd129 - { 2'd0, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h360064 = + IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 } ; + assign _theResult___fst_exp__h593145 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && - NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || - !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476) ? + NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8528 || + !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8585) ? 8'd0 : - _theResult___fst_exp__h360058 ; - assign _theResult___fst_exp__h360067 = + _theResult___fst_exp__h593139 ; + assign _theResult___fst_exp__h593148 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h360064 : + _theResult___fst_exp__h593145 : 8'd129 ; - assign _theResult___fst_exp__h360590 = - (_theResult___fst_exp__h360067 == 8'd255) ? - _theResult___fst_exp__h360067 : - _theResult___fst_exp__h360587 ; - assign _theResult___fst_exp__h369177 = - _theResult____h360939[56] ? + assign _theResult___fst_exp__h593671 = + (_theResult___fst_exp__h593148 == 8'd255) ? + _theResult___fst_exp__h593148 : + _theResult___fst_exp__h593668 ; + assign _theResult___fst_exp__h602258 = + _theResult____h594020[56] ? 8'd2 : - _theResult___fst_exp__h369251 ; - assign _theResult___fst_exp__h369242 = + _theResult___fst_exp__h602332 ; + assign _theResult___fst_exp__h602323 = 8'd0 - { 2'd0, - IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 } ; - assign _theResult___fst_exp__h369248 = - (!_theResult____h360939[56] && !_theResult____h360939[55] && - !_theResult____h360939[54] && - !_theResult____h360939[53] && - !_theResult____h360939[52] && - !_theResult____h360939[51] && - !_theResult____h360939[50] && - !_theResult____h360939[49] && - !_theResult____h360939[48] && - !_theResult____h360939[47] && - !_theResult____h360939[46] && - !_theResult____h360939[45] && - !_theResult____h360939[44] && - !_theResult____h360939[43] && - !_theResult____h360939[42] && - !_theResult____h360939[41] && - !_theResult____h360939[40] && - !_theResult____h360939[39] && - !_theResult____h360939[38] && - !_theResult____h360939[37] && - !_theResult____h360939[36] && - !_theResult____h360939[35] && - !_theResult____h360939[34] && - !_theResult____h360939[33] && - !_theResult____h360939[32] && - !_theResult____h360939[31] && - !_theResult____h360939[30] && - !_theResult____h360939[29] && - !_theResult____h360939[28] && - !_theResult____h360939[27] && - !_theResult____h360939[26] && - !_theResult____h360939[25] && - !_theResult____h360939[24] && - !_theResult____h360939[23] && - !_theResult____h360939[22] && - !_theResult____h360939[21] && - !_theResult____h360939[20] && - !_theResult____h360939[19] && - !_theResult____h360939[18] && - !_theResult____h360939[17] && - !_theResult____h360939[16] && - !_theResult____h360939[15] && - !_theResult____h360939[14] && - !_theResult____h360939[13] && - !_theResult____h360939[12] && - !_theResult____h360939[11] && - !_theResult____h360939[10] && - !_theResult____h360939[9] && - !_theResult____h360939[8] && - !_theResult____h360939[7] && - !_theResult____h360939[6] && - !_theResult____h360939[5] && - !_theResult____h360939[4] && - !_theResult____h360939[3] && - !_theResult____h360939[2] && - !_theResult____h360939[1] && - !_theResult____h360939[0] || - !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796) ? + IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8903 } ; + assign _theResult___fst_exp__h602329 = + (!_theResult____h594020[56] && !_theResult____h594020[55] && + !_theResult____h594020[54] && + !_theResult____h594020[53] && + !_theResult____h594020[52] && + !_theResult____h594020[51] && + !_theResult____h594020[50] && + !_theResult____h594020[49] && + !_theResult____h594020[48] && + !_theResult____h594020[47] && + !_theResult____h594020[46] && + !_theResult____h594020[45] && + !_theResult____h594020[44] && + !_theResult____h594020[43] && + !_theResult____h594020[42] && + !_theResult____h594020[41] && + !_theResult____h594020[40] && + !_theResult____h594020[39] && + !_theResult____h594020[38] && + !_theResult____h594020[37] && + !_theResult____h594020[36] && + !_theResult____h594020[35] && + !_theResult____h594020[34] && + !_theResult____h594020[33] && + !_theResult____h594020[32] && + !_theResult____h594020[31] && + !_theResult____h594020[30] && + !_theResult____h594020[29] && + !_theResult____h594020[28] && + !_theResult____h594020[27] && + !_theResult____h594020[26] && + !_theResult____h594020[25] && + !_theResult____h594020[24] && + !_theResult____h594020[23] && + !_theResult____h594020[22] && + !_theResult____h594020[21] && + !_theResult____h594020[20] && + !_theResult____h594020[19] && + !_theResult____h594020[18] && + !_theResult____h594020[17] && + !_theResult____h594020[16] && + !_theResult____h594020[15] && + !_theResult____h594020[14] && + !_theResult____h594020[13] && + !_theResult____h594020[12] && + !_theResult____h594020[11] && + !_theResult____h594020[10] && + !_theResult____h594020[9] && + !_theResult____h594020[8] && + !_theResult____h594020[7] && + !_theResult____h594020[6] && + !_theResult____h594020[5] && + !_theResult____h594020[4] && + !_theResult____h594020[3] && + !_theResult____h594020[2] && + !_theResult____h594020[1] && + !_theResult____h594020[0] || + !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8905) ? 8'd0 : - _theResult___fst_exp__h369242 ; - assign _theResult___fst_exp__h369251 = - (!_theResult____h360939[56] && _theResult____h360939[55]) ? + _theResult___fst_exp__h602323 ; + assign _theResult___fst_exp__h602332 = + (!_theResult____h594020[56] && _theResult____h594020[55]) ? 8'd1 : - _theResult___fst_exp__h369248 ; - assign _theResult___fst_exp__h369774 = - (_theResult___fst_exp__h369177 == 8'd255) ? - _theResult___fst_exp__h369177 : - _theResult___fst_exp__h369771 ; - assign _theResult___fst_exp__h377814 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] == + _theResult___fst_exp__h602329 ; + assign _theResult___fst_exp__h602855 = + (_theResult___fst_exp__h602258 == 8'd255) ? + _theResult___fst_exp__h602258 : + _theResult___fst_exp__h602852 ; + assign _theResult___fst_exp__h610895 = + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48[7:0] == 8'd0) ? 8'd1 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] ; - assign _theResult___fst_exp__h377853 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] - + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48[7:0] ; + assign _theResult___fst_exp__h610934 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48[7:0] - { 2'd0, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h377859 = + IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 } ; + assign _theResult___fst_exp__h610940 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && - NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || - !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869) ? + NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8528 || + !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8978) ? 8'd0 : - _theResult___fst_exp__h377853 ; - assign _theResult___fst_exp__h377862 = + _theResult___fst_exp__h610934 ; + assign _theResult___fst_exp__h610943 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h377859 : - _theResult___fst_exp__h377814 ; - assign _theResult___fst_exp__h378410 = - (_theResult___fst_exp__h377862 == 8'd255) ? - _theResult___fst_exp__h377862 : - _theResult___fst_exp__h378407 ; - assign _theResult___fst_exp__h378419 = + _theResult___fst_exp__h610940 : + _theResult___fst_exp__h610895 ; + assign _theResult___fst_exp__h611491 = + (_theResult___fst_exp__h610943 == 8'd255) ? + _theResult___fst_exp__h610943 : + _theResult___fst_exp__h611488 ; + assign _theResult___fst_exp__h611500 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_exp__h360593 : - _theResult___fst_exp__h343282) : - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_exp__h378413 : - _theResult___fst_exp__h343282) ; - assign _theResult___fst_exp__h378422 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 ? + _theResult___snd_fst_exp__h593674 : + _theResult___fst_exp__h576363) : + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 ? + _theResult___snd_fst_exp__h611494 : + _theResult___fst_exp__h576363) ; + assign _theResult___fst_exp__h611503 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h378419 ; - assign _theResult___fst_exp__h397101 = - _theResult____h388992[56] ? + _theResult___fst_exp__h611500 ; + assign _theResult___fst_exp__h630241 = + _theResult____h622132[56] ? 8'd2 : - _theResult___fst_exp__h397175 ; - assign _theResult___fst_exp__h397166 = + _theResult___fst_exp__h630315 ; + assign _theResult___fst_exp__h630306 = 8'd0 - { 2'd0, - IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ; - assign _theResult___fst_exp__h397172 = - (!_theResult____h388992[56] && !_theResult____h388992[55] && - !_theResult____h388992[54] && - !_theResult____h388992[53] && - !_theResult____h388992[52] && - !_theResult____h388992[51] && - !_theResult____h388992[50] && - !_theResult____h388992[49] && - !_theResult____h388992[48] && - !_theResult____h388992[47] && - !_theResult____h388992[46] && - !_theResult____h388992[45] && - !_theResult____h388992[44] && - !_theResult____h388992[43] && - !_theResult____h388992[42] && - !_theResult____h388992[41] && - !_theResult____h388992[40] && - !_theResult____h388992[39] && - !_theResult____h388992[38] && - !_theResult____h388992[37] && - !_theResult____h388992[36] && - !_theResult____h388992[35] && - !_theResult____h388992[34] && - !_theResult____h388992[33] && - !_theResult____h388992[32] && - !_theResult____h388992[31] && - !_theResult____h388992[30] && - !_theResult____h388992[29] && - !_theResult____h388992[28] && - !_theResult____h388992[27] && - !_theResult____h388992[26] && - !_theResult____h388992[25] && - !_theResult____h388992[24] && - !_theResult____h388992[23] && - !_theResult____h388992[22] && - !_theResult____h388992[21] && - !_theResult____h388992[20] && - !_theResult____h388992[19] && - !_theResult____h388992[18] && - !_theResult____h388992[17] && - !_theResult____h388992[16] && - !_theResult____h388992[15] && - !_theResult____h388992[14] && - !_theResult____h388992[13] && - !_theResult____h388992[12] && - !_theResult____h388992[11] && - !_theResult____h388992[10] && - !_theResult____h388992[9] && - !_theResult____h388992[8] && - !_theResult____h388992[7] && - !_theResult____h388992[6] && - !_theResult____h388992[5] && - !_theResult____h388992[4] && - !_theResult____h388992[3] && - !_theResult____h388992[2] && - !_theResult____h388992[1] && - !_theResult____h388992[0] || - !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637) ? + IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749 } ; + assign _theResult___fst_exp__h630312 = + (!_theResult____h622132[56] && !_theResult____h622132[55] && + !_theResult____h622132[54] && + !_theResult____h622132[53] && + !_theResult____h622132[52] && + !_theResult____h622132[51] && + !_theResult____h622132[50] && + !_theResult____h622132[49] && + !_theResult____h622132[48] && + !_theResult____h622132[47] && + !_theResult____h622132[46] && + !_theResult____h622132[45] && + !_theResult____h622132[44] && + !_theResult____h622132[43] && + !_theResult____h622132[42] && + !_theResult____h622132[41] && + !_theResult____h622132[40] && + !_theResult____h622132[39] && + !_theResult____h622132[38] && + !_theResult____h622132[37] && + !_theResult____h622132[36] && + !_theResult____h622132[35] && + !_theResult____h622132[34] && + !_theResult____h622132[33] && + !_theResult____h622132[32] && + !_theResult____h622132[31] && + !_theResult____h622132[30] && + !_theResult____h622132[29] && + !_theResult____h622132[28] && + !_theResult____h622132[27] && + !_theResult____h622132[26] && + !_theResult____h622132[25] && + !_theResult____h622132[24] && + !_theResult____h622132[23] && + !_theResult____h622132[22] && + !_theResult____h622132[21] && + !_theResult____h622132[20] && + !_theResult____h622132[19] && + !_theResult____h622132[18] && + !_theResult____h622132[17] && + !_theResult____h622132[16] && + !_theResult____h622132[15] && + !_theResult____h622132[14] && + !_theResult____h622132[13] && + !_theResult____h622132[12] && + !_theResult____h622132[11] && + !_theResult____h622132[10] && + !_theResult____h622132[9] && + !_theResult____h622132[8] && + !_theResult____h622132[7] && + !_theResult____h622132[6] && + !_theResult____h622132[5] && + !_theResult____h622132[4] && + !_theResult____h622132[3] && + !_theResult____h622132[2] && + !_theResult____h622132[1] && + !_theResult____h622132[0] || + !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9751) ? 8'd0 : - _theResult___fst_exp__h397166 ; - assign _theResult___fst_exp__h397175 = - (!_theResult____h388992[56] && _theResult____h388992[55]) ? + _theResult___fst_exp__h630306 ; + assign _theResult___fst_exp__h630315 = + (!_theResult____h622132[56] && _theResult____h622132[55]) ? 8'd1 : - _theResult___fst_exp__h397172 ; - assign _theResult___fst_exp__h397698 = - (_theResult___fst_exp__h397101 == 8'd255) ? - _theResult___fst_exp__h397101 : - _theResult___fst_exp__h397695 ; - assign _theResult___fst_exp__h405748 = + _theResult___fst_exp__h630312 ; + assign _theResult___fst_exp__h630838 = + (_theResult___fst_exp__h630241 == 8'd255) ? + _theResult___fst_exp__h630241 : + _theResult___fst_exp__h630835 ; + assign _theResult___fst_exp__h638888 = 8'd129 - { 2'd0, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h405754 = + IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 } ; + assign _theResult___fst_exp__h638894 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && - NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || - !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868) ? + NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9925 || + !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9982) ? 8'd0 : - _theResult___fst_exp__h405748 ; - assign _theResult___fst_exp__h405757 = + _theResult___fst_exp__h638888 ; + assign _theResult___fst_exp__h638897 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h405754 : + _theResult___fst_exp__h638894 : 8'd129 ; - assign _theResult___fst_exp__h406280 = - (_theResult___fst_exp__h405757 == 8'd255) ? - _theResult___fst_exp__h405757 : - _theResult___fst_exp__h406277 ; - assign _theResult___fst_exp__h414867 = - _theResult____h406629[56] ? + assign _theResult___fst_exp__h639420 = + (_theResult___fst_exp__h638897 == 8'd255) ? + _theResult___fst_exp__h638897 : + _theResult___fst_exp__h639417 ; + assign _theResult___fst_exp__h648007 = + _theResult____h639769[56] ? 8'd2 : - _theResult___fst_exp__h414941 ; - assign _theResult___fst_exp__h414932 = + _theResult___fst_exp__h648081 ; + assign _theResult___fst_exp__h648072 = 8'd0 - { 2'd0, - IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ; - assign _theResult___fst_exp__h414938 = - (!_theResult____h406629[56] && !_theResult____h406629[55] && - !_theResult____h406629[54] && - !_theResult____h406629[53] && - !_theResult____h406629[52] && - !_theResult____h406629[51] && - !_theResult____h406629[50] && - !_theResult____h406629[49] && - !_theResult____h406629[48] && - !_theResult____h406629[47] && - !_theResult____h406629[46] && - !_theResult____h406629[45] && - !_theResult____h406629[44] && - !_theResult____h406629[43] && - !_theResult____h406629[42] && - !_theResult____h406629[41] && - !_theResult____h406629[40] && - !_theResult____h406629[39] && - !_theResult____h406629[38] && - !_theResult____h406629[37] && - !_theResult____h406629[36] && - !_theResult____h406629[35] && - !_theResult____h406629[34] && - !_theResult____h406629[33] && - !_theResult____h406629[32] && - !_theResult____h406629[31] && - !_theResult____h406629[30] && - !_theResult____h406629[29] && - !_theResult____h406629[28] && - !_theResult____h406629[27] && - !_theResult____h406629[26] && - !_theResult____h406629[25] && - !_theResult____h406629[24] && - !_theResult____h406629[23] && - !_theResult____h406629[22] && - !_theResult____h406629[21] && - !_theResult____h406629[20] && - !_theResult____h406629[19] && - !_theResult____h406629[18] && - !_theResult____h406629[17] && - !_theResult____h406629[16] && - !_theResult____h406629[15] && - !_theResult____h406629[14] && - !_theResult____h406629[13] && - !_theResult____h406629[12] && - !_theResult____h406629[11] && - !_theResult____h406629[10] && - !_theResult____h406629[9] && - !_theResult____h406629[8] && - !_theResult____h406629[7] && - !_theResult____h406629[6] && - !_theResult____h406629[5] && - !_theResult____h406629[4] && - !_theResult____h406629[3] && - !_theResult____h406629[2] && - !_theResult____h406629[1] && - !_theResult____h406629[0] || - !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188) ? + IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10300 } ; + assign _theResult___fst_exp__h648078 = + (!_theResult____h639769[56] && !_theResult____h639769[55] && + !_theResult____h639769[54] && + !_theResult____h639769[53] && + !_theResult____h639769[52] && + !_theResult____h639769[51] && + !_theResult____h639769[50] && + !_theResult____h639769[49] && + !_theResult____h639769[48] && + !_theResult____h639769[47] && + !_theResult____h639769[46] && + !_theResult____h639769[45] && + !_theResult____h639769[44] && + !_theResult____h639769[43] && + !_theResult____h639769[42] && + !_theResult____h639769[41] && + !_theResult____h639769[40] && + !_theResult____h639769[39] && + !_theResult____h639769[38] && + !_theResult____h639769[37] && + !_theResult____h639769[36] && + !_theResult____h639769[35] && + !_theResult____h639769[34] && + !_theResult____h639769[33] && + !_theResult____h639769[32] && + !_theResult____h639769[31] && + !_theResult____h639769[30] && + !_theResult____h639769[29] && + !_theResult____h639769[28] && + !_theResult____h639769[27] && + !_theResult____h639769[26] && + !_theResult____h639769[25] && + !_theResult____h639769[24] && + !_theResult____h639769[23] && + !_theResult____h639769[22] && + !_theResult____h639769[21] && + !_theResult____h639769[20] && + !_theResult____h639769[19] && + !_theResult____h639769[18] && + !_theResult____h639769[17] && + !_theResult____h639769[16] && + !_theResult____h639769[15] && + !_theResult____h639769[14] && + !_theResult____h639769[13] && + !_theResult____h639769[12] && + !_theResult____h639769[11] && + !_theResult____h639769[10] && + !_theResult____h639769[9] && + !_theResult____h639769[8] && + !_theResult____h639769[7] && + !_theResult____h639769[6] && + !_theResult____h639769[5] && + !_theResult____h639769[4] && + !_theResult____h639769[3] && + !_theResult____h639769[2] && + !_theResult____h639769[1] && + !_theResult____h639769[0] || + !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10302) ? 8'd0 : - _theResult___fst_exp__h414932 ; - assign _theResult___fst_exp__h414941 = - (!_theResult____h406629[56] && _theResult____h406629[55]) ? + _theResult___fst_exp__h648072 ; + assign _theResult___fst_exp__h648081 = + (!_theResult____h639769[56] && _theResult____h639769[55]) ? 8'd1 : - _theResult___fst_exp__h414938 ; - assign _theResult___fst_exp__h415464 = - (_theResult___fst_exp__h414867 == 8'd255) ? - _theResult___fst_exp__h414867 : - _theResult___fst_exp__h415461 ; - assign _theResult___fst_exp__h423504 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] == + _theResult___fst_exp__h648078 ; + assign _theResult___fst_exp__h648604 = + (_theResult___fst_exp__h648007 == 8'd255) ? + _theResult___fst_exp__h648007 : + _theResult___fst_exp__h648601 ; + assign _theResult___fst_exp__h656644 = + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83[7:0] == 8'd0) ? 8'd1 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] ; - assign _theResult___fst_exp__h423543 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] - + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83[7:0] ; + assign _theResult___fst_exp__h656683 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83[7:0] - { 2'd0, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h423549 = + IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 } ; + assign _theResult___fst_exp__h656689 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && - NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || - !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261) ? + NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9925 || + !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10375) ? 8'd0 : - _theResult___fst_exp__h423543 ; - assign _theResult___fst_exp__h423552 = + _theResult___fst_exp__h656683 ; + assign _theResult___fst_exp__h656692 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h423549 : - _theResult___fst_exp__h423504 ; - assign _theResult___fst_exp__h424100 = - (_theResult___fst_exp__h423552 == 8'd255) ? - _theResult___fst_exp__h423552 : - _theResult___fst_exp__h424097 ; - assign _theResult___fst_exp__h424109 = + _theResult___fst_exp__h656689 : + _theResult___fst_exp__h656644 ; + assign _theResult___fst_exp__h657240 = + (_theResult___fst_exp__h656692 == 8'd255) ? + _theResult___fst_exp__h656692 : + _theResult___fst_exp__h657237 ; + assign _theResult___fst_exp__h657249 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_exp__h406283 : - _theResult___fst_exp__h388974) : - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_exp__h424103 : - _theResult___fst_exp__h388974) ; - assign _theResult___fst_exp__h424112 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 ? + _theResult___snd_fst_exp__h639423 : + _theResult___fst_exp__h622114) : + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 ? + _theResult___snd_fst_exp__h657243 : + _theResult___fst_exp__h622114) ; + assign _theResult___fst_exp__h657252 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h424109 ; - assign _theResult___fst_exp__h442789 = - _theResult____h434680[56] ? + _theResult___fst_exp__h657249 ; + assign _theResult___fst_exp__h675988 = + _theResult____h667879[56] ? 8'd2 : - _theResult___fst_exp__h442863 ; - assign _theResult___fst_exp__h442854 = + _theResult___fst_exp__h676062 ; + assign _theResult___fst_exp__h676053 = 8'd0 - { 2'd0, - IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ; - assign _theResult___fst_exp__h442860 = - (!_theResult____h434680[56] && !_theResult____h434680[55] && - !_theResult____h434680[54] && - !_theResult____h434680[53] && - !_theResult____h434680[52] && - !_theResult____h434680[51] && - !_theResult____h434680[50] && - !_theResult____h434680[49] && - !_theResult____h434680[48] && - !_theResult____h434680[47] && - !_theResult____h434680[46] && - !_theResult____h434680[45] && - !_theResult____h434680[44] && - !_theResult____h434680[43] && - !_theResult____h434680[42] && - !_theResult____h434680[41] && - !_theResult____h434680[40] && - !_theResult____h434680[39] && - !_theResult____h434680[38] && - !_theResult____h434680[37] && - !_theResult____h434680[36] && - !_theResult____h434680[35] && - !_theResult____h434680[34] && - !_theResult____h434680[33] && - !_theResult____h434680[32] && - !_theResult____h434680[31] && - !_theResult____h434680[30] && - !_theResult____h434680[29] && - !_theResult____h434680[28] && - !_theResult____h434680[27] && - !_theResult____h434680[26] && - !_theResult____h434680[25] && - !_theResult____h434680[24] && - !_theResult____h434680[23] && - !_theResult____h434680[22] && - !_theResult____h434680[21] && - !_theResult____h434680[20] && - !_theResult____h434680[19] && - !_theResult____h434680[18] && - !_theResult____h434680[17] && - !_theResult____h434680[16] && - !_theResult____h434680[15] && - !_theResult____h434680[14] && - !_theResult____h434680[13] && - !_theResult____h434680[12] && - !_theResult____h434680[11] && - !_theResult____h434680[10] && - !_theResult____h434680[9] && - !_theResult____h434680[8] && - !_theResult____h434680[7] && - !_theResult____h434680[6] && - !_theResult____h434680[5] && - !_theResult____h434680[4] && - !_theResult____h434680[3] && - !_theResult____h434680[2] && - !_theResult____h434680[1] && - !_theResult____h434680[0] || - !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029) ? + IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146 } ; + assign _theResult___fst_exp__h676059 = + (!_theResult____h667879[56] && !_theResult____h667879[55] && + !_theResult____h667879[54] && + !_theResult____h667879[53] && + !_theResult____h667879[52] && + !_theResult____h667879[51] && + !_theResult____h667879[50] && + !_theResult____h667879[49] && + !_theResult____h667879[48] && + !_theResult____h667879[47] && + !_theResult____h667879[46] && + !_theResult____h667879[45] && + !_theResult____h667879[44] && + !_theResult____h667879[43] && + !_theResult____h667879[42] && + !_theResult____h667879[41] && + !_theResult____h667879[40] && + !_theResult____h667879[39] && + !_theResult____h667879[38] && + !_theResult____h667879[37] && + !_theResult____h667879[36] && + !_theResult____h667879[35] && + !_theResult____h667879[34] && + !_theResult____h667879[33] && + !_theResult____h667879[32] && + !_theResult____h667879[31] && + !_theResult____h667879[30] && + !_theResult____h667879[29] && + !_theResult____h667879[28] && + !_theResult____h667879[27] && + !_theResult____h667879[26] && + !_theResult____h667879[25] && + !_theResult____h667879[24] && + !_theResult____h667879[23] && + !_theResult____h667879[22] && + !_theResult____h667879[21] && + !_theResult____h667879[20] && + !_theResult____h667879[19] && + !_theResult____h667879[18] && + !_theResult____h667879[17] && + !_theResult____h667879[16] && + !_theResult____h667879[15] && + !_theResult____h667879[14] && + !_theResult____h667879[13] && + !_theResult____h667879[12] && + !_theResult____h667879[11] && + !_theResult____h667879[10] && + !_theResult____h667879[9] && + !_theResult____h667879[8] && + !_theResult____h667879[7] && + !_theResult____h667879[6] && + !_theResult____h667879[5] && + !_theResult____h667879[4] && + !_theResult____h667879[3] && + !_theResult____h667879[2] && + !_theResult____h667879[1] && + !_theResult____h667879[0] || + !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11148) ? 8'd0 : - _theResult___fst_exp__h442854 ; - assign _theResult___fst_exp__h442863 = - (!_theResult____h434680[56] && _theResult____h434680[55]) ? + _theResult___fst_exp__h676053 ; + assign _theResult___fst_exp__h676062 = + (!_theResult____h667879[56] && _theResult____h667879[55]) ? 8'd1 : - _theResult___fst_exp__h442860 ; - assign _theResult___fst_exp__h443386 = - (_theResult___fst_exp__h442789 == 8'd255) ? - _theResult___fst_exp__h442789 : - _theResult___fst_exp__h443383 ; - assign _theResult___fst_exp__h451436 = + _theResult___fst_exp__h676059 ; + assign _theResult___fst_exp__h676585 = + (_theResult___fst_exp__h675988 == 8'd255) ? + _theResult___fst_exp__h675988 : + _theResult___fst_exp__h676582 ; + assign _theResult___fst_exp__h684635 = 8'd129 - { 2'd0, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h451442 = + IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 } ; + assign _theResult___fst_exp__h684641 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && - NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || - !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260) ? + NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11322 || + !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11379) ? 8'd0 : - _theResult___fst_exp__h451436 ; - assign _theResult___fst_exp__h451445 = + _theResult___fst_exp__h684635 ; + assign _theResult___fst_exp__h684644 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h451442 : + _theResult___fst_exp__h684641 : 8'd129 ; - assign _theResult___fst_exp__h451968 = - (_theResult___fst_exp__h451445 == 8'd255) ? - _theResult___fst_exp__h451445 : - _theResult___fst_exp__h451965 ; - assign _theResult___fst_exp__h460555 = - _theResult____h452317[56] ? + assign _theResult___fst_exp__h685167 = + (_theResult___fst_exp__h684644 == 8'd255) ? + _theResult___fst_exp__h684644 : + _theResult___fst_exp__h685164 ; + assign _theResult___fst_exp__h693754 = + _theResult____h685516[56] ? 8'd2 : - _theResult___fst_exp__h460629 ; - assign _theResult___fst_exp__h460620 = + _theResult___fst_exp__h693828 ; + assign _theResult___fst_exp__h693819 = 8'd0 - { 2'd0, - IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ; - assign _theResult___fst_exp__h460626 = - (!_theResult____h452317[56] && !_theResult____h452317[55] && - !_theResult____h452317[54] && - !_theResult____h452317[53] && - !_theResult____h452317[52] && - !_theResult____h452317[51] && - !_theResult____h452317[50] && - !_theResult____h452317[49] && - !_theResult____h452317[48] && - !_theResult____h452317[47] && - !_theResult____h452317[46] && - !_theResult____h452317[45] && - !_theResult____h452317[44] && - !_theResult____h452317[43] && - !_theResult____h452317[42] && - !_theResult____h452317[41] && - !_theResult____h452317[40] && - !_theResult____h452317[39] && - !_theResult____h452317[38] && - !_theResult____h452317[37] && - !_theResult____h452317[36] && - !_theResult____h452317[35] && - !_theResult____h452317[34] && - !_theResult____h452317[33] && - !_theResult____h452317[32] && - !_theResult____h452317[31] && - !_theResult____h452317[30] && - !_theResult____h452317[29] && - !_theResult____h452317[28] && - !_theResult____h452317[27] && - !_theResult____h452317[26] && - !_theResult____h452317[25] && - !_theResult____h452317[24] && - !_theResult____h452317[23] && - !_theResult____h452317[22] && - !_theResult____h452317[21] && - !_theResult____h452317[20] && - !_theResult____h452317[19] && - !_theResult____h452317[18] && - !_theResult____h452317[17] && - !_theResult____h452317[16] && - !_theResult____h452317[15] && - !_theResult____h452317[14] && - !_theResult____h452317[13] && - !_theResult____h452317[12] && - !_theResult____h452317[11] && - !_theResult____h452317[10] && - !_theResult____h452317[9] && - !_theResult____h452317[8] && - !_theResult____h452317[7] && - !_theResult____h452317[6] && - !_theResult____h452317[5] && - !_theResult____h452317[4] && - !_theResult____h452317[3] && - !_theResult____h452317[2] && - !_theResult____h452317[1] && - !_theResult____h452317[0] || - !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580) ? + IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11697 } ; + assign _theResult___fst_exp__h693825 = + (!_theResult____h685516[56] && !_theResult____h685516[55] && + !_theResult____h685516[54] && + !_theResult____h685516[53] && + !_theResult____h685516[52] && + !_theResult____h685516[51] && + !_theResult____h685516[50] && + !_theResult____h685516[49] && + !_theResult____h685516[48] && + !_theResult____h685516[47] && + !_theResult____h685516[46] && + !_theResult____h685516[45] && + !_theResult____h685516[44] && + !_theResult____h685516[43] && + !_theResult____h685516[42] && + !_theResult____h685516[41] && + !_theResult____h685516[40] && + !_theResult____h685516[39] && + !_theResult____h685516[38] && + !_theResult____h685516[37] && + !_theResult____h685516[36] && + !_theResult____h685516[35] && + !_theResult____h685516[34] && + !_theResult____h685516[33] && + !_theResult____h685516[32] && + !_theResult____h685516[31] && + !_theResult____h685516[30] && + !_theResult____h685516[29] && + !_theResult____h685516[28] && + !_theResult____h685516[27] && + !_theResult____h685516[26] && + !_theResult____h685516[25] && + !_theResult____h685516[24] && + !_theResult____h685516[23] && + !_theResult____h685516[22] && + !_theResult____h685516[21] && + !_theResult____h685516[20] && + !_theResult____h685516[19] && + !_theResult____h685516[18] && + !_theResult____h685516[17] && + !_theResult____h685516[16] && + !_theResult____h685516[15] && + !_theResult____h685516[14] && + !_theResult____h685516[13] && + !_theResult____h685516[12] && + !_theResult____h685516[11] && + !_theResult____h685516[10] && + !_theResult____h685516[9] && + !_theResult____h685516[8] && + !_theResult____h685516[7] && + !_theResult____h685516[6] && + !_theResult____h685516[5] && + !_theResult____h685516[4] && + !_theResult____h685516[3] && + !_theResult____h685516[2] && + !_theResult____h685516[1] && + !_theResult____h685516[0] || + !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11699) ? 8'd0 : - _theResult___fst_exp__h460620 ; - assign _theResult___fst_exp__h460629 = - (!_theResult____h452317[56] && _theResult____h452317[55]) ? + _theResult___fst_exp__h693819 ; + assign _theResult___fst_exp__h693828 = + (!_theResult____h685516[56] && _theResult____h685516[55]) ? 8'd1 : - _theResult___fst_exp__h460626 ; - assign _theResult___fst_exp__h461152 = - (_theResult___fst_exp__h460555 == 8'd255) ? - _theResult___fst_exp__h460555 : - _theResult___fst_exp__h461149 ; - assign _theResult___fst_exp__h469192 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] == + _theResult___fst_exp__h693825 ; + assign _theResult___fst_exp__h694351 = + (_theResult___fst_exp__h693754 == 8'd255) ? + _theResult___fst_exp__h693754 : + _theResult___fst_exp__h694348 ; + assign _theResult___fst_exp__h702391 = + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118[7:0] == 8'd0) ? 8'd1 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] ; - assign _theResult___fst_exp__h469231 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] - + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118[7:0] ; + assign _theResult___fst_exp__h702430 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118[7:0] - { 2'd0, - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h469237 = + IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 } ; + assign _theResult___fst_exp__h702436 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && - NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || - !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653) ? + NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11322 || + !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11772) ? 8'd0 : - _theResult___fst_exp__h469231 ; - assign _theResult___fst_exp__h469240 = + _theResult___fst_exp__h702430 ; + assign _theResult___fst_exp__h702439 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h469237 : - _theResult___fst_exp__h469192 ; - assign _theResult___fst_exp__h469788 = - (_theResult___fst_exp__h469240 == 8'd255) ? - _theResult___fst_exp__h469240 : - _theResult___fst_exp__h469785 ; - assign _theResult___fst_exp__h469797 = + _theResult___fst_exp__h702436 : + _theResult___fst_exp__h702391 ; + assign _theResult___fst_exp__h702987 = + (_theResult___fst_exp__h702439 == 8'd255) ? + _theResult___fst_exp__h702439 : + _theResult___fst_exp__h702984 ; + assign _theResult___fst_exp__h702996 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_exp__h451971 : - _theResult___fst_exp__h434662) : - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_exp__h469791 : - _theResult___fst_exp__h434662) ; - assign _theResult___fst_exp__h469800 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 ? + _theResult___snd_fst_exp__h685170 : + _theResult___fst_exp__h667861) : + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 ? + _theResult___snd_fst_exp__h702990 : + _theResult___fst_exp__h667861) ; + assign _theResult___fst_exp__h702999 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h469797 ; - assign _theResult___fst_exp__h483601 = + _theResult___fst_exp__h702996 ; + assign _theResult___fst_exp__h719140 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 ; - assign _theResult___fst_exp__h498665 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q26 ; + assign _theResult___fst_exp__h734204 = 11'd897 - { 5'd0, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ; - assign _theResult___fst_exp__h498671 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && - !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548 || - !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577) ? + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 } ; + assign _theResult___fst_exp__h734210 = + (f1_exp__h714825 == 8'd0 && !f1_sfd__h714826[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12718) ? 11'd0 : - _theResult___fst_exp__h498665 ; - assign _theResult___fst_exp__h498674 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___fst_exp__h498671 : + _theResult___fst_exp__h734204 ; + assign _theResult___fst_exp__h734213 = + (f1_exp__h714825 == 8'd0) ? + _theResult___fst_exp__h734210 : 11'd897 ; - assign _theResult___fst_exp__h499429 = + assign _theResult___fst_exp__h734968 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 ; - assign _theResult___fst_exp__h499432 = - (_theResult___fst_exp__h498674 == 11'd2047) ? - _theResult___fst_exp__h498674 : - _theResult___fst_exp__h499429 ; - assign _theResult___fst_exp__h508251 = - _theResult____h500015[56] ? + CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 ; + assign _theResult___fst_exp__h734971 = + (_theResult___fst_exp__h734213 == 11'd2047) ? + _theResult___fst_exp__h734213 : + _theResult___fst_exp__h734968 ; + assign _theResult___fst_exp__h743790 = + _theResult____h735554[56] ? 11'd2 : - _theResult___fst_exp__h508325 ; - assign _theResult___fst_exp__h508316 = + _theResult___fst_exp__h743864 ; + assign _theResult___fst_exp__h743855 = 11'd0 - { 5'd0, - IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 } ; - assign _theResult___fst_exp__h508322 = - (!_theResult____h500015[56] && !_theResult____h500015[55] && - !_theResult____h500015[54] && - !_theResult____h500015[53] && - !_theResult____h500015[52] && - !_theResult____h500015[51] && - !_theResult____h500015[50] && - !_theResult____h500015[49] && - !_theResult____h500015[48] && - !_theResult____h500015[47] && - !_theResult____h500015[46] && - !_theResult____h500015[45] && - !_theResult____h500015[44] && - !_theResult____h500015[43] && - !_theResult____h500015[42] && - !_theResult____h500015[41] && - !_theResult____h500015[40] && - !_theResult____h500015[39] && - !_theResult____h500015[38] && - !_theResult____h500015[37] && - !_theResult____h500015[36] && - !_theResult____h500015[35] && - !_theResult____h500015[34] && - !_theResult____h500015[33] && - !_theResult____h500015[32] && - !_theResult____h500015[31] && - !_theResult____h500015[30] && - !_theResult____h500015[29] && - !_theResult____h500015[28] && - !_theResult____h500015[27] && - !_theResult____h500015[26] && - !_theResult____h500015[25] && - !_theResult____h500015[24] && - !_theResult____h500015[23] && - !_theResult____h500015[22] && - !_theResult____h500015[21] && - !_theResult____h500015[20] && - !_theResult____h500015[19] && - !_theResult____h500015[18] && - !_theResult____h500015[17] && - !_theResult____h500015[16] && - !_theResult____h500015[15] && - !_theResult____h500015[14] && - !_theResult____h500015[13] && - !_theResult____h500015[12] && - !_theResult____h500015[11] && - !_theResult____h500015[10] && - !_theResult____h500015[9] && - !_theResult____h500015[8] && - !_theResult____h500015[7] && - !_theResult____h500015[6] && - !_theResult____h500015[5] && - !_theResult____h500015[4] && - !_theResult____h500015[3] && - !_theResult____h500015[2] && - !_theResult____h500015[1] && - !_theResult____h500015[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889) ? + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13028 } ; + assign _theResult___fst_exp__h743861 = + (!_theResult____h735554[56] && !_theResult____h735554[55] && + !_theResult____h735554[54] && + !_theResult____h735554[53] && + !_theResult____h735554[52] && + !_theResult____h735554[51] && + !_theResult____h735554[50] && + !_theResult____h735554[49] && + !_theResult____h735554[48] && + !_theResult____h735554[47] && + !_theResult____h735554[46] && + !_theResult____h735554[45] && + !_theResult____h735554[44] && + !_theResult____h735554[43] && + !_theResult____h735554[42] && + !_theResult____h735554[41] && + !_theResult____h735554[40] && + !_theResult____h735554[39] && + !_theResult____h735554[38] && + !_theResult____h735554[37] && + !_theResult____h735554[36] && + !_theResult____h735554[35] && + !_theResult____h735554[34] && + !_theResult____h735554[33] && + !_theResult____h735554[32] && + !_theResult____h735554[31] && + !_theResult____h735554[30] && + !_theResult____h735554[29] && + !_theResult____h735554[28] && + !_theResult____h735554[27] && + !_theResult____h735554[26] && + !_theResult____h735554[25] && + !_theResult____h735554[24] && + !_theResult____h735554[23] && + !_theResult____h735554[22] && + !_theResult____h735554[21] && + !_theResult____h735554[20] && + !_theResult____h735554[19] && + !_theResult____h735554[18] && + !_theResult____h735554[17] && + !_theResult____h735554[16] && + !_theResult____h735554[15] && + !_theResult____h735554[14] && + !_theResult____h735554[13] && + !_theResult____h735554[12] && + !_theResult____h735554[11] && + !_theResult____h735554[10] && + !_theResult____h735554[9] && + !_theResult____h735554[8] && + !_theResult____h735554[7] && + !_theResult____h735554[6] && + !_theResult____h735554[5] && + !_theResult____h735554[4] && + !_theResult____h735554[3] && + !_theResult____h735554[2] && + !_theResult____h735554[1] && + !_theResult____h735554[0] || + !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13030) ? 11'd0 : - _theResult___fst_exp__h508316 ; - assign _theResult___fst_exp__h508325 = - (!_theResult____h500015[56] && _theResult____h500015[55]) ? + _theResult___fst_exp__h743855 ; + assign _theResult___fst_exp__h743864 = + (!_theResult____h735554[56] && _theResult____h735554[55]) ? 11'd1 : - _theResult___fst_exp__h508322 ; - assign _theResult___fst_exp__h509080 = + _theResult___fst_exp__h743861 ; + assign _theResult___fst_exp__h744619 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 ; - assign _theResult___fst_exp__h509083 = - (_theResult___fst_exp__h508251 == 11'd2047) ? - _theResult___fst_exp__h508251 : - _theResult___fst_exp__h509080 ; - assign _theResult___fst_exp__h517036 = - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] == + CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 ; + assign _theResult___fst_exp__h744622 = + (_theResult___fst_exp__h743790 == 11'd2047) ? + _theResult___fst_exp__h743790 : + _theResult___fst_exp__h744619 ; + assign _theResult___fst_exp__h752575 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] == 11'd0) ? 11'd1 : - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] ; - assign _theResult___fst_exp__h517075 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] - + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] ; + assign _theResult___fst_exp__h752614 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] - { 5'd0, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ; - assign _theResult___fst_exp__h517081 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && - !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548 || - !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8939) ? + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 } ; + assign _theResult___fst_exp__h752620 = + (f1_exp__h714825 == 8'd0 && !f1_sfd__h714826[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13080) ? 11'd0 : - _theResult___fst_exp__h517075 ; - assign _theResult___fst_exp__h517084 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___fst_exp__h517081 : - _theResult___fst_exp__h517036 ; - assign _theResult___fst_exp__h517864 = + _theResult___fst_exp__h752614 ; + assign _theResult___fst_exp__h752623 = + (f1_exp__h714825 == 8'd0) ? + _theResult___fst_exp__h752620 : + _theResult___fst_exp__h752575 ; + assign _theResult___fst_exp__h753403 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 ; - assign _theResult___fst_exp__h517867 = - (_theResult___fst_exp__h517084 == 11'd2047) ? - _theResult___fst_exp__h517084 : - _theResult___fst_exp__h517864 ; - assign _theResult___fst_exp__h517876 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 ? - _theResult___snd_fst_exp__h499435 : - _theResult___fst_exp__h483601) : - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 ? - _theResult___snd_fst_exp__h517870 : - _theResult___fst_exp__h483601) ; - assign _theResult___fst_exp__h517879 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? + CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 ; + assign _theResult___fst_exp__h753406 = + (_theResult___fst_exp__h752623 == 11'd2047) ? + _theResult___fst_exp__h752623 : + _theResult___fst_exp__h753403 ; + assign _theResult___fst_exp__h753415 = + (f1_exp__h714825 == 8'd0) ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 ? + _theResult___snd_fst_exp__h734974 : + _theResult___fst_exp__h719140) : + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 ? + _theResult___snd_fst_exp__h753409 : + _theResult___fst_exp__h719140) ; + assign _theResult___fst_exp__h753418 = + (f1_exp__h714825 == 8'd0 && f1_sfd__h714826 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h517876 ; - assign _theResult___fst_exp__h522402 = + _theResult___fst_exp__h753415 ; + assign _theResult___fst_exp__h757993 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 ; - assign _theResult___fst_exp__h537466 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28 ; + assign _theResult___fst_exp__h773057 = 11'd897 - { 5'd0, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ; - assign _theResult___fst_exp__h537472 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && - !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036 || - !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065) ? + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 } ; + assign _theResult___fst_exp__h773063 = + (f2_exp__h753819 == 8'd0 && !f2_sfd__h753820[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14218) ? 11'd0 : - _theResult___fst_exp__h537466 ; - assign _theResult___fst_exp__h537475 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___fst_exp__h537472 : + _theResult___fst_exp__h773057 ; + assign _theResult___fst_exp__h773066 = + (f2_exp__h753819 == 8'd0) ? + _theResult___fst_exp__h773063 : 11'd897 ; - assign _theResult___fst_exp__h538230 = + assign _theResult___fst_exp__h773821 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 ; - assign _theResult___fst_exp__h538233 = - (_theResult___fst_exp__h537475 == 11'd2047) ? - _theResult___fst_exp__h537475 : - _theResult___fst_exp__h538230 ; - assign _theResult___fst_exp__h547052 = - _theResult____h538816[56] ? + CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 ; + assign _theResult___fst_exp__h773824 = + (_theResult___fst_exp__h773066 == 11'd2047) ? + _theResult___fst_exp__h773066 : + _theResult___fst_exp__h773821 ; + assign _theResult___fst_exp__h782643 = + _theResult____h774407[56] ? 11'd2 : - _theResult___fst_exp__h547126 ; - assign _theResult___fst_exp__h547117 = + _theResult___fst_exp__h782717 ; + assign _theResult___fst_exp__h782708 = 11'd0 - { 5'd0, - IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 } ; - assign _theResult___fst_exp__h547123 = - (!_theResult____h538816[56] && !_theResult____h538816[55] && - !_theResult____h538816[54] && - !_theResult____h538816[53] && - !_theResult____h538816[52] && - !_theResult____h538816[51] && - !_theResult____h538816[50] && - !_theResult____h538816[49] && - !_theResult____h538816[48] && - !_theResult____h538816[47] && - !_theResult____h538816[46] && - !_theResult____h538816[45] && - !_theResult____h538816[44] && - !_theResult____h538816[43] && - !_theResult____h538816[42] && - !_theResult____h538816[41] && - !_theResult____h538816[40] && - !_theResult____h538816[39] && - !_theResult____h538816[38] && - !_theResult____h538816[37] && - !_theResult____h538816[36] && - !_theResult____h538816[35] && - !_theResult____h538816[34] && - !_theResult____h538816[33] && - !_theResult____h538816[32] && - !_theResult____h538816[31] && - !_theResult____h538816[30] && - !_theResult____h538816[29] && - !_theResult____h538816[28] && - !_theResult____h538816[27] && - !_theResult____h538816[26] && - !_theResult____h538816[25] && - !_theResult____h538816[24] && - !_theResult____h538816[23] && - !_theResult____h538816[22] && - !_theResult____h538816[21] && - !_theResult____h538816[20] && - !_theResult____h538816[19] && - !_theResult____h538816[18] && - !_theResult____h538816[17] && - !_theResult____h538816[16] && - !_theResult____h538816[15] && - !_theResult____h538816[14] && - !_theResult____h538816[13] && - !_theResult____h538816[12] && - !_theResult____h538816[11] && - !_theResult____h538816[10] && - !_theResult____h538816[9] && - !_theResult____h538816[8] && - !_theResult____h538816[7] && - !_theResult____h538816[6] && - !_theResult____h538816[5] && - !_theResult____h538816[4] && - !_theResult____h538816[3] && - !_theResult____h538816[2] && - !_theResult____h538816[1] && - !_theResult____h538816[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362) ? + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14513 } ; + assign _theResult___fst_exp__h782714 = + (!_theResult____h774407[56] && !_theResult____h774407[55] && + !_theResult____h774407[54] && + !_theResult____h774407[53] && + !_theResult____h774407[52] && + !_theResult____h774407[51] && + !_theResult____h774407[50] && + !_theResult____h774407[49] && + !_theResult____h774407[48] && + !_theResult____h774407[47] && + !_theResult____h774407[46] && + !_theResult____h774407[45] && + !_theResult____h774407[44] && + !_theResult____h774407[43] && + !_theResult____h774407[42] && + !_theResult____h774407[41] && + !_theResult____h774407[40] && + !_theResult____h774407[39] && + !_theResult____h774407[38] && + !_theResult____h774407[37] && + !_theResult____h774407[36] && + !_theResult____h774407[35] && + !_theResult____h774407[34] && + !_theResult____h774407[33] && + !_theResult____h774407[32] && + !_theResult____h774407[31] && + !_theResult____h774407[30] && + !_theResult____h774407[29] && + !_theResult____h774407[28] && + !_theResult____h774407[27] && + !_theResult____h774407[26] && + !_theResult____h774407[25] && + !_theResult____h774407[24] && + !_theResult____h774407[23] && + !_theResult____h774407[22] && + !_theResult____h774407[21] && + !_theResult____h774407[20] && + !_theResult____h774407[19] && + !_theResult____h774407[18] && + !_theResult____h774407[17] && + !_theResult____h774407[16] && + !_theResult____h774407[15] && + !_theResult____h774407[14] && + !_theResult____h774407[13] && + !_theResult____h774407[12] && + !_theResult____h774407[11] && + !_theResult____h774407[10] && + !_theResult____h774407[9] && + !_theResult____h774407[8] && + !_theResult____h774407[7] && + !_theResult____h774407[6] && + !_theResult____h774407[5] && + !_theResult____h774407[4] && + !_theResult____h774407[3] && + !_theResult____h774407[2] && + !_theResult____h774407[1] && + !_theResult____h774407[0] || + !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14515) ? 11'd0 : - _theResult___fst_exp__h547117 ; - assign _theResult___fst_exp__h547126 = - (!_theResult____h538816[56] && _theResult____h538816[55]) ? + _theResult___fst_exp__h782708 ; + assign _theResult___fst_exp__h782717 = + (!_theResult____h774407[56] && _theResult____h774407[55]) ? 11'd1 : - _theResult___fst_exp__h547123 ; - assign _theResult___fst_exp__h547881 = + _theResult___fst_exp__h782714 ; + assign _theResult___fst_exp__h783472 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 ; - assign _theResult___fst_exp__h547884 = - (_theResult___fst_exp__h547052 == 11'd2047) ? - _theResult___fst_exp__h547052 : - _theResult___fst_exp__h547881 ; - assign _theResult___fst_exp__h555837 = - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] == + CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 ; + assign _theResult___fst_exp__h783475 = + (_theResult___fst_exp__h782643 == 11'd2047) ? + _theResult___fst_exp__h782643 : + _theResult___fst_exp__h783472 ; + assign _theResult___fst_exp__h791428 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] == 11'd0) ? 11'd1 : - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] ; - assign _theResult___fst_exp__h555876 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] - + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] ; + assign _theResult___fst_exp__h791467 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] - { 5'd0, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ; - assign _theResult___fst_exp__h555882 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && - !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036 || - !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10412) ? + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 } ; + assign _theResult___fst_exp__h791473 = + (f2_exp__h753819 == 8'd0 && !f2_sfd__h753820[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14565) ? 11'd0 : - _theResult___fst_exp__h555876 ; - assign _theResult___fst_exp__h555885 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___fst_exp__h555882 : - _theResult___fst_exp__h555837 ; - assign _theResult___fst_exp__h556665 = + _theResult___fst_exp__h791467 ; + assign _theResult___fst_exp__h791476 = + (f2_exp__h753819 == 8'd0) ? + _theResult___fst_exp__h791473 : + _theResult___fst_exp__h791428 ; + assign _theResult___fst_exp__h792256 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 ; - assign _theResult___fst_exp__h556668 = - (_theResult___fst_exp__h555885 == 11'd2047) ? - _theResult___fst_exp__h555885 : - _theResult___fst_exp__h556665 ; - assign _theResult___fst_exp__h556677 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 ? - _theResult___snd_fst_exp__h538236 : - _theResult___fst_exp__h522402) : - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 ? - _theResult___snd_fst_exp__h556671 : - _theResult___fst_exp__h522402) ; - assign _theResult___fst_exp__h556680 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? + CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q199 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 ; + assign _theResult___fst_exp__h792259 = + (_theResult___fst_exp__h791476 == 11'd2047) ? + _theResult___fst_exp__h791476 : + _theResult___fst_exp__h792256 ; + assign _theResult___fst_exp__h792268 = + (f2_exp__h753819 == 8'd0) ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 ? + _theResult___snd_fst_exp__h773827 : + _theResult___fst_exp__h757993) : + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 ? + _theResult___snd_fst_exp__h792262 : + _theResult___fst_exp__h757993) ; + assign _theResult___fst_exp__h792271 = + (f2_exp__h753819 == 8'd0 && f2_sfd__h753820 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h556677 ; - assign _theResult___fst_exp__h561603 = + _theResult___fst_exp__h792268 ; + assign _theResult___fst_exp__h797297 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 ; - assign _theResult___fst_exp__h576667 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30 ; + assign _theResult___fst_exp__h812361 = 11'd897 - { 5'd0, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 } ; - assign _theResult___fst_exp__h576673 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && - !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273 || - !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9302) ? + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 } ; + assign _theResult___fst_exp__h812367 = + (f3_exp__h793123 == 8'd0 && !f3_sfd__h793124[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13448) ? 11'd0 : - _theResult___fst_exp__h576667 ; - assign _theResult___fst_exp__h576676 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___fst_exp__h576673 : + _theResult___fst_exp__h812361 ; + assign _theResult___fst_exp__h812370 = + (f3_exp__h793123 == 8'd0) ? + _theResult___fst_exp__h812367 : 11'd897 ; - assign _theResult___fst_exp__h577431 = + assign _theResult___fst_exp__h813125 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 ; - assign _theResult___fst_exp__h577434 = - (_theResult___fst_exp__h576676 == 11'd2047) ? - _theResult___fst_exp__h576676 : - _theResult___fst_exp__h577431 ; - assign _theResult___fst_exp__h586253 = - _theResult____h578017[56] ? + CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 ; + assign _theResult___fst_exp__h813128 = + (_theResult___fst_exp__h812370 == 11'd2047) ? + _theResult___fst_exp__h812370 : + _theResult___fst_exp__h813125 ; + assign _theResult___fst_exp__h821947 = + _theResult____h813711[56] ? 11'd2 : - _theResult___fst_exp__h586327 ; - assign _theResult___fst_exp__h586318 = + _theResult___fst_exp__h822021 ; + assign _theResult___fst_exp__h822012 = 11'd0 - { 5'd0, - IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 } ; - assign _theResult___fst_exp__h586324 = - (!_theResult____h578017[56] && !_theResult____h578017[55] && - !_theResult____h578017[54] && - !_theResult____h578017[53] && - !_theResult____h578017[52] && - !_theResult____h578017[51] && - !_theResult____h578017[50] && - !_theResult____h578017[49] && - !_theResult____h578017[48] && - !_theResult____h578017[47] && - !_theResult____h578017[46] && - !_theResult____h578017[45] && - !_theResult____h578017[44] && - !_theResult____h578017[43] && - !_theResult____h578017[42] && - !_theResult____h578017[41] && - !_theResult____h578017[40] && - !_theResult____h578017[39] && - !_theResult____h578017[38] && - !_theResult____h578017[37] && - !_theResult____h578017[36] && - !_theResult____h578017[35] && - !_theResult____h578017[34] && - !_theResult____h578017[33] && - !_theResult____h578017[32] && - !_theResult____h578017[31] && - !_theResult____h578017[30] && - !_theResult____h578017[29] && - !_theResult____h578017[28] && - !_theResult____h578017[27] && - !_theResult____h578017[26] && - !_theResult____h578017[25] && - !_theResult____h578017[24] && - !_theResult____h578017[23] && - !_theResult____h578017[22] && - !_theResult____h578017[21] && - !_theResult____h578017[20] && - !_theResult____h578017[19] && - !_theResult____h578017[18] && - !_theResult____h578017[17] && - !_theResult____h578017[16] && - !_theResult____h578017[15] && - !_theResult____h578017[14] && - !_theResult____h578017[13] && - !_theResult____h578017[12] && - !_theResult____h578017[11] && - !_theResult____h578017[10] && - !_theResult____h578017[9] && - !_theResult____h578017[8] && - !_theResult____h578017[7] && - !_theResult____h578017[6] && - !_theResult____h578017[5] && - !_theResult____h578017[4] && - !_theResult____h578017[3] && - !_theResult____h578017[2] && - !_theResult____h578017[1] && - !_theResult____h578017[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9599) ? + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13743 } ; + assign _theResult___fst_exp__h822018 = + (!_theResult____h813711[56] && !_theResult____h813711[55] && + !_theResult____h813711[54] && + !_theResult____h813711[53] && + !_theResult____h813711[52] && + !_theResult____h813711[51] && + !_theResult____h813711[50] && + !_theResult____h813711[49] && + !_theResult____h813711[48] && + !_theResult____h813711[47] && + !_theResult____h813711[46] && + !_theResult____h813711[45] && + !_theResult____h813711[44] && + !_theResult____h813711[43] && + !_theResult____h813711[42] && + !_theResult____h813711[41] && + !_theResult____h813711[40] && + !_theResult____h813711[39] && + !_theResult____h813711[38] && + !_theResult____h813711[37] && + !_theResult____h813711[36] && + !_theResult____h813711[35] && + !_theResult____h813711[34] && + !_theResult____h813711[33] && + !_theResult____h813711[32] && + !_theResult____h813711[31] && + !_theResult____h813711[30] && + !_theResult____h813711[29] && + !_theResult____h813711[28] && + !_theResult____h813711[27] && + !_theResult____h813711[26] && + !_theResult____h813711[25] && + !_theResult____h813711[24] && + !_theResult____h813711[23] && + !_theResult____h813711[22] && + !_theResult____h813711[21] && + !_theResult____h813711[20] && + !_theResult____h813711[19] && + !_theResult____h813711[18] && + !_theResult____h813711[17] && + !_theResult____h813711[16] && + !_theResult____h813711[15] && + !_theResult____h813711[14] && + !_theResult____h813711[13] && + !_theResult____h813711[12] && + !_theResult____h813711[11] && + !_theResult____h813711[10] && + !_theResult____h813711[9] && + !_theResult____h813711[8] && + !_theResult____h813711[7] && + !_theResult____h813711[6] && + !_theResult____h813711[5] && + !_theResult____h813711[4] && + !_theResult____h813711[3] && + !_theResult____h813711[2] && + !_theResult____h813711[1] && + !_theResult____h813711[0] || + !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13745) ? 11'd0 : - _theResult___fst_exp__h586318 ; - assign _theResult___fst_exp__h586327 = - (!_theResult____h578017[56] && _theResult____h578017[55]) ? + _theResult___fst_exp__h822012 ; + assign _theResult___fst_exp__h822021 = + (!_theResult____h813711[56] && _theResult____h813711[55]) ? 11'd1 : - _theResult___fst_exp__h586324 ; - assign _theResult___fst_exp__h587082 = + _theResult___fst_exp__h822018 ; + assign _theResult___fst_exp__h822776 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 ; - assign _theResult___fst_exp__h587085 = - (_theResult___fst_exp__h586253 == 11'd2047) ? - _theResult___fst_exp__h586253 : - _theResult___fst_exp__h587082 ; - assign _theResult___fst_exp__h595038 = - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] == + CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q201 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 ; + assign _theResult___fst_exp__h822779 = + (_theResult___fst_exp__h821947 == 11'd2047) ? + _theResult___fst_exp__h821947 : + _theResult___fst_exp__h822776 ; + assign _theResult___fst_exp__h830732 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] == 11'd0) ? 11'd1 : - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] ; - assign _theResult___fst_exp__h595077 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] - + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] ; + assign _theResult___fst_exp__h830771 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] - { 5'd0, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 } ; - assign _theResult___fst_exp__h595083 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && - !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273 || - !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9649) ? + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 } ; + assign _theResult___fst_exp__h830777 = + (f3_exp__h793123 == 8'd0 && !f3_sfd__h793124[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13795) ? 11'd0 : - _theResult___fst_exp__h595077 ; - assign _theResult___fst_exp__h595086 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___fst_exp__h595083 : - _theResult___fst_exp__h595038 ; - assign _theResult___fst_exp__h595866 = + _theResult___fst_exp__h830771 ; + assign _theResult___fst_exp__h830780 = + (f3_exp__h793123 == 8'd0) ? + _theResult___fst_exp__h830777 : + _theResult___fst_exp__h830732 ; + assign _theResult___fst_exp__h831560 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 ; - assign _theResult___fst_exp__h595869 = - (_theResult___fst_exp__h595086 == 11'd2047) ? - _theResult___fst_exp__h595086 : - _theResult___fst_exp__h595866 ; - assign _theResult___fst_exp__h595878 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 ? - _theResult___snd_fst_exp__h577437 : - _theResult___fst_exp__h561603) : - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 ? - _theResult___snd_fst_exp__h595872 : - _theResult___fst_exp__h561603) ; - assign _theResult___fst_exp__h595881 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? + CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 ; + assign _theResult___fst_exp__h831563 = + (_theResult___fst_exp__h830780 == 11'd2047) ? + _theResult___fst_exp__h830780 : + _theResult___fst_exp__h831560 ; + assign _theResult___fst_exp__h831572 = + (f3_exp__h793123 == 8'd0) ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 ? + _theResult___snd_fst_exp__h813131 : + _theResult___fst_exp__h797297) : + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 ? + _theResult___snd_fst_exp__h831566 : + _theResult___fst_exp__h797297) ; + assign _theResult___fst_exp__h831575 = + (f3_exp__h793123 == 8'd0 && f3_sfd__h793124 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h595878 ; - assign _theResult___fst_sfd__h352009 = - (_theResult___fst_exp__h351411 == 8'd255) ? - sfdin__h351405[56:34] : - _theResult___fst_sfd__h352006 ; - assign _theResult___fst_sfd__h360591 = - (_theResult___fst_exp__h360067 == 8'd255) ? - _theResult___snd__h360018[56:34] : - _theResult___fst_sfd__h360588 ; - assign _theResult___fst_sfd__h369775 = - (_theResult___fst_exp__h369177 == 8'd255) ? - sfdin__h369171[56:34] : - _theResult___fst_sfd__h369772 ; - assign _theResult___fst_sfd__h378411 = - (_theResult___fst_exp__h377862 == 8'd255) ? - _theResult___snd__h377808[56:34] : - _theResult___fst_sfd__h378408 ; - assign _theResult___fst_sfd__h378420 = + _theResult___fst_exp__h831572 ; + assign _theResult___fst_sfd__h585090 = + (_theResult___fst_exp__h584492 == 8'd255) ? + sfdin__h584486[56:34] : + _theResult___fst_sfd__h585087 ; + assign _theResult___fst_sfd__h593672 = + (_theResult___fst_exp__h593148 == 8'd255) ? + _theResult___snd__h593099[56:34] : + _theResult___fst_sfd__h593669 ; + assign _theResult___fst_sfd__h602856 = + (_theResult___fst_exp__h602258 == 8'd255) ? + sfdin__h602252[56:34] : + _theResult___fst_sfd__h602853 ; + assign _theResult___fst_sfd__h611492 = + (_theResult___fst_exp__h610943 == 8'd255) ? + _theResult___snd__h610889[56:34] : + _theResult___fst_sfd__h611489 ; + assign _theResult___fst_sfd__h611501 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_sfd__h360594 : - _theResult___fst_sfd__h343283) : - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_sfd__h378414 : - _theResult___fst_sfd__h343283) ; - assign _theResult___fst_sfd__h378426 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 ? + _theResult___snd_fst_sfd__h593675 : + _theResult___fst_sfd__h576364) : + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 ? + _theResult___snd_fst_sfd__h611495 : + _theResult___fst_sfd__h576364) ; + assign _theResult___fst_sfd__h611507 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -25718,33 +30821,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h378420 ; - assign _theResult___fst_sfd__h397699 = - (_theResult___fst_exp__h397101 == 8'd255) ? - sfdin__h397095[56:34] : - _theResult___fst_sfd__h397696 ; - assign _theResult___fst_sfd__h406281 = - (_theResult___fst_exp__h405757 == 8'd255) ? - _theResult___snd__h405708[56:34] : - _theResult___fst_sfd__h406278 ; - assign _theResult___fst_sfd__h415465 = - (_theResult___fst_exp__h414867 == 8'd255) ? - sfdin__h414861[56:34] : - _theResult___fst_sfd__h415462 ; - assign _theResult___fst_sfd__h424101 = - (_theResult___fst_exp__h423552 == 8'd255) ? - _theResult___snd__h423498[56:34] : - _theResult___fst_sfd__h424098 ; - assign _theResult___fst_sfd__h424110 = + _theResult___fst_sfd__h611501 ; + assign _theResult___fst_sfd__h630839 = + (_theResult___fst_exp__h630241 == 8'd255) ? + sfdin__h630235[56:34] : + _theResult___fst_sfd__h630836 ; + assign _theResult___fst_sfd__h639421 = + (_theResult___fst_exp__h638897 == 8'd255) ? + _theResult___snd__h638848[56:34] : + _theResult___fst_sfd__h639418 ; + assign _theResult___fst_sfd__h648605 = + (_theResult___fst_exp__h648007 == 8'd255) ? + sfdin__h648001[56:34] : + _theResult___fst_sfd__h648602 ; + assign _theResult___fst_sfd__h657241 = + (_theResult___fst_exp__h656692 == 8'd255) ? + _theResult___snd__h656638[56:34] : + _theResult___fst_sfd__h657238 ; + assign _theResult___fst_sfd__h657250 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_sfd__h406284 : - _theResult___fst_sfd__h388975) : - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_sfd__h424104 : - _theResult___fst_sfd__h388975) ; - assign _theResult___fst_sfd__h424116 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 ? + _theResult___snd_fst_sfd__h639424 : + _theResult___fst_sfd__h622115) : + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 ? + _theResult___snd_fst_sfd__h657244 : + _theResult___fst_sfd__h622115) ; + assign _theResult___fst_sfd__h657256 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -25752,33 +30855,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h424110 ; - assign _theResult___fst_sfd__h443387 = - (_theResult___fst_exp__h442789 == 8'd255) ? - sfdin__h442783[56:34] : - _theResult___fst_sfd__h443384 ; - assign _theResult___fst_sfd__h451969 = - (_theResult___fst_exp__h451445 == 8'd255) ? - _theResult___snd__h451396[56:34] : - _theResult___fst_sfd__h451966 ; - assign _theResult___fst_sfd__h461153 = - (_theResult___fst_exp__h460555 == 8'd255) ? - sfdin__h460549[56:34] : - _theResult___fst_sfd__h461150 ; - assign _theResult___fst_sfd__h469789 = - (_theResult___fst_exp__h469240 == 8'd255) ? - _theResult___snd__h469186[56:34] : - _theResult___fst_sfd__h469786 ; - assign _theResult___fst_sfd__h469798 = + _theResult___fst_sfd__h657250 ; + assign _theResult___fst_sfd__h676586 = + (_theResult___fst_exp__h675988 == 8'd255) ? + sfdin__h675982[56:34] : + _theResult___fst_sfd__h676583 ; + assign _theResult___fst_sfd__h685168 = + (_theResult___fst_exp__h684644 == 8'd255) ? + _theResult___snd__h684595[56:34] : + _theResult___fst_sfd__h685165 ; + assign _theResult___fst_sfd__h694352 = + (_theResult___fst_exp__h693754 == 8'd255) ? + sfdin__h693748[56:34] : + _theResult___fst_sfd__h694349 ; + assign _theResult___fst_sfd__h702988 = + (_theResult___fst_exp__h702439 == 8'd255) ? + _theResult___snd__h702385[56:34] : + _theResult___fst_sfd__h702985 ; + assign _theResult___fst_sfd__h702997 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_sfd__h451972 : - _theResult___fst_sfd__h434663) : - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_sfd__h469792 : - _theResult___fst_sfd__h434663) ; - assign _theResult___fst_sfd__h469804 = + (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 ? + _theResult___snd_fst_sfd__h685171 : + _theResult___fst_sfd__h667862) : + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 ? + _theResult___snd_fst_sfd__h702991 : + _theResult___fst_sfd__h667862) ; + assign _theResult___fst_sfd__h703003 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -25786,2888 +30889,5479 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h469798 ; - assign _theResult___fst_sfd__h483602 = + _theResult___fst_sfd__h702997 ; + assign _theResult___fst_sfd__h719141 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 ; - assign _theResult___fst_sfd__h499430 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27 ; + assign _theResult___fst_sfd__h734969 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 ; - assign _theResult___fst_sfd__h499433 = - (_theResult___fst_exp__h498674 == 11'd2047) ? - _theResult___snd__h498625[56:5] : - _theResult___fst_sfd__h499430 ; - assign _theResult___fst_sfd__h509081 = + CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 ; + assign _theResult___fst_sfd__h734972 = + (_theResult___fst_exp__h734213 == 11'd2047) ? + _theResult___snd__h734164[56:5] : + _theResult___fst_sfd__h734969 ; + assign _theResult___fst_sfd__h744620 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 ; - assign _theResult___fst_sfd__h509084 = - (_theResult___fst_exp__h508251 == 11'd2047) ? - sfdin__h508245[56:5] : - _theResult___fst_sfd__h509081 ; - assign _theResult___fst_sfd__h517865 = + CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q231 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 ; + assign _theResult___fst_sfd__h744623 = + (_theResult___fst_exp__h743790 == 11'd2047) ? + sfdin__h743784[56:5] : + _theResult___fst_sfd__h744620 ; + assign _theResult___fst_sfd__h753404 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 ; - assign _theResult___fst_sfd__h517868 = - (_theResult___fst_exp__h517084 == 11'd2047) ? - _theResult___snd__h517030[56:5] : - _theResult___fst_sfd__h517865 ; - assign _theResult___fst_sfd__h517877 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 ? - _theResult___snd_fst_sfd__h499436 : - _theResult___fst_sfd__h483602) : - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 ? - _theResult___snd_fst_sfd__h517871 : - _theResult___fst_sfd__h483602) ; - assign _theResult___fst_sfd__h517883 = - ((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) && - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? + CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q229 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 ; + assign _theResult___fst_sfd__h753407 = + (_theResult___fst_exp__h752623 == 11'd2047) ? + _theResult___snd__h752569[56:5] : + _theResult___fst_sfd__h753404 ; + assign _theResult___fst_sfd__h753416 = + (f1_exp__h714825 == 8'd0) ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 ? + _theResult___snd_fst_sfd__h734975 : + _theResult___fst_sfd__h719141) : + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 ? + _theResult___snd_fst_sfd__h753410 : + _theResult___fst_sfd__h719141) ; + assign _theResult___fst_sfd__h753422 = + ((f1_exp__h714825 == 8'd255 || f1_exp__h714825 == 8'd0) && + f1_sfd__h714826 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h517877 ; - assign _theResult___fst_sfd__h522403 = + _theResult___fst_sfd__h753416 ; + assign _theResult___fst_sfd__h757994 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 ; - assign _theResult___fst_sfd__h538231 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29 ; + assign _theResult___fst_sfd__h773822 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 ; - assign _theResult___fst_sfd__h538234 = - (_theResult___fst_exp__h537475 == 11'd2047) ? - _theResult___snd__h537426[56:5] : - _theResult___fst_sfd__h538231 ; - assign _theResult___fst_sfd__h547882 = + CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 ; + assign _theResult___fst_sfd__h773825 = + (_theResult___fst_exp__h773066 == 11'd2047) ? + _theResult___snd__h773017[56:5] : + _theResult___fst_sfd__h773822 ; + assign _theResult___fst_sfd__h783473 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 ; - assign _theResult___fst_sfd__h547885 = - (_theResult___fst_exp__h547052 == 11'd2047) ? - sfdin__h547046[56:5] : - _theResult___fst_sfd__h547882 ; - assign _theResult___fst_sfd__h556666 = + CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 ; + assign _theResult___fst_sfd__h783476 = + (_theResult___fst_exp__h782643 == 11'd2047) ? + sfdin__h782637[56:5] : + _theResult___fst_sfd__h783473 ; + assign _theResult___fst_sfd__h792257 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 ; - assign _theResult___fst_sfd__h556669 = - (_theResult___fst_exp__h555885 == 11'd2047) ? - _theResult___snd__h555831[56:5] : - _theResult___fst_sfd__h556666 ; - assign _theResult___fst_sfd__h556678 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 ? - _theResult___snd_fst_sfd__h538237 : - _theResult___fst_sfd__h522403) : - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 ? - _theResult___snd_fst_sfd__h556672 : - _theResult___fst_sfd__h522403) ; - assign _theResult___fst_sfd__h556684 = - ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) && - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? + CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 ; + assign _theResult___fst_sfd__h792260 = + (_theResult___fst_exp__h791476 == 11'd2047) ? + _theResult___snd__h791422[56:5] : + _theResult___fst_sfd__h792257 ; + assign _theResult___fst_sfd__h792269 = + (f2_exp__h753819 == 8'd0) ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 ? + _theResult___snd_fst_sfd__h773828 : + _theResult___fst_sfd__h757994) : + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 ? + _theResult___snd_fst_sfd__h792263 : + _theResult___fst_sfd__h757994) ; + assign _theResult___fst_sfd__h792275 = + ((f2_exp__h753819 == 8'd255 || f2_exp__h753819 == 8'd0) && + f2_sfd__h753820 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h556678 ; - assign _theResult___fst_sfd__h561604 = + _theResult___fst_sfd__h792269 ; + assign _theResult___fst_sfd__h797298 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 ; - assign _theResult___fst_sfd__h577432 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31 ; + assign _theResult___fst_sfd__h813126 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 ; - assign _theResult___fst_sfd__h577435 = - (_theResult___fst_exp__h576676 == 11'd2047) ? - _theResult___snd__h576627[56:5] : - _theResult___fst_sfd__h577432 ; - assign _theResult___fst_sfd__h587083 = + CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 ; + assign _theResult___fst_sfd__h813129 = + (_theResult___fst_exp__h812370 == 11'd2047) ? + _theResult___snd__h812321[56:5] : + _theResult___fst_sfd__h813126 ; + assign _theResult___fst_sfd__h822777 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 ; - assign _theResult___fst_sfd__h587086 = - (_theResult___fst_exp__h586253 == 11'd2047) ? - sfdin__h586247[56:5] : - _theResult___fst_sfd__h587083 ; - assign _theResult___fst_sfd__h595867 = + CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 ; + assign _theResult___fst_sfd__h822780 = + (_theResult___fst_exp__h821947 == 11'd2047) ? + sfdin__h821941[56:5] : + _theResult___fst_sfd__h822777 ; + assign _theResult___fst_sfd__h831561 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 ; - assign _theResult___fst_sfd__h595870 = - (_theResult___fst_exp__h595086 == 11'd2047) ? - _theResult___snd__h595032[56:5] : - _theResult___fst_sfd__h595867 ; - assign _theResult___fst_sfd__h595879 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 ? - _theResult___snd_fst_sfd__h577438 : - _theResult___fst_sfd__h561604) : - (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 ? - _theResult___snd_fst_sfd__h595873 : - _theResult___fst_sfd__h561604) ; - assign _theResult___fst_sfd__h595885 = - ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) && - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? + CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 ; + assign _theResult___fst_sfd__h831564 = + (_theResult___fst_exp__h830780 == 11'd2047) ? + _theResult___snd__h830726[56:5] : + _theResult___fst_sfd__h831561 ; + assign _theResult___fst_sfd__h831573 = + (f3_exp__h793123 == 8'd0) ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 ? + _theResult___snd_fst_sfd__h813132 : + _theResult___fst_sfd__h797298) : + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 ? + _theResult___snd_fst_sfd__h831567 : + _theResult___fst_sfd__h797298) ; + assign _theResult___fst_sfd__h831579 = + ((f3_exp__h793123 == 8'd255 || f3_exp__h793123 == 8'd0) && + f3_sfd__h793124 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h595879 ; - assign _theResult___sfd__h351928 = - sfd__h351503[24] ? - ((_theResult___fst_exp__h351411 == 8'd254) ? + _theResult___fst_sfd__h831573 ; + assign _theResult___sfd__h585009 = + sfd__h584584[24] ? + ((_theResult___fst_exp__h584492 == 8'd254) ? 23'd0 : - sfd__h351503[23:1]) : - sfd__h351503[22:0] ; - assign _theResult___sfd__h360510 = - sfd__h360085[24] ? - ((_theResult___fst_exp__h360067 == 8'd254) ? + sfd__h584584[23:1]) : + sfd__h584584[22:0] ; + assign _theResult___sfd__h593591 = + sfd__h593166[24] ? + ((_theResult___fst_exp__h593148 == 8'd254) ? 23'd0 : - sfd__h360085[23:1]) : - sfd__h360085[22:0] ; - assign _theResult___sfd__h369694 = - sfd__h369269[24] ? - ((_theResult___fst_exp__h369177 == 8'd254) ? + sfd__h593166[23:1]) : + sfd__h593166[22:0] ; + assign _theResult___sfd__h602775 = + sfd__h602350[24] ? + ((_theResult___fst_exp__h602258 == 8'd254) ? 23'd0 : - sfd__h369269[23:1]) : - sfd__h369269[22:0] ; - assign _theResult___sfd__h378330 = - sfd__h377881[24] ? - ((_theResult___fst_exp__h377862 == 8'd254) ? + sfd__h602350[23:1]) : + sfd__h602350[22:0] ; + assign _theResult___sfd__h611411 = + sfd__h610962[24] ? + ((_theResult___fst_exp__h610943 == 8'd254) ? 23'd0 : - sfd__h377881[23:1]) : - sfd__h377881[22:0] ; - assign _theResult___sfd__h378432 = + sfd__h610962[23:1]) : + sfd__h610962[22:0] ; + assign _theResult___sfd__h611513 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h335645 : - _theResult___fst_sfd__h378426 ; - assign _theResult___sfd__h397618 = - sfd__h397193[24] ? - ((_theResult___fst_exp__h397101 == 8'd254) ? + _theResult___snd_fst_sfd__h568726 : + _theResult___fst_sfd__h611507 ; + assign _theResult___sfd__h630758 = + sfd__h630333[24] ? + ((_theResult___fst_exp__h630241 == 8'd254) ? 23'd0 : - sfd__h397193[23:1]) : - sfd__h397193[22:0] ; - assign _theResult___sfd__h406200 = - sfd__h405775[24] ? - ((_theResult___fst_exp__h405757 == 8'd254) ? + sfd__h630333[23:1]) : + sfd__h630333[22:0] ; + assign _theResult___sfd__h639340 = + sfd__h638915[24] ? + ((_theResult___fst_exp__h638897 == 8'd254) ? 23'd0 : - sfd__h405775[23:1]) : - sfd__h405775[22:0] ; - assign _theResult___sfd__h415384 = - sfd__h414959[24] ? - ((_theResult___fst_exp__h414867 == 8'd254) ? + sfd__h638915[23:1]) : + sfd__h638915[22:0] ; + assign _theResult___sfd__h648524 = + sfd__h648099[24] ? + ((_theResult___fst_exp__h648007 == 8'd254) ? 23'd0 : - sfd__h414959[23:1]) : - sfd__h414959[22:0] ; - assign _theResult___sfd__h424020 = - sfd__h423571[24] ? - ((_theResult___fst_exp__h423552 == 8'd254) ? + sfd__h648099[23:1]) : + sfd__h648099[22:0] ; + assign _theResult___sfd__h657160 = + sfd__h656711[24] ? + ((_theResult___fst_exp__h656692 == 8'd254) ? 23'd0 : - sfd__h423571[23:1]) : - sfd__h423571[22:0] ; - assign _theResult___sfd__h424122 = + sfd__h656711[23:1]) : + sfd__h656711[22:0] ; + assign _theResult___sfd__h657262 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h381340 : - _theResult___fst_sfd__h424116 ; - assign _theResult___sfd__h443306 = - sfd__h442881[24] ? - ((_theResult___fst_exp__h442789 == 8'd254) ? + _theResult___snd_fst_sfd__h614480 : + _theResult___fst_sfd__h657256 ; + assign _theResult___sfd__h676505 = + sfd__h676080[24] ? + ((_theResult___fst_exp__h675988 == 8'd254) ? 23'd0 : - sfd__h442881[23:1]) : - sfd__h442881[22:0] ; - assign _theResult___sfd__h451888 = - sfd__h451463[24] ? - ((_theResult___fst_exp__h451445 == 8'd254) ? + sfd__h676080[23:1]) : + sfd__h676080[22:0] ; + assign _theResult___sfd__h685087 = + sfd__h684662[24] ? + ((_theResult___fst_exp__h684644 == 8'd254) ? 23'd0 : - sfd__h451463[23:1]) : - sfd__h451463[22:0] ; - assign _theResult___sfd__h461072 = - sfd__h460647[24] ? - ((_theResult___fst_exp__h460555 == 8'd254) ? + sfd__h684662[23:1]) : + sfd__h684662[22:0] ; + assign _theResult___sfd__h694271 = + sfd__h693846[24] ? + ((_theResult___fst_exp__h693754 == 8'd254) ? 23'd0 : - sfd__h460647[23:1]) : - sfd__h460647[22:0] ; - assign _theResult___sfd__h469708 = - sfd__h469259[24] ? - ((_theResult___fst_exp__h469240 == 8'd254) ? + sfd__h693846[23:1]) : + sfd__h693846[22:0] ; + assign _theResult___sfd__h702907 = + sfd__h702458[24] ? + ((_theResult___fst_exp__h702439 == 8'd254) ? 23'd0 : - sfd__h469259[23:1]) : - sfd__h469259[22:0] ; - assign _theResult___sfd__h469810 = + sfd__h702458[23:1]) : + sfd__h702458[22:0] ; + assign _theResult___sfd__h703009 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h427028 : - _theResult___fst_sfd__h469804 ; - assign _theResult___sfd__h499330 = - sfd__h498692[53] ? - ((_theResult___fst_exp__h498674 == 11'd2046) ? + _theResult___snd_fst_sfd__h660227 : + _theResult___fst_sfd__h703003 ; + assign _theResult___sfd__h734869 = + sfd__h734231[53] ? + ((_theResult___fst_exp__h734213 == 11'd2046) ? 52'd0 : - sfd__h498692[52:1]) : - sfd__h498692[51:0] ; - assign _theResult___sfd__h508981 = - sfd__h508343[53] ? - ((_theResult___fst_exp__h508251 == 11'd2046) ? + sfd__h734231[52:1]) : + sfd__h734231[51:0] ; + assign _theResult___sfd__h744520 = + sfd__h743882[53] ? + ((_theResult___fst_exp__h743790 == 11'd2046) ? 52'd0 : - sfd__h508343[52:1]) : - sfd__h508343[51:0] ; - assign _theResult___sfd__h517765 = - sfd__h517103[53] ? - ((_theResult___fst_exp__h517084 == 11'd2046) ? + sfd__h743882[52:1]) : + sfd__h743882[51:0] ; + assign _theResult___sfd__h753304 = + sfd__h752642[53] ? + ((_theResult___fst_exp__h752623 == 11'd2046) ? 52'd0 : - sfd__h517103[52:1]) : - sfd__h517103[51:0] ; - assign _theResult___sfd__h538131 = - sfd__h537493[53] ? - ((_theResult___fst_exp__h537475 == 11'd2046) ? + sfd__h752642[52:1]) : + sfd__h752642[51:0] ; + assign _theResult___sfd__h773722 = + sfd__h773084[53] ? + ((_theResult___fst_exp__h773066 == 11'd2046) ? 52'd0 : - sfd__h537493[52:1]) : - sfd__h537493[51:0] ; - assign _theResult___sfd__h547782 = - sfd__h547144[53] ? - ((_theResult___fst_exp__h547052 == 11'd2046) ? + sfd__h773084[52:1]) : + sfd__h773084[51:0] ; + assign _theResult___sfd__h783373 = + sfd__h782735[53] ? + ((_theResult___fst_exp__h782643 == 11'd2046) ? 52'd0 : - sfd__h547144[52:1]) : - sfd__h547144[51:0] ; - assign _theResult___sfd__h556566 = - sfd__h555904[53] ? - ((_theResult___fst_exp__h555885 == 11'd2046) ? + sfd__h782735[52:1]) : + sfd__h782735[51:0] ; + assign _theResult___sfd__h792157 = + sfd__h791495[53] ? + ((_theResult___fst_exp__h791476 == 11'd2046) ? 52'd0 : - sfd__h555904[52:1]) : - sfd__h555904[51:0] ; - assign _theResult___sfd__h577332 = - sfd__h576694[53] ? - ((_theResult___fst_exp__h576676 == 11'd2046) ? + sfd__h791495[52:1]) : + sfd__h791495[51:0] ; + assign _theResult___sfd__h813026 = + sfd__h812388[53] ? + ((_theResult___fst_exp__h812370 == 11'd2046) ? 52'd0 : - sfd__h576694[52:1]) : - sfd__h576694[51:0] ; - assign _theResult___sfd__h586983 = - sfd__h586345[53] ? - ((_theResult___fst_exp__h586253 == 11'd2046) ? + sfd__h812388[52:1]) : + sfd__h812388[51:0] ; + assign _theResult___sfd__h822677 = + sfd__h822039[53] ? + ((_theResult___fst_exp__h821947 == 11'd2046) ? 52'd0 : - sfd__h586345[52:1]) : - sfd__h586345[51:0] ; - assign _theResult___sfd__h595767 = - sfd__h595105[53] ? - ((_theResult___fst_exp__h595086 == 11'd2046) ? + sfd__h822039[52:1]) : + sfd__h822039[51:0] ; + assign _theResult___sfd__h831461 = + sfd__h830799[53] ? + ((_theResult___fst_exp__h830780 == 11'd2046) ? 52'd0 : - sfd__h595105[52:1]) : - sfd__h595105[51:0] ; - assign _theResult___snd__h351422 = { _theResult____h343300[55:0], 1'd0 } ; - assign _theResult___snd__h351433 = - (!_theResult____h343300[56] && _theResult____h343300[55]) ? - _theResult___snd__h351435 : - _theResult___snd__h351445 ; - assign _theResult___snd__h351435 = { _theResult____h343300[54:0], 2'd0 } ; - assign _theResult___snd__h351445 = - (!_theResult____h343300[56] && !_theResult____h343300[55] && - !_theResult____h343300[54] && - !_theResult____h343300[53] && - !_theResult____h343300[52] && - !_theResult____h343300[51] && - !_theResult____h343300[50] && - !_theResult____h343300[49] && - !_theResult____h343300[48] && - !_theResult____h343300[47] && - !_theResult____h343300[46] && - !_theResult____h343300[45] && - !_theResult____h343300[44] && - !_theResult____h343300[43] && - !_theResult____h343300[42] && - !_theResult____h343300[41] && - !_theResult____h343300[40] && - !_theResult____h343300[39] && - !_theResult____h343300[38] && - !_theResult____h343300[37] && - !_theResult____h343300[36] && - !_theResult____h343300[35] && - !_theResult____h343300[34] && - !_theResult____h343300[33] && - !_theResult____h343300[32] && - !_theResult____h343300[31] && - !_theResult____h343300[30] && - !_theResult____h343300[29] && - !_theResult____h343300[28] && - !_theResult____h343300[27] && - !_theResult____h343300[26] && - !_theResult____h343300[25] && - !_theResult____h343300[24] && - !_theResult____h343300[23] && - !_theResult____h343300[22] && - !_theResult____h343300[21] && - !_theResult____h343300[20] && - !_theResult____h343300[19] && - !_theResult____h343300[18] && - !_theResult____h343300[17] && - !_theResult____h343300[16] && - !_theResult____h343300[15] && - !_theResult____h343300[14] && - !_theResult____h343300[13] && - !_theResult____h343300[12] && - !_theResult____h343300[11] && - !_theResult____h343300[10] && - !_theResult____h343300[9] && - !_theResult____h343300[8] && - !_theResult____h343300[7] && - !_theResult____h343300[6] && - !_theResult____h343300[5] && - !_theResult____h343300[4] && - !_theResult____h343300[3] && - !_theResult____h343300[2] && - !_theResult____h343300[1] && - !_theResult____h343300[0]) ? - _theResult____h343300 : - _theResult___snd__h351451 ; - assign _theResult___snd__h351451 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20[54:0], + sfd__h830799[52:1]) : + sfd__h830799[51:0] ; + assign _theResult___snd__h584503 = { _theResult____h576381[55:0], 1'd0 } ; + assign _theResult___snd__h584514 = + (!_theResult____h576381[56] && _theResult____h576381[55]) ? + _theResult___snd__h584516 : + _theResult___snd__h584526 ; + assign _theResult___snd__h584516 = { _theResult____h576381[54:0], 2'd0 } ; + assign _theResult___snd__h584526 = + (!_theResult____h576381[56] && !_theResult____h576381[55] && + !_theResult____h576381[54] && + !_theResult____h576381[53] && + !_theResult____h576381[52] && + !_theResult____h576381[51] && + !_theResult____h576381[50] && + !_theResult____h576381[49] && + !_theResult____h576381[48] && + !_theResult____h576381[47] && + !_theResult____h576381[46] && + !_theResult____h576381[45] && + !_theResult____h576381[44] && + !_theResult____h576381[43] && + !_theResult____h576381[42] && + !_theResult____h576381[41] && + !_theResult____h576381[40] && + !_theResult____h576381[39] && + !_theResult____h576381[38] && + !_theResult____h576381[37] && + !_theResult____h576381[36] && + !_theResult____h576381[35] && + !_theResult____h576381[34] && + !_theResult____h576381[33] && + !_theResult____h576381[32] && + !_theResult____h576381[31] && + !_theResult____h576381[30] && + !_theResult____h576381[29] && + !_theResult____h576381[28] && + !_theResult____h576381[27] && + !_theResult____h576381[26] && + !_theResult____h576381[25] && + !_theResult____h576381[24] && + !_theResult____h576381[23] && + !_theResult____h576381[22] && + !_theResult____h576381[21] && + !_theResult____h576381[20] && + !_theResult____h576381[19] && + !_theResult____h576381[18] && + !_theResult____h576381[17] && + !_theResult____h576381[16] && + !_theResult____h576381[15] && + !_theResult____h576381[14] && + !_theResult____h576381[13] && + !_theResult____h576381[12] && + !_theResult____h576381[11] && + !_theResult____h576381[10] && + !_theResult____h576381[9] && + !_theResult____h576381[8] && + !_theResult____h576381[7] && + !_theResult____h576381[6] && + !_theResult____h576381[5] && + !_theResult____h576381[4] && + !_theResult____h576381[3] && + !_theResult____h576381[2] && + !_theResult____h576381[1] && + !_theResult____h576381[0]) ? + _theResult____h576381 : + _theResult___snd__h584532 ; + assign _theResult___snd__h584532 = + { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q39[54:0], 2'd0 } ; - assign _theResult___snd__h351474 = - _theResult____h343300 << - IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 ; - assign _theResult___snd__h360018 = + assign _theResult___snd__h584555 = + _theResult____h576381 << + IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352 ; + assign _theResult___snd__h593099 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h360027 : - _theResult___snd__h360020 ; - assign _theResult___snd__h360020 = + _theResult___snd__h593108 : + _theResult___snd__h593101 ; + assign _theResult___snd__h593101 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h360027 = + assign _theResult___snd__h593108 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && - NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h335695 : - _theResult___snd__h360033 ; - assign _theResult___snd__h360033 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22[54:0], + NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8528) ? + sfd__h568776 : + _theResult___snd__h593114 ; + assign _theResult___snd__h593114 = + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q41[54:0], 2'd0 } ; - assign _theResult___snd__h360056 = - sfd__h335695 << - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 ; - assign _theResult___snd__h369188 = { _theResult____h360939[55:0], 1'd0 } ; - assign _theResult___snd__h369199 = - (!_theResult____h360939[56] && _theResult____h360939[55]) ? - _theResult___snd__h369201 : - _theResult___snd__h369211 ; - assign _theResult___snd__h369201 = { _theResult____h360939[54:0], 2'd0 } ; - assign _theResult___snd__h369211 = - (!_theResult____h360939[56] && !_theResult____h360939[55] && - !_theResult____h360939[54] && - !_theResult____h360939[53] && - !_theResult____h360939[52] && - !_theResult____h360939[51] && - !_theResult____h360939[50] && - !_theResult____h360939[49] && - !_theResult____h360939[48] && - !_theResult____h360939[47] && - !_theResult____h360939[46] && - !_theResult____h360939[45] && - !_theResult____h360939[44] && - !_theResult____h360939[43] && - !_theResult____h360939[42] && - !_theResult____h360939[41] && - !_theResult____h360939[40] && - !_theResult____h360939[39] && - !_theResult____h360939[38] && - !_theResult____h360939[37] && - !_theResult____h360939[36] && - !_theResult____h360939[35] && - !_theResult____h360939[34] && - !_theResult____h360939[33] && - !_theResult____h360939[32] && - !_theResult____h360939[31] && - !_theResult____h360939[30] && - !_theResult____h360939[29] && - !_theResult____h360939[28] && - !_theResult____h360939[27] && - !_theResult____h360939[26] && - !_theResult____h360939[25] && - !_theResult____h360939[24] && - !_theResult____h360939[23] && - !_theResult____h360939[22] && - !_theResult____h360939[21] && - !_theResult____h360939[20] && - !_theResult____h360939[19] && - !_theResult____h360939[18] && - !_theResult____h360939[17] && - !_theResult____h360939[16] && - !_theResult____h360939[15] && - !_theResult____h360939[14] && - !_theResult____h360939[13] && - !_theResult____h360939[12] && - !_theResult____h360939[11] && - !_theResult____h360939[10] && - !_theResult____h360939[9] && - !_theResult____h360939[8] && - !_theResult____h360939[7] && - !_theResult____h360939[6] && - !_theResult____h360939[5] && - !_theResult____h360939[4] && - !_theResult____h360939[3] && - !_theResult____h360939[2] && - !_theResult____h360939[1] && - !_theResult____h360939[0]) ? - _theResult____h360939 : - _theResult___snd__h369217 ; - assign _theResult___snd__h369217 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30[54:0], + assign _theResult___snd__h593137 = + sfd__h568776 << + IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 ; + assign _theResult___snd__h602269 = { _theResult____h594020[55:0], 1'd0 } ; + assign _theResult___snd__h602280 = + (!_theResult____h594020[56] && _theResult____h594020[55]) ? + _theResult___snd__h602282 : + _theResult___snd__h602292 ; + assign _theResult___snd__h602282 = { _theResult____h594020[54:0], 2'd0 } ; + assign _theResult___snd__h602292 = + (!_theResult____h594020[56] && !_theResult____h594020[55] && + !_theResult____h594020[54] && + !_theResult____h594020[53] && + !_theResult____h594020[52] && + !_theResult____h594020[51] && + !_theResult____h594020[50] && + !_theResult____h594020[49] && + !_theResult____h594020[48] && + !_theResult____h594020[47] && + !_theResult____h594020[46] && + !_theResult____h594020[45] && + !_theResult____h594020[44] && + !_theResult____h594020[43] && + !_theResult____h594020[42] && + !_theResult____h594020[41] && + !_theResult____h594020[40] && + !_theResult____h594020[39] && + !_theResult____h594020[38] && + !_theResult____h594020[37] && + !_theResult____h594020[36] && + !_theResult____h594020[35] && + !_theResult____h594020[34] && + !_theResult____h594020[33] && + !_theResult____h594020[32] && + !_theResult____h594020[31] && + !_theResult____h594020[30] && + !_theResult____h594020[29] && + !_theResult____h594020[28] && + !_theResult____h594020[27] && + !_theResult____h594020[26] && + !_theResult____h594020[25] && + !_theResult____h594020[24] && + !_theResult____h594020[23] && + !_theResult____h594020[22] && + !_theResult____h594020[21] && + !_theResult____h594020[20] && + !_theResult____h594020[19] && + !_theResult____h594020[18] && + !_theResult____h594020[17] && + !_theResult____h594020[16] && + !_theResult____h594020[15] && + !_theResult____h594020[14] && + !_theResult____h594020[13] && + !_theResult____h594020[12] && + !_theResult____h594020[11] && + !_theResult____h594020[10] && + !_theResult____h594020[9] && + !_theResult____h594020[8] && + !_theResult____h594020[7] && + !_theResult____h594020[6] && + !_theResult____h594020[5] && + !_theResult____h594020[4] && + !_theResult____h594020[3] && + !_theResult____h594020[2] && + !_theResult____h594020[1] && + !_theResult____h594020[0]) ? + _theResult____h594020 : + _theResult___snd__h602298 ; + assign _theResult___snd__h602298 = + { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q49[54:0], 2'd0 } ; - assign _theResult___snd__h369240 = - _theResult____h360939 << - IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 ; - assign _theResult___snd__h377808 = + assign _theResult___snd__h602321 = + _theResult____h594020 << + IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8903 ; + assign _theResult___snd__h610889 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h377822 : - _theResult___snd__h360020 ; - assign _theResult___snd__h377822 = + _theResult___snd__h610903 : + _theResult___snd__h593101 ; + assign _theResult___snd__h610903 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && - NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h335695 : - _theResult___snd__h377828 ; - assign _theResult___snd__h377828 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35[54:0], + NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8528) ? + sfd__h568776 : + _theResult___snd__h610909 ; + assign _theResult___snd__h610909 = + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q54[54:0], 2'd0 } ; - assign _theResult___snd__h377846 = - sfd__h335695 << - (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868[8] ? + assign _theResult___snd__h610927 = + sfd__h568776 << + (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8977[8] ? 9'h0AA : - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868) ; - assign _theResult___snd__h397112 = { _theResult____h388992[55:0], 1'd0 } ; - assign _theResult___snd__h397123 = - (!_theResult____h388992[56] && _theResult____h388992[55]) ? - _theResult___snd__h397125 : - _theResult___snd__h397135 ; - assign _theResult___snd__h397125 = { _theResult____h388992[54:0], 2'd0 } ; - assign _theResult___snd__h397135 = - (!_theResult____h388992[56] && !_theResult____h388992[55] && - !_theResult____h388992[54] && - !_theResult____h388992[53] && - !_theResult____h388992[52] && - !_theResult____h388992[51] && - !_theResult____h388992[50] && - !_theResult____h388992[49] && - !_theResult____h388992[48] && - !_theResult____h388992[47] && - !_theResult____h388992[46] && - !_theResult____h388992[45] && - !_theResult____h388992[44] && - !_theResult____h388992[43] && - !_theResult____h388992[42] && - !_theResult____h388992[41] && - !_theResult____h388992[40] && - !_theResult____h388992[39] && - !_theResult____h388992[38] && - !_theResult____h388992[37] && - !_theResult____h388992[36] && - !_theResult____h388992[35] && - !_theResult____h388992[34] && - !_theResult____h388992[33] && - !_theResult____h388992[32] && - !_theResult____h388992[31] && - !_theResult____h388992[30] && - !_theResult____h388992[29] && - !_theResult____h388992[28] && - !_theResult____h388992[27] && - !_theResult____h388992[26] && - !_theResult____h388992[25] && - !_theResult____h388992[24] && - !_theResult____h388992[23] && - !_theResult____h388992[22] && - !_theResult____h388992[21] && - !_theResult____h388992[20] && - !_theResult____h388992[19] && - !_theResult____h388992[18] && - !_theResult____h388992[17] && - !_theResult____h388992[16] && - !_theResult____h388992[15] && - !_theResult____h388992[14] && - !_theResult____h388992[13] && - !_theResult____h388992[12] && - !_theResult____h388992[11] && - !_theResult____h388992[10] && - !_theResult____h388992[9] && - !_theResult____h388992[8] && - !_theResult____h388992[7] && - !_theResult____h388992[6] && - !_theResult____h388992[5] && - !_theResult____h388992[4] && - !_theResult____h388992[3] && - !_theResult____h388992[2] && - !_theResult____h388992[1] && - !_theResult____h388992[0]) ? - _theResult____h388992 : - _theResult___snd__h397141 ; - assign _theResult___snd__h397141 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55[54:0], + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8977) ; + assign _theResult___snd__h630252 = { _theResult____h622132[55:0], 1'd0 } ; + assign _theResult___snd__h630263 = + (!_theResult____h622132[56] && _theResult____h622132[55]) ? + _theResult___snd__h630265 : + _theResult___snd__h630275 ; + assign _theResult___snd__h630265 = { _theResult____h622132[54:0], 2'd0 } ; + assign _theResult___snd__h630275 = + (!_theResult____h622132[56] && !_theResult____h622132[55] && + !_theResult____h622132[54] && + !_theResult____h622132[53] && + !_theResult____h622132[52] && + !_theResult____h622132[51] && + !_theResult____h622132[50] && + !_theResult____h622132[49] && + !_theResult____h622132[48] && + !_theResult____h622132[47] && + !_theResult____h622132[46] && + !_theResult____h622132[45] && + !_theResult____h622132[44] && + !_theResult____h622132[43] && + !_theResult____h622132[42] && + !_theResult____h622132[41] && + !_theResult____h622132[40] && + !_theResult____h622132[39] && + !_theResult____h622132[38] && + !_theResult____h622132[37] && + !_theResult____h622132[36] && + !_theResult____h622132[35] && + !_theResult____h622132[34] && + !_theResult____h622132[33] && + !_theResult____h622132[32] && + !_theResult____h622132[31] && + !_theResult____h622132[30] && + !_theResult____h622132[29] && + !_theResult____h622132[28] && + !_theResult____h622132[27] && + !_theResult____h622132[26] && + !_theResult____h622132[25] && + !_theResult____h622132[24] && + !_theResult____h622132[23] && + !_theResult____h622132[22] && + !_theResult____h622132[21] && + !_theResult____h622132[20] && + !_theResult____h622132[19] && + !_theResult____h622132[18] && + !_theResult____h622132[17] && + !_theResult____h622132[16] && + !_theResult____h622132[15] && + !_theResult____h622132[14] && + !_theResult____h622132[13] && + !_theResult____h622132[12] && + !_theResult____h622132[11] && + !_theResult____h622132[10] && + !_theResult____h622132[9] && + !_theResult____h622132[8] && + !_theResult____h622132[7] && + !_theResult____h622132[6] && + !_theResult____h622132[5] && + !_theResult____h622132[4] && + !_theResult____h622132[3] && + !_theResult____h622132[2] && + !_theResult____h622132[1] && + !_theResult____h622132[0]) ? + _theResult____h622132 : + _theResult___snd__h630281 ; + assign _theResult___snd__h630281 = + { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q74[54:0], 2'd0 } ; - assign _theResult___snd__h397164 = - _theResult____h388992 << - IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 ; - assign _theResult___snd__h405708 = + assign _theResult___snd__h630304 = + _theResult____h622132 << + IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749 ; + assign _theResult___snd__h638848 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h405717 : - _theResult___snd__h405710 ; - assign _theResult___snd__h405710 = + _theResult___snd__h638857 : + _theResult___snd__h638850 ; + assign _theResult___snd__h638850 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h405717 = + assign _theResult___snd__h638857 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && - NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h381390 : - _theResult___snd__h405723 ; - assign _theResult___snd__h405723 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57[54:0], + NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9925) ? + sfd__h614530 : + _theResult___snd__h638863 ; + assign _theResult___snd__h638863 = + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q76[54:0], 2'd0 } ; - assign _theResult___snd__h405746 = - sfd__h381390 << - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 ; - assign _theResult___snd__h414878 = { _theResult____h406629[55:0], 1'd0 } ; - assign _theResult___snd__h414889 = - (!_theResult____h406629[56] && _theResult____h406629[55]) ? - _theResult___snd__h414891 : - _theResult___snd__h414901 ; - assign _theResult___snd__h414891 = { _theResult____h406629[54:0], 2'd0 } ; - assign _theResult___snd__h414901 = - (!_theResult____h406629[56] && !_theResult____h406629[55] && - !_theResult____h406629[54] && - !_theResult____h406629[53] && - !_theResult____h406629[52] && - !_theResult____h406629[51] && - !_theResult____h406629[50] && - !_theResult____h406629[49] && - !_theResult____h406629[48] && - !_theResult____h406629[47] && - !_theResult____h406629[46] && - !_theResult____h406629[45] && - !_theResult____h406629[44] && - !_theResult____h406629[43] && - !_theResult____h406629[42] && - !_theResult____h406629[41] && - !_theResult____h406629[40] && - !_theResult____h406629[39] && - !_theResult____h406629[38] && - !_theResult____h406629[37] && - !_theResult____h406629[36] && - !_theResult____h406629[35] && - !_theResult____h406629[34] && - !_theResult____h406629[33] && - !_theResult____h406629[32] && - !_theResult____h406629[31] && - !_theResult____h406629[30] && - !_theResult____h406629[29] && - !_theResult____h406629[28] && - !_theResult____h406629[27] && - !_theResult____h406629[26] && - !_theResult____h406629[25] && - !_theResult____h406629[24] && - !_theResult____h406629[23] && - !_theResult____h406629[22] && - !_theResult____h406629[21] && - !_theResult____h406629[20] && - !_theResult____h406629[19] && - !_theResult____h406629[18] && - !_theResult____h406629[17] && - !_theResult____h406629[16] && - !_theResult____h406629[15] && - !_theResult____h406629[14] && - !_theResult____h406629[13] && - !_theResult____h406629[12] && - !_theResult____h406629[11] && - !_theResult____h406629[10] && - !_theResult____h406629[9] && - !_theResult____h406629[8] && - !_theResult____h406629[7] && - !_theResult____h406629[6] && - !_theResult____h406629[5] && - !_theResult____h406629[4] && - !_theResult____h406629[3] && - !_theResult____h406629[2] && - !_theResult____h406629[1] && - !_theResult____h406629[0]) ? - _theResult____h406629 : - _theResult___snd__h414907 ; - assign _theResult___snd__h414907 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65[54:0], + assign _theResult___snd__h638886 = + sfd__h614530 << + IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 ; + assign _theResult___snd__h648018 = { _theResult____h639769[55:0], 1'd0 } ; + assign _theResult___snd__h648029 = + (!_theResult____h639769[56] && _theResult____h639769[55]) ? + _theResult___snd__h648031 : + _theResult___snd__h648041 ; + assign _theResult___snd__h648031 = { _theResult____h639769[54:0], 2'd0 } ; + assign _theResult___snd__h648041 = + (!_theResult____h639769[56] && !_theResult____h639769[55] && + !_theResult____h639769[54] && + !_theResult____h639769[53] && + !_theResult____h639769[52] && + !_theResult____h639769[51] && + !_theResult____h639769[50] && + !_theResult____h639769[49] && + !_theResult____h639769[48] && + !_theResult____h639769[47] && + !_theResult____h639769[46] && + !_theResult____h639769[45] && + !_theResult____h639769[44] && + !_theResult____h639769[43] && + !_theResult____h639769[42] && + !_theResult____h639769[41] && + !_theResult____h639769[40] && + !_theResult____h639769[39] && + !_theResult____h639769[38] && + !_theResult____h639769[37] && + !_theResult____h639769[36] && + !_theResult____h639769[35] && + !_theResult____h639769[34] && + !_theResult____h639769[33] && + !_theResult____h639769[32] && + !_theResult____h639769[31] && + !_theResult____h639769[30] && + !_theResult____h639769[29] && + !_theResult____h639769[28] && + !_theResult____h639769[27] && + !_theResult____h639769[26] && + !_theResult____h639769[25] && + !_theResult____h639769[24] && + !_theResult____h639769[23] && + !_theResult____h639769[22] && + !_theResult____h639769[21] && + !_theResult____h639769[20] && + !_theResult____h639769[19] && + !_theResult____h639769[18] && + !_theResult____h639769[17] && + !_theResult____h639769[16] && + !_theResult____h639769[15] && + !_theResult____h639769[14] && + !_theResult____h639769[13] && + !_theResult____h639769[12] && + !_theResult____h639769[11] && + !_theResult____h639769[10] && + !_theResult____h639769[9] && + !_theResult____h639769[8] && + !_theResult____h639769[7] && + !_theResult____h639769[6] && + !_theResult____h639769[5] && + !_theResult____h639769[4] && + !_theResult____h639769[3] && + !_theResult____h639769[2] && + !_theResult____h639769[1] && + !_theResult____h639769[0]) ? + _theResult____h639769 : + _theResult___snd__h648047 ; + assign _theResult___snd__h648047 = + { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q84[54:0], 2'd0 } ; - assign _theResult___snd__h414930 = - _theResult____h406629 << - IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 ; - assign _theResult___snd__h423498 = + assign _theResult___snd__h648070 = + _theResult____h639769 << + IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10300 ; + assign _theResult___snd__h656638 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h423512 : - _theResult___snd__h405710 ; - assign _theResult___snd__h423512 = + _theResult___snd__h656652 : + _theResult___snd__h638850 ; + assign _theResult___snd__h656652 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && - NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h381390 : - _theResult___snd__h423518 ; - assign _theResult___snd__h423518 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70[54:0], + NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9925) ? + sfd__h614530 : + _theResult___snd__h656658 ; + assign _theResult___snd__h656658 = + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q89[54:0], 2'd0 } ; - assign _theResult___snd__h423536 = - sfd__h381390 << - (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260[8] ? + assign _theResult___snd__h656676 = + sfd__h614530 << + (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10374[8] ? 9'h0AA : - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260) ; - assign _theResult___snd__h442800 = { _theResult____h434680[55:0], 1'd0 } ; - assign _theResult___snd__h442811 = - (!_theResult____h434680[56] && _theResult____h434680[55]) ? - _theResult___snd__h442813 : - _theResult___snd__h442823 ; - assign _theResult___snd__h442813 = { _theResult____h434680[54:0], 2'd0 } ; - assign _theResult___snd__h442823 = - (!_theResult____h434680[56] && !_theResult____h434680[55] && - !_theResult____h434680[54] && - !_theResult____h434680[53] && - !_theResult____h434680[52] && - !_theResult____h434680[51] && - !_theResult____h434680[50] && - !_theResult____h434680[49] && - !_theResult____h434680[48] && - !_theResult____h434680[47] && - !_theResult____h434680[46] && - !_theResult____h434680[45] && - !_theResult____h434680[44] && - !_theResult____h434680[43] && - !_theResult____h434680[42] && - !_theResult____h434680[41] && - !_theResult____h434680[40] && - !_theResult____h434680[39] && - !_theResult____h434680[38] && - !_theResult____h434680[37] && - !_theResult____h434680[36] && - !_theResult____h434680[35] && - !_theResult____h434680[34] && - !_theResult____h434680[33] && - !_theResult____h434680[32] && - !_theResult____h434680[31] && - !_theResult____h434680[30] && - !_theResult____h434680[29] && - !_theResult____h434680[28] && - !_theResult____h434680[27] && - !_theResult____h434680[26] && - !_theResult____h434680[25] && - !_theResult____h434680[24] && - !_theResult____h434680[23] && - !_theResult____h434680[22] && - !_theResult____h434680[21] && - !_theResult____h434680[20] && - !_theResult____h434680[19] && - !_theResult____h434680[18] && - !_theResult____h434680[17] && - !_theResult____h434680[16] && - !_theResult____h434680[15] && - !_theResult____h434680[14] && - !_theResult____h434680[13] && - !_theResult____h434680[12] && - !_theResult____h434680[11] && - !_theResult____h434680[10] && - !_theResult____h434680[9] && - !_theResult____h434680[8] && - !_theResult____h434680[7] && - !_theResult____h434680[6] && - !_theResult____h434680[5] && - !_theResult____h434680[4] && - !_theResult____h434680[3] && - !_theResult____h434680[2] && - !_theResult____h434680[1] && - !_theResult____h434680[0]) ? - _theResult____h434680 : - _theResult___snd__h442829 ; - assign _theResult___snd__h442829 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90[54:0], + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10374) ; + assign _theResult___snd__h675999 = { _theResult____h667879[55:0], 1'd0 } ; + assign _theResult___snd__h676010 = + (!_theResult____h667879[56] && _theResult____h667879[55]) ? + _theResult___snd__h676012 : + _theResult___snd__h676022 ; + assign _theResult___snd__h676012 = { _theResult____h667879[54:0], 2'd0 } ; + assign _theResult___snd__h676022 = + (!_theResult____h667879[56] && !_theResult____h667879[55] && + !_theResult____h667879[54] && + !_theResult____h667879[53] && + !_theResult____h667879[52] && + !_theResult____h667879[51] && + !_theResult____h667879[50] && + !_theResult____h667879[49] && + !_theResult____h667879[48] && + !_theResult____h667879[47] && + !_theResult____h667879[46] && + !_theResult____h667879[45] && + !_theResult____h667879[44] && + !_theResult____h667879[43] && + !_theResult____h667879[42] && + !_theResult____h667879[41] && + !_theResult____h667879[40] && + !_theResult____h667879[39] && + !_theResult____h667879[38] && + !_theResult____h667879[37] && + !_theResult____h667879[36] && + !_theResult____h667879[35] && + !_theResult____h667879[34] && + !_theResult____h667879[33] && + !_theResult____h667879[32] && + !_theResult____h667879[31] && + !_theResult____h667879[30] && + !_theResult____h667879[29] && + !_theResult____h667879[28] && + !_theResult____h667879[27] && + !_theResult____h667879[26] && + !_theResult____h667879[25] && + !_theResult____h667879[24] && + !_theResult____h667879[23] && + !_theResult____h667879[22] && + !_theResult____h667879[21] && + !_theResult____h667879[20] && + !_theResult____h667879[19] && + !_theResult____h667879[18] && + !_theResult____h667879[17] && + !_theResult____h667879[16] && + !_theResult____h667879[15] && + !_theResult____h667879[14] && + !_theResult____h667879[13] && + !_theResult____h667879[12] && + !_theResult____h667879[11] && + !_theResult____h667879[10] && + !_theResult____h667879[9] && + !_theResult____h667879[8] && + !_theResult____h667879[7] && + !_theResult____h667879[6] && + !_theResult____h667879[5] && + !_theResult____h667879[4] && + !_theResult____h667879[3] && + !_theResult____h667879[2] && + !_theResult____h667879[1] && + !_theResult____h667879[0]) ? + _theResult____h667879 : + _theResult___snd__h676028 ; + assign _theResult___snd__h676028 = + { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q109[54:0], 2'd0 } ; - assign _theResult___snd__h442852 = - _theResult____h434680 << - IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 ; - assign _theResult___snd__h451396 = + assign _theResult___snd__h676051 = + _theResult____h667879 << + IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146 ; + assign _theResult___snd__h684595 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h451405 : - _theResult___snd__h451398 ; - assign _theResult___snd__h451398 = + _theResult___snd__h684604 : + _theResult___snd__h684597 ; + assign _theResult___snd__h684597 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h451405 = + assign _theResult___snd__h684604 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && - NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427078 : - _theResult___snd__h451411 ; - assign _theResult___snd__h451411 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92[54:0], + NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11322) ? + sfd__h660277 : + _theResult___snd__h684610 ; + assign _theResult___snd__h684610 = + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q111[54:0], 2'd0 } ; - assign _theResult___snd__h451434 = - sfd__h427078 << - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 ; - assign _theResult___snd__h460566 = { _theResult____h452317[55:0], 1'd0 } ; - assign _theResult___snd__h460577 = - (!_theResult____h452317[56] && _theResult____h452317[55]) ? - _theResult___snd__h460579 : - _theResult___snd__h460589 ; - assign _theResult___snd__h460579 = { _theResult____h452317[54:0], 2'd0 } ; - assign _theResult___snd__h460589 = - (!_theResult____h452317[56] && !_theResult____h452317[55] && - !_theResult____h452317[54] && - !_theResult____h452317[53] && - !_theResult____h452317[52] && - !_theResult____h452317[51] && - !_theResult____h452317[50] && - !_theResult____h452317[49] && - !_theResult____h452317[48] && - !_theResult____h452317[47] && - !_theResult____h452317[46] && - !_theResult____h452317[45] && - !_theResult____h452317[44] && - !_theResult____h452317[43] && - !_theResult____h452317[42] && - !_theResult____h452317[41] && - !_theResult____h452317[40] && - !_theResult____h452317[39] && - !_theResult____h452317[38] && - !_theResult____h452317[37] && - !_theResult____h452317[36] && - !_theResult____h452317[35] && - !_theResult____h452317[34] && - !_theResult____h452317[33] && - !_theResult____h452317[32] && - !_theResult____h452317[31] && - !_theResult____h452317[30] && - !_theResult____h452317[29] && - !_theResult____h452317[28] && - !_theResult____h452317[27] && - !_theResult____h452317[26] && - !_theResult____h452317[25] && - !_theResult____h452317[24] && - !_theResult____h452317[23] && - !_theResult____h452317[22] && - !_theResult____h452317[21] && - !_theResult____h452317[20] && - !_theResult____h452317[19] && - !_theResult____h452317[18] && - !_theResult____h452317[17] && - !_theResult____h452317[16] && - !_theResult____h452317[15] && - !_theResult____h452317[14] && - !_theResult____h452317[13] && - !_theResult____h452317[12] && - !_theResult____h452317[11] && - !_theResult____h452317[10] && - !_theResult____h452317[9] && - !_theResult____h452317[8] && - !_theResult____h452317[7] && - !_theResult____h452317[6] && - !_theResult____h452317[5] && - !_theResult____h452317[4] && - !_theResult____h452317[3] && - !_theResult____h452317[2] && - !_theResult____h452317[1] && - !_theResult____h452317[0]) ? - _theResult____h452317 : - _theResult___snd__h460595 ; - assign _theResult___snd__h460595 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100[54:0], + assign _theResult___snd__h684633 = + sfd__h660277 << + IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 ; + assign _theResult___snd__h693765 = { _theResult____h685516[55:0], 1'd0 } ; + assign _theResult___snd__h693776 = + (!_theResult____h685516[56] && _theResult____h685516[55]) ? + _theResult___snd__h693778 : + _theResult___snd__h693788 ; + assign _theResult___snd__h693778 = { _theResult____h685516[54:0], 2'd0 } ; + assign _theResult___snd__h693788 = + (!_theResult____h685516[56] && !_theResult____h685516[55] && + !_theResult____h685516[54] && + !_theResult____h685516[53] && + !_theResult____h685516[52] && + !_theResult____h685516[51] && + !_theResult____h685516[50] && + !_theResult____h685516[49] && + !_theResult____h685516[48] && + !_theResult____h685516[47] && + !_theResult____h685516[46] && + !_theResult____h685516[45] && + !_theResult____h685516[44] && + !_theResult____h685516[43] && + !_theResult____h685516[42] && + !_theResult____h685516[41] && + !_theResult____h685516[40] && + !_theResult____h685516[39] && + !_theResult____h685516[38] && + !_theResult____h685516[37] && + !_theResult____h685516[36] && + !_theResult____h685516[35] && + !_theResult____h685516[34] && + !_theResult____h685516[33] && + !_theResult____h685516[32] && + !_theResult____h685516[31] && + !_theResult____h685516[30] && + !_theResult____h685516[29] && + !_theResult____h685516[28] && + !_theResult____h685516[27] && + !_theResult____h685516[26] && + !_theResult____h685516[25] && + !_theResult____h685516[24] && + !_theResult____h685516[23] && + !_theResult____h685516[22] && + !_theResult____h685516[21] && + !_theResult____h685516[20] && + !_theResult____h685516[19] && + !_theResult____h685516[18] && + !_theResult____h685516[17] && + !_theResult____h685516[16] && + !_theResult____h685516[15] && + !_theResult____h685516[14] && + !_theResult____h685516[13] && + !_theResult____h685516[12] && + !_theResult____h685516[11] && + !_theResult____h685516[10] && + !_theResult____h685516[9] && + !_theResult____h685516[8] && + !_theResult____h685516[7] && + !_theResult____h685516[6] && + !_theResult____h685516[5] && + !_theResult____h685516[4] && + !_theResult____h685516[3] && + !_theResult____h685516[2] && + !_theResult____h685516[1] && + !_theResult____h685516[0]) ? + _theResult____h685516 : + _theResult___snd__h693794 ; + assign _theResult___snd__h693794 = + { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q119[54:0], 2'd0 } ; - assign _theResult___snd__h460618 = - _theResult____h452317 << - IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 ; - assign _theResult___snd__h469186 = + assign _theResult___snd__h693817 = + _theResult____h685516 << + IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11697 ; + assign _theResult___snd__h702385 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h469200 : - _theResult___snd__h451398 ; - assign _theResult___snd__h469200 = + _theResult___snd__h702399 : + _theResult___snd__h684597 ; + assign _theResult___snd__h702399 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && - NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427078 : - _theResult___snd__h469206 ; - assign _theResult___snd__h469206 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105[54:0], + NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11322) ? + sfd__h660277 : + _theResult___snd__h702405 ; + assign _theResult___snd__h702405 = + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q124[54:0], 2'd0 } ; - assign _theResult___snd__h469224 = - sfd__h427078 << - (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652[8] ? + assign _theResult___snd__h702423 = + sfd__h660277 << + (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11771[8] ? 9'h0AA : - IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652) ; - assign _theResult___snd__h498625 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___snd__h498634 : - _theResult___snd__h498627 ; - assign _theResult___snd__h498627 = - { coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 34'd0 } ; - assign _theResult___snd__h498634 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && - !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548) ? - sfd__h479673 : - _theResult___snd__h498640 ; - assign _theResult___snd__h498640 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126[54:0], + IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11771) ; + assign _theResult___snd__h734164 = + (f1_exp__h714825 == 8'd0) ? + _theResult___snd__h734173 : + _theResult___snd__h734166 ; + assign _theResult___snd__h734166 = { f1_sfd__h714826, 34'd0 } ; + assign _theResult___snd__h734173 = + (f1_exp__h714825 == 8'd0 && !f1_sfd__h714826[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689) ? + sfd__h715187 : + _theResult___snd__h734179 ; + assign _theResult___snd__h734179 = + { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q145[54:0], 2'd0 } ; - assign _theResult___snd__h498663 = - sfd__h479673 << - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 ; - assign _theResult___snd__h508262 = { _theResult____h500015[55:0], 1'd0 } ; - assign _theResult___snd__h508273 = - (!_theResult____h500015[56] && _theResult____h500015[55]) ? - _theResult___snd__h508275 : - _theResult___snd__h508285 ; - assign _theResult___snd__h508275 = { _theResult____h500015[54:0], 2'd0 } ; - assign _theResult___snd__h508285 = - (!_theResult____h500015[56] && !_theResult____h500015[55] && - !_theResult____h500015[54] && - !_theResult____h500015[53] && - !_theResult____h500015[52] && - !_theResult____h500015[51] && - !_theResult____h500015[50] && - !_theResult____h500015[49] && - !_theResult____h500015[48] && - !_theResult____h500015[47] && - !_theResult____h500015[46] && - !_theResult____h500015[45] && - !_theResult____h500015[44] && - !_theResult____h500015[43] && - !_theResult____h500015[42] && - !_theResult____h500015[41] && - !_theResult____h500015[40] && - !_theResult____h500015[39] && - !_theResult____h500015[38] && - !_theResult____h500015[37] && - !_theResult____h500015[36] && - !_theResult____h500015[35] && - !_theResult____h500015[34] && - !_theResult____h500015[33] && - !_theResult____h500015[32] && - !_theResult____h500015[31] && - !_theResult____h500015[30] && - !_theResult____h500015[29] && - !_theResult____h500015[28] && - !_theResult____h500015[27] && - !_theResult____h500015[26] && - !_theResult____h500015[25] && - !_theResult____h500015[24] && - !_theResult____h500015[23] && - !_theResult____h500015[22] && - !_theResult____h500015[21] && - !_theResult____h500015[20] && - !_theResult____h500015[19] && - !_theResult____h500015[18] && - !_theResult____h500015[17] && - !_theResult____h500015[16] && - !_theResult____h500015[15] && - !_theResult____h500015[14] && - !_theResult____h500015[13] && - !_theResult____h500015[12] && - !_theResult____h500015[11] && - !_theResult____h500015[10] && - !_theResult____h500015[9] && - !_theResult____h500015[8] && - !_theResult____h500015[7] && - !_theResult____h500015[6] && - !_theResult____h500015[5] && - !_theResult____h500015[4] && - !_theResult____h500015[3] && - !_theResult____h500015[2] && - !_theResult____h500015[1] && - !_theResult____h500015[0]) ? - _theResult____h500015 : - _theResult___snd__h508291 ; - assign _theResult___snd__h508291 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130[54:0], + assign _theResult___snd__h734202 = + sfd__h715187 << + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 ; + assign _theResult___snd__h743801 = { _theResult____h735554[55:0], 1'd0 } ; + assign _theResult___snd__h743812 = + (!_theResult____h735554[56] && _theResult____h735554[55]) ? + _theResult___snd__h743814 : + _theResult___snd__h743824 ; + assign _theResult___snd__h743814 = { _theResult____h735554[54:0], 2'd0 } ; + assign _theResult___snd__h743824 = + (!_theResult____h735554[56] && !_theResult____h735554[55] && + !_theResult____h735554[54] && + !_theResult____h735554[53] && + !_theResult____h735554[52] && + !_theResult____h735554[51] && + !_theResult____h735554[50] && + !_theResult____h735554[49] && + !_theResult____h735554[48] && + !_theResult____h735554[47] && + !_theResult____h735554[46] && + !_theResult____h735554[45] && + !_theResult____h735554[44] && + !_theResult____h735554[43] && + !_theResult____h735554[42] && + !_theResult____h735554[41] && + !_theResult____h735554[40] && + !_theResult____h735554[39] && + !_theResult____h735554[38] && + !_theResult____h735554[37] && + !_theResult____h735554[36] && + !_theResult____h735554[35] && + !_theResult____h735554[34] && + !_theResult____h735554[33] && + !_theResult____h735554[32] && + !_theResult____h735554[31] && + !_theResult____h735554[30] && + !_theResult____h735554[29] && + !_theResult____h735554[28] && + !_theResult____h735554[27] && + !_theResult____h735554[26] && + !_theResult____h735554[25] && + !_theResult____h735554[24] && + !_theResult____h735554[23] && + !_theResult____h735554[22] && + !_theResult____h735554[21] && + !_theResult____h735554[20] && + !_theResult____h735554[19] && + !_theResult____h735554[18] && + !_theResult____h735554[17] && + !_theResult____h735554[16] && + !_theResult____h735554[15] && + !_theResult____h735554[14] && + !_theResult____h735554[13] && + !_theResult____h735554[12] && + !_theResult____h735554[11] && + !_theResult____h735554[10] && + !_theResult____h735554[9] && + !_theResult____h735554[8] && + !_theResult____h735554[7] && + !_theResult____h735554[6] && + !_theResult____h735554[5] && + !_theResult____h735554[4] && + !_theResult____h735554[3] && + !_theResult____h735554[2] && + !_theResult____h735554[1] && + !_theResult____h735554[0]) ? + _theResult____h735554 : + _theResult___snd__h743830 ; + assign _theResult___snd__h743830 = + { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q149[54:0], 2'd0 } ; - assign _theResult___snd__h508314 = - _theResult____h500015 << - IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 ; - assign _theResult___snd__h517030 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___snd__h517044 : - _theResult___snd__h498627 ; - assign _theResult___snd__h517044 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && - !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548) ? - sfd__h479673 : - _theResult___snd__h517050 ; - assign _theResult___snd__h517050 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133[54:0], + assign _theResult___snd__h743853 = + _theResult____h735554 << + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13028 ; + assign _theResult___snd__h752569 = + (f1_exp__h714825 == 8'd0) ? + _theResult___snd__h752583 : + _theResult___snd__h734166 ; + assign _theResult___snd__h752583 = + (f1_exp__h714825 == 8'd0 && !f1_sfd__h714826[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689) ? + sfd__h715187 : + _theResult___snd__h752589 ; + assign _theResult___snd__h752589 = + { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q152[54:0], 2'd0 } ; - assign _theResult___snd__h517068 = - sfd__h479673 << - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938 ; - assign _theResult___snd__h537426 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___snd__h537435 : - _theResult___snd__h537428 ; - assign _theResult___snd__h537428 = - { coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 34'd0 } ; - assign _theResult___snd__h537435 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && - !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036) ? - sfd__h518615 : - _theResult___snd__h537441 ; - assign _theResult___snd__h537441 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166[54:0], + assign _theResult___snd__h752607 = + sfd__h715187 << + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13079 ; + assign _theResult___snd__h773017 = + (f2_exp__h753819 == 8'd0) ? + _theResult___snd__h773026 : + _theResult___snd__h773019 ; + assign _theResult___snd__h773019 = { f2_sfd__h753820, 34'd0 } ; + assign _theResult___snd__h773026 = + (f2_exp__h753819 == 8'd0 && !f2_sfd__h753820[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189) ? + sfd__h754181 : + _theResult___snd__h773032 ; + assign _theResult___snd__h773032 = + { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q185[54:0], 2'd0 } ; - assign _theResult___snd__h537464 = - sfd__h518615 << - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 ; - assign _theResult___snd__h547063 = { _theResult____h538816[55:0], 1'd0 } ; - assign _theResult___snd__h547074 = - (!_theResult____h538816[56] && _theResult____h538816[55]) ? - _theResult___snd__h547076 : - _theResult___snd__h547086 ; - assign _theResult___snd__h547076 = { _theResult____h538816[54:0], 2'd0 } ; - assign _theResult___snd__h547086 = - (!_theResult____h538816[56] && !_theResult____h538816[55] && - !_theResult____h538816[54] && - !_theResult____h538816[53] && - !_theResult____h538816[52] && - !_theResult____h538816[51] && - !_theResult____h538816[50] && - !_theResult____h538816[49] && - !_theResult____h538816[48] && - !_theResult____h538816[47] && - !_theResult____h538816[46] && - !_theResult____h538816[45] && - !_theResult____h538816[44] && - !_theResult____h538816[43] && - !_theResult____h538816[42] && - !_theResult____h538816[41] && - !_theResult____h538816[40] && - !_theResult____h538816[39] && - !_theResult____h538816[38] && - !_theResult____h538816[37] && - !_theResult____h538816[36] && - !_theResult____h538816[35] && - !_theResult____h538816[34] && - !_theResult____h538816[33] && - !_theResult____h538816[32] && - !_theResult____h538816[31] && - !_theResult____h538816[30] && - !_theResult____h538816[29] && - !_theResult____h538816[28] && - !_theResult____h538816[27] && - !_theResult____h538816[26] && - !_theResult____h538816[25] && - !_theResult____h538816[24] && - !_theResult____h538816[23] && - !_theResult____h538816[22] && - !_theResult____h538816[21] && - !_theResult____h538816[20] && - !_theResult____h538816[19] && - !_theResult____h538816[18] && - !_theResult____h538816[17] && - !_theResult____h538816[16] && - !_theResult____h538816[15] && - !_theResult____h538816[14] && - !_theResult____h538816[13] && - !_theResult____h538816[12] && - !_theResult____h538816[11] && - !_theResult____h538816[10] && - !_theResult____h538816[9] && - !_theResult____h538816[8] && - !_theResult____h538816[7] && - !_theResult____h538816[6] && - !_theResult____h538816[5] && - !_theResult____h538816[4] && - !_theResult____h538816[3] && - !_theResult____h538816[2] && - !_theResult____h538816[1] && - !_theResult____h538816[0]) ? - _theResult____h538816 : - _theResult___snd__h547092 ; - assign _theResult___snd__h547092 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170[54:0], + assign _theResult___snd__h773055 = + sfd__h754181 << + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 ; + assign _theResult___snd__h782654 = { _theResult____h774407[55:0], 1'd0 } ; + assign _theResult___snd__h782665 = + (!_theResult____h774407[56] && _theResult____h774407[55]) ? + _theResult___snd__h782667 : + _theResult___snd__h782677 ; + assign _theResult___snd__h782667 = { _theResult____h774407[54:0], 2'd0 } ; + assign _theResult___snd__h782677 = + (!_theResult____h774407[56] && !_theResult____h774407[55] && + !_theResult____h774407[54] && + !_theResult____h774407[53] && + !_theResult____h774407[52] && + !_theResult____h774407[51] && + !_theResult____h774407[50] && + !_theResult____h774407[49] && + !_theResult____h774407[48] && + !_theResult____h774407[47] && + !_theResult____h774407[46] && + !_theResult____h774407[45] && + !_theResult____h774407[44] && + !_theResult____h774407[43] && + !_theResult____h774407[42] && + !_theResult____h774407[41] && + !_theResult____h774407[40] && + !_theResult____h774407[39] && + !_theResult____h774407[38] && + !_theResult____h774407[37] && + !_theResult____h774407[36] && + !_theResult____h774407[35] && + !_theResult____h774407[34] && + !_theResult____h774407[33] && + !_theResult____h774407[32] && + !_theResult____h774407[31] && + !_theResult____h774407[30] && + !_theResult____h774407[29] && + !_theResult____h774407[28] && + !_theResult____h774407[27] && + !_theResult____h774407[26] && + !_theResult____h774407[25] && + !_theResult____h774407[24] && + !_theResult____h774407[23] && + !_theResult____h774407[22] && + !_theResult____h774407[21] && + !_theResult____h774407[20] && + !_theResult____h774407[19] && + !_theResult____h774407[18] && + !_theResult____h774407[17] && + !_theResult____h774407[16] && + !_theResult____h774407[15] && + !_theResult____h774407[14] && + !_theResult____h774407[13] && + !_theResult____h774407[12] && + !_theResult____h774407[11] && + !_theResult____h774407[10] && + !_theResult____h774407[9] && + !_theResult____h774407[8] && + !_theResult____h774407[7] && + !_theResult____h774407[6] && + !_theResult____h774407[5] && + !_theResult____h774407[4] && + !_theResult____h774407[3] && + !_theResult____h774407[2] && + !_theResult____h774407[1] && + !_theResult____h774407[0]) ? + _theResult____h774407 : + _theResult___snd__h782683 ; + assign _theResult___snd__h782683 = + { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q189[54:0], 2'd0 } ; - assign _theResult___snd__h547115 = - _theResult____h538816 << - IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 ; - assign _theResult___snd__h555831 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___snd__h555845 : - _theResult___snd__h537428 ; - assign _theResult___snd__h555845 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && - !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036) ? - sfd__h518615 : - _theResult___snd__h555851 ; - assign _theResult___snd__h555851 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173[54:0], + assign _theResult___snd__h782706 = + _theResult____h774407 << + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14513 ; + assign _theResult___snd__h791422 = + (f2_exp__h753819 == 8'd0) ? + _theResult___snd__h791436 : + _theResult___snd__h773019 ; + assign _theResult___snd__h791436 = + (f2_exp__h753819 == 8'd0 && !f2_sfd__h753820[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189) ? + sfd__h754181 : + _theResult___snd__h791442 ; + assign _theResult___snd__h791442 = + { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q192[54:0], 2'd0 } ; - assign _theResult___snd__h555869 = - sfd__h518615 << - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411 ; - assign _theResult___snd__h576627 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___snd__h576636 : - _theResult___snd__h576629 ; - assign _theResult___snd__h576629 = - { coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 34'd0 } ; - assign _theResult___snd__h576636 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && - !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273) ? - sfd__h557816 : - _theResult___snd__h576642 ; - assign _theResult___snd__h576642 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143[54:0], + assign _theResult___snd__h791460 = + sfd__h754181 << + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14564 ; + assign _theResult___snd__h812321 = + (f3_exp__h793123 == 8'd0) ? + _theResult___snd__h812330 : + _theResult___snd__h812323 ; + assign _theResult___snd__h812323 = { f3_sfd__h793124, 34'd0 } ; + assign _theResult___snd__h812330 = + (f3_exp__h793123 == 8'd0 && !f3_sfd__h793124[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419) ? + sfd__h793485 : + _theResult___snd__h812336 ; + assign _theResult___snd__h812336 = + { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q162[54:0], 2'd0 } ; - assign _theResult___snd__h576665 = - sfd__h557816 << - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 ; - assign _theResult___snd__h586264 = { _theResult____h578017[55:0], 1'd0 } ; - assign _theResult___snd__h586275 = - (!_theResult____h578017[56] && _theResult____h578017[55]) ? - _theResult___snd__h586277 : - _theResult___snd__h586287 ; - assign _theResult___snd__h586277 = { _theResult____h578017[54:0], 2'd0 } ; - assign _theResult___snd__h586287 = - (!_theResult____h578017[56] && !_theResult____h578017[55] && - !_theResult____h578017[54] && - !_theResult____h578017[53] && - !_theResult____h578017[52] && - !_theResult____h578017[51] && - !_theResult____h578017[50] && - !_theResult____h578017[49] && - !_theResult____h578017[48] && - !_theResult____h578017[47] && - !_theResult____h578017[46] && - !_theResult____h578017[45] && - !_theResult____h578017[44] && - !_theResult____h578017[43] && - !_theResult____h578017[42] && - !_theResult____h578017[41] && - !_theResult____h578017[40] && - !_theResult____h578017[39] && - !_theResult____h578017[38] && - !_theResult____h578017[37] && - !_theResult____h578017[36] && - !_theResult____h578017[35] && - !_theResult____h578017[34] && - !_theResult____h578017[33] && - !_theResult____h578017[32] && - !_theResult____h578017[31] && - !_theResult____h578017[30] && - !_theResult____h578017[29] && - !_theResult____h578017[28] && - !_theResult____h578017[27] && - !_theResult____h578017[26] && - !_theResult____h578017[25] && - !_theResult____h578017[24] && - !_theResult____h578017[23] && - !_theResult____h578017[22] && - !_theResult____h578017[21] && - !_theResult____h578017[20] && - !_theResult____h578017[19] && - !_theResult____h578017[18] && - !_theResult____h578017[17] && - !_theResult____h578017[16] && - !_theResult____h578017[15] && - !_theResult____h578017[14] && - !_theResult____h578017[13] && - !_theResult____h578017[12] && - !_theResult____h578017[11] && - !_theResult____h578017[10] && - !_theResult____h578017[9] && - !_theResult____h578017[8] && - !_theResult____h578017[7] && - !_theResult____h578017[6] && - !_theResult____h578017[5] && - !_theResult____h578017[4] && - !_theResult____h578017[3] && - !_theResult____h578017[2] && - !_theResult____h578017[1] && - !_theResult____h578017[0]) ? - _theResult____h578017 : - _theResult___snd__h586293 ; - assign _theResult___snd__h586293 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147[54:0], + assign _theResult___snd__h812359 = + sfd__h793485 << + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 ; + assign _theResult___snd__h821958 = { _theResult____h813711[55:0], 1'd0 } ; + assign _theResult___snd__h821969 = + (!_theResult____h813711[56] && _theResult____h813711[55]) ? + _theResult___snd__h821971 : + _theResult___snd__h821981 ; + assign _theResult___snd__h821971 = { _theResult____h813711[54:0], 2'd0 } ; + assign _theResult___snd__h821981 = + (!_theResult____h813711[56] && !_theResult____h813711[55] && + !_theResult____h813711[54] && + !_theResult____h813711[53] && + !_theResult____h813711[52] && + !_theResult____h813711[51] && + !_theResult____h813711[50] && + !_theResult____h813711[49] && + !_theResult____h813711[48] && + !_theResult____h813711[47] && + !_theResult____h813711[46] && + !_theResult____h813711[45] && + !_theResult____h813711[44] && + !_theResult____h813711[43] && + !_theResult____h813711[42] && + !_theResult____h813711[41] && + !_theResult____h813711[40] && + !_theResult____h813711[39] && + !_theResult____h813711[38] && + !_theResult____h813711[37] && + !_theResult____h813711[36] && + !_theResult____h813711[35] && + !_theResult____h813711[34] && + !_theResult____h813711[33] && + !_theResult____h813711[32] && + !_theResult____h813711[31] && + !_theResult____h813711[30] && + !_theResult____h813711[29] && + !_theResult____h813711[28] && + !_theResult____h813711[27] && + !_theResult____h813711[26] && + !_theResult____h813711[25] && + !_theResult____h813711[24] && + !_theResult____h813711[23] && + !_theResult____h813711[22] && + !_theResult____h813711[21] && + !_theResult____h813711[20] && + !_theResult____h813711[19] && + !_theResult____h813711[18] && + !_theResult____h813711[17] && + !_theResult____h813711[16] && + !_theResult____h813711[15] && + !_theResult____h813711[14] && + !_theResult____h813711[13] && + !_theResult____h813711[12] && + !_theResult____h813711[11] && + !_theResult____h813711[10] && + !_theResult____h813711[9] && + !_theResult____h813711[8] && + !_theResult____h813711[7] && + !_theResult____h813711[6] && + !_theResult____h813711[5] && + !_theResult____h813711[4] && + !_theResult____h813711[3] && + !_theResult____h813711[2] && + !_theResult____h813711[1] && + !_theResult____h813711[0]) ? + _theResult____h813711 : + _theResult___snd__h821987 ; + assign _theResult___snd__h821987 = + { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q166[54:0], 2'd0 } ; - assign _theResult___snd__h586316 = - _theResult____h578017 << - IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 ; - assign _theResult___snd__h595032 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___snd__h595046 : - _theResult___snd__h576629 ; - assign _theResult___snd__h595046 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && - !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273) ? - sfd__h557816 : - _theResult___snd__h595052 ; - assign _theResult___snd__h595052 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150[54:0], + assign _theResult___snd__h822010 = + _theResult____h813711 << + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13743 ; + assign _theResult___snd__h830726 = + (f3_exp__h793123 == 8'd0) ? + _theResult___snd__h830740 : + _theResult___snd__h812323 ; + assign _theResult___snd__h830740 = + (f3_exp__h793123 == 8'd0 && !f3_sfd__h793124[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419) ? + sfd__h793485 : + _theResult___snd__h830746 ; + assign _theResult___snd__h830746 = + { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q169[54:0], 2'd0 } ; - assign _theResult___snd__h595070 = - sfd__h557816 << - IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9648 ; - assign _theResult___snd__h600260 = - b__h599838[63] ? b___1__h600309 : b__h599838 ; - assign _theResult___snd_fst_exp__h360593 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_exp__h352008 : - _theResult___fst_exp__h360590 ; - assign _theResult___snd_fst_exp__h378413 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_exp__h369774 : - _theResult___fst_exp__h378410 ; - assign _theResult___snd_fst_exp__h406283 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_exp__h397698 : - _theResult___fst_exp__h406280 ; - assign _theResult___snd_fst_exp__h424103 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_exp__h415464 : - _theResult___fst_exp__h424100 ; - assign _theResult___snd_fst_exp__h451971 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_exp__h443386 : - _theResult___fst_exp__h451968 ; - assign _theResult___snd_fst_exp__h469791 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_exp__h461152 : - _theResult___fst_exp__h469788 ; - assign _theResult___snd_fst_exp__h499435 = - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 ? + assign _theResult___snd__h830764 = + sfd__h793485 << + IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13794 ; + assign _theResult___snd__h836056 = + b__h835634[63] ? b___1__h836105 : b__h835634 ; + assign _theResult___snd_fst_exp__h593674 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? + _theResult___fst_exp__h585089 : + _theResult___fst_exp__h593671 ; + assign _theResult___snd_fst_exp__h611494 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? + _theResult___fst_exp__h602855 : + _theResult___fst_exp__h611491 ; + assign _theResult___snd_fst_exp__h639423 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? + _theResult___fst_exp__h630838 : + _theResult___fst_exp__h639420 ; + assign _theResult___snd_fst_exp__h657243 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? + _theResult___fst_exp__h648604 : + _theResult___fst_exp__h657240 ; + assign _theResult___snd_fst_exp__h685170 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? + _theResult___fst_exp__h676585 : + _theResult___fst_exp__h685167 ; + assign _theResult___snd_fst_exp__h702990 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? + _theResult___fst_exp__h694351 : + _theResult___fst_exp__h702987 ; + assign _theResult___snd_fst_exp__h734974 = + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 ? 11'd0 : - _theResult___fst_exp__h499432 ; - assign _theResult___snd_fst_exp__h517870 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - _theResult___fst_exp__h509083 : - _theResult___fst_exp__h517867 ; - assign _theResult___snd_fst_exp__h538236 = - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 ? + _theResult___fst_exp__h734971 ; + assign _theResult___snd_fst_exp__h753409 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? + _theResult___fst_exp__h744622 : + _theResult___fst_exp__h753406 ; + assign _theResult___snd_fst_exp__h773827 = + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 ? 11'd0 : - _theResult___fst_exp__h538233 ; - assign _theResult___snd_fst_exp__h556671 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - _theResult___fst_exp__h547884 : - _theResult___fst_exp__h556668 ; - assign _theResult___snd_fst_exp__h577437 = - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 ? + _theResult___fst_exp__h773824 ; + assign _theResult___snd_fst_exp__h792262 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? + _theResult___fst_exp__h783475 : + _theResult___fst_exp__h792259 ; + assign _theResult___snd_fst_exp__h813131 = + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 ? 11'd0 : - _theResult___fst_exp__h577434 ; - assign _theResult___snd_fst_exp__h595872 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - _theResult___fst_exp__h587085 : - _theResult___fst_exp__h595869 ; - assign _theResult___snd_fst_sfd__h335645 = + _theResult___fst_exp__h813128 ; + assign _theResult___snd_fst_exp__h831566 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? + _theResult___fst_exp__h822779 : + _theResult___fst_exp__h831563 ; + assign _theResult___snd_fst_sfd__h568726 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h360594 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_sfd__h352009 : - _theResult___fst_sfd__h360591 ; - assign _theResult___snd_fst_sfd__h378414 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_sfd__h369775 : - _theResult___fst_sfd__h378411 ; - assign _theResult___snd_fst_sfd__h381340 = + assign _theResult___snd_fst_sfd__h593675 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? + _theResult___fst_sfd__h585090 : + _theResult___fst_sfd__h593672 ; + assign _theResult___snd_fst_sfd__h611495 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? + _theResult___fst_sfd__h602856 : + _theResult___fst_sfd__h611492 ; + assign _theResult___snd_fst_sfd__h614480 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h406284 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_sfd__h397699 : - _theResult___fst_sfd__h406281 ; - assign _theResult___snd_fst_sfd__h424104 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_sfd__h415465 : - _theResult___fst_sfd__h424101 ; - assign _theResult___snd_fst_sfd__h427028 = + assign _theResult___snd_fst_sfd__h639424 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? + _theResult___fst_sfd__h630839 : + _theResult___fst_sfd__h639421 ; + assign _theResult___snd_fst_sfd__h657244 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? + _theResult___fst_sfd__h648605 : + _theResult___fst_sfd__h657241 ; + assign _theResult___snd_fst_sfd__h660227 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h451972 = - _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_sfd__h443387 : - _theResult___fst_sfd__h451969 ; - assign _theResult___snd_fst_sfd__h469792 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_sfd__h461153 : - _theResult___fst_sfd__h469789 ; - assign _theResult___snd_fst_sfd__h479627 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? + assign _theResult___snd_fst_sfd__h685171 = + _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? + _theResult___fst_sfd__h676586 : + _theResult___fst_sfd__h685168 ; + assign _theResult___snd_fst_sfd__h702991 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? + _theResult___fst_sfd__h694352 : + _theResult___fst_sfd__h702988 ; + assign _theResult___snd_fst_sfd__h715141 = + (f1_sfd__h714826 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h479376 ; - assign _theResult___snd_fst_sfd__h499436 = - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 ? + out___1_sfd__h714889 ; + assign _theResult___snd_fst_sfd__h734975 = + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 ? 52'd0 : - _theResult___fst_sfd__h499433 ; - assign _theResult___snd_fst_sfd__h517871 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - _theResult___fst_sfd__h509084 : - _theResult___fst_sfd__h517868 ; - assign _theResult___snd_fst_sfd__h518569 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? + _theResult___fst_sfd__h734972 ; + assign _theResult___snd_fst_sfd__h753410 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? + _theResult___fst_sfd__h744623 : + _theResult___fst_sfd__h753407 ; + assign _theResult___snd_fst_sfd__h754135 = + (f2_sfd__h753820 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h518318 ; - assign _theResult___snd_fst_sfd__h538237 = - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 ? + out___1_sfd__h753883 ; + assign _theResult___snd_fst_sfd__h773828 = + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 ? 52'd0 : - _theResult___fst_sfd__h538234 ; - assign _theResult___snd_fst_sfd__h556672 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - _theResult___fst_sfd__h547885 : - _theResult___fst_sfd__h556669 ; - assign _theResult___snd_fst_sfd__h557770 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? + _theResult___fst_sfd__h773825 ; + assign _theResult___snd_fst_sfd__h792263 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? + _theResult___fst_sfd__h783476 : + _theResult___fst_sfd__h792260 ; + assign _theResult___snd_fst_sfd__h793439 = + (f3_sfd__h793124 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h557519 ; - assign _theResult___snd_fst_sfd__h577438 = - _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 ? + out___1_sfd__h793187 ; + assign _theResult___snd_fst_sfd__h813132 = + _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 ? 52'd0 : - _theResult___fst_sfd__h577435 ; - assign _theResult___snd_fst_sfd__h595873 = - SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - _theResult___fst_sfd__h587086 : - _theResult___fst_sfd__h595870 ; - assign a___1__h599978 = + _theResult___fst_sfd__h813129 ; + assign _theResult___snd_fst_sfd__h831567 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? + _theResult___fst_sfd__h822780 : + _theResult___fst_sfd__h831564 ; + assign a___1__h835774 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : - { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2[31]}}, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2 } ; - assign a___1__h600264 = 64'd0 - a__h599837 ; - assign a__h599837 = + { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q21[31]}}, + coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q21 } ; + assign a___1__h836060 = 64'd0 - a__h835633 ; + assign a__h835633 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h599978 : + a___1__h835774 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h599979 = + assign addBase__h239805 = + { {48{base__h239640[15]}}, base__h239640 } << + coreFix_memExe_regToExeQ$first[264:259] ; + assign addBase__h240962 = + { {48{base__h240797[15]}}, base__h240797 } << + coreFix_memExe_regToExeQ$first[101:96] ; + assign addBase__h254571 = + { {48{base__h254406[15]}}, base__h254406 } << + coreFix_memExe_dTlb$procResp[334:329] ; + assign addTop__h239914 = + { {50{x__h240013[15]}}, x__h240013 } << + coreFix_memExe_regToExeQ$first[264:259] ; + assign addTop__h241071 = + { {50{x__h241170[15]}}, x__h241170 } << + coreFix_memExe_regToExeQ$first[101:96] ; + assign addTop__h254680 = + { {50{x__h254779[15]}}, x__h254779 } << + coreFix_memExe_dTlb$procResp[334:329] ; + assign addr__h148408 = + coreFix_memExe_reqLdQ_data_0_lat_0$whas ? + coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : + coreFix_memExe_reqLdQ_data_0_rl[63:0] ; + assign addr__h151984 = + CAN_FIRE_RL_coreFix_memExe_doIssueSB ? + coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : + coreFix_memExe_reqStQ_data_0_rl[63:0] ; + assign addr__h235261 = x__h235690[63:0] + csrf_ddc_reg[149:86] ; + assign addr__h986843 = + (rob$deqPort_0_deq_data[273:272] == 2'd1 && + (rob$deqPort_0_deq_data[265:261] == 5'd1 || + rob$deqPort_0_deq_data[265:261] == 5'd12)) ? + rob$deqPort_0_deq_data[260:197] : + rob$deqPort_0_deq_data[191:128] ; + assign address__h1008010 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; + assign address__h996535 = base__h996496 + { 57'd0, x__h996694 } ; + assign address__h996585 = base__h996550 + { 57'd0, x__h996694 } ; + assign address__h996601 = { 2'd0, address__h996535 } ; + assign address__h996945 = { 2'd0, base__h996496 } ; + assign address__h997258 = { 2'd0, address__h996585 } ; + assign address__h997602 = { 2'd0, base__h996550 } ; + assign b___1__h835775 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3[31]}}, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3 } : + { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q22[31]}}, + coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q22 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h600309 = 64'd0 - b__h599838 ; - assign b__h599838 = + assign b___1__h836105 = 64'd0 - b__h835634 ; + assign b__h835634 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h599979 : + b___1__h835775 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign base__h694789 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h694992 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h692187 = - commitStage_commitTrap[4] ? i__h692362 : i__h692202 ; - assign coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101 = - coreFix_aluExe_0_bypassWire_0$wget[70:64] == + assign b_base__h127497 = + { coreFix_memExe_respLrScAmoQ_data_0[77:67], + ~coreFix_memExe_respLrScAmoQ_data_0[66], + coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; + assign b_base__h140413 = + { mmio_dataRespQ_data_0[77:67], + ~mmio_dataRespQ_data_0[66], + mmio_dataRespQ_data_0[65:64] } ; + assign b_base__h183674 = + { x__h183367[77:67], ~x__h183367[66], x__h183367[65:64] } ; + assign b_base__h202425 = + { x__h199219[77:67], ~x__h199219[66], x__h199219[65:64] } ; + assign b_base__h216991 = + { coreFix_memExe_lsq$respLd[77:67], + ~coreFix_memExe_lsq$respLd[66], + coreFix_memExe_lsq$respLd[65:64] } ; + assign b_base__h865747 = + { coreFix_aluExe_1_regToExeQ$first[255:245], + ~coreFix_aluExe_1_regToExeQ$first[244], + coreFix_aluExe_1_regToExeQ$first[243:242] } ; + assign b_base__h866295 = + { coreFix_aluExe_1_regToExeQ$first[126:116], + ~coreFix_aluExe_1_regToExeQ$first[115], + coreFix_aluExe_1_regToExeQ$first[114:113] } ; + assign b_base__h904228 = + { coreFix_aluExe_0_regToExeQ$first[255:245], + ~coreFix_aluExe_0_regToExeQ$first[244], + coreFix_aluExe_0_regToExeQ$first[243:242] } ; + assign b_base__h904776 = + { coreFix_aluExe_0_regToExeQ$first[126:116], + ~coreFix_aluExe_0_regToExeQ$first[115], + coreFix_aluExe_0_regToExeQ$first[114:113] } ; + assign b_base__h992243 = + { commitStage_commitTrap[186:176], + ~commitStage_commitTrap[175], + commitStage_commitTrap[174:173] } ; + assign b_top__h127496 = + { coreFix_memExe_respLrScAmoQ_data_0[89:81], + ~coreFix_memExe_respLrScAmoQ_data_0[80:79], + coreFix_memExe_respLrScAmoQ_data_0[78] } ; + assign b_top__h140412 = + { mmio_dataRespQ_data_0[89:81], + ~mmio_dataRespQ_data_0[80:79], + mmio_dataRespQ_data_0[78] } ; + assign b_top__h183673 = + { x__h183367[89:81], ~x__h183367[80:79], x__h183367[78] } ; + assign b_top__h202424 = + { x__h199219[89:81], ~x__h199219[80:79], x__h199219[78] } ; + assign b_top__h216990 = + { coreFix_memExe_lsq$respLd[89:81], + ~coreFix_memExe_lsq$respLd[80:79], + coreFix_memExe_lsq$respLd[78] } ; + assign b_top__h865746 = + { coreFix_aluExe_1_regToExeQ$first[267:259], + ~coreFix_aluExe_1_regToExeQ$first[258:257], + coreFix_aluExe_1_regToExeQ$first[256] } ; + assign b_top__h866294 = + { coreFix_aluExe_1_regToExeQ$first[138:130], + ~coreFix_aluExe_1_regToExeQ$first[129:128], + coreFix_aluExe_1_regToExeQ$first[127] } ; + assign b_top__h904227 = + { coreFix_aluExe_0_regToExeQ$first[267:259], + ~coreFix_aluExe_0_regToExeQ$first[258:257], + coreFix_aluExe_0_regToExeQ$first[256] } ; + assign b_top__h904775 = + { coreFix_aluExe_0_regToExeQ$first[138:130], + ~coreFix_aluExe_0_regToExeQ$first[129:128], + coreFix_aluExe_0_regToExeQ$first[127] } ; + assign b_top__h992242 = + { commitStage_commitTrap[198:190], + ~commitStage_commitTrap[189:188], + commitStage_commitTrap[187] } ; + assign base__h239640 = + { coreFix_memExe_regToExeQ$first[222:221], + coreFix_memExe_regToExeQ$first[244:231] } ; + assign base__h240797 = + { coreFix_memExe_regToExeQ$first[59:58], + coreFix_memExe_regToExeQ$first[81:68] } ; + assign base__h254406 = + { coreFix_memExe_dTlb$procResp[292:291], + coreFix_memExe_dTlb$procResp[314:301] } ; + assign base__h994681 = + { (IF_INV_commitStage_commitTrap_2029_BITS_217_TO_ETC___d22422 == + IF_INV_commitStage_commitTrap_2029_BITS_217_TO_ETC___d22424) ? + 2'd0 : + ((IF_INV_commitStage_commitTrap_2029_BITS_217_TO_ETC___d22422 && + !IF_INV_commitStage_commitTrap_2029_BITS_217_TO_ETC___d22424) ? + 2'd1 : + 2'd3), + x__h992236 } ; + assign base__h996496 = { csrf_stcc_reg[149:88], 2'b0 } ; + assign base__h996550 = { csrf_mtcc_reg[149:88], 2'b0 } ; + assign carry_out__h127401 = + (topBits__h127399 < x__h127490[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h140317 = + (topBits__h140315 < x__h140406[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h183578 = + (topBits__h183576 < x__h183667[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h202329 = + (topBits__h202327 < x__h202418[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h216895 = + (topBits__h216893 < x__h216984[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h865650 = + (topBits__h865648 < x__h865740[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h866198 = + (topBits__h866196 < x__h866288[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h904131 = + (topBits__h904129 < x__h904221[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h904679 = + (topBits__h904677 < x__h904769[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h992147 = + (topBits__h992145 < x__h992236[11:0]) ? 2'b01 : 2'b0 ; + assign cause_code__h993965 = { 1'd0, i__h992617 } ; + assign cause_interrupt__h992425 = + commitStage_commitTrap[44:43] != 2'd1 && + commitStage_commitTrap[44:43] != 2'd0 ; + assign commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22262 = + (commitStage_commitTrap[44:43] == 2'd0 || + commitStage_commitTrap[44:43] == 2'd1 || + commitStage_commitTrap[35:32] == 4'd0 || + commitStage_commitTrap[35:32] == 4'd1 || + commitStage_commitTrap[35:32] == 4'd3 || + commitStage_commitTrap[35:32] == 4'd4 || + commitStage_commitTrap[35:32] == 4'd5 || + commitStage_commitTrap[35:32] == 4'd7 || + commitStage_commitTrap[35:32] == 4'd8 || + commitStage_commitTrap[35:32] == 4'd9 || + commitStage_commitTrap[35:32] == 4'd11) && + (commitStage_commitTrap[44:43] != 2'd1 || + commitStage_commitTrap[36:32] != 5'd3 || + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q273) ; + assign commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22269 = + commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22262 || + coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq ; + assign commitStage_commitTrap_2029_BITS_44_TO_43_2222_ETC___d22374 = + (commitStage_commitTrap[44:43] == 2'd0 || + commitStage_commitTrap[44:43] == 2'd1 || + commitStage_commitTrap[35:32] != 4'd14) && + (commitStage_commitTrap[44:43] == 2'd0 || + commitStage_commitTrap[44:43] == 2'd1 || + commitStage_commitTrap[35:32] == 4'd0 || + commitStage_commitTrap[35:32] == 4'd1 || + commitStage_commitTrap[35:32] == 4'd3 || + commitStage_commitTrap[35:32] == 4'd4 || + commitStage_commitTrap[35:32] == 4'd5 || + commitStage_commitTrap[35:32] == 4'd7 || + commitStage_commitTrap[35:32] == 4'd8 || + commitStage_commitTrap[35:32] == 4'd9 || + commitStage_commitTrap[35:32] == 4'd11 || + commitStage_commitTrap[35:32] == 4'd14) && + (commitStage_commitTrap[44:43] != 2'd1 || + commitStage_commitTrap[36:32] != 5'd3 || + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q273) ; + assign coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18222 = + coreFix_aluExe_0_bypassWire_0$wget[169:163] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12140 = - coreFix_aluExe_0_bypassWire_0$wget[70:64] == + assign coreFix_aluExe_0_bypassWire_0_wget__8220_BITS__ETC___d18261 = + coreFix_aluExe_0_bypassWire_0$wget[169:163] == coreFix_aluExe_0_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12114 = - coreFix_aluExe_0_bypassWire_1$wget[70:64] == + assign coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18235 = + coreFix_aluExe_0_bypassWire_1$wget[169:163] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12146 = - coreFix_aluExe_0_bypassWire_1$wget[70:64] == + assign coreFix_aluExe_0_bypassWire_1_wget__8233_BITS__ETC___d18267 = + coreFix_aluExe_0_bypassWire_1$wget[169:163] == coreFix_aluExe_0_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_0_bypassWire_2_wget__2120_BITS__ETC___d12122 = - coreFix_aluExe_0_bypassWire_2$wget[70:64] == + assign coreFix_aluExe_0_bypassWire_2_wget__8241_BITS__ETC___d18243 = + coreFix_aluExe_0_bypassWire_2$wget[169:163] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_0_bypassWire_2_wget__2120_BITS__ETC___d12150 = - coreFix_aluExe_0_bypassWire_2$wget[70:64] == + assign coreFix_aluExe_0_bypassWire_2_wget__8241_BITS__ETC___d18271 = + coreFix_aluExe_0_bypassWire_2$wget[169:163] == coreFix_aluExe_0_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_0_dispToRegQ_first__2078_BIT_13_ETC___d12163 = - (coreFix_aluExe_0_dispToRegQ$first[131] || + assign coreFix_aluExe_0_dispToRegQ_first__8199_BIT_12_ETC___d19237 = + { coreFix_aluExe_0_dispToRegQ$first[124] && + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19004, + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19196, + coreFix_aluExe_0_dispToRegQ$first[124] ? + repBound__h898124 : + 3'd7, + NOT_coreFix_aluExe_0_dispToRegQ_first__8199_BI_ETC___d19236 } ; + assign coreFix_aluExe_0_dispToRegQ_first__8199_BIT_13_ETC___d18284 = + (coreFix_aluExe_0_dispToRegQ$first[137] || sbCons$lazyLookup_0_get[3] || - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2077_ETC___d12109 && - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12135) && + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__8198_ETC___d18230 && + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18256) && (sbCons$lazyLookup_0_get[2] || - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2077_ETC___d12143 && - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12160) ; - assign coreFix_aluExe_0_exeToFinQ_RDY_first__2490_AND_ETC___d12528 = - coreFix_aluExe_0_exeToFinQ$RDY_first && - rob$RDY_setExecuted_doFinishAlu_0_set && - (coreFix_aluExe_0_exeToFinQ$first[325:321] != 5'd9 && - coreFix_aluExe_0_exeToFinQ$first[325:321] != 5'd10 || - coreFix_trainBPQ_0$FULL_N) ; - assign coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 = + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__8198_ETC___d18264 && + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__821_ETC___d18281) ; + assign coreFix_aluExe_0_exeToFinQ_first__9735_BITS_14_ETC___d19769 = + coreFix_aluExe_0_exeToFinQ$first[146:83] < + coreFix_aluExe_0_exeToFinQ$first[281:218] ; + assign coreFix_aluExe_0_exeToFinQ_first__9735_BITS_14_ETC___d19778 = + coreFix_aluExe_0_exeToFinQ_first__9735_BITS_14_ETC___d19769 || + (coreFix_aluExe_0_exeToFinQ$first[17] ? + !coreFix_aluExe_0_exeToFinQ_first__9735_BITS_82_ETC___d19773 : + !coreFix_aluExe_0_exeToFinQ_first__9735_BITS_82_ETC___d19775) ; + assign coreFix_aluExe_0_exeToFinQ_first__9735_BITS_82_ETC___d19773 = + coreFix_aluExe_0_exeToFinQ$first[82:18] <= + coreFix_aluExe_0_exeToFinQ$first[217:153] ; + assign coreFix_aluExe_0_exeToFinQ_first__9735_BITS_82_ETC___d19775 = + coreFix_aluExe_0_exeToFinQ$first[82:18] < + coreFix_aluExe_0_exeToFinQ$first[217:153] ; + assign coreFix_aluExe_0_rsAlu_approximateCount__0973__ETC___d20975 = coreFix_aluExe_0_rsAlu$approximateCount < coreFix_aluExe_1_rsAlu$approximateCount ; - assign coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11306 = - coreFix_aluExe_0_bypassWire_0$wget[70:64] == + assign coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15613 = + coreFix_aluExe_0_bypassWire_0$wget[169:163] == coreFix_aluExe_1_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_1_bypassWire_0_wget__1304_BITS__ETC___d11345 = - coreFix_aluExe_0_bypassWire_0$wget[70:64] == + assign coreFix_aluExe_1_bypassWire_0_wget__5611_BITS__ETC___d15652 = + coreFix_aluExe_0_bypassWire_0$wget[169:163] == coreFix_aluExe_1_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_1_bypassWire_1_wget__1317_BITS__ETC___d11319 = - coreFix_aluExe_0_bypassWire_1$wget[70:64] == + assign coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15626 = + coreFix_aluExe_0_bypassWire_1$wget[169:163] == coreFix_aluExe_1_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_1_bypassWire_1_wget__1317_BITS__ETC___d11351 = - coreFix_aluExe_0_bypassWire_1$wget[70:64] == + assign coreFix_aluExe_1_bypassWire_1_wget__5624_BITS__ETC___d15658 = + coreFix_aluExe_0_bypassWire_1$wget[169:163] == coreFix_aluExe_1_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_1_bypassWire_2_wget__1325_BITS__ETC___d11327 = - coreFix_aluExe_0_bypassWire_2$wget[70:64] == + assign coreFix_aluExe_1_bypassWire_2_wget__5632_BITS__ETC___d15634 = + coreFix_aluExe_0_bypassWire_2$wget[169:163] == coreFix_aluExe_1_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_1_bypassWire_2_wget__1325_BITS__ETC___d11355 = - coreFix_aluExe_0_bypassWire_2$wget[70:64] == + assign coreFix_aluExe_1_bypassWire_2_wget__5632_BITS__ETC___d15662 = + coreFix_aluExe_0_bypassWire_2$wget[169:163] == coreFix_aluExe_1_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_1_dispToRegQ_first__1283_BIT_13_ETC___d11368 = - (coreFix_aluExe_1_dispToRegQ$first[131] || + assign coreFix_aluExe_1_dispToRegQ_first__5590_BIT_12_ETC___d17159 = + { coreFix_aluExe_1_dispToRegQ$first[124] && + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16640, + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17092, + coreFix_aluExe_1_dispToRegQ$first[124] ? + repBound__h859255 : + 3'd7, + NOT_coreFix_aluExe_1_dispToRegQ_first__5590_BI_ETC___d17158 } ; + assign coreFix_aluExe_1_dispToRegQ_first__5590_BIT_13_ETC___d15675 = + (coreFix_aluExe_1_dispToRegQ$first[137] || sbCons$lazyLookup_1_get[3] || - IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1282_ETC___d11314 && - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11340) && + IF_coreFix_aluExe_1_dispToRegQ_RDY_first__5589_ETC___d15621 && + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15647) && (sbCons$lazyLookup_1_get[2] || - IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1282_ETC___d11348 && - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11365) ; - assign coreFix_aluExe_1_exeToFinQ_RDY_first__1881_AND_ETC___d11920 = - coreFix_aluExe_1_exeToFinQ$RDY_first && - rob$RDY_setExecuted_doFinishAlu_1_set && - (coreFix_aluExe_1_exeToFinQ$first[325:321] != 5'd9 && - coreFix_aluExe_1_exeToFinQ$first[325:321] != 5'd10 || - coreFix_trainBPQ_1$FULL_N) ; - assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206 = - coreFix_aluExe_0_bypassWire_0$wget[70:64] == + IF_coreFix_aluExe_1_dispToRegQ_RDY_first__5589_ETC___d15655 && + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d15672) ; + assign coreFix_aluExe_1_exeToFinQ_first__7657_BITS_14_ETC___d17692 = + coreFix_aluExe_1_exeToFinQ$first[146:83] < + coreFix_aluExe_1_exeToFinQ$first[281:218] ; + assign coreFix_aluExe_1_exeToFinQ_first__7657_BITS_14_ETC___d17701 = + coreFix_aluExe_1_exeToFinQ_first__7657_BITS_14_ETC___d17692 || + (coreFix_aluExe_1_exeToFinQ$first[17] ? + !coreFix_aluExe_1_exeToFinQ_first__7657_BITS_82_ETC___d17696 : + !coreFix_aluExe_1_exeToFinQ_first__7657_BITS_82_ETC___d17698) ; + assign coreFix_aluExe_1_exeToFinQ_first__7657_BITS_82_ETC___d17696 = + coreFix_aluExe_1_exeToFinQ$first[82:18] <= + coreFix_aluExe_1_exeToFinQ$first[217:153] ; + assign coreFix_aluExe_1_exeToFinQ_first__7657_BITS_82_ETC___d17698 = + coreFix_aluExe_1_exeToFinQ$first[82:18] < + coreFix_aluExe_1_exeToFinQ$first[217:153] ; + assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12339 = + coreFix_fpuMulDivExe_0_bypassWire_0$wget[70:64] == coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ; - assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244 = - coreFix_aluExe_0_bypassWire_0$wget[70:64] == + assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12377 = + coreFix_fpuMulDivExe_0_bypassWire_0$wget[70:64] == coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ; - assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268 = - coreFix_aluExe_0_bypassWire_0$wget[70:64] == + assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__2337_ETC___d12401 = + coreFix_fpuMulDivExe_0_bypassWire_0$wget[70:64] == coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ; - assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8219 = - coreFix_aluExe_0_bypassWire_1$wget[70:64] == + assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12352 = + coreFix_fpuMulDivExe_0_bypassWire_1$wget[70:64] == coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ; - assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8250 = - coreFix_aluExe_0_bypassWire_1$wget[70:64] == + assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12383 = + coreFix_fpuMulDivExe_0_bypassWire_1$wget[70:64] == coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ; - assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8274 = - coreFix_aluExe_0_bypassWire_1$wget[70:64] == + assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__2350_ETC___d12407 = + coreFix_fpuMulDivExe_0_bypassWire_1$wget[70:64] == coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ; - assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8227 = - coreFix_aluExe_0_bypassWire_2$wget[70:64] == + assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__2358_ETC___d12360 = + coreFix_fpuMulDivExe_0_bypassWire_2$wget[70:64] == coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ; - assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8254 = - coreFix_aluExe_0_bypassWire_2$wget[70:64] == + assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__2358_ETC___d12387 = + coreFix_fpuMulDivExe_0_bypassWire_2$wget[70:64] == coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ; - assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8278 = - coreFix_aluExe_0_bypassWire_2$wget[70:64] == + assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__2358_ETC___d12411 = + coreFix_fpuMulDivExe_0_bypassWire_2$wget[70:64] == coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ; - assign coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5268 = + assign coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d9382 = coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned && !coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned && rob$RDY_setExecuted_doFinishFpuMulDiv_0_set && coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get && coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data ; - assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63 = + assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q82 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] - 11'd1023 ; - assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28 = + assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q47 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] - 11'd1023 ; - assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98 = + assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q117 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] - 11'd1023 ; - assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3876 = + assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d7985 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned && !coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned && rob$RDY_setExecuted_doFinishFpuMulDiv_0_set && coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get && coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data ; - assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6660 = + assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d10779 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned && !coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned && rob$RDY_setExecuted_doFinishFpuMulDiv_0_set && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get && coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data ; - assign coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_fir_ETC___d8098 = - coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data && - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init && - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY && - (!coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] || - ((coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == - 2'd2) ? - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid : - coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] != - 2'd3 || - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid)) ; - assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8101 = + assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d12228 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid && coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned && !coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned && rob$RDY_setExecuted_doFinishFpuMulDiv_0_set && - coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_fir_ETC___d8098 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8052 = + coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data && + coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init && + coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY && + ((coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == + 2'd2) ? + coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid : + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] != + 2'd3 || + coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid) ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d12176 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned && !coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned && rob$RDY_setExecuted_doFinishFpuMulDiv_0_set && coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data && coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N ; - assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10830 = + assign coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d14985 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10785 | - ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10825) ; - assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10866 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14940 | + ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && + (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && + (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14980) ; + assign coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15021 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10854 | - ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10861) ; - assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10914 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15009 | + ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && + (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && + (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15016) ; + assign coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15069 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10898 | - ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10909) ; - assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10956 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15053 | + ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && + (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && + (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15064) ; + assign coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15111 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10942 | - ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10951) ; - assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10998 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15097 | + ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && + (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && + (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15106) ; + assign coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15153 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10984 | - ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) && - (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 || - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) && - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10993) ; - assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168 = - coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] - 8'd127 ; - assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15139 | + ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && + (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && + (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15148) ; + assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q22 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; - assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128 = - coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] - 8'd127 ; - assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2 = + assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q21 = coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ; - assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145 = - coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] - 8'd127 ; - assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__36_ETC___d13767 = + assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__16_ETC___d21705 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3181_3271_OR_NOT__ETC___d13747) ; - assign coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570 = - coreFix_aluExe_0_bypassWire_0$wget[70:64] == - coreFix_memExe_dispToRegQ$first[61:55] ; - assign coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608 = - coreFix_aluExe_0_bypassWire_0$wget[70:64] == - coreFix_memExe_dispToRegQ$first[53:47] ; - assign coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583 = - coreFix_aluExe_0_bypassWire_1$wget[70:64] == - coreFix_memExe_dispToRegQ$first[61:55] ; - assign coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614 = - coreFix_aluExe_0_bypassWire_1$wget[70:64] == - coreFix_memExe_dispToRegQ$first[53:47] ; - assign coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591 = - coreFix_aluExe_0_bypassWire_2$wget[70:64] == - coreFix_memExe_dispToRegQ$first[61:55] ; - assign coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618 = - coreFix_aluExe_0_bypassWire_2$wget[70:64] == - coreFix_memExe_dispToRegQ$first[53:47] ; - assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2573 = - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + NOT_specTagManager_canClaim__0927_1023_OR_NOT__ETC___d21685) ; + assign coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2701 = + coreFix_aluExe_0_bypassWire_0$wget[169:163] == + coreFix_memExe_dispToRegQ$first[108:102] ; + assign coreFix_memExe_bypassWire_0_wget__699_BITS_169_ETC___d2739 = + coreFix_aluExe_0_bypassWire_0$wget[169:163] == + coreFix_memExe_dispToRegQ$first[100:94] ; + assign coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2714 = + coreFix_aluExe_0_bypassWire_1$wget[169:163] == + coreFix_memExe_dispToRegQ$first[108:102] ; + assign coreFix_memExe_bypassWire_1_wget__712_BITS_169_ETC___d2745 = + coreFix_aluExe_0_bypassWire_1$wget[169:163] == + coreFix_memExe_dispToRegQ$first[100:94] ; + assign coreFix_memExe_bypassWire_2_wget__720_BITS_169_ETC___d2722 = + coreFix_aluExe_0_bypassWire_2$wget[169:163] == + coreFix_memExe_dispToRegQ$first[108:102] ; + assign coreFix_memExe_bypassWire_2_wget__720_BITS_169_ETC___d2749 = + coreFix_aluExe_0_bypassWire_2$wget[169:163] == + coreFix_memExe_dispToRegQ$first[100:94] ; + assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5549 = + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 || - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] != + (!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] || + !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979) || + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520] != 2'd0 && - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 && - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT && - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h252024 ; - assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063 = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 || - (!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT || - !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry && - !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl) && - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full ; - assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3166 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 || - (!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT || - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas && - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl) && - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ; - assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2066 = + y__h422493 ; + assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5614 = + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3 && + (!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] || + !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ; + assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979 = coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] ; - assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 = - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT && - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2066 ; - assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2723 = - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT && - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[221:164] ; + assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d6972 = coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:8] ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] == - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] < - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] < + coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:8] && + coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] == + 2'd0 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[518:516] == + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520] < + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[157:156] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520] < 2'd2 ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] == - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96] ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2527 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:522] == + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[221:169] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5500 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942 && + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] != 3'd3 || - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2556 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979) ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5506 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5500 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932) || + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5505 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5526 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942 && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3 && + (!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] || + !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d4979) ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5530 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd2 || - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3) ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2561 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553 || - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2560 ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2578 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553 || - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2577 ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2595 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2588 || - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2594 ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2615 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5535 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5527 || + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5534 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5554 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5527 || + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5553 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5559 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5571 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5564 || + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5570 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5591 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0 && coreFix_memExe_lsq$getHit[8] && !coreFix_memExe_lsq$getHit[9] ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 && - (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5594 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0 && coreFix_memExe_lsq$getHit[8] && !coreFix_memExe_lsq$getHit[9] || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != 3'd1) && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2615 ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2639 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == - 3'd3 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 && - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2645 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2639 || - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5591 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5630 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5500 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != 3'd1) && - NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2642 ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2647 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 && - coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 && - (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] != - 3'd3 || - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <= + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5627 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5641 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5646 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5650 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[9] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5654 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !coreFix_memExe_lsq$getHit[9] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5658 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[8] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5663 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !coreFix_memExe_lsq$getHit[8] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5677 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5681 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2 && + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5685 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2 && + !SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5688 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5693 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[516] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5698 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[516] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5702 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[517] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5707 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[517] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5711 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[518] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5716 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[518] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5720 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[519] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5725 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[519] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5729 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[520] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5734 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[520] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5738 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[521] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5743 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[521] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5747 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[522] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5752 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[522] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5756 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[523] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5761 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[523] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5765 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[524] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5770 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[524] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5774 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[525] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5779 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[525] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5783 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[526] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5788 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[526] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5792 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[527] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5797 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[527] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5801 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[528] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5806 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[528] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5810 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[529] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5815 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[529] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5819 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[530] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5824 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[530] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5828 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[531] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5833 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[531] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5837 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[532] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5842 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[532] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5846 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[533] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5851 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[533] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5855 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[534] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5860 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[534] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5864 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[535] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5869 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[535] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5873 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[536] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5878 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[536] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5882 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[537] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5887 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[537] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5891 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[538] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5896 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[538] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5900 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[539] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5905 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[539] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5909 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[540] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5914 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[540] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5918 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[541] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5923 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[541] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5927 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[542] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5932 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[542] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5936 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[543] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5941 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[543] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5945 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[544] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5950 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[544] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5954 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[545] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5959 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[545] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5963 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[546] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5968 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[546] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5972 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[547] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5977 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[547] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5981 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[548] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5986 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[548] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5990 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[549] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5995 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[549] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5999 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[550] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6004 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[550] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6008 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[551] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6013 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[551] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6017 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[552] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6022 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[552] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6026 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[553] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6031 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[553] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6035 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[554] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6040 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[554] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6044 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[555] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6049 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[555] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6053 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[556] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6058 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[556] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6062 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[557] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6067 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[557] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6071 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[558] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6076 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[558] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6080 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[559] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6085 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[559] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6089 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[560] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6094 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[560] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6098 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[561] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6103 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[561] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6107 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[562] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6112 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[562] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6116 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[563] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6121 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[563] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6125 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[564] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6130 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[564] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6134 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[565] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6139 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[565] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6143 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[566] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6148 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[566] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6152 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[567] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6157 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[567] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6161 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[568] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6166 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[568] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6170 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[569] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6175 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[569] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6179 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[570] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6184 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[570] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6188 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[571] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6193 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[571] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6197 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[572] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6202 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[572] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6206 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[573] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6211 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[573] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6215 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[574] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6220 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[574] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6224 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[575] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6229 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[575] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6233 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[576] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6238 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[576] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6242 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[577] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6247 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[577] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6251 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[578] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6256 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[578] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6260 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[579] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6265 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[579] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6269 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[512] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6274 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[512] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6278 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[513] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6283 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[513] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6287 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[514] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6292 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[514] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6296 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[515] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6301 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[515] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6314 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6317 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6320 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[9] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6323 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !coreFix_memExe_lsq$getHit[9] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6326 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[8] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6329 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !coreFix_memExe_lsq$getHit[8] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6332 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[8] && + coreFix_memExe_lsq$getHit[0] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6335 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[8] && + !coreFix_memExe_lsq$getHit[0] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6340 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2 && + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6343 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2 && + !SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638 ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6349 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[516] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6352 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[516] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6355 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[517] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6358 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[517] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6361 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[518] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6364 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[518] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6367 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[519] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6370 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[519] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6373 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[520] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6376 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[520] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6379 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[521] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6382 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[521] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6385 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[522] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6388 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[522] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6391 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[523] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6394 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[523] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6397 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[524] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6400 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[524] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6403 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[525] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6406 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[525] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6409 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[526] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6412 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[526] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6415 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[527] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6418 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[527] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6421 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[528] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6424 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[528] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6427 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[529] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6430 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[529] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6433 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[530] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6436 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[530] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6439 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[531] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6442 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[531] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6445 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[532] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6448 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[532] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6451 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[533] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6454 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[533] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6457 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[534] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6460 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[534] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6463 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[535] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6466 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[535] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6469 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[536] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6472 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[536] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6475 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[537] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6478 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[537] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6481 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[538] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6484 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[538] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6487 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[539] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6490 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[539] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6493 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[540] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6496 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[540] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6499 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[541] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6502 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[541] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6505 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[542] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6508 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[542] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6511 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[543] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6514 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[543] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6517 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[544] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6520 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[544] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6523 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[545] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6526 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[545] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6529 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[546] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6532 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[546] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6535 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[547] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6538 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[547] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6541 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[548] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6544 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[548] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6547 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[549] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6550 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[549] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6553 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[550] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6556 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[550] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6559 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[551] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6562 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[551] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6565 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[552] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6568 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[552] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6571 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[553] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6574 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[553] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6577 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[554] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6580 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[554] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6583 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[555] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6586 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[555] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6589 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[556] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6592 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[556] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6595 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[557] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6598 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[557] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6601 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[558] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6604 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[558] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6607 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[559] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6610 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[559] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6613 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[560] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6616 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[560] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6619 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[561] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6622 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[561] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6625 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[562] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6628 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[562] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6631 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[563] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6634 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[563] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6637 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[564] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6640 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[564] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6643 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[565] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6646 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[565] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6649 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[566] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6652 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[566] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6655 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[567] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6658 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[567] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6661 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[568] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6664 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[568] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6667 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[569] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6670 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[569] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6673 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[570] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6676 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[570] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6679 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[571] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6682 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[571] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6685 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[572] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6688 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[572] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6691 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[573] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6694 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[573] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6697 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[574] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6700 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[574] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6703 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[575] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6706 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[575] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6709 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[576] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6712 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[576] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6715 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[577] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6718 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[577] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6721 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[578] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6724 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[578] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6727 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[579] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6730 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[579] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6733 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[512] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6736 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[512] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6739 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[513] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6742 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[513] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6745 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[514] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6748 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[514] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6751 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + coreFix_memExe_stb$deq[515] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6754 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1 && + !coreFix_memExe_stb$deq[515] ; + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6940 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[521:520] <= coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ; - assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] == - coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:14] ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[78] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[78]) ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[77] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[77]) ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[76] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[76]) ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2806 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[75] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[75]) ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[74] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[74]) ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[73] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[73]) ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[72] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[72]) ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[71] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[71]) ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[2] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[2]) ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[1] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[1]) ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[0] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[0]) ; - assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3337 = - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305 || - (!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT || - !EN_dCacheToParent_rqToP_deq && - !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl) && - coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full ; - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3433 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 || - (!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT || - !EN_dCacheToParent_rsToP_deq && - !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl) && - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full ; - assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1907 = - coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT && - coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] || - (!coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT || - !coreFix_memExe_dMem_perfReqQ_deqReq_rl) && - coreFix_memExe_dMem_perfReqQ_full ; - assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 = - coreFix_memExe_dTlb$procResp[174:114] < 61'd402653184 ; - assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1723 = - coreFix_memExe_dTlb$procResp[174:114] < 61'd536870912 ; - assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 = - coreFix_memExe_dTlb$procResp[174:114] == mmio_toHostAddr ; - assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1730 = - coreFix_memExe_dTlb$procResp[174:114] == mmio_fromHostAddr ; - assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731 = - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 || - !coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1723 || - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 || - coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1730 ; - assign coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3755 = - coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724 || - (!coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT || - !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && - !coreFix_memExe_forwardQ_deqReq_rl) && - coreFix_memExe_forwardQ_full ; - assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3661 = - coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630 || - (!coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT || - !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && - !coreFix_memExe_memRespLdQ_deqReq_rl) && - coreFix_memExe_memRespLdQ_full ; - assign coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4 = - coreFix_memExe_regToExeQ$first[189:158] ; - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[78] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[78]) ; - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[77] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[77]) ; - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[76] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[76]) ; - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[75] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[75]) ; - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[74] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[74]) ; - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[73] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[73]) ; - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[72] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[72]) ; - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[71] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[71]) ; - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[2] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[2]) ; - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[1] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[1]) ; - assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT && - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[0] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[0]) ; - assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3570 = - coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3554 || - (!coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT || - !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && - !coreFix_memExe_respLrScAmoQ_deqReq_rl) && - coreFix_memExe_respLrScAmoQ_full ; - assign coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14366 = + assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6943 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:522] == + coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:13] ; + assign coreFix_memExe_dTlb_procResp__239_BITS_141_TO__ETC___d4529 = + coreFix_memExe_dTlb$procResp[141:78] < + coreFix_memExe_dTlb$procResp[276:213] ; + assign coreFix_memExe_dTlb_procResp__239_BITS_141_TO__ETC___d4570 = + coreFix_memExe_dTlb_procResp__239_BITS_141_TO__ETC___d4529 || + (coreFix_memExe_dTlb$procResp[12] ? + !coreFix_memExe_dTlb_procResp__239_BITS_77_TO_1_ETC___d4531 : + !coreFix_memExe_dTlb_procResp__239_BITS_77_TO_1_ETC___d4532) ; + assign coreFix_memExe_dTlb_procResp__239_BITS_334_TO__ETC___d4402 = + coreFix_memExe_dTlb$procResp[334:329] < 6'd51 && + coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389[64:63] - + { 1'd0, x__h254848 } > + 2'd1 ; + assign coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389 = + { coreFix_memExe_dTlb$procResp[452:401] & mask__h254681, + 14'd0 } + + addTop__h254680 ; + assign coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4539 = + coreFix_memExe_dTlb$procResp[560:500] < 61'd402653184 ; + assign coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4540 = + coreFix_memExe_dTlb$procResp[560:500] < 61'd536870912 ; + assign coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4544 = + coreFix_memExe_dTlb$procResp[560:500] == mmio_toHostAddr ; + assign coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4547 = + coreFix_memExe_dTlb$procResp[560:500] == mmio_fromHostAddr ; + assign coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4548 = + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4539 || + !coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4540 || + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4544 || + coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4547 ; + assign coreFix_memExe_dTlb_procResp__239_BITS_77_TO_1_ETC___d4531 = + coreFix_memExe_dTlb$procResp[77:13] <= + coreFix_memExe_dTlb$procResp[212:148] ; + assign coreFix_memExe_dTlb_procResp__239_BITS_77_TO_1_ETC___d4532 = + coreFix_memExe_dTlb$procResp[77:13] < + coreFix_memExe_dTlb$procResp[212:148] ; + assign coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q4 = + coreFix_memExe_dTlb$procResp[292:291] ; + assign coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q5 = + coreFix_memExe_dTlb$procResp[450:401] + + ({ {48{coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q4[1]}}, + coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q4 } << + coreFix_memExe_dTlb$procResp[334:329]) ; + assign coreFix_memExe_dispToRegQ_first__680_BIT_101_6_ETC___d3567 = + { coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3531, + (coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3539 : + 2'd0, + IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3566 } ; + assign coreFix_memExe_dispToRegQ_first__680_BIT_101_6_ETC___d3569 = + { coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0 && + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3397, + (coreFix_memExe_dispToRegQ$first[101] && + coreFix_memExe_dispToRegQ$first[100:94] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3405 : + 66'd0, + IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3568 } ; + assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4232 = + { coreFix_memExe_lsq$getOrigBE << pointer__h242569[3:0], + (highOffsetBits__h242578 == 50'd0 && + IF_SEXT_coreFix_memExe_regToExeQ_first__633_BI_ETC___d4077 || + coreFix_memExe_regToExeQ$first[264:259] >= 6'd50) && + coreFix_memExe_regToExeQ$first[383], + result_d_address__h242780, + x__h248052[13:0], + coreFix_memExe_regToExeQ$first[302:231], + repBound__h248150, + coreFix_memExe_regToExeQ_first__633_BITS_258_T_ETC___d4092, + coreFix_memExe_regToExeQ_first__633_BITS_244_T_ETC___d4093, + coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4105, + IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4231 } ; + assign coreFix_memExe_regToExeQ_first__633_BITS_101_T_ETC___d3767 = + coreFix_memExe_regToExeQ$first[101:96] < 6'd51 && + coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754[64:63] - + { 1'd0, x__h241239 } > + 2'd1 ; + assign coreFix_memExe_regToExeQ_first__633_BITS_139_T_ETC___d4052 = + { coreFix_memExe_regToExeQ$first[139:124], + coreFix_memExe_regToExeQ$first[122:121], + coreFix_memExe_regToExeQ$first[123], + ~coreFix_memExe_regToExeQ$first[120:102], + IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[25:17], + ~IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[16:15], + IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[14:3], + ~IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[2], + IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[1:0], + coreFix_memExe_regToExeQ$first[217:154] } << + x__h244610 ; + assign coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754 = + { coreFix_memExe_regToExeQ$first[219:168] & mask__h241072, + 14'd0 } + + addTop__h241071 ; + assign coreFix_memExe_regToExeQ_first__633_BITS_244_T_ETC___d4093 = + coreFix_memExe_regToExeQ$first[244:242] < repBound__h248150 ; + assign coreFix_memExe_regToExeQ_first__633_BITS_258_T_ETC___d4092 = + coreFix_memExe_regToExeQ$first[258:256] < repBound__h248150 ; + assign coreFix_memExe_regToExeQ_first__633_BITS_264_T_ETC___d3705 = + coreFix_memExe_regToExeQ$first[264:259] < 6'd51 && + coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692[64:63] - + { 1'd0, x__h240082 } > + 2'd1 ; + assign coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692 = + { coreFix_memExe_regToExeQ$first[382:331] & mask__h239915, + 14'd0 } + + addTop__h239914 ; + assign coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4095 = + x__h248052[13:11] < repBound__h248150 ; + assign coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4105 = + { coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4095, + (coreFix_memExe_regToExeQ_first__633_BITS_258_T_ETC___d4092 == + coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4095) ? + 2'd0 : + ((coreFix_memExe_regToExeQ_first__633_BITS_258_T_ETC___d4092 && + !coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4095) ? + 2'd1 : + 2'd3), + (coreFix_memExe_regToExeQ_first__633_BITS_244_T_ETC___d4093 == + coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4095) ? + 2'd0 : + ((coreFix_memExe_regToExeQ_first__633_BITS_244_T_ETC___d4093 && + !coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4095) ? + 2'd1 : + 2'd3) } ; + assign coreFix_memExe_regToExeQfirst_BITS_217_TO_168_ETC__q7 = + coreFix_memExe_regToExeQ$first[217:168] + + ({ {48{coreFix_memExe_regToExeQfirst_BITS_59_TO_58__q6[1]}}, + coreFix_memExe_regToExeQfirst_BITS_59_TO_58__q6 } << + coreFix_memExe_regToExeQ$first[101:96]) ; + assign coreFix_memExe_regToExeQfirst_BITS_222_TO_221__q2 = + coreFix_memExe_regToExeQ$first[222:221] ; + assign coreFix_memExe_regToExeQfirst_BITS_380_TO_331_ETC__q3 = + coreFix_memExe_regToExeQ$first[380:331] + + ({ {48{coreFix_memExe_regToExeQfirst_BITS_222_TO_221__q2[1]}}, + coreFix_memExe_regToExeQfirst_BITS_222_TO_221__q2 } << + coreFix_memExe_regToExeQ$first[264:259]) ; + assign coreFix_memExe_regToExeQfirst_BITS_433_TO_402__q16 = + coreFix_memExe_regToExeQ$first[433:402] ; + assign coreFix_memExe_regToExeQfirst_BITS_59_TO_58__q6 = + coreFix_memExe_regToExeQ$first[59:58] ; + assign coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d22800 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4053_BITS_186_TO_1_ETC___d14361 ; - assign csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12642 = - { csrf_debug_int_pend, - 2'b0, - csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3, - 1'd0, - csrf_external_int_en_vec_1 & csrf_external_int_pend_vec_1, - csrf_external_int_en_vec_0 & csrf_external_int_pend_vec_0 } ; - assign csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12647 = - { csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12642, - csrf_timer_int_en_vec_3 & csrf_timer_int_pend_vec_3, - 1'd0, - csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, - csrf_timer_int_en_vec_0 & csrf_timer_int_pend_vec_0 } ; - assign csrf_fs_reg_read__1491_EQ_0_2828_AND_fetchStag_ETC___d12874 = + NOT_rob_deqPort_0_deq_data__2022_BITS_469_TO_4_ETC___d22795 ; + assign cr_addrBits__h865333 = + INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? + x__h865509[13:0] : + coreFix_aluExe_1_regToExeQ$first[191:178] ; + assign cr_addrBits__h865881 = + INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? + x__h866057[13:0] : + coreFix_aluExe_1_regToExeQ$first[62:49] ; + assign cr_addrBits__h903814 = + INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? + x__h903990[13:0] : + coreFix_aluExe_0_regToExeQ$first[191:178] ; + assign cr_addrBits__h904362 = + INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? + x__h904538[13:0] : + coreFix_aluExe_0_regToExeQ$first[62:49] ; + assign cr_address__h865332 = + { 2'd0, coreFix_aluExe_1_regToExeQ$first[241:178] } ; + assign cr_address__h865880 = + { 2'd0, coreFix_aluExe_1_regToExeQ$first[112:49] } ; + assign cr_address__h903813 = + { 2'd0, coreFix_aluExe_0_regToExeQ$first[241:178] } ; + assign cr_address__h904361 = + { 2'd0, coreFix_aluExe_0_regToExeQ$first[112:49] } ; + assign cr_flags__h865335 = coreFix_aluExe_1_regToExeQ$first[287] ; + assign cr_flags__h865883 = coreFix_aluExe_1_regToExeQ$first[158] ; + assign cr_flags__h903816 = coreFix_aluExe_0_regToExeQ$first[287] ; + assign cr_flags__h904364 = coreFix_aluExe_0_regToExeQ$first[158] ; + assign cr_reserved__h865336 = coreFix_aluExe_1_regToExeQ$first[289:288] ; + assign cr_reserved__h865884 = coreFix_aluExe_1_regToExeQ$first[160:159] ; + assign cr_reserved__h903817 = coreFix_aluExe_0_regToExeQ$first[289:288] ; + assign cr_reserved__h904365 = coreFix_aluExe_0_regToExeQ$first[160:159] ; + assign csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126 = + csrf_ddc_reg[13:11] < repBound__h248675 ; + assign csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125 = + csrf_ddc_reg[27:25] < repBound__h248675 ; + assign csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4128 = + csrf_ddc_reg[85:83] < repBound__h248675 ; + assign csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4138 = + { csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4128, + (csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125 == + csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4128) ? + 2'd0 : + ((csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125 && + !csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4128) ? + 2'd1 : + 2'd3), + (csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126 == + csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4128) ? + 2'd0 : + ((csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126 && + !csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4128) ? + 2'd1 : + 2'd3) } ; + assign csrf_fs_reg_read__5969_EQ_0_0418_AND_fetchStag_ETC___d20452 = csrf_fs_reg == 2'd0 && - (fetchStage$pipelines_0_first[95] && - fetchStage$pipelines_0_first[94] || - fetchStage$pipelines_0_first[88] && - fetchStage$pipelines_0_first[87] || - fetchStage$pipelines_0_first[81] || - fetchStage$pipelines_0_first[75] && - fetchStage$pipelines_0_first[74]) || - fetchStage$pipelines_0_first[199:195] == 5'd13 && - (fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d12869 || - csrf_prv_reg_read__2633_ULT_IF_fetchStage_pipe_ETC___d12871) ; - assign csrf_fs_reg_read__1491_EQ_0_2828_AND_fetchStag_ETC___d13280 = - csrf_fs_reg == 2'd0 && - (fetchStage$pipelines_0_first[95] && - fetchStage$pipelines_0_first[94] || - fetchStage$pipelines_0_first[88] && - fetchStage$pipelines_0_first[87] || - fetchStage$pipelines_0_first[81] || - fetchStage$pipelines_0_first[75] && - fetchStage$pipelines_0_first[74]) || - fetchStage$pipelines_0_first[231:200] == 32'h10500073 && + (fetchStage$pipelines_0_first[180] && + fetchStage$pipelines_0_first[179:168] == 12'd3 && + fetchStage$pipelines_0_first[272:268] == 5'd17 || + fetchStage$pipelines_0_first[96] && + fetchStage$pipelines_0_first[95] || + fetchStage$pipelines_0_first[89] && + fetchStage$pipelines_0_first[88] || + fetchStage$pipelines_0_first[82] || + fetchStage$pipelines_0_first[76] && + fetchStage$pipelines_0_first[75]) || + fetchStage$pipelines_0_first[304:273] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_fs_reg_read__1491_EQ_0_2828_AND_fetchStag_ETC___d13547 = + assign csrf_fs_reg_read__5969_EQ_0_0418_AND_fetchStag_ETC___d21034 = csrf_fs_reg == 2'd0 && - (fetchStage$pipelines_1_first[95] && - fetchStage$pipelines_1_first[94] || - fetchStage$pipelines_1_first[88] && - fetchStage$pipelines_1_first[87] || - fetchStage$pipelines_1_first[81] || - fetchStage$pipelines_1_first[75] && - fetchStage$pipelines_1_first[74]) || - fetchStage$pipelines_1_first[231:200] == 32'h10500073 && + (fetchStage$pipelines_0_first[96] && + fetchStage$pipelines_0_first[95] || + fetchStage$pipelines_0_first[89] && + fetchStage$pipelines_0_first[88] || + fetchStage$pipelines_0_first[82] || + fetchStage$pipelines_0_first[76] && + fetchStage$pipelines_0_first[75]) || + fetchStage$pipelines_0_first[304:273] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 = - csrf_prv_reg_read__2633_ULE_1___d14189 && - (commitStage_commitTrap[4] ? - _0b0_CONCAT_csrf_mideleg_11_reg_read__1606_1607_ETC___d14209 : - _0b0_CONCAT_csrf_medeleg_15_reg_read__1598_1599_ETC___d14227) ; - assign csrf_prv_reg_read__2633_ULE_1___d14189 = csrf_prv_reg <= 2'd1 ; - assign csrf_prv_reg_read__2633_ULT_IF_fetchStage_pipe_ETC___d12871 = - csrf_prv_reg < - IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[9:8] ; - assign data72479_BITS_31_TO_0__q5 = data__h472479[31:0] ; - assign data___1__h472205 = - { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125[31]}}, - IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125 } ; - assign data___1__h473013 = - { {32{data72479_BITS_31_TO_0__q5[31]}}, - data72479_BITS_31_TO_0__q5 } ; - assign data__h472479 = + assign csrf_fs_reg_read__5969_EQ_0_0418_AND_fetchStag_ETC___d21467 = + csrf_fs_reg == 2'd0 && + (fetchStage$pipelines_1_first[96] && + fetchStage$pipelines_1_first[95] || + fetchStage$pipelines_1_first[89] && + fetchStage$pipelines_1_first[88] || + fetchStage$pipelines_1_first[82] || + fetchStage$pipelines_1_first[76] && + fetchStage$pipelines_1_first[75]) || + fetchStage$pipelines_1_first[304:273] == 32'h10500073 && + csrf_tw_reg && + csrf_prv_reg != 2'd3 ; + assign csrf_mtcc_reg_read__6624_BITS_149_TO_86_2579_A_ETC___d22582 = + csrf_mtcc_reg[149:86] & mask__h997264 ; + assign csrf_mtcc_reg_read__6624_BITS_149_TO_86_2579_A_ETC___d22589 = + newAddrDiff__h997265 == mask__h997264 ; + assign csrf_mtcc_reg_read__6624_BITS_149_TO_86_2579_A_ETC___d22622 = + newAddrDiff__h997609 == mask__h997264 ; + assign csrf_mtcc_reg_read__6624_BITS_85_TO_83_2597_UL_ETC___d22600 = + csrf_mtcc_reg[85:83] < repBound__h997416 ; + assign csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 = + csrf_prv_reg_read__0075_ULE_1___d22375 && + ((commitStage_commitTrap[44:43] == 2'd1) ? + _0b0_CONCAT_csrf_medeleg_15_reg_read__6063_6064_ETC___d22403 : + commitStage_commitTrap[44:43] != 2'd0 && + _0b0_CONCAT_csrf_mideleg_11_reg_read__6071_6072_ETC___d22405) ; + assign csrf_prv_reg_read__0075_ULE_1___d22375 = csrf_prv_reg <= 2'd1 ; + assign csrf_rg_dcsr_read__6184_BIT_2_0464_OR_NOT_fetc_ETC___d21029 = + csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || + fetchStage$RDY_pipelines_0_first && + IF_fetchStage_RDY_pipelines_0_first__0042_AND__ETC___d20964 ; + assign csrf_stcc_reg_read__6615_BITS_149_TO_86_2502_A_ETC___d22505 = + csrf_stcc_reg[149:86] & mask__h996607 ; + assign csrf_stcc_reg_read__6615_BITS_149_TO_86_2502_A_ETC___d22514 = + newAddrDiff__h996608 == mask__h996607 ; + assign csrf_stcc_reg_read__6615_BITS_149_TO_86_2502_A_ETC___d22547 = + newAddrDiff__h996952 == mask__h996607 ; + assign csrf_stcc_reg_read__6615_BITS_85_TO_83_2522_UL_ETC___d22525 = + csrf_stcc_reg[85:83] < repBound__h996759 ; + assign data05760_BITS_31_TO_0__q25 = data__h705760[31:0] ; + assign data___1__h705460 = + { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q144[31]}}, + IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q144 } ; + assign data___1__h706320 = + { {32{data05760_BITS_31_TO_0__q25[31]}}, + data05760_BITS_31_TO_0__q25 } ; + assign data__h567607 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? + res_data__h568170 : + res_data__h568165 ; + assign data__h613367 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? + res_data__h613924 : + res_data__h613919 ; + assign data__h659114 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? + res_data__h659671 : + res_data__h659666 ; + assign data__h704928 = + coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? + data___1__h705460 : + IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d12190 ; + assign data__h705760 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h472393 : - x_remainder__h472394 ; - assign din_inc___2_exp__h378444 = _theResult___fst_exp__h351411 + 8'd1 ; - assign din_inc___2_exp__h378468 = _theResult___fst_exp__h360067 + 8'd1 ; - assign din_inc___2_exp__h378498 = _theResult___fst_exp__h369177 + 8'd1 ; - assign din_inc___2_exp__h378522 = _theResult___fst_exp__h377862 + 8'd1 ; - assign din_inc___2_exp__h424134 = _theResult___fst_exp__h397101 + 8'd1 ; - assign din_inc___2_exp__h424158 = _theResult___fst_exp__h405757 + 8'd1 ; - assign din_inc___2_exp__h424188 = _theResult___fst_exp__h414867 + 8'd1 ; - assign din_inc___2_exp__h424212 = _theResult___fst_exp__h423552 + 8'd1 ; - assign din_inc___2_exp__h469822 = _theResult___fst_exp__h442789 + 8'd1 ; - assign din_inc___2_exp__h469846 = _theResult___fst_exp__h451445 + 8'd1 ; - assign din_inc___2_exp__h469876 = _theResult___fst_exp__h460555 + 8'd1 ; - assign din_inc___2_exp__h469900 = _theResult___fst_exp__h469240 + 8'd1 ; - assign din_inc___2_exp__h517924 = _theResult___fst_exp__h498674 + 11'd1 ; - assign din_inc___2_exp__h517959 = _theResult___fst_exp__h508251 + 11'd1 ; - assign din_inc___2_exp__h517985 = _theResult___fst_exp__h517084 + 11'd1 ; - assign din_inc___2_exp__h556725 = _theResult___fst_exp__h537475 + 11'd1 ; - assign din_inc___2_exp__h556760 = _theResult___fst_exp__h547052 + 11'd1 ; - assign din_inc___2_exp__h556786 = _theResult___fst_exp__h555885 + 11'd1 ; - assign din_inc___2_exp__h595926 = _theResult___fst_exp__h576676 + 11'd1 ; - assign din_inc___2_exp__h595961 = _theResult___fst_exp__h586253 + 11'd1 ; - assign din_inc___2_exp__h595987 = _theResult___fst_exp__h595086 + 11'd1 ; - assign enabled_ints___1__h645893 = pend_ints__h645394 & y__h645905 ; - assign enabled_ints__h645940 = - pend_ints__h645394 & - { r1__read_BITS_12_TO_0___h645916, csrf_mideleg_1_0_reg } ; - assign fcsr_csr__read__h606149 = { 56'd0, x__h608823 } ; - assign fetchStage_RDY_pipelines_0_first__2602_AND_NOT_ETC___d13210 = - fetchStage$RDY_pipelines_0_first && - (fetchStage$pipelines_0_first[194:192] != 3'd1 || - specTagManager$canClaim) && - regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207 ; - assign fetchStage_RDY_pipelines_0_first__2602_AND_fet_ETC___d13277 = - fetchStage$RDY_pipelines_0_first && - fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13272 || - !fetchStage$pipelines_0_canDeq || - fetchStage$RDY_pipelines_0_first && - IF_fetchStage_RDY_pipelines_0_first__2602_AND__ETC___d13214 ; - assign fetchStage_RDY_pipelines_1_deq__2617_AND_NOT_f_ETC___d13816 = - fetchStage$RDY_pipelines_1_deq && + x_quotient__h705674 : + x_remainder__h705675 ; + assign data__h705791 = + coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? + data___1__h706320 : + data__h705760 ; + assign data_addrBits__h1013046 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; + assign data_addrBits__h1013900 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; + assign data_address__h1013045 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; + assign data_address__h1013899 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; + assign dcsr_cause__h991471 = + (commitStage_commitTrap[44:43] != 2'd0 && + commitStage_commitTrap[44:43] != 2'd1 && + commitStage_commitTrap[35:32] == 4'd14) ? + 3'd3 : + ((commitStage_commitTrap[44:43] != 2'd0 && + commitStage_commitTrap[44:43] != 2'd1 && + commitStage_commitTrap[35:32] != 4'd0 && + commitStage_commitTrap[35:32] != 4'd1 && + commitStage_commitTrap[35:32] != 4'd3 && + commitStage_commitTrap[35:32] != 4'd4 && + commitStage_commitTrap[35:32] != 4'd5 && + commitStage_commitTrap[35:32] != 4'd7 && + commitStage_commitTrap[35:32] != 4'd8 && + commitStage_commitTrap[35:32] != 4'd9 && + commitStage_commitTrap[35:32] != 4'd11 && + commitStage_commitTrap[35:32] != 4'd14) ? + 3'd4 : + 3'd1) ; + assign din_inc___2_exp__h611525 = _theResult___fst_exp__h584492 + 8'd1 ; + assign din_inc___2_exp__h611549 = _theResult___fst_exp__h593148 + 8'd1 ; + assign din_inc___2_exp__h611579 = _theResult___fst_exp__h602258 + 8'd1 ; + assign din_inc___2_exp__h611603 = _theResult___fst_exp__h610943 + 8'd1 ; + assign din_inc___2_exp__h657274 = _theResult___fst_exp__h630241 + 8'd1 ; + assign din_inc___2_exp__h657298 = _theResult___fst_exp__h638897 + 8'd1 ; + assign din_inc___2_exp__h657328 = _theResult___fst_exp__h648007 + 8'd1 ; + assign din_inc___2_exp__h657352 = _theResult___fst_exp__h656692 + 8'd1 ; + assign din_inc___2_exp__h703021 = _theResult___fst_exp__h675988 + 8'd1 ; + assign din_inc___2_exp__h703045 = _theResult___fst_exp__h684644 + 8'd1 ; + assign din_inc___2_exp__h703075 = _theResult___fst_exp__h693754 + 8'd1 ; + assign din_inc___2_exp__h703099 = _theResult___fst_exp__h702439 + 8'd1 ; + assign din_inc___2_exp__h753463 = _theResult___fst_exp__h734213 + 11'd1 ; + assign din_inc___2_exp__h753498 = _theResult___fst_exp__h743790 + 11'd1 ; + assign din_inc___2_exp__h753524 = _theResult___fst_exp__h752623 + 11'd1 ; + assign din_inc___2_exp__h792316 = _theResult___fst_exp__h773066 + 11'd1 ; + assign din_inc___2_exp__h792351 = _theResult___fst_exp__h782643 + 11'd1 ; + assign din_inc___2_exp__h792377 = _theResult___fst_exp__h791476 + 11'd1 ; + assign din_inc___2_exp__h831620 = _theResult___fst_exp__h812370 + 11'd1 ; + assign din_inc___2_exp__h831655 = _theResult___fst_exp__h821947 + 11'd1 ; + assign din_inc___2_exp__h831681 = _theResult___fst_exp__h830780 + 11'd1 ; + assign enabled_ints___1__h918214 = pend_ints__h917687 & y__h918226 ; + assign enabled_ints__h918260 = + pend_ints__h917687 & + { r1__read_BITS_13_TO_0___h918236, csrf_mideleg_1_0_reg } ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d21405 = + epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3181_3271_OR_NOT__ETC___d13812) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; - assign fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13758 = + (fetchStage$pipelines_0_first[267:265] != 3'd1 || + specTagManager$canClaim) && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21010 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20996) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d21553 = + epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && + (!fetchStage$pipelines_0_canDeq || + (fetchStage$pipelines_0_first[267:265] != 3'd1 || + specTagManager$canClaim) && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21010 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21549) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d21572 = + epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && + (!fetchStage$pipelines_0_canDeq || + (fetchStage$pipelines_0_first[267:265] != 3'd1 || + specTagManager$canClaim) && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21010 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21568) ; + assign f1_exp14825_MINUS_127__q147 = f1_exp__h714825 - 8'd127 ; + assign f1_exp__h714825 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : + 8'd255 ; + assign f1_sfd__h714826 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : + 23'd4194304 ; + assign f2_exp53819_MINUS_127__q187 = f2_exp__h753819 - 8'd127 ; + assign f2_exp__h753819 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : + 8'd255 ; + assign f2_sfd__h753820 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : + 23'd4194304 ; + assign f3_exp93123_MINUS_127__q164 = f3_exp__h793123 - 8'd127 ; + assign f3_exp__h793123 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : + 8'd255 ; + assign f3_sfd__h793124 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : + 23'd4194304 ; + assign f_csr_rsps_i_notFull__3520_AND_f_csr_reqs_firs_ETC___d23615 = + f_csr_rsps$FULL_N && + (f_csr_reqs$D_OUT[75:64] != 12'd2049 || + csrf_stats_module_writeQ$FULL_N) && + (f_csr_reqs$D_OUT[75:64] != 12'd2048 || + csrf_terminate_module_terminateQ$FULL_N) ; + assign fcsr_csr__read__h849070 = { 56'd0, x__h852553 } ; + assign fetchStage_RDY_pipelines_0_deq__0048_AND_regRe_ETC___d20817 = + fetchStage$RDY_pipelines_0_deq && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[267:265] != 3'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 && + fetchStage$pipelines_0_first[237:236] != 2'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign fetchStage_pipelines_0_canDeq__0043_AND_NOT_fe_ETC___d21696 = fetchStage$pipelines_0_canDeq && - (fetchStage$pipelines_0_first[194:192] != 3'd1 || + (fetchStage$pipelines_0_first[267:265] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258 && - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13502 || - !coreFix_aluExe_0_rsAlu$canEnq || - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13757 ; - assign fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837 = - fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13834 && - (fetchStage$pipelines_0_first[194:192] == 3'd0 || - fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 ; - assign fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13924 = - fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13834 && - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13502 || + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21010 && + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21418 || !coreFix_aluExe_0_rsAlu$canEnq || (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13919 || - fetchStage$pipelines_0_first[194:192] != 3'd0 && - fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227) && + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21692) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign fetchStage_pipelines_0_canDeq__2603_AND_fetchS_ETC___d13826 = + !coreFix_aluExe_0_rsAlu_approximateCount__0973__ETC___d20975 ; + assign fetchStage_pipelines_0_canDeq__0043_AND_NOT_fe_ETC___d21862 = fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13709 || + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21775 && + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21418 || + !coreFix_aluExe_0_rsAlu$canEnq ; + assign fetchStage_pipelines_0_canDeq__0043_AND_fetchS_ETC___d21766 = + fetchStage$pipelines_0_canDeq && + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21640 || !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && - (fetchStage_pipelines_1_first__2614_BITS_194_TO_ETC___d13720 || - NOT_regRenamingTable_rename_1_canRename__3307__ETC___d13726 || - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13822) && - IF_fetchStage_RDY_pipelines_1_first__2613_AND__ETC___d13653 ; - assign fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13764 = + (fetchStage_pipelines_1_first__0054_BITS_267_TO_ETC___d21651 || + !regRenamingTable$rename_1_canRename || + fetchStage_pipelines_1_first__0054_BITS_272_TO_ETC___d21663 || + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21762) && + IF_fetchStage_RDY_pipelines_1_first__0053_AND__ETC___d21583 ; + assign fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21702 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258 && - (fetchStage$pipelines_0_first[194:192] == 3'd3 || - fetchStage$pipelines_0_first[194:192] == 3'd4) ; - assign fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13771 = + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21010 && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 && + (fetchStage$pipelines_0_first[267:265] == 3'd3 || + fetchStage$pipelines_0_first[267:265] == 3'd4) ; + assign fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21709 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258 && - fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 || + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21010 && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 && + fetchStage$pipelines_0_first[267:265] == 3'd2 && + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 || !coreFix_memExe_rsMem$canEnq || - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ; - assign fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13792 = - fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13764 || + CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q264 ; + assign fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21731 = + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21702 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || fetchStage$pipelines_0_canDeq && - (fetchStage$pipelines_0_first[194:192] == 3'd1 && + (fetchStage$pipelines_0_first[267:265] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13287 || - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13784) ; - assign fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13803 = - fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13771 || + NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21514 || + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21722) ; + assign fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21743 = + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21709 || fetchStage$pipelines_0_canDeq && - (fetchStage$pipelines_0_first[194:192] == 3'd1 && + (fetchStage$pipelines_0_first[267:265] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13287 || - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13795) ; - assign fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d14029 = + NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21514 || + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21734) ; + assign fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21993 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d14027 || + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21991 || !coreFix_memExe_rsMem$canEnq || - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ; - assign fetchStage_pipelines_0_canDeq__2603_AND_specTa_ETC___d13889 = + CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q264 ; + assign fetchStage_pipelines_0_canDeq__0043_AND_specTa_ETC___d21836 = fetchStage$pipelines_0_canDeq && specTagManager$canClaim && regRenamingTable$rename_0_canRename && - !checkForException___d12839[4] && + !checkForException___d20432[13] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 && - fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d12869 = - (fetchStage$pipelines_0_first[194:192] == 3'd0 && - fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h649451 != 5'd0 || - imm__h649452 != 32'd0) && - IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[11:10] == - 2'b11 ; - assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13502 = - (fetchStage$pipelines_0_first[194:192] == 3'd0 || - fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21020 && + fetchStage$pipelines_0_first[267:265] == 3'd1 ; + assign fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21418 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 && (!coreFix_aluExe_1_rsAlu$canEnq || - coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223) ; - assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13523 = - fetchStage$pipelines_0_first[194:192] == 3'd1 && + coreFix_aluExe_0_rsAlu_approximateCount__0973__ETC___d20975) ; + assign fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21424 = + (fetchStage$pipelines_0_first[267:265] == 3'd0 || + fetchStage$pipelines_0_first[267:265] == 3'd1 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1) && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 && + (!coreFix_aluExe_0_rsAlu$canEnq || + !coreFix_aluExe_0_rsAlu_approximateCount__0973__ETC___d20975) ; + assign fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21442 = + fetchStage$pipelines_0_first[267:265] == 3'd1 && + !specTagManager$canClaim || + NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21434 || + fetchStage$pipelines_0_first[267:265] != 3'd0 && + fetchStage$pipelines_0_first[267:265] != 3'd1 && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 ; + assign fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21634 = + fetchStage$pipelines_0_first[267:265] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2605_BITS_199_TO_ETC___d13516 || - fetchStage$pipelines_0_first[194:192] != 3'd0 && - fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 ; - assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13595 = - fetchStage$pipelines_0_first[194:192] == 3'd1 && - !specTagManager$canClaim || - fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[12] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[13] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[14] ; - assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13703 = - fetchStage$pipelines_0_first[194:192] == 3'd1 && - !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13668 || - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13692 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13701 ; - assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13709 = - fetchStage$pipelines_0_first[194:192] == 3'd1 && - !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13668 || - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13708 ; - assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13731 = - fetchStage$pipelines_0_first[194:192] == 3'd1 && + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21598 || + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21623 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21632 ; + assign fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21640 = + fetchStage$pipelines_0_first[267:265] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2605_BITS_199_TO_ETC___d13516 || - fetchStage$pipelines_0_first[194:192] != 3'd0 && - fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 || - coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13738 = - fetchStage$pipelines_0_first[194:192] == 3'd1 && + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21598 || + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21639 ; + assign fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21657 = + fetchStage$pipelines_0_first[267:265] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2605_BITS_199_TO_ETC___d13516 || - fetchStage$pipelines_0_first[194:192] != 3'd0 && - fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 || - coreFix_aluExe_0_rsAlu$canEnq && - coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13919 = - fetchStage$pipelines_0_first[194:192] == 3'd1 && + fetchStage$pipelines_0_first[69] || + checkForException___d20432[13] || + !rob$enqPort_0_canEnq || + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21639 ; + assign fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21692 = + fetchStage$pipelines_0_first[267:265] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage$pipelines_0_first[68] || - checkForException___d12839[4] || - !rob$enqPort_0_canEnq ; - assign fetchStage_pipelines_0_first__2605_BITS_199_TO_ETC___d13516 = - fetchStage$pipelines_0_first[199:195] == 5'd0 || - fetchStage$pipelines_0_first[199:195] == 5'd21 || - fetchStage$pipelines_0_first[199:195] == 5'd17 || - fetchStage$pipelines_0_first[199:195] == 5'd18 || - fetchStage$pipelines_0_first[199:195] == 5'd13 || - fetchStage$pipelines_0_first[199:195] == 5'd16 || - fetchStage$pipelines_0_first[199:195] == 5'd15 || - fetchStage$pipelines_0_first[199:195] == 5'd19 || - fetchStage$pipelines_0_first[199:195] == 5'd20 || - fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d13513 || + fetchStage_pipelines_0_first__0045_BITS_272_TO_ETC___d21041 || + fetchStage$pipelines_0_first[267:265] != 3'd0 && + fetchStage$pipelines_0_first[267:265] != 3'd1 && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 ; + assign fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21872 = + fetchStage$pipelines_0_first[267:265] == 3'd1 && + !specTagManager$canClaim || + NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21870 || + fetchStage$pipelines_0_first[267:265] != 3'd0 && + fetchStage$pipelines_0_first[267:265] != 3'd1 && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 ; + assign fetchStage_pipelines_0_first__0045_BITS_272_TO_ETC___d21041 = + fetchStage$pipelines_0_first[272:268] == 5'd0 || + fetchStage$pipelines_0_first[272:268] == 5'd26 || + fetchStage$pipelines_0_first[272:268] == 5'd22 || + fetchStage$pipelines_0_first[272:268] == 5'd23 || + fetchStage$pipelines_0_first[272:268] == 5'd17 || + fetchStage$pipelines_0_first[272:268] == 5'd18 || + fetchStage$pipelines_0_first[272:268] == 5'd21 || + fetchStage$pipelines_0_first[272:268] == 5'd20 || + fetchStage$pipelines_0_first[272:268] == 5'd24 || + fetchStage$pipelines_0_first[272:268] == 5'd25 || + renameStage_rg_m_halt_req[4] || + fetchStage$pipelines_0_first[69] || + checkForException___d20432[13] || + csrf_fs_reg_read__5969_EQ_0_0418_AND_fetchStag_ETC___d21034 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_0_first__2605_BIT_68_2632_ETC___d13285 = - fetchStage$pipelines_0_first[68] || - checkForException___d12839[4] || - csrf_fs_reg_read__1491_EQ_0_2828_AND_fetchStag_ETC___d13280 || + assign fetchStage_pipelines_0_first__0045_BIT_167_037_ETC___d20394 = + { fetchStage$pipelines_0_first[167], + CASE_fetchStagepipelines_0_first_BITS_166_TO__ETC__q252 } ; + assign fetchStage_pipelines_0_first__0045_BIT_167_037_ETC___d20923 = + { fetchStage_pipelines_0_first__0045_BIT_167_037_ETC___d20394, + fetchStage_pipelines_0_first__0045_BIT_180_027_ETC___d20370, + 81'h12AA80000000000000000, + fetchStage$pipelines_0_first[495:333], + 5'd0, + (fetchStage$pipelines_0_first[180] && + fetchStage$pipelines_0_first[272:268] == 5'd17 && + (fetchStage$pipelines_0_first[179:168] == 12'd1 || + fetchStage$pipelines_0_first[179:168] == 12'd2 || + fetchStage$pipelines_0_first[179:168] == 12'd3)) ? + fetchStage$pipelines_0_first[267:265] == 3'd0 && + fetchStage$pipelines_0_first[242:238] == 5'd15 || + (!fetchStage$pipelines_0_first[89] || + fetchStage$pipelines_0_first[88] || + fetchStage$pipelines_0_first[87:83] != 5'd0) && + (!fetchStage$pipelines_0_first[161] || + fetchStage$pipelines_0_first[160:129] != 32'd0) : + fetchStage$pipelines_0_first[76] && + fetchStage$pipelines_0_first[75], + fetchStage$pipelines_0_first[267:265] != 3'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 && + fetchStage$pipelines_0_first[237:236] != 2'd0, + 13'h1521, + specTagManager$currentSpecBits } ; + assign fetchStage_pipelines_0_first__0045_BIT_180_027_ETC___d20370 = + { fetchStage$pipelines_0_first[180], + CASE_fetchStagepipelines_0_first_BITS_179_TO__ETC__q253 } ; + assign fetchStage_pipelines_0_first__0045_BIT_69_0074_ETC___d20559 = + fetchStage$pipelines_0_first[69] || + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] && + !IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15] && + (!checkForException___d20432[13] || + checkForException___d20432[12:11] == 2'd1) ; + assign fetchStage_pipelines_0_first__0045_BIT_69_0074_ETC___d21512 = + fetchStage$pipelines_0_first[69] || + checkForException___d20432[13] || + csrf_fs_reg_read__5969_EQ_0_0418_AND_fetchStag_ETC___d21034 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_1_first__2614_BITS_194_TO_ETC___d13720 = - fetchStage$pipelines_1_first[194:192] == 3'd1 && + assign fetchStage_pipelines_1_first__0054_BITS_267_TO_ETC___d21651 = + fetchStage$pipelines_1_first[267:265] == 3'd1 && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13717 || + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21648 || !specTagManager$canClaim) ; - assign fetchStage_pipelines_1_first__2614_BITS_199_TO_ETC___d13555 = - fetchStage$pipelines_1_first[199:195] == 5'd0 || - fetchStage$pipelines_1_first[199:195] == 5'd21 || - fetchStage$pipelines_1_first[199:195] == 5'd17 || - fetchStage$pipelines_1_first[199:195] == 5'd18 || - fetchStage$pipelines_1_first[199:195] == 5'd13 || - fetchStage$pipelines_1_first[199:195] == 5'd16 || - fetchStage$pipelines_1_first[199:195] == 5'd15 || - fetchStage$pipelines_1_first[199:195] == 5'd19 || - fetchStage$pipelines_1_first[199:195] == 5'd20 || - fetchStage$pipelines_1_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d13549 || - !rob$enqPort_1_canEnq || - !epochManager$checkEpoch_1_check || - !fetchStage$pipelines_0_canDeq || - fetchStage$RDY_pipelines_0_first && - IF_fetchStage_RDY_pipelines_0_first__2602_AND__ETC___d13214 ; - assign fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437 = - { fetchStage$pipelines_1_first[173], - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 } ; - assign fetchStage_pipelines_1_first__2614_BIT_68_3335_ETC___d13724 = - fetchStage$pipelines_1_first[68] || - checkForException___d13458[4] || - csrf_fs_reg_read__1491_EQ_0_2828_AND_fetchStag_ETC___d13547 || + assign fetchStage_pipelines_1_first__0054_BITS_267_TO_ETC___d21937 = + (fetchStage$pipelines_1_first[267:265] == 3'd3 || + fetchStage$pipelines_1_first[267:265] == 3'd4) && + (!fetchStage$pipelines_0_canDeq || + !regRenamingTable$rename_0_canRename || + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21598 || + fetchStage$pipelines_0_first[237:236] == 2'd0 || + fetchStage$pipelines_0_first[237:236] == 2'd1 || + fetchStage$pipelines_0_first[267:265] != 3'd3 && + fetchStage$pipelines_0_first[267:265] != 3'd4) && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; + assign fetchStage_pipelines_1_first__0054_BITS_272_TO_ETC___d21663 = + fetchStage$pipelines_1_first[272:268] == 5'd0 || + fetchStage$pipelines_1_first[272:268] == 5'd26 || + fetchStage$pipelines_1_first[272:268] == 5'd22 || + fetchStage$pipelines_1_first[272:268] == 5'd23 || + fetchStage$pipelines_1_first[272:268] == 5'd17 || + fetchStage$pipelines_1_first[272:268] == 5'd18 || + fetchStage$pipelines_1_first[272:268] == 5'd21 || + fetchStage$pipelines_1_first[272:268] == 5'd20 || + fetchStage$pipelines_1_first[272:268] == 5'd24 || + fetchStage$pipelines_1_first[272:268] == 5'd25 || + renameStage_rg_m_halt_req[4] || + fetchStage$pipelines_1_first[69] || + checkForException___d21369[13] || + csrf_fs_reg_read__5969_EQ_0_0418_AND_fetchStag_ETC___d21467 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || + csrf_rg_dcsr[2] || fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13709 ; - assign fflags__h705625 = - NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_fst__h705685 : - IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 ; - assign fflags_csr__read__h606124 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h606135 = { 61'd0, csrf_frm_reg } ; - assign guard__h343310 = - { IF_sfdin51405_BIT_33_THEN_2_ELSE_0__q21[1], - { sfdin__h351405[32:0], 23'd0 } != 56'd0 } ; - assign guard__h352019 = - { IF_theResult___snd60018_BIT_33_THEN_2_ELSE_0__q23[1], - { _theResult___snd__h360018[32:0], 23'd0 } != 56'd0 } ; - assign guard__h360949 = - { IF_sfdin69171_BIT_33_THEN_2_ELSE_0__q31[1], - { sfdin__h369171[32:0], 23'd0 } != 56'd0 } ; - assign guard__h361547 = x__h361649 != 57'd0 ; - assign guard__h369785 = - { IF_theResult___snd77808_BIT_33_THEN_2_ELSE_0__q36[1], - { _theResult___snd__h377808[32:0], 23'd0 } != 56'd0 } ; - assign guard__h389002 = - { IF_sfdin97095_BIT_33_THEN_2_ELSE_0__q56[1], - { sfdin__h397095[32:0], 23'd0 } != 56'd0 } ; - assign guard__h397709 = - { IF_theResult___snd05708_BIT_33_THEN_2_ELSE_0__q58[1], - { _theResult___snd__h405708[32:0], 23'd0 } != 56'd0 } ; - assign guard__h406639 = - { IF_sfdin14861_BIT_33_THEN_2_ELSE_0__q66[1], - { sfdin__h414861[32:0], 23'd0 } != 56'd0 } ; - assign guard__h407237 = x__h407339 != 57'd0 ; - assign guard__h415475 = - { IF_theResult___snd23498_BIT_33_THEN_2_ELSE_0__q71[1], - { _theResult___snd__h423498[32:0], 23'd0 } != 56'd0 } ; - assign guard__h434690 = - { IF_sfdin42783_BIT_33_THEN_2_ELSE_0__q91[1], - { sfdin__h442783[32:0], 23'd0 } != 56'd0 } ; - assign guard__h443397 = - { IF_theResult___snd51396_BIT_33_THEN_2_ELSE_0__q93[1], - { _theResult___snd__h451396[32:0], 23'd0 } != 56'd0 } ; - assign guard__h452327 = - { IF_sfdin60549_BIT_33_THEN_2_ELSE_0__q101[1], - { sfdin__h460549[32:0], 23'd0 } != 56'd0 } ; - assign guard__h452925 = x__h453027 != 57'd0 ; - assign guard__h461163 = - { IF_theResult___snd69186_BIT_33_THEN_2_ELSE_0__q106[1], - { _theResult___snd__h469186[32:0], 23'd0 } != 56'd0 } ; - assign guard__h490713 = - { IF_theResult___snd98625_BIT_4_THEN_2_ELSE_0__q127[1], - { _theResult___snd__h498625[3:0], 52'd0 } != 56'd0 } ; - assign guard__h500025 = - { IF_sfdin08245_BIT_4_THEN_2_ELSE_0__q131[1], - { sfdin__h508245[3:0], 52'd0 } != 56'd0 } ; - assign guard__h500623 = x__h500723 != 57'd0 ; - assign guard__h509094 = - { IF_theResult___snd17030_BIT_4_THEN_2_ELSE_0__q134[1], - { _theResult___snd__h517030[3:0], 52'd0 } != 56'd0 } ; - assign guard__h529514 = - { IF_theResult___snd37426_BIT_4_THEN_2_ELSE_0__q167[1], - { _theResult___snd__h537426[3:0], 52'd0 } != 56'd0 } ; - assign guard__h538826 = - { IF_sfdin47046_BIT_4_THEN_2_ELSE_0__q171[1], - { sfdin__h547046[3:0], 52'd0 } != 56'd0 } ; - assign guard__h539424 = x__h539524 != 57'd0 ; - assign guard__h547895 = - { IF_theResult___snd55831_BIT_4_THEN_2_ELSE_0__q174[1], - { _theResult___snd__h555831[3:0], 52'd0 } != 56'd0 } ; - assign guard__h568715 = - { IF_theResult___snd76627_BIT_4_THEN_2_ELSE_0__q144[1], - { _theResult___snd__h576627[3:0], 52'd0 } != 56'd0 } ; - assign guard__h578027 = - { IF_sfdin86247_BIT_4_THEN_2_ELSE_0__q148[1], - { sfdin__h586247[3:0], 52'd0 } != 56'd0 } ; - assign guard__h578625 = x__h578725 != 57'd0 ; - assign guard__h587096 = - { IF_theResult___snd95032_BIT_4_THEN_2_ELSE_0__q151[1], - { _theResult___snd__h595032[3:0], 52'd0 } != 56'd0 } ; - assign idx__h675477 = + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21657 ; + assign fetchStage_pipelines_1_first__0054_BIT_167_131_ETC___d21342 = + { fetchStage$pipelines_1_first[167], + CASE_fetchStagepipelines_1_first_BITS_166_TO__ETC__q262 } ; + assign fetchStage_pipelines_1_first__0054_BIT_180_122_ETC___d21318 = + { fetchStage$pipelines_1_first[180], + CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q258 } ; + assign fflags__h1010644 = + NOT_rob_deqPort_0_canDeq__3151_3152_OR_rob_deq_ETC___d23371 ? + y_avValue_snd_fst__h1010704 : + IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23378 ; + assign fflags_csr__read__h849045 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h849056 = { 61'd0, csrf_frm_reg } ; + assign guard__h576391 = + { IF_sfdin84486_BIT_33_THEN_2_ELSE_0__q40[1], + { sfdin__h584486[32:0], 23'd0 } != 56'd0 } ; + assign guard__h585100 = + { IF_theResult___snd93099_BIT_33_THEN_2_ELSE_0__q42[1], + { _theResult___snd__h593099[32:0], 23'd0 } != 56'd0 } ; + assign guard__h594030 = + { IF_sfdin02252_BIT_33_THEN_2_ELSE_0__q50[1], + { sfdin__h602252[32:0], 23'd0 } != 56'd0 } ; + assign guard__h594628 = x__h594730 != 57'd0 ; + assign guard__h602866 = + { IF_theResult___snd10889_BIT_33_THEN_2_ELSE_0__q55[1], + { _theResult___snd__h610889[32:0], 23'd0 } != 56'd0 } ; + assign guard__h622142 = + { IF_sfdin30235_BIT_33_THEN_2_ELSE_0__q75[1], + { sfdin__h630235[32:0], 23'd0 } != 56'd0 } ; + assign guard__h630849 = + { IF_theResult___snd38848_BIT_33_THEN_2_ELSE_0__q77[1], + { _theResult___snd__h638848[32:0], 23'd0 } != 56'd0 } ; + assign guard__h639779 = + { IF_sfdin48001_BIT_33_THEN_2_ELSE_0__q85[1], + { sfdin__h648001[32:0], 23'd0 } != 56'd0 } ; + assign guard__h640377 = x__h640479 != 57'd0 ; + assign guard__h648615 = + { IF_theResult___snd56638_BIT_33_THEN_2_ELSE_0__q90[1], + { _theResult___snd__h656638[32:0], 23'd0 } != 56'd0 } ; + assign guard__h667889 = + { IF_sfdin75982_BIT_33_THEN_2_ELSE_0__q110[1], + { sfdin__h675982[32:0], 23'd0 } != 56'd0 } ; + assign guard__h676596 = + { IF_theResult___snd84595_BIT_33_THEN_2_ELSE_0__q112[1], + { _theResult___snd__h684595[32:0], 23'd0 } != 56'd0 } ; + assign guard__h685526 = + { IF_sfdin93748_BIT_33_THEN_2_ELSE_0__q120[1], + { sfdin__h693748[32:0], 23'd0 } != 56'd0 } ; + assign guard__h686124 = x__h686226 != 57'd0 ; + assign guard__h694362 = + { IF_theResult___snd02385_BIT_33_THEN_2_ELSE_0__q125[1], + { _theResult___snd__h702385[32:0], 23'd0 } != 56'd0 } ; + assign guard__h726252 = + { IF_theResult___snd34164_BIT_4_THEN_2_ELSE_0__q146[1], + { _theResult___snd__h734164[3:0], 52'd0 } != 56'd0 } ; + assign guard__h735564 = + { IF_sfdin43784_BIT_4_THEN_2_ELSE_0__q150[1], + { sfdin__h743784[3:0], 52'd0 } != 56'd0 } ; + assign guard__h736162 = x__h736262 != 57'd0 ; + assign guard__h744633 = + { IF_theResult___snd52569_BIT_4_THEN_2_ELSE_0__q153[1], + { _theResult___snd__h752569[3:0], 52'd0 } != 56'd0 } ; + assign guard__h765105 = + { IF_theResult___snd73017_BIT_4_THEN_2_ELSE_0__q186[1], + { _theResult___snd__h773017[3:0], 52'd0 } != 56'd0 } ; + assign guard__h774417 = + { IF_sfdin82637_BIT_4_THEN_2_ELSE_0__q190[1], + { sfdin__h782637[3:0], 52'd0 } != 56'd0 } ; + assign guard__h775015 = x__h775115 != 57'd0 ; + assign guard__h783486 = + { IF_theResult___snd91422_BIT_4_THEN_2_ELSE_0__q193[1], + { _theResult___snd__h791422[3:0], 52'd0 } != 56'd0 } ; + assign guard__h804409 = + { IF_theResult___snd12321_BIT_4_THEN_2_ELSE_0__q163[1], + { _theResult___snd__h812321[3:0], 52'd0 } != 56'd0 } ; + assign guard__h813721 = + { IF_sfdin21941_BIT_4_THEN_2_ELSE_0__q167[1], + { sfdin__h821941[3:0], 52'd0 } != 56'd0 } ; + assign guard__h814319 = x__h814419 != 57'd0 ; + assign guard__h822790 = + { IF_theResult___snd30726_BIT_4_THEN_2_ELSE_0__q170[1], + { _theResult___snd__h830726[3:0], 52'd0 } != 56'd0 } ; + assign highOffsetBits__h242578 = x__h242605 & mask__h239806 ; + assign idx__h966094 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13503 || + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21419 || !coreFix_aluExe_0_rsAlu$canEnq || (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13523) && + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21442) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign imm__h649452 = - fetchStage$pipelines_0_first[160] ? - fetchStage$pipelines_0_first[159:128] : - 32'd0 ; - assign k__h661043 = + !coreFix_aluExe_0_rsAlu_approximateCount__0973__ETC___d20975 ; + assign impliedTopBits__h127403 = x__h127487 + len_correction__h127402 ; + assign impliedTopBits__h140319 = x__h140403 + len_correction__h140318 ; + assign impliedTopBits__h183580 = x__h183664 + len_correction__h183579 ; + assign impliedTopBits__h202331 = x__h202415 + len_correction__h202330 ; + assign impliedTopBits__h216897 = x__h216981 + len_correction__h216896 ; + assign impliedTopBits__h865652 = x__h865737 + len_correction__h865651 ; + assign impliedTopBits__h866200 = x__h866285 + len_correction__h866199 ; + assign impliedTopBits__h904133 = x__h904218 + len_correction__h904132 ; + assign impliedTopBits__h904681 = x__h904766 + len_correction__h904680 ; + assign impliedTopBits__h992149 = x__h992233 + len_correction__h992148 ; + assign in__h239745 = coreFix_memExe_regToExeQ$first[382:317] & y__h239762 ; + assign in__h240902 = coreFix_memExe_regToExeQ$first[219:154] & y__h240919 ; + assign in__h254511 = coreFix_memExe_dTlb$procResp[452:387] & y__h254528 ; + assign in__h994763 = pc_address__h991846 & y__h994780 ; + assign k__h942381 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign mcause_csr__read__h607796 = - { r1__read__h610363, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h607541 = - { r1__read__h610350, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h607141 = - { r1__read__h610186, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h607236 = - { r1__read__h610203, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h607367 = - { r1__read__h610227, csrf_software_int_en_vec_0 } ; - assign mip_csr__read__h608036 = - { r1__read__h610369, csrf_software_int_pend_vec_0 } ; - assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = - mmio_cRqQ_enqReq_dummy2_2$Q_OUT && - IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || - (!mmio_cRqQ_deqReq_dummy2_2$Q_OUT || - !EN_mmioToPlatform_cRq_deq && !mmio_cRqQ_deqReq_rl) && - mmio_cRqQ_full ; - assign mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 = - mmio_cRsQ_enqReq_dummy2_2$Q_OUT && - IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 || - (!mmio_cRsQ_deqReq_dummy2_2$Q_OUT || - !EN_mmioToPlatform_cRs_deq && !mmio_cRsQ_deqReq_rl) && - mmio_cRsQ_full ; - assign mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 = - mmio_dataPendQ_enqReq_dummy2_2$Q_OUT && - (mmio_dataPendQ_enqReq_lat_0$whas || mmio_dataPendQ_enqReq_rl) || - (!mmio_dataPendQ_deqReq_dummy2_2$Q_OUT || - !mmio_dataRespQ_deqReq_lat_0$whas && - !mmio_dataPendQ_deqReq_rl) && - mmio_dataPendQ_full ; - assign mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 = - mmio_dataReqQ_enqReq_dummy2_2$Q_OUT && - IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 || - (!mmio_dataReqQ_deqReq_dummy2_2$Q_OUT || - !CAN_FIRE_RL_mmio_sendDataReq && !mmio_dataReqQ_deqReq_rl) && - mmio_dataReqQ_full ; - assign mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 = - mmio_dataRespQ_enqReq_dummy2_2$Q_OUT && - IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 || - (!mmio_dataRespQ_deqReq_dummy2_2$Q_OUT || - !mmio_dataRespQ_deqReq_lat_0$whas && - !mmio_dataRespQ_deqReq_rl) && - mmio_dataRespQ_full ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12885 = + !coreFix_aluExe_0_rsAlu_approximateCount__0973__ETC___d20975 ; + assign len_correction__h127402 = + INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? + 2'b01 : + 2'b0 ; + assign len_correction__h140318 = + INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? 2'b01 : 2'b0 ; + assign len_correction__h183579 = + INV_x83367_BITS_108_TO_90__q33[0] ? 2'b01 : 2'b0 ; + assign len_correction__h202330 = + INV_x99219_BITS_108_TO_90__q35[0] ? 2'b01 : 2'b0 ; + assign len_correction__h216896 = + INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? + 2'b01 : + 2'b0 ; + assign len_correction__h865651 = + INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? + 2'b01 : + 2'b0 ; + assign len_correction__h866199 = + INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? + 2'b01 : + 2'b0 ; + assign len_correction__h904132 = + INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? + 2'b01 : + 2'b0 ; + assign len_correction__h904680 = + INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? + 2'b01 : + 2'b0 ; + assign len_correction__h992148 = + INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? + 2'b01 : + 2'b0 ; + assign mask__h239806 = + 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[264:259] ; + assign mask__h239915 = + 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[264:259] ; + assign mask__h240963 = + 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[101:96] ; + assign mask__h241072 = + 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[101:96] ; + assign mask__h254572 = + 50'h3FFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; + assign mask__h254681 = + 52'hFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; + assign mask__h996607 = 64'hFFFFFFFFFFFFFFFF << x__h996668 ; + assign mask__h997264 = 64'hFFFFFFFFFFFFFFFF << x__h997325 ; + assign mcause_csr__read__h850486 = + { r1__read__h854005, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h850307 = + { r1__read__h853993, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h849987 = + { r1__read__h853859, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h850085 = + { r1__read__h853876, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h850212 = { r1__read__h853900, 1'b0 } ; + assign mip_csr__read__h850725 = { r1__read__h854012, 1'b0 } ; + assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20457 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && - (fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12881) && + (renameStage_rg_m_halt_req[4] || + fetchStage$pipelines_0_first[69] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20454) ; + assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20849 = + mmio_pRqQ_empty && epochManager$checkEpoch_0_check && + !renameStage_rg_m_halt_req[4] && + !fetchStage$pipelines_0_first[69] && + NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_007_ETC___d20846 ; + assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20869 = + mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20849 && + (fetchStage$pipelines_0_first[272:268] == 5'd0 || + fetchStage$pipelines_0_first[272:268] == 5'd26 || + fetchStage$pipelines_0_first[272:268] == 5'd22 || + fetchStage$pipelines_0_first[272:268] == 5'd23 || + fetchStage$pipelines_0_first[272:268] == 5'd17 || + fetchStage$pipelines_0_first[272:268] == 5'd18 || + fetchStage$pipelines_0_first[272:268] == 5'd21 || + fetchStage$pipelines_0_first[272:268] == 5'd20 || + fetchStage$pipelines_0_first[272:268] == 5'd24 || + fetchStage$pipelines_0_first[272:268] == 5'd25) && rob$isEmpty ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13147 = + assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21770 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && - !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_263_ETC___d13128 && - (fetchStage$pipelines_0_first[199:195] == 5'd0 || - fetchStage$pipelines_0_first[199:195] == 5'd21 || - fetchStage$pipelines_0_first[199:195] == 5'd17 || - fetchStage$pipelines_0_first[199:195] == 5'd18 || - fetchStage$pipelines_0_first[199:195] == 5'd13 || - fetchStage$pipelines_0_first[199:195] == 5'd16 || - fetchStage$pipelines_0_first[199:195] == 5'd15 || - fetchStage$pipelines_0_first[199:195] == 5'd19 || - fetchStage$pipelines_0_first[199:195] == 5'd20) ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13831 = - mmio_pRqQ_empty && epochManager$checkEpoch_0_check && - !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_263_ETC___d13202 && - fetchStage$pipelines_0_first[199:195] != 5'd0 && - fetchStage$pipelines_0_first[199:195] != 5'd21 && - fetchStage$pipelines_0_first[199:195] != 5'd17 && - fetchStage$pipelines_0_first[199:195] != 5'd18 && - fetchStage$pipelines_0_first[199:195] != 5'd13 && - fetchStage$pipelines_0_first[199:195] != 5'd16 && - fetchStage$pipelines_0_first[199:195] != 5'd15 && - fetchStage$pipelines_0_first[199:195] != 5'd19 && - fetchStage$pipelines_0_first[199:195] != 5'd20 ; - assign mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 = - mmio_pRqQ_enqReq_dummy2_2$Q_OUT && - IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 || - (!mmio_pRqQ_deqReq_dummy2_2$Q_OUT || - !CAN_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_deqReq_rl) && - mmio_pRqQ_full ; - assign mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 = - mmio_pRsQ_enqReq_dummy2_2$Q_OUT && - IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 || - (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT || - !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && - mmio_pRsQ_full ; - assign msip__h75409 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h606993 = { r1__read__h610049, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h607449 = - { r1__read__h610345, csrf_mtvec_mode_low_reg } ; - assign n___1__h195750 = - { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h194347[63:56], - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h194347[55:48], - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h194347[47:40], - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h194347[39:32], - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h194347[31:24], - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h194347[23:16], - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h194347[15:8], - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h194347[7:0] } ; - assign n__read__h608140 = - (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && - csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? - csrf_mcycle_ehr_data_rl : - 64'd0 ; - assign n__read__h608331 = - (csrf_minstret_ehr_data_dummy2_0$Q_OUT && - csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? - csrf_minstret_ehr_data_rl : - 64'd0 ; - assign n__read__h6134 = - csrf_mcycle_ehr_data_dummy2_1$Q_OUT ? - (csrf_mcycle_ehr_data_lat_0$whas ? - rob$deqPort_0_deq_data[95:32] : - csrf_mcycle_ehr_data_rl) : - 64'd0 ; - assign n__read__h703197 = - csrf_minstret_ehr_data_dummy2_1$Q_OUT ? - IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : - 64'd0 ; - assign next_deqP___1__h294020 = + !renameStage_rg_m_halt_req[4] && + !fetchStage$pipelines_0_first[69] && + NOT_IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_007_ETC___d20951 ; + assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21772 = + mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21770 && + fetchStage$pipelines_0_first[272:268] != 5'd0 && + fetchStage$pipelines_0_first[272:268] != 5'd26 && + fetchStage$pipelines_0_first[272:268] != 5'd22 && + fetchStage$pipelines_0_first[272:268] != 5'd23 && + fetchStage$pipelines_0_first[272:268] != 5'd17 && + fetchStage$pipelines_0_first[272:268] != 5'd18 && + fetchStage$pipelines_0_first[272:268] != 5'd21 && + fetchStage$pipelines_0_first[272:268] != 5'd20 && + fetchStage$pipelines_0_first[272:268] != 5'd24 && + fetchStage$pipelines_0_first[272:268] != 5'd25 && + rg_core_run_state == 2'd2 ; + assign mstatus_csr__read__h849833 = { r1__read__h853734, csrf_ie_vec_0 } ; + assign n__read__h1008440 = + csrf_minstret_ehr_data_lat_0$whas ? + upd__h1008516 : + csrf_minstret_ehr_data_rl ; + assign n__read__h7877 = + csrf_mcycle_ehr_data_lat_0$whas ? + upd__h7946 : + csrf_mcycle_ehr_data_rl ; + assign newAddrDiff__h996608 = + csrf_stcc_reg_read__6615_BITS_149_TO_86_2502_A_ETC___d22505 - + (address__h996535 & mask__h996607) ; + assign newAddrDiff__h996952 = + csrf_stcc_reg_read__6615_BITS_149_TO_86_2502_A_ETC___d22505 - + (base__h996496 & mask__h996607) ; + assign newAddrDiff__h997265 = + csrf_mtcc_reg_read__6624_BITS_149_TO_86_2579_A_ETC___d22582 - + (address__h996585 & mask__h997264) ; + assign newAddrDiff__h997609 = + csrf_mtcc_reg_read__6624_BITS_149_TO_86_2579_A_ETC___d22582 - + (base__h996550 & mask__h997264) ; + assign new_pc__h871587 = + { coreFix_aluExe_1_exeToFinQ$first[460], + coreFix_aluExe_1_exeToFinQ$first[379:364], + coreFix_aluExe_1_exeToFinQ$first[362:361], + coreFix_aluExe_1_exeToFinQ$first[363], + ~coreFix_aluExe_1_exeToFinQ$first[360:342], + IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17823[25:17], + ~IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17823[16:15], + IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17823[14:3], + ~IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17823[2], + IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17823[1:0], + coreFix_aluExe_1_exeToFinQ$first[457:394] } ; + assign new_pc__h909530 = + { coreFix_aluExe_0_exeToFinQ$first[460], + coreFix_aluExe_0_exeToFinQ$first[379:364], + coreFix_aluExe_0_exeToFinQ$first[362:361], + coreFix_aluExe_0_exeToFinQ$first[363], + ~coreFix_aluExe_0_exeToFinQ$first[360:342], + IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19900[25:17], + ~IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19900[16:15], + IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19900[14:3], + ~IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19900[2], + IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19900[1:0], + coreFix_aluExe_0_exeToFinQ$first[457:394] } ; + assign next_deqP___1__h515541 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h302016 = + assign next_deqP___1__h526318 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h308297 = + assign next_deqP___1__h533596 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h316151 = + assign next_deqP___1__h544231 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h326208 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h329433 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h702540 = - (rob$deqPort_0_deq_data[97:96] == 2'd0) ? - rob$deqPort_0_deq_data[95:32] : - rob$deqPort_0_deq_data[282:219] + 64'd4 ; - assign out___1_sfd__h479376 = - { coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 29'd0 } ; - assign out___1_sfd__h518318 = - { coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 29'd0 } ; - assign out___1_sfd__h557519 = - { coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 29'd0 } ; - assign out_exp__h351930 = - sfdin__h351405[34] ? - _theResult___exp__h351927 : - _theResult___fst_exp__h351411 ; - assign out_exp__h360512 = - _theResult___snd__h360018[34] ? - _theResult___exp__h360509 : - _theResult___fst_exp__h360067 ; - assign out_exp__h369696 = - sfdin__h369171[34] ? - _theResult___exp__h369693 : - _theResult___fst_exp__h369177 ; - assign out_exp__h378332 = - _theResult___snd__h377808[34] ? - _theResult___exp__h378329 : - _theResult___fst_exp__h377862 ; - assign out_exp__h397620 = - sfdin__h397095[34] ? - _theResult___exp__h397617 : - _theResult___fst_exp__h397101 ; - assign out_exp__h406202 = - _theResult___snd__h405708[34] ? - _theResult___exp__h406199 : - _theResult___fst_exp__h405757 ; - assign out_exp__h415386 = - sfdin__h414861[34] ? - _theResult___exp__h415383 : - _theResult___fst_exp__h414867 ; - assign out_exp__h424022 = - _theResult___snd__h423498[34] ? - _theResult___exp__h424019 : - _theResult___fst_exp__h423552 ; - assign out_exp__h443308 = - sfdin__h442783[34] ? - _theResult___exp__h443305 : - _theResult___fst_exp__h442789 ; - assign out_exp__h451890 = - _theResult___snd__h451396[34] ? - _theResult___exp__h451887 : - _theResult___fst_exp__h451445 ; - assign out_exp__h461074 = - sfdin__h460549[34] ? - _theResult___exp__h461071 : - _theResult___fst_exp__h460555 ; - assign out_exp__h469710 = - _theResult___snd__h469186[34] ? - _theResult___exp__h469707 : - _theResult___fst_exp__h469240 ; - assign out_exp__h499332 = - _theResult___snd__h498625[5] ? - _theResult___exp__h499329 : - _theResult___fst_exp__h498674 ; - assign out_exp__h508983 = - sfdin__h508245[5] ? - _theResult___exp__h508980 : - _theResult___fst_exp__h508251 ; - assign out_exp__h517767 = - _theResult___snd__h517030[5] ? - _theResult___exp__h517764 : - _theResult___fst_exp__h517084 ; - assign out_exp__h538133 = - _theResult___snd__h537426[5] ? - _theResult___exp__h538130 : - _theResult___fst_exp__h537475 ; - assign out_exp__h547784 = - sfdin__h547046[5] ? - _theResult___exp__h547781 : - _theResult___fst_exp__h547052 ; - assign out_exp__h556568 = - _theResult___snd__h555831[5] ? - _theResult___exp__h556565 : - _theResult___fst_exp__h555885 ; - assign out_exp__h577334 = - _theResult___snd__h576627[5] ? - _theResult___exp__h577331 : - _theResult___fst_exp__h576676 ; - assign out_exp__h586985 = - sfdin__h586247[5] ? - _theResult___exp__h586982 : - _theResult___fst_exp__h586253 ; - assign out_exp__h595769 = - _theResult___snd__h595032[5] ? - _theResult___exp__h595766 : - _theResult___fst_exp__h595086 ; - assign out_f_exp__h378708 = - (_theResult___exp__h378431 == 8'd255 && - _theResult___sfd__h378432 != 23'd0 || + assign next_deqP___1__h557879 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h561658 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h1007056 = + (rob$deqPort_0_deq_data[196:195] == 2'd0) ? + rob$deqPort_0_deq_data[160:32] : + { rob$deqPort_0_deq_data[630:566], address__h1008010 } ; + assign offset__h239641 = + { 2'd0, coreFix_memExe_regToExeQ$first[316:303] } - + base__h239640 ; + assign offset__h240798 = + { 2'd0, coreFix_memExe_regToExeQ$first[153:140] } - + base__h240797 ; + assign offset__h242559 = + { {32{coreFix_memExe_regToExeQfirst_BITS_433_TO_402__q16[31]}}, + coreFix_memExe_regToExeQfirst_BITS_433_TO_402__q16 } ; + assign offset__h254407 = + { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h254406 ; + assign offset__h994682 = { 2'd0, pc_addrBits__h991847 } - base__h994681 ; + assign out___1_sfd__h714889 = { f1_sfd__h714826, 29'd0 } ; + assign out___1_sfd__h753883 = { f2_sfd__h753820, 29'd0 } ; + assign out___1_sfd__h793187 = { f3_sfd__h793124, 29'd0 } ; + assign out_exp__h585011 = + sfdin__h584486[34] ? + _theResult___exp__h585008 : + _theResult___fst_exp__h584492 ; + assign out_exp__h593593 = + _theResult___snd__h593099[34] ? + _theResult___exp__h593590 : + _theResult___fst_exp__h593148 ; + assign out_exp__h602777 = + sfdin__h602252[34] ? + _theResult___exp__h602774 : + _theResult___fst_exp__h602258 ; + assign out_exp__h611413 = + _theResult___snd__h610889[34] ? + _theResult___exp__h611410 : + _theResult___fst_exp__h610943 ; + assign out_exp__h630760 = + sfdin__h630235[34] ? + _theResult___exp__h630757 : + _theResult___fst_exp__h630241 ; + assign out_exp__h639342 = + _theResult___snd__h638848[34] ? + _theResult___exp__h639339 : + _theResult___fst_exp__h638897 ; + assign out_exp__h648526 = + sfdin__h648001[34] ? + _theResult___exp__h648523 : + _theResult___fst_exp__h648007 ; + assign out_exp__h657162 = + _theResult___snd__h656638[34] ? + _theResult___exp__h657159 : + _theResult___fst_exp__h656692 ; + assign out_exp__h676507 = + sfdin__h675982[34] ? + _theResult___exp__h676504 : + _theResult___fst_exp__h675988 ; + assign out_exp__h685089 = + _theResult___snd__h684595[34] ? + _theResult___exp__h685086 : + _theResult___fst_exp__h684644 ; + assign out_exp__h694273 = + sfdin__h693748[34] ? + _theResult___exp__h694270 : + _theResult___fst_exp__h693754 ; + assign out_exp__h702909 = + _theResult___snd__h702385[34] ? + _theResult___exp__h702906 : + _theResult___fst_exp__h702439 ; + assign out_exp__h734871 = + _theResult___snd__h734164[5] ? + _theResult___exp__h734868 : + _theResult___fst_exp__h734213 ; + assign out_exp__h744522 = + sfdin__h743784[5] ? + _theResult___exp__h744519 : + _theResult___fst_exp__h743790 ; + assign out_exp__h753306 = + _theResult___snd__h752569[5] ? + _theResult___exp__h753303 : + _theResult___fst_exp__h752623 ; + assign out_exp__h773724 = + _theResult___snd__h773017[5] ? + _theResult___exp__h773721 : + _theResult___fst_exp__h773066 ; + assign out_exp__h783375 = + sfdin__h782637[5] ? + _theResult___exp__h783372 : + _theResult___fst_exp__h782643 ; + assign out_exp__h792159 = + _theResult___snd__h791422[5] ? + _theResult___exp__h792156 : + _theResult___fst_exp__h791476 ; + assign out_exp__h813028 = + _theResult___snd__h812321[5] ? + _theResult___exp__h813025 : + _theResult___fst_exp__h812370 ; + assign out_exp__h822679 = + sfdin__h821941[5] ? + _theResult___exp__h822676 : + _theResult___fst_exp__h821947 ; + assign out_exp__h831463 = + _theResult___snd__h830726[5] ? + _theResult___exp__h831460 : + _theResult___fst_exp__h830780 ; + assign out_f_exp__h611789 = + (_theResult___exp__h611512 == 8'd255 && + _theResult___sfd__h611513 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h378422 ; - assign out_f_exp__h424398 = - (_theResult___exp__h424121 == 8'd255 && - _theResult___sfd__h424122 != 23'd0 || + _theResult___fst_exp__h611503 ; + assign out_f_exp__h657538 = + (_theResult___exp__h657261 == 8'd255 && + _theResult___sfd__h657262 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424112 ; - assign out_f_exp__h470086 = - (_theResult___exp__h469809 == 8'd255 && - _theResult___sfd__h469810 != 23'd0 || + _theResult___fst_exp__h657252 ; + assign out_f_exp__h703285 = + (_theResult___exp__h703008 == 8'd255 && + _theResult___sfd__h703009 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h469800 ; - assign out_f_sfd__h378709 = - (_theResult___exp__h378431 == 8'd255 && - _theResult___sfd__h378432 != 23'd0) ? + _theResult___fst_exp__h702999 ; + assign out_f_sfd__h611790 = + (_theResult___exp__h611512 == 8'd255 && + _theResult___sfd__h611513 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h378432 ; - assign out_f_sfd__h424399 = - (_theResult___exp__h424121 == 8'd255 && - _theResult___sfd__h424122 != 23'd0) ? + _theResult___sfd__h611513 ; + assign out_f_sfd__h657539 = + (_theResult___exp__h657261 == 8'd255 && + _theResult___sfd__h657262 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h424122 ; - assign out_f_sfd__h470087 = - (_theResult___exp__h469809 == 8'd255 && - _theResult___sfd__h469810 != 23'd0) ? + _theResult___sfd__h657262 ; + assign out_f_sfd__h703286 = + (_theResult___exp__h703008 == 8'd255 && + _theResult___sfd__h703009 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h469810 ; - assign out_sfd__h351931 = - sfdin__h351405[34] ? - _theResult___sfd__h351928 : - sfdin__h351405[56:34] ; - assign out_sfd__h360513 = - _theResult___snd__h360018[34] ? - _theResult___sfd__h360510 : - _theResult___snd__h360018[56:34] ; - assign out_sfd__h369697 = - sfdin__h369171[34] ? - _theResult___sfd__h369694 : - sfdin__h369171[56:34] ; - assign out_sfd__h378333 = - _theResult___snd__h377808[34] ? - _theResult___sfd__h378330 : - _theResult___snd__h377808[56:34] ; - assign out_sfd__h397621 = - sfdin__h397095[34] ? - _theResult___sfd__h397618 : - sfdin__h397095[56:34] ; - assign out_sfd__h406203 = - _theResult___snd__h405708[34] ? - _theResult___sfd__h406200 : - _theResult___snd__h405708[56:34] ; - assign out_sfd__h415387 = - sfdin__h414861[34] ? - _theResult___sfd__h415384 : - sfdin__h414861[56:34] ; - assign out_sfd__h424023 = - _theResult___snd__h423498[34] ? - _theResult___sfd__h424020 : - _theResult___snd__h423498[56:34] ; - assign out_sfd__h443309 = - sfdin__h442783[34] ? - _theResult___sfd__h443306 : - sfdin__h442783[56:34] ; - assign out_sfd__h451891 = - _theResult___snd__h451396[34] ? - _theResult___sfd__h451888 : - _theResult___snd__h451396[56:34] ; - assign out_sfd__h461075 = - sfdin__h460549[34] ? - _theResult___sfd__h461072 : - sfdin__h460549[56:34] ; - assign out_sfd__h469711 = - _theResult___snd__h469186[34] ? - _theResult___sfd__h469708 : - _theResult___snd__h469186[56:34] ; - assign out_sfd__h499333 = - _theResult___snd__h498625[5] ? - _theResult___sfd__h499330 : - _theResult___snd__h498625[56:5] ; - assign out_sfd__h508984 = - sfdin__h508245[5] ? - _theResult___sfd__h508981 : - sfdin__h508245[56:5] ; - assign out_sfd__h517768 = - _theResult___snd__h517030[5] ? - _theResult___sfd__h517765 : - _theResult___snd__h517030[56:5] ; - assign out_sfd__h538134 = - _theResult___snd__h537426[5] ? - _theResult___sfd__h538131 : - _theResult___snd__h537426[56:5] ; - assign out_sfd__h547785 = - sfdin__h547046[5] ? - _theResult___sfd__h547782 : - sfdin__h547046[56:5] ; - assign out_sfd__h556569 = - _theResult___snd__h555831[5] ? - _theResult___sfd__h556566 : - _theResult___snd__h555831[56:5] ; - assign out_sfd__h577335 = - _theResult___snd__h576627[5] ? - _theResult___sfd__h577332 : - _theResult___snd__h576627[56:5] ; - assign out_sfd__h586986 = - sfdin__h586247[5] ? - _theResult___sfd__h586983 : - sfdin__h586247[56:5] ; - assign out_sfd__h595770 = - _theResult___snd__h595032[5] ? - _theResult___sfd__h595767 : - _theResult___snd__h595032[56:5] ; - assign pend_ints__h645394 = - { csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12647, + _theResult___sfd__h703009 ; + assign out_sfd__h585012 = + sfdin__h584486[34] ? + _theResult___sfd__h585009 : + sfdin__h584486[56:34] ; + assign out_sfd__h593594 = + _theResult___snd__h593099[34] ? + _theResult___sfd__h593591 : + _theResult___snd__h593099[56:34] ; + assign out_sfd__h602778 = + sfdin__h602252[34] ? + _theResult___sfd__h602775 : + sfdin__h602252[56:34] ; + assign out_sfd__h611414 = + _theResult___snd__h610889[34] ? + _theResult___sfd__h611411 : + _theResult___snd__h610889[56:34] ; + assign out_sfd__h630761 = + sfdin__h630235[34] ? + _theResult___sfd__h630758 : + sfdin__h630235[56:34] ; + assign out_sfd__h639343 = + _theResult___snd__h638848[34] ? + _theResult___sfd__h639340 : + _theResult___snd__h638848[56:34] ; + assign out_sfd__h648527 = + sfdin__h648001[34] ? + _theResult___sfd__h648524 : + sfdin__h648001[56:34] ; + assign out_sfd__h657163 = + _theResult___snd__h656638[34] ? + _theResult___sfd__h657160 : + _theResult___snd__h656638[56:34] ; + assign out_sfd__h676508 = + sfdin__h675982[34] ? + _theResult___sfd__h676505 : + sfdin__h675982[56:34] ; + assign out_sfd__h685090 = + _theResult___snd__h684595[34] ? + _theResult___sfd__h685087 : + _theResult___snd__h684595[56:34] ; + assign out_sfd__h694274 = + sfdin__h693748[34] ? + _theResult___sfd__h694271 : + sfdin__h693748[56:34] ; + assign out_sfd__h702910 = + _theResult___snd__h702385[34] ? + _theResult___sfd__h702907 : + _theResult___snd__h702385[56:34] ; + assign out_sfd__h734872 = + _theResult___snd__h734164[5] ? + _theResult___sfd__h734869 : + _theResult___snd__h734164[56:5] ; + assign out_sfd__h744523 = + sfdin__h743784[5] ? + _theResult___sfd__h744520 : + sfdin__h743784[56:5] ; + assign out_sfd__h753307 = + _theResult___snd__h752569[5] ? + _theResult___sfd__h753304 : + _theResult___snd__h752569[56:5] ; + assign out_sfd__h773725 = + _theResult___snd__h773017[5] ? + _theResult___sfd__h773722 : + _theResult___snd__h773017[56:5] ; + assign out_sfd__h783376 = + sfdin__h782637[5] ? + _theResult___sfd__h783373 : + sfdin__h782637[56:5] ; + assign out_sfd__h792160 = + _theResult___snd__h791422[5] ? + _theResult___sfd__h792157 : + _theResult___snd__h791422[56:5] ; + assign out_sfd__h813029 = + _theResult___snd__h812321[5] ? + _theResult___sfd__h813026 : + _theResult___snd__h812321[56:5] ; + assign out_sfd__h822680 = + sfdin__h821941[5] ? + _theResult___sfd__h822677 : + sfdin__h821941[56:5] ; + assign out_sfd__h831464 = + _theResult___snd__h830726[5] ? + _theResult___sfd__h831461 : + _theResult___snd__h830726[56:5] ; + assign pc__h960508 = fetchStage$pipelines_1_first[590:462] ; + assign pc_addrBits__h991847 = + INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? + x__h992018[13:0] : + commitStage_commitTrap[122:109] ; + assign pc_address__h991846 = { 2'd0, commitStage_commitTrap[172:109] } ; + assign pend_ints__h917687 = + { _0_CONCAT_csrf_external_int_en_vec_3_read__6082_ETC___d20086, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, - csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ; - assign prv__h707140 = csrf_prv_reg ; - assign prv__h707184 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h473078 = + 1'd0 } ; + assign pointer__h242569 = + coreFix_memExe_regToExeQ$first[382:317] + + { 2'd0, offset__h242559 } ; + assign prv__h1011737 = csrf_prv_reg ; + assign prv__h1011781 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h706385 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_12_TO_0___h645916 = - { 3'd0, + assign r1__read_BITS_13_TO_0___h918236 = + { 4'd0, csrf_mideleg_11_reg, 1'b0, csrf_mideleg_9_7_reg, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h649320 = csrf_fs_reg ; - assign r1__read_BIT_20___h649948 = csrf_tw_reg ; - assign r1__read__h608838 = { r1__read__h608840, csrf_ie_vec_1 } ; - assign r1__read__h608840 = { r1__read__h608842, 2'b0 } ; - assign r1__read__h608842 = { r1__read__h608844, csrf_prev_ie_vec_0 } ; - assign r1__read__h608844 = { r1__read__h608846, csrf_prev_ie_vec_1 } ; - assign r1__read__h608846 = { r1__read__h608848, 2'b0 } ; - assign r1__read__h608848 = { r1__read__h608850, csrf_spp_reg } ; - assign r1__read__h608850 = { r1__read__h608852, 4'b0 } ; - assign r1__read__h608852 = { r1__read__h608854, csrf_fs_reg } ; - assign r1__read__h608854 = { r1__read__h608856, 2'd0 } ; - assign r1__read__h608856 = { r1__read__h608858, 1'b0 } ; - assign r1__read__h608858 = { r1__read__h608860, csrf_sum_reg } ; - assign r1__read__h608860 = { r1__read__h608862, csrf_mxr_reg } ; - assign r1__read__h608862 = { r1__read__h608864, 12'b0 } ; - assign r1__read__h608864 = { r1__read__h608866, 2'b10 } ; - assign r1__read__h608866 = { r__h608870, 29'b0 } ; - assign r1__read__h609242 = - { r1__read__h609244, csrf_software_int_en_vec_1 } ; - assign r1__read__h609244 = { r1__read__h609246, 2'b0 } ; - assign r1__read__h609246 = { r1__read__h609248, csrf_timer_int_en_vec_0 } ; - assign r1__read__h609248 = { r1__read__h609250, csrf_timer_int_en_vec_1 } ; - assign r1__read__h609250 = { r1__read__h609252, 2'b0 } ; - assign r1__read__h609252 = - { r1__read__h609254, csrf_external_int_en_vec_0 } ; - assign r1__read__h609254 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h609772 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h609777 = { r1__read__h609779, csrf_scounteren_tm_reg } ; - assign r1__read__h609779 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h609790 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h609796 = - { r1__read__h609798, csrf_software_int_pend_vec_1 } ; - assign r1__read__h609798 = { r1__read__h609800, 2'b0 } ; - assign r1__read__h609800 = - { r1__read__h609802, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h609802 = - { r1__read__h609804, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h609804 = { r1__read__h609806, 2'b0 } ; - assign r1__read__h609806 = - { r1__read__h609808, csrf_external_int_pend_vec_0 } ; - assign r1__read__h609808 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h610026 = { vm_mode_reg__read__h610032, 16'd0 } ; - assign r1__read__h610049 = { r1__read__h610051, csrf_ie_vec_1 } ; - assign r1__read__h610051 = { r1__read__h610053, 1'b0 } ; - assign r1__read__h610053 = { r1__read__h610055, csrf_ie_vec_3 } ; - assign r1__read__h610055 = { r1__read__h610057, csrf_prev_ie_vec_0 } ; - assign r1__read__h610057 = { r1__read__h610059, csrf_prev_ie_vec_1 } ; - assign r1__read__h610059 = { r1__read__h610061, 1'b0 } ; - assign r1__read__h610061 = { r1__read__h610063, csrf_prev_ie_vec_3 } ; - assign r1__read__h610063 = { r1__read__h610065, csrf_spp_reg } ; - assign r1__read__h610065 = { r1__read__h610067, 2'b0 } ; - assign r1__read__h610067 = { r1__read__h610069, csrf_mpp_reg } ; - assign r1__read__h610069 = { r1__read__h610071, csrf_fs_reg } ; - assign r1__read__h610071 = { r1__read__h610073, 2'd0 } ; - assign r1__read__h610073 = { r1__read__h610075, csrf_mprv_reg } ; - assign r1__read__h610075 = { r1__read__h610077, csrf_sum_reg } ; - assign r1__read__h610077 = { r1__read__h610079, csrf_mxr_reg } ; - assign r1__read__h610079 = { r1__read__h610081, csrf_tvm_reg } ; - assign r1__read__h610081 = { r1__read__h610083, csrf_tw_reg } ; - assign r1__read__h610083 = { r1__read__h610085, csrf_tsr_reg } ; - assign r1__read__h610085 = { r1__read__h610087, 9'b0 } ; - assign r1__read__h610087 = { r1__read__h610089, 2'b10 } ; - assign r1__read__h610089 = { r1__read__h610091, 2'b10 } ; - assign r1__read__h610091 = { r__h608870, 27'b0 } ; - assign r1__read__h610186 = { r1__read__h610188, 1'b0 } ; - assign r1__read__h610188 = { r1__read__h610190, csrf_medeleg_13_11_reg } ; - assign r1__read__h610190 = { r1__read__h610192, 1'b0 } ; - assign r1__read__h610192 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h610203 = { r1__read__h610205, 1'b0 } ; - assign r1__read__h610205 = { r1__read__h610207, csrf_mideleg_5_3_reg } ; - assign r1__read__h610207 = { r1__read__h610209, 1'b0 } ; - assign r1__read__h610209 = { r1__read__h610211, csrf_mideleg_9_7_reg } ; - assign r1__read__h610211 = { r1__read__h610213, 1'b0 } ; - assign r1__read__h610213 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h610227 = - { r1__read__h610229, csrf_software_int_en_vec_1 } ; - assign r1__read__h610229 = { r1__read__h610231, 1'b0 } ; - assign r1__read__h610231 = - { r1__read__h610233, csrf_software_int_en_vec_3 } ; - assign r1__read__h610233 = { r1__read__h610235, csrf_timer_int_en_vec_0 } ; - assign r1__read__h610235 = { r1__read__h610237, csrf_timer_int_en_vec_1 } ; - assign r1__read__h610237 = { r1__read__h610239, 1'b0 } ; - assign r1__read__h610239 = { r1__read__h610241, csrf_timer_int_en_vec_3 } ; - assign r1__read__h610241 = - { r1__read__h610243, csrf_external_int_en_vec_0 } ; - assign r1__read__h610243 = - { r1__read__h610245, csrf_external_int_en_vec_1 } ; - assign r1__read__h610245 = { r1__read__h610247, 1'b0 } ; - assign r1__read__h610247 = { 52'd4, csrf_external_int_en_vec_3 } ; - assign r1__read__h610345 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h610350 = { r1__read__h610352, csrf_mcounteren_tm_reg } ; - assign r1__read__h610352 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h610363 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h610369 = - { r1__read__h610371, csrf_software_int_pend_vec_1 } ; - assign r1__read__h610371 = { r1__read__h610373, 1'b0 } ; - assign r1__read__h610373 = - { r1__read__h610375, csrf_software_int_pend_vec_3 } ; - assign r1__read__h610375 = - { r1__read__h610377, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h610377 = - { r1__read__h610379, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h610379 = { r1__read__h610381, 1'b0 } ; - assign r1__read__h610381 = - { r1__read__h610383, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h610383 = - { r1__read__h610385, csrf_external_int_pend_vec_0 } ; - assign r1__read__h610385 = - { r1__read__h610387, csrf_external_int_pend_vec_1 } ; - assign r1__read__h610387 = { r1__read__h610389, 1'b0 } ; - assign r1__read__h610389 = - { r1__read__h610391, csrf_external_int_pend_vec_3 } ; - assign r1__read__h610391 = { r1__read__h610393, 2'b0 } ; - assign r1__read__h610393 = { 49'b0, csrf_debug_int_pend } ; - assign rVal1__h478959 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h478960 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h473104 = + assign r1__read_BITS_13_TO_12___h923870 = csrf_fs_reg ; + assign r1__read_BIT_20___h924376 = csrf_tw_reg ; + assign r1__read__h852568 = { r1__read__h852570, csrf_ie_vec_1 } ; + assign r1__read__h852570 = { r1__read__h852572, 2'b0 } ; + assign r1__read__h852572 = { r1__read__h852574, csrf_prev_ie_vec_0 } ; + assign r1__read__h852574 = { r1__read__h852576, csrf_prev_ie_vec_1 } ; + assign r1__read__h852576 = { r1__read__h852578, 2'b0 } ; + assign r1__read__h852578 = { r1__read__h852580, csrf_spp_reg } ; + assign r1__read__h852580 = { r1__read__h852582, 4'b0 } ; + assign r1__read__h852582 = { r1__read__h852584, csrf_fs_reg } ; + assign r1__read__h852584 = { r1__read__h852586, 2'd0 } ; + assign r1__read__h852586 = { r1__read__h852588, 1'b0 } ; + assign r1__read__h852588 = { r1__read__h852590, csrf_sum_reg } ; + assign r1__read__h852590 = { r1__read__h852592, csrf_mxr_reg } ; + assign r1__read__h852592 = { r1__read__h852594, 12'b0 } ; + assign r1__read__h852594 = { r1__read__h852596, 2'b10 } ; + assign r1__read__h852596 = { r__h852600, 29'b0 } ; + assign r1__read__h852972 = + { r1__read__h852974, csrf_software_int_en_vec_1 } ; + assign r1__read__h852974 = { r1__read__h852976, 2'b0 } ; + assign r1__read__h852976 = { r1__read__h852978, 1'b0 } ; + assign r1__read__h852978 = { r1__read__h852980, csrf_timer_int_en_vec_1 } ; + assign r1__read__h852980 = { r1__read__h852982, 2'b0 } ; + assign r1__read__h852982 = { r1__read__h852984, 1'b0 } ; + assign r1__read__h852984 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h853482 = { r1__read__h853484, csrf_scounteren_tm_reg } ; + assign r1__read__h853484 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h853494 = { csrf_scause_interrupt_reg, 58'b0 } ; + assign r1__read__h853501 = + { r1__read__h853503, csrf_software_int_pend_vec_1 } ; + assign r1__read__h853503 = { r1__read__h853505, 2'b0 } ; + assign r1__read__h853505 = { r1__read__h853507, 1'b0 } ; + assign r1__read__h853507 = + { r1__read__h853509, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h853509 = { r1__read__h853511, 2'b0 } ; + assign r1__read__h853511 = { r1__read__h853513, 1'b0 } ; + assign r1__read__h853513 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h853711 = { vm_mode_reg__read__h853717, 16'd0 } ; + assign r1__read__h853734 = { r1__read__h853736, csrf_ie_vec_1 } ; + assign r1__read__h853736 = { r1__read__h853738, 1'b0 } ; + assign r1__read__h853738 = { r1__read__h853740, csrf_ie_vec_3 } ; + assign r1__read__h853740 = { r1__read__h853742, csrf_prev_ie_vec_0 } ; + assign r1__read__h853742 = { r1__read__h853744, csrf_prev_ie_vec_1 } ; + assign r1__read__h853744 = { r1__read__h853746, 1'b0 } ; + assign r1__read__h853746 = { r1__read__h853748, csrf_prev_ie_vec_3 } ; + assign r1__read__h853748 = { r1__read__h853750, csrf_spp_reg } ; + assign r1__read__h853750 = { r1__read__h853752, 2'b0 } ; + assign r1__read__h853752 = { r1__read__h853754, csrf_mpp_reg } ; + assign r1__read__h853754 = { r1__read__h853756, csrf_fs_reg } ; + assign r1__read__h853756 = { r1__read__h853758, 2'd0 } ; + assign r1__read__h853758 = { r1__read__h853760, csrf_mprv_reg } ; + assign r1__read__h853760 = { r1__read__h853762, csrf_sum_reg } ; + assign r1__read__h853762 = { r1__read__h853764, csrf_mxr_reg } ; + assign r1__read__h853764 = { r1__read__h853766, csrf_tvm_reg } ; + assign r1__read__h853766 = { r1__read__h853768, csrf_tw_reg } ; + assign r1__read__h853768 = { r1__read__h853770, csrf_tsr_reg } ; + assign r1__read__h853770 = { r1__read__h853772, 9'b0 } ; + assign r1__read__h853772 = { r1__read__h853774, 2'b10 } ; + assign r1__read__h853774 = { r1__read__h853776, 2'b10 } ; + assign r1__read__h853776 = { r__h852600, 27'b0 } ; + assign r1__read__h853859 = { r1__read__h853861, 1'b0 } ; + assign r1__read__h853861 = { r1__read__h853863, csrf_medeleg_13_11_reg } ; + assign r1__read__h853863 = { r1__read__h853865, 1'b0 } ; + assign r1__read__h853865 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h853876 = { r1__read__h853878, 1'b0 } ; + assign r1__read__h853878 = { r1__read__h853880, csrf_mideleg_5_3_reg } ; + assign r1__read__h853880 = { r1__read__h853882, 1'b0 } ; + assign r1__read__h853882 = { r1__read__h853884, csrf_mideleg_9_7_reg } ; + assign r1__read__h853884 = { r1__read__h853886, 1'b0 } ; + assign r1__read__h853886 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h853900 = + { r1__read__h853902, csrf_software_int_en_vec_1 } ; + assign r1__read__h853902 = { r1__read__h853904, 1'b0 } ; + assign r1__read__h853904 = + { r1__read__h853906, csrf_software_int_en_vec_3 } ; + assign r1__read__h853906 = { r1__read__h853908, 1'b0 } ; + assign r1__read__h853908 = { r1__read__h853910, csrf_timer_int_en_vec_1 } ; + assign r1__read__h853910 = { r1__read__h853912, 1'b0 } ; + assign r1__read__h853912 = { r1__read__h853914, csrf_timer_int_en_vec_3 } ; + assign r1__read__h853914 = { r1__read__h853916, 1'b0 } ; + assign r1__read__h853916 = + { r1__read__h853918, csrf_external_int_en_vec_1 } ; + assign r1__read__h853918 = { r1__read__h853920, 1'b0 } ; + assign r1__read__h853920 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h853993 = { r1__read__h853995, csrf_mcounteren_tm_reg } ; + assign r1__read__h853995 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h854005 = { csrf_mcause_interrupt_reg, 58'd0 } ; + assign r1__read__h854012 = + { r1__read__h854014, csrf_software_int_pend_vec_1 } ; + assign r1__read__h854014 = { r1__read__h854016, 1'b0 } ; + assign r1__read__h854016 = + { r1__read__h854018, csrf_software_int_pend_vec_3 } ; + assign r1__read__h854018 = { r1__read__h854020, 1'b0 } ; + assign r1__read__h854020 = + { r1__read__h854022, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h854022 = { r1__read__h854024, 1'b0 } ; + assign r1__read__h854024 = + { r1__read__h854026, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h854026 = { r1__read__h854028, 1'b0 } ; + assign r1__read__h854028 = + { r1__read__h854030, csrf_external_int_pend_vec_1 } ; + assign r1__read__h854030 = { r1__read__h854032, 1'b0 } ; + assign r1__read__h854032 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h854341 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h714446 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h714447 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h706411 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign r__h608870 = csrf_fs_reg == 2'b11 ; - assign regRenamingTable_RDY_rename_0_getRename__3087__ETC___d13688 = + assign r__h852600 = csrf_fs_reg == 2'b11 ; + assign r__h854087 = csrf_software_int_pend_vec_3 ; + assign regRenamingTable_RDY_rename_0_getRename__0805__ETC___d21619 = regRenamingTable$RDY_rename_0_getRename && - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 && - (fetchStage$pipelines_0_first[199:195] == 5'd14 || + CASE_fetchStagepipelines_0_first_BITS_264_TO__ETC__q268 && + (fetchStage$pipelines_0_first[272:268] == 5'd19 || coreFix_memExe_rsMem$RDY_enq) ; - assign regRenamingTable_RDY_rename_1_getRename__3744__ETC___d13762 = - regRenamingTable$RDY_rename_1_getRename && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3181_3271_OR_NOT__ETC___d13747) && - _0_OR_NOT_fetchStage_pipelines_1_first__2614_BI_ETC___d13760 ; - assign regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258 = + assign regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958 = regRenamingTable$rename_0_canRename && - fetchStage$pipelines_0_first[199:195] != 5'd0 && - fetchStage$pipelines_0_first[199:195] != 5'd21 && - fetchStage$pipelines_0_first[199:195] != 5'd17 && - fetchStage$pipelines_0_first[199:195] != 5'd18 && - fetchStage$pipelines_0_first[199:195] != 5'd13 && - fetchStage$pipelines_0_first[199:195] != 5'd16 && - fetchStage$pipelines_0_first[199:195] != 5'd15 && - fetchStage$pipelines_0_first[199:195] != 5'd19 && - fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_0_first__2605_BIT_68__ETC___d13256 ; - assign regRenamingTable_rename_0_canRename__3183_AND__ETC___d13272 = - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 && - fetchStage$pipelines_0_first[194:192] == 3'd1 || + fetchStage$pipelines_0_first[272:268] != 5'd0 && + fetchStage$pipelines_0_first[272:268] != 5'd26 && + fetchStage$pipelines_0_first[272:268] != 5'd22 && + fetchStage$pipelines_0_first[272:268] != 5'd23 && + fetchStage$pipelines_0_first[272:268] != 5'd17 && + fetchStage$pipelines_0_first[272:268] != 5'd18 && + fetchStage$pipelines_0_first[272:268] != 5'd21 && + fetchStage$pipelines_0_first[272:268] != 5'd20 && + fetchStage$pipelines_0_first[272:268] != 5'd24 && + fetchStage$pipelines_0_first[272:268] != 5'd25 && + NOT_renameStage_rg_m_halt_req_0072_BIT_4_0073__ETC___d20956 ; + assign regRenamingTable_rename_0_canRename__0929_AND__ETC___d21010 = + regRenamingTable$rename_0_canRename && + fetchStage$pipelines_0_first[272:268] != 5'd0 && + fetchStage$pipelines_0_first[272:268] != 5'd26 && + fetchStage$pipelines_0_first[272:268] != 5'd22 && + fetchStage$pipelines_0_first[272:268] != 5'd23 && + fetchStage$pipelines_0_first[272:268] != 5'd17 && + fetchStage$pipelines_0_first[272:268] != 5'd18 && + fetchStage$pipelines_0_first[272:268] != 5'd21 && + fetchStage$pipelines_0_first[272:268] != 5'd20 && + fetchStage$pipelines_0_first[272:268] != 5'd24 && + fetchStage$pipelines_0_first[272:268] != 5'd25 && + NOT_fetchStage_pipelines_0_first__0045_BIT_69__ETC___d21008 ; + assign regRenamingTable_rename_0_canRename__0929_AND__ETC___d21024 = + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21010 && + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21020 && + fetchStage$pipelines_0_first[267:265] == 3'd1 || !specTagManager$canClaim ; - assign regRenamingTable_rename_0_canRename__3183_AND__ETC___d13578 = - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258 && - fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 || + assign regRenamingTable_rename_0_canRename__0929_AND__ETC___d21500 = + regRenamingTable_rename_0_canRename__0929_AND__ETC___d21010 && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 && + fetchStage$pipelines_0_first[267:265] == 3'd2 && + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 || !coreFix_memExe_rsMem$canEnq || - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ; - assign regRenamingTable_rename_0_canRename__3183_AND__ETC___d13717 = + CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q264 ; + assign regRenamingTable_rename_0_canRename__0929_AND__ETC___d21648 = regRenamingTable$rename_0_canRename && - !checkForException___d12839[4] && + !checkForException___d20432[13] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13715 && - fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign regRenamingTable_rename_0_canRename__3183_AND__ETC___d13849 = + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21646 && + fetchStage$pipelines_0_first[267:265] == 3'd1 ; + assign regRenamingTable_rename_0_canRename__0929_AND__ETC___d21790 = regRenamingTable$rename_0_canRename && - !checkForException___d12839[4] && + !checkForException___d20432[13] && rob$enqPort_0_canEnq && - (fetchStage$pipelines_0_first[194:192] == 3'd3 || - fetchStage$pipelines_0_first[194:192] == 3'd4) && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 && + (fetchStage$pipelines_0_first[267:265] == 3'd3 || + fetchStage$pipelines_0_first[267:265] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign regRenamingTable_rename_0_canRename__3183_AND__ETC___d13855 = + assign regRenamingTable_rename_0_canRename__0929_AND__ETC___d21797 = regRenamingTable$rename_0_canRename && - !checkForException___d12839[4] && + !checkForException___d20432[13] && rob$enqPort_0_canEnq && - fetchStage$pipelines_0_first[194:192] == 3'd2 && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 && + fetchStage$pipelines_0_first[267:265] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 && - fetchStage$pipelines_0_first[199:195] != 5'd14 ; - assign regRenamingTable_rename_0_canRename__3183_AND__ETC___d13875 = + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 && + fetchStage$pipelines_0_first[272:268] != 5'd19 ; + assign regRenamingTable_rename_0_canRename__0929_AND__ETC___d21821 = regRenamingTable$rename_0_canRename && - !checkForException___d12839[4] && + !checkForException___d20432[13] && rob$enqPort_0_canEnq && - fetchStage$pipelines_0_first[194:192] == 3'd2 && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 && + fetchStage$pipelines_0_first[267:265] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 && - (fetchStage$pipelines_0_first[191:189] == 3'd0 || - fetchStage$pipelines_0_first[191:189] == 3'd2) ; - assign regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883 = + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 && + (fetchStage$pipelines_0_first[264:262] == 3'd0 || + fetchStage$pipelines_0_first[264:262] == 3'd2) ; + assign regRenamingTable_rename_0_canRename__0929_AND__ETC___d21830 = regRenamingTable$rename_0_canRename && - !checkForException___d12839[4] && + !checkForException___d20432[13] && rob$enqPort_0_canEnq && - fetchStage$pipelines_0_first[194:192] == 3'd2 && + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 && + fetchStage$pipelines_0_first[267:265] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 && - fetchStage$pipelines_0_first[191:189] != 3'd0 && - fetchStage$pipelines_0_first[191:189] != 3'd2 ; - assign regRenamingTable_rename_0_canRename__3183_AND__ETC___d14027 = + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 && + fetchStage$pipelines_0_first[264:262] != 3'd0 && + fetchStage$pipelines_0_first[264:262] != 3'd2 ; + assign regRenamingTable_rename_0_canRename__0929_AND__ETC___d21991 = regRenamingTable$rename_0_canRename && - !checkForException___d12839[4] && + !checkForException___d20432[13] && rob$enqPort_0_canEnq && - fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 ; - assign regRenamingTable_rename_1_canRename__3307_AND__ETC___d13937 = + fetchStage$pipelines_0_first[237:236] != 2'd0 && + fetchStage$pipelines_0_first[237:236] != 2'd1 && + fetchStage$pipelines_0_first[267:265] == 3'd2 && + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 ; + assign regRenamingTable_rename_1_canRename__1062_AND__ETC___d21409 = regRenamingTable$rename_1_canRename && - fetchStage$pipelines_1_first[199:195] != 5'd0 && - fetchStage$pipelines_1_first[199:195] != 5'd21 && - fetchStage$pipelines_1_first[199:195] != 5'd17 && - fetchStage$pipelines_1_first[199:195] != 5'd18 && - fetchStage$pipelines_1_first[199:195] != 5'd13 && - fetchStage$pipelines_1_first[199:195] != 5'd16 && - fetchStage$pipelines_1_first[199:195] != 5'd15 && - fetchStage$pipelines_1_first[199:195] != 5'd19 && - fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_1_first__2614_BIT_68__ETC___d13935 ; - assign regRenamingTable_rename_1_canRename__3307_AND__ETC___d13981 = - regRenamingTable_rename_1_canRename__3307_AND__ETC___d13937 && - (fetchStage$pipelines_1_first[194:192] == 3'd3 || - fetchStage$pipelines_1_first[194:192] == 3'd4) && - (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3183__ETC___d13668 || - fetchStage$pipelines_0_first[194:192] != 3'd3 && - fetchStage$pipelines_0_first[194:192] != 3'd4) && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign renaming_spec_bits__h675346 = + fetchStage$pipelines_1_first[272:268] != 5'd0 && + fetchStage$pipelines_1_first[272:268] != 5'd26 && + fetchStage$pipelines_1_first[272:268] != 5'd22 && + fetchStage$pipelines_1_first[272:268] != 5'd23 && + fetchStage$pipelines_1_first[272:268] != 5'd17 && + fetchStage$pipelines_1_first[272:268] != 5'd18 && + fetchStage$pipelines_1_first[272:268] != 5'd21 && + fetchStage$pipelines_1_first[272:268] != 5'd20 && + fetchStage$pipelines_1_first[272:268] != 5'd24 && + fetchStage$pipelines_1_first[272:268] != 5'd25 && + NOT_renameStage_rg_m_halt_req_0072_BIT_4_0073__ETC___d21407 ; + assign regRenamingTable_rename_1_canRename__1062_AND__ETC___d21557 = + regRenamingTable$rename_1_canRename && + fetchStage$pipelines_1_first[272:268] != 5'd0 && + fetchStage$pipelines_1_first[272:268] != 5'd26 && + fetchStage$pipelines_1_first[272:268] != 5'd22 && + fetchStage$pipelines_1_first[272:268] != 5'd23 && + fetchStage$pipelines_1_first[272:268] != 5'd17 && + fetchStage$pipelines_1_first[272:268] != 5'd18 && + fetchStage$pipelines_1_first[272:268] != 5'd21 && + fetchStage$pipelines_1_first[272:268] != 5'd20 && + fetchStage$pipelines_1_first[272:268] != 5'd24 && + fetchStage$pipelines_1_first[272:268] != 5'd25 && + NOT_renameStage_rg_m_halt_req_0072_BIT_4_0073__ETC___d21555 ; + assign regRenamingTable_rename_1_canRename__1062_AND__ETC___d21576 = + regRenamingTable$rename_1_canRename && + fetchStage$pipelines_1_first[272:268] != 5'd0 && + fetchStage$pipelines_1_first[272:268] != 5'd26 && + fetchStage$pipelines_1_first[272:268] != 5'd22 && + fetchStage$pipelines_1_first[272:268] != 5'd23 && + fetchStage$pipelines_1_first[272:268] != 5'd17 && + fetchStage$pipelines_1_first[272:268] != 5'd18 && + fetchStage$pipelines_1_first[272:268] != 5'd21 && + fetchStage$pipelines_1_first[272:268] != 5'd20 && + fetchStage$pipelines_1_first[272:268] != 5'd24 && + fetchStage$pipelines_1_first[272:268] != 5'd25 && + NOT_renameStage_rg_m_halt_req_0072_BIT_4_0073__ETC___d21574 ; + assign regRenamingTable_rename_1_canRename__1062_AND__ETC___d21890 = + regRenamingTable$rename_1_canRename && + fetchStage$pipelines_1_first[272:268] != 5'd0 && + fetchStage$pipelines_1_first[272:268] != 5'd26 && + fetchStage$pipelines_1_first[272:268] != 5'd22 && + fetchStage$pipelines_1_first[272:268] != 5'd23 && + fetchStage$pipelines_1_first[272:268] != 5'd17 && + fetchStage$pipelines_1_first[272:268] != 5'd18 && + fetchStage$pipelines_1_first[272:268] != 5'd21 && + fetchStage$pipelines_1_first[272:268] != 5'd20 && + fetchStage$pipelines_1_first[272:268] != 5'd24 && + fetchStage$pipelines_1_first[272:268] != 5'd25 && + NOT_fetchStage_pipelines_1_first__0054_BIT_69__ETC___d21888 ; + assign renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21432 = + renameStage_rg_m_halt_req[4] || + fetchStage$pipelines_0_first[69] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d21429 || + !rob$enqPort_0_canEnq || + !epochManager$checkEpoch_0_check ; + assign renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21475 = + renameStage_rg_m_halt_req[4] || + fetchStage$pipelines_1_first[69] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d21469 || + !rob$enqPort_1_canEnq || + !epochManager$checkEpoch_1_check || + csrf_rg_dcsr_read__6184_BIT_2_0464_OR_NOT_fetc_ETC___d21029 ; + assign renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21517 = + renameStage_rg_m_halt_req[4] || + fetchStage$pipelines_0_first[69] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[0] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[1] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[2] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[3] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[4] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[5] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[6] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[7] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[8] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[9] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[10] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[11] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[12] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[13] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[14] || + IF_IF_NOT_csrf_prv_reg_read__0075_EQ_3_0076_00_ETC___d20112[15] ; + assign renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21598 = + renameStage_rg_m_halt_req[4] || + fetchStage$pipelines_0_first[69] || + checkForException___d20432[13] || + !rob$enqPort_0_canEnq ; + assign renaming_spec_bits__h965955 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h672112 : + y_avValue_snd_fst__h960652 : specTagManager$currentSpecBits ; - assign res_data__h335087 = { 32'd0, x__h335099 } ; - assign res_data__h335092 = + assign repBoundBits__h242584 = + { coreFix_memExe_regToExeQ$first[230:228], 11'd0 } ; + assign repBound__h237262 = rf$read_3_rd1[13:11] - 3'b001 ; + assign repBound__h238947 = rf$read_3_rd2[13:11] - 3'b001 ; + assign repBound__h248150 = + coreFix_memExe_regToExeQ$first[244:242] - 3'b001 ; + assign repBound__h248675 = csrf_ddc_reg[13:11] - 3'b001 ; + assign repBound__h855893 = rf$read_1_rd1[13:11] - 3'b001 ; + assign repBound__h859237 = rf$read_1_rd2[13:11] - 3'b001 ; + assign repBound__h859255 = thin_bounds_baseBits__h859108[13:11] - 3'b001 ; + assign repBound__h865801 = x__h865740[13:11] - 3'b001 ; + assign repBound__h866349 = x__h866288[13:11] - 3'b001 ; + assign repBound__h895779 = rf$read_0_rd1[13:11] - 3'b001 ; + assign repBound__h898106 = rf$read_0_rd2[13:11] - 3'b001 ; + assign repBound__h898124 = thin_bounds_baseBits__h898009[13:11] - 3'b001 ; + assign repBound__h904282 = x__h904221[13:11] - 3'b001 ; + assign repBound__h904830 = x__h904769[13:11] - 3'b001 ; + assign repBound__h994706 = x__h992236[13:11] - 3'b001 ; + assign repBound__h996759 = csrf_stcc_reg[13:11] - 3'b001 ; + assign repBound__h997416 = csrf_mtcc_reg[13:11] - 3'b001 ; + assign res_addrBits__h126792 = + INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? + x__h127272[13:0] : + coreFix_memExe_respLrScAmoQ_data_0[13:0] ; + assign res_addrBits__h139704 = + INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? + x__h140188[13:0] : + mmio_dataRespQ_data_0[13:0] ; + assign res_addrBits__h178867 = + INV_x83367_BITS_108_TO_90__q33[0] ? + x__h183449[13:0] : + x__h183367[13:0] ; + assign res_addrBits__h197632 = + INV_x99219_BITS_108_TO_90__q35[0] ? + x__h202200[13:0] : + x__h199219[13:0] ; + assign res_addrBits__h216391 = + INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? + x__h216766[13:0] : + coreFix_memExe_lsq$respLd[13:0] ; + assign res_addrBits__h235268 = { 2'b0, addr__h235261[63:52] } ; + assign res_addrBits__h567274 = + { 2'b0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:90] } ; + assign res_addrBits__h568126 = { 2'b0, data__h567607[63:52] } ; + assign res_addrBits__h613883 = { 2'b0, data__h613367[63:52] } ; + assign res_addrBits__h659630 = { 2'b0, data__h659114[63:52] } ; + assign res_addrBits__h705439 = { 2'b0, data__h704928[63:52] } ; + assign res_addrBits__h706299 = { 2'b0, data__h705791[63:52] } ; + assign res_addrBits__h848497 = { 2'b0, addr__h843839[63:52] } ; + assign res_addrBits__h890734 = { 2'b0, addr__h886084[63:52] } ; + assign res_address__h126791 = + { 2'd0, coreFix_memExe_respLrScAmoQ_data_0[63:0] } ; + assign res_address__h139703 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; + assign res_address__h178866 = { 2'd0, x__h183367[63:0] } ; + assign res_address__h197631 = { 2'd0, x__h199219[63:0] } ; + assign res_address__h216390 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; + assign res_address__h235267 = { 2'd0, addr__h235261 } ; + assign res_address__h567273 = + { 2'd0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38] } ; + assign res_address__h568125 = { 2'd0, data__h567607 } ; + assign res_address__h613882 = { 2'd0, data__h613367 } ; + assign res_address__h659629 = { 2'd0, data__h659114 } ; + assign res_address__h705438 = { 2'd0, data__h704928 } ; + assign res_address__h706298 = { 2'd0, data__h705791 } ; + assign res_address__h848496 = { 2'd0, addr__h843839 } ; + assign res_address__h890733 = { 2'd0, addr__h886084 } ; + assign res_data__h568165 = { 32'hFFFFFFFF, x__h568180 } ; + assign res_data__h568170 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -28680,8 +36374,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h380782 = { 32'd0, x__h380794 } ; - assign res_data__h380787 = + assign res_data__h613919 = { 32'hFFFFFFFF, x__h613934 } ; + assign res_data__h613924 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -28694,8 +36388,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h426470 = { 32'd0, x__h426482 } ; - assign res_data__h426475 = + assign res_data__h659666 = { 32'hFFFFFFFF, x__h659681 } ; + assign res_data__h659671 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -28708,7 +36402,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h335088 = + assign res_fflags__h568166 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -28723,7 +36417,7 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5198, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9312, (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -28736,7 +36430,7 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5209, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9323, (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -28749,7 +36443,7 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5225, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9339, (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -28762,7 +36456,7 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5238, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9352, (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -28775,8 +36469,8 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251 } ; - assign res_fflags__h380783 = + IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9365 } ; + assign res_fflags__h613920 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -28791,7 +36485,7 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10709, (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -28804,7 +36498,7 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6601, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10720, (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -28817,7 +36511,7 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6617, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10736, (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -28830,7 +36524,7 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6630, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10749, (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -28843,8 +36537,8 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643 } ; - assign res_fflags__h426471 = + IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10762 } ; + assign res_fflags__h659667 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -28859,7 +36553,7 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7982, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12106, (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -28872,7 +36566,7 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7993, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12117, (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -28885,7 +36579,7 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8009, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12133, (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -28898,7 +36592,7 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8022, + IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12146, (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -28911,548 +36605,903 @@ module mkCore(CLK, 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035 } ; - assign resp_addr__h289191 = - { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h361552 = - { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[56:1], - _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[0] | - guard__h361547 } ; - assign result__h407242 = - { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[56:1], - _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[0] | - guard__h407237 } ; - assign result__h452930 = - { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[56:1], - _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[0] | - guard__h452925 } ; - assign result__h500628 = - { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645[56:1], - _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645[0] | - guard__h500623 } ; - assign result__h539429 = - { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118[56:1], - _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118[0] | - guard__h539424 } ; - assign result__h578630 = - { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355[56:1], - _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355[0] | - guard__h578625 } ; - assign result__h641103 = w__h641098 & y__h641132 ; - assign result__h641154 = ~x__h641153 ; - assign rob_RDY_enqPort_0_enq__2627_AND_regRenamingTab_ETC___d13095 = - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign rob_enqPort_1_canEnq__3487_AND_epochManager_ch_ETC___d13492 = - rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && + IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12159 } ; + assign resp_addr__h509039 = + { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[53:1], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[168:158] } ; + assign result__h240541 = + { 1'd0, + ~coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692[64], + coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692[63:0] } ; + assign result__h241698 = + { 1'd0, + ~coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754[64], + coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754[63:0] } ; + assign result__h255307 = + { 1'd0, + ~coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389[64], + coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389[63:0] } ; + assign result__h594633 = + { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8663[56:1], + _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8663[0] | + guard__h594628 } ; + assign result__h640382 = + { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10060[56:1], + _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10060[0] | + guard__h640377 } ; + assign result__h686129 = + { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11457[56:1], + _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11457[0] | + guard__h686124 } ; + assign result__h736167 = + { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12786[56:1], + _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12786[0] | + guard__h736162 } ; + assign result__h775020 = + { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14271[56:1], + _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14271[0] | + guard__h775015 } ; + assign result__h814324 = + { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13501[56:1], + _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13501[0] | + guard__h814319 } ; + assign result__h913267 = w__h913262 & y__h913296 ; + assign result__h913318 = ~x__h913317 ; + assign result_d_address__h242780 = { 2'd0, pointer__h242569[63:0] } ; + assign ret__h239918 = + { 1'd0, + coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692[64:0] } ; + assign ret__h241075 = + { 1'd0, + coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754[64:0] } ; + assign ret__h254684 = + { 1'd0, + coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389[64:0] } ; + assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18897 = + rf$read_0_rd1[27:25] < repBound__h895779 ; + assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18910 = + rf$read_0_rd1[13:11] < repBound__h895779 ; + assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18924 = + rf$read_0_rd1[85:83] < repBound__h895779 ; + assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18968 = + rf$read_0_rd2[27:25] < repBound__h898106 ; + assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18969 = + rf$read_0_rd2[13:11] < repBound__h898106 ; + assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18971 = + rf$read_0_rd2[85:83] < repBound__h898106 ; + assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18981 = + { rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18971, + (rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18968 == + rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18971) ? + 2'd0 : + ((rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18968 && + !rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18971) ? + 2'd1 : + 2'd3), + (rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18969 == + rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18971) ? + 2'd0 : + ((rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18969 && + !rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18971) ? + 2'd1 : + 2'd3) } ; + assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16514 = + rf$read_1_rd1[27:25] < repBound__h855893 ; + assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16527 = + rf$read_1_rd1[13:11] < repBound__h855893 ; + assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16541 = + rf$read_1_rd1[85:83] < repBound__h855893 ; + assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16585 = + rf$read_1_rd2[27:25] < repBound__h859237 ; + assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16586 = + rf$read_1_rd2[13:11] < repBound__h859237 ; + assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16588 = + rf$read_1_rd2[85:83] < repBound__h859237 ; + assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16598 = + { rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16588, + (rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16585 == + rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16588) ? + 2'd0 : + ((rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16585 && + !rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16588) ? + 2'd1 : + 2'd3), + (rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16586 == + rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16588) ? + 2'd0 : + ((rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16586 && + !rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16588) ? + 2'd1 : + 2'd3) } ; + assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3319 = + rf$read_3_rd1[27:25] < repBound__h237262 ; + assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3332 = + rf$read_3_rd1[13:11] < repBound__h237262 ; + assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3346 = + rf$read_3_rd1[85:83] < repBound__h237262 ; + assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3580 = + rf$read_3_rd2[27:25] < repBound__h238947 ; + assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3588 = + rf$read_3_rd2[13:11] < repBound__h238947 ; + assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3597 = + rf$read_3_rd2[85:83] < repBound__h238947 ; + assign rg_core_run_state_read__0460_EQ_2_0461_AND_NOT_ETC___d23446 = + rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && + !update_vm_info && + fetchStage$iTlbIfc_flush_done && + coreFix_memExe_dTlb$flush_done && + !flush_caches ; + assign rg_tdata1__read__h851826 = + { r1__read__h854341, csrf_rg_tdata1_data } ; + assign rob_RDY_enqPort_1_enq__1748_AND_NOT_fetchStage_ETC___d21756 = + rob$RDY_enqPort_1_enq && (!fetchStage$pipelines_0_canDeq || - (fetchStage$pipelines_0_first[194:192] != 3'd1 || - specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13244) ; - assign rob_enqPort_1_canEnq__3487_AND_epochManager_ch_ETC___d13626 = - rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && - (!fetchStage$pipelines_0_canDeq || - (fetchStage$pipelines_0_first[194:192] != 3'd1 || - specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13622) ; - assign rob_enqPort_1_canEnq__3487_AND_epochManager_ch_ETC___d13643 = - rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && - (!fetchStage$pipelines_0_canDeq || - (fetchStage$pipelines_0_first[194:192] != 3'd1 || - specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258 && - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13639) ; - assign robdeqPort_0_deq_data_BITS_95_TO_32__q261 = + NOT_specTagManager_canClaim__0927_1023_OR_NOT__ETC___d21752) && + (fetchStage$pipelines_1_first[267:265] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; + assign robdeqPort_0_deq_data_BITS_95_TO_32__q326 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h649451 = - (fetchStage$pipelines_0_first[88] && - !fetchStage$pipelines_0_first[87]) ? - fetchStage$pipelines_0_first[86:82] : - 5'd0 ; - assign satp_csr__read__h606850 = { r1__read__h610026, csrf_ppn_reg } ; - assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291 = + assign satp_csr__read__h849687 = { r1__read__h853711, csrf_ppn_reg } ; + assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12424 = (sbCons$lazyLookup_2_get[2] || - IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8247 && - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8264) && + IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d12380 && + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12397) && (sbCons$lazyLookup_2_get[1] || - IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8271 && - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8288) ; - assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8292 = + IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d12404 && + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12421) ; + assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12425 = (sbCons$lazyLookup_2_get[3] || - IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8214 && - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8240) && - sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291 ; - assign sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631 = + IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d12347 && + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12373) && + sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12424 ; + assign sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d2762 = (sbCons$lazyLookup_3_get[3] || - IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1578 && - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1604) && + IF_coreFix_memExe_dispToRegQ_RDY_first__679_AN_ETC___d2709 && + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2735) && (sbCons$lazyLookup_3_get[2] || - IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611 && - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628) ; - assign sbIdx__h156310 = - coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? - (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? - coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : - coreFix_memExe_reqStQ_data_0_rl[65:64]) : - 2'd0 ; - assign scause_csr__read__h606648 = - { r1__read__h609790, csrf_scause_code_reg } ; - assign scounteren_csr__read__h606510 = - { r1__read__h609777, csrf_scounteren_cy_reg } ; - assign sfd__h335695 = { value__h343922, 3'd0 } ; - assign sfd__h351503 = + IF_coreFix_memExe_dispToRegQ_RDY_first__679_AN_ETC___d2742 && + IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2759) ; + assign sbIdx__h151985 = + CAN_FIRE_RL_coreFix_memExe_doIssueSB ? + coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : + coreFix_memExe_reqStQ_data_0_rl[65:64] ; + assign scause_csr__read__h849484 = + { r1__read__h853494, csrf_scause_code_reg } ; + assign scounteren_csr__read__h849389 = + { r1__read__h853482, csrf_scounteren_cy_reg } ; + assign sfd__h568776 = { value__h577003, 3'd0 } ; + assign sfd__h584584 = { 1'b0, - _theResult___fst_exp__h351411 != 8'd0, - sfdin__h351405[56:34] } + + _theResult___fst_exp__h584492 != 8'd0, + sfdin__h584486[56:34] } + 25'd1 ; - assign sfd__h360085 = + assign sfd__h593166 = { 1'b0, - _theResult___fst_exp__h360067 != 8'd0, - _theResult___snd__h360018[56:34] } + + _theResult___fst_exp__h593148 != 8'd0, + _theResult___snd__h593099[56:34] } + 25'd1 ; - assign sfd__h369269 = + assign sfd__h602350 = { 1'b0, - _theResult___fst_exp__h369177 != 8'd0, - sfdin__h369171[56:34] } + + _theResult___fst_exp__h602258 != 8'd0, + sfdin__h602252[56:34] } + 25'd1 ; - assign sfd__h377881 = + assign sfd__h610962 = { 1'b0, - _theResult___fst_exp__h377862 != 8'd0, - _theResult___snd__h377808[56:34] } + + _theResult___fst_exp__h610943 != 8'd0, + _theResult___snd__h610889[56:34] } + 25'd1 ; - assign sfd__h381390 = { value__h389612, 3'd0 } ; - assign sfd__h397193 = + assign sfd__h614530 = { value__h622752, 3'd0 } ; + assign sfd__h630333 = { 1'b0, - _theResult___fst_exp__h397101 != 8'd0, - sfdin__h397095[56:34] } + + _theResult___fst_exp__h630241 != 8'd0, + sfdin__h630235[56:34] } + 25'd1 ; - assign sfd__h405775 = + assign sfd__h638915 = { 1'b0, - _theResult___fst_exp__h405757 != 8'd0, - _theResult___snd__h405708[56:34] } + + _theResult___fst_exp__h638897 != 8'd0, + _theResult___snd__h638848[56:34] } + 25'd1 ; - assign sfd__h414959 = + assign sfd__h648099 = { 1'b0, - _theResult___fst_exp__h414867 != 8'd0, - sfdin__h414861[56:34] } + + _theResult___fst_exp__h648007 != 8'd0, + sfdin__h648001[56:34] } + 25'd1 ; - assign sfd__h423571 = + assign sfd__h656711 = { 1'b0, - _theResult___fst_exp__h423552 != 8'd0, - _theResult___snd__h423498[56:34] } + + _theResult___fst_exp__h656692 != 8'd0, + _theResult___snd__h656638[56:34] } + 25'd1 ; - assign sfd__h427078 = { value__h435300, 3'd0 } ; - assign sfd__h442881 = + assign sfd__h660277 = { value__h668499, 3'd0 } ; + assign sfd__h676080 = { 1'b0, - _theResult___fst_exp__h442789 != 8'd0, - sfdin__h442783[56:34] } + + _theResult___fst_exp__h675988 != 8'd0, + sfdin__h675982[56:34] } + 25'd1 ; - assign sfd__h451463 = + assign sfd__h684662 = { 1'b0, - _theResult___fst_exp__h451445 != 8'd0, - _theResult___snd__h451396[56:34] } + + _theResult___fst_exp__h684644 != 8'd0, + _theResult___snd__h684595[56:34] } + 25'd1 ; - assign sfd__h460647 = + assign sfd__h693846 = { 1'b0, - _theResult___fst_exp__h460555 != 8'd0, - sfdin__h460549[56:34] } + + _theResult___fst_exp__h693754 != 8'd0, + sfdin__h693748[56:34] } + 25'd1 ; - assign sfd__h469259 = + assign sfd__h702458 = { 1'b0, - _theResult___fst_exp__h469240 != 8'd0, - _theResult___snd__h469186[56:34] } + + _theResult___fst_exp__h702439 != 8'd0, + _theResult___snd__h702385[56:34] } + 25'd1 ; - assign sfd__h479673 = { value__h484231, 32'd0 } ; - assign sfd__h498692 = + assign sfd__h715187 = { value__h719770, 32'd0 } ; + assign sfd__h734231 = { 1'b0, - _theResult___fst_exp__h498674 != 11'd0, - _theResult___snd__h498625[56:5] } + + _theResult___fst_exp__h734213 != 11'd0, + _theResult___snd__h734164[56:5] } + 54'd1 ; - assign sfd__h508343 = + assign sfd__h743882 = { 1'b0, - _theResult___fst_exp__h508251 != 11'd0, - sfdin__h508245[56:5] } + + _theResult___fst_exp__h743790 != 11'd0, + sfdin__h743784[56:5] } + 54'd1 ; - assign sfd__h517103 = + assign sfd__h752642 = { 1'b0, - _theResult___fst_exp__h517084 != 11'd0, - _theResult___snd__h517030[56:5] } + + _theResult___fst_exp__h752623 != 11'd0, + _theResult___snd__h752569[56:5] } + 54'd1 ; - assign sfd__h518615 = { value__h523032, 32'd0 } ; - assign sfd__h537493 = + assign sfd__h754181 = { value__h758623, 32'd0 } ; + assign sfd__h773084 = { 1'b0, - _theResult___fst_exp__h537475 != 11'd0, - _theResult___snd__h537426[56:5] } + + _theResult___fst_exp__h773066 != 11'd0, + _theResult___snd__h773017[56:5] } + 54'd1 ; - assign sfd__h547144 = + assign sfd__h782735 = { 1'b0, - _theResult___fst_exp__h547052 != 11'd0, - sfdin__h547046[56:5] } + + _theResult___fst_exp__h782643 != 11'd0, + sfdin__h782637[56:5] } + 54'd1 ; - assign sfd__h555904 = + assign sfd__h791495 = { 1'b0, - _theResult___fst_exp__h555885 != 11'd0, - _theResult___snd__h555831[56:5] } + + _theResult___fst_exp__h791476 != 11'd0, + _theResult___snd__h791422[56:5] } + 54'd1 ; - assign sfd__h557816 = { value__h562233, 32'd0 } ; - assign sfd__h576694 = + assign sfd__h793485 = { value__h797927, 32'd0 } ; + assign sfd__h812388 = { 1'b0, - _theResult___fst_exp__h576676 != 11'd0, - _theResult___snd__h576627[56:5] } + + _theResult___fst_exp__h812370 != 11'd0, + _theResult___snd__h812321[56:5] } + 54'd1 ; - assign sfd__h586345 = + assign sfd__h822039 = { 1'b0, - _theResult___fst_exp__h586253 != 11'd0, - sfdin__h586247[56:5] } + + _theResult___fst_exp__h821947 != 11'd0, + sfdin__h821941[56:5] } + 54'd1 ; - assign sfd__h595105 = + assign sfd__h830799 = { 1'b0, - _theResult___fst_exp__h595086 != 11'd0, - _theResult___snd__h595032[56:5] } + + _theResult___fst_exp__h830780 != 11'd0, + _theResult___snd__h830726[56:5] } + 54'd1 ; - assign sfdin__h351405 = - _theResult____h343300[56] ? - _theResult___snd__h351422 : - _theResult___snd__h351433 ; - assign sfdin__h369171 = - _theResult____h360939[56] ? - _theResult___snd__h369188 : - _theResult___snd__h369199 ; - assign sfdin__h397095 = - _theResult____h388992[56] ? - _theResult___snd__h397112 : - _theResult___snd__h397123 ; - assign sfdin__h414861 = - _theResult____h406629[56] ? - _theResult___snd__h414878 : - _theResult___snd__h414889 ; - assign sfdin__h442783 = - _theResult____h434680[56] ? - _theResult___snd__h442800 : - _theResult___snd__h442811 ; - assign sfdin__h460549 = - _theResult____h452317[56] ? - _theResult___snd__h460566 : - _theResult___snd__h460577 ; - assign sfdin__h508245 = - _theResult____h500015[56] ? - _theResult___snd__h508262 : - _theResult___snd__h508273 ; - assign sfdin__h547046 = - _theResult____h538816[56] ? - _theResult___snd__h547063 : - _theResult___snd__h547074 ; - assign sfdin__h586247 = - _theResult____h578017[56] ? - _theResult___snd__h586264 : - _theResult___snd__h586275 ; - assign shiftData__h180514 = - coreFix_memExe_regToExeQ$first[75:12] << x__h180646 ; - assign sie_csr__read__h606414 = - { r1__read__h609242, csrf_software_int_en_vec_0 } ; - assign sip_csr__read__h606787 = - { r1__read__h609796, csrf_software_int_pend_vec_0 } ; - assign spec_bits__h678441 = specTagManager$currentSpecBits | y__h678454 ; - assign sstatus_csr__read__h606345 = { r1__read__h608838, csrf_ie_vec_0 } ; - assign stvec_csr__read__h606457 = - { r1__read__h609772, csrf_stvec_mode_low_reg } ; - assign upd__h3639 = + assign sfdin__h584486 = + _theResult____h576381[56] ? + _theResult___snd__h584503 : + _theResult___snd__h584514 ; + assign sfdin__h602252 = + _theResult____h594020[56] ? + _theResult___snd__h602269 : + _theResult___snd__h602280 ; + assign sfdin__h630235 = + _theResult____h622132[56] ? + _theResult___snd__h630252 : + _theResult___snd__h630263 ; + assign sfdin__h648001 = + _theResult____h639769[56] ? + _theResult___snd__h648018 : + _theResult___snd__h648029 ; + assign sfdin__h675982 = + _theResult____h667879[56] ? + _theResult___snd__h675999 : + _theResult___snd__h676010 ; + assign sfdin__h693748 = + _theResult____h685516[56] ? + _theResult___snd__h693765 : + _theResult___snd__h693776 ; + assign sfdin__h743784 = + _theResult____h735554[56] ? + _theResult___snd__h743801 : + _theResult___snd__h743812 ; + assign sfdin__h782637 = + _theResult____h774407[56] ? + _theResult___snd__h782654 : + _theResult___snd__h782665 ; + assign sfdin__h821941 = + _theResult____h813711[56] ? + _theResult___snd__h821958 : + _theResult___snd__h821969 ; + assign sie_csr__read__h849336 = { r1__read__h852972, 1'b0 } ; + assign signBits__h242575 = {50{offset__h242559[63]}} ; + assign sip_csr__read__h849624 = { r1__read__h853501, 1'b0 } ; + assign spec_bits__h970974 = specTagManager$currentSpecBits | y__h970987 ; + assign sstatus_csr__read__h849266 = { r1__read__h852568, csrf_ie_vec_0 } ; + assign tb__h865798 = { impliedTopBits__h865652, topBits__h865648[11] } ; + assign tb__h866346 = { impliedTopBits__h866200, topBits__h866196[11] } ; + assign tb__h904279 = { impliedTopBits__h904133, topBits__h904129[11] } ; + assign tb__h904827 = { impliedTopBits__h904681, topBits__h904677[11] } ; + assign thin_address__h996489 = + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 ? + IF_csrf_stcc_reg_read__6615_BIT_86_2497_AND_NO_ETC___d22677 : + IF_csrf_mtcc_reg_read__6624_BIT_86_2574_AND_NO_ETC___d22678 ; + assign tmpAddr__h242768 = pointer__h242569[63:0] ; + assign tmp_expBotHalf__h127265 = + { ~coreFix_memExe_respLrScAmoQ_data_0[66], + coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; + assign tmp_expBotHalf__h140181 = + { ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; + assign tmp_expBotHalf__h183442 = { ~x__h183367[66], x__h183367[65:64] } ; + assign tmp_expBotHalf__h202193 = { ~x__h199219[66], x__h199219[65:64] } ; + assign tmp_expBotHalf__h216759 = + { ~coreFix_memExe_lsq$respLd[66], + coreFix_memExe_lsq$respLd[65:64] } ; + assign tmp_expBotHalf__h865501 = + { ~coreFix_aluExe_1_regToExeQ$first[244], + coreFix_aluExe_1_regToExeQ$first[243:242] } ; + assign tmp_expBotHalf__h866049 = + { ~coreFix_aluExe_1_regToExeQ$first[115], + coreFix_aluExe_1_regToExeQ$first[114:113] } ; + assign tmp_expBotHalf__h903982 = + { ~coreFix_aluExe_0_regToExeQ$first[244], + coreFix_aluExe_0_regToExeQ$first[243:242] } ; + assign tmp_expBotHalf__h904530 = + { ~coreFix_aluExe_0_regToExeQ$first[115], + coreFix_aluExe_0_regToExeQ$first[114:113] } ; + assign tmp_expBotHalf__h992011 = + { ~commitStage_commitTrap[175], + commitStage_commitTrap[174:173] } ; + assign tmp_expTopHalf__h127263 = + { ~coreFix_memExe_respLrScAmoQ_data_0[80:79], + coreFix_memExe_respLrScAmoQ_data_0[78] } ; + assign tmp_expTopHalf__h140179 = + { ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; + assign tmp_expTopHalf__h183440 = { ~x__h183367[80:79], x__h183367[78] } ; + assign tmp_expTopHalf__h202191 = { ~x__h199219[80:79], x__h199219[78] } ; + assign tmp_expTopHalf__h216757 = + { ~coreFix_memExe_lsq$respLd[80:79], + coreFix_memExe_lsq$respLd[78] } ; + assign tmp_expTopHalf__h865499 = + { ~coreFix_aluExe_1_regToExeQ$first[258:257], + coreFix_aluExe_1_regToExeQ$first[256] } ; + assign tmp_expTopHalf__h866047 = + { ~coreFix_aluExe_1_regToExeQ$first[129:128], + coreFix_aluExe_1_regToExeQ$first[127] } ; + assign tmp_expTopHalf__h903980 = + { ~coreFix_aluExe_0_regToExeQ$first[258:257], + coreFix_aluExe_0_regToExeQ$first[256] } ; + assign tmp_expTopHalf__h904528 = + { ~coreFix_aluExe_0_regToExeQ$first[129:128], + coreFix_aluExe_0_regToExeQ$first[127] } ; + assign tmp_expTopHalf__h992009 = + { ~commitStage_commitTrap[189:188], + commitStage_commitTrap[187] } ; + assign toBoundsM1__h242588 = + repBoundBits__h242584 + + ~coreFix_memExe_regToExeQ$first[316:303] ; + assign toBounds__h242587 = + repBoundBits__h242584 - coreFix_memExe_regToExeQ$first[316:303] ; + assign topBits__h127399 = + INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? + { coreFix_memExe_respLrScAmoQ_data_0[89:81], 3'd0 } : + b_top__h127496 ; + assign topBits__h140315 = + INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? + { mmio_dataRespQ_data_0[89:81], 3'd0 } : + b_top__h140412 ; + assign topBits__h183576 = + INV_x83367_BITS_108_TO_90__q33[0] ? + { x__h183367[89:81], 3'd0 } : + b_top__h183673 ; + assign topBits__h202327 = + INV_x99219_BITS_108_TO_90__q35[0] ? + { x__h199219[89:81], 3'd0 } : + b_top__h202424 ; + assign topBits__h216893 = + INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? + { coreFix_memExe_lsq$respLd[89:81], 3'd0 } : + b_top__h216990 ; + assign topBits__h865648 = + INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? + { coreFix_aluExe_1_regToExeQ$first[267:259], 3'd0 } : + b_top__h865746 ; + assign topBits__h866196 = + INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? + { coreFix_aluExe_1_regToExeQ$first[138:130], 3'd0 } : + b_top__h866294 ; + assign topBits__h904129 = + INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? + { coreFix_aluExe_0_regToExeQ$first[267:259], 3'd0 } : + b_top__h904227 ; + assign topBits__h904677 = + INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? + { coreFix_aluExe_0_regToExeQ$first[138:130], 3'd0 } : + b_top__h904775 ; + assign topBits__h992145 = + INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? + { commitStage_commitTrap[198:190], 3'd0 } : + b_top__h992242 ; + assign trap_val__h994147 = { 53'd0, x__h995968 } ; + assign upd__h1008516 = + MUX_csrf_minstret_ehr_data_lat_0$wset_1__SEL_1 ? + f_csr_reqs$D_OUT[63:0] : + rob$deqPort_0_deq_data[95:32] ; + assign upd__h3035 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; - assign upd__h4956 = n__read__h6134 + 64'd1 ; - assign v__h293161 = - (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027) ? - v__h293392 : + assign upd__h3645 = n__read__h7877 + 64'd1 ; + assign upd__h7946 = + MUX_csrf_mcycle_ehr_data_lat_0$wset_1__SEL_1 ? + f_csr_reqs$D_OUT[63:0] : + rob$deqPort_0_deq_data[95:32] ; + assign v__h1007095 = + { csrf_sepcc_reg_data_rl[152], + csrf_sepcc_reg_data_rl[71:56], + csrf_sepcc_reg_data_rl[54:53], + csrf_sepcc_reg_data_rl[55], + ~csrf_sepcc_reg_data_rl[52:34], + IF_csrf_sepcc_reg_read_wget__3069_BIT_34_3078__ETC___d23086[25:17], + ~IF_csrf_sepcc_reg_read_wget__3069_BIT_34_3078__ETC___d23086[16:15], + IF_csrf_sepcc_reg_read_wget__3069_BIT_34_3078__ETC___d23086[14:3], + ~IF_csrf_sepcc_reg_read_wget__3069_BIT_34_3078__ETC___d23086[2], + IF_csrf_sepcc_reg_read_wget__3069_BIT_34_3078__ETC___d23086[1:0], + csrf_sepcc_reg_data_rl[149:86] } ; + assign v__h1007548 = + { csrf_mepcc_reg_data_rl[152], + csrf_mepcc_reg_data_rl[71:56], + csrf_mepcc_reg_data_rl[54:53], + csrf_mepcc_reg_data_rl[55], + ~csrf_mepcc_reg_data_rl[52:34], + IF_csrf_mepcc_reg_read_wget__3098_BIT_34_3107__ETC___d23115[25:17], + ~IF_csrf_mepcc_reg_read_wget__3098_BIT_34_3107__ETC___d23115[16:15], + IF_csrf_mepcc_reg_read_wget__3098_BIT_34_3107__ETC___d23115[14:3], + ~IF_csrf_mepcc_reg_read_wget__3098_BIT_34_3107__ETC___d23115[2], + IF_csrf_mepcc_reg_read_wget__3098_BIT_34_3107__ETC___d23115[1:0], + csrf_mepcc_reg_data_rl[149:86] } ; + assign v__h514752 = + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 ? + v__h514947 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h293392 = + assign v__h514947 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h296506 = - (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134) ? - v__h297024 : + assign v__h516772 = + IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7303 ? + v__h517152 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h297024 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h307020 = - (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305) ? - v__h307251 : + assign v__h517152 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h532491 = + IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7462 ? + v__h532686 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h307251 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h310896 = - (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401) ? - v__h311127 : + assign v__h532686 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h534940 = + IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7546 ? + v__h535135 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h311127 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h325497 = - (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630) ? - v__h325728 : + assign v__h535135 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h555960 = + IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7751 ? + v__h556155 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h325728 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h328722 = - (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724) ? - v__h328953 : + assign v__h556155 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h559739 = + IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7833 ? + v__h559934 : coreFix_memExe_forwardQ_enqP ; - assign v__h328953 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h600772 = + assign v__h559934 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h836568 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h600782 : + v__h836578 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h600782 = + assign v__h836578 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h601417 = v__h600772 - 2'd1 ; - assign v__h604755 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h605661 ; - assign v__h628443 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h629196 ; - assign vaddr__h180509 = - coreFix_memExe_regToExeQ$first[139:76] + - { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4[31]}}, - coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4 } ; - assign value__h343922 = + assign v__h837213 = v__h836568 - 2'd1 ; + assign value__h239635 = x__h239653 | in__h239745[63:0] ; + assign value__h239799 = + { coreFix_memExe_regToExeQ$first[380:331] & mask__h239806, + 14'd0 } + + addBase__h239805 ; + assign value__h240792 = x__h240810 | in__h240902[63:0] ; + assign value__h240956 = + { coreFix_memExe_regToExeQ$first[217:168] & mask__h240963, + 14'd0 } + + addBase__h240962 ; + assign value__h254401 = x__h254419 | in__h254511[63:0] ; + assign value__h254565 = + { coreFix_memExe_dTlb$procResp[450:401] & mask__h254572, + 14'd0 } + + addBase__h254571 ; + assign value__h577003 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h389612 = + assign value__h622752 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h435300 = + assign value__h668499 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h484231 = - { 1'b0, - coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0, - coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] } ; - assign value__h523032 = - { 1'b0, - coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0, - coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] } ; - assign value__h562233 = - { 1'b0, - coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0, - coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] } ; - assign vm_mode_reg__read__h610032 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h641098 = + assign value__h719770 = { 1'b0, f1_exp__h714825 != 8'd0, f1_sfd__h714826 } ; + assign value__h758623 = { 1'b0, f2_exp__h753819 != 8'd0, f2_sfd__h753820 } ; + assign value__h797927 = { 1'b0, f3_exp__h793123 != 8'd0, f3_sfd__h793124 } ; + assign vm_mode_reg__read__h853717 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h913262 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h641154 : + result__h913318 : 12'd4095 ; - assign x__h152884 = - coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? - coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : - coreFix_memExe_reqLdQ_data_0_rl[68:64]) : - 5'd0 ; - assign x__h152890 = - coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? - coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : - coreFix_memExe_reqLdQ_data_0_rl[63:0]) : - 64'd0 ; - assign x__h156431 = { 3'd0, sbIdx__h156310 } ; - assign x__h156437 = - coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? - (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? - coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : - coreFix_memExe_reqStQ_data_0_rl[63:0]) : - 64'd0 ; - assign x__h159247 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : - 5'd0 ; - assign x__h159251 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : - 64'd0 ; - assign x__h161099 = - coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? - coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : - coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) : - 64'd0 ; - assign x__h17672 = - mmio_dataReqQ_enqReq_lat_0$whas ? - mmio_dataReqQ_enqReq_lat_0$wget[141:78] : - mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h180423 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h179511 ; - assign x__h180424 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180117 ; - assign x__h180646 = { vaddr__h180509[2:0], 3'b0 } ; - assign x__h190900 = - coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h190137[63:32] : - curData__h190137[31:0] ; - assign x__h20210 = - mmio_dataReqQ_enqReq_lat_0$whas ? - mmio_dataReqQ_enqReq_lat_0$wget[63:0] : - mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h284499 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : - 5'd0 ; - assign x__h284511 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : - 64'd0 ; - assign x__h286365 = - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? - (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : - coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : - 64'd0 ; - assign x__h299371 = + assign wordIdx__h263160 = + coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164] ; + assign x1_avValue_new_pcc_capFat_bounds_baseBits__h997994 = + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 ? + csrf_stcc_reg[13:0] : + csrf_mtcc_reg[13:0] ; + assign x__h1007116 = { 1'b0, csrf_spp_reg } ; + assign x__h1010892 = + NOT_rob_deqPort_0_canDeq__3151_3152_OR_rob_deq_ETC___d23371 ? + y_avValue_snd_snd_snd_fst__h1010714 : + IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23400 ; + assign x__h127272 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h127310 ; + assign x__h127310 = { tmp_expTopHalf__h127263, tmp_expBotHalf__h127265 } ; + assign x__h127470 = { impliedTopBits__h127403, topBits__h127399 } ; + assign x__h127487 = x__h127490[13:12] + carry_out__h127401 ; + assign x__h127490 = + INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? + { coreFix_memExe_respLrScAmoQ_data_0[77:67], 3'd0 } : + b_base__h127497 ; + assign x__h140188 = mmio_dataRespQ_data_0[63:0] >> x__h140226 ; + assign x__h140226 = { tmp_expTopHalf__h140179, tmp_expBotHalf__h140181 } ; + assign x__h140386 = { impliedTopBits__h140319, topBits__h140315 } ; + assign x__h140403 = x__h140406[13:12] + carry_out__h140317 ; + assign x__h140406 = + INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? + { mmio_dataRespQ_data_0[77:67], 3'd0 } : + b_base__h140413 ; + assign x__h148960 = + coreFix_memExe_reqLdQ_data_0_lat_0$whas ? + coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : + coreFix_memExe_reqLdQ_data_0_rl[68:64] ; + assign x__h152094 = { 3'd0, sbIdx__h151985 } ; + assign x__h183367 = + (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? + coreFix_memExe_respLrScAmoQ_data_0[127:0] : + { 64'd0, + IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d1913 } ; + assign x__h183449 = x__h183367[63:0] >> x__h183487 ; + assign x__h183487 = { tmp_expTopHalf__h183440, tmp_expBotHalf__h183442 } ; + assign x__h183647 = { impliedTopBits__h183580, topBits__h183576 } ; + assign x__h183664 = x__h183667[13:12] + carry_out__h183578 ; + assign x__h183667 = + INV_x83367_BITS_108_TO_90__q33[0] ? + { x__h183367[77:67], 3'd0 } : + b_base__h183674 ; + assign x__h199219 = + (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? + mmio_dataRespQ_data_0[127:0] : + { 64'd0, + IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d2079 } ; + assign x__h202200 = x__h199219[63:0] >> x__h202238 ; + assign x__h202238 = { tmp_expTopHalf__h202191, tmp_expBotHalf__h202193 } ; + assign x__h202398 = { impliedTopBits__h202331, topBits__h202327 } ; + assign x__h202415 = x__h202418[13:12] + carry_out__h202329 ; + assign x__h202418 = + INV_x99219_BITS_108_TO_90__q35[0] ? + { x__h199219[77:67], 3'd0 } : + b_base__h202425 ; + assign x__h216766 = coreFix_memExe_lsq$respLd[63:0] >> x__h216804 ; + assign x__h216804 = { tmp_expTopHalf__h216757, tmp_expBotHalf__h216759 } ; + assign x__h216964 = { impliedTopBits__h216897, topBits__h216893 } ; + assign x__h216981 = x__h216984[13:12] + carry_out__h216895 ; + assign x__h216984 = + INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? + { coreFix_memExe_lsq$respLd[77:67], 3'd0 } : + b_base__h216991 ; + assign x__h235690 = + (coreFix_memExe_dispToRegQ$first[109] && + coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? + IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3036 : + 66'd0 ; + assign x__h239653 = x__h239655 << coreFix_memExe_regToExeQ$first[264:259] ; + assign x__h239655 = { {48{offset__h239641[15]}}, offset__h239641 } ; + assign x__h239763 = + 66'h3FFFFFFFFFFFFFFFF << + coreFix_memExe_regToExeQ$first[264:259] ; + assign x__h239911 = + coreFix_memExe_regToExeQ_first__633_BITS_264_T_ETC___d3705 ? + result__h240541 : + ret__h239918 ; + assign x__h240013 = + { coreFix_memExe_regToExeQ$first[224:223], + coreFix_memExe_regToExeQ$first[258:245] } ; + assign x__h240082 = + (coreFix_memExe_regToExeQ$first[264:259] == 6'd50) ? + coreFix_memExe_regToExeQ$first[244] : + coreFix_memExe_regToExeQfirst_BITS_380_TO_331_ETC__q3[49] ; + assign x__h240810 = x__h240812 << coreFix_memExe_regToExeQ$first[101:96] ; + assign x__h240812 = { {48{offset__h240798[15]}}, offset__h240798 } ; + assign x__h240920 = + 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[101:96] ; + assign x__h241068 = + coreFix_memExe_regToExeQ_first__633_BITS_101_T_ETC___d3767 ? + result__h241698 : + ret__h241075 ; + assign x__h241170 = + { coreFix_memExe_regToExeQ$first[61:60], + coreFix_memExe_regToExeQ$first[95:82] } ; + assign x__h241239 = + (coreFix_memExe_regToExeQ$first[101:96] == 6'd50) ? + coreFix_memExe_regToExeQ$first[81] : + coreFix_memExe_regToExeQfirst_BITS_217_TO_168_ETC__q7[49] ; + assign x__h242605 = offset__h242559[63:14] ^ signBits__h242575 ; + assign x__h242708 = + offset__h242559 >> coreFix_memExe_regToExeQ$first[264:259] ; + assign x__h244610 = { pointer__h242569[3:0], 3'b0 } ; + assign x__h248052 = + pointer__h242569 >> coreFix_memExe_regToExeQ$first[264:259] ; + assign x__h249407 = x__h249419 + y__h249420 ; + assign x__h249419 = x__h249431 + y__h249432 ; + assign x__h249431 = x__h249443 + y__h249444 ; + assign x__h249443 = x__h249455 + y__h249456 ; + assign x__h249455 = x__h249467 + y__h249468 ; + assign x__h249467 = x__h249479 + y__h249480 ; + assign x__h249479 = x__h249491 + y__h249492 ; + assign x__h249491 = x__h249503 + y__h249504 ; + assign x__h249503 = x__h249515 + y__h249516 ; + assign x__h249515 = x__h249527 + y__h249528 ; + assign x__h249527 = x__h249539 + y__h249540 ; + assign x__h249539 = x__h249551 + y__h249552 ; + assign x__h249551 = x__h249563 + y__h249564 ; + assign x__h249563 = x__h249575 + y__h249576 ; + assign x__h249575 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; + assign x__h254419 = x__h254421 << coreFix_memExe_dTlb$procResp[334:329] ; + assign x__h254421 = { {48{offset__h254407[15]}}, offset__h254407 } ; + assign x__h254529 = + 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; + assign x__h254677 = + coreFix_memExe_dTlb_procResp__239_BITS_334_TO__ETC___d4402 ? + result__h255307 : + ret__h254684 ; + assign x__h254779 = + { coreFix_memExe_dTlb$procResp[294:293], + coreFix_memExe_dTlb$procResp[328:315] } ; + assign x__h254848 = + (coreFix_memExe_dTlb$procResp[334:329] == 6'd50) ? + coreFix_memExe_dTlb$procResp[314] : + coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q5[49] ; + assign x__h521603 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h335099 = - { (_theResult___exp__h378431 != 8'd255 || - _theResult___sfd__h378432 == 23'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136, - out_f_exp__h378708, - out_f_sfd__h378709 } ; - assign x__h361649 = - sfd__h335695 << (x__h361682[11] ? 12'hAAA : x__h361682) ; - assign x__h361682 = + assign x__h568180 = + { (_theResult___exp__h611512 != 8'd255 || + _theResult___sfd__h611513 == 23'd0) && + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9245, + out_f_exp__h611789, + out_f_sfd__h611790 } ; + assign x__h594730 = + sfd__h568776 << (x__h594763[11] ? 12'hAAA : x__h594763) ; + assign x__h594763 = 12'd57 - - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ; - assign x__h380794 = - { (_theResult___exp__h424121 != 8'd255 || - _theResult___sfd__h424122 == 23'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528, - out_f_exp__h424398, - out_f_sfd__h424399 } ; - assign x__h407339 = - sfd__h381390 << (x__h407372[11] ? 12'hAAA : x__h407372) ; - assign x__h407372 = + _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659 ; + assign x__h613934 = + { (_theResult___exp__h657261 != 8'd255 || + _theResult___sfd__h657262 == 23'd0) && + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10642, + out_f_exp__h657538, + out_f_sfd__h657539 } ; + assign x__h640479 = + sfd__h614530 << (x__h640512[11] ? 12'hAAA : x__h640512) ; + assign x__h640512 = 12'd57 - - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ; - assign x__h426482 = - { (_theResult___exp__h469809 != 8'd255 || - _theResult___sfd__h469810 == 23'd0) && - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920, - out_f_exp__h470086, - out_f_sfd__h470087 } ; - assign x__h453027 = - sfd__h427078 << (x__h453060[11] ? 12'hAAA : x__h453060) ; - assign x__h453060 = + _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056 ; + assign x__h65608 = mmio_pRqQ_data_0[31:0] ; + assign x__h659681 = + { (_theResult___exp__h703008 != 8'd255 || + _theResult___sfd__h703009 == 23'd0) && + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12039, + out_f_exp__h703285, + out_f_sfd__h703286 } ; + assign x__h686226 = + sfd__h660277 << (x__h686259[11] ? 12'hAAA : x__h686259) ; + assign x__h686259 = 12'd57 - - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ; - assign x__h45579 = + _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453 ; + assign x__h714355 = + sbCons$lazyLookup_2_get[3] ? + rf$read_2_rd1[149:86] : + y_avValue__h710401 ; + assign x__h714356 = + sbCons$lazyLookup_2_get[2] ? + rf$read_2_rd2[149:86] : + y_avValue__h711034 ; + assign x__h714357 = + sbCons$lazyLookup_2_get[1] ? + rf$read_2_rd3[149:86] : + y_avValue__h711661 ; + assign x__h736262 = sfd__h715187 << x__h736295 ; + assign x__h736295 = + 12'd57 - + _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12782 ; + assign x__h775115 = sfd__h754181 << x__h775148 ; + assign x__h775148 = + 12'd57 - + _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14267 ; + assign x__h814419 = sfd__h793485 << x__h814452 ; + assign x__h814452 = + 12'd57 - + _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13497 ; + assign x__h836069 = a__h835633[63] ^ b__h835634[63] ; + assign x__h852553 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h865509 = + coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h865547 ; + assign x__h865547 = { tmp_expTopHalf__h865499, tmp_expBotHalf__h865501 } ; + assign x__h865720 = { impliedTopBits__h865652, topBits__h865648 } ; + assign x__h865737 = x__h865740[13:12] + carry_out__h865650 ; + assign x__h865740 = + INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? + { coreFix_aluExe_1_regToExeQ$first[255:245], 3'd0 } : + b_base__h865747 ; + assign x__h866057 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h866095 ; + assign x__h866095 = { tmp_expTopHalf__h866047, tmp_expBotHalf__h866049 } ; + assign x__h866268 = { impliedTopBits__h866200, topBits__h866196 } ; + assign x__h866285 = x__h866288[13:12] + carry_out__h866198 ; + assign x__h866288 = + INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? + { coreFix_aluExe_1_regToExeQ$first[126:116], 3'd0 } : + b_base__h866295 ; + assign x__h878565 = + { coreFix_aluExe_1_exeToFinQ$first[623], + coreFix_aluExe_1_exeToFinQ$first[542:527], + coreFix_aluExe_1_exeToFinQ$first[525:524], + coreFix_aluExe_1_exeToFinQ$first[526], + ~coreFix_aluExe_1_exeToFinQ$first[523:505], + IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17854[25:17], + ~IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17854[16:15], + IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17854[14:3], + ~IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17854[2], + IF_coreFix_aluExe_1_exeToFinQ_first__7657_BIT__ETC___d17854[1:0], + coreFix_aluExe_1_exeToFinQ$first[620:557] } ; + assign x__h894178 = + { csrf_mccsr_reg[10:5], + CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q23, + 5'd3 } ; + assign x__h903990 = + coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h904028 ; + assign x__h904028 = { tmp_expTopHalf__h903980, tmp_expBotHalf__h903982 } ; + assign x__h904201 = { impliedTopBits__h904133, topBits__h904129 } ; + assign x__h904218 = x__h904221[13:12] + carry_out__h904131 ; + assign x__h904221 = + INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? + { coreFix_aluExe_0_regToExeQ$first[255:245], 3'd0 } : + b_base__h904228 ; + assign x__h904538 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h904576 ; + assign x__h904576 = { tmp_expTopHalf__h904528, tmp_expBotHalf__h904530 } ; + assign x__h904749 = { impliedTopBits__h904681, topBits__h904677 } ; + assign x__h904766 = x__h904769[13:12] + carry_out__h904679 ; + assign x__h904769 = + INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? + { coreFix_aluExe_0_regToExeQ$first[126:116], 3'd0 } : + b_base__h904776 ; + assign x__h912077 = + { coreFix_aluExe_0_exeToFinQ$first[623], + coreFix_aluExe_0_exeToFinQ$first[542:527], + coreFix_aluExe_0_exeToFinQ$first[525:524], + coreFix_aluExe_0_exeToFinQ$first[526], + ~coreFix_aluExe_0_exeToFinQ$first[523:505], + IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19931[25:17], + ~IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19931[16:15], + IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19931[14:3], + ~IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19931[2], + IF_coreFix_aluExe_0_exeToFinQ_first__9735_BIT__ETC___d19931[1:0], + coreFix_aluExe_0_exeToFinQ$first[620:557] } ; + assign x__h913266 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h913317 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h992018 = commitStage_commitTrap[172:109] >> x__h992056 ; + assign x__h992056 = { tmp_expTopHalf__h992009, tmp_expBotHalf__h992011 } ; + assign x__h992216 = { impliedTopBits__h992149, topBits__h992145 } ; + assign x__h992233 = x__h992236[13:12] + carry_out__h992147 ; + assign x__h992236 = + INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? + { commitStage_commitTrap[186:176], 3'd0 } : + b_base__h992243 ; + assign x__h994694 = + x__h994696 << + IF_INV_commitStage_commitTrap_2029_BITS_217_TO_ETC___d22341 ; + assign x__h994696 = { {48{offset__h994682[15]}}, offset__h994682 } ; + assign x__h994781 = + 66'h3FFFFFFFFFFFFFFFF << + IF_INV_commitStage_commitTrap_2029_BITS_217_TO_ETC___d22341 ; + assign x__h995968 = + { commitStage_commitTrap[42:37], + CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q24 } ; + assign x__h996668 = csrf_stcc_reg[33:28] + 6'd14 ; + assign x__h996694 = { cause_code__h992427, 2'b0 } ; + assign x__h996795 = address__h996601 >> csrf_stcc_reg[33:28] ; + assign x__h997099 = address__h996945 >> csrf_stcc_reg[33:28] ; + assign x__h997325 = csrf_mtcc_reg[33:28] + 6'd14 ; + assign x__h997452 = address__h997258 >> csrf_mtcc_reg[33:28] ; + assign x__h997756 = address__h997602 >> csrf_mtcc_reg[33:28] ; + assign x__h997991 = + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 ? + csrf_stcc_reg[27:14] : + csrf_mtcc_reg[27:14] ; + assign x__h998012 = + csrf_prv_reg_read__0075_ULE_1_2375_AND_IF_comm_ETC___d22408 ? + csrf_stcc_reg[33:28] : + csrf_mtcc_reg[33:28] ; + assign x_addr__h19852 = + mmio_dataReqQ_enqReq_lat_0$whas ? + mmio_dataReqQ_enqReq_lat_0$wget[214:151] : + mmio_dataReqQ_enqReq_rl[214:151] ; + assign x_addr__h44221 = mmio_cRqQ_enqReq_lat_0$whas ? - mmio_cRqQ_enqReq_lat_0$wget[141:78] : - mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h478868 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476004 ; - assign x__h478869 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h476612 ; - assign x__h478870 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477214 ; - assign x__h48115 = - mmio_cRqQ_enqReq_lat_0$whas ? - mmio_cRqQ_enqReq_lat_0$wget[63:0] : - mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h500723 = sfd__h479673 << x__h500756 ; - assign x__h500756 = - 12'd57 - - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ; - assign x__h539524 = sfd__h518615 << x__h539557 ; - assign x__h539557 = - 12'd57 - - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ; - assign x__h578725 = sfd__h557816 << x__h578758 ; - assign x__h578758 = - 12'd57 - - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ; - assign x__h600273 = a__h599837[63] ^ b__h599838[63] ; - assign x__h608823 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h613034 = - coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h605871 : - v__h604755 ; - assign x__h613035 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h610923 ; - assign x__h634254 = - coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h629404 : - v__h628443 ; - assign x__h634255 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h632153 ; - assign x__h641102 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h641153 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h688723 = - (!rob$deqPort_0_deq_data[166] && - (rob$deqPort_0_deq_data[165:162] == 4'd1 || - rob$deqPort_0_deq_data[165:162] == 4'd12)) ? - rob$deqPort_0_deq_data[161:98] : - rob$deqPort_0_deq_data[95:32] ; - assign x__h694804 = { cause_code__h692187, 2'b0 } ; - assign x__h702600 = { 1'b0, csrf_spp_reg } ; - assign x__h705873 = - NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_snd_snd_fst__h705695 : - IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 ; - assign x__h75524 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h311294 = + mmio_cRqQ_enqReq_lat_0$wget[214:151] : + mmio_cRqQ_enqReq_rl[214:151] ; + assign x_addr__h535302 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; - assign x_data__h65373 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[582:519] : + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[582:519] ; + assign x_data__h60109 = EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h667947 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h682690 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h649135 = csrf_frm_reg ; - assign x_quotient__h472393 = + assign x_decodeInfo_frm__h923668 = csrf_frm_reg ; + assign x_quotient__h705674 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h473078 : + q___1__h706385 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h606254 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h472394 = + assign x_reg_ifc__read__h849175 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h705675 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h473104 : + r___1__h706411 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h252024 = - { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h641132 = ~x__h641102 ; - assign y__h645905 = - { 3'd7, + assign y__h1010667 = + NOT_rob_deqPort_0_canDeq__3151_3152_OR_rob_deq_ETC___d23371 ? + y_avValue_snd_snd_snd_snd_snd__h1010720 : + IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23272 ; + assign y__h239762 = ~x__h239763 ; + assign y__h240919 = ~x__h240920 ; + assign y__h249408 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; + assign y__h249420 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; + assign y__h249432 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; + assign y__h249444 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; + assign y__h249456 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; + assign y__h249468 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; + assign y__h249480 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; + assign y__h249492 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; + assign y__h249504 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; + assign y__h249516 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; + assign y__h249528 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; + assign y__h249540 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; + assign y__h249552 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; + assign y__h249564 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; + assign y__h249576 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; + assign y__h254528 = ~x__h254529 ; + assign y__h422493 = + { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:522], + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[168:164] } ; + assign y__h913296 = ~x__h913266 ; + assign y__h918226 = + { 4'd15, ~csrf_mideleg_11_reg, 1'd1, ~csrf_mideleg_9_7_reg, @@ -29460,202 +37509,144 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h678454 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h705648 = - NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_snd_snd_snd_snd__h705701 : - IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 ; - assign y_avValue__h179511 = - NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ? - coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 ; - assign y_avValue__h180117 = - NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ? - coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 ; - assign y_avValue__h476004 = - NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230 ? - coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334 ; - assign y_avValue__h476612 = - NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8257 ? - coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345 ; - assign y_avValue__h477214 = - NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8281 ? - coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8356 ; - assign y_avValue__h605661 = - NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11330 ? - coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11708 ; - assign y_avValue__h610923 = - NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11358 ? - coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11720 ; - assign y_avValue__h629196 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12125 ? - coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12317 ; - assign y_avValue__h632153 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12153 ? - coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12329 ; - assign y_avValue__h693065 = - (csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h694789 + { 58'd0, x__h694804 } : - base__h694789 ; - assign y_avValue__h694826 = - (csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h694992 + { 58'd0, x__h694804 } : - base__h694992 ; - assign y_avValue_fst__h671838 = - (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h678441 : + assign y__h970987 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h994780 = ~x__h994781 ; + assign y__h996724 = { mask__h996607[62:0], 1'd0 } ; + assign y__h997381 = { mask__h997264[62:0], 1'd0 } ; + assign y_avValue__h710401 = + NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12363 ? + coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12468 ; + assign y_avValue__h711034 = + NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12390 ? + coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12480 ; + assign y_avValue__h711661 = + NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12414 ? + coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : + IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12492 ; + assign y_avValue_fst__h960364 = + (fetchStage$pipelines_0_first[267:265] == 3'd1) ? + spec_bits__h970974 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h672112 = - ((fetchStage$pipelines_0_first[194:192] != 3'd1 || - specTagManager$canClaim) && - regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207) ? - y_avValue_snd_fst__h672147 : - specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h672147 = - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 ? - y_avValue_fst__h671838 : - specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h705132 = + assign y_avValue_snd_fst__h1010122 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || - rob$deqPort_0_deq_data[167] || - rob$deqPort_0_deq_data[186:182] == 5'd0 || - rob$deqPort_0_deq_data[186:182] == 5'd21 || - rob$deqPort_0_deq_data[186:182] == 5'd17 || - rob$deqPort_0_deq_data[186:182] == 5'd18 || - rob$deqPort_0_deq_data[186:182] == 5'd13 || - rob$deqPort_0_deq_data[186:182] == 5'd16 || - rob$deqPort_0_deq_data[186:182] == 5'd15 || - rob$deqPort_0_deq_data[186:182] == 5'd19 || - rob$deqPort_0_deq_data[186:182] == 5'd20) ? + rob$deqPort_0_deq_data[274] || + rob$deqPort_0_deq_data[469:465] == 5'd0 || + rob$deqPort_0_deq_data[469:465] == 5'd26 || + rob$deqPort_0_deq_data[469:465] == 5'd22 || + rob$deqPort_0_deq_data[469:465] == 5'd23 || + rob$deqPort_0_deq_data[469:465] == 5'd17 || + rob$deqPort_0_deq_data[469:465] == 5'd18 || + rob$deqPort_0_deq_data[469:465] == 5'd21 || + rob$deqPort_0_deq_data[469:465] == 5'd20 || + rob$deqPort_0_deq_data[469:465] == 5'd24 || + rob$deqPort_0_deq_data[469:465] == 5'd25) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h705685 = + assign y_avValue_snd_fst__h1010704 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || - rob$deqPort_1_deq_data[167] || - rob$deqPort_1_deq_data[186:182] == 5'd0 || - rob$deqPort_1_deq_data[186:182] == 5'd21 || - rob$deqPort_1_deq_data[186:182] == 5'd17 || - rob$deqPort_1_deq_data[186:182] == 5'd18 || - rob$deqPort_1_deq_data[186:182] == 5'd13 || - rob$deqPort_1_deq_data[186:182] == 5'd16 || - rob$deqPort_1_deq_data[186:182] == 5'd15 || - rob$deqPort_1_deq_data[186:182] == 5'd19 || - rob$deqPort_1_deq_data[186:182] == 5'd20) ? - IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 : - y_avValue_snd_fst__h705714 ; - assign y_avValue_snd_fst__h705714 = - IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 | + rob$deqPort_1_deq_data[274] || + rob$deqPort_1_deq_data[469:465] == 5'd0 || + rob$deqPort_1_deq_data[469:465] == 5'd26 || + rob$deqPort_1_deq_data[469:465] == 5'd22 || + rob$deqPort_1_deq_data[469:465] == 5'd23 || + rob$deqPort_1_deq_data[469:465] == 5'd17 || + rob$deqPort_1_deq_data[469:465] == 5'd18 || + rob$deqPort_1_deq_data[469:465] == 5'd21 || + rob$deqPort_1_deq_data[469:465] == 5'd20 || + rob$deqPort_1_deq_data[469:465] == 5'd24 || + rob$deqPort_1_deq_data[469:465] == 5'd25) ? + IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23378 : + y_avValue_snd_fst__h1010733 ; + assign y_avValue_snd_fst__h1010733 = + IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23378 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_snd_snd_fst__h705142 = + assign y_avValue_snd_fst__h960652 = + ((fetchStage$pipelines_0_first[267:265] != 3'd1 || + specTagManager$canClaim) && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958) ? + y_avValue_snd_fst__h960694 : + specTagManager$currentSpecBits ; + assign y_avValue_snd_fst__h960694 = + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21020 ? + y_avValue_fst__h960364 : + specTagManager$currentSpecBits ; + assign y_avValue_snd_snd_snd_fst__h1010132 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || - rob$deqPort_0_deq_data[167] || - rob$deqPort_0_deq_data[186:182] == 5'd0 || - rob$deqPort_0_deq_data[186:182] == 5'd21 || - rob$deqPort_0_deq_data[186:182] == 5'd17 || - rob$deqPort_0_deq_data[186:182] == 5'd18 || - rob$deqPort_0_deq_data[186:182] == 5'd13 || - rob$deqPort_0_deq_data[186:182] == 5'd16 || - rob$deqPort_0_deq_data[186:182] == 5'd15 || - rob$deqPort_0_deq_data[186:182] == 5'd19 || - rob$deqPort_0_deq_data[186:182] == 5'd20) ? + rob$deqPort_0_deq_data[274] || + rob$deqPort_0_deq_data[469:465] == 5'd0 || + rob$deqPort_0_deq_data[469:465] == 5'd26 || + rob$deqPort_0_deq_data[469:465] == 5'd22 || + rob$deqPort_0_deq_data[469:465] == 5'd23 || + rob$deqPort_0_deq_data[469:465] == 5'd17 || + rob$deqPort_0_deq_data[469:465] == 5'd18 || + rob$deqPort_0_deq_data[469:465] == 5'd21 || + rob$deqPort_0_deq_data[469:465] == 5'd20 || + rob$deqPort_0_deq_data[469:465] == 5'd24 || + rob$deqPort_0_deq_data[469:465] == 5'd25) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h705695 = + assign y_avValue_snd_snd_snd_fst__h1010714 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || - rob$deqPort_1_deq_data[167] || - rob$deqPort_1_deq_data[186:182] == 5'd0 || - rob$deqPort_1_deq_data[186:182] == 5'd21 || - rob$deqPort_1_deq_data[186:182] == 5'd17 || - rob$deqPort_1_deq_data[186:182] == 5'd18 || - rob$deqPort_1_deq_data[186:182] == 5'd13 || - rob$deqPort_1_deq_data[186:182] == 5'd16 || - rob$deqPort_1_deq_data[186:182] == 5'd15 || - rob$deqPort_1_deq_data[186:182] == 5'd19 || - rob$deqPort_1_deq_data[186:182] == 5'd20) ? - IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 : - y_avValue_snd_snd_snd_fst__h705724 ; - assign y_avValue_snd_snd_snd_fst__h705724 = - IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 + + rob$deqPort_1_deq_data[274] || + rob$deqPort_1_deq_data[469:465] == 5'd0 || + rob$deqPort_1_deq_data[469:465] == 5'd26 || + rob$deqPort_1_deq_data[469:465] == 5'd22 || + rob$deqPort_1_deq_data[469:465] == 5'd23 || + rob$deqPort_1_deq_data[469:465] == 5'd17 || + rob$deqPort_1_deq_data[469:465] == 5'd18 || + rob$deqPort_1_deq_data[469:465] == 5'd21 || + rob$deqPort_1_deq_data[469:465] == 5'd20 || + rob$deqPort_1_deq_data[469:465] == 5'd24 || + rob$deqPort_1_deq_data[469:465] == 5'd25) ? + IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23400 : + y_avValue_snd_snd_snd_fst__h1010743 ; + assign y_avValue_snd_snd_snd_fst__h1010743 = + IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23400 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h705148 = + assign y_avValue_snd_snd_snd_snd_snd__h1010138 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || - rob$deqPort_0_deq_data[167] || - rob$deqPort_0_deq_data[186:182] == 5'd0 || - rob$deqPort_0_deq_data[186:182] == 5'd21 || - rob$deqPort_0_deq_data[186:182] == 5'd17 || - rob$deqPort_0_deq_data[186:182] == 5'd18 || - rob$deqPort_0_deq_data[186:182] == 5'd13 || - rob$deqPort_0_deq_data[186:182] == 5'd16 || - rob$deqPort_0_deq_data[186:182] == 5'd15 || - rob$deqPort_0_deq_data[186:182] == 5'd19 || - rob$deqPort_0_deq_data[186:182] == 5'd20) ? + rob$deqPort_0_deq_data[274] || + rob$deqPort_0_deq_data[469:465] == 5'd0 || + rob$deqPort_0_deq_data[469:465] == 5'd26 || + rob$deqPort_0_deq_data[469:465] == 5'd22 || + rob$deqPort_0_deq_data[469:465] == 5'd23 || + rob$deqPort_0_deq_data[469:465] == 5'd17 || + rob$deqPort_0_deq_data[469:465] == 5'd18 || + rob$deqPort_0_deq_data[469:465] == 5'd21 || + rob$deqPort_0_deq_data[469:465] == 5'd20 || + rob$deqPort_0_deq_data[469:465] == 5'd24 || + rob$deqPort_0_deq_data[469:465] == 5'd25) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h705701 = + assign y_avValue_snd_snd_snd_snd_snd__h1010720 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || - rob$deqPort_1_deq_data[167] || - rob$deqPort_1_deq_data[186:182] == 5'd0 || - rob$deqPort_1_deq_data[186:182] == 5'd21 || - rob$deqPort_1_deq_data[186:182] == 5'd17 || - rob$deqPort_1_deq_data[186:182] == 5'd18 || - rob$deqPort_1_deq_data[186:182] == 5'd13 || - rob$deqPort_1_deq_data[186:182] == 5'd16 || - rob$deqPort_1_deq_data[186:182] == 5'd15 || - rob$deqPort_1_deq_data[186:182] == 5'd19 || - rob$deqPort_1_deq_data[186:182] == 5'd20) ? - IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 : - y_avValue_snd_snd_snd_snd_snd__h705730 ; - assign y_avValue_snd_snd_snd_snd_snd__h705730 = - IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 + + rob$deqPort_1_deq_data[274] || + rob$deqPort_1_deq_data[469:465] == 5'd0 || + rob$deqPort_1_deq_data[469:465] == 5'd26 || + rob$deqPort_1_deq_data[469:465] == 5'd22 || + rob$deqPort_1_deq_data[469:465] == 5'd23 || + rob$deqPort_1_deq_data[469:465] == 5'd17 || + rob$deqPort_1_deq_data[469:465] == 5'd18 || + rob$deqPort_1_deq_data[469:465] == 5'd21 || + rob$deqPort_1_deq_data[469:465] == 5'd20 || + rob$deqPort_1_deq_data[469:465] == 5'd24 || + rob$deqPort_1_deq_data[469:465] == 5'd25) ? + IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23272 : + y_avValue_snd_snd_snd_snd_snd__h1010749 ; + assign y_avValue_snd_snd_snd_snd_snd__h1010749 = + IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23272 + 64'd1 ; always@(mmio_cRqQ_data_0) begin - case (mmio_cRqQ_data_0[77:76]) + case (mmio_cRqQ_data_0[150:149]) 2'd0, 2'd1, 2'd2: - CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1 = - mmio_cRqQ_data_0[77:72]; + CASE_mmio_cRqQ_data_0_BITS_150_TO_149_0_mmio_c_ETC__q1 = + mmio_cRqQ_data_0[150:145]; 2'd3: - CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1 = - { 2'd3, mmio_cRqQ_data_0[75:72] }; - endcase - end - always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) - 3'd0: - x__h194347 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; - 3'd1: - x__h194347 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; - 3'd2: - x__h194347 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; - 3'd3: - x__h194347 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; - 3'd4: - x__h194347 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; - 3'd5: - x__h194347 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; - 3'd6: - x__h194347 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; - 3'd7: - x__h194347 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; + CASE_mmio_cRqQ_data_0_BITS_150_TO_149_0_mmio_c_ETC__q1 = + { 2'd3, mmio_cRqQ_data_0[148:145] }; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP or @@ -29670,28 +37661,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h283066 = + x__h501025 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h283066 = + x__h501025 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h283066 = + x__h501025 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h283066 = + x__h501025 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h283066 = + x__h501025 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h283066 = + x__h501025 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h283066 = + x__h501025 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h283066 = + x__h501025 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -29701,54 +37692,169 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h287287 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; + addr__h505543 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[585:522]; 1'd1: - addr__h287287 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; + addr__h505543 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[585:522]; + endcase + end + always@(coreFix_memExe_memRespLdQ_deqP or + coreFix_memExe_memRespLdQ_data_0 or + coreFix_memExe_memRespLdQ_data_1) + begin + case (coreFix_memExe_memRespLdQ_deqP) + 1'd0: t__h212809 = coreFix_memExe_memRespLdQ_data_0[133:129]; + 1'd1: t__h212809 = coreFix_memExe_memRespLdQ_data_1[133:129]; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: t__h215095 = coreFix_memExe_forwardQ_data_0[133:129]; + 1'd1: t__h215095 = coreFix_memExe_forwardQ_data_1[133:129]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) begin - case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) - 3'd0: - curData__h190137 = + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165]) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q17 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; - 3'd1: - curData__h190137 = + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q17 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; - 3'd2: - curData__h190137 = + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165]) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; - 3'd3: - curData__h190137 = + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; - 3'd4: - curData__h190137 = + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165]) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; - 3'd5: - curData__h190137 = + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; - 3'd6: - curData__h190137 = + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165]) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; - 3'd7: - curData__h190137 = + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q17 or + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18 or + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19 or + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) + 2'd0: + x__h264659 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q17; + 2'd1: + x__h264659 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18; + 2'd2: + x__h264659 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19; + 2'd3: + x__h264659 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20; + endcase + end always@(commitStage_commitTrap) begin - case (commitStage_commitTrap[3:0]) - 4'd0, 4'd3: trap_val__h693218 = commitStage_commitTrap[132:69]; - default: trap_val__h693218 = - (commitStage_commitTrap[3:0] != 4'd2 && - commitStage_commitTrap[3:0] != 4'd8 && - commitStage_commitTrap[3:0] != 4'd9 && - commitStage_commitTrap[3:0] != 4'd11) ? - commitStage_commitTrap[68:5] : - 64'd0; + case (commitStage_commitTrap[35:32]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + i__h992617 = commitStage_commitTrap[35:32]; + default: i__h992617 = 4'd15; + endcase + end + always@(csrf_mccsr_reg) + begin + case (csrf_mccsr_reg[4:0]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd10, + 5'd11, + 5'd16, + 5'd17, + 5'd18, + 5'd19, + 5'd20, + 5'd21, + 5'd22, + 5'd23, + 5'd24, + 5'd25, + 5'd26: + CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q23 = + csrf_mccsr_reg[4:0]; + default: CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q23 = + 5'd27; + endcase + end + always@(commitStage_commitTrap) + begin + case (commitStage_commitTrap[36:32]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd10, + 5'd11, + 5'd16, + 5'd17, + 5'd18, + 5'd19, + 5'd20, + 5'd21, + 5'd22, + 5'd23, + 5'd24, + 5'd25, + 5'd26: + CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q24 = + commitStage_commitTrap[36:32]; + default: CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q24 = + 5'd27; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or @@ -29757,517 +37863,903 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h288836 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h508693 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h288836 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h508693 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + endcase + end + always@(f_csr_reqs$D_OUT or + fflags_csr__read__h849045 or + frm_csr__read__h849056 or + fcsr_csr__read__h849070 or + sstatus_csr__read__h849266 or + sie_csr__read__h849336 or + scounteren_csr__read__h849389 or + csrf_sscratch_csr or + scause_csr__read__h849484 or + csrf_stval_csr or + sip_csr__read__h849624 or + satp_csr__read__h849687 or + mstatus_csr__read__h849833 or + medeleg_csr__read__h849987 or + mideleg_csr__read__h850085 or + mie_csr__read__h850212 or + mcounteren_csr__read__h850307 or + csrf_mscratch_csr or + mcause_csr__read__h850486 or + csrf_mtval_csr or + mip_csr__read__h850725 or + csrf_rg_tselect or + rg_tdata1__read__h851826 or + csrf_rg_tdata2 or + csrf_rg_tdata3 or + csrf_rg_dcsr or + csrf_rg_dscratch0 or + csrf_rg_dscratch1 or + x_reg_ifc__read__h849175 or + csrf_mcycle_ehr_data_rl or + csrf_minstret_ehr_data_rl or x__h894178 or csrf_time_reg) + begin + case (f_csr_reqs$D_OUT[75:64]) + 12'd1: data_out__h1014318 = fflags_csr__read__h849045; + 12'd2: data_out__h1014318 = frm_csr__read__h849056; + 12'd3: data_out__h1014318 = fcsr_csr__read__h849070; + 12'd256: data_out__h1014318 = sstatus_csr__read__h849266; + 12'd260: data_out__h1014318 = sie_csr__read__h849336; + 12'd262: data_out__h1014318 = scounteren_csr__read__h849389; + 12'd320: data_out__h1014318 = csrf_sscratch_csr; + 12'd322: data_out__h1014318 = scause_csr__read__h849484; + 12'd323: data_out__h1014318 = csrf_stval_csr; + 12'd324: data_out__h1014318 = sip_csr__read__h849624; + 12'd384: data_out__h1014318 = satp_csr__read__h849687; + 12'd768: data_out__h1014318 = mstatus_csr__read__h849833; + 12'd769: data_out__h1014318 = 64'h800000000014112D; + 12'd770: data_out__h1014318 = medeleg_csr__read__h849987; + 12'd771: data_out__h1014318 = mideleg_csr__read__h850085; + 12'd772: data_out__h1014318 = mie_csr__read__h850212; + 12'd774: data_out__h1014318 = mcounteren_csr__read__h850307; + 12'd832: data_out__h1014318 = csrf_mscratch_csr; + 12'd834: data_out__h1014318 = mcause_csr__read__h850486; + 12'd835: data_out__h1014318 = csrf_mtval_csr; + 12'd836: data_out__h1014318 = mip_csr__read__h850725; + 12'd1952: data_out__h1014318 = csrf_rg_tselect; + 12'd1953: data_out__h1014318 = rg_tdata1__read__h851826; + 12'd1954: data_out__h1014318 = csrf_rg_tdata2; + 12'd1955: data_out__h1014318 = csrf_rg_tdata3; + 12'd1968: data_out__h1014318 = csrf_rg_dcsr; + 12'd1970: data_out__h1014318 = csrf_rg_dscratch0; + 12'd1971: data_out__h1014318 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: + data_out__h1014318 = 64'd0; + 12'd2049: data_out__h1014318 = x_reg_ifc__read__h849175; + 12'd2816, 12'd3072: data_out__h1014318 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: data_out__h1014318 = csrf_minstret_ehr_data_rl; + 12'd3008: data_out__h1014318 = { 48'd0, x__h894178 }; + 12'd3073: data_out__h1014318 = csrf_time_reg; + default: data_out__h1014318 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h606124 or - frm_csr__read__h606135 or - fcsr_csr__read__h606149 or - sstatus_csr__read__h606345 or - sie_csr__read__h606414 or - stvec_csr__read__h606457 or - scounteren_csr__read__h606510 or + fflags_csr__read__h849045 or + frm_csr__read__h849056 or + fcsr_csr__read__h849070 or + sstatus_csr__read__h849266 or + sie_csr__read__h849336 or + scounteren_csr__read__h849389 or csrf_sscratch_csr or - csrf_sepc_csr or - scause_csr__read__h606648 or + scause_csr__read__h849484 or csrf_stval_csr or - sip_csr__read__h606787 or - satp_csr__read__h606850 or - mstatus_csr__read__h606993 or - medeleg_csr__read__h607141 or - mideleg_csr__read__h607236 or - mie_csr__read__h607367 or - mtvec_csr__read__h607449 or - mcounteren_csr__read__h607541 or + sip_csr__read__h849624 or + satp_csr__read__h849687 or + mstatus_csr__read__h849833 or + medeleg_csr__read__h849987 or + mideleg_csr__read__h850085 or + mie_csr__read__h850212 or + mcounteren_csr__read__h850307 or csrf_mscratch_csr or - csrf_mepc_csr or - mcause_csr__read__h607796 or + mcause_csr__read__h850486 or csrf_mtval_csr or - mip_csr__read__h608036 or - x_reg_ifc__read__h606254 or - n__read__h608140 or n__read__h608331 or csrf_time_reg) + mip_csr__read__h850725 or + csrf_rg_tselect or + rg_tdata1__read__h851826 or + csrf_rg_tdata2 or + csrf_rg_tdata3 or + csrf_rg_dcsr or + csrf_rg_dscratch0 or + csrf_rg_dscratch1 or + x_reg_ifc__read__h849175 or + csrf_mcycle_ehr_data_rl or + csrf_minstret_ehr_data_rl or x__h894178 or csrf_time_reg) begin - case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h605871 = fflags_csr__read__h606124; - 12'd2: rVal1__h605871 = frm_csr__read__h606135; - 12'd3: rVal1__h605871 = fcsr_csr__read__h606149; - 12'd256: rVal1__h605871 = sstatus_csr__read__h606345; - 12'd260: rVal1__h605871 = sie_csr__read__h606414; - 12'd261: rVal1__h605871 = stvec_csr__read__h606457; - 12'd262: rVal1__h605871 = scounteren_csr__read__h606510; - 12'd320: rVal1__h605871 = csrf_sscratch_csr; - 12'd321: rVal1__h605871 = csrf_sepc_csr; - 12'd322: rVal1__h605871 = scause_csr__read__h606648; - 12'd323: rVal1__h605871 = csrf_stval_csr; - 12'd324: rVal1__h605871 = sip_csr__read__h606787; - 12'd384: rVal1__h605871 = satp_csr__read__h606850; - 12'd768: rVal1__h605871 = mstatus_csr__read__h606993; - 12'd769: rVal1__h605871 = 64'h8000000000141129; - 12'd770: rVal1__h605871 = medeleg_csr__read__h607141; - 12'd771: rVal1__h605871 = mideleg_csr__read__h607236; - 12'd772: rVal1__h605871 = mie_csr__read__h607367; - 12'd773: rVal1__h605871 = mtvec_csr__read__h607449; - 12'd774: rVal1__h605871 = mcounteren_csr__read__h607541; - 12'd832: rVal1__h605871 = csrf_mscratch_csr; - 12'd833: rVal1__h605871 = csrf_mepc_csr; - 12'd834: rVal1__h605871 = mcause_csr__read__h607796; - 12'd835: rVal1__h605871 = csrf_mtval_csr; - 12'd836: rVal1__h605871 = mip_csr__read__h608036; - 12'd2048: rVal1__h605871 = 64'd0; - 12'd2049: rVal1__h605871 = x_reg_ifc__read__h606254; - 12'd2816, 12'd3072: rVal1__h605871 = n__read__h608140; - 12'd2818, 12'd3074: rVal1__h605871 = n__read__h608331; - 12'd3073: rVal1__h605871 = csrf_time_reg; - default: rVal1__h605871 = 64'd0; + case (coreFix_aluExe_1_dispToRegQ$first[136:125]) + 12'd1: addr__h843839 = fflags_csr__read__h849045; + 12'd2: addr__h843839 = frm_csr__read__h849056; + 12'd3: addr__h843839 = fcsr_csr__read__h849070; + 12'd256: addr__h843839 = sstatus_csr__read__h849266; + 12'd260: addr__h843839 = sie_csr__read__h849336; + 12'd262: addr__h843839 = scounteren_csr__read__h849389; + 12'd320: addr__h843839 = csrf_sscratch_csr; + 12'd322: addr__h843839 = scause_csr__read__h849484; + 12'd323: addr__h843839 = csrf_stval_csr; + 12'd324: addr__h843839 = sip_csr__read__h849624; + 12'd384: addr__h843839 = satp_csr__read__h849687; + 12'd768: addr__h843839 = mstatus_csr__read__h849833; + 12'd769: addr__h843839 = 64'h800000000014112D; + 12'd770: addr__h843839 = medeleg_csr__read__h849987; + 12'd771: addr__h843839 = mideleg_csr__read__h850085; + 12'd772: addr__h843839 = mie_csr__read__h850212; + 12'd774: addr__h843839 = mcounteren_csr__read__h850307; + 12'd832: addr__h843839 = csrf_mscratch_csr; + 12'd834: addr__h843839 = mcause_csr__read__h850486; + 12'd835: addr__h843839 = csrf_mtval_csr; + 12'd836: addr__h843839 = mip_csr__read__h850725; + 12'd1952: addr__h843839 = csrf_rg_tselect; + 12'd1953: addr__h843839 = rg_tdata1__read__h851826; + 12'd1954: addr__h843839 = csrf_rg_tdata2; + 12'd1955: addr__h843839 = csrf_rg_tdata3; + 12'd1968: addr__h843839 = csrf_rg_dcsr; + 12'd1970: addr__h843839 = csrf_rg_dscratch0; + 12'd1971: addr__h843839 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h843839 = 64'd0; + 12'd2049: addr__h843839 = x_reg_ifc__read__h849175; + 12'd2816, 12'd3072: addr__h843839 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h843839 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h843839 = { 48'd0, x__h894178 }; + 12'd3073: addr__h843839 = csrf_time_reg; + default: addr__h843839 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h606124 or - frm_csr__read__h606135 or - fcsr_csr__read__h606149 or - sstatus_csr__read__h606345 or - sie_csr__read__h606414 or - stvec_csr__read__h606457 or - scounteren_csr__read__h606510 or + fflags_csr__read__h849045 or + frm_csr__read__h849056 or + fcsr_csr__read__h849070 or + sstatus_csr__read__h849266 or + sie_csr__read__h849336 or + scounteren_csr__read__h849389 or csrf_sscratch_csr or - csrf_sepc_csr or - scause_csr__read__h606648 or + scause_csr__read__h849484 or csrf_stval_csr or - sip_csr__read__h606787 or - satp_csr__read__h606850 or - mstatus_csr__read__h606993 or - medeleg_csr__read__h607141 or - mideleg_csr__read__h607236 or - mie_csr__read__h607367 or - mtvec_csr__read__h607449 or - mcounteren_csr__read__h607541 or + sip_csr__read__h849624 or + satp_csr__read__h849687 or + mstatus_csr__read__h849833 or + medeleg_csr__read__h849987 or + mideleg_csr__read__h850085 or + mie_csr__read__h850212 or + mcounteren_csr__read__h850307 or csrf_mscratch_csr or - csrf_mepc_csr or - mcause_csr__read__h607796 or + mcause_csr__read__h850486 or csrf_mtval_csr or - mip_csr__read__h608036 or - x_reg_ifc__read__h606254 or - n__read__h608140 or n__read__h608331 or csrf_time_reg) + mip_csr__read__h850725 or + csrf_rg_tselect or + rg_tdata1__read__h851826 or + csrf_rg_tdata2 or + csrf_rg_tdata3 or + csrf_rg_dcsr or + csrf_rg_dscratch0 or + csrf_rg_dscratch1 or + x_reg_ifc__read__h849175 or + csrf_mcycle_ehr_data_rl or + csrf_minstret_ehr_data_rl or x__h894178 or csrf_time_reg) begin - case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h629404 = fflags_csr__read__h606124; - 12'd2: rVal1__h629404 = frm_csr__read__h606135; - 12'd3: rVal1__h629404 = fcsr_csr__read__h606149; - 12'd256: rVal1__h629404 = sstatus_csr__read__h606345; - 12'd260: rVal1__h629404 = sie_csr__read__h606414; - 12'd261: rVal1__h629404 = stvec_csr__read__h606457; - 12'd262: rVal1__h629404 = scounteren_csr__read__h606510; - 12'd320: rVal1__h629404 = csrf_sscratch_csr; - 12'd321: rVal1__h629404 = csrf_sepc_csr; - 12'd322: rVal1__h629404 = scause_csr__read__h606648; - 12'd323: rVal1__h629404 = csrf_stval_csr; - 12'd324: rVal1__h629404 = sip_csr__read__h606787; - 12'd384: rVal1__h629404 = satp_csr__read__h606850; - 12'd768: rVal1__h629404 = mstatus_csr__read__h606993; - 12'd769: rVal1__h629404 = 64'h8000000000141129; - 12'd770: rVal1__h629404 = medeleg_csr__read__h607141; - 12'd771: rVal1__h629404 = mideleg_csr__read__h607236; - 12'd772: rVal1__h629404 = mie_csr__read__h607367; - 12'd773: rVal1__h629404 = mtvec_csr__read__h607449; - 12'd774: rVal1__h629404 = mcounteren_csr__read__h607541; - 12'd832: rVal1__h629404 = csrf_mscratch_csr; - 12'd833: rVal1__h629404 = csrf_mepc_csr; - 12'd834: rVal1__h629404 = mcause_csr__read__h607796; - 12'd835: rVal1__h629404 = csrf_mtval_csr; - 12'd836: rVal1__h629404 = mip_csr__read__h608036; - 12'd2048: rVal1__h629404 = 64'd0; - 12'd2049: rVal1__h629404 = x_reg_ifc__read__h606254; - 12'd2816, 12'd3072: rVal1__h629404 = n__read__h608140; - 12'd2818, 12'd3074: rVal1__h629404 = n__read__h608331; - 12'd3073: rVal1__h629404 = csrf_time_reg; - default: rVal1__h629404 = 64'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h388974 = 8'd255; - 3'd2: - _theResult___fst_exp__h388974 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h388974 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h388974 = 8'd254; - default: _theResult___fst_exp__h388974 = 8'd0; + case (coreFix_aluExe_0_dispToRegQ$first[136:125]) + 12'd1: addr__h886084 = fflags_csr__read__h849045; + 12'd2: addr__h886084 = frm_csr__read__h849056; + 12'd3: addr__h886084 = fcsr_csr__read__h849070; + 12'd256: addr__h886084 = sstatus_csr__read__h849266; + 12'd260: addr__h886084 = sie_csr__read__h849336; + 12'd262: addr__h886084 = scounteren_csr__read__h849389; + 12'd320: addr__h886084 = csrf_sscratch_csr; + 12'd322: addr__h886084 = scause_csr__read__h849484; + 12'd323: addr__h886084 = csrf_stval_csr; + 12'd324: addr__h886084 = sip_csr__read__h849624; + 12'd384: addr__h886084 = satp_csr__read__h849687; + 12'd768: addr__h886084 = mstatus_csr__read__h849833; + 12'd769: addr__h886084 = 64'h800000000014112D; + 12'd770: addr__h886084 = medeleg_csr__read__h849987; + 12'd771: addr__h886084 = mideleg_csr__read__h850085; + 12'd772: addr__h886084 = mie_csr__read__h850212; + 12'd774: addr__h886084 = mcounteren_csr__read__h850307; + 12'd832: addr__h886084 = csrf_mscratch_csr; + 12'd834: addr__h886084 = mcause_csr__read__h850486; + 12'd835: addr__h886084 = csrf_mtval_csr; + 12'd836: addr__h886084 = mip_csr__read__h850725; + 12'd1952: addr__h886084 = csrf_rg_tselect; + 12'd1953: addr__h886084 = rg_tdata1__read__h851826; + 12'd1954: addr__h886084 = csrf_rg_tdata2; + 12'd1955: addr__h886084 = csrf_rg_tdata3; + 12'd1968: addr__h886084 = csrf_rg_dcsr; + 12'd1970: addr__h886084 = csrf_rg_dscratch0; + 12'd1971: addr__h886084 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h886084 = 64'd0; + 12'd2049: addr__h886084 = x_reg_ifc__read__h849175; + 12'd2816, 12'd3072: addr__h886084 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h886084 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h886084 = { 48'd0, x__h894178 }; + 12'd3073: addr__h886084 = csrf_time_reg; + default: addr__h886084 = 64'b0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h343282 = 8'd255; + 3'd0, 3'd1: _theResult___fst_sfd__h576364 = 23'd0; 3'd2: - _theResult___fst_exp__h343282 = + _theResult___fst_sfd__h576364 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 8'd254 : - 8'd255; + 23'd8388607 : + 23'd0; 3'd3: - _theResult___fst_exp__h343282 = + _theResult___fst_sfd__h576364 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h343282 = 8'd254; - default: _theResult___fst_exp__h343282 = 8'd0; + 23'd0 : + 23'd8388607; + 3'd4: _theResult___fst_sfd__h576364 = 23'd8388607; + default: _theResult___fst_sfd__h576364 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h343283 = 23'd0; + 3'd0, 3'd1: _theResult___fst_exp__h576363 = 8'd255; 3'd2: - _theResult___fst_sfd__h343283 = + _theResult___fst_exp__h576363 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 23'd8388607 : - 23'd0; + 8'd254 : + 8'd255; 3'd3: - _theResult___fst_sfd__h343283 = + _theResult___fst_exp__h576363 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 23'd0 : - 23'd8388607; - 3'd4: _theResult___fst_sfd__h343283 = 23'd8388607; - default: _theResult___fst_sfd__h343283 = 23'd0; + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h576363 = 8'd254; + default: _theResult___fst_exp__h576363 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h388975 = 23'd0; + 3'd0, 3'd1: _theResult___fst_exp__h622114 = 8'd255; 3'd2: - _theResult___fst_sfd__h388975 = + _theResult___fst_exp__h622114 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h622114 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h622114 = 8'd254; + default: _theResult___fst_exp__h622114 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h622115 = 23'd0; + 3'd2: + _theResult___fst_sfd__h622115 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h388975 = + _theResult___fst_sfd__h622115 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h388975 = 23'd8388607; - default: _theResult___fst_sfd__h388975 = 23'd0; + 3'd4: _theResult___fst_sfd__h622115 = 23'd8388607; + default: _theResult___fst_sfd__h622115 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h434662 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h667861 = 8'd255; 3'd2: - _theResult___fst_exp__h434662 = + _theResult___fst_exp__h667861 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h434662 = + _theResult___fst_exp__h667861 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h434662 = 8'd254; - default: _theResult___fst_exp__h434662 = 8'd0; + 3'd4: _theResult___fst_exp__h667861 = 8'd254; + default: _theResult___fst_exp__h667861 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h434663 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h667862 = 23'd0; 3'd2: - _theResult___fst_sfd__h434663 = + _theResult___fst_sfd__h667862 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h434663 = + _theResult___fst_sfd__h667862 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h434663 = 23'd8388607; - default: _theResult___fst_sfd__h434663 = 23'd0; + 3'd4: _theResult___fst_sfd__h667862 = 23'd8388607; + default: _theResult___fst_sfd__h667862 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q26 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 = - coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q26 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 = - coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q26 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 = 11'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q26 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = - coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = - coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27 = 52'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 = - coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 = - coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 = 11'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 = - coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 = - coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29 = 52'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 = - coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 = - coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 = 11'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 = - coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 = - coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31 = 52'd0; endcase end always@(commitStage_commitTrap) begin - case (commitStage_commitTrap[3:0]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - i__h692202 = commitStage_commitTrap[3:0]; - default: i__h692202 = 4'd15; + case (commitStage_commitTrap[36:32]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd11, + 5'd12, + 5'd13, + 5'd15: + i__h992443 = commitStage_commitTrap[36:32]; + default: i__h992443 = 5'd28; endcase end - always@(commitStage_commitTrap) + always@(commitStage_commitTrap or cause_code__h993965 or i__h992443) begin - case (commitStage_commitTrap[3:0]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11: - i__h692362 = commitStage_commitTrap[3:0]; - default: i__h692362 = 4'd14; + case (commitStage_commitTrap[44:43]) + 2'd0: cause_code__h992427 = 5'd28; + 2'd1: cause_code__h992427 = i__h992443; + default: cause_code__h992427 = cause_code__h993965; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin - case (coreFix_memExe_lsq$firstLd[19]) - 1'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 = - coreFix_memExe_respLrScAmoQ_data_0[31:0]; - 1'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 = - coreFix_memExe_respLrScAmoQ_data_0[63:32]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19:18]) - 2'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + case (coreFix_memExe_lsq$firstLd[37:35]) + 3'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = coreFix_memExe_respLrScAmoQ_data_0[15:0]; - 2'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + 3'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = coreFix_memExe_respLrScAmoQ_data_0[31:16]; - 2'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + 3'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = coreFix_memExe_respLrScAmoQ_data_0[47:32]; - 2'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + 3'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = coreFix_memExe_respLrScAmoQ_data_0[63:48]; + 3'd4: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[79:64]; + 3'd5: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[95:80]; + 3'd6: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[111:96]; + 3'd7: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[127:112]; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin - case (coreFix_memExe_lsq$firstLd[19:17]) - 3'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 = + case (coreFix_memExe_lsq$firstLd[37:34]) + 4'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = coreFix_memExe_respLrScAmoQ_data_0[7:0]; - 3'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 = + 4'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = coreFix_memExe_respLrScAmoQ_data_0[15:8]; - 3'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 = + 4'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = coreFix_memExe_respLrScAmoQ_data_0[23:16]; - 3'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 = + 4'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = coreFix_memExe_respLrScAmoQ_data_0[31:24]; - 3'd4: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 = + 4'd4: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = coreFix_memExe_respLrScAmoQ_data_0[39:32]; - 3'd5: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 = + 4'd5: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = coreFix_memExe_respLrScAmoQ_data_0[47:40]; - 3'd6: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 = + 4'd6: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = coreFix_memExe_respLrScAmoQ_data_0[55:48]; - 3'd7: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 = + 4'd7: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = coreFix_memExe_respLrScAmoQ_data_0[63:56]; + 4'd8: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = + coreFix_memExe_respLrScAmoQ_data_0[71:64]; + 4'd9: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = + coreFix_memExe_respLrScAmoQ_data_0[79:72]; + 4'd10: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = + coreFix_memExe_respLrScAmoQ_data_0[87:80]; + 4'd11: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = + coreFix_memExe_respLrScAmoQ_data_0[95:88]; + 4'd12: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = + coreFix_memExe_respLrScAmoQ_data_0[103:96]; + 4'd13: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = + coreFix_memExe_respLrScAmoQ_data_0[111:104]; + 4'd14: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = + coreFix_memExe_respLrScAmoQ_data_0[119:112]; + 4'd15: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907 = + coreFix_memExe_respLrScAmoQ_data_0[127:120]; endcase end - always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin - case (coreFix_memExe_lsq$firstLd[19]) - 1'd0: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = - mmio_dataRespQ_data_0[31:0]; - 1'd1: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = - mmio_dataRespQ_data_0[63:32]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19:18]) + case (coreFix_memExe_lsq$firstLd[37:36]) 2'd0: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 = - mmio_dataRespQ_data_0[15:0]; + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = + coreFix_memExe_respLrScAmoQ_data_0[31:0]; 2'd1: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 = - mmio_dataRespQ_data_0[31:16]; + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = + coreFix_memExe_respLrScAmoQ_data_0[63:32]; 2'd2: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 = - mmio_dataRespQ_data_0[47:32]; + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = + coreFix_memExe_respLrScAmoQ_data_0[95:64]; 2'd3: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 = - mmio_dataRespQ_data_0[63:48]; + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = + coreFix_memExe_respLrScAmoQ_data_0[127:96]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[37]) + 1'd0: + CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_coreF_ETC__q32 = + coreFix_memExe_respLrScAmoQ_data_0[63:0]; + 1'd1: + CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_coreF_ETC__q32 = + coreFix_memExe_respLrScAmoQ_data_0[127:64]; endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin - case (coreFix_memExe_lsq$firstLd[19:17]) - 3'd0: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 = + case (coreFix_memExe_lsq$firstLd[37:36]) + 2'd0: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040 = + mmio_dataRespQ_data_0[31:0]; + 2'd1: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040 = + mmio_dataRespQ_data_0[63:32]; + 2'd2: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040 = + mmio_dataRespQ_data_0[95:64]; + 2'd3: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040 = + mmio_dataRespQ_data_0[127:96]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[37:34]) + 4'd0: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = mmio_dataRespQ_data_0[7:0]; - 3'd1: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 = + 4'd1: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = mmio_dataRespQ_data_0[15:8]; - 3'd2: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 = + 4'd2: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = mmio_dataRespQ_data_0[23:16]; - 3'd3: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 = + 4'd3: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = mmio_dataRespQ_data_0[31:24]; - 3'd4: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 = + 4'd4: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = mmio_dataRespQ_data_0[39:32]; - 3'd5: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 = + 4'd5: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = mmio_dataRespQ_data_0[47:40]; - 3'd6: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 = + 4'd6: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = mmio_dataRespQ_data_0[55:48]; - 3'd7: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 = + 4'd7: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = mmio_dataRespQ_data_0[63:56]; + 4'd8: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = + mmio_dataRespQ_data_0[71:64]; + 4'd9: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = + mmio_dataRespQ_data_0[79:72]; + 4'd10: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = + mmio_dataRespQ_data_0[87:80]; + 4'd11: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = + mmio_dataRespQ_data_0[95:88]; + 4'd12: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = + mmio_dataRespQ_data_0[103:96]; + 4'd13: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = + mmio_dataRespQ_data_0[111:104]; + 4'd14: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = + mmio_dataRespQ_data_0[119:112]; + 4'd15: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073 = + mmio_dataRespQ_data_0[127:120]; endcase end - always@(coreFix_memExe_dTlb$procResp) + always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin - case (coreFix_memExe_dTlb$procResp[105:103]) - 3'd0, 3'd2: - CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12 = 4'd4; - default: CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12 = 4'd6; + case (coreFix_memExe_lsq$firstLd[37:35]) + 3'd0: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052 = + mmio_dataRespQ_data_0[15:0]; + 3'd1: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052 = + mmio_dataRespQ_data_0[31:16]; + 3'd2: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052 = + mmio_dataRespQ_data_0[47:32]; + 3'd3: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052 = + mmio_dataRespQ_data_0[63:48]; + 3'd4: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052 = + mmio_dataRespQ_data_0[79:64]; + 3'd5: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052 = + mmio_dataRespQ_data_0[95:80]; + 3'd6: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052 = + mmio_dataRespQ_data_0[111:96]; + 3'd7: + SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052 = + mmio_dataRespQ_data_0[127:112]; endcase end - always@(coreFix_memExe_dTlb$procResp) + always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin - case (coreFix_memExe_dTlb$procResp[109:106]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 = - coreFix_memExe_dTlb$procResp[109:106]; - 4'd11: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 = 4'd10; - 4'd12: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 = 4'd11; - 4'd13: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 = 4'd12; - default: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 = 4'd13; + case (coreFix_memExe_lsq$firstLd[37]) + 1'd0: + CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_mmio__ETC__q34 = + mmio_dataRespQ_data_0[63:0]; + 1'd1: + CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_mmio__ETC__q34 = + mmio_dataRespQ_data_0[127:64]; + endcase + end + always@(coreFix_memExe_memRespLdQ_deqP or + coreFix_memExe_memRespLdQ_data_0 or + coreFix_memExe_memRespLdQ_data_1) + begin + case (coreFix_memExe_memRespLdQ_deqP) + 1'd0: + SEL_ARR_NOT_coreFix_memExe_memRespLdQ_data_0_1_ETC___d2157 = + !coreFix_memExe_memRespLdQ_data_0[128]; + 1'd1: + SEL_ARR_NOT_coreFix_memExe_memRespLdQ_data_0_1_ETC___d2157 = + !coreFix_memExe_memRespLdQ_data_1[128]; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_NOT_coreFix_memExe_forwardQ_data_0_216_ETC___d2240 = + !coreFix_memExe_forwardQ_data_0[128]; + 1'd1: + SEL_ARR_NOT_coreFix_memExe_forwardQ_data_0_216_ETC___d2240 = + !coreFix_memExe_forwardQ_data_1[128]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) + 2'd0: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; + 2'd1: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; + 2'd2: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; + 2'd3: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) + 2'd0: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; + 2'd1: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; + 2'd2: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; + 2'd3: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849 or + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164]) + 2'd0: + x__h264814 = + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849[31:0]; + 2'd1: + x__h264814 = + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849[63:32]; + 2'd2: + x__h264814 = + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843[31:0]; + 2'd3: + x__h264814 = + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843[63:32]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) + 2'd0: + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4882 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[512]; + 2'd1: + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4882 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[513]; + 2'd2: + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4882 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514]; + 2'd3: + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4882 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) + 2'd0: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4836 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[512]; + 2'd1: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4836 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[513]; + 2'd2: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4836 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514]; + 2'd3: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4836 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[163:162]) + 2'd0: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5062 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[512]; + 2'd1: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5062 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[513]; + 2'd2: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5062 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514]; + 2'd3: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5062 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[163:162]) + 2'd0: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; + 2'd1: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; + 2'd2: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; + 2'd3: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5077 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[163:162]) + 2'd0: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; + 2'd1: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; + 2'd2: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; + 2'd3: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d5113 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[163:162]) + 2'd0: + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[512]; + 2'd1: + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[513]; + 2'd2: + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514]; + 2'd3: + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or @@ -30276,10 +38768,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871 = + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7038 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[65:2]; 1'd1: - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871 = + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7038 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[65:2]; endcase end @@ -30289,11 +38781,11 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q14 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[514:451]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q36 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[518]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q14 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[514:451]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q36 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[518]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or @@ -30302,11 +38794,11 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[450:387]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q37 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[450:387]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q37 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or @@ -30315,776 +38807,724 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[386:323]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q38 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[516]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[386:323]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q38 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[516]; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) + always@(guard__h585100 or + _theResult___fst_exp__h593148 or + out_exp__h593593 or _theResult___exp__h593590) begin - case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) - 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[322:259]; - 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[322:259]; + case (guard__h585100) + 2'b0, 2'b01: + CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43 = + _theResult___fst_exp__h593148; + 2'b10: + CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43 = + out_exp__h593593; + 2'b11: + CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43 = + _theResult___exp__h593590; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) + always@(guard__h585100 or + _theResult___fst_exp__h593148 or _theResult___exp__h593590) begin - case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) - 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[258:195]; - 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[258:195]; - endcase - end - always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) - 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[194:131]; - 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; + case (guard__h585100) + 2'b0: + CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44 = + _theResult___fst_exp__h593148; + 2'b01, 2'b10, 2'b11: + CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44 = + _theResult___exp__h593590; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43 or + CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8637 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8639 or + _theResult___fst_exp__h593148) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_exp__h593668 = + CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43; + 3'd1: + _theResult___fst_exp__h593668 = + CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44; + 3'd2: + _theResult___fst_exp__h593668 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8637; + 3'd3: + _theResult___fst_exp__h593668 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8639; + 3'd4: _theResult___fst_exp__h593668 = _theResult___fst_exp__h593148; + default: _theResult___fst_exp__h593668 = 8'd0; + endcase + end + always@(guard__h576391 or + _theResult___fst_exp__h584492 or + out_exp__h585011 or _theResult___exp__h585008) + begin + case (guard__h576391) + 2'b0, 2'b01: + CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45 = + _theResult___fst_exp__h584492; + 2'b10: + CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45 = + out_exp__h585011; + 2'b11: + CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45 = + _theResult___exp__h585008; + endcase + end + always@(guard__h576391 or + _theResult___fst_exp__h584492 or _theResult___exp__h585008) + begin + case (guard__h576391) + 2'b0: + CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46 = + _theResult___fst_exp__h584492; + 2'b01, 2'b10, 2'b11: + CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46 = + _theResult___exp__h585008; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45 or + CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8415 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8418 or + _theResult___fst_exp__h584492) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_exp__h585086 = + CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45; + 3'd1: + _theResult___fst_exp__h585086 = + CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46; + 3'd2: + _theResult___fst_exp__h585086 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8415; + 3'd3: + _theResult___fst_exp__h585086 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8418; + 3'd4: _theResult___fst_exp__h585086 = _theResult___fst_exp__h584492; + default: _theResult___fst_exp__h585086 = 8'd0; + endcase + end + always@(guard__h594030 or + _theResult___fst_exp__h602258 or + out_exp__h602777 or _theResult___exp__h602774) + begin + case (guard__h594030) + 2'b0, 2'b01: + CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51 = + _theResult___fst_exp__h602258; + 2'b10: + CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51 = + out_exp__h602777; + 2'b11: + CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51 = + _theResult___exp__h602774; + endcase + end + always@(guard__h594030 or + _theResult___fst_exp__h602258 or _theResult___exp__h602774) + begin + case (guard__h594030) + 2'b0: + CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52 = + _theResult___fst_exp__h602258; + 2'b01, 2'b10, 2'b11: + CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52 = + _theResult___exp__h602774; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51 or + CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8962 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8964 or + _theResult___fst_exp__h602258) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_exp__h602852 = + CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51; + 3'd1: + _theResult___fst_exp__h602852 = + CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52; + 3'd2: + _theResult___fst_exp__h602852 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8962; + 3'd3: + _theResult___fst_exp__h602852 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8964; + 3'd4: _theResult___fst_exp__h602852 = _theResult___fst_exp__h602258; + default: _theResult___fst_exp__h602852 = 8'd0; + endcase + end + always@(guard__h602866 or + _theResult___fst_exp__h610943 or + out_exp__h611413 or _theResult___exp__h611410) + begin + case (guard__h602866) + 2'b0, 2'b01: + CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56 = + _theResult___fst_exp__h610943; + 2'b10: + CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56 = + out_exp__h611413; + 2'b11: + CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56 = + _theResult___exp__h611410; + endcase + end + always@(guard__h602866 or + _theResult___fst_exp__h610943 or _theResult___exp__h611410) + begin + case (guard__h602866) + 2'b0: + CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57 = + _theResult___fst_exp__h610943; + 2'b01, 2'b10, 2'b11: + CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57 = + _theResult___exp__h611410; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56 or + CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9031 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9033 or + _theResult___fst_exp__h610943) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_exp__h611488 = + CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56; + 3'd1: + _theResult___fst_exp__h611488 = + CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57; + 3'd2: + _theResult___fst_exp__h611488 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9031; + 3'd3: + _theResult___fst_exp__h611488 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9033; + 3'd4: _theResult___fst_exp__h611488 = _theResult___fst_exp__h610943; + default: _theResult___fst_exp__h611488 = 8'd0; + endcase + end + always@(guard__h585100 or + _theResult___snd__h593099 or + out_sfd__h593594 or _theResult___sfd__h593591) + begin + case (guard__h585100) + 2'b0, 2'b01: + CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58 = + _theResult___snd__h593099[56:34]; + 2'b10: + CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58 = + out_sfd__h593594; + 2'b11: + CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58 = + _theResult___sfd__h593591; + endcase + end + always@(guard__h585100 or + _theResult___snd__h593099 or _theResult___sfd__h593591) + begin + case (guard__h585100) + 2'b0: + CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59 = + _theResult___snd__h593099[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59 = + _theResult___sfd__h593591; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58 or + CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9081 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9083 or + _theResult___snd__h593099) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h593669 = + CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58; + 3'd1: + _theResult___fst_sfd__h593669 = + CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59; + 3'd2: + _theResult___fst_sfd__h593669 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9081; + 3'd3: + _theResult___fst_sfd__h593669 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9083; + 3'd4: _theResult___fst_sfd__h593669 = _theResult___snd__h593099[56:34]; + default: _theResult___fst_sfd__h593669 = 23'd0; + endcase + end + always@(guard__h576391 or + sfdin__h584486 or out_sfd__h585012 or _theResult___sfd__h585009) + begin + case (guard__h576391) + 2'b0, 2'b01: + CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60 = + sfdin__h584486[56:34]; + 2'b10: + CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60 = + out_sfd__h585012; + 2'b11: + CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60 = + _theResult___sfd__h585009; + endcase + end + always@(guard__h576391 or sfdin__h584486 or _theResult___sfd__h585009) + begin + case (guard__h576391) + 2'b0: + CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61 = + sfdin__h584486[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61 = + _theResult___sfd__h585009; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60 or + CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9062 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9064 or + sfdin__h584486) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h585087 = + CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60; + 3'd1: + _theResult___fst_sfd__h585087 = + CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61; + 3'd2: + _theResult___fst_sfd__h585087 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9062; + 3'd3: + _theResult___fst_sfd__h585087 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9064; + 3'd4: _theResult___fst_sfd__h585087 = sfdin__h584486[56:34]; + default: _theResult___fst_sfd__h585087 = 23'd0; + endcase + end + always@(guard__h594030 or + sfdin__h602252 or out_sfd__h602778 or _theResult___sfd__h602775) + begin + case (guard__h594030) + 2'b0, 2'b01: + CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62 = + sfdin__h602252[56:34]; + 2'b10: + CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62 = + out_sfd__h602778; + 2'b11: + CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62 = + _theResult___sfd__h602775; + endcase + end + always@(guard__h594030 or sfdin__h602252 or _theResult___sfd__h602775) + begin + case (guard__h594030) + 2'b0: + CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63 = + sfdin__h602252[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63 = + _theResult___sfd__h602775; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62 or + CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9108 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9110 or + sfdin__h602252) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h602853 = + CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62; + 3'd1: + _theResult___fst_sfd__h602853 = + CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63; + 3'd2: + _theResult___fst_sfd__h602853 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9108; + 3'd3: + _theResult___fst_sfd__h602853 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9110; + 3'd4: _theResult___fst_sfd__h602853 = sfdin__h602252[56:34]; + default: _theResult___fst_sfd__h602853 = 23'd0; + endcase + end + always@(guard__h602866 or + _theResult___snd__h610889 or + out_sfd__h611414 or _theResult___sfd__h611411) + begin + case (guard__h602866) + 2'b0, 2'b01: + CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64 = + _theResult___snd__h610889[56:34]; + 2'b10: + CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64 = + out_sfd__h611414; + 2'b11: + CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64 = + _theResult___sfd__h611411; + endcase + end + always@(guard__h602866 or + _theResult___snd__h610889 or _theResult___sfd__h611411) + begin + case (guard__h602866) + 2'b0: + CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65 = + _theResult___snd__h610889[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65 = + _theResult___sfd__h611411; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64 or + CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9127 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9129 or + _theResult___snd__h610889) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h611489 = + CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64; + 3'd1: + _theResult___fst_sfd__h611489 = + CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65; + 3'd2: + _theResult___fst_sfd__h611489 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9127; + 3'd3: + _theResult___fst_sfd__h611489 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9129; + 3'd4: _theResult___fst_sfd__h611489 = _theResult___snd__h610889[56:34]; + default: _theResult___fst_sfd__h611489 = 23'd0; + endcase + end + always@(guard__h576391 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(guard__h352019 or - _theResult___fst_exp__h360067 or - out_exp__h360512 or _theResult___exp__h360509) - begin - case (guard__h352019) - 2'b0, 2'b01: - CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24 = - _theResult___fst_exp__h360067; - 2'b10: - CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24 = - out_exp__h360512; - 2'b11: - CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24 = - _theResult___exp__h360509; - endcase - end - always@(guard__h352019 or - _theResult___fst_exp__h360067 or _theResult___exp__h360509) - begin - case (guard__h352019) - 2'b0: - CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25 = - _theResult___fst_exp__h360067; - 2'b01, 2'b10, 2'b11: - CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25 = - _theResult___exp__h360509; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24 or - CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 or - _theResult___fst_exp__h360067) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_exp__h360587 = - CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24; - 3'd1: - _theResult___fst_exp__h360587 = - CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25; - 3'd2: - _theResult___fst_exp__h360587 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528; - 3'd3: - _theResult___fst_exp__h360587 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530; - 3'd4: _theResult___fst_exp__h360587 = _theResult___fst_exp__h360067; - default: _theResult___fst_exp__h360587 = 8'd0; - endcase - end - always@(guard__h343310 or - _theResult___fst_exp__h351411 or - out_exp__h351930 or _theResult___exp__h351927) - begin - case (guard__h343310) - 2'b0, 2'b01: - CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26 = - _theResult___fst_exp__h351411; - 2'b10: - CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26 = - out_exp__h351930; - 2'b11: - CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26 = - _theResult___exp__h351927; - endcase - end - always@(guard__h343310 or - _theResult___fst_exp__h351411 or _theResult___exp__h351927) - begin - case (guard__h343310) - 2'b0: - CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27 = - _theResult___fst_exp__h351411; - 2'b01, 2'b10, 2'b11: - CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27 = - _theResult___exp__h351927; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26 or - CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 or - _theResult___fst_exp__h351411) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_exp__h352005 = - CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26; - 3'd1: - _theResult___fst_exp__h352005 = - CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27; - 3'd2: - _theResult___fst_exp__h352005 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306; - 3'd3: - _theResult___fst_exp__h352005 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309; - 3'd4: _theResult___fst_exp__h352005 = _theResult___fst_exp__h351411; - default: _theResult___fst_exp__h352005 = 8'd0; - endcase - end - always@(guard__h360949 or - _theResult___fst_exp__h369177 or - out_exp__h369696 or _theResult___exp__h369693) - begin - case (guard__h360949) - 2'b0, 2'b01: - CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32 = - _theResult___fst_exp__h369177; - 2'b10: - CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32 = - out_exp__h369696; - 2'b11: - CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32 = - _theResult___exp__h369693; - endcase - end - always@(guard__h360949 or - _theResult___fst_exp__h369177 or _theResult___exp__h369693) - begin - case (guard__h360949) - 2'b0: - CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33 = - _theResult___fst_exp__h369177; - 2'b01, 2'b10, 2'b11: - CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33 = - _theResult___exp__h369693; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32 or - CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 or - _theResult___fst_exp__h369177) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_exp__h369771 = - CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32; - 3'd1: - _theResult___fst_exp__h369771 = - CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33; - 3'd2: - _theResult___fst_exp__h369771 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853; - 3'd3: - _theResult___fst_exp__h369771 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855; - 3'd4: _theResult___fst_exp__h369771 = _theResult___fst_exp__h369177; - default: _theResult___fst_exp__h369771 = 8'd0; - endcase - end - always@(guard__h369785 or - _theResult___fst_exp__h377862 or - out_exp__h378332 or _theResult___exp__h378329) - begin - case (guard__h369785) - 2'b0, 2'b01: - CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37 = - _theResult___fst_exp__h377862; - 2'b10: - CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37 = - out_exp__h378332; - 2'b11: - CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37 = - _theResult___exp__h378329; - endcase - end - always@(guard__h369785 or - _theResult___fst_exp__h377862 or _theResult___exp__h378329) - begin - case (guard__h369785) - 2'b0: - CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38 = - _theResult___fst_exp__h377862; - 2'b01, 2'b10, 2'b11: - CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38 = - _theResult___exp__h378329; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37 or - CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 or - _theResult___fst_exp__h377862) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_exp__h378407 = - CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37; - 3'd1: - _theResult___fst_exp__h378407 = - CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38; - 3'd2: - _theResult___fst_exp__h378407 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922; - 3'd3: - _theResult___fst_exp__h378407 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924; - 3'd4: _theResult___fst_exp__h378407 = _theResult___fst_exp__h377862; - default: _theResult___fst_exp__h378407 = 8'd0; - endcase - end - always@(guard__h352019 or - _theResult___snd__h360018 or - out_sfd__h360513 or _theResult___sfd__h360510) - begin - case (guard__h352019) - 2'b0, 2'b01: - CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39 = - _theResult___snd__h360018[56:34]; - 2'b10: - CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39 = - out_sfd__h360513; - 2'b11: - CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39 = - _theResult___sfd__h360510; - endcase - end - always@(guard__h352019 or - _theResult___snd__h360018 or _theResult___sfd__h360510) - begin - case (guard__h352019) - 2'b0: - CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40 = - _theResult___snd__h360018[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40 = - _theResult___sfd__h360510; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39 or - CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 or - _theResult___snd__h360018) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h360588 = - CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39; - 3'd1: - _theResult___fst_sfd__h360588 = - CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40; - 3'd2: - _theResult___fst_sfd__h360588 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972; - 3'd3: - _theResult___fst_sfd__h360588 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974; - 3'd4: _theResult___fst_sfd__h360588 = _theResult___snd__h360018[56:34]; - default: _theResult___fst_sfd__h360588 = 23'd0; - endcase - end - always@(guard__h343310 or - sfdin__h351405 or out_sfd__h351931 or _theResult___sfd__h351928) - begin - case (guard__h343310) - 2'b0, 2'b01: - CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41 = - sfdin__h351405[56:34]; - 2'b10: - CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41 = - out_sfd__h351931; - 2'b11: - CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41 = - _theResult___sfd__h351928; - endcase - end - always@(guard__h343310 or sfdin__h351405 or _theResult___sfd__h351928) - begin - case (guard__h343310) - 2'b0: - CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42 = - sfdin__h351405[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42 = - _theResult___sfd__h351928; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41 or - CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 or - sfdin__h351405) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h352006 = - CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41; - 3'd1: - _theResult___fst_sfd__h352006 = - CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42; - 3'd2: - _theResult___fst_sfd__h352006 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953; - 3'd3: - _theResult___fst_sfd__h352006 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955; - 3'd4: _theResult___fst_sfd__h352006 = sfdin__h351405[56:34]; - default: _theResult___fst_sfd__h352006 = 23'd0; - endcase - end - always@(guard__h360949 or - sfdin__h369171 or out_sfd__h369697 or _theResult___sfd__h369694) - begin - case (guard__h360949) - 2'b0, 2'b01: - CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43 = - sfdin__h369171[56:34]; - 2'b10: - CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43 = - out_sfd__h369697; - 2'b11: - CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43 = - _theResult___sfd__h369694; - endcase - end - always@(guard__h360949 or sfdin__h369171 or _theResult___sfd__h369694) - begin - case (guard__h360949) - 2'b0: - CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44 = - sfdin__h369171[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44 = - _theResult___sfd__h369694; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43 or - CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 or - sfdin__h369171) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h369772 = - CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43; - 3'd1: - _theResult___fst_sfd__h369772 = - CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44; - 3'd2: - _theResult___fst_sfd__h369772 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999; - 3'd3: - _theResult___fst_sfd__h369772 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001; - 3'd4: _theResult___fst_sfd__h369772 = sfdin__h369171[56:34]; - default: _theResult___fst_sfd__h369772 = 23'd0; - endcase - end - always@(guard__h369785 or - _theResult___snd__h377808 or - out_sfd__h378333 or _theResult___sfd__h378330) - begin - case (guard__h369785) - 2'b0, 2'b01: - CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45 = - _theResult___snd__h377808[56:34]; - 2'b10: - CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45 = - out_sfd__h378333; - 2'b11: - CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45 = - _theResult___sfd__h378330; - endcase - end - always@(guard__h369785 or - _theResult___snd__h377808 or _theResult___sfd__h378330) - begin - case (guard__h369785) - 2'b0: - CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46 = - _theResult___snd__h377808[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46 = - _theResult___sfd__h378330; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45 or - CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 or - _theResult___snd__h377808) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h378408 = - CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45; - 3'd1: - _theResult___fst_sfd__h378408 = - CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46; - 3'd2: - _theResult___fst_sfd__h378408 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018; - 3'd3: - _theResult___fst_sfd__h378408 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020; - 3'd4: _theResult___fst_sfd__h378408 = _theResult___snd__h377808[56:34]; - default: _theResult___fst_sfd__h378408 = 23'd0; - endcase - end - always@(guard__h343310 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h343310) + case (guard__h576391) 2'b0, 2'b01, 2'b10: - CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = - guard__h343310 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 or - guard__h343310) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - (guard__h343310 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h343310 == 2'b01 || guard__h343310 == 2'b10 || - guard__h343310 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(guard__h352019 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h352019) - 2'b0, 2'b01, 2'b10: - CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = - guard__h352019 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or - guard__h352019) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - (guard__h352019 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h352019 == 2'b01 || guard__h352019 == 2'b10 || - guard__h352019 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(guard__h343310 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h343310) - 2'b0, 2'b01, 2'b10: - CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q66 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = - guard__h343310 != 2'b11 || + CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q66 = + guard__h576391 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or - guard__h343310) + CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q66 or + guard__h576391) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159 = + CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q66; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - (guard__h343310 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159 = + (guard__h576391 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h343310 != 2'b01 && guard__h343310 != 2'b10 && - guard__h343310 != 2'b11 || + guard__h576391 != 2'b01 && guard__h576391 != 2'b10 && + guard__h576391 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352019 or + always@(guard__h576391 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h352019) + case (guard__h576391) 2'b0, 2'b01, 2'b10: - CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = - guard__h352019 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 or - guard__h352019) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - (guard__h352019 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h352019 != 2'b01 && guard__h352019 != 2'b10 && - guard__h352019 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(guard__h360949 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h360949) - 2'b0, 2'b01, 2'b10: - CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = + CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = - guard__h360949 == 2'b11 && + CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 = + guard__h576391 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 or - guard__h360949) + CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 or + guard__h576391) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51; + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215 = + CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - (guard__h360949 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215 = + (guard__h576391 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h360949 == 2'b01 || guard__h360949 == 2'b10 || - guard__h360949 == 2'b11) && + (guard__h576391 == 2'b01 || guard__h576391 == 2'b10 || + guard__h576391 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == 3'd4 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h369785 or + always@(guard__h585100 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h369785) + case (guard__h585100) 2'b0, 2'b01, 2'b10: - CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = - guard__h369785 == 2'b11 && + CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = + guard__h585100 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or - guard__h369785) + CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 or + guard__h585100) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222 = + CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - (guard__h369785 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222 = + (guard__h585100 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h369785 == 2'b01 || guard__h369785 == 2'b10 || - guard__h369785 == 2'b11) && + (guard__h585100 == 2'b01 || guard__h585100 == 2'b10 || + guard__h585100 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == 3'd4 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h360949 or + always@(guard__h585100 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h360949) + case (guard__h585100) 2'b0, 2'b01, 2'b10: - CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = - guard__h360949 != 2'b11 || + CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = + guard__h585100 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or - guard__h360949) + CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 or + guard__h585100) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172 = + CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - (guard__h360949 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172 = + (guard__h585100 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h360949 != 2'b01 && guard__h360949 != 2'b10 && - guard__h360949 != 2'b11 || + guard__h585100 != 2'b01 && guard__h585100 != 2'b10 && + guard__h585100 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h369785 or + always@(guard__h594030 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h369785) + case (guard__h594030) 2'b0, 2'b01, 2'b10: - CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = + CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = + guard__h594030 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 or + guard__h594030) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232 = + CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232 = + (guard__h594030 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + (guard__h594030 == 2'b01 || guard__h594030 == 2'b10 || + guard__h594030 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(guard__h602866 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h602866) + 2'b0, 2'b01, 2'b10: + CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = + guard__h602866 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 or + guard__h602866) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239 = + CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239 = + (guard__h602866 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + (guard__h602866 == 2'b01 || guard__h602866 == 2'b10 || + guard__h602866 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(guard__h594030 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h594030) + 2'b0, 2'b01, 2'b10: + CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = - guard__h369785 != 2'b11 || + CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = + guard__h594030 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 or - guard__h369785) + CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 or + guard__h594030) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54; + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189 = + CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - (guard__h369785 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189 = + (guard__h594030 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h369785 != 2'b01 && guard__h369785 != 2'b10 && - guard__h369785 != 2'b11 || + guard__h594030 != 2'b01 && guard__h594030 != 2'b10 && + guard__h594030 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(guard__h602866 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h602866) + 2'b0, 2'b01, 2'b10: + CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = + guard__h602866 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 or + guard__h602866) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202 = + CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202 = + (guard__h602866 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + guard__h602866 != 2'b01 && guard__h602866 != 2'b10 && + guard__h602866 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202 = + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; @@ -31095,725 +39535,738 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9225 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9225 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1, 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9176 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9176 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h397709 or - _theResult___fst_exp__h405757 or - out_exp__h406202 or _theResult___exp__h406199) + always@(guard__h630849 or + _theResult___fst_exp__h638897 or + out_exp__h639342 or _theResult___exp__h639339) begin - case (guard__h397709) + case (guard__h630849) 2'b0, 2'b01: - CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59 = - _theResult___fst_exp__h405757; + CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78 = + _theResult___fst_exp__h638897; 2'b10: - CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59 = - out_exp__h406202; + CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78 = + out_exp__h639342; 2'b11: - CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59 = - _theResult___exp__h406199; + CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78 = + _theResult___exp__h639339; endcase end - always@(guard__h397709 or - _theResult___fst_exp__h405757 or _theResult___exp__h406199) + always@(guard__h630849 or + _theResult___fst_exp__h638897 or _theResult___exp__h639339) begin - case (guard__h397709) + case (guard__h630849) 2'b0: - CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60 = - _theResult___fst_exp__h405757; + CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79 = + _theResult___fst_exp__h638897; 2'b01, 2'b10, 2'b11: - CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60 = - _theResult___exp__h406199; + CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79 = + _theResult___exp__h639339; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59 or - CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 or - _theResult___fst_exp__h405757) + CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78 or + CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10034 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10036 or + _theResult___fst_exp__h638897) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h406277 = - CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59; + _theResult___fst_exp__h639417 = + CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78; 3'd1: - _theResult___fst_exp__h406277 = - CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60; + _theResult___fst_exp__h639417 = + CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79; 3'd2: - _theResult___fst_exp__h406277 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920; + _theResult___fst_exp__h639417 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10034; 3'd3: - _theResult___fst_exp__h406277 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922; - 3'd4: _theResult___fst_exp__h406277 = _theResult___fst_exp__h405757; - default: _theResult___fst_exp__h406277 = 8'd0; + _theResult___fst_exp__h639417 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10036; + 3'd4: _theResult___fst_exp__h639417 = _theResult___fst_exp__h638897; + default: _theResult___fst_exp__h639417 = 8'd0; endcase end - always@(guard__h389002 or - _theResult___fst_exp__h397101 or - out_exp__h397620 or _theResult___exp__h397617) + always@(guard__h622142 or + _theResult___fst_exp__h630241 or + out_exp__h630760 or _theResult___exp__h630757) begin - case (guard__h389002) + case (guard__h622142) 2'b0, 2'b01: - CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61 = - _theResult___fst_exp__h397101; + CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80 = + _theResult___fst_exp__h630241; 2'b10: - CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61 = - out_exp__h397620; + CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80 = + out_exp__h630760; 2'b11: - CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61 = - _theResult___exp__h397617; + CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80 = + _theResult___exp__h630757; endcase end - always@(guard__h389002 or - _theResult___fst_exp__h397101 or _theResult___exp__h397617) + always@(guard__h622142 or + _theResult___fst_exp__h630241 or _theResult___exp__h630757) begin - case (guard__h389002) + case (guard__h622142) 2'b0: - CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62 = - _theResult___fst_exp__h397101; + CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81 = + _theResult___fst_exp__h630241; 2'b01, 2'b10, 2'b11: - CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62 = - _theResult___exp__h397617; + CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81 = + _theResult___exp__h630757; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61 or - CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 or - _theResult___fst_exp__h397101) + CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80 or + CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9812 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9815 or + _theResult___fst_exp__h630241) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h397695 = - CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61; + _theResult___fst_exp__h630835 = + CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80; 3'd1: - _theResult___fst_exp__h397695 = - CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62; + _theResult___fst_exp__h630835 = + CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81; 3'd2: - _theResult___fst_exp__h397695 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698; + _theResult___fst_exp__h630835 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9812; 3'd3: - _theResult___fst_exp__h397695 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701; - 3'd4: _theResult___fst_exp__h397695 = _theResult___fst_exp__h397101; - default: _theResult___fst_exp__h397695 = 8'd0; + _theResult___fst_exp__h630835 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9815; + 3'd4: _theResult___fst_exp__h630835 = _theResult___fst_exp__h630241; + default: _theResult___fst_exp__h630835 = 8'd0; endcase end - always@(guard__h406639 or - _theResult___fst_exp__h414867 or - out_exp__h415386 or _theResult___exp__h415383) + always@(guard__h639779 or + _theResult___fst_exp__h648007 or + out_exp__h648526 or _theResult___exp__h648523) begin - case (guard__h406639) + case (guard__h639779) 2'b0, 2'b01: - CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67 = - _theResult___fst_exp__h414867; + CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86 = + _theResult___fst_exp__h648007; 2'b10: - CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67 = - out_exp__h415386; + CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86 = + out_exp__h648526; 2'b11: - CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67 = - _theResult___exp__h415383; + CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86 = + _theResult___exp__h648523; endcase end - always@(guard__h406639 or - _theResult___fst_exp__h414867 or _theResult___exp__h415383) + always@(guard__h639779 or + _theResult___fst_exp__h648007 or _theResult___exp__h648523) begin - case (guard__h406639) + case (guard__h639779) 2'b0: - CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68 = - _theResult___fst_exp__h414867; + CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87 = + _theResult___fst_exp__h648007; 2'b01, 2'b10, 2'b11: - CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68 = - _theResult___exp__h415383; + CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87 = + _theResult___exp__h648523; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67 or - CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 or - _theResult___fst_exp__h414867) + CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86 or + CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10359 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10361 or + _theResult___fst_exp__h648007) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h415461 = - CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67; + _theResult___fst_exp__h648601 = + CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86; 3'd1: - _theResult___fst_exp__h415461 = - CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68; + _theResult___fst_exp__h648601 = + CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87; 3'd2: - _theResult___fst_exp__h415461 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245; + _theResult___fst_exp__h648601 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10359; 3'd3: - _theResult___fst_exp__h415461 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247; - 3'd4: _theResult___fst_exp__h415461 = _theResult___fst_exp__h414867; - default: _theResult___fst_exp__h415461 = 8'd0; + _theResult___fst_exp__h648601 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10361; + 3'd4: _theResult___fst_exp__h648601 = _theResult___fst_exp__h648007; + default: _theResult___fst_exp__h648601 = 8'd0; endcase end - always@(guard__h415475 or - _theResult___fst_exp__h423552 or - out_exp__h424022 or _theResult___exp__h424019) + always@(guard__h648615 or + _theResult___fst_exp__h656692 or + out_exp__h657162 or _theResult___exp__h657159) begin - case (guard__h415475) + case (guard__h648615) 2'b0, 2'b01: - CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72 = - _theResult___fst_exp__h423552; + CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91 = + _theResult___fst_exp__h656692; 2'b10: - CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72 = - out_exp__h424022; + CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91 = + out_exp__h657162; 2'b11: - CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72 = - _theResult___exp__h424019; + CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91 = + _theResult___exp__h657159; endcase end - always@(guard__h415475 or - _theResult___fst_exp__h423552 or _theResult___exp__h424019) + always@(guard__h648615 or + _theResult___fst_exp__h656692 or _theResult___exp__h657159) begin - case (guard__h415475) + case (guard__h648615) 2'b0: - CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73 = - _theResult___fst_exp__h423552; + CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92 = + _theResult___fst_exp__h656692; 2'b01, 2'b10, 2'b11: - CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73 = - _theResult___exp__h424019; + CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92 = + _theResult___exp__h657159; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72 or - CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 or - _theResult___fst_exp__h423552) + CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91 or + CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10428 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10430 or + _theResult___fst_exp__h656692) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h424097 = - CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72; + _theResult___fst_exp__h657237 = + CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91; 3'd1: - _theResult___fst_exp__h424097 = - CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73; + _theResult___fst_exp__h657237 = + CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92; 3'd2: - _theResult___fst_exp__h424097 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314; + _theResult___fst_exp__h657237 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10428; 3'd3: - _theResult___fst_exp__h424097 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316; - 3'd4: _theResult___fst_exp__h424097 = _theResult___fst_exp__h423552; - default: _theResult___fst_exp__h424097 = 8'd0; + _theResult___fst_exp__h657237 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10430; + 3'd4: _theResult___fst_exp__h657237 = _theResult___fst_exp__h656692; + default: _theResult___fst_exp__h657237 = 8'd0; endcase end - always@(guard__h397709 or - _theResult___snd__h405708 or - out_sfd__h406203 or _theResult___sfd__h406200) + always@(guard__h630849 or + _theResult___snd__h638848 or + out_sfd__h639343 or _theResult___sfd__h639340) begin - case (guard__h397709) + case (guard__h630849) 2'b0, 2'b01: - CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74 = - _theResult___snd__h405708[56:34]; + CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93 = + _theResult___snd__h638848[56:34]; 2'b10: - CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74 = - out_sfd__h406203; + CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93 = + out_sfd__h639343; 2'b11: - CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74 = - _theResult___sfd__h406200; + CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93 = + _theResult___sfd__h639340; endcase end - always@(guard__h397709 or - _theResult___snd__h405708 or _theResult___sfd__h406200) + always@(guard__h630849 or + _theResult___snd__h638848 or _theResult___sfd__h639340) begin - case (guard__h397709) + case (guard__h630849) 2'b0: - CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75 = - _theResult___snd__h405708[56:34]; + CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94 = + _theResult___snd__h638848[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75 = - _theResult___sfd__h406200; + CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94 = + _theResult___sfd__h639340; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74 or - CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 or - _theResult___snd__h405708) + CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93 or + CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10478 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10480 or + _theResult___snd__h638848) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h406278 = - CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74; + _theResult___fst_sfd__h639418 = + CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93; 3'd1: - _theResult___fst_sfd__h406278 = - CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75; + _theResult___fst_sfd__h639418 = + CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94; 3'd2: - _theResult___fst_sfd__h406278 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364; + _theResult___fst_sfd__h639418 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10478; 3'd3: - _theResult___fst_sfd__h406278 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366; - 3'd4: _theResult___fst_sfd__h406278 = _theResult___snd__h405708[56:34]; - default: _theResult___fst_sfd__h406278 = 23'd0; + _theResult___fst_sfd__h639418 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10480; + 3'd4: _theResult___fst_sfd__h639418 = _theResult___snd__h638848[56:34]; + default: _theResult___fst_sfd__h639418 = 23'd0; endcase end - always@(guard__h389002 or - sfdin__h397095 or out_sfd__h397621 or _theResult___sfd__h397618) + always@(guard__h622142 or + sfdin__h630235 or out_sfd__h630761 or _theResult___sfd__h630758) begin - case (guard__h389002) + case (guard__h622142) 2'b0, 2'b01: - CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76 = - sfdin__h397095[56:34]; + CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95 = + sfdin__h630235[56:34]; 2'b10: - CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76 = - out_sfd__h397621; + CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95 = + out_sfd__h630761; 2'b11: - CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76 = - _theResult___sfd__h397618; + CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95 = + _theResult___sfd__h630758; endcase end - always@(guard__h389002 or sfdin__h397095 or _theResult___sfd__h397618) + always@(guard__h622142 or sfdin__h630235 or _theResult___sfd__h630758) begin - case (guard__h389002) + case (guard__h622142) 2'b0: - CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77 = - sfdin__h397095[56:34]; + CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96 = + sfdin__h630235[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77 = - _theResult___sfd__h397618; + CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96 = + _theResult___sfd__h630758; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76 or - CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 or - sfdin__h397095) + CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95 or + CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10459 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10461 or + sfdin__h630235) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h397696 = - CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76; + _theResult___fst_sfd__h630836 = + CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95; 3'd1: - _theResult___fst_sfd__h397696 = - CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77; + _theResult___fst_sfd__h630836 = + CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96; 3'd2: - _theResult___fst_sfd__h397696 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345; + _theResult___fst_sfd__h630836 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10459; 3'd3: - _theResult___fst_sfd__h397696 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347; - 3'd4: _theResult___fst_sfd__h397696 = sfdin__h397095[56:34]; - default: _theResult___fst_sfd__h397696 = 23'd0; + _theResult___fst_sfd__h630836 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10461; + 3'd4: _theResult___fst_sfd__h630836 = sfdin__h630235[56:34]; + default: _theResult___fst_sfd__h630836 = 23'd0; endcase end - always@(guard__h406639 or - sfdin__h414861 or out_sfd__h415387 or _theResult___sfd__h415384) + always@(guard__h639779 or + sfdin__h648001 or out_sfd__h648527 or _theResult___sfd__h648524) begin - case (guard__h406639) + case (guard__h639779) 2'b0, 2'b01: - CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78 = - sfdin__h414861[56:34]; + CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97 = + sfdin__h648001[56:34]; 2'b10: - CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78 = - out_sfd__h415387; + CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97 = + out_sfd__h648527; 2'b11: - CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78 = - _theResult___sfd__h415384; + CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97 = + _theResult___sfd__h648524; endcase end - always@(guard__h406639 or sfdin__h414861 or _theResult___sfd__h415384) + always@(guard__h639779 or sfdin__h648001 or _theResult___sfd__h648524) begin - case (guard__h406639) + case (guard__h639779) 2'b0: - CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79 = - sfdin__h414861[56:34]; + CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98 = + sfdin__h648001[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79 = - _theResult___sfd__h415384; + CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98 = + _theResult___sfd__h648524; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78 or - CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 or - sfdin__h414861) + CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97 or + CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507 or + sfdin__h648001) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h415462 = - CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78; + _theResult___fst_sfd__h648602 = + CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97; 3'd1: - _theResult___fst_sfd__h415462 = - CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79; + _theResult___fst_sfd__h648602 = + CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98; 3'd2: - _theResult___fst_sfd__h415462 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391; + _theResult___fst_sfd__h648602 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505; 3'd3: - _theResult___fst_sfd__h415462 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393; - 3'd4: _theResult___fst_sfd__h415462 = sfdin__h414861[56:34]; - default: _theResult___fst_sfd__h415462 = 23'd0; + _theResult___fst_sfd__h648602 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507; + 3'd4: _theResult___fst_sfd__h648602 = sfdin__h648001[56:34]; + default: _theResult___fst_sfd__h648602 = 23'd0; endcase end - always@(guard__h415475 or - _theResult___snd__h423498 or - out_sfd__h424023 or _theResult___sfd__h424020) + always@(guard__h648615 or + _theResult___snd__h656638 or + out_sfd__h657163 or _theResult___sfd__h657160) begin - case (guard__h415475) + case (guard__h648615) 2'b0, 2'b01: - CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80 = - _theResult___snd__h423498[56:34]; + CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99 = + _theResult___snd__h656638[56:34]; 2'b10: - CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80 = - out_sfd__h424023; + CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99 = + out_sfd__h657163; 2'b11: - CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80 = - _theResult___sfd__h424020; + CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99 = + _theResult___sfd__h657160; endcase end - always@(guard__h415475 or - _theResult___snd__h423498 or _theResult___sfd__h424020) + always@(guard__h648615 or + _theResult___snd__h656638 or _theResult___sfd__h657160) begin - case (guard__h415475) + case (guard__h648615) 2'b0: - CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81 = - _theResult___snd__h423498[56:34]; + CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100 = + _theResult___snd__h656638[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81 = - _theResult___sfd__h424020; + CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100 = + _theResult___sfd__h657160; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80 or - CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 or - _theResult___snd__h423498) + CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99 or + CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10524 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10526 or + _theResult___snd__h656638) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h424098 = - CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80; + _theResult___fst_sfd__h657238 = + CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99; 3'd1: - _theResult___fst_sfd__h424098 = - CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81; + _theResult___fst_sfd__h657238 = + CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100; 3'd2: - _theResult___fst_sfd__h424098 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410; + _theResult___fst_sfd__h657238 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10524; 3'd3: - _theResult___fst_sfd__h424098 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412; - 3'd4: _theResult___fst_sfd__h424098 = _theResult___snd__h423498[56:34]; - default: _theResult___fst_sfd__h424098 = 23'd0; + _theResult___fst_sfd__h657238 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10526; + 3'd4: _theResult___fst_sfd__h657238 = _theResult___snd__h656638[56:34]; + default: _theResult___fst_sfd__h657238 = 23'd0; endcase end - always@(guard__h389002 or + always@(guard__h622142 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h389002) + case (guard__h622142) 2'b0, 2'b01, 2'b10: - CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = + CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = - guard__h389002 == 2'b11 && + CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 = + guard__h622142 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 or - guard__h389002) + CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 or + guard__h622142) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82; + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612 = + CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - (guard__h389002 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612 = + (guard__h622142 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h389002 == 2'b01 || guard__h389002 == 2'b10 || - guard__h389002 == 2'b11) && + (guard__h622142 == 2'b01 || guard__h622142 == 2'b10 || + guard__h622142 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] == 3'd4 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h389002 or + always@(guard__h622142 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h389002) + case (guard__h622142) 2'b0, 2'b01, 2'b10: - CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = + CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = - guard__h389002 != 2'b11 || + CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 = + guard__h622142 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 or - guard__h389002) + CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 or + guard__h622142) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83; + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556 = + CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - (guard__h389002 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556 = + (guard__h622142 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h389002 != 2'b01 && guard__h389002 != 2'b10 && - guard__h389002 != 2'b11 || + guard__h622142 != 2'b01 && guard__h622142 != 2'b10 && + guard__h622142 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h397709 or + always@(guard__h630849 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h397709) + case (guard__h630849) 2'b0, 2'b01, 2'b10: - CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = + CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = - guard__h397709 == 2'b11 && + CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = + guard__h630849 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 or - guard__h397709) + CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 or + guard__h630849) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84; + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619 = + CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - (guard__h397709 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619 = + (guard__h630849 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h397709 == 2'b01 || guard__h397709 == 2'b10 || - guard__h397709 == 2'b11) && + (guard__h630849 == 2'b01 || guard__h630849 == 2'b10 || + guard__h630849 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] == 3'd4 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h397709 or + always@(guard__h630849 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h397709) + case (guard__h630849) 2'b0, 2'b01, 2'b10: - CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = + CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = - guard__h397709 != 2'b11 || + CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 = + guard__h630849 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 or - guard__h397709) + CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 or + guard__h630849) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85; + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569 = + CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - (guard__h397709 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569 = + (guard__h630849 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h397709 != 2'b01 && guard__h397709 != 2'b10 && - guard__h397709 != 2'b11 || + guard__h630849 != 2'b01 && guard__h630849 != 2'b10 && + guard__h630849 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h406639 or + always@(guard__h639779 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h406639) + case (guard__h639779) 2'b0, 2'b01, 2'b10: - CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = + CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = - guard__h406639 == 2'b11 && + CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 = + guard__h639779 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 or - guard__h406639) + CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 or + guard__h639779) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86; + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629 = + CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - (guard__h406639 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629 = + (guard__h639779 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h406639 == 2'b01 || guard__h406639 == 2'b10 || - guard__h406639 == 2'b11) && + (guard__h639779 == 2'b01 || guard__h639779 == 2'b10 || + guard__h639779 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] == 3'd4 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h406639 or + always@(guard__h639779 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h406639) + case (guard__h639779) 2'b0, 2'b01, 2'b10: - CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = + CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = - guard__h406639 != 2'b11 || + CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = + guard__h639779 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 or - guard__h406639) + CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 or + guard__h639779) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87; + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586 = + CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - (guard__h406639 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586 = + (guard__h639779 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h406639 != 2'b01 && guard__h406639 != 2'b10 && - guard__h406639 != 2'b11 || + guard__h639779 != 2'b01 && guard__h639779 != 2'b10 && + guard__h639779 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h415475 or + always@(guard__h648615 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h415475) + case (guard__h648615) 2'b0, 2'b01, 2'b10: - CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = - guard__h415475 == 2'b11 && + CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = + guard__h648615 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or - guard__h415475) + CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 or + guard__h648615) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88; + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636 = + CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - (guard__h415475 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636 = + (guard__h648615 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h415475 == 2'b01 || guard__h415475 == 2'b10 || - guard__h415475 == 2'b11) && + (guard__h648615 == 2'b01 || guard__h648615 == 2'b10 || + guard__h648615 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] == 3'd4 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h415475 or + always@(guard__h648615 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h415475) + case (guard__h648615) 2'b0, 2'b01, 2'b10: - CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = + CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = - guard__h415475 != 2'b11 || + CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = + guard__h648615 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 or - guard__h415475) + CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 or + guard__h648615) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89; + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599 = + CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - (guard__h415475 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599 = + (guard__h648615 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h415475 != 2'b01 && guard__h415475 != 2'b10 && - guard__h415475 != 2'b11 || + guard__h648615 != 2'b01 && guard__h648615 != 2'b10 && + guard__h648615 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; @@ -31824,9 +40277,9 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508 = + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10622 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10622 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] == 3'd4 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; @@ -31837,725 +40290,725 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10573 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10573 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h443397 or - _theResult___fst_exp__h451445 or - out_exp__h451890 or _theResult___exp__h451887) + always@(guard__h676596 or + _theResult___fst_exp__h684644 or + out_exp__h685089 or _theResult___exp__h685086) begin - case (guard__h443397) + case (guard__h676596) 2'b0, 2'b01: - CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94 = - _theResult___fst_exp__h451445; + CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113 = + _theResult___fst_exp__h684644; 2'b10: - CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94 = - out_exp__h451890; + CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113 = + out_exp__h685089; 2'b11: - CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94 = - _theResult___exp__h451887; + CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113 = + _theResult___exp__h685086; endcase end - always@(guard__h443397 or - _theResult___fst_exp__h451445 or _theResult___exp__h451887) + always@(guard__h676596 or + _theResult___fst_exp__h684644 or _theResult___exp__h685086) begin - case (guard__h443397) + case (guard__h676596) 2'b0: - CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95 = - _theResult___fst_exp__h451445; + CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114 = + _theResult___fst_exp__h684644; 2'b01, 2'b10, 2'b11: - CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95 = - _theResult___exp__h451887; + CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114 = + _theResult___exp__h685086; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94 or - CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 or - _theResult___fst_exp__h451445) + CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113 or + CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11431 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11433 or + _theResult___fst_exp__h684644) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h451965 = - CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94; + _theResult___fst_exp__h685164 = + CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113; 3'd1: - _theResult___fst_exp__h451965 = - CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95; + _theResult___fst_exp__h685164 = + CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114; 3'd2: - _theResult___fst_exp__h451965 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312; + _theResult___fst_exp__h685164 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11431; 3'd3: - _theResult___fst_exp__h451965 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314; - 3'd4: _theResult___fst_exp__h451965 = _theResult___fst_exp__h451445; - default: _theResult___fst_exp__h451965 = 8'd0; + _theResult___fst_exp__h685164 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11433; + 3'd4: _theResult___fst_exp__h685164 = _theResult___fst_exp__h684644; + default: _theResult___fst_exp__h685164 = 8'd0; endcase end - always@(guard__h434690 or - _theResult___fst_exp__h442789 or - out_exp__h443308 or _theResult___exp__h443305) + always@(guard__h667889 or + _theResult___fst_exp__h675988 or + out_exp__h676507 or _theResult___exp__h676504) begin - case (guard__h434690) + case (guard__h667889) 2'b0, 2'b01: - CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96 = - _theResult___fst_exp__h442789; + CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115 = + _theResult___fst_exp__h675988; 2'b10: - CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96 = - out_exp__h443308; + CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115 = + out_exp__h676507; 2'b11: - CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96 = - _theResult___exp__h443305; + CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115 = + _theResult___exp__h676504; endcase end - always@(guard__h434690 or - _theResult___fst_exp__h442789 or _theResult___exp__h443305) + always@(guard__h667889 or + _theResult___fst_exp__h675988 or _theResult___exp__h676504) begin - case (guard__h434690) + case (guard__h667889) 2'b0: - CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97 = - _theResult___fst_exp__h442789; + CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116 = + _theResult___fst_exp__h675988; 2'b01, 2'b10, 2'b11: - CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97 = - _theResult___exp__h443305; + CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116 = + _theResult___exp__h676504; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96 or - CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 or - _theResult___fst_exp__h442789) + CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115 or + CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11209 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11212 or + _theResult___fst_exp__h675988) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h443383 = - CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96; + _theResult___fst_exp__h676582 = + CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115; 3'd1: - _theResult___fst_exp__h443383 = - CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97; + _theResult___fst_exp__h676582 = + CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116; 3'd2: - _theResult___fst_exp__h443383 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090; + _theResult___fst_exp__h676582 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11209; 3'd3: - _theResult___fst_exp__h443383 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093; - 3'd4: _theResult___fst_exp__h443383 = _theResult___fst_exp__h442789; - default: _theResult___fst_exp__h443383 = 8'd0; + _theResult___fst_exp__h676582 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11212; + 3'd4: _theResult___fst_exp__h676582 = _theResult___fst_exp__h675988; + default: _theResult___fst_exp__h676582 = 8'd0; endcase end - always@(guard__h452327 or - _theResult___fst_exp__h460555 or - out_exp__h461074 or _theResult___exp__h461071) + always@(guard__h685526 or + _theResult___fst_exp__h693754 or + out_exp__h694273 or _theResult___exp__h694270) begin - case (guard__h452327) + case (guard__h685526) 2'b0, 2'b01: - CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102 = - _theResult___fst_exp__h460555; + CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121 = + _theResult___fst_exp__h693754; 2'b10: - CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102 = - out_exp__h461074; + CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121 = + out_exp__h694273; 2'b11: - CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102 = - _theResult___exp__h461071; + CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121 = + _theResult___exp__h694270; endcase end - always@(guard__h452327 or - _theResult___fst_exp__h460555 or _theResult___exp__h461071) + always@(guard__h685526 or + _theResult___fst_exp__h693754 or _theResult___exp__h694270) begin - case (guard__h452327) + case (guard__h685526) 2'b0: - CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103 = - _theResult___fst_exp__h460555; + CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122 = + _theResult___fst_exp__h693754; 2'b01, 2'b10, 2'b11: - CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103 = - _theResult___exp__h461071; + CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122 = + _theResult___exp__h694270; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102 or - CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 or - _theResult___fst_exp__h460555) + CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121 or + CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11756 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11758 or + _theResult___fst_exp__h693754) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h461149 = - CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102; + _theResult___fst_exp__h694348 = + CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121; 3'd1: - _theResult___fst_exp__h461149 = - CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103; + _theResult___fst_exp__h694348 = + CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122; 3'd2: - _theResult___fst_exp__h461149 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637; + _theResult___fst_exp__h694348 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11756; 3'd3: - _theResult___fst_exp__h461149 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639; - 3'd4: _theResult___fst_exp__h461149 = _theResult___fst_exp__h460555; - default: _theResult___fst_exp__h461149 = 8'd0; + _theResult___fst_exp__h694348 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11758; + 3'd4: _theResult___fst_exp__h694348 = _theResult___fst_exp__h693754; + default: _theResult___fst_exp__h694348 = 8'd0; endcase end - always@(guard__h461163 or - _theResult___fst_exp__h469240 or - out_exp__h469710 or _theResult___exp__h469707) + always@(guard__h694362 or + _theResult___fst_exp__h702439 or + out_exp__h702909 or _theResult___exp__h702906) begin - case (guard__h461163) + case (guard__h694362) 2'b0, 2'b01: - CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107 = - _theResult___fst_exp__h469240; + CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126 = + _theResult___fst_exp__h702439; 2'b10: - CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107 = - out_exp__h469710; + CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126 = + out_exp__h702909; 2'b11: - CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107 = - _theResult___exp__h469707; + CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126 = + _theResult___exp__h702906; endcase end - always@(guard__h461163 or - _theResult___fst_exp__h469240 or _theResult___exp__h469707) + always@(guard__h694362 or + _theResult___fst_exp__h702439 or _theResult___exp__h702906) begin - case (guard__h461163) + case (guard__h694362) 2'b0: - CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108 = - _theResult___fst_exp__h469240; + CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127 = + _theResult___fst_exp__h702439; 2'b01, 2'b10, 2'b11: - CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108 = - _theResult___exp__h469707; + CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127 = + _theResult___exp__h702906; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107 or - CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 or - _theResult___fst_exp__h469240) + CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126 or + CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11825 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11827 or + _theResult___fst_exp__h702439) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h469785 = - CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107; + _theResult___fst_exp__h702984 = + CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126; 3'd1: - _theResult___fst_exp__h469785 = - CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108; + _theResult___fst_exp__h702984 = + CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127; 3'd2: - _theResult___fst_exp__h469785 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706; + _theResult___fst_exp__h702984 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11825; 3'd3: - _theResult___fst_exp__h469785 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708; - 3'd4: _theResult___fst_exp__h469785 = _theResult___fst_exp__h469240; - default: _theResult___fst_exp__h469785 = 8'd0; + _theResult___fst_exp__h702984 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11827; + 3'd4: _theResult___fst_exp__h702984 = _theResult___fst_exp__h702439; + default: _theResult___fst_exp__h702984 = 8'd0; endcase end - always@(guard__h443397 or - _theResult___snd__h451396 or - out_sfd__h451891 or _theResult___sfd__h451888) + always@(guard__h676596 or + _theResult___snd__h684595 or + out_sfd__h685090 or _theResult___sfd__h685087) begin - case (guard__h443397) + case (guard__h676596) 2'b0, 2'b01: - CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109 = - _theResult___snd__h451396[56:34]; + CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128 = + _theResult___snd__h684595[56:34]; 2'b10: - CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109 = - out_sfd__h451891; + CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128 = + out_sfd__h685090; 2'b11: - CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109 = - _theResult___sfd__h451888; + CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128 = + _theResult___sfd__h685087; endcase end - always@(guard__h443397 or - _theResult___snd__h451396 or _theResult___sfd__h451888) + always@(guard__h676596 or + _theResult___snd__h684595 or _theResult___sfd__h685087) begin - case (guard__h443397) + case (guard__h676596) 2'b0: - CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110 = - _theResult___snd__h451396[56:34]; + CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129 = + _theResult___snd__h684595[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110 = - _theResult___sfd__h451888; + CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129 = + _theResult___sfd__h685087; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109 or - CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 or - _theResult___snd__h451396) + CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128 or + CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11875 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11877 or + _theResult___snd__h684595) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h451966 = - CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109; + _theResult___fst_sfd__h685165 = + CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128; 3'd1: - _theResult___fst_sfd__h451966 = - CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110; + _theResult___fst_sfd__h685165 = + CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129; 3'd2: - _theResult___fst_sfd__h451966 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756; + _theResult___fst_sfd__h685165 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11875; 3'd3: - _theResult___fst_sfd__h451966 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758; - 3'd4: _theResult___fst_sfd__h451966 = _theResult___snd__h451396[56:34]; - default: _theResult___fst_sfd__h451966 = 23'd0; + _theResult___fst_sfd__h685165 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11877; + 3'd4: _theResult___fst_sfd__h685165 = _theResult___snd__h684595[56:34]; + default: _theResult___fst_sfd__h685165 = 23'd0; endcase end - always@(guard__h434690 or - sfdin__h442783 or out_sfd__h443309 or _theResult___sfd__h443306) + always@(guard__h667889 or + sfdin__h675982 or out_sfd__h676508 or _theResult___sfd__h676505) begin - case (guard__h434690) + case (guard__h667889) 2'b0, 2'b01: - CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111 = - sfdin__h442783[56:34]; + CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130 = + sfdin__h675982[56:34]; 2'b10: - CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111 = - out_sfd__h443309; + CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130 = + out_sfd__h676508; 2'b11: - CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111 = - _theResult___sfd__h443306; + CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130 = + _theResult___sfd__h676505; endcase end - always@(guard__h434690 or sfdin__h442783 or _theResult___sfd__h443306) + always@(guard__h667889 or sfdin__h675982 or _theResult___sfd__h676505) begin - case (guard__h434690) + case (guard__h667889) 2'b0: - CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112 = - sfdin__h442783[56:34]; + CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131 = + sfdin__h675982[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112 = - _theResult___sfd__h443306; + CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131 = + _theResult___sfd__h676505; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111 or - CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 or - sfdin__h442783) + CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130 or + CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11856 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11858 or + sfdin__h675982) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h443384 = - CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111; + _theResult___fst_sfd__h676583 = + CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130; 3'd1: - _theResult___fst_sfd__h443384 = - CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112; + _theResult___fst_sfd__h676583 = + CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131; 3'd2: - _theResult___fst_sfd__h443384 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737; + _theResult___fst_sfd__h676583 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11856; 3'd3: - _theResult___fst_sfd__h443384 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739; - 3'd4: _theResult___fst_sfd__h443384 = sfdin__h442783[56:34]; - default: _theResult___fst_sfd__h443384 = 23'd0; + _theResult___fst_sfd__h676583 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11858; + 3'd4: _theResult___fst_sfd__h676583 = sfdin__h675982[56:34]; + default: _theResult___fst_sfd__h676583 = 23'd0; endcase end - always@(guard__h452327 or - sfdin__h460549 or out_sfd__h461075 or _theResult___sfd__h461072) + always@(guard__h685526 or + sfdin__h693748 or out_sfd__h694274 or _theResult___sfd__h694271) begin - case (guard__h452327) + case (guard__h685526) 2'b0, 2'b01: - CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113 = - sfdin__h460549[56:34]; + CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132 = + sfdin__h693748[56:34]; 2'b10: - CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113 = - out_sfd__h461075; + CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132 = + out_sfd__h694274; 2'b11: - CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113 = - _theResult___sfd__h461072; + CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132 = + _theResult___sfd__h694271; endcase end - always@(guard__h452327 or sfdin__h460549 or _theResult___sfd__h461072) + always@(guard__h685526 or sfdin__h693748 or _theResult___sfd__h694271) begin - case (guard__h452327) + case (guard__h685526) 2'b0: - CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114 = - sfdin__h460549[56:34]; + CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133 = + sfdin__h693748[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114 = - _theResult___sfd__h461072; + CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133 = + _theResult___sfd__h694271; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113 or - CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 or - sfdin__h460549) + CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132 or + CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11902 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11904 or + sfdin__h693748) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h461150 = - CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113; + _theResult___fst_sfd__h694349 = + CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132; 3'd1: - _theResult___fst_sfd__h461150 = - CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114; + _theResult___fst_sfd__h694349 = + CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133; 3'd2: - _theResult___fst_sfd__h461150 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783; + _theResult___fst_sfd__h694349 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11902; 3'd3: - _theResult___fst_sfd__h461150 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785; - 3'd4: _theResult___fst_sfd__h461150 = sfdin__h460549[56:34]; - default: _theResult___fst_sfd__h461150 = 23'd0; + _theResult___fst_sfd__h694349 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11904; + 3'd4: _theResult___fst_sfd__h694349 = sfdin__h693748[56:34]; + default: _theResult___fst_sfd__h694349 = 23'd0; endcase end - always@(guard__h461163 or - _theResult___snd__h469186 or - out_sfd__h469711 or _theResult___sfd__h469708) + always@(guard__h694362 or + _theResult___snd__h702385 or + out_sfd__h702910 or _theResult___sfd__h702907) begin - case (guard__h461163) + case (guard__h694362) 2'b0, 2'b01: - CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115 = - _theResult___snd__h469186[56:34]; + CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134 = + _theResult___snd__h702385[56:34]; 2'b10: - CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115 = - out_sfd__h469711; + CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134 = + out_sfd__h702910; 2'b11: - CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115 = - _theResult___sfd__h469708; + CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134 = + _theResult___sfd__h702907; endcase end - always@(guard__h461163 or - _theResult___snd__h469186 or _theResult___sfd__h469708) + always@(guard__h694362 or + _theResult___snd__h702385 or _theResult___sfd__h702907) begin - case (guard__h461163) + case (guard__h694362) 2'b0: - CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116 = - _theResult___snd__h469186[56:34]; + CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135 = + _theResult___snd__h702385[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116 = - _theResult___sfd__h469708; + CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135 = + _theResult___sfd__h702907; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115 or - CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 or - _theResult___snd__h469186) + CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134 or + CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11921 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11923 or + _theResult___snd__h702385) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h469786 = - CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115; + _theResult___fst_sfd__h702985 = + CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134; 3'd1: - _theResult___fst_sfd__h469786 = - CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116; + _theResult___fst_sfd__h702985 = + CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135; 3'd2: - _theResult___fst_sfd__h469786 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802; + _theResult___fst_sfd__h702985 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11921; 3'd3: - _theResult___fst_sfd__h469786 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804; - 3'd4: _theResult___fst_sfd__h469786 = _theResult___snd__h469186[56:34]; - default: _theResult___fst_sfd__h469786 = 23'd0; + _theResult___fst_sfd__h702985 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11923; + 3'd4: _theResult___fst_sfd__h702985 = _theResult___snd__h702385[56:34]; + default: _theResult___fst_sfd__h702985 = 23'd0; endcase end - always@(guard__h434690 or + always@(guard__h667889 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h434690) + case (guard__h667889) 2'b0, 2'b01, 2'b10: - CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = + CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q136 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = - guard__h434690 == 2'b11 && + CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q136 = + guard__h667889 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 or - guard__h434690) + CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q136 or + guard__h667889) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117; + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009 = + CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q136; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - (guard__h434690 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009 = + (guard__h667889 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h434690 == 2'b01 || guard__h434690 == 2'b10 || - guard__h434690 == 2'b11) && + (guard__h667889 == 2'b01 || guard__h667889 == 2'b10 || + guard__h667889 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == 3'd4 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h434690 or + always@(guard__h667889 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h434690) + case (guard__h667889) 2'b0, 2'b01, 2'b10: - CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q137 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = - guard__h434690 != 2'b11 || + CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q137 = + guard__h667889 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or - guard__h434690) + CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q137 or + guard__h667889) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118; + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953 = + CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q137; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - (guard__h434690 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953 = + (guard__h667889 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h434690 != 2'b01 && guard__h434690 != 2'b10 && - guard__h434690 != 2'b11 || + guard__h667889 != 2'b01 && guard__h667889 != 2'b10 && + guard__h667889 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h443397 or + always@(guard__h676596 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h443397) + case (guard__h676596) 2'b0, 2'b01, 2'b10: - CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = - guard__h443397 == 2'b11 && + CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = + guard__h676596 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or - guard__h443397) + CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 or + guard__h676596) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016 = + CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - (guard__h443397 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016 = + (guard__h676596 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h443397 == 2'b01 || guard__h443397 == 2'b10 || - guard__h443397 == 2'b11) && + (guard__h676596 == 2'b01 || guard__h676596 == 2'b10 || + guard__h676596 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == 3'd4 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h443397 or + always@(guard__h676596 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h443397) + case (guard__h676596) 2'b0, 2'b01, 2'b10: - CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = - guard__h443397 != 2'b11 || + CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = + guard__h676596 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or - guard__h443397) + CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 or + guard__h676596) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966 = + CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - (guard__h443397 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966 = + (guard__h676596 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h443397 != 2'b01 && guard__h443397 != 2'b10 && - guard__h443397 != 2'b11 || + guard__h676596 != 2'b01 && guard__h676596 != 2'b10 && + guard__h676596 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h452327 or + always@(guard__h685526 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h452327) + case (guard__h685526) 2'b0, 2'b01, 2'b10: - CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = + CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = - guard__h452327 == 2'b11 && + CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = + guard__h685526 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 or - guard__h452327) + CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 or + guard__h685526) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121; + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026 = + CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - (guard__h452327 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026 = + (guard__h685526 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h452327 == 2'b01 || guard__h452327 == 2'b10 || - guard__h452327 == 2'b11) && + (guard__h685526 == 2'b01 || guard__h685526 == 2'b10 || + guard__h685526 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == 3'd4 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h452327 or + always@(guard__h685526 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h452327) + case (guard__h685526) 2'b0, 2'b01, 2'b10: - CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = + CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = - guard__h452327 != 2'b11 || + CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141 = + guard__h685526 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 or - guard__h452327) + CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141 or + guard__h685526) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122; + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983 = + CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - (guard__h452327 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983 = + (guard__h685526 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h452327 != 2'b01 && guard__h452327 != 2'b10 && - guard__h452327 != 2'b11 || + guard__h685526 != 2'b01 && guard__h685526 != 2'b10 && + guard__h685526 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h461163 or + always@(guard__h694362 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h461163) + case (guard__h694362) 2'b0, 2'b01, 2'b10: - CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = + CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = - guard__h461163 == 2'b11 && + CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142 = + guard__h694362 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or - guard__h461163) + CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142 or + guard__h694362) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123; + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033 = + CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - (guard__h461163 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033 = + (guard__h694362 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h461163 == 2'b01 || guard__h461163 == 2'b10 || - guard__h461163 == 2'b11) && + (guard__h694362 == 2'b01 || guard__h694362 == 2'b10 || + guard__h694362 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == 3'd4 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h461163 or + always@(guard__h694362 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h461163) + case (guard__h694362) 2'b0, 2'b01, 2'b10: - CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = + CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = - guard__h461163 != 2'b11 || + CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = + guard__h694362 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 or - guard__h461163) + CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 or + guard__h694362) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124; + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996 = + CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143; 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - (guard__h461163 == 2'b0) ? + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996 = + (guard__h694362 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h461163 != 2'b01 && guard__h461163 != 2'b10 && - guard__h461163 != 2'b11 || + guard__h694362 != 2'b01 && guard__h694362 != 2'b10 && + guard__h694362 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; @@ -32566,9 +41019,9 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900 = + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12019 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12019 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == 3'd4 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; @@ -32579,9 +41032,9 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11970 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11970 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != 3'd4 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; @@ -32594,1841 +41047,1951 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12529 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; 5'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12529 = coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put; 5'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12529 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393 = + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12529 = coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h490713 or - _theResult___fst_exp__h498674 or _theResult___exp__h499329) + always@(guard__h726252 or + _theResult___fst_exp__h734213 or _theResult___exp__h734868) begin - case (guard__h490713) + case (guard__h726252) 2'b0: - CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135 = - _theResult___fst_exp__h498674; + CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154 = + _theResult___fst_exp__h734213; 2'b01, 2'b10, 2'b11: - CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135 = - _theResult___exp__h499329; + CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154 = + _theResult___exp__h734868; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h498674 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005 or - CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135) + _theResult___fst_exp__h734213 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13148 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13146 or + CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = - _theResult___fst_exp__h498674; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 = + _theResult___fst_exp__h734213; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13148; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13146; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = - CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 = + CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 = 11'd0; endcase end - always@(guard__h490713 or - _theResult___fst_exp__h498674 or - out_exp__h499332 or _theResult___exp__h499329) + always@(guard__h726252 or + _theResult___fst_exp__h734213 or + out_exp__h734871 or _theResult___exp__h734868) begin - case (guard__h490713) + case (guard__h726252) 2'b0, 2'b01: - CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136 = - _theResult___fst_exp__h498674; + CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155 = + _theResult___fst_exp__h734213; 2'b10: - CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136 = - out_exp__h499332; + CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155 = + out_exp__h734871; 2'b11: - CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136 = - _theResult___exp__h499329; + CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155 = + _theResult___exp__h734868; endcase end - always@(guard__h490713 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h726252 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h490713) + case (guard__h726252) 2'b0, 2'b01, 2'b10: - CASE_guard90713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + CASE_guard26252_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard90713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = - guard__h490713 == 2'b11 && + CASE_guard26252_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h726252 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h490713) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = - (guard__h490713 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h490713 == 2'b01 || guard__h490713 == 2'b10 || - guard__h490713 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - endcase - end - always@(guard__h500025 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h500025) - 2'b0, 2'b01, 2'b10: - CASE_guard00025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - 2'd3: - CASE_guard00025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = - guard__h500025 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500025) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = - (guard__h500025 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h500025 == 2'b01 || guard__h500025 == 2'b10 || - guard__h500025 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - endcase - end - always@(guard__h509094 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h509094) - 2'b0, 2'b01, 2'b10: - CASE_guard09094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - 2'd3: - CASE_guard09094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = - guard__h509094 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509094) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = - (guard__h509094 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h509094 == 2'b01 || guard__h509094 == 2'b10 || - guard__h509094 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - endcase - end - always@(guard__h568715 or - _theResult___fst_exp__h576676 or _theResult___exp__h577331) - begin - case (guard__h568715) - 2'b0: - CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152 = - _theResult___fst_exp__h576676; - 2'b01, 2'b10, 2'b11: - CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152 = - _theResult___exp__h577331; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h576676 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715 or - CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = - _theResult___fst_exp__h576676; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = - CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = - 11'd0; - endcase - end - always@(guard__h568715 or - _theResult___fst_exp__h576676 or - out_exp__h577334 or _theResult___exp__h577331) - begin - case (guard__h568715) - 2'b0, 2'b01: - CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153 = - _theResult___fst_exp__h576676; - 2'b10: - CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153 = - out_exp__h577334; - 2'b11: - CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153 = - _theResult___exp__h577331; - endcase - end - always@(guard__h568715 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h568715) - 2'b0, 2'b01, 2'b10: - CASE_guard68715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - 2'd3: - CASE_guard68715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = - guard__h568715 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568715) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = - (guard__h568715 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h568715 == 2'b01 || guard__h568715 == 2'b10 || - guard__h568715 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - endcase - end - always@(guard__h578027 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h578027) - 2'b0, 2'b01, 2'b10: - CASE_guard78027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - 2'd3: - CASE_guard78027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h578027 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578027) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h726252) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h578027 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h578027 == 2'b01 || guard__h578027 == 2'b10 || - guard__h578027 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + (guard__h726252 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171] : + (guard__h726252 == 2'b01 || guard__h726252 == 2'b10 || + guard__h726252 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h587096 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h735564 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587096) + case (guard__h735564) 2'b0, 2'b01, 2'b10: - CASE_guard87096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + CASE_guard35564_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard87096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h587096 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + CASE_guard35564_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h735564 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587096) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h735564) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h587096 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h587096 == 2'b01 || guard__h587096 == 2'b10 || - guard__h587096 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + (guard__h735564 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171] : + (guard__h735564 == 2'b01 || guard__h735564 == 2'b10 || + guard__h735564 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + endcase + end + always@(guard__h744633 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h744633) + 2'b0, 2'b01, 2'b10: + CASE_guard44633_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + 2'd3: + CASE_guard44633_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = + guard__h744633 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h744633) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = + (guard__h744633 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171] : + (guard__h744633 == 2'b01 || guard__h744633 == 2'b10 || + guard__h744633 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + endcase + end + always@(guard__h804409 or + _theResult___fst_exp__h812370 or _theResult___exp__h813025) + begin + case (guard__h804409) + 2'b0: + CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171 = + _theResult___fst_exp__h812370; + 2'b01, 2'b10, 2'b11: + CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171 = + _theResult___exp__h813025; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h812370 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13863 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13861 or + CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 = + _theResult___fst_exp__h812370; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13863; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13861; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 = + CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 = + 11'd0; + endcase + end + always@(guard__h804409 or + _theResult___fst_exp__h812370 or + out_exp__h813028 or _theResult___exp__h813025) + begin + case (guard__h804409) + 2'b0, 2'b01: + CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172 = + _theResult___fst_exp__h812370; + 2'b10: + CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172 = + out_exp__h813028; + 2'b11: + CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172 = + _theResult___exp__h813025; + endcase + end + always@(guard__h804409 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h804409) + 2'b0, 2'b01, 2'b10: + CASE_guard04409_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 2'd3: + CASE_guard04409_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = + guard__h804409 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804409) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q174 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q174 = + (guard__h804409 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43] : + (guard__h804409 == 2'b01 || guard__h804409 == 2'b10 || + guard__h804409 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q174 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h578027 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h813721 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h578027) + case (guard__h813721) 2'b0, 2'b01, 2'b10: - CASE_guard78027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + CASE_guard13721_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard78027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = - guard__h578027 != 2'b11 || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + CASE_guard13721_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = + guard__h813721 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578027) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813721) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q176 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q176 = + (guard__h813721 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43] : + (guard__h813721 == 2'b01 || guard__h813721 == 2'b10 || + guard__h813721 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q176 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + endcase + end + always@(guard__h822790 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h822790) + 2'b0, 2'b01, 2'b10: + CASE_guard22790_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 2'd3: + CASE_guard22790_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = + guard__h822790 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822790) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q178 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q178 = + (guard__h822790 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43] : + (guard__h822790 == 2'b01 || guard__h822790 == 2'b10 || + guard__h822790 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q178 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + endcase + end + always@(guard__h813721 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h813721) + 2'b0, 2'b01, 2'b10: + CASE_guard13721_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 2'd3: + CASE_guard13721_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = + guard__h813721 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813721) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q180 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = - (guard__h578027 == 2'b0) ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q180 = + (guard__h813721 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h578027 != 2'b01 && guard__h578027 != 2'b10 && - guard__h578027 != 2'b11 || + guard__h813721 != 2'b01 && guard__h813721 != 2'b10 && + guard__h813721 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q180 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h587096 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h822790 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587096) + case (guard__h822790) 2'b0, 2'b01, 2'b10: - CASE_guard87096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + CASE_guard22790_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard87096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = - guard__h587096 != 2'b11 || + CASE_guard22790_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = + guard__h822790 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587096) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822790) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q182 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h587096 == 2'b0) ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q182 = + (guard__h822790 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h587096 != 2'b01 && guard__h587096 != 2'b10 && - guard__h587096 != 2'b11 || + guard__h822790 != 2'b01 && guard__h822790 != 2'b10 && + guard__h822790 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q182 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h568715 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h804409 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h568715) + case (guard__h804409) 2'b0, 2'b01, 2'b10: - CASE_guard68715_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + CASE_guard04409_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard68715_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = - guard__h568715 != 2'b11 || + CASE_guard04409_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = + guard__h804409 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568715) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804409) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q184 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h568715 == 2'b0) ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q184 = + (guard__h804409 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h568715 != 2'b01 && guard__h568715 != 2'b10 && - guard__h568715 != 2'b11 || + guard__h804409 != 2'b01 && guard__h804409 != 2'b10 && + guard__h804409 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q184 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h529514 or - _theResult___fst_exp__h537475 or _theResult___exp__h538130) + always@(guard__h765105 or + _theResult___fst_exp__h773066 or _theResult___exp__h773721) begin - case (guard__h529514) + case (guard__h765105) 2'b0: - CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175 = - _theResult___fst_exp__h537475; + CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194 = + _theResult___fst_exp__h773066; 2'b01, 2'b10, 2'b11: - CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175 = - _theResult___exp__h538130; + CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194 = + _theResult___exp__h773721; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h537475 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478 or - CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175) + _theResult___fst_exp__h773066 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14633 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14631 or + CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = - _theResult___fst_exp__h537475; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 = + _theResult___fst_exp__h773066; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14633; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14631; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = - CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 = + CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 = 11'd0; endcase end - always@(guard__h529514 or - _theResult___fst_exp__h537475 or - out_exp__h538133 or _theResult___exp__h538130) + always@(guard__h765105 or + _theResult___fst_exp__h773066 or + out_exp__h773724 or _theResult___exp__h773721) begin - case (guard__h529514) + case (guard__h765105) 2'b0, 2'b01: - CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176 = - _theResult___fst_exp__h537475; + CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195 = + _theResult___fst_exp__h773066; 2'b10: - CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176 = - out_exp__h538133; + CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195 = + out_exp__h773724; 2'b11: - CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176 = - _theResult___exp__h538130; + CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195 = + _theResult___exp__h773721; endcase end - always@(guard__h538826 or - _theResult___fst_exp__h547052 or _theResult___exp__h547781) + always@(guard__h774417 or + _theResult___fst_exp__h782643 or _theResult___exp__h783372) begin - case (guard__h538826) + case (guard__h774417) 2'b0: - CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177 = - _theResult___fst_exp__h547052; + CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196 = + _theResult___fst_exp__h782643; 2'b01, 2'b10, 2'b11: - CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177 = - _theResult___exp__h547781; + CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196 = + _theResult___exp__h783372; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h547052 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516 or - CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177) + _theResult___fst_exp__h782643 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14671 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14669 or + CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = - _theResult___fst_exp__h547052; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 = + _theResult___fst_exp__h782643; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14671; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14669; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = - CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 = + CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 = 11'd0; endcase end - always@(guard__h538826 or - _theResult___fst_exp__h547052 or - out_exp__h547784 or _theResult___exp__h547781) + always@(guard__h774417 or + _theResult___fst_exp__h782643 or + out_exp__h783375 or _theResult___exp__h783372) begin - case (guard__h538826) + case (guard__h774417) 2'b0, 2'b01: - CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178 = - _theResult___fst_exp__h547052; + CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197 = + _theResult___fst_exp__h782643; 2'b10: - CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178 = - out_exp__h547784; + CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197 = + out_exp__h783375; 2'b11: - CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178 = - _theResult___exp__h547781; + CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197 = + _theResult___exp__h783372; endcase end - always@(guard__h547895 or - _theResult___fst_exp__h555885 or _theResult___exp__h556565) + always@(guard__h783486 or + _theResult___fst_exp__h791476 or _theResult___exp__h792156) begin - case (guard__h547895) + case (guard__h783486) 2'b0: - CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179 = - _theResult___fst_exp__h555885; + CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q198 = + _theResult___fst_exp__h791476; 2'b01, 2'b10, 2'b11: - CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179 = - _theResult___exp__h556565; + CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q198 = + _theResult___exp__h792156; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h555885 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547 or - CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179) + _theResult___fst_exp__h791476 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14702 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14700 or + CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q198) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = - _theResult___fst_exp__h555885; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 = + _theResult___fst_exp__h791476; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14702; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14700; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = - CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 = + CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q198; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 = 11'd0; endcase end - always@(guard__h547895 or - _theResult___fst_exp__h555885 or - out_exp__h556568 or _theResult___exp__h556565) + always@(guard__h783486 or + _theResult___fst_exp__h791476 or + out_exp__h792159 or _theResult___exp__h792156) begin - case (guard__h547895) + case (guard__h783486) 2'b0, 2'b01: - CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180 = - _theResult___fst_exp__h555885; + CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q199 = + _theResult___fst_exp__h791476; 2'b10: - CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180 = - out_exp__h556568; + CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q199 = + out_exp__h792159; 2'b11: - CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180 = - _theResult___exp__h556565; + CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q199 = + _theResult___exp__h792156; endcase end - always@(guard__h587096 or - _theResult___fst_exp__h595086 or _theResult___exp__h595766) + always@(guard__h813721 or + _theResult___fst_exp__h821947 or _theResult___exp__h822676) begin - case (guard__h587096) + case (guard__h813721) 2'b0: - CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181 = - _theResult___fst_exp__h595086; + CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q200 = + _theResult___fst_exp__h821947; 2'b01, 2'b10, 2'b11: - CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181 = - _theResult___exp__h595766; + CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q200 = + _theResult___exp__h822676; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h595086 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784 or - CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181) + _theResult___fst_exp__h821947 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13901 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13899 or + CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q200) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = - _theResult___fst_exp__h595086; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 = + _theResult___fst_exp__h821947; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13901; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13899; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = - CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 = + CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q200; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 = 11'd0; endcase end - always@(guard__h587096 or - _theResult___fst_exp__h595086 or - out_exp__h595769 or _theResult___exp__h595766) + always@(guard__h813721 or + _theResult___fst_exp__h821947 or + out_exp__h822679 or _theResult___exp__h822676) begin - case (guard__h587096) + case (guard__h813721) 2'b0, 2'b01: - CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182 = - _theResult___fst_exp__h595086; + CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q201 = + _theResult___fst_exp__h821947; 2'b10: - CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182 = - out_exp__h595769; + CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q201 = + out_exp__h822679; 2'b11: - CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182 = - _theResult___exp__h595766; + CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q201 = + _theResult___exp__h822676; endcase end - always@(guard__h578027 or - _theResult___fst_exp__h586253 or _theResult___exp__h586982) + always@(guard__h822790 or + _theResult___fst_exp__h830780 or _theResult___exp__h831460) begin - case (guard__h578027) + case (guard__h822790) 2'b0: - CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183 = - _theResult___fst_exp__h586253; + CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202 = + _theResult___fst_exp__h830780; 2'b01, 2'b10, 2'b11: - CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183 = - _theResult___exp__h586982; + CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202 = + _theResult___exp__h831460; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h586253 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753 or - CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183) + _theResult___fst_exp__h830780 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13932 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13930 or + CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = - _theResult___fst_exp__h586253; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 = + _theResult___fst_exp__h830780; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13932; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13930; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = - CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 = + CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 = 11'd0; endcase end - always@(guard__h578027 or - _theResult___fst_exp__h586253 or - out_exp__h586985 or _theResult___exp__h586982) + always@(guard__h822790 or + _theResult___fst_exp__h830780 or + out_exp__h831463 or _theResult___exp__h831460) begin - case (guard__h578027) + case (guard__h822790) 2'b0, 2'b01: - CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184 = - _theResult___fst_exp__h586253; + CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203 = + _theResult___fst_exp__h830780; 2'b10: - CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184 = - out_exp__h586985; + CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203 = + out_exp__h831463; 2'b11: - CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184 = - _theResult___exp__h586982; + CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203 = + _theResult___exp__h831460; endcase end - always@(guard__h529514 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h765105 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h529514) + case (guard__h765105) 2'b0, 2'b01, 2'b10: - CASE_guard29514_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + CASE_guard65105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard29514_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = - guard__h529514 == 2'b11 && + CASE_guard65105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = + guard__h765105 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529514) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765105) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q205 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = - (guard__h529514 == 2'b0) ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q205 = + (guard__h765105 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h529514 == 2'b01 || guard__h529514 == 2'b10 || - guard__h529514 == 2'b11) && + (guard__h765105 == 2'b01 || guard__h765105 == 2'b10 || + guard__h765105 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q205 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h538826 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h783486 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h538826) + case (guard__h783486) 2'b0, 2'b01, 2'b10: - CASE_guard38826_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + CASE_guard83486_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard38826_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = - guard__h538826 == 2'b11 && + CASE_guard83486_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = + guard__h783486 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538826) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783486) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q207 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = - (guard__h538826 == 2'b0) ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q207 = + (guard__h783486 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h538826 == 2'b01 || guard__h538826 == 2'b10 || - guard__h538826 == 2'b11) && + (guard__h783486 == 2'b01 || guard__h783486 == 2'b10 || + guard__h783486 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q207 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547895 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h774417 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547895) + case (guard__h774417) 2'b0, 2'b01, 2'b10: - CASE_guard47895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + CASE_guard74417_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = - guard__h547895 == 2'b11 && + CASE_guard74417_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = + guard__h774417 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547895) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774417) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q209 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = - (guard__h547895 == 2'b0) ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q209 = + (guard__h774417 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h547895 == 2'b01 || guard__h547895 == 2'b10 || - guard__h547895 == 2'b11) && + (guard__h774417 == 2'b01 || guard__h774417 == 2'b10 || + guard__h774417 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q209 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h538826 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h774417 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h538826) + case (guard__h774417) 2'b0, 2'b01, 2'b10: - CASE_guard38826_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + CASE_guard74417_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard38826_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = - guard__h538826 != 2'b11 || + CASE_guard74417_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = + guard__h774417 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538826) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774417) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q211 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - (guard__h538826 == 2'b0) ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q211 = + (guard__h774417 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h538826 != 2'b01 && guard__h538826 != 2'b10 && - guard__h538826 != 2'b11 || + guard__h774417 != 2'b01 && guard__h774417 != 2'b10 && + guard__h774417 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q211 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547895 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h783486 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547895) + case (guard__h783486) 2'b0, 2'b01, 2'b10: - CASE_guard47895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + CASE_guard83486_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = - guard__h547895 != 2'b11 || + CASE_guard83486_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = + guard__h783486 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547895) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783486) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q213 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h547895 == 2'b0) ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q213 = + (guard__h783486 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h547895 != 2'b01 && guard__h547895 != 2'b10 && - guard__h547895 != 2'b11 || + guard__h783486 != 2'b01 && guard__h783486 != 2'b10 && + guard__h783486 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q213 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h529514 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h765105 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h529514) + case (guard__h765105) 2'b0, 2'b01, 2'b10: - CASE_guard29514_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + CASE_guard65105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard29514_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = - guard__h529514 != 2'b11 || + CASE_guard65105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = + guard__h765105 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529514) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765105) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q215 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h529514 == 2'b0) ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q215 = + (guard__h765105 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h529514 != 2'b01 && guard__h529514 != 2'b10 && - guard__h529514 != 2'b11 || + guard__h765105 != 2'b01 && guard__h765105 != 2'b10 && + guard__h765105 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q215 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h529514 or - _theResult___snd__h537426 or _theResult___sfd__h538131) + always@(guard__h765105 or + _theResult___snd__h773017 or _theResult___sfd__h773722) begin - case (guard__h529514) + case (guard__h765105) 2'b0: - CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197 = - _theResult___snd__h537426[56:5]; + CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216 = + _theResult___snd__h773017[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197 = - _theResult___sfd__h538131; + CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216 = + _theResult___sfd__h773722; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h537426 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573 or - CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197) + _theResult___snd__h773017 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14728 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14726 or + CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = - _theResult___snd__h537426[56:5]; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 = + _theResult___snd__h773017[56:5]; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14728; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14726; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = - CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 = + CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 = 52'd0; endcase end - always@(guard__h529514 or - _theResult___snd__h537426 or - out_sfd__h538134 or _theResult___sfd__h538131) + always@(guard__h765105 or + _theResult___snd__h773017 or + out_sfd__h773725 or _theResult___sfd__h773722) begin - case (guard__h529514) + case (guard__h765105) 2'b0, 2'b01: - CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198 = - _theResult___snd__h537426[56:5]; + CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217 = + _theResult___snd__h773017[56:5]; 2'b10: - CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198 = - out_sfd__h538134; + CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217 = + out_sfd__h773725; 2'b11: - CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198 = - _theResult___sfd__h538131; + CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217 = + _theResult___sfd__h773722; endcase end - always@(guard__h538826 or sfdin__h547046 or _theResult___sfd__h547782) + always@(guard__h774417 or sfdin__h782637 or _theResult___sfd__h783373) begin - case (guard__h538826) + case (guard__h774417) 2'b0: - CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199 = - sfdin__h547046[56:5]; + CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218 = + sfdin__h782637[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199 = - _theResult___sfd__h547782; + CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218 = + _theResult___sfd__h783373; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h547046 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599 or - CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199) + sfdin__h782637 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14754 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14752 or + CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = - sfdin__h547046[56:5]; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 = + sfdin__h782637[56:5]; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14754; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14752; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = - CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 = + CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 = 52'd0; endcase end - always@(guard__h538826 or - sfdin__h547046 or out_sfd__h547785 or _theResult___sfd__h547782) + always@(guard__h774417 or + sfdin__h782637 or out_sfd__h783376 or _theResult___sfd__h783373) begin - case (guard__h538826) + case (guard__h774417) 2'b0, 2'b01: - CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200 = - sfdin__h547046[56:5]; + CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219 = + sfdin__h782637[56:5]; 2'b10: - CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200 = - out_sfd__h547785; + CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219 = + out_sfd__h783376; 2'b11: - CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200 = - _theResult___sfd__h547782; + CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219 = + _theResult___sfd__h783373; endcase end - always@(guard__h547895 or - _theResult___snd__h555831 or _theResult___sfd__h556566) + always@(guard__h783486 or + _theResult___snd__h791422 or _theResult___sfd__h792157) begin - case (guard__h547895) + case (guard__h783486) 2'b0: - CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201 = - _theResult___snd__h555831[56:5]; + CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220 = + _theResult___snd__h791422[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201 = - _theResult___sfd__h556566; + CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220 = + _theResult___sfd__h792157; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h555831 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618 or - CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201) + _theResult___snd__h791422 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14773 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14771 or + CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = - _theResult___snd__h555831[56:5]; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 = + _theResult___snd__h791422[56:5]; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14773; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14771; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = - CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 = + CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 = 52'd0; endcase end - always@(guard__h547895 or - _theResult___snd__h555831 or - out_sfd__h556569 or _theResult___sfd__h556566) + always@(guard__h783486 or + _theResult___snd__h791422 or + out_sfd__h792160 or _theResult___sfd__h792157) begin - case (guard__h547895) + case (guard__h783486) 2'b0, 2'b01: - CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202 = - _theResult___snd__h555831[56:5]; + CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221 = + _theResult___snd__h791422[56:5]; 2'b10: - CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202 = - out_sfd__h556569; + CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221 = + out_sfd__h792160; 2'b11: - CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202 = - _theResult___sfd__h556566; + CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221 = + _theResult___sfd__h792157; endcase end - always@(guard__h500025 or - _theResult___fst_exp__h508251 or _theResult___exp__h508980) + always@(guard__h735564 or + _theResult___fst_exp__h743790 or _theResult___exp__h744519) begin - case (guard__h500025) + case (guard__h735564) 2'b0: - CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203 = - _theResult___fst_exp__h508251; + CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222 = + _theResult___fst_exp__h743790; 2'b01, 2'b10, 2'b11: - CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203 = - _theResult___exp__h508980; + CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222 = + _theResult___exp__h744519; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h508251 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048 or - CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203) + _theResult___fst_exp__h743790 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13191 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13189 or + CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = - _theResult___fst_exp__h508251; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 = + _theResult___fst_exp__h743790; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13191; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13189; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = - CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 = + CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 = 11'd0; endcase end - always@(guard__h500025 or - _theResult___fst_exp__h508251 or - out_exp__h508983 or _theResult___exp__h508980) + always@(guard__h735564 or + _theResult___fst_exp__h743790 or + out_exp__h744522 or _theResult___exp__h744519) begin - case (guard__h500025) + case (guard__h735564) 2'b0, 2'b01: - CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204 = - _theResult___fst_exp__h508251; + CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223 = + _theResult___fst_exp__h743790; 2'b10: - CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204 = - out_exp__h508983; + CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223 = + out_exp__h744522; 2'b11: - CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204 = - _theResult___exp__h508980; + CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223 = + _theResult___exp__h744519; endcase end - always@(guard__h509094 or - _theResult___fst_exp__h517084 or _theResult___exp__h517764) + always@(guard__h744633 or + _theResult___fst_exp__h752623 or _theResult___exp__h753303) begin - case (guard__h509094) + case (guard__h744633) 2'b0: - CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205 = - _theResult___fst_exp__h517084; + CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224 = + _theResult___fst_exp__h752623; 2'b01, 2'b10, 2'b11: - CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205 = - _theResult___exp__h517764; + CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224 = + _theResult___exp__h753303; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h517084 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079 or - CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205) + _theResult___fst_exp__h752623 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13222 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13220 or + CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = - _theResult___fst_exp__h517084; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 = + _theResult___fst_exp__h752623; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13222; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13220; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = - CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 = + CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 = 11'd0; endcase end - always@(guard__h509094 or - _theResult___fst_exp__h517084 or - out_exp__h517767 or _theResult___exp__h517764) + always@(guard__h744633 or + _theResult___fst_exp__h752623 or + out_exp__h753306 or _theResult___exp__h753303) begin - case (guard__h509094) + case (guard__h744633) 2'b0, 2'b01: - CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206 = - _theResult___fst_exp__h517084; + CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225 = + _theResult___fst_exp__h752623; 2'b10: - CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206 = - out_exp__h517767; + CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225 = + out_exp__h753306; 2'b11: - CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206 = - _theResult___exp__h517764; + CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225 = + _theResult___exp__h753303; endcase end - always@(guard__h490713 or - _theResult___snd__h498625 or _theResult___sfd__h499330) + always@(guard__h726252 or + _theResult___snd__h734164 or _theResult___sfd__h734869) begin - case (guard__h490713) + case (guard__h726252) 2'b0: - CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207 = - _theResult___snd__h498625[56:5]; + CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226 = + _theResult___snd__h734164[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207 = - _theResult___sfd__h499330; + CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226 = + _theResult___sfd__h734869; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h498625 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105 or - CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207) + _theResult___snd__h734164 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13248 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13246 or + CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = - _theResult___snd__h498625[56:5]; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 = + _theResult___snd__h734164[56:5]; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13248; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13246; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = - CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 = + CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 = 52'd0; endcase end - always@(guard__h490713 or - _theResult___snd__h498625 or - out_sfd__h499333 or _theResult___sfd__h499330) + always@(guard__h726252 or + _theResult___snd__h734164 or + out_sfd__h734872 or _theResult___sfd__h734869) begin - case (guard__h490713) + case (guard__h726252) 2'b0, 2'b01: - CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208 = - _theResult___snd__h498625[56:5]; + CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227 = + _theResult___snd__h734164[56:5]; 2'b10: - CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208 = - out_sfd__h499333; + CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227 = + out_sfd__h734872; 2'b11: - CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208 = - _theResult___sfd__h499330; + CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227 = + _theResult___sfd__h734869; endcase end - always@(guard__h509094 or - _theResult___snd__h517030 or _theResult___sfd__h517765) + always@(guard__h744633 or + _theResult___snd__h752569 or _theResult___sfd__h753304) begin - case (guard__h509094) + case (guard__h744633) 2'b0: - CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209 = - _theResult___snd__h517030[56:5]; + CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q228 = + _theResult___snd__h752569[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209 = - _theResult___sfd__h517765; + CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q228 = + _theResult___sfd__h753304; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h517030 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151 or - CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209) + _theResult___snd__h752569 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13294 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13292 or + CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q228) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = - _theResult___snd__h517030[56:5]; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 = + _theResult___snd__h752569[56:5]; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13294; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13292; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = - CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 = + CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q228; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 = 52'd0; endcase end - always@(guard__h509094 or - _theResult___snd__h517030 or - out_sfd__h517768 or _theResult___sfd__h517765) + always@(guard__h744633 or + _theResult___snd__h752569 or + out_sfd__h753307 or _theResult___sfd__h753304) begin - case (guard__h509094) + case (guard__h744633) 2'b0, 2'b01: - CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210 = - _theResult___snd__h517030[56:5]; + CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q229 = + _theResult___snd__h752569[56:5]; 2'b10: - CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210 = - out_sfd__h517768; + CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q229 = + out_sfd__h753307; 2'b11: - CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210 = - _theResult___sfd__h517765; + CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q229 = + _theResult___sfd__h753304; endcase end - always@(guard__h500025 or sfdin__h508245 or _theResult___sfd__h508981) + always@(guard__h735564 or sfdin__h743784 or _theResult___sfd__h744520) begin - case (guard__h500025) + case (guard__h735564) 2'b0: - CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211 = - sfdin__h508245[56:5]; + CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q230 = + sfdin__h743784[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211 = - _theResult___sfd__h508981; + CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q230 = + _theResult___sfd__h744520; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h508245 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132 or - CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211) + sfdin__h743784 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13275 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13273 or + CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q230) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = - sfdin__h508245[56:5]; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 = + sfdin__h743784[56:5]; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13275; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13273; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = - CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 = + CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q230; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 = 52'd0; endcase end - always@(guard__h500025 or - sfdin__h508245 or out_sfd__h508984 or _theResult___sfd__h508981) + always@(guard__h735564 or + sfdin__h743784 or out_sfd__h744523 or _theResult___sfd__h744520) begin - case (guard__h500025) + case (guard__h735564) 2'b0, 2'b01: - CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212 = - sfdin__h508245[56:5]; + CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q231 = + sfdin__h743784[56:5]; 2'b10: - CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212 = - out_sfd__h508984; + CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q231 = + out_sfd__h744523; 2'b11: - CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212 = - _theResult___sfd__h508981; + CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q231 = + _theResult___sfd__h744520; endcase end - always@(guard__h568715 or - _theResult___snd__h576627 or _theResult___sfd__h577332) + always@(guard__h804409 or + _theResult___snd__h812321 or _theResult___sfd__h813026) begin - case (guard__h568715) + case (guard__h804409) 2'b0: - CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213 = - _theResult___snd__h576627[56:5]; + CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232 = + _theResult___snd__h812321[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213 = - _theResult___sfd__h577332; + CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232 = + _theResult___sfd__h813026; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h576627 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810 or - CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213) + _theResult___snd__h812321 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13958 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13956 or + CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = - _theResult___snd__h576627[56:5]; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 = + _theResult___snd__h812321[56:5]; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13958; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13956; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = - CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 = + CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 = 52'd0; endcase end - always@(guard__h568715 or - _theResult___snd__h576627 or - out_sfd__h577335 or _theResult___sfd__h577332) + always@(guard__h804409 or + _theResult___snd__h812321 or + out_sfd__h813029 or _theResult___sfd__h813026) begin - case (guard__h568715) + case (guard__h804409) 2'b0, 2'b01: - CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214 = - _theResult___snd__h576627[56:5]; + CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233 = + _theResult___snd__h812321[56:5]; 2'b10: - CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214 = - out_sfd__h577335; + CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233 = + out_sfd__h813029; 2'b11: - CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214 = - _theResult___sfd__h577332; + CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233 = + _theResult___sfd__h813026; endcase end - always@(guard__h578027 or sfdin__h586247 or _theResult___sfd__h586983) + always@(guard__h813721 or sfdin__h821941 or _theResult___sfd__h822677) begin - case (guard__h578027) + case (guard__h813721) 2'b0: - CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215 = - sfdin__h586247[56:5]; + CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234 = + sfdin__h821941[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215 = - _theResult___sfd__h586983; + CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234 = + _theResult___sfd__h822677; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h586247 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836 or - CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215) + sfdin__h821941 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13984 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13982 or + CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = - sfdin__h586247[56:5]; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 = + sfdin__h821941[56:5]; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13984; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13982; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = - CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 = + CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 = 52'd0; endcase end - always@(guard__h578027 or - sfdin__h586247 or out_sfd__h586986 or _theResult___sfd__h586983) + always@(guard__h813721 or + sfdin__h821941 or out_sfd__h822680 or _theResult___sfd__h822677) begin - case (guard__h578027) + case (guard__h813721) 2'b0, 2'b01: - CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216 = - sfdin__h586247[56:5]; + CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235 = + sfdin__h821941[56:5]; 2'b10: - CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216 = - out_sfd__h586986; + CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235 = + out_sfd__h822680; 2'b11: - CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216 = - _theResult___sfd__h586983; + CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235 = + _theResult___sfd__h822677; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10866 or - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10854 or - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10843) + coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15021 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15009 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14998) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10868 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10854; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15023 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15009; 5'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10868 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10843; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10868 = - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10866; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15023 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14998; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15023 = + coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15021; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10830 or - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10785 or - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10743) + coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d14985 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14940 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14898) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10832 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10785; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14987 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14940; 5'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10832 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10743; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10832 = - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10830; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14987 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14898; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14987 = + coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d14985; endcase end - always@(guard__h587096 or - _theResult___snd__h595032 or _theResult___sfd__h595767) + always@(guard__h822790 or + _theResult___snd__h830726 or _theResult___sfd__h831461) begin - case (guard__h587096) + case (guard__h822790) 2'b0: - CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217 = - _theResult___snd__h595032[56:5]; + CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236 = + _theResult___snd__h830726[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217 = - _theResult___sfd__h595767; + CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236 = + _theResult___sfd__h831461; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h595032 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855 or - CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217) + _theResult___snd__h830726 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14003 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14001 or + CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = - _theResult___snd__h595032[56:5]; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 = + _theResult___snd__h830726[56:5]; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14003; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14001; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = - CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 = + CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 = 52'd0; endcase end - always@(guard__h587096 or - _theResult___snd__h595032 or - out_sfd__h595770 or _theResult___sfd__h595767) + always@(guard__h822790 or + _theResult___snd__h830726 or + out_sfd__h831464 or _theResult___sfd__h831461) begin - case (guard__h587096) + case (guard__h822790) 2'b0, 2'b01: - CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218 = - _theResult___snd__h595032[56:5]; + CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237 = + _theResult___snd__h830726[56:5]; 2'b10: - CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218 = - out_sfd__h595770; + CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237 = + out_sfd__h831464; 2'b11: - CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218 = - _theResult___sfd__h595767; + CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237 = + _theResult___sfd__h831461; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10914 or - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10898 or - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10883) + coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15069 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15053 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15038) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10916 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10898; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15071 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15053; 5'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10916 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10883; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10916 = - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10914; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15071 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15038; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15071 = + coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15069; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10956 or - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10942 or - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10929) + coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15111 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15097 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15084) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10958 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10942; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15113 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15097; 5'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10958 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10929; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10958 = - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10956; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15113 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15084; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15113 = + coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15111; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10998 or - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10984 or - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10971) + coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15153 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15139 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15126) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d11000 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10984; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15155 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15139; 5'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d11000 = - NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10971; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d11000 = - coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10998; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15155 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15126; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d15155 = + coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15153; + endcase + end + always@(coreFix_aluExe_1_rsAlu$dispatchData) + begin + case (coreFix_aluExe_1_rsAlu$dispatchData[196:193]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15357 = + coreFix_aluExe_1_rsAlu$dispatchData[196:193]; + default: IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15357 = + 4'd11; + endcase + end + always@(coreFix_aluExe_1_rsAlu$dispatchData) + begin + case (coreFix_aluExe_1_rsAlu$dispatchData[192:190]) + 3'd2, 3'd3: + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15386 = + coreFix_aluExe_1_rsAlu$dispatchData[192:190]; + default: IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15386 = + 3'd4; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first) + begin + case (coreFix_aluExe_1_dispToRegQ$first[192:189]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15732 = + coreFix_aluExe_1_dispToRegQ$first[192:189]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15732 = + 4'd11; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first) + begin + case (coreFix_aluExe_1_dispToRegQ$first[188:186]) + 3'd2, 3'd3: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15761 = + coreFix_aluExe_1_dispToRegQ$first[188:186]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15761 = + 3'd4; + endcase + end + always@(IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15761) + begin + case (IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15761) + 3'd2, 3'd3: + CASE_IF_coreFix_aluExe_1_dispToRegQ_first__559_ETC__q238 = + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15761; + default: CASE_IF_coreFix_aluExe_1_dispToRegQ_first__559_ETC__q238 = + 3'd4; + endcase + end + always@(IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15732) + begin + case (IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15732) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + CASE_IF_coreFix_aluExe_1_dispToRegQ_first__559_ETC__q239 = + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15732; + default: CASE_IF_coreFix_aluExe_1_dispToRegQ_first__559_ETC__q239 = + 4'd11; + endcase + end + always@(IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15386) + begin + case (IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15386) + 3'd2, 3'd3: + CASE_IF_coreFix_aluExe_1_rsAlu_dispatchData__5_ETC__q240 = + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15386; + default: CASE_IF_coreFix_aluExe_1_rsAlu_dispatchData__5_ETC__q240 = + 3'd4; + endcase + end + always@(IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15357) + begin + case (IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15357) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + CASE_IF_coreFix_aluExe_1_rsAlu_dispatchData__5_ETC__q241 = + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15357; + default: CASE_IF_coreFix_aluExe_1_rsAlu_dispatchData__5_ETC__q241 = + 4'd11; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first) + begin + case (coreFix_aluExe_0_dispToRegQ$first[192:189]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18341 = + coreFix_aluExe_0_dispToRegQ$first[192:189]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18341 = + 4'd11; endcase end always@(coreFix_aluExe_1_regToExeQ$first) begin - case (coreFix_aluExe_1_regToExeQ$first[399:397]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219 = - coreFix_aluExe_1_regToExeQ$first[399:397]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219 = 3'd7; - endcase - end - always@(coreFix_aluExe_1_regToExeQ$first or - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219) - begin - case (coreFix_aluExe_1_regToExeQ$first[416:414]) - 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 = - coreFix_aluExe_1_regToExeQ$first[416:396]; - 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 = - { coreFix_aluExe_1_regToExeQ$first[416:414], - 9'h0AA, - coreFix_aluExe_1_regToExeQ$first[404:400], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219, - coreFix_aluExe_1_regToExeQ$first[396] }; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 = - { 3'd5, 18'h2AAAA }; + case (coreFix_aluExe_1_regToExeQ$first[784:781]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17235 = + coreFix_aluExe_1_regToExeQ$first[784:781]; + default: IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17235 = + 4'd11; endcase end always@(coreFix_aluExe_1_regToExeQ$first) begin - case (coreFix_aluExe_1_regToExeQ$first[394:383]) - 12'd3860, - 12'd3859, - 12'd3858, - 12'd3857, - 12'd2818, - 12'd2816, - 12'd836, - 12'd835, - 12'd834, - 12'd833, - 12'd832, - 12'd774, - 12'd773, - 12'd772, - 12'd771, - 12'd770, - 12'd769, - 12'd768, - 12'd384, - 12'd324, - 12'd323, - 12'd322, - 12'd321, - 12'd320, - 12'd262, - 12'd261, - 12'd260, - 12'd256, - 12'd2049, - 12'd2048, - 12'd3074, - 12'd3073, - 12'd3072, - 12'd3, - 12'd2, - 12'd1: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221 = - coreFix_aluExe_1_regToExeQ$first[394:383]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221 = - 12'd2303; + case (coreFix_aluExe_1_regToExeQ$first[780:778]) + 3'd2, 3'd3: + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17264 = + coreFix_aluExe_1_regToExeQ$first[780:778]; + default: IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17264 = + 3'd4; + endcase + end + always@(IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17264) + begin + case (IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17264) + 3'd2, 3'd3: + CASE_IF_coreFix_aluExe_1_regToExeQ_first__7179_ETC__q242 = + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17264; + default: CASE_IF_coreFix_aluExe_1_regToExeQ_first__7179_ETC__q242 = + 3'd4; + endcase + end + always@(IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17235) + begin + case (IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17235) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + CASE_IF_coreFix_aluExe_1_regToExeQ_first__7179_ETC__q243 = + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17235; + default: CASE_IF_coreFix_aluExe_1_regToExeQ_first__7179_ETC__q243 = + 4'd11; + endcase + end + always@(coreFix_aluExe_0_rsAlu$dispatchData) + begin + case (coreFix_aluExe_0_rsAlu$dispatchData[196:193]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17968 = + coreFix_aluExe_0_rsAlu$dispatchData[196:193]; + default: IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17968 = + 4'd11; + endcase + end + always@(coreFix_aluExe_0_rsAlu$dispatchData) + begin + case (coreFix_aluExe_0_rsAlu$dispatchData[192:190]) + 3'd2, 3'd3: + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17997 = + coreFix_aluExe_0_rsAlu$dispatchData[192:190]; + default: IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17997 = + 3'd4; + endcase + end + always@(IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17997) + begin + case (IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17997) + 3'd2, 3'd3: + CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__7_ETC__q244 = + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17997; + default: CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__7_ETC__q244 = + 3'd4; + endcase + end + always@(IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17968) + begin + case (IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17968) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__7_ETC__q245 = + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d17968; + default: CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__7_ETC__q245 = + 4'd11; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first) + begin + case (coreFix_aluExe_0_dispToRegQ$first[188:186]) + 3'd2, 3'd3: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18370 = + coreFix_aluExe_0_dispToRegQ$first[188:186]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18370 = + 3'd4; + endcase + end + always@(IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18370) + begin + case (IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18370) + 3'd2, 3'd3: + CASE_IF_coreFix_aluExe_0_dispToRegQ_first__819_ETC__q246 = + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18370; + default: CASE_IF_coreFix_aluExe_0_dispToRegQ_first__819_ETC__q246 = + 3'd4; + endcase + end + always@(IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18341) + begin + case (IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18341) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + CASE_IF_coreFix_aluExe_0_dispToRegQ_first__819_ETC__q247 = + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18341; + default: CASE_IF_coreFix_aluExe_0_dispToRegQ_first__819_ETC__q247 = + 4'd11; endcase end always@(coreFix_aluExe_0_regToExeQ$first) begin - case (coreFix_aluExe_0_regToExeQ$first[399:397]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222 = - coreFix_aluExe_0_regToExeQ$first[399:397]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222 = 3'd7; - endcase - end - always@(coreFix_aluExe_0_regToExeQ$first or - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222) - begin - case (coreFix_aluExe_0_regToExeQ$first[416:414]) - 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 = - coreFix_aluExe_0_regToExeQ$first[416:396]; - 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 = - { coreFix_aluExe_0_regToExeQ$first[416:414], - 9'h0AA, - coreFix_aluExe_0_regToExeQ$first[404:400], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, - coreFix_aluExe_0_regToExeQ$first[396] }; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 = - { 3'd5, 18'h2AAAA }; + case (coreFix_aluExe_0_regToExeQ$first[784:781]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19313 = + coreFix_aluExe_0_regToExeQ$first[784:781]; + default: IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19313 = + 4'd11; endcase end always@(coreFix_aluExe_0_regToExeQ$first) begin - case (coreFix_aluExe_0_regToExeQ$first[394:383]) - 12'd3860, - 12'd3859, - 12'd3858, - 12'd3857, - 12'd2818, - 12'd2816, - 12'd836, - 12'd835, - 12'd834, - 12'd833, - 12'd832, - 12'd774, - 12'd773, - 12'd772, - 12'd771, - 12'd770, - 12'd769, - 12'd768, - 12'd384, - 12'd324, - 12'd323, - 12'd322, - 12'd321, - 12'd320, - 12'd262, - 12'd261, - 12'd260, - 12'd256, - 12'd2049, - 12'd2048, - 12'd3074, - 12'd3073, - 12'd3072, - 12'd3, - 12'd2, - 12'd1: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224 = - coreFix_aluExe_0_regToExeQ$first[394:383]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224 = - 12'd2303; + case (coreFix_aluExe_0_regToExeQ$first[780:778]) + 3'd2, 3'd3: + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19342 = + coreFix_aluExe_0_regToExeQ$first[780:778]; + default: IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19342 = + 3'd4; + endcase + end + always@(IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19342) + begin + case (IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19342) + 3'd2, 3'd3: + CASE_IF_coreFix_aluExe_0_regToExeQ_first__9257_ETC__q248 = + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19342; + default: CASE_IF_coreFix_aluExe_0_regToExeQ_first__9257_ETC__q248 = + 3'd4; + endcase + end + always@(IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19313) + begin + case (IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19313) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + CASE_IF_coreFix_aluExe_0_regToExeQ_first__9257_ETC__q249 = + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19313; + default: CASE_IF_coreFix_aluExe_0_regToExeQ_first__9257_ETC__q249 = + 4'd11; endcase end always@(fetchStage$pipelines_0_first) begin - case (fetchStage$pipelines_0_first[172:161]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805 = - fetchStage$pipelines_0_first[172:161]; - default: IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805 = - 12'd2303; + case (fetchStage$pipelines_0_first[231:229]) + 3'd2, 3'd3: + IF_fetchStage_pipelines_0_first__0045_BITS_231_ETC___d20226 = + fetchStage$pipelines_0_first[231:229]; + default: IF_fetchStage_pipelines_0_first__0045_BITS_231_ETC___d20226 = + 3'd4; endcase end always@(fetchStage$pipelines_0_first) begin - case (fetchStage$pipelines_0_first[67:64]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 = - fetchStage$pipelines_0_first[67:64]; - 4'd11: - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 = 4'd10; - 4'd12: - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 = 4'd11; - 4'd13: - IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 = 4'd12; - default: IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949 = - 4'd13; + case (fetchStage$pipelines_0_first[235:232]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20197 = + fetchStage$pipelines_0_first[235:232]; + default: IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20197 = + 4'd11; + endcase + end + always@(IF_fetchStage_pipelines_0_first__0045_BITS_231_ETC___d20226) + begin + case (IF_fetchStage_pipelines_0_first__0045_BITS_231_ETC___d20226) + 3'd2, 3'd3: + CASE_IF_fetchStage_pipelines_0_first__0045_BIT_ETC__q250 = + IF_fetchStage_pipelines_0_first__0045_BITS_231_ETC___d20226; + default: CASE_IF_fetchStage_pipelines_0_first__0045_BIT_ETC__q250 = + 3'd4; + endcase + end + always@(IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20197) + begin + case (IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20197) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + CASE_IF_fetchStage_pipelines_0_first__0045_BIT_ETC__q251 = + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20197; + default: CASE_IF_fetchStage_pipelines_0_first__0045_BIT_ETC__q251 = + 4'd11; endcase end always@(fetchStage$pipelines_0_first) begin - case (fetchStage$pipelines_0_first[177:175]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225 = - fetchStage$pipelines_0_first[177:175]; - default: CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225 = 3'd7; - endcase - end - always@(fetchStage$pipelines_0_first or - CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731 = - fetchStage$pipelines_0_first[194:174]; - 3'd4: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731 = - { fetchStage$pipelines_0_first[194:192], - 9'h0AA, - fetchStage$pipelines_0_first[182:178], - CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, - fetchStage$pipelines_0_first[174] }; - default: IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731 = - 21'd1485482; - endcase - end - always@(checkForException___d12839) - begin - case (checkForException___d12839[3:0]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - CASE_checkForException_2839_BITS_3_TO_0_0_chec_ETC__q226 = - checkForException___d12839[3:0]; - 4'd11: CASE_checkForException_2839_BITS_3_TO_0_0_chec_ETC__q226 = 4'd10; - 4'd12: CASE_checkForException_2839_BITS_3_TO_0_0_chec_ETC__q226 = 4'd11; - 4'd13: CASE_checkForException_2839_BITS_3_TO_0_0_chec_ETC__q226 = 4'd12; - default: CASE_checkForException_2839_BITS_3_TO_0_0_chec_ETC__q226 = - 4'd13; - endcase - end - always@(IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3__ETC___d13055) - begin - case (IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3__ETC___d13055) - 4'd0, 4'd1: - CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633__ETC__q227 = - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3__ETC___d13055; - 4'd2: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633__ETC__q227 = 4'd3; - 4'd3: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633__ETC__q227 = 4'd4; - 4'd4: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633__ETC__q227 = 4'd5; - 4'd5: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633__ETC__q227 = 4'd7; - 4'd6: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633__ETC__q227 = 4'd8; - 4'd7: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633__ETC__q227 = 4'd9; - 4'd8: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633__ETC__q227 = 4'd11; - default: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633__ETC__q227 = + case (fetchStage$pipelines_0_first[68:64]) + 5'd0: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd0; + 5'd1: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd1; + 5'd2: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd2; + 5'd3: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd3; + 5'd4: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd4; + 5'd5: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd5; + 5'd6: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd6; + 5'd7: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd7; + 5'd8: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd8; + 5'd9: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd9; + 5'd11: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd10; + 5'd12: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd11; + 5'd13: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd12; + 5'd15: + IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd13; + default: IF_fetchStage_pipelines_0_first__0045_BIT_69_0_ETC___d20590 = 4'd14; endcase end - always@(k__h661043 or - coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) + always@(fetchStage$pipelines_0_first) begin - case (k__h661043) - 1'd0: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 = - coreFix_aluExe_0_rsAlu$canEnq; - 1'd1: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 = - coreFix_aluExe_1_rsAlu$canEnq; + case (fetchStage$pipelines_0_first[166:162]) + 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: + CASE_fetchStagepipelines_0_first_BITS_166_TO__ETC__q252 = + fetchStage$pipelines_0_first[166:162]; + default: CASE_fetchStagepipelines_0_first_BITS_166_TO__ETC__q252 = + 5'd10; endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) + always@(fetchStage$pipelines_0_first) begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 = - coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 = - coreFix_memExe_lsq$enqStTag[6]; - endcase - end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 or - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13244 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227; - 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13244 = - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13244 = - fetchStage$pipelines_0_first[194:192] != 3'd2 || - coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240; - endcase - end - always@(k__h661043 or - coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) - begin - case (k__h661043) - 1'd0: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 = - !coreFix_aluExe_0_rsAlu$canEnq; - 1'd1: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 = - !coreFix_aluExe_1_rsAlu$canEnq; - endcase - end - always@(fetchStage$pipelines_0_first or - regRenamingTable$rename_0_canRename or - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207 or - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13263 or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 or - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 = - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13263; - 3'd2: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 = - coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 && - regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207; - 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 = - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207; - default: IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 = - regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207; - endcase - end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) - begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296 = - !coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296 = - !coreFix_memExe_lsq$enqStTag[6]; - endcase - end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 or - specTagManager$canClaim or - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13301 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 || - fetchStage$pipelines_0_first[194:192] == 3'd1 && - !specTagManager$canClaim; - 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13301 = - !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13301 = - fetchStage$pipelines_0_first[194:192] == 3'd2 && - (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296); - endcase - end - always@(fetchStage$pipelines_1_first) - begin - case (fetchStage$pipelines_1_first[172:161]) + case (fetchStage$pipelines_0_first[179:168]) 12'd1, 12'd2, 12'd3, @@ -34454,10 +43017,20 @@ module mkCore(CLK, 12'd834, 12'd835, 12'd836, + 12'd1952, + 12'd1953, + 12'd1954, + 12'd1955, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, 12'd2048, 12'd2049, + 12'd2496, 12'd2816, 12'd2818, + 12'd3008, 12'd3072, 12'd3073, 12'd3074, @@ -34465,577 +43038,856 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 = - fetchStage$pipelines_1_first[172:161]; - default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 = + CASE_fetchStagepipelines_0_first_BITS_179_TO__ETC__q253 = + fetchStage$pipelines_0_first[179:168]; + default: CASE_fetchStagepipelines_0_first_BITS_179_TO__ETC__q253 = 12'd2303; endcase end + always@(fetchStage$pipelines_0_first) + begin + case (fetchStage$pipelines_0_first[241:239]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_fetchStagepipelines_0_first_BITS_241_TO__ETC__q254 = + fetchStage$pipelines_0_first[241:239]; + default: CASE_fetchStagepipelines_0_first_BITS_241_TO__ETC__q254 = 3'd7; + endcase + end + always@(fetchStage$pipelines_0_first or + CASE_fetchStagepipelines_0_first_BITS_241_TO__ETC__q254) + begin + case (fetchStage$pipelines_0_first[267:265]) + 3'd0, 3'd1, 3'd2, 3'd3: + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20171 = + fetchStage$pipelines_0_first[267:238]; + 3'd4: + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20171 = + { fetchStage$pipelines_0_first[267:265], + 18'h2AAAA, + fetchStage$pipelines_0_first[246:242], + CASE_fetchStagepipelines_0_first_BITS_241_TO__ETC__q254, + fetchStage$pipelines_0_first[238] }; + default: IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20171 = + 30'd715827882; + endcase + end + always@(fetchStage$pipelines_0_first or + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20270) + begin + case (fetchStage$pipelines_0_first[237:236]) + 2'd0: + CASE_fetchStagepipelines_0_first_BITS_237_TO__ETC__q255 = + fetchStage$pipelines_0_first[237:227]; + 2'd1: + CASE_fetchStagepipelines_0_first_BITS_237_TO__ETC__q255 = + { fetchStage$pipelines_0_first[237:236], + IF_fetchStage_pipelines_0_first__0045_BITS_235_ETC___d20270 }; + default: CASE_fetchStagepipelines_0_first_BITS_237_TO__ETC__q255 = + 11'd1194; + endcase + end + always@(checkForException___d20432) + begin + case (checkForException___d20432[3:0]) + 4'd0, 4'd1: + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 = + checkForException___d20432[3:0]; + 4'd3: + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 = 4'd2; + 4'd4: + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 = 4'd3; + 4'd5: + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 = 4'd4; + 4'd7: + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 = 4'd5; + 4'd8: + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 = 4'd6; + 4'd9: + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 = 4'd7; + 4'd11: + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 = 4'd8; + 4'd14: + IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 = 4'd9; + default: IF_checkForException_0432_BITS_3_TO_0_0685_EQ__ETC___d20705 = + 4'd10; + endcase + end + always@(checkForException___d20432) + begin + case (checkForException___d20432[4:0]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd10, + 5'd11, + 5'd16, + 5'd17, + 5'd18, + 5'd19, + 5'd20, + 5'd21, + 5'd22, + 5'd23, + 5'd24, + 5'd25, + 5'd26: + CASE_checkForException_0432_BITS_4_TO_0_0_chec_ETC__q256 = + checkForException___d20432[4:0]; + default: CASE_checkForException_0432_BITS_4_TO_0_0_chec_ETC__q256 = + 5'd27; + endcase + end + always@(checkForException___d20432) + begin + case (checkForException___d20432[4:0]) + 5'd0: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd0; + 5'd1: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd1; + 5'd2: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd2; + 5'd3: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd3; + 5'd4: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd4; + 5'd5: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd5; + 5'd6: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd6; + 5'd7: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd7; + 5'd8: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd8; + 5'd9: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd9; + 5'd11: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd10; + 5'd12: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd11; + 5'd13: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd12; + 5'd15: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = 4'd13; + default: CASE_checkForException_0432_BITS_4_TO_0_0_0_1__ETC__q257 = + 4'd14; + endcase + end + always@(k__h942381 or + coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) + begin + case (k__h942381) + 1'd0: + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 = + coreFix_aluExe_0_rsAlu$canEnq; + 1'd1: + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0969_co_ETC___d20979 = + coreFix_aluExe_1_rsAlu$canEnq; + endcase + end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) + begin + case (fetchStage$pipelines_0_first[264:262]) + 3'd0, 3'd2: + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 = + coreFix_memExe_lsq$enqLdTag[6]; + default: IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 = + coreFix_memExe_lsq$enqStTag[6]; + endcase + end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_rsMem$canEnq or + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 or + coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) + begin + case (fetchStage$pipelines_0_first[267:265]) + 3'd3, 3'd4: + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20995 = + coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; + default: IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d20995 = + fetchStage$pipelines_0_first[267:265] != 3'd2 || + coreFix_memExe_rsMem$canEnq && + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992; + endcase + end + always@(k__h942381 or + coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) + begin + case (k__h942381) + 1'd0: + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__096_ETC___d21013 = + !coreFix_aluExe_0_rsAlu$canEnq; + 1'd1: + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__096_ETC___d21013 = + !coreFix_aluExe_1_rsAlu$canEnq; + endcase + end + always@(fetchStage$pipelines_0_first or + regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958 or + coreFix_memExe_rsMem$canEnq or + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 or + coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) + begin + case (fetchStage$pipelines_0_first[267:265]) + 3'd2: + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21019 = + coreFix_memExe_rsMem$canEnq && + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958; + 3'd3, 3'd4: + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21019 = + coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958; + default: IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21019 = + regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958; + endcase + end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) + begin + case (fetchStage$pipelines_0_first[264:262]) + 3'd0, 3'd2: + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051 = + !coreFix_memExe_lsq$enqLdTag[6]; + default: IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051 = + !coreFix_memExe_lsq$enqStTag[6]; + endcase + end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_rsMem$canEnq or + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051 or + coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) + begin + case (fetchStage$pipelines_0_first[267:265]) + 3'd3, 3'd4: + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21055 = + !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; + default: IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21055 = + fetchStage$pipelines_0_first[267:265] == 3'd2 && + (!coreFix_memExe_rsMem$canEnq || + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051); + endcase + end always@(fetchStage$pipelines_1_first) begin - case (fetchStage$pipelines_1_first[177:175]) + case (fetchStage$pipelines_1_first[235:232]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21145 = + fetchStage$pipelines_1_first[235:232]; + default: IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21145 = + 4'd11; + endcase + end + always@(fetchStage$pipelines_1_first) + begin + case (fetchStage$pipelines_1_first[231:229]) + 3'd2, 3'd3: + IF_fetchStage_pipelines_1_first__0054_BITS_231_ETC___d21174 = + fetchStage$pipelines_1_first[231:229]; + default: IF_fetchStage_pipelines_1_first__0054_BITS_231_ETC___d21174 = + 3'd4; + endcase + end + always@(fetchStage$pipelines_1_first) + begin + case (fetchStage$pipelines_1_first[179:168]) + 12'd1, + 12'd2, + 12'd3, + 12'd256, + 12'd260, + 12'd261, + 12'd262, + 12'd320, + 12'd321, + 12'd322, + 12'd323, + 12'd324, + 12'd384, + 12'd768, + 12'd769, + 12'd770, + 12'd771, + 12'd772, + 12'd773, + 12'd774, + 12'd832, + 12'd833, + 12'd834, + 12'd835, + 12'd836, + 12'd1952, + 12'd1953, + 12'd1954, + 12'd1955, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, + 12'd2048, + 12'd2049, + 12'd2496, + 12'd2816, + 12'd2818, + 12'd3008, + 12'd3072, + 12'd3073, + 12'd3074, + 12'd3857, + 12'd3858, + 12'd3859, + 12'd3860: + CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q258 = + fetchStage$pipelines_1_first[179:168]; + default: CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q258 = + 12'd2303; + endcase + end + always@(IF_fetchStage_pipelines_1_first__0054_BITS_231_ETC___d21174) + begin + case (IF_fetchStage_pipelines_1_first__0054_BITS_231_ETC___d21174) + 3'd2, 3'd3: + CASE_IF_fetchStage_pipelines_1_first__0054_BIT_ETC__q259 = + IF_fetchStage_pipelines_1_first__0054_BITS_231_ETC___d21174; + default: CASE_IF_fetchStage_pipelines_1_first__0054_BIT_ETC__q259 = + 3'd4; + endcase + end + always@(IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21145) + begin + case (IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21145) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + CASE_IF_fetchStage_pipelines_1_first__0054_BIT_ETC__q260 = + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21145; + default: CASE_IF_fetchStage_pipelines_1_first__0054_BIT_ETC__q260 = + 4'd11; + endcase + end + always@(fetchStage$pipelines_1_first) + begin + case (fetchStage$pipelines_1_first[241:239]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229 = - fetchStage$pipelines_1_first[177:175]; - default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229 = 3'd7; + CASE_fetchStagepipelines_1_first_BITS_241_TO__ETC__q261 = + fetchStage$pipelines_1_first[241:239]; + default: CASE_fetchStagepipelines_1_first_BITS_241_TO__ETC__q261 = 3'd7; endcase end always@(fetchStage$pipelines_1_first or - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229) + CASE_fetchStagepipelines_1_first_BITS_241_TO__ETC__q261) begin - case (fetchStage$pipelines_1_first[194:192]) + case (fetchStage$pipelines_1_first[267:265]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361 = - fetchStage$pipelines_1_first[194:174]; + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21119 = + fetchStage$pipelines_1_first[267:238]; 3'd4: - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361 = - { fetchStage$pipelines_1_first[194:192], - 9'h0AA, - fetchStage$pipelines_1_first[182:178], - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, - fetchStage$pipelines_1_first[174] }; - default: IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361 = - 21'd1485482; + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21119 = + { fetchStage$pipelines_1_first[267:265], + 18'h2AAAA, + fetchStage$pipelines_1_first[246:242], + CASE_fetchStagepipelines_1_first_BITS_241_TO__ETC__q261, + fetchStage$pipelines_1_first[238] }; + default: IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21119 = + 30'd715827882; endcase end - always@(idx__h675477 or + always@(fetchStage$pipelines_1_first) + begin + case (fetchStage$pipelines_1_first[166:162]) + 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: + CASE_fetchStagepipelines_1_first_BITS_166_TO__ETC__q262 = + fetchStage$pipelines_1_first[166:162]; + default: CASE_fetchStagepipelines_1_first_BITS_166_TO__ETC__q262 = + 5'd10; + endcase + end + always@(fetchStage$pipelines_1_first or + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21218) + begin + case (fetchStage$pipelines_1_first[237:236]) + 2'd0: + CASE_fetchStagepipelines_1_first_BITS_237_TO__ETC__q263 = + fetchStage$pipelines_1_first[237:227]; + 2'd1: + CASE_fetchStagepipelines_1_first_BITS_237_TO__ETC__q263 = + { fetchStage$pipelines_1_first[237:236], + IF_fetchStage_pipelines_1_first__0054_BITS_235_ETC___d21218 }; + default: CASE_fetchStagepipelines_1_first_BITS_237_TO__ETC__q263 = + 11'd1194; + endcase + end + always@(idx__h966094 or fetchStage$pipelines_0_canDeq or - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13503 or + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21419 or coreFix_aluExe_0_rsAlu$canEnq or - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13509 or + fetchStage$pipelines_0_first or + specTagManager$canClaim or + regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958 or + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21424 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h675477) + case (idx__h966094) 1'd0: - SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13528 = + SEL_ARR_fetchStage_pipelines_0_canDeq__0043_AN_ETC___d21447 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13503 || + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21419 || !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13528 = + SEL_ARR_fetchStage_pipelines_0_canDeq__0043_AN_ETC___d21447 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13509 || + (fetchStage$pipelines_0_first[267:265] != 3'd1 || + specTagManager$canClaim) && + regRenamingTable_rename_0_canRename__0929_AND__ETC___d20958 && + fetchStage_pipelines_0_first__0045_BITS_267_TO_ETC___d21424 || !coreFix_aluExe_1_rsAlu$canEnq; endcase end always@(fetchStage$pipelines_1_first or coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) begin - case (fetchStage$pipelines_1_first[191:189]) + case (fetchStage$pipelines_1_first[264:262]) 3'd0, 3'd2: - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 = + CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q264 = !coreFix_memExe_lsq$enqLdTag[6]; - default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 = + default: CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q264 = !coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 or - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13595 or - NOT_coreFix_memExe_rsMem_canEnq__3231_3293_OR__ETC___d13598 or - NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13597) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13601 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 || - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13595; - 3'd2: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13601 = - NOT_coreFix_memExe_rsMem_canEnq__3231_3293_OR__ETC___d13598; - 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13601 = - NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13597; - default: IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13601 = - fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[2] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[3] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[4] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[5] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[6] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[7] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[8] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[9] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[10] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[11] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[12] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[13] || - IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[14]; - endcase - end - always@(fetchStage$pipelines_0_first or + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21517 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13622 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227; - default: IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13622 = - fetchStage$pipelines_0_first[194:192] != 3'd2 || - coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240; - endcase - end - always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 or + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13639 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227; + case (fetchStage$pipelines_0_first[267:265]) + 3'd2: + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21526 = + !coreFix_memExe_rsMem$canEnq || + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051 || + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21517; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13639 = + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21526 = + !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21517; + default: IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21526 = + renameStage_rg_m_halt_req_0072_BIT_4_0073_OR_f_ETC___d21517; + endcase + end + always@(fetchStage$pipelines_0_first or + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992 or + coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) + begin + case (fetchStage$pipelines_0_first[267:265]) + 3'd3, 3'd4: + CASE_fetchStagepipelines_0_first_BITS_267_TO__ETC__q265 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13639 = - fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240; + default: CASE_fetchStagepipelines_0_first_BITS_267_TO__ETC__q265 = + fetchStage$pipelines_0_first[267:265] != 3'd2 || + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d20992; endcase end always@(fetchStage$pipelines_1_first or coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) begin - case (fetchStage$pipelines_1_first[191:189]) + case (fetchStage$pipelines_1_first[264:262]) 3'd0, 3'd2: - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 = + CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q266 = coreFix_memExe_lsq$enqLdTag[6]; - default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 = + default: CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q266 = coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_1_first or - regRenamingTable$rename_1_canRename or - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13494 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13528 or - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13607 or - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13636 or - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13645 or - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13619 or - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13628) + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21409 or + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21565 or + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21576 or + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21558) begin - case (fetchStage$pipelines_1_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13650 = - !SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13528 && - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13607; + case (fetchStage$pipelines_1_first[267:265]) 3'd2: - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13650 = - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13636 && - regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13645; + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21579 = + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21565 && + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21576; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13650 = - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13619 && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13628; - default: IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13650 = - regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13494; + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21579 = + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21558; + default: IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21579 = + regRenamingTable_rename_1_canRename__1062_AND__ETC___d21409; endcase end - always@(k__h661043 or + always@(k__h942381 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h661043) + case (k__h942381) 1'd0: - CASE_k61043_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k42381_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k61043_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k42381_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) begin - case (fetchStage$pipelines_0_first[191:189]) + case (fetchStage$pipelines_0_first[264:262]) 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = + CASE_fetchStagepipelines_0_first_BITS_264_TO__ETC__q268 = coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = + default: CASE_fetchStagepipelines_0_first_BITS_264_TO__ETC__q268 = coreFix_memExe_lsq$RDY_enqSt; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 or - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13694 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261; - 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13694 = - !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13694 = - fetchStage$pipelines_0_first[194:192] == 3'd2 && - (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296); - endcase - end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296 or - regRenamingTable_RDY_rename_0_getRename__3087__ETC___d13688 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 or - regRenamingTable$RDY_rename_0_getRename or - _0_OR_NOT_fetchStage_pipelines_0_first__2605_BI_ETC___d13675 or + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051 or + regRenamingTable_RDY_rename_0_getRename__0805__ETC___d21619 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq) + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq or + regRenamingTable$RDY_rename_0_getRename) begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13692 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 || - regRenamingTable$RDY_rename_0_getRename && - _0_OR_NOT_fetchStage_pipelines_0_first__2605_BI_ETC___d13675; + case (fetchStage$pipelines_0_first[267:265]) 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13692 = + IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21622 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_0_getRename; - default: IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13692 = - fetchStage$pipelines_0_first[194:192] != 3'd2 || + default: IF_fetchStage_pipelines_0_first__0045_BITS_267_ETC___d21622 = + fetchStage$pipelines_0_first[267:265] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296 || - regRenamingTable_RDY_rename_0_getRename__3087__ETC___d13688; + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051 || + regRenamingTable_RDY_rename_0_getRename__0805__ETC___d21619; endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 or - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13708 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227; - 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13708 = - !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13708 = - fetchStage$pipelines_0_first[194:192] == 3'd2 && - (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296); - endcase - end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 or - specTagManager$canClaim or - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13715 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 && - (fetchStage$pipelines_0_first[194:192] != 3'd1 || - specTagManager$canClaim); - 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13715 = - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13715 = - fetchStage$pipelines_0_first[194:192] != 3'd2 || - coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240; - endcase - end - always@(idx__h675477 or + always@(idx__h966094 or fetchStage$pipelines_0_canDeq or - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13731 or + fetchStage$pipelines_0_first or + specTagManager$canClaim or + NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21434 or + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21668 or coreFix_aluExe_0_rsAlu$canEnq or - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13738 or + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21675 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h675477) + case (idx__h966094) 1'd0: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__260_ETC___d13742 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__004_ETC___d21680 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13731) && + fetchStage$pipelines_0_first[267:265] == 3'd1 && + !specTagManager$canClaim || + NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21434 || + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21668) && coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__260_ETC___d13742 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__004_ETC___d21680 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13738) && + fetchStage$pipelines_0_first[267:265] == 3'd1 && + !specTagManager$canClaim || + NOT_regRenamingTable_rename_0_canRename__0929__ETC___d21434 || + NOT_fetchStage_pipelines_0_first__0045_BITS_26_ETC___d21675) && coreFix_aluExe_1_rsAlu$canEnq; endcase end - always@(fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13758 or + always@(fetchStage_pipelines_0_canDeq__0043_AND_NOT_fe_ETC___d21696 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13758) + case (fetchStage_pipelines_0_canDeq__0043_AND_NOT_fe_ETC___d21696) 1'd0: - CASE_fetchStage_pipelines_0_canDeq__2603_AND_N_ETC__q234 = + CASE_fetchStage_pipelines_0_canDeq__0043_AND_N_ETC__q269 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_fetchStage_pipelines_0_canDeq__2603_AND_N_ETC__q234 = + CASE_fetchStage_pipelines_0_canDeq__0043_AND_N_ETC__q269 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end always@(fetchStage$pipelines_1_first or coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) begin - case (fetchStage$pipelines_1_first[191:189]) + case (fetchStage$pipelines_1_first[264:262]) 3'd0, 3'd2: - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 = + CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q270 = coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 = + default: CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q270 = coreFix_memExe_lsq$RDY_enqSt; endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 or + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13795 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227; + case (fetchStage$pipelines_0_first[267:265]) 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13795 = + CASE_fetchStagepipelines_0_first_BITS_267_TO__ETC__q271 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13795 = - fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296; - endcase - end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13784 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227; - default: IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13784 = - fetchStage$pipelines_0_first[194:192] == 3'd2 && - (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13296); + default: CASE_fetchStagepipelines_0_first_BITS_267_TO__ETC__q271 = + fetchStage$pipelines_0_first[267:265] == 3'd2 && + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21051; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13803 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13528 or - fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13792) + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21743 or + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21731) begin - case (fetchStage$pipelines_1_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13806 = - SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13528; + case (fetchStage$pipelines_1_first[267:265]) 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13806 = - fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13792; - default: IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13806 = - fetchStage$pipelines_1_first[194:192] == 3'd2 && - fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13803; + CASE_fetchStagepipelines_1_first_BITS_267_TO__ETC__q272 = + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21731; + default: CASE_fetchStagepipelines_1_first_BITS_267_TO__ETC__q272 = + fetchStage$pipelines_1_first[267:265] == 3'd2 && + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21743; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13771 or + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21709 or regRenamingTable$RDY_rename_1_getRename or - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13776 or - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__260_ETC___d13742 or - regRenamingTable_RDY_rename_1_getRename__3744__ETC___d13762 or - fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13764 or + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21714 or + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21702 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__36_ETC___d13767) + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__16_ETC___d21705) begin - case (fetchStage$pipelines_1_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13781 = - !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__260_ETC___d13742 || - regRenamingTable_RDY_rename_1_getRename__3744__ETC___d13762; + case (fetchStage$pipelines_1_first[267:265]) 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13781 = - fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13764 || + IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21718 = + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21702 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__36_ETC___d13767; - default: IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13781 = - fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2603_AND_regRen_ETC___d13771 || + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__16_ETC___d21705; + default: IF_fetchStage_pipelines_1_first__0054_BITS_267_ETC___d21718 = + fetchStage$pipelines_1_first[267:265] != 3'd2 || + fetchStage_pipelines_0_canDeq__0043_AND_regRen_ETC___d21709 || regRenamingTable$RDY_rename_1_getRename && - NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13776; + NOT_fetchStage_pipelines_0_canDeq__0043_0044_O_ETC___d21714; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) begin - case (fetchStage$pipelines_0_first[191:189]) + case (fetchStage$pipelines_0_first[264:262]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13862 = + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21804 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13862 = + default: IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21804 = !coreFix_memExe_lsq$enqStTag[5]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) begin - case (fetchStage$pipelines_0_first[191:189]) + case (fetchStage$pipelines_0_first[264:262]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13868 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13868 = - coreFix_memExe_lsq$enqStTag[3:0]; - endcase - end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) - begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13859 = + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21801 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13859 = + default: IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21801 = coreFix_memExe_lsq$enqStTag[5]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) begin - case (fetchStage$pipelines_0_first[191:189]) + case (fetchStage$pipelines_0_first[264:262]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13865 = + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21810 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21810 = + coreFix_memExe_lsq$enqStTag[3:0]; + endcase + end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) + begin + case (fetchStage$pipelines_0_first[264:262]) + 3'd0, 3'd2: + IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21807 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13865 = + default: IF_fetchStage_pipelines_0_first__0045_BITS_264_ETC___d21807 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end always@(fetchStage$pipelines_1_first or coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) begin - case (fetchStage$pipelines_1_first[191:189]) + case (fetchStage$pipelines_1_first[264:262]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13993 = + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21954 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21954 = + coreFix_memExe_lsq$enqStTag[3:0]; + endcase + end + always@(fetchStage$pipelines_1_first or + coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) + begin + case (fetchStage$pipelines_1_first[264:262]) + 3'd0, 3'd2: + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21951 = + coreFix_memExe_lsq$enqLdTag[5]; + default: IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21951 = + coreFix_memExe_lsq$enqStTag[5]; + endcase + end + always@(fetchStage$pipelines_1_first or + coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) + begin + case (fetchStage$pipelines_1_first[264:262]) + 3'd0, 3'd2: + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21952 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13993 = + default: IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21952 = !coreFix_memExe_lsq$enqStTag[5]; endcase end always@(fetchStage$pipelines_1_first or coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) begin - case (fetchStage$pipelines_1_first[191:189]) + case (fetchStage$pipelines_1_first[264:262]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13995 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13995 = - coreFix_memExe_lsq$enqStTag[3:0]; - endcase - end - always@(fetchStage$pipelines_1_first or - coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) - begin - case (fetchStage$pipelines_1_first[191:189]) - 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13992 = - coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13992 = - coreFix_memExe_lsq$enqStTag[5]; - endcase - end - always@(fetchStage$pipelines_1_first or - coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) - begin - case (fetchStage$pipelines_1_first[191:189]) - 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13994 = + IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21953 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13994 = + default: IF_fetchStage_pipelines_1_first__0054_BITS_264_ETC___d21953 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end + always@(csrf_prv_reg or csrf_rg_dcsr) + begin + case (csrf_prv_reg) + 2'd1: + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q273 = + !csrf_rg_dcsr[13]; + 2'd3: + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q273 = + !csrf_rg_dcsr[15]; + default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q273 = + !csrf_rg_dcsr[12]; + endcase + end + always@(csrf_prv_reg or csrf_rg_dcsr) + begin + case (csrf_prv_reg) + 2'd1: + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q274 = + csrf_rg_dcsr[13]; + 2'd3: + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q274 = + csrf_rg_dcsr[15]; + default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q274 = + csrf_rg_dcsr[12]; + endcase + end always@(rob$deqPort_0_deq_data) begin - case (rob$deqPort_0_deq_data[180:169]) + case (rob$deqPort_0_deq_data[287:276]) 12'd1: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd0; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd1; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd2; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd8; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd9; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd10; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd11; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd12; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd13; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd14; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd15; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd16; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd17; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd18; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd19; 12'd769: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd19; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd20; 12'd770: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd20; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd21; 12'd771: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd21; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd22; 12'd772: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd22; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd23; 12'd773: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd23; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd24; 12'd774: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd24; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd25; 12'd832: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd25; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd26; 12'd833: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd26; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd27; 12'd834: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd27; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd28; 12'd835: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd28; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd29; 12'd836: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd29; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd30; + 12'd1952: + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd38; + 12'd1953: + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd39; + 12'd1954: + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd40; + 12'd1955: + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd41; + 12'd1968: + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd42; + 12'd1969: + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd43; + 12'd1970: + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd44; + 12'd1971: + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd45; 12'd2048: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd6; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd7; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd7; + 12'd2496: + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd18; 12'd2816: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd30; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd31; 12'd2818: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd31; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd32; + 12'd3008: + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd37; 12'd3072: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd3; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd4; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd5; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd32; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd33; 12'd3858: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd33; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd34; 12'd3859: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd34; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd35; 12'd3860: - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = 6'd35; - default: IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 = - 6'd36; + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = 6'd36; + default: IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 = + 6'd46; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[293:289]) + 5'd0: + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 = 4'd0; + 5'd1: + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 = 4'd1; + 5'd12: + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 = 4'd2; + 5'd13: + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 = 4'd3; + 5'd14: + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 = 4'd4; + 5'd15: + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 = 4'd5; + 5'd28: + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 = 4'd6; + 5'd29: + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 = 4'd7; + 5'd30: + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 = 4'd8; + 5'd31: + IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 = 4'd9; + default: IF_rob_deqPort_0_deq_data__2022_BIT_294_3017_T_ETC___d23039 = + 4'd10; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or @@ -35044,10 +43896,726 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q275 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[515]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q275 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[515]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q276 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q276 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q277 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[513]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q277 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[513]; + endcase + end + always@(coreFix_memExe_memRespLdQ_deqP or + coreFix_memExe_memRespLdQ_data_0 or + coreFix_memExe_memRespLdQ_data_1) + begin + case (coreFix_memExe_memRespLdQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = + coreFix_memExe_memRespLdQ_data_0[127:64]; + 1'd1: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = + coreFix_memExe_memRespLdQ_data_1[127:64]; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = + coreFix_memExe_forwardQ_data_0[63:0]; + 1'd1: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = + coreFix_memExe_forwardQ_data_1[63:0]; + endcase + end + always@(coreFix_memExe_memRespLdQ_deqP or + coreFix_memExe_memRespLdQ_data_0 or + coreFix_memExe_memRespLdQ_data_1) + begin + case (coreFix_memExe_memRespLdQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = + coreFix_memExe_memRespLdQ_data_0[63:0]; + 1'd1: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = + coreFix_memExe_memRespLdQ_data_1[63:0]; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = + coreFix_memExe_forwardQ_data_0[127:64]; + 1'd1: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = + coreFix_memExe_forwardQ_data_1[127:64]; + endcase + end + always@(commitStage_commitTrap or + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22438) + begin + case (commitStage_commitTrap[36:32]) + 5'd0, 5'd3: + trap_val__h993994 = + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22438; + 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: + trap_val__h993994 = commitStage_commitTrap[108:45]; + 5'd2: trap_val__h993994 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h993994 = 64'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd4; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd3; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd2; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd1; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = + 3'd0; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or + coreFix_memExe_stb$deq or + IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d5154) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153]) + 3'd0, 3'd2, 3'd4: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5470 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:0]; + 3'd1: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5470 = + { (coreFix_memExe_stb$deq[579:564] == 16'd0) ? + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] : + coreFix_memExe_stb$deq[579:564] == 16'd65535 && + coreFix_memExe_stb$deq[515], + (coreFix_memExe_stb$deq[563:548] == 16'd0) ? + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514] : + coreFix_memExe_stb$deq[563:548] == 16'd65535 && + coreFix_memExe_stb$deq[514], + (coreFix_memExe_stb$deq[547:532] == 16'd0) ? + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[513] : + coreFix_memExe_stb$deq[547:532] == 16'd65535 && + coreFix_memExe_stb$deq[513], + (coreFix_memExe_stb$deq[531:516] == 16'd0) ? + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[512] : + coreFix_memExe_stb$deq[531:516] == 16'd65535 && + coreFix_memExe_stb$deq[512], + coreFix_memExe_stb$deq[579] ? + coreFix_memExe_stb$deq[511:504] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:504], + coreFix_memExe_stb$deq[578] ? + coreFix_memExe_stb$deq[503:496] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[503:496], + coreFix_memExe_stb$deq[577] ? + coreFix_memExe_stb$deq[495:488] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[495:488], + coreFix_memExe_stb$deq[576] ? + coreFix_memExe_stb$deq[487:480] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[487:480], + coreFix_memExe_stb$deq[575] ? + coreFix_memExe_stb$deq[479:472] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[479:472], + coreFix_memExe_stb$deq[574] ? + coreFix_memExe_stb$deq[471:464] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[471:464], + coreFix_memExe_stb$deq[573] ? + coreFix_memExe_stb$deq[463:456] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[463:456], + coreFix_memExe_stb$deq[572] ? + coreFix_memExe_stb$deq[455:448] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[455:448], + coreFix_memExe_stb$deq[571] ? + coreFix_memExe_stb$deq[447:440] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:440], + coreFix_memExe_stb$deq[570] ? + coreFix_memExe_stb$deq[439:432] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[439:432], + coreFix_memExe_stb$deq[569] ? + coreFix_memExe_stb$deq[431:424] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[431:424], + coreFix_memExe_stb$deq[568] ? + coreFix_memExe_stb$deq[423:416] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[423:416], + coreFix_memExe_stb$deq[567] ? + coreFix_memExe_stb$deq[415:408] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[415:408], + coreFix_memExe_stb$deq[566] ? + coreFix_memExe_stb$deq[407:400] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[407:400], + coreFix_memExe_stb$deq[565] ? + coreFix_memExe_stb$deq[399:392] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[399:392], + coreFix_memExe_stb$deq[564] ? + coreFix_memExe_stb$deq[391:384] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[391:384], + coreFix_memExe_stb$deq[563] ? + coreFix_memExe_stb$deq[383:376] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:376], + coreFix_memExe_stb$deq[562] ? + coreFix_memExe_stb$deq[375:368] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[375:368], + coreFix_memExe_stb$deq[561] ? + coreFix_memExe_stb$deq[367:360] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[367:360], + coreFix_memExe_stb$deq[560] ? + coreFix_memExe_stb$deq[359:352] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[359:352], + coreFix_memExe_stb$deq[559] ? + coreFix_memExe_stb$deq[351:344] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[351:344], + coreFix_memExe_stb$deq[558] ? + coreFix_memExe_stb$deq[343:336] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[343:336], + coreFix_memExe_stb$deq[557] ? + coreFix_memExe_stb$deq[335:328] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[335:328], + coreFix_memExe_stb$deq[556] ? + coreFix_memExe_stb$deq[327:320] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[327:320], + coreFix_memExe_stb$deq[555] ? + coreFix_memExe_stb$deq[319:312] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:312], + coreFix_memExe_stb$deq[554] ? + coreFix_memExe_stb$deq[311:304] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[311:304], + coreFix_memExe_stb$deq[553] ? + coreFix_memExe_stb$deq[303:296] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[303:296], + coreFix_memExe_stb$deq[552] ? + coreFix_memExe_stb$deq[295:288] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[295:288], + coreFix_memExe_stb$deq[551] ? + coreFix_memExe_stb$deq[287:280] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[287:280], + coreFix_memExe_stb$deq[550] ? + coreFix_memExe_stb$deq[279:272] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[279:272], + coreFix_memExe_stb$deq[549] ? + coreFix_memExe_stb$deq[271:264] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[271:264], + coreFix_memExe_stb$deq[548] ? + coreFix_memExe_stb$deq[263:256] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[263:256], + coreFix_memExe_stb$deq[547] ? + coreFix_memExe_stb$deq[255:248] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:248], + coreFix_memExe_stb$deq[546] ? + coreFix_memExe_stb$deq[247:240] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[247:240], + coreFix_memExe_stb$deq[545] ? + coreFix_memExe_stb$deq[239:232] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[239:232], + coreFix_memExe_stb$deq[544] ? + coreFix_memExe_stb$deq[231:224] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[231:224], + coreFix_memExe_stb$deq[543] ? + coreFix_memExe_stb$deq[223:216] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[223:216], + coreFix_memExe_stb$deq[542] ? + coreFix_memExe_stb$deq[215:208] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[215:208], + coreFix_memExe_stb$deq[541] ? + coreFix_memExe_stb$deq[207:200] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[207:200], + coreFix_memExe_stb$deq[540] ? + coreFix_memExe_stb$deq[199:192] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[199:192], + coreFix_memExe_stb$deq[539] ? + coreFix_memExe_stb$deq[191:184] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:184], + coreFix_memExe_stb$deq[538] ? + coreFix_memExe_stb$deq[183:176] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[183:176], + coreFix_memExe_stb$deq[537] ? + coreFix_memExe_stb$deq[175:168] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[175:168], + coreFix_memExe_stb$deq[536] ? + coreFix_memExe_stb$deq[167:160] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[167:160], + coreFix_memExe_stb$deq[535] ? + coreFix_memExe_stb$deq[159:152] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[159:152], + coreFix_memExe_stb$deq[534] ? + coreFix_memExe_stb$deq[151:144] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[151:144], + coreFix_memExe_stb$deq[533] ? + coreFix_memExe_stb$deq[143:136] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[143:136], + coreFix_memExe_stb$deq[532] ? + coreFix_memExe_stb$deq[135:128] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[135:128], + coreFix_memExe_stb$deq[531] ? + coreFix_memExe_stb$deq[127:120] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:120], + coreFix_memExe_stb$deq[530] ? + coreFix_memExe_stb$deq[119:112] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[119:112], + coreFix_memExe_stb$deq[529] ? + coreFix_memExe_stb$deq[111:104] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[111:104], + coreFix_memExe_stb$deq[528] ? + coreFix_memExe_stb$deq[103:96] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[103:96], + coreFix_memExe_stb$deq[527] ? + coreFix_memExe_stb$deq[95:88] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[95:88], + coreFix_memExe_stb$deq[526] ? + coreFix_memExe_stb$deq[87:80] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[87:80], + coreFix_memExe_stb$deq[525] ? + coreFix_memExe_stb$deq[79:72] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[79:72], + coreFix_memExe_stb$deq[524] ? + coreFix_memExe_stb$deq[71:64] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[71:64], + coreFix_memExe_stb$deq[523] ? + coreFix_memExe_stb$deq[63:56] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:56], + coreFix_memExe_stb$deq[522] ? + coreFix_memExe_stb$deq[55:48] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[55:48], + coreFix_memExe_stb$deq[521] ? + coreFix_memExe_stb$deq[47:40] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[47:40], + coreFix_memExe_stb$deq[520] ? + coreFix_memExe_stb$deq[39:32] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[39:32], + coreFix_memExe_stb$deq[519] ? + coreFix_memExe_stb$deq[31:24] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[31:24], + coreFix_memExe_stb$deq[518] ? + coreFix_memExe_stb$deq[23:16] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[23:16], + coreFix_memExe_stb$deq[517] ? + coreFix_memExe_stb$deq[15:8] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[15:8], + coreFix_memExe_stb$deq[516] ? + coreFix_memExe_stb$deq[7:0] : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[7:0] }; + 3'd3: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5470 = + IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d5154; + default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5470 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:0]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q278 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q278 = 3'd7; + endcase + end + always@(coreFix_aluExe_1_regToExeQ$first) + begin + case (coreFix_aluExe_1_regToExeQ$first[790:788]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_790_ETC__q279 = + coreFix_aluExe_1_regToExeQ$first[790:788]; + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_790_ETC__q279 = 3'd7; + endcase + end + always@(coreFix_aluExe_1_regToExeQ$first or + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_790_ETC__q279) + begin + case (coreFix_aluExe_1_regToExeQ$first[816:814]) + 3'd0, 3'd1, 3'd2, 3'd3: + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_816_ETC__q280 = + coreFix_aluExe_1_regToExeQ$first[816:787]; + 3'd4: + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_816_ETC__q280 = + { coreFix_aluExe_1_regToExeQ$first[816:814], + 18'h2AAAA, + coreFix_aluExe_1_regToExeQ$first[795:791], + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_790_ETC__q279, + coreFix_aluExe_1_regToExeQ$first[787] }; + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_816_ETC__q280 = + 30'd715827882; + endcase + end + always@(coreFix_aluExe_1_regToExeQ$first or + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17308) + begin + case (coreFix_aluExe_1_regToExeQ$first[786:785]) + 2'd0: + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_786_ETC__q281 = + coreFix_aluExe_1_regToExeQ$first[786:776]; + 2'd1: + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_786_ETC__q281 = + { coreFix_aluExe_1_regToExeQ$first[786:785], + IF_coreFix_aluExe_1_regToExeQ_first__7179_BITS_ETC___d17308 }; + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_786_ETC__q281 = + 11'd1194; + endcase + end + always@(coreFix_aluExe_1_regToExeQ$first) + begin + case (coreFix_aluExe_1_regToExeQ$first[728:717]) + 12'd1, + 12'd2, + 12'd3, + 12'd256, + 12'd260, + 12'd261, + 12'd262, + 12'd320, + 12'd321, + 12'd322, + 12'd323, + 12'd324, + 12'd384, + 12'd768, + 12'd769, + 12'd770, + 12'd771, + 12'd772, + 12'd773, + 12'd774, + 12'd832, + 12'd833, + 12'd834, + 12'd835, + 12'd836, + 12'd1952, + 12'd1953, + 12'd1954, + 12'd1955, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, + 12'd2048, + 12'd2049, + 12'd2496, + 12'd2816, + 12'd2818, + 12'd3008, + 12'd3072, + 12'd3073, + 12'd3074, + 12'd3857, + 12'd3858, + 12'd3859, + 12'd3860: + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q282 = + coreFix_aluExe_1_regToExeQ$first[728:717]; + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q282 = + 12'd2303; + endcase + end + always@(coreFix_aluExe_1_regToExeQ$first) + begin + case (coreFix_aluExe_1_regToExeQ$first[715:711]) + 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q283 = + coreFix_aluExe_1_regToExeQ$first[715:711]; + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q283 = + 5'd10; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first) + begin + case (coreFix_aluExe_0_regToExeQ$first[790:788]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_790_ETC__q284 = + coreFix_aluExe_0_regToExeQ$first[790:788]; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_790_ETC__q284 = 3'd7; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first or + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_790_ETC__q284) + begin + case (coreFix_aluExe_0_regToExeQ$first[816:814]) + 3'd0, 3'd1, 3'd2, 3'd3: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_816_ETC__q285 = + coreFix_aluExe_0_regToExeQ$first[816:787]; + 3'd4: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_816_ETC__q285 = + { coreFix_aluExe_0_regToExeQ$first[816:814], + 18'h2AAAA, + coreFix_aluExe_0_regToExeQ$first[795:791], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_790_ETC__q284, + coreFix_aluExe_0_regToExeQ$first[787] }; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_816_ETC__q285 = + 30'd715827882; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first or + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19386) + begin + case (coreFix_aluExe_0_regToExeQ$first[786:785]) + 2'd0: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_786_ETC__q286 = + coreFix_aluExe_0_regToExeQ$first[786:776]; + 2'd1: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_786_ETC__q286 = + { coreFix_aluExe_0_regToExeQ$first[786:785], + IF_coreFix_aluExe_0_regToExeQ_first__9257_BITS_ETC___d19386 }; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_786_ETC__q286 = + 11'd1194; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first) + begin + case (coreFix_aluExe_0_regToExeQ$first[728:717]) + 12'd1, + 12'd2, + 12'd3, + 12'd256, + 12'd260, + 12'd261, + 12'd262, + 12'd320, + 12'd321, + 12'd322, + 12'd323, + 12'd324, + 12'd384, + 12'd768, + 12'd769, + 12'd770, + 12'd771, + 12'd772, + 12'd773, + 12'd774, + 12'd832, + 12'd833, + 12'd834, + 12'd835, + 12'd836, + 12'd1952, + 12'd1953, + 12'd1954, + 12'd1955, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, + 12'd2048, + 12'd2049, + 12'd2496, + 12'd2816, + 12'd2818, + 12'd3008, + 12'd3072, + 12'd3073, + 12'd3074, + 12'd3857, + 12'd3858, + 12'd3859, + 12'd3860: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q287 = + coreFix_aluExe_0_regToExeQ$first[728:717]; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q287 = + 12'd2303; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first) + begin + case (coreFix_aluExe_0_regToExeQ$first[715:711]) + 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q288 = + coreFix_aluExe_0_regToExeQ$first[715:711]; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q288 = + 5'd10; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4871 or + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843 or + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849 or + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4863) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[7:6]) + 2'd0: + IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4873 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849 }; + 2'd1: + IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4873 = + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4863; + default: IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4873 = + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4871; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14017 or + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13307 or + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14073) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) + 5'd0, 5'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14077 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13307; + 5'd25: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14077 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14017; + 5'd26, 5'd27: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14077 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14073; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14077 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14017; + endcase + end + always@(capChecks___d4142) + begin + case (capChecks___d4142[4:0]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd10, + 5'd11, + 5'd16, + 5'd17, + 5'd18, + 5'd19, + 5'd20, + 5'd21, + 5'd22, + 5'd23, + 5'd24, + 5'd25, + 5'd26: + CASE_capChecks_142_BITS_4_TO_0_0_capChecks_142_ETC__q289 = + capChecks___d4142[4:0]; + default: CASE_capChecks_142_BITS_4_TO_0_0_capChecks_142_ETC__q289 = + 5'd27; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q290 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[514:451]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q290 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[514:451]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q291 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[450:387]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q291 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[450:387]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q292 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[386:323]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q292 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[386:323]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[322:259]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[322:259]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[258:195]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[258:195]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[194:131]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q296 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q296 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448]; endcase end @@ -35057,10 +44625,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q297 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q297 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384]; endcase end @@ -35070,10 +44638,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q298 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q298 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320]; endcase end @@ -35083,10 +44651,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256]; endcase end @@ -35096,10 +44664,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192]; endcase end @@ -35109,282 +44677,36 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695 = 3'd4; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695 = 3'd3; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695 = 3'd2; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695 = 3'd1; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695 = - 3'd0; - endcase - end - always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or - coreFix_memExe_stb$deq or - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 or - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79]) - 3'd0, 3'd2, 3'd4: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; - 3'd1: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 = - { coreFix_memExe_stb$deq[575] ? - coreFix_memExe_stb$deq[511:504] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:504], - coreFix_memExe_stb$deq[574] ? - coreFix_memExe_stb$deq[503:496] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[503:496], - coreFix_memExe_stb$deq[573] ? - coreFix_memExe_stb$deq[495:488] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[495:488], - coreFix_memExe_stb$deq[572] ? - coreFix_memExe_stb$deq[487:480] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[487:480], - coreFix_memExe_stb$deq[571] ? - coreFix_memExe_stb$deq[479:472] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[479:472], - coreFix_memExe_stb$deq[570] ? - coreFix_memExe_stb$deq[471:464] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[471:464], - coreFix_memExe_stb$deq[569] ? - coreFix_memExe_stb$deq[463:456] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[463:456], - coreFix_memExe_stb$deq[568] ? - coreFix_memExe_stb$deq[455:448] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[455:448], - coreFix_memExe_stb$deq[567] ? - coreFix_memExe_stb$deq[447:440] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:440], - coreFix_memExe_stb$deq[566] ? - coreFix_memExe_stb$deq[439:432] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[439:432], - coreFix_memExe_stb$deq[565] ? - coreFix_memExe_stb$deq[431:424] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[431:424], - coreFix_memExe_stb$deq[564] ? - coreFix_memExe_stb$deq[423:416] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[423:416], - coreFix_memExe_stb$deq[563] ? - coreFix_memExe_stb$deq[415:408] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[415:408], - coreFix_memExe_stb$deq[562] ? - coreFix_memExe_stb$deq[407:400] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[407:400], - coreFix_memExe_stb$deq[561] ? - coreFix_memExe_stb$deq[399:392] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[399:392], - coreFix_memExe_stb$deq[560] ? - coreFix_memExe_stb$deq[391:384] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[391:384], - coreFix_memExe_stb$deq[559] ? - coreFix_memExe_stb$deq[383:376] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:376], - coreFix_memExe_stb$deq[558] ? - coreFix_memExe_stb$deq[375:368] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[375:368], - coreFix_memExe_stb$deq[557] ? - coreFix_memExe_stb$deq[367:360] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[367:360], - coreFix_memExe_stb$deq[556] ? - coreFix_memExe_stb$deq[359:352] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[359:352], - coreFix_memExe_stb$deq[555] ? - coreFix_memExe_stb$deq[351:344] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[351:344], - coreFix_memExe_stb$deq[554] ? - coreFix_memExe_stb$deq[343:336] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[343:336], - coreFix_memExe_stb$deq[553] ? - coreFix_memExe_stb$deq[335:328] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[335:328], - coreFix_memExe_stb$deq[552] ? - coreFix_memExe_stb$deq[327:320] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[327:320], - coreFix_memExe_stb$deq[551] ? - coreFix_memExe_stb$deq[319:312] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:312], - coreFix_memExe_stb$deq[550] ? - coreFix_memExe_stb$deq[311:304] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[311:304], - coreFix_memExe_stb$deq[549] ? - coreFix_memExe_stb$deq[303:296] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[303:296], - coreFix_memExe_stb$deq[548] ? - coreFix_memExe_stb$deq[295:288] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[295:288], - coreFix_memExe_stb$deq[547] ? - coreFix_memExe_stb$deq[287:280] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[287:280], - coreFix_memExe_stb$deq[546] ? - coreFix_memExe_stb$deq[279:272] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[279:272], - coreFix_memExe_stb$deq[545] ? - coreFix_memExe_stb$deq[271:264] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[271:264], - coreFix_memExe_stb$deq[544] ? - coreFix_memExe_stb$deq[263:256] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[263:256], - coreFix_memExe_stb$deq[543] ? - coreFix_memExe_stb$deq[255:248] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:248], - coreFix_memExe_stb$deq[542] ? - coreFix_memExe_stb$deq[247:240] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[247:240], - coreFix_memExe_stb$deq[541] ? - coreFix_memExe_stb$deq[239:232] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[239:232], - coreFix_memExe_stb$deq[540] ? - coreFix_memExe_stb$deq[231:224] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[231:224], - coreFix_memExe_stb$deq[539] ? - coreFix_memExe_stb$deq[223:216] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[223:216], - coreFix_memExe_stb$deq[538] ? - coreFix_memExe_stb$deq[215:208] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[215:208], - coreFix_memExe_stb$deq[537] ? - coreFix_memExe_stb$deq[207:200] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[207:200], - coreFix_memExe_stb$deq[536] ? - coreFix_memExe_stb$deq[199:192] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[199:192], - coreFix_memExe_stb$deq[535] ? - coreFix_memExe_stb$deq[191:184] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:184], - coreFix_memExe_stb$deq[534] ? - coreFix_memExe_stb$deq[183:176] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[183:176], - coreFix_memExe_stb$deq[533] ? - coreFix_memExe_stb$deq[175:168] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[175:168], - coreFix_memExe_stb$deq[532] ? - coreFix_memExe_stb$deq[167:160] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[167:160], - coreFix_memExe_stb$deq[531] ? - coreFix_memExe_stb$deq[159:152] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[159:152], - coreFix_memExe_stb$deq[530] ? - coreFix_memExe_stb$deq[151:144] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[151:144], - coreFix_memExe_stb$deq[529] ? - coreFix_memExe_stb$deq[143:136] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[143:136], - coreFix_memExe_stb$deq[528] ? - coreFix_memExe_stb$deq[135:128] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[135:128], - coreFix_memExe_stb$deq[527] ? - coreFix_memExe_stb$deq[127:120] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:120], - coreFix_memExe_stb$deq[526] ? - coreFix_memExe_stb$deq[119:112] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[119:112], - coreFix_memExe_stb$deq[525] ? - coreFix_memExe_stb$deq[111:104] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[111:104], - coreFix_memExe_stb$deq[524] ? - coreFix_memExe_stb$deq[103:96] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[103:96], - coreFix_memExe_stb$deq[523] ? - coreFix_memExe_stb$deq[95:88] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[95:88], - coreFix_memExe_stb$deq[522] ? - coreFix_memExe_stb$deq[87:80] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[87:80], - coreFix_memExe_stb$deq[521] ? - coreFix_memExe_stb$deq[79:72] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[79:72], - coreFix_memExe_stb$deq[520] ? - coreFix_memExe_stb$deq[71:64] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[71:64], - coreFix_memExe_stb$deq[519] ? - coreFix_memExe_stb$deq[63:56] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:56], - coreFix_memExe_stb$deq[518] ? - coreFix_memExe_stb$deq[55:48] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[55:48], - coreFix_memExe_stb$deq[517] ? - coreFix_memExe_stb$deq[47:40] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[47:40], - coreFix_memExe_stb$deq[516] ? - coreFix_memExe_stb$deq[39:32] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[39:32], - coreFix_memExe_stb$deq[515] ? - coreFix_memExe_stb$deq[31:24] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[31:24], - coreFix_memExe_stb$deq[514] ? - coreFix_memExe_stb$deq[23:16] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[23:16], - coreFix_memExe_stb$deq[513] ? - coreFix_memExe_stb$deq[15:8] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[15:8], - coreFix_memExe_stb$deq[512] ? - coreFix_memExe_stb$deq[7:0] : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[7:0] }; - 3'd3: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 = - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 ? - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; - default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242 = 3'd7; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 or - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9166 or - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9925) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) - 5'd0, 5'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9929 = - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9166; - 5'd25: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9929 = - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871; - 5'd26, 5'd27: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9929 = - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9925; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9929 = - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q302 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q302 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q303 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q303 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67]; endcase end @@ -35394,10 +44716,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q304 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q304 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3]; endcase end @@ -35407,10 +44729,23 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64]; endcase end @@ -35420,10 +44755,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q307 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q307 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0]; endcase end @@ -35433,11 +44768,11 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[578:515]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[582:519]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[578:515]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[582:519]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or @@ -35446,11 +44781,11 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514:513]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[518:517]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514:513]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[518:517]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or @@ -35459,11 +44794,37 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 = - !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = + !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[516]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 = - !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = + !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[516]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q311 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[521:520]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q311 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[521:520]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q312 = + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[519]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q312 = + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[519]; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -35474,44 +44835,18 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12542 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq; 5'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12542 = coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq; 5'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12542 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406 = + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12542 = coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) - 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516]; - 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516]; - endcase - end - always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) - 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251 = - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515]; - 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251 = - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515]; - endcase - end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready or coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready or @@ -35523,10 +44858,10 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228]) 2'd0, 2'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8425 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12561 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit != 2'd0 && coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8425 = + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d12561 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready && coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq && @@ -35540,10 +44875,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q313 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q313 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4]; endcase end @@ -35553,10 +44888,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q314 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q314 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3]; endcase end @@ -35566,10 +44901,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q315 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q315 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0]; endcase end @@ -35579,10 +44914,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q316 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q316 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8]; endcase end @@ -35592,10 +44927,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6]; endcase end @@ -35605,11 +44940,11 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q257 = - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q318 = + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[586]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q257 = - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q318 = + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[586]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or @@ -35618,141 +44953,1979 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q319 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[586]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582]; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q319 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[586]; endcase end always@(rob$deqPort_0_deq_data) begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q259 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q259 = - 4'd14; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 = + case (rob$deqPort_0_deq_data[264:261]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q320 = + rob$deqPort_0_deq_data[264:261]; + default: CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q320 = 4'd15; endcase end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[265:261]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd10, + 5'd11, + 5'd16, + 5'd17, + 5'd18, + 5'd19, + 5'd20, + 5'd21, + 5'd22, + 5'd23, + 5'd24, + 5'd25, + 5'd26: + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q321 = + rob$deqPort_0_deq_data[265:261]; + default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q321 = + 5'd27; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[265:261]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd11, + 5'd12, + 5'd13, + 5'd15: + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q322 = + rob$deqPort_0_deq_data[265:261]; + default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q322 = + 5'd28; + endcase + end + always@(rob$deqPort_0_deq_data or + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q320 or + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q321 or + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q322) + begin + case (rob$deqPort_0_deq_data[273:272]) + 2'd0: + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q323 = + { 2'd0, + rob$deqPort_0_deq_data[271:266], + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q321 }; + 2'd1: + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q323 = + { rob$deqPort_0_deq_data[273:272], + 6'h2A, + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q322 }; + default: CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q323 = + { 9'd298, + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q320 }; + endcase + end + always@(coreFix_memExe_memRespLdQ_deqP or + coreFix_memExe_memRespLdQ_data_0 or + coreFix_memExe_memRespLdQ_data_1) + begin + case (coreFix_memExe_memRespLdQ_deqP) + 1'd0: + CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q324 = + coreFix_memExe_memRespLdQ_data_0[128]; + 1'd1: + CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q324 = + coreFix_memExe_memRespLdQ_data_1[128]; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q325 = + coreFix_memExe_forwardQ_data_0[128]; + 1'd1: + CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q325 = + coreFix_memExe_forwardQ_data_1[128]; + endcase + end + always@(f_csr_reqs$D_OUT) + begin + case (f_csr_reqs$D_OUT[9:5]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd10, + 5'd11, + 5'd16, + 5'd17, + 5'd18, + 5'd19, + 5'd20, + 5'd21, + 5'd22, + 5'd23, + 5'd24, + 5'd25, + 5'd26: + CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q327 = + f_csr_reqs$D_OUT[9:5]; + default: CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q327 = + 5'd27; + endcase + end + always@(robdeqPort_0_deq_data_BITS_95_TO_32__q326) + begin + case (robdeqPort_0_deq_data_BITS_95_TO_32__q326[9:5]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd10, + 5'd11, + 5'd16, + 5'd17, + 5'd18, + 5'd19, + 5'd20, + 5'd21, + 5'd22, + 5'd23, + 5'd24, + 5'd25, + 5'd26: + CASE_robdeqPort_0_deq_data_BITS_95_TO_3226_BIT_ETC__q328 = + robdeqPort_0_deq_data_BITS_95_TO_32__q326[9:5]; + default: CASE_robdeqPort_0_deq_data_BITS_95_TO_3226_BIT_ETC__q328 = + 5'd27; + endcase + end always@(mmio_dataReqQ_data_0) begin - case (mmio_dataReqQ_data_0[77:76]) + case (mmio_dataReqQ_data_0[150:149]) 2'd0, 2'd1, 2'd2: - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q262 = - mmio_dataReqQ_data_0[77:72]; + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q329 = + mmio_dataReqQ_data_0[150:145]; 2'd3: - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q262 = - { 2'd3, mmio_dataReqQ_data_0[75:72] }; + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q329 = + { 2'd3, mmio_dataReqQ_data_0[148:145] }; endcase end always@(coreFix_memExe_lsq$firstSt) begin case (coreFix_memExe_lsq$firstSt[3:0]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q263 = + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q263 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330 = 4'd15; endcase end + always@(coreFix_memExe_lsq$firstSt) + begin + case (coreFix_memExe_lsq$firstSt[4:0]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd10, + 5'd11, + 5'd16, + 5'd17, + 5'd18, + 5'd19, + 5'd20, + 5'd21, + 5'd22, + 5'd23, + 5'd24, + 5'd25, + 5'd26: + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331 = + coreFix_memExe_lsq$firstSt[4:0]; + default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331 = + 5'd27; + endcase + end + always@(coreFix_memExe_lsq$firstSt) + begin + case (coreFix_memExe_lsq$firstSt[4:0]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd11, + 5'd12, + 5'd13, + 5'd15: + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332 = + coreFix_memExe_lsq$firstSt[4:0]; + default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332 = + 5'd28; + endcase + end + always@(coreFix_memExe_lsq$firstSt or + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330 or + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331 or + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332) + begin + case (coreFix_memExe_lsq$firstSt[12:11]) + 2'd0: + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333 = + { 2'd0, + coreFix_memExe_lsq$firstSt[10:5], + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331 }; + 2'd1: + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333 = + { coreFix_memExe_lsq$firstSt[12:11], + 6'h2A, + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332 }; + default: CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333 = + { 9'd298, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330 }; + endcase + end always@(coreFix_memExe_lsq$firstLd) begin case (coreFix_memExe_lsq$firstLd[6:3]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264 = + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334 = coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264 = + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334 = 4'd15; endcase end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[7:3]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd10, + 5'd11, + 5'd16, + 5'd17, + 5'd18, + 5'd19, + 5'd20, + 5'd21, + 5'd22, + 5'd23, + 5'd24, + 5'd25, + 5'd26: + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335 = + coreFix_memExe_lsq$firstLd[7:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335 = + 5'd27; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[7:3]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd11, + 5'd12, + 5'd13, + 5'd15: + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336 = + coreFix_memExe_lsq$firstLd[7:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336 = + 5'd28; + endcase + end + always@(coreFix_memExe_lsq$firstLd or + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334 or + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335 or + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336) + begin + case (coreFix_memExe_lsq$firstLd[15:14]) + 2'd0: + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337 = + { 2'd0, + coreFix_memExe_lsq$firstLd[13:8], + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335 }; + 2'd1: + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337 = + { coreFix_memExe_lsq$firstLd[15:14], + 6'h2A, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336 }; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337 = + { 9'd298, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334 }; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16720 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16714 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16728 = + csrf_ddc_reg[67]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16728 = + csrf_stcc_reg[67]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16728 = + csrf_stdc_reg[67]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16728 = + csrf_sScratchC_reg[67]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16728 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16714; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16728 = + csrf_mtcc_reg[67]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16728 = + csrf_mtdc_reg[67]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16728 = + csrf_mScratchC_reg[67]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16728 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16720; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16632 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16623 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16640 = + csrf_ddc_reg[152]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16640 = + csrf_stcc_reg[152]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16640 = + csrf_stdc_reg[152]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16640 = + csrf_sScratchC_reg[152]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16640 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16623; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16640 = + csrf_mtcc_reg[152]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16640 = + csrf_mtdc_reg[152]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16640 = + csrf_mScratchC_reg[152]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16640 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16632; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16742 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16736 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16750 = + csrf_ddc_reg[66]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16750 = + csrf_stcc_reg[66]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16750 = + csrf_stdc_reg[66]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16750 = + csrf_sScratchC_reg[66]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16750 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16736; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16750 = + csrf_mtcc_reg[66]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16750 = + csrf_mtdc_reg[66]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16750 = + csrf_mScratchC_reg[66]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16750 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16742; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16764 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16758 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16772 = + csrf_ddc_reg[65]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16772 = + csrf_stcc_reg[65]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16772 = + csrf_stdc_reg[65]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16772 = + csrf_sScratchC_reg[65]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16772 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16758; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16772 = + csrf_mtcc_reg[65]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16772 = + csrf_mtdc_reg[65]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16772 = + csrf_mScratchC_reg[65]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16772 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16764; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16786 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16780 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16794 = + csrf_ddc_reg[64]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16794 = + csrf_stcc_reg[64]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16794 = + csrf_stdc_reg[64]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16794 = + csrf_sScratchC_reg[64]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16794 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16780; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16794 = + csrf_mtcc_reg[64]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16794 = + csrf_mtdc_reg[64]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16794 = + csrf_mScratchC_reg[64]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16794 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16786; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16808 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16802 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16816 = + csrf_ddc_reg[63]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16816 = + csrf_stcc_reg[63]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16816 = + csrf_stdc_reg[63]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16816 = + csrf_sScratchC_reg[63]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16816 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16802; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16816 = + csrf_mtcc_reg[63]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16816 = + csrf_mtdc_reg[63]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16816 = + csrf_mScratchC_reg[63]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16816 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16808; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16830 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16824 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16838 = + csrf_ddc_reg[62]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16838 = + csrf_stcc_reg[62]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16838 = + csrf_stdc_reg[62]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16838 = + csrf_sScratchC_reg[62]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16838 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16824; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16838 = + csrf_mtcc_reg[62]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16838 = + csrf_mtdc_reg[62]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16838 = + csrf_mScratchC_reg[62]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16838 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16830; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16852 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16846 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16860 = + csrf_ddc_reg[61]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16860 = + csrf_stcc_reg[61]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16860 = + csrf_stdc_reg[61]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16860 = + csrf_sScratchC_reg[61]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16860 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16846; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16860 = + csrf_mtcc_reg[61]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16860 = + csrf_mtdc_reg[61]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16860 = + csrf_mScratchC_reg[61]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16860 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16852; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16874 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16868 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16882 = + csrf_ddc_reg[60]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16882 = + csrf_stcc_reg[60]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16882 = + csrf_stdc_reg[60]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16882 = + csrf_sScratchC_reg[60]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16882 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16868; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16882 = + csrf_mtcc_reg[60]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16882 = + csrf_mtdc_reg[60]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16882 = + csrf_mScratchC_reg[60]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16882 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16874; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16896 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16890 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16904 = + csrf_ddc_reg[59]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16904 = + csrf_stcc_reg[59]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16904 = + csrf_stdc_reg[59]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16904 = + csrf_sScratchC_reg[59]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16904 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16890; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16904 = + csrf_mtcc_reg[59]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16904 = + csrf_mtdc_reg[59]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16904 = + csrf_mScratchC_reg[59]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16904 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16896; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16918 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16912 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16926 = + csrf_ddc_reg[58]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16926 = + csrf_stcc_reg[58]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16926 = + csrf_stdc_reg[58]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16926 = + csrf_sScratchC_reg[58]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16926 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16912; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16926 = + csrf_mtcc_reg[58]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16926 = + csrf_mtdc_reg[58]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16926 = + csrf_mScratchC_reg[58]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16926 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16918; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16940 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16934 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16948 = + csrf_ddc_reg[57]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16948 = + csrf_stcc_reg[57]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16948 = + csrf_stdc_reg[57]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16948 = + csrf_sScratchC_reg[57]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16948 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16934; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16948 = + csrf_mtcc_reg[57]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16948 = + csrf_mtdc_reg[57]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16948 = + csrf_mScratchC_reg[57]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16948 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16940; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16962 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16956 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16970 = + csrf_ddc_reg[56]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16970 = + csrf_stcc_reg[56]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16970 = + csrf_stdc_reg[56]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16970 = + csrf_sScratchC_reg[56]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16970 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16956; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16970 = + csrf_mtcc_reg[56]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16970 = + csrf_mtdc_reg[56]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16970 = + csrf_mScratchC_reg[56]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16970 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16962; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16990 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16984 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16998 = + csrf_ddc_reg[55]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16998 = + csrf_stcc_reg[55]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16998 = + csrf_stdc_reg[55]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16998 = + csrf_sScratchC_reg[55]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16998 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16984; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16998 = + csrf_mtcc_reg[55]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16998 = + csrf_mtdc_reg[55]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16998 = + csrf_mScratchC_reg[55]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16998 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16990; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17057 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17051 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17065 = + csrf_ddc_reg[34]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17065 = + csrf_stcc_reg[34]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17065 = + csrf_stdc_reg[34]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17065 = + csrf_sScratchC_reg[34]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17065 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17051; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17065 = + csrf_mtcc_reg[34]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17065 = + csrf_mtdc_reg[34]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17065 = + csrf_mScratchC_reg[34]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17065 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17057; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17012 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17006 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: thin_reserved__h857113 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h857113 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h857113 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h857113 = csrf_sScratchC_reg[54:53]; + 5'd15: + thin_reserved__h857113 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17006; + 5'd28: thin_reserved__h857113 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h857113 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h857113 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h857113 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17012; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17012 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17006 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: thin_reserved__h896606 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h896606 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h896606 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h896606 = csrf_sScratchC_reg[54:53]; + 5'd15: + thin_reserved__h896606 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17006; + 5'd28: thin_reserved__h896606 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h896606 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h896606 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h896606 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17012; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16698 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16692 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: thin_perms_soft__h857361 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h857361 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h857361 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h857361 = csrf_sScratchC_reg[71:68]; + 5'd15: + thin_perms_soft__h857361 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16692; + 5'd28: thin_perms_soft__h857361 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h857361 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h857361 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h857361 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16698; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16698 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16692 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: thin_perms_soft__h896782 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h896782 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h896782 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h896782 = csrf_sScratchC_reg[71:68]; + 5'd15: + thin_perms_soft__h896782 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16692; + 5'd28: thin_perms_soft__h896782 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h896782 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h896782 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h896782 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16698; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16654 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16648 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: thin_address__h857109 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h857109 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h857109 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h857109 = csrf_sScratchC_reg[151:86]; + 5'd15: + thin_address__h857109 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16648; + 5'd28: thin_address__h857109 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h857109 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h857109 = csrf_mScratchC_reg[151:86]; + default: thin_address__h857109 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16654; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16654 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16648 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: thin_address__h896602 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h896602 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h896602 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h896602 = csrf_sScratchC_reg[151:86]; + 5'd15: + thin_address__h896602 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16648; + 5'd28: thin_address__h896602 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h896602 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h896602 = csrf_mScratchC_reg[151:86]; + default: thin_address__h896602 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16654; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17105 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17099 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: thin_bounds_baseBits__h859108 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h859108 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h859108 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h859108 = csrf_sScratchC_reg[13:0]; + 5'd15: + thin_bounds_baseBits__h859108 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17099; + 5'd28: thin_bounds_baseBits__h859108 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h859108 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h859108 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h859108 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17105; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17105 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17099 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: thin_bounds_baseBits__h898009 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h898009 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h898009 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h898009 = csrf_sScratchC_reg[13:0]; + 5'd15: + thin_bounds_baseBits__h898009 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17099; + 5'd28: thin_bounds_baseBits__h898009 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h898009 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h898009 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h898009 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17105; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17129 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17123 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: thin_bounds_topBits__h859107 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h859107 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h859107 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h859107 = csrf_sScratchC_reg[27:14]; + 5'd15: + thin_bounds_topBits__h859107 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17123; + 5'd28: thin_bounds_topBits__h859107 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h859107 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h859107 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h859107 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17129; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17129 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17123 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: thin_bounds_topBits__h898008 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h898008 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h898008 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h898008 = csrf_sScratchC_reg[27:14]; + 5'd15: + thin_bounds_topBits__h898008 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17123; + 5'd28: thin_bounds_topBits__h898008 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h898008 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h898008 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h898008 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17129; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16676 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16670 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: thin_addrBits__h857110 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h857110 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h857110 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h857110 = csrf_sScratchC_reg[85:72]; + 5'd15: + thin_addrBits__h857110 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16670; + 5'd28: thin_addrBits__h857110 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h857110 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h857110 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h857110 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16676; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16676 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16670 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: thin_addrBits__h896603 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h896603 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h896603 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h896603 = csrf_sScratchC_reg[85:72]; + 5'd15: + thin_addrBits__h896603 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16670; + 5'd28: thin_addrBits__h896603 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h896603 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h896603 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h896603 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16676; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16720 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16714 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19040 = + csrf_ddc_reg[67]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19040 = + csrf_stcc_reg[67]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19040 = + csrf_stdc_reg[67]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19040 = + csrf_sScratchC_reg[67]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19040 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16714; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19040 = + csrf_mtcc_reg[67]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19040 = + csrf_mtdc_reg[67]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19040 = + csrf_mScratchC_reg[67]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19040 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16720; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16632 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16623 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19004 = + csrf_ddc_reg[152]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19004 = + csrf_stcc_reg[152]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19004 = + csrf_stdc_reg[152]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19004 = + csrf_sScratchC_reg[152]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19004 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16623; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19004 = + csrf_mtcc_reg[152]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19004 = + csrf_mtdc_reg[152]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19004 = + csrf_mScratchC_reg[152]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19004 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16632; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16742 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16736 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19049 = + csrf_ddc_reg[66]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19049 = + csrf_stcc_reg[66]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19049 = + csrf_stdc_reg[66]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19049 = + csrf_sScratchC_reg[66]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19049 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16736; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19049 = + csrf_mtcc_reg[66]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19049 = + csrf_mtdc_reg[66]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19049 = + csrf_mScratchC_reg[66]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19049 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16742; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16764 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16758 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19058 = + csrf_ddc_reg[65]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19058 = + csrf_stcc_reg[65]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19058 = + csrf_stdc_reg[65]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19058 = + csrf_sScratchC_reg[65]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19058 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16758; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19058 = + csrf_mtcc_reg[65]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19058 = + csrf_mtdc_reg[65]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19058 = + csrf_mScratchC_reg[65]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19058 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16764; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16808 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16802 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19076 = + csrf_ddc_reg[63]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19076 = + csrf_stcc_reg[63]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19076 = + csrf_stdc_reg[63]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19076 = + csrf_sScratchC_reg[63]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19076 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16802; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19076 = + csrf_mtcc_reg[63]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19076 = + csrf_mtdc_reg[63]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19076 = + csrf_mScratchC_reg[63]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19076 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16808; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16786 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16780 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19067 = + csrf_ddc_reg[64]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19067 = + csrf_stcc_reg[64]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19067 = + csrf_stdc_reg[64]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19067 = + csrf_sScratchC_reg[64]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19067 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16780; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19067 = + csrf_mtcc_reg[64]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19067 = + csrf_mtdc_reg[64]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19067 = + csrf_mScratchC_reg[64]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19067 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16786; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16830 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16824 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19085 = + csrf_ddc_reg[62]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19085 = + csrf_stcc_reg[62]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19085 = + csrf_stdc_reg[62]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19085 = + csrf_sScratchC_reg[62]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19085 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16824; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19085 = + csrf_mtcc_reg[62]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19085 = + csrf_mtdc_reg[62]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19085 = + csrf_mScratchC_reg[62]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19085 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16830; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16852 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16846 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19094 = + csrf_ddc_reg[61]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19094 = + csrf_stcc_reg[61]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19094 = + csrf_stdc_reg[61]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19094 = + csrf_sScratchC_reg[61]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19094 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16846; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19094 = + csrf_mtcc_reg[61]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19094 = + csrf_mtdc_reg[61]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19094 = + csrf_mScratchC_reg[61]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19094 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16852; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16874 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16868 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19103 = + csrf_ddc_reg[60]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19103 = + csrf_stcc_reg[60]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19103 = + csrf_stdc_reg[60]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19103 = + csrf_sScratchC_reg[60]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19103 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16868; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19103 = + csrf_mtcc_reg[60]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19103 = + csrf_mtdc_reg[60]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19103 = + csrf_mScratchC_reg[60]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19103 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16874; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16896 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16890 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19112 = + csrf_ddc_reg[59]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19112 = + csrf_stcc_reg[59]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19112 = + csrf_stdc_reg[59]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19112 = + csrf_sScratchC_reg[59]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19112 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16890; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19112 = + csrf_mtcc_reg[59]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19112 = + csrf_mtdc_reg[59]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19112 = + csrf_mScratchC_reg[59]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19112 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16896; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16940 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16934 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19130 = + csrf_ddc_reg[57]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19130 = + csrf_stcc_reg[57]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19130 = + csrf_stdc_reg[57]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19130 = + csrf_sScratchC_reg[57]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19130 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16934; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19130 = + csrf_mtcc_reg[57]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19130 = + csrf_mtdc_reg[57]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19130 = + csrf_mScratchC_reg[57]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19130 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16940; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16918 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16912 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19121 = + csrf_ddc_reg[58]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19121 = + csrf_stcc_reg[58]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19121 = + csrf_stdc_reg[58]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19121 = + csrf_sScratchC_reg[58]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19121 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16912; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19121 = + csrf_mtcc_reg[58]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19121 = + csrf_mtdc_reg[58]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19121 = + csrf_mScratchC_reg[58]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19121 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16918; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16962 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16956 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19139 = + csrf_ddc_reg[56]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19139 = + csrf_stcc_reg[56]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19139 = + csrf_stdc_reg[56]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19139 = + csrf_sScratchC_reg[56]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19139 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16956; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19139 = + csrf_mtcc_reg[56]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19139 = + csrf_mtdc_reg[56]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19139 = + csrf_mScratchC_reg[56]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19139 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16962; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16990 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16984 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19154 = + csrf_ddc_reg[55]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19154 = + csrf_stcc_reg[55]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19154 = + csrf_stdc_reg[55]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19154 = + csrf_sScratchC_reg[55]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19154 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16984; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19154 = + csrf_mtcc_reg[55]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19154 = + csrf_mtdc_reg[55]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19154 = + csrf_mScratchC_reg[55]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19154 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16990; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17057 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17051 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19182 = + csrf_ddc_reg[34]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19182 = + csrf_stcc_reg[34]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19182 = + csrf_stdc_reg[34]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19182 = + csrf_sScratchC_reg[34]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19182 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17051; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19182 = + csrf_mtcc_reg[34]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19182 = + csrf_mtdc_reg[34]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19182 = + csrf_mScratchC_reg[34]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19182 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17057; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17034 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17028 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: thin_otype__h857114 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h857114 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h857114 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h857114 = csrf_sScratchC_reg[52:35]; + 5'd15: + thin_otype__h857114 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17028; + 5'd28: thin_otype__h857114 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h857114 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h857114 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h857114 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17034; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17034 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17028 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: thin_otype__h896607 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h896607 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h896607 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h896607 = csrf_sScratchC_reg[52:35]; + 5'd15: + thin_otype__h896607 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17028; + 5'd28: thin_otype__h896607 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h896607 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h896607 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h896607 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17034; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17079 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17073 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17087 = + csrf_ddc_reg[33:0]; + 5'd12: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17087 = + csrf_stcc_reg[33:0]; + 5'd13: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17087 = + csrf_stdc_reg[33:0]; + 5'd14: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17087 = + csrf_sScratchC_reg[33:0]; + 5'd15: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17087 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17073; + 5'd28: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17087 = + csrf_mtcc_reg[33:0]; + 5'd29: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17087 = + csrf_mtdc_reg[33:0]; + 5'd30: + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17087 = + csrf_mScratchC_reg[33:0]; + default: IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17087 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17079; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17079 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17073 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19191 = + csrf_ddc_reg[33:0]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19191 = + csrf_stcc_reg[33:0]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19191 = + csrf_stdc_reg[33:0]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19191 = + csrf_sScratchC_reg[33:0]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19191 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17073; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19191 = + csrf_mtcc_reg[33:0]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19191 = + csrf_mtdc_reg[33:0]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19191 = + csrf_mScratchC_reg[33:0]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d19191 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17079; + endcase + end always@(mmioToPlatform_pRq_enq_x) begin case (mmioToPlatform_pRq_enq_x[37:36]) 2'd0, 2'd1, 2'd2: - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q265 = + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q338 = mmioToPlatform_pRq_enq_x[37:32]; 2'd3: - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q265 = + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q338 = { 2'd3, mmioToPlatform_pRq_enq_x[35:32] }; endcase end always@(coreFix_aluExe_0_rsAlu$dispatchData) begin - case (coreFix_aluExe_0_rsAlu$dispatchData[139:137]) + case (coreFix_aluExe_0_rsAlu$dispatchData[202:200]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266 = - coreFix_aluExe_0_rsAlu$dispatchData[139:137]; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266 = 3'd7; + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q339 = + coreFix_aluExe_0_rsAlu$dispatchData[202:200]; + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q339 = 3'd7; endcase end always@(coreFix_aluExe_0_rsAlu$dispatchData or - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266) + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q339) begin - case (coreFix_aluExe_0_rsAlu$dispatchData[156:154]) + case (coreFix_aluExe_0_rsAlu$dispatchData[228:226]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267 = - coreFix_aluExe_0_rsAlu$dispatchData[156:136]; + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q340 = + coreFix_aluExe_0_rsAlu$dispatchData[228:199]; 3'd4: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267 = - { coreFix_aluExe_0_rsAlu$dispatchData[156:154], - 9'h0AA, - coreFix_aluExe_0_rsAlu$dispatchData[144:140], - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266, - coreFix_aluExe_0_rsAlu$dispatchData[136] }; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267 = - 21'd1485482; + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q340 = + { coreFix_aluExe_0_rsAlu$dispatchData[228:226], + 18'h2AAAA, + coreFix_aluExe_0_rsAlu$dispatchData[207:203], + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q339, + coreFix_aluExe_0_rsAlu$dispatchData[199] }; + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q340 = + 30'd715827882; + endcase + end + always@(coreFix_aluExe_0_rsAlu$dispatchData or + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d18041) + begin + case (coreFix_aluExe_0_rsAlu$dispatchData[198:197]) + 2'd0: + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341 = + coreFix_aluExe_0_rsAlu$dispatchData[198:188]; + 2'd1: + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341 = + { coreFix_aluExe_0_rsAlu$dispatchData[198:197], + IF_coreFix_aluExe_0_rsAlu_dispatchData__7911_B_ETC___d18041 }; + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341 = + 11'd1194; endcase end always@(coreFix_aluExe_0_rsAlu$dispatchData) begin - case (coreFix_aluExe_0_rsAlu$dispatchData[134:123]) + case (coreFix_aluExe_0_rsAlu$dispatchData[140:129]) 12'd1, 12'd2, 12'd3, @@ -35778,10 +46951,20 @@ module mkCore(CLK, 12'd834, 12'd835, 12'd836, + 12'd1952, + 12'd1953, + 12'd1954, + 12'd1955, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, 12'd2048, 12'd2049, + 12'd2496, 12'd2816, 12'd2818, + 12'd3008, 12'd3072, 12'd3073, 12'd3074, @@ -35789,42 +46972,99 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268 = - coreFix_aluExe_0_rsAlu$dispatchData[134:123]; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342 = + coreFix_aluExe_0_rsAlu$dispatchData[140:129]; + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342 = 12'd2303; endcase end + always@(coreFix_aluExe_0_rsAlu$dispatchData) + begin + case (coreFix_aluExe_0_rsAlu$dispatchData[127:123]) + 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = + coreFix_aluExe_0_rsAlu$dispatchData[127:123]; + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = + 5'd10; + endcase + end + always@(basicExec___d19648) + begin + case (basicExec___d19648[270:266]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd10, + 5'd11, + 5'd16, + 5'd17, + 5'd18, + 5'd19, + 5'd20, + 5'd21, + 5'd22, + 5'd23, + 5'd24, + 5'd25, + 5'd26: + CASE_basicExec_9648_BITS_270_TO_266_0_basicExe_ETC__q344 = + basicExec___d19648[270:266]; + default: CASE_basicExec_9648_BITS_270_TO_266_0_basicExe_ETC__q344 = + 5'd27; + endcase + end always@(coreFix_aluExe_0_dispToRegQ$first) begin - case (coreFix_aluExe_0_dispToRegQ$first[135:133]) + case (coreFix_aluExe_0_dispToRegQ$first[198:196]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269 = - coreFix_aluExe_0_dispToRegQ$first[135:133]; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269 = 3'd7; + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q345 = + coreFix_aluExe_0_dispToRegQ$first[198:196]; + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q345 = 3'd7; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269) + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q345) begin - case (coreFix_aluExe_0_dispToRegQ$first[152:150]) + case (coreFix_aluExe_0_dispToRegQ$first[224:222]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270 = - coreFix_aluExe_0_dispToRegQ$first[152:132]; + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q346 = + coreFix_aluExe_0_dispToRegQ$first[224:195]; 3'd4: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270 = - { coreFix_aluExe_0_dispToRegQ$first[152:150], - 9'h0AA, - coreFix_aluExe_0_dispToRegQ$first[140:136], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269, - coreFix_aluExe_0_dispToRegQ$first[132] }; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270 = - 21'd1485482; + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q346 = + { coreFix_aluExe_0_dispToRegQ$first[224:222], + 18'h2AAAA, + coreFix_aluExe_0_dispToRegQ$first[203:199], + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q345, + coreFix_aluExe_0_dispToRegQ$first[195] }; + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q346 = + 30'd715827882; + endcase + end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18414) + begin + case (coreFix_aluExe_0_dispToRegQ$first[194:193]) + 2'd0: + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347 = + coreFix_aluExe_0_dispToRegQ$first[194:184]; + 2'd1: + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347 = + { coreFix_aluExe_0_dispToRegQ$first[194:193], + IF_coreFix_aluExe_0_dispToRegQ_first__8199_BIT_ETC___d18414 }; + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347 = + 11'd1194; endcase end always@(coreFix_aluExe_0_dispToRegQ$first) begin - case (coreFix_aluExe_0_dispToRegQ$first[130:119]) + case (coreFix_aluExe_0_dispToRegQ$first[136:125]) 12'd1, 12'd2, 12'd3, @@ -35850,10 +47090,20 @@ module mkCore(CLK, 12'd834, 12'd835, 12'd836, + 12'd1952, + 12'd1953, + 12'd1954, + 12'd1955, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, 12'd2048, 12'd2049, + 12'd2496, 12'd2816, 12'd2818, + 12'd3008, 12'd3072, 12'd3073, 12'd3074, @@ -35861,42 +47111,67 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271 = - coreFix_aluExe_0_dispToRegQ$first[130:119]; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q348 = + coreFix_aluExe_0_dispToRegQ$first[136:125]; + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q348 = 12'd2303; endcase end + always@(coreFix_aluExe_0_dispToRegQ$first) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q349 = + coreFix_aluExe_0_dispToRegQ$first[123:119]; + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q349 = + 5'd10; + endcase + end always@(coreFix_aluExe_1_rsAlu$dispatchData) begin - case (coreFix_aluExe_1_rsAlu$dispatchData[139:137]) + case (coreFix_aluExe_1_rsAlu$dispatchData[202:200]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q272 = - coreFix_aluExe_1_rsAlu$dispatchData[139:137]; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q272 = 3'd7; + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q350 = + coreFix_aluExe_1_rsAlu$dispatchData[202:200]; + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q350 = 3'd7; endcase end always@(coreFix_aluExe_1_rsAlu$dispatchData or - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q272) + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q350) begin - case (coreFix_aluExe_1_rsAlu$dispatchData[156:154]) + case (coreFix_aluExe_1_rsAlu$dispatchData[228:226]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273 = - coreFix_aluExe_1_rsAlu$dispatchData[156:136]; + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q351 = + coreFix_aluExe_1_rsAlu$dispatchData[228:199]; 3'd4: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273 = - { coreFix_aluExe_1_rsAlu$dispatchData[156:154], - 9'h0AA, - coreFix_aluExe_1_rsAlu$dispatchData[144:140], - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q272, - coreFix_aluExe_1_rsAlu$dispatchData[136] }; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273 = - 21'd1485482; + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q351 = + { coreFix_aluExe_1_rsAlu$dispatchData[228:226], + 18'h2AAAA, + coreFix_aluExe_1_rsAlu$dispatchData[207:203], + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q350, + coreFix_aluExe_1_rsAlu$dispatchData[199] }; + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q351 = + 30'd715827882; + endcase + end + always@(coreFix_aluExe_1_rsAlu$dispatchData or + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15431) + begin + case (coreFix_aluExe_1_rsAlu$dispatchData[198:197]) + 2'd0: + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352 = + coreFix_aluExe_1_rsAlu$dispatchData[198:188]; + 2'd1: + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352 = + { coreFix_aluExe_1_rsAlu$dispatchData[198:197], + IF_coreFix_aluExe_1_rsAlu_dispatchData__5300_B_ETC___d15431 }; + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352 = + 11'd1194; endcase end always@(coreFix_aluExe_1_rsAlu$dispatchData) begin - case (coreFix_aluExe_1_rsAlu$dispatchData[134:123]) + case (coreFix_aluExe_1_rsAlu$dispatchData[140:129]) 12'd1, 12'd2, 12'd3, @@ -35922,10 +47197,20 @@ module mkCore(CLK, 12'd834, 12'd835, 12'd836, + 12'd1952, + 12'd1953, + 12'd1954, + 12'd1955, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, 12'd2048, 12'd2049, + 12'd2496, 12'd2816, 12'd2818, + 12'd3008, 12'd3072, 12'd3073, 12'd3074, @@ -35933,42 +47218,99 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274 = - coreFix_aluExe_1_rsAlu$dispatchData[134:123]; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353 = + coreFix_aluExe_1_rsAlu$dispatchData[140:129]; + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353 = 12'd2303; endcase end + always@(coreFix_aluExe_1_rsAlu$dispatchData) + begin + case (coreFix_aluExe_1_rsAlu$dispatchData[127:123]) + 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = + coreFix_aluExe_1_rsAlu$dispatchData[127:123]; + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = + 5'd10; + endcase + end + always@(basicExec___d17570) + begin + case (basicExec___d17570[270:266]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd10, + 5'd11, + 5'd16, + 5'd17, + 5'd18, + 5'd19, + 5'd20, + 5'd21, + 5'd22, + 5'd23, + 5'd24, + 5'd25, + 5'd26: + CASE_basicExec_7570_BITS_270_TO_266_0_basicExe_ETC__q355 = + basicExec___d17570[270:266]; + default: CASE_basicExec_7570_BITS_270_TO_266_0_basicExe_ETC__q355 = + 5'd27; + endcase + end always@(coreFix_aluExe_1_dispToRegQ$first) begin - case (coreFix_aluExe_1_dispToRegQ$first[135:133]) + case (coreFix_aluExe_1_dispToRegQ$first[198:196]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q275 = - coreFix_aluExe_1_dispToRegQ$first[135:133]; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q275 = 3'd7; + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q356 = + coreFix_aluExe_1_dispToRegQ$first[198:196]; + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q356 = 3'd7; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q275) + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q356) begin - case (coreFix_aluExe_1_dispToRegQ$first[152:150]) + case (coreFix_aluExe_1_dispToRegQ$first[224:222]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q276 = - coreFix_aluExe_1_dispToRegQ$first[152:132]; + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q357 = + coreFix_aluExe_1_dispToRegQ$first[224:195]; 3'd4: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q276 = - { coreFix_aluExe_1_dispToRegQ$first[152:150], - 9'h0AA, - coreFix_aluExe_1_dispToRegQ$first[140:136], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q275, - coreFix_aluExe_1_dispToRegQ$first[132] }; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q276 = - 21'd1485482; + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q357 = + { coreFix_aluExe_1_dispToRegQ$first[224:222], + 18'h2AAAA, + coreFix_aluExe_1_dispToRegQ$first[203:199], + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q356, + coreFix_aluExe_1_dispToRegQ$first[195] }; + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q357 = + 30'd715827882; + endcase + end + always@(coreFix_aluExe_1_dispToRegQ$first or + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15805) + begin + case (coreFix_aluExe_1_dispToRegQ$first[194:193]) + 2'd0: + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358 = + coreFix_aluExe_1_dispToRegQ$first[194:184]; + 2'd1: + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358 = + { coreFix_aluExe_1_dispToRegQ$first[194:193], + IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15805 }; + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358 = + 11'd1194; endcase end always@(coreFix_aluExe_1_dispToRegQ$first) begin - case (coreFix_aluExe_1_dispToRegQ$first[130:119]) + case (coreFix_aluExe_1_dispToRegQ$first[136:125]) 12'd1, 12'd2, 12'd3, @@ -35994,10 +47336,20 @@ module mkCore(CLK, 12'd834, 12'd835, 12'd836, + 12'd1952, + 12'd1953, + 12'd1954, + 12'd1955, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, 12'd2048, 12'd2049, + 12'd2496, 12'd2816, 12'd2818, + 12'd3008, 12'd3072, 12'd3073, 12'd3074, @@ -36005,96 +47357,106 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277 = - coreFix_aluExe_1_dispToRegQ$first[130:119]; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q359 = + coreFix_aluExe_1_dispToRegQ$first[136:125]; + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q359 = 12'd2303; endcase end + always@(coreFix_aluExe_1_dispToRegQ$first) + begin + case (coreFix_aluExe_1_dispToRegQ$first[123:119]) + 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q360 = + coreFix_aluExe_1_dispToRegQ$first[123:119]; + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q360 = + 5'd10; + endcase + end always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData) begin case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q278 = + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q361 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67]; - default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q278 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q361 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData or - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q278) + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q361) begin - case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84]) + case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[95:93]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279 = - coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:66]; + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q362 = + coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[95:66]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279 = - { coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84], - 9'h0AA, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q362 = + { coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[95:93], + 18'h2AAAA, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[74:70], - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q278, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q361, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[66] }; - default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279 = - 21'd1485482; + default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q362 = + 30'd715827882; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9166 or - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10634 or - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10685 or - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10632) + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13307 or + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14787 or + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14840 or + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14785) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q280 = - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10634; + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q363 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14787; 5'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q280 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q363 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? { !coreFix_fpuMulDivExe_0_regToExeQ$first[139], coreFix_fpuMulDivExe_0_regToExeQ$first[138:76] } : - { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10685, - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10632 }; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q280 = - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9166; + { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14840, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14785 }; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q363 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13307; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10634) + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14787) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q364 = 64'h3FF0000000000000; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 = - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10634; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q364 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14787; endcase end always@(coreFix_fpuMulDivExe_0_dispToRegQ$first) begin case (coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q282 = + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q365 = coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58]; - default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q282 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q365 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_dispToRegQ$first or - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q282) + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q365) begin - case (coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75]) + case (coreFix_fpuMulDivExe_0_dispToRegQ$first[86:84]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283 = - coreFix_fpuMulDivExe_0_dispToRegQ$first[77:57]; + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q366 = + coreFix_fpuMulDivExe_0_dispToRegQ$first[86:57]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283 = - { coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75], - 9'h0AA, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q366 = + { coreFix_fpuMulDivExe_0_dispToRegQ$first[86:84], + 18'h2AAAA, coreFix_fpuMulDivExe_0_dispToRegQ$first[65:61], - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q282, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q365, coreFix_fpuMulDivExe_0_dispToRegQ$first[57] }; - default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283 = - 21'd1485482; + default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q366 = + 30'd715827882; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or @@ -36103,13 +47465,45 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q284 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q367 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[1:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q284 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q367 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[1:0]; endcase end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4871 or + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849 or + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4863) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[7:6]) + 2'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q368 = + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849; + 2'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q368 = + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4863[63:0]; + default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q368 = + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4871[63:0]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4871 or + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843 or + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4863) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[7:6]) + 2'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q369 = + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843; + 2'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q369 = + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4863[127:64]; + default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q369 = + SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4871[127:64]; + endcase + end // handling of inlined registers @@ -36118,8 +47512,9 @@ module mkCore(CLK, if (RST_N == `BSV_RESET_VALUE) begin commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY - 134'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - commitStage_rg_instret <= `BSV_ASSIGNMENT_DELAY 64'd0; + 239'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY 1'd0; + commitStage_rg_serial_num <= `BSV_ASSIGNMENT_DELAY 64'd0; coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY 4'd0; @@ -36164,9 +47559,9 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY - 583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000; + 587'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY - 583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000; + 587'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY @@ -36176,15 +47571,15 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY - 584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 588'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY 59'h2AAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY - 161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 235'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY - 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 227'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1; coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY @@ -36210,9 +47605,9 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY - 579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 583'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY - 579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 583'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY @@ -36222,7 +47617,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY - 580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY @@ -36233,31 +47628,31 @@ module mkCore(CLK, coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 5'd10; coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0; - coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0; + coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY 134'd0; + coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY 134'd0; coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY - 70'h0AAAAAAAAAAAAAAAAA; + 135'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0; - coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0; + coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY 134'd0; + coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY 134'd0; coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY - 70'h0AAAAAAAAAAAAAAAAA; + 135'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY 69'h0AAAAAAAAAAAAAAAAA; coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1; coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY - 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 227'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1; coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY @@ -36265,15 +47660,16 @@ module mkCore(CLK, coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1; coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0; + coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY 129'd0; coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY - 65'h0AAAAAAAAAAAAAAAA; + 130'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY 3'd0; csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - csrf_debug_int_pend <= `BSV_ASSIGNMENT_DELAY 1'd0; + csrf_ddc_reg <= `BSV_ASSIGNMENT_DELAY + 153'h100000000000000000000FFFF1FFFFF44000000; csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -36282,12 +47678,15 @@ module mkCore(CLK, csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY 5'd0; csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY 3'd0; - csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY 2'd0; + csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY 2'b0; csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0; + csrf_mScratchC_reg <= `BSV_ASSIGNMENT_DELAY + 153'h00000000000000000000000001FFFFF44000000; + csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY 5'd0; csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; + csrf_mccsr_reg <= `BSV_ASSIGNMENT_DELAY 11'd0; csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -36295,7 +47694,8 @@ module mkCore(CLK, csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY 3'd0; csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY 10'd0; - csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0; + csrf_mepcc_reg_data_rl <= `BSV_ASSIGNMENT_DELAY + 153'h100000000000000000000FFFF1FFFFF44000000; csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY 2'd0; csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY 3'd0; @@ -36304,21 +47704,32 @@ module mkCore(CLK, csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY 2'd0; csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0; + csrf_mtcc_reg <= `BSV_ASSIGNMENT_DELAY + 153'h100000000000000000000FFFF1FFFFF44000000; + csrf_mtdc_reg <= `BSV_ASSIGNMENT_DELAY + 153'h00000000000000000000000001FFFFF44000000; csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0; - csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0; - csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY 44'd0; csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY 2'd3; - csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0; + csrf_rg_dcsr <= `BSV_ASSIGNMENT_DELAY 64'd1073741843; + csrf_rg_dpc <= `BSV_ASSIGNMENT_DELAY + 153'h1000000001C0000000000FFFF1FFFFF44000000; + csrf_rg_tdata1_data <= `BSV_ASSIGNMENT_DELAY 59'd0; + csrf_rg_tdata1_dmode <= `BSV_ASSIGNMENT_DELAY 1'd0; + csrf_rg_tselect <= `BSV_ASSIGNMENT_DELAY 64'd0; + csrf_sScratchC_reg <= `BSV_ASSIGNMENT_DELAY + 153'h00000000000000000000000001FFFFF44000000; + csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY 5'd0; csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; - csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0; + csrf_sepcc_reg_data_rl <= `BSV_ASSIGNMENT_DELAY + 153'h100000000000000000000FFFF1FFFFF44000000; csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -36328,9 +47739,11 @@ module mkCore(CLK, csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0; csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY 1'd0; + csrf_stcc_reg <= `BSV_ASSIGNMENT_DELAY + 153'h100000000000000000000FFFF1FFFFF44000000; + csrf_stdc_reg <= `BSV_ASSIGNMENT_DELAY + 153'h00000000000000000000000001FFFFF44000000; csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0; - csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0; - csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_time_reg <= `BSV_ASSIGNMENT_DELAY 64'd0; csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -36343,15 +47756,17 @@ module mkCore(CLK, csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; + flush_brpred <= `BSV_ASSIGNMENT_DELAY 1'd0; + flush_caches <= `BSV_ASSIGNMENT_DELAY 1'd0; flush_reservation <= `BSV_ASSIGNMENT_DELAY 1'd0; flush_tlbs <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY - 142'h000000000000000004000000000000000000; + 215'h000000000000000008000000000000000000000000000000000000; mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY - 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 216'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -36366,18 +47781,18 @@ module mkCore(CLK, mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY - 142'h000000000000000004000000000000000000; + 215'h000000000000000008000000000000000000000000000000000000; mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY - 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 216'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0; + mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY 130'd0; mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY - 66'h0AAAAAAAAAAAAAAAA; + 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0; mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -36387,13 +47802,17 @@ module mkCore(CLK, mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 40'h2AAAAAAAAA; mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 67'h155555554AAAAAAAA; + mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY + 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA; mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 68'h2AAAAAAAAAAAAAAAA; + mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY + 132'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0; outOfReset <= `BSV_ASSIGNMENT_DELAY 1'd0; + renameStage_rg_m_halt_req <= `BSV_ASSIGNMENT_DELAY 5'd10; + rg_core_run_state <= `BSV_ASSIGNMENT_DELAY 2'd2; started <= `BSV_ASSIGNMENT_DELAY 1'd0; update_vm_info <= `BSV_ASSIGNMENT_DELAY 1'd0; end @@ -36402,9 +47821,12 @@ module mkCore(CLK, if (commitStage_commitTrap$EN) commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY commitStage_commitTrap$D_IN; - if (commitStage_rg_instret$EN) - commitStage_rg_instret <= `BSV_ASSIGNMENT_DELAY - commitStage_rg_instret$D_IN; + if (commitStage_rg_run_state$EN) + commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY + commitStage_rg_run_state$D_IN; + if (commitStage_rg_serial_num$EN) + commitStage_rg_serial_num <= `BSV_ASSIGNMENT_DELAY + commitStage_rg_serial_num$D_IN; if (coreFix_doStatsReg$EN) coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY coreFix_doStatsReg$D_IN; if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN) @@ -36686,9 +48108,8 @@ module mkCore(CLK, if (csrInstOrInterruptInflight_rl$EN) csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY csrInstOrInterruptInflight_rl$D_IN; - if (csrf_debug_int_pend$EN) - csrf_debug_int_pend <= `BSV_ASSIGNMENT_DELAY - csrf_debug_int_pend$D_IN; + if (csrf_ddc_reg$EN) + csrf_ddc_reg <= `BSV_ASSIGNMENT_DELAY csrf_ddc_reg$D_IN; if (csrf_external_int_en_vec_0$EN) csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_external_int_en_vec_0$D_IN; @@ -36719,12 +48140,16 @@ module mkCore(CLK, csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_1$D_IN; if (csrf_ie_vec_3$EN) csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_3$D_IN; + if (csrf_mScratchC_reg$EN) + csrf_mScratchC_reg <= `BSV_ASSIGNMENT_DELAY csrf_mScratchC_reg$D_IN; if (csrf_mcause_code_reg$EN) csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY csrf_mcause_code_reg$D_IN; if (csrf_mcause_interrupt_reg$EN) csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY csrf_mcause_interrupt_reg$D_IN; + if (csrf_mccsr_reg$EN) + csrf_mccsr_reg <= `BSV_ASSIGNMENT_DELAY csrf_mccsr_reg$D_IN; if (csrf_mcounteren_cy_reg$EN) csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY csrf_mcounteren_cy_reg$D_IN; @@ -36746,8 +48171,9 @@ module mkCore(CLK, if (csrf_medeleg_9_0_reg$EN) csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY csrf_medeleg_9_0_reg$D_IN; - if (csrf_mepc_csr$EN) - csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_mepc_csr$D_IN; + if (csrf_mepcc_reg_data_rl$EN) + csrf_mepcc_reg_data_rl <= `BSV_ASSIGNMENT_DELAY + csrf_mepcc_reg_data_rl$D_IN; if (csrf_mideleg_11_reg$EN) csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY csrf_mideleg_11_reg$D_IN; @@ -36769,14 +48195,12 @@ module mkCore(CLK, csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY csrf_mprv_reg$D_IN; if (csrf_mscratch_csr$EN) csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_mscratch_csr$D_IN; + if (csrf_mtcc_reg$EN) + csrf_mtcc_reg <= `BSV_ASSIGNMENT_DELAY csrf_mtcc_reg$D_IN; + if (csrf_mtdc_reg$EN) + csrf_mtdc_reg <= `BSV_ASSIGNMENT_DELAY csrf_mtdc_reg$D_IN; if (csrf_mtval_csr$EN) csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY csrf_mtval_csr$D_IN; - if (csrf_mtvec_base_hi_reg$EN) - csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY - csrf_mtvec_base_hi_reg$D_IN; - if (csrf_mtvec_mode_low_reg$EN) - csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY - csrf_mtvec_mode_low_reg$D_IN; if (csrf_mxr_reg$EN) csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY csrf_mxr_reg$D_IN; if (csrf_ppn_reg$EN) @@ -36789,6 +48213,20 @@ module mkCore(CLK, csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_3$D_IN; if (csrf_prv_reg$EN) csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY csrf_prv_reg$D_IN; + if (csrf_rg_dcsr$EN) + csrf_rg_dcsr <= `BSV_ASSIGNMENT_DELAY csrf_rg_dcsr$D_IN; + if (csrf_rg_dpc$EN) + csrf_rg_dpc <= `BSV_ASSIGNMENT_DELAY csrf_rg_dpc$D_IN; + if (csrf_rg_tdata1_data$EN) + csrf_rg_tdata1_data <= `BSV_ASSIGNMENT_DELAY + csrf_rg_tdata1_data$D_IN; + if (csrf_rg_tdata1_dmode$EN) + csrf_rg_tdata1_dmode <= `BSV_ASSIGNMENT_DELAY + csrf_rg_tdata1_dmode$D_IN; + if (csrf_rg_tselect$EN) + csrf_rg_tselect <= `BSV_ASSIGNMENT_DELAY csrf_rg_tselect$D_IN; + if (csrf_sScratchC_reg$EN) + csrf_sScratchC_reg <= `BSV_ASSIGNMENT_DELAY csrf_sScratchC_reg$D_IN; if (csrf_scause_code_reg$EN) csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY csrf_scause_code_reg$D_IN; @@ -36804,8 +48242,9 @@ module mkCore(CLK, if (csrf_scounteren_tm_reg$EN) csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY csrf_scounteren_tm_reg$D_IN; - if (csrf_sepc_csr$EN) - csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_sepc_csr$D_IN; + if (csrf_sepcc_reg_data_rl$EN) + csrf_sepcc_reg_data_rl <= `BSV_ASSIGNMENT_DELAY + csrf_sepcc_reg_data_rl$D_IN; if (csrf_software_int_en_vec_0$EN) csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_software_int_en_vec_0$D_IN; @@ -36831,14 +48270,12 @@ module mkCore(CLK, if (csrf_stats_module_doStats$EN) csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY csrf_stats_module_doStats$D_IN; + if (csrf_stcc_reg$EN) + csrf_stcc_reg <= `BSV_ASSIGNMENT_DELAY csrf_stcc_reg$D_IN; + if (csrf_stdc_reg$EN) + csrf_stdc_reg <= `BSV_ASSIGNMENT_DELAY csrf_stdc_reg$D_IN; if (csrf_stval_csr$EN) csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY csrf_stval_csr$D_IN; - if (csrf_stvec_base_hi_reg$EN) - csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY - csrf_stvec_base_hi_reg$D_IN; - if (csrf_stvec_mode_low_reg$EN) - csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY - csrf_stvec_mode_low_reg$D_IN; if (csrf_sum_reg$EN) csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY csrf_sum_reg$D_IN; if (csrf_time_reg$EN) @@ -36870,6 +48307,10 @@ module mkCore(CLK, if (csrf_vm_mode_sv39_reg$EN) csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY csrf_vm_mode_sv39_reg$D_IN; + if (flush_brpred$EN) + flush_brpred <= `BSV_ASSIGNMENT_DELAY flush_brpred$D_IN; + if (flush_caches$EN) + flush_caches <= `BSV_ASSIGNMENT_DELAY flush_caches$D_IN; if (flush_reservation$EN) flush_reservation <= `BSV_ASSIGNMENT_DELAY flush_reservation$D_IN; if (flush_tlbs$EN) @@ -36990,10 +48431,23 @@ module mkCore(CLK, mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_toHostAddr$D_IN; if (outOfReset$EN) outOfReset <= `BSV_ASSIGNMENT_DELAY outOfReset$D_IN; + if (renameStage_rg_m_halt_req$EN) + renameStage_rg_m_halt_req <= `BSV_ASSIGNMENT_DELAY + renameStage_rg_m_halt_req$D_IN; + if (rg_core_run_state$EN) + rg_core_run_state <= `BSV_ASSIGNMENT_DELAY rg_core_run_state$D_IN; if (started$EN) started <= `BSV_ASSIGNMENT_DELAY started$D_IN; if (update_vm_info$EN) update_vm_info <= `BSV_ASSIGNMENT_DELAY update_vm_info$D_IN; end + if (csrf_rg_dscratch0$EN) + csrf_rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY csrf_rg_dscratch0$D_IN; + if (csrf_rg_dscratch1$EN) + csrf_rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY csrf_rg_dscratch1$D_IN; + if (csrf_rg_tdata2$EN) + csrf_rg_tdata2 <= `BSV_ASSIGNMENT_DELAY csrf_rg_tdata2$D_IN; + if (csrf_rg_tdata3$EN) + csrf_rg_tdata3 <= `BSV_ASSIGNMENT_DELAY csrf_rg_tdata3$D_IN; end // synopsys translate_off @@ -37001,8 +48455,10 @@ module mkCore(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - commitStage_commitTrap = 134'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - commitStage_rg_instret = 64'hAAAAAAAAAAAAAAAA; + commitStage_commitTrap = + 239'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + commitStage_rg_run_state = 1'h0; + commitStage_rg_serial_num = 64'hAAAAAAAAAAAAAAAA; coreFix_doStatsReg = 1'h0; coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt = 4'hA; coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init = 1'h0; @@ -37026,21 +48482,21 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 = - 583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 587'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 = - 583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 587'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl = - 584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 588'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl = 59'h2AAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_processAmo = - 161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 235'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl = - 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 227'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl = 1'h0; @@ -37057,15 +48513,15 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 = - 579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 = - 579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP = 1'h0; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl = - 580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full = 1'h0; coreFix_memExe_dMem_perfReqQ_clearReq_rl = 1'h0; coreFix_memExe_dMem_perfReqQ_data_0 = 4'hA; @@ -37074,42 +48530,48 @@ module mkCore(CLK, coreFix_memExe_dMem_perfReqQ_enqReq_rl = 5'h0A; coreFix_memExe_dMem_perfReqQ_full = 1'h0; coreFix_memExe_forwardQ_clearReq_rl = 1'h0; - coreFix_memExe_forwardQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA; - coreFix_memExe_forwardQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA; + coreFix_memExe_forwardQ_data_0 = 134'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + coreFix_memExe_forwardQ_data_1 = 134'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_forwardQ_deqP = 1'h0; coreFix_memExe_forwardQ_deqReq_rl = 1'h0; coreFix_memExe_forwardQ_empty = 1'h0; coreFix_memExe_forwardQ_enqP = 1'h0; - coreFix_memExe_forwardQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA; + coreFix_memExe_forwardQ_enqReq_rl = + 135'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_forwardQ_full = 1'h0; coreFix_memExe_memRespLdQ_clearReq_rl = 1'h0; - coreFix_memExe_memRespLdQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA; - coreFix_memExe_memRespLdQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA; + coreFix_memExe_memRespLdQ_data_0 = + 134'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + coreFix_memExe_memRespLdQ_data_1 = + 134'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_memRespLdQ_deqP = 1'h0; coreFix_memExe_memRespLdQ_deqReq_rl = 1'h0; coreFix_memExe_memRespLdQ_empty = 1'h0; coreFix_memExe_memRespLdQ_enqP = 1'h0; - coreFix_memExe_memRespLdQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA; + coreFix_memExe_memRespLdQ_enqReq_rl = + 135'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_memRespLdQ_full = 1'h0; coreFix_memExe_reqLdQ_data_0_rl = 69'h0AAAAAAAAAAAAAAAAA; coreFix_memExe_reqLdQ_empty_rl = 1'h0; coreFix_memExe_reqLdQ_full_rl = 1'h0; coreFix_memExe_reqLrScAmoQ_data_0_rl = - 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 227'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_reqLrScAmoQ_empty_rl = 1'h0; coreFix_memExe_reqLrScAmoQ_full_rl = 1'h0; coreFix_memExe_reqStQ_data_0_rl = 66'h2AAAAAAAAAAAAAAAA; coreFix_memExe_reqStQ_empty_rl = 1'h0; coreFix_memExe_reqStQ_full_rl = 1'h0; coreFix_memExe_respLrScAmoQ_clearReq_rl = 1'h0; - coreFix_memExe_respLrScAmoQ_data_0 = 64'hAAAAAAAAAAAAAAAA; + coreFix_memExe_respLrScAmoQ_data_0 = + 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_respLrScAmoQ_deqReq_rl = 1'h0; coreFix_memExe_respLrScAmoQ_empty = 1'h0; - coreFix_memExe_respLrScAmoQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA; + coreFix_memExe_respLrScAmoQ_enqReq_rl = + 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; coreFix_memExe_respLrScAmoQ_full = 1'h0; coreFix_memExe_waitLrScAmoMMIOResp = 3'h2; csrInstOrInterruptInflight_rl = 1'h0; - csrf_debug_int_pend = 1'h0; + csrf_ddc_reg = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; csrf_external_int_en_vec_0 = 1'h0; csrf_external_int_en_vec_1 = 1'h0; csrf_external_int_en_vec_3 = 1'h0; @@ -37122,8 +48584,10 @@ module mkCore(CLK, csrf_ie_vec_0 = 1'h0; csrf_ie_vec_1 = 1'h0; csrf_ie_vec_3 = 1'h0; - csrf_mcause_code_reg = 4'hA; + csrf_mScratchC_reg = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + csrf_mcause_code_reg = 5'h0A; csrf_mcause_interrupt_reg = 1'h0; + csrf_mccsr_reg = 11'h2AA; csrf_mcounteren_cy_reg = 1'h0; csrf_mcounteren_ir_reg = 1'h0; csrf_mcounteren_tm_reg = 1'h0; @@ -37131,7 +48595,7 @@ module mkCore(CLK, csrf_medeleg_13_11_reg = 3'h2; csrf_medeleg_15_reg = 1'h0; csrf_medeleg_9_0_reg = 10'h2AA; - csrf_mepc_csr = 64'hAAAAAAAAAAAAAAAA; + csrf_mepcc_reg_data_rl = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; csrf_mideleg_11_reg = 1'h0; csrf_mideleg_1_0_reg = 2'h2; csrf_mideleg_5_3_reg = 3'h2; @@ -37140,21 +48604,31 @@ module mkCore(CLK, csrf_mpp_reg = 2'h2; csrf_mprv_reg = 1'h0; csrf_mscratch_csr = 64'hAAAAAAAAAAAAAAAA; + csrf_mtcc_reg = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + csrf_mtdc_reg = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; csrf_mtval_csr = 64'hAAAAAAAAAAAAAAAA; - csrf_mtvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA; - csrf_mtvec_mode_low_reg = 1'h0; csrf_mxr_reg = 1'h0; csrf_ppn_reg = 44'hAAAAAAAAAAA; csrf_prev_ie_vec_0 = 1'h0; csrf_prev_ie_vec_1 = 1'h0; csrf_prev_ie_vec_3 = 1'h0; csrf_prv_reg = 2'h2; - csrf_scause_code_reg = 4'hA; + csrf_rg_dcsr = 64'hAAAAAAAAAAAAAAAA; + csrf_rg_dpc = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + csrf_rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA; + csrf_rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA; + csrf_rg_tdata1_data = 59'h2AAAAAAAAAAAAAA; + csrf_rg_tdata1_dmode = 1'h0; + csrf_rg_tdata2 = 64'hAAAAAAAAAAAAAAAA; + csrf_rg_tdata3 = 64'hAAAAAAAAAAAAAAAA; + csrf_rg_tselect = 64'hAAAAAAAAAAAAAAAA; + csrf_sScratchC_reg = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + csrf_scause_code_reg = 5'h0A; csrf_scause_interrupt_reg = 1'h0; csrf_scounteren_cy_reg = 1'h0; csrf_scounteren_ir_reg = 1'h0; csrf_scounteren_tm_reg = 1'h0; - csrf_sepc_csr = 64'hAAAAAAAAAAAAAAAA; + csrf_sepcc_reg_data_rl = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; csrf_software_int_en_vec_0 = 1'h0; csrf_software_int_en_vec_1 = 1'h0; csrf_software_int_en_vec_3 = 1'h0; @@ -37164,9 +48638,9 @@ module mkCore(CLK, csrf_spp_reg = 1'h0; csrf_sscratch_csr = 64'hAAAAAAAAAAAAAAAA; csrf_stats_module_doStats = 1'h0; + csrf_stcc_reg = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + csrf_stdc_reg = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; csrf_stval_csr = 64'hAAAAAAAAAAAAAAAA; - csrf_stvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA; - csrf_stvec_mode_low_reg = 1'h0; csrf_sum_reg = 1'h0; csrf_time_reg = 64'hAAAAAAAAAAAAAAAA; csrf_timer_int_en_vec_0 = 1'h0; @@ -37179,13 +48653,17 @@ module mkCore(CLK, csrf_tvm_reg = 1'h0; csrf_tw_reg = 1'h0; csrf_vm_mode_sv39_reg = 1'h0; + flush_brpred = 1'h0; + flush_caches = 1'h0; flush_reservation = 1'h0; flush_tlbs = 1'h0; mmio_cRqQ_clearReq_rl = 1'h0; - mmio_cRqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + mmio_cRqQ_data_0 = + 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmio_cRqQ_deqReq_rl = 1'h0; mmio_cRqQ_empty = 1'h0; - mmio_cRqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + mmio_cRqQ_enqReq_rl = + 216'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmio_cRqQ_full = 1'h0; mmio_cRsQ_clearReq_rl = 1'h0; mmio_cRsQ_data_0 = 1'h0; @@ -37199,16 +48677,18 @@ module mkCore(CLK, mmio_dataPendQ_enqReq_rl = 1'h0; mmio_dataPendQ_full = 1'h0; mmio_dataReqQ_clearReq_rl = 1'h0; - mmio_dataReqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + mmio_dataReqQ_data_0 = + 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmio_dataReqQ_deqReq_rl = 1'h0; mmio_dataReqQ_empty = 1'h0; - mmio_dataReqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + mmio_dataReqQ_enqReq_rl = + 216'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmio_dataReqQ_full = 1'h0; mmio_dataRespQ_clearReq_rl = 1'h0; - mmio_dataRespQ_data_0 = 65'h0AAAAAAAAAAAAAAAA; + mmio_dataRespQ_data_0 = 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmio_dataRespQ_deqReq_rl = 1'h0; mmio_dataRespQ_empty = 1'h0; - mmio_dataRespQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA; + mmio_dataRespQ_enqReq_rl = 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmio_dataRespQ_full = 1'h0; mmio_fromHostAddr = 61'h0AAAAAAAAAAAAAAA; mmio_pRqQ_clearReq_rl = 1'h0; @@ -37218,13 +48698,15 @@ module mkCore(CLK, mmio_pRqQ_enqReq_rl = 40'hAAAAAAAAAA; mmio_pRqQ_full = 1'h0; mmio_pRsQ_clearReq_rl = 1'h0; - mmio_pRsQ_data_0 = 67'h2AAAAAAAAAAAAAAAA; + mmio_pRsQ_data_0 = 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmio_pRsQ_deqReq_rl = 1'h0; mmio_pRsQ_empty = 1'h0; - mmio_pRsQ_enqReq_rl = 68'hAAAAAAAAAAAAAAAAA; + mmio_pRsQ_enqReq_rl = 132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmio_pRsQ_full = 1'h0; mmio_toHostAddr = 61'h0AAAAAAAAAAAAAAA; outOfReset = 1'h0; + renameStage_rg_m_halt_req = 5'h0A; + rg_core_run_state = 2'h2; started = 1'h0; update_vm_info = 1'h0; end @@ -37240,120 +48722,3997 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_outOfReset) $fwrite(32'h80000002, "mkProc came out of reset\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd2048) + $display("[Terminate CSR] being written (val = %x), ", + "send terminate signal to host", + f_csr_reqs$D_OUT[63:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write("[doDeqLdQ_fault] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write("LdQDeqEntry { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write("'h%h", coreFix_memExe_lsq$firstLd[143:139]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write(", ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write("'h%h", coreFix_memExe_lsq$firstLd[138]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write("'h%h", coreFix_memExe_lsq$firstLd[137:133]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write("'h%h", coreFix_memExe_lsq$firstLd[132:127], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[126]) + $write("Lr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !coreFix_memExe_lsq$firstLd[126]) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write(", ", "unsignedLd: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[109]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !coreFix_memExe_lsq$firstLd[109]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[108]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !coreFix_memExe_lsq$firstLd[108]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[107]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !coreFix_memExe_lsq$firstLd[107]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[106]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !coreFix_memExe_lsq$firstLd[106]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[106]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[106]) + $write("'h%h", coreFix_memExe_lsq$firstLd[105:99]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[106]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[106] && + coreFix_memExe_lsq$firstLd[98]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[106] && + !coreFix_memExe_lsq$firstLd[98]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[106]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write("'h%h", coreFix_memExe_lsq$firstLd[97:34]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[33]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !coreFix_memExe_lsq$firstLd[33]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write("tagged CapException "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1) + $write("tagged Exception "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1) + $write("tagged Interrupt "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd0) + $write("UserSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd1) + $write("SupervisorSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd3) + $write("MachineSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd4) + $write("UserTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd5) + $write("SupervisorTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd7) + $write("MachineTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd8) + $write("UserExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd9) + $write("SupervisorExternel"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd11) + $write("MachineExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd14) + $write("DebugHalt"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd0 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd1 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd3 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd4 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd5 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd7 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd8 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd9 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd11 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd14) + $write("DebugStep"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd0) + $write("InstAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd1) + $write("InstAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd2) + $write("IllegalInst"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd3) + $write("Breakpoint"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd4) + $write("LoadAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd5) + $write("LoadAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd6) + $write("StoreAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd7) + $write("StoreAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd8) + $write("EnvCallU"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd9) + $write("EnvCallS"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd11) + $write("EnvCallM"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd12) + $write("InstPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd13) + $write("LoadPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd15) + $write("StorePageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd0 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd1 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd2 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd3 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd4 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd5 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd6 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd7 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd8 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd9 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd11 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd12 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd13 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd15) + $write("CHERIFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write("CSR_XCapCause { ", "cheri_exc_reg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write("'h%h", coreFix_memExe_lsq$firstLd[13:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(", ", "cheri_exc_code: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd0) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd1) + $write("LengthViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd2) + $write("TagViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd3) + $write("SealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd4) + $write("TypeViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd5) + $write("CallTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd6) + $write("ReturnTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd7) + $write("StackUnderflow"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd8) + $write("SoftwarePermViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd9) + $write("MMUStoreCapProhibit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd10) + $write("RepresentViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd11) + $write("UnalignedBase"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd16) + $write("GlobalViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd17) + $write("PermitXViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd18) + $write("PermitRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd19) + $write("PermitWViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd20) + $write("PermitRCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd21) + $write("PermitWCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd22) + $write("PermitWLocalCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd23) + $write("PermitSealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd24) + $write("PermitASRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd25) + $write("PermitCCallViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd26) + $write("PermitUnsealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd0 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd1 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd2 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd3 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd4 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd5 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd6 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd7 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd8 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd9 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd10 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd11 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd16 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd17 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd18 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd19 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd20 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd21 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd22 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd23 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd24 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd25 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd26) + $write("PermitSetCIDViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) + $write(", ", "killed: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[2]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !coreFix_memExe_lsq$firstLd[2]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd0) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd1) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] != 2'd0 && + coreFix_memExe_lsq$firstLd[1:0] != 2'd1) + $write("Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault && + !coreFix_memExe_lsq$firstLd[2]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write("[doDeqLdQ_Ld] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write("LdQDeqEntry { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write("'h%h", coreFix_memExe_lsq$firstLd[143:139]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write(", ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write("'h%h", coreFix_memExe_lsq$firstLd[138]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write("'h%h", coreFix_memExe_lsq$firstLd[137:133]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write("'h%h", coreFix_memExe_lsq$firstLd[132:127], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write(", ", "unsignedLd: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[109]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !coreFix_memExe_lsq$firstLd[109]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[108]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !coreFix_memExe_lsq$firstLd[108]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[107]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !coreFix_memExe_lsq$firstLd[107]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[106]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !coreFix_memExe_lsq$firstLd[106]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[106]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[106]) + $write("'h%h", coreFix_memExe_lsq$firstLd[105:99]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[106]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[106] && + coreFix_memExe_lsq$firstLd[98]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[106] && + !coreFix_memExe_lsq$firstLd[98]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[106]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write("'h%h", coreFix_memExe_lsq$firstLd[97:34]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) + $write(", ", "killed: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[2]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !coreFix_memExe_lsq$firstLd[2]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd0) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd1) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] != 2'd0 && + coreFix_memExe_lsq$firstLd[1:0] != 2'd1) + $write("Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !coreFix_memExe_lsq$firstLd[2]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write("[doDeqLdQ_Lr_issue] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write("LdQDeqEntry { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write("'h%h", coreFix_memExe_lsq$firstLd[143:139]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write("'h%h", coreFix_memExe_lsq$firstLd[138]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write("'h%h", coreFix_memExe_lsq$firstLd[137:133]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write("'h%h", coreFix_memExe_lsq$firstLd[132:127], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write("Lr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "unsignedLd: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[109]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + !coreFix_memExe_lsq$firstLd[109]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[108]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + !coreFix_memExe_lsq$firstLd[108]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[107]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + !coreFix_memExe_lsq$firstLd[107]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[106]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + !coreFix_memExe_lsq$firstLd[106]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[106]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[106]) + $write("'h%h", coreFix_memExe_lsq$firstLd[105:99]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[106]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[106] && + coreFix_memExe_lsq$firstLd[98]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[106] && + !coreFix_memExe_lsq$firstLd[98]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[106]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write("'h%h", coreFix_memExe_lsq$firstLd[97:34]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "killed: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[2]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + !coreFix_memExe_lsq$firstLd[2]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd0) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd1) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] != 2'd0 && + coreFix_memExe_lsq$firstLd[1:0] != 2'd1) + $write("Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue && + !coreFix_memExe_lsq$firstLd[2]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write("ProcRq { ", "id: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write("'h%h", 5'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "addr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write("'h%h", coreFix_memExe_lsq$firstLd[97:34]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "toState: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write("E"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(", ", "op: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write("Lr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "amoInst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write("AmoInst { ", "func: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) + $write(", ", "width: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(", ", "aq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(", ", "rl: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write("[doDeqLdQ_MMIO_issue] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write("LdQDeqEntry { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write("'h%h", coreFix_memExe_lsq$firstLd[143:139]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write("'h%h", coreFix_memExe_lsq$firstLd[138]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write("'h%h", coreFix_memExe_lsq$firstLd[137:133]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write("'h%h", coreFix_memExe_lsq$firstLd[132:127], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[126]) + $write("Lr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + !coreFix_memExe_lsq$firstLd[126]) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "unsignedLd: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[109]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + !coreFix_memExe_lsq$firstLd[109]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[108]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + !coreFix_memExe_lsq$firstLd[108]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[107]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + !coreFix_memExe_lsq$firstLd[107]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[106]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + !coreFix_memExe_lsq$firstLd[106]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[106]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[106]) + $write("'h%h", coreFix_memExe_lsq$firstLd[105:99]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[106]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[106] && + coreFix_memExe_lsq$firstLd[98]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[106] && + !coreFix_memExe_lsq$firstLd[98]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[106]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write("'h%h", coreFix_memExe_lsq$firstLd[97:34]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "killed: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[2]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + !coreFix_memExe_lsq$firstLd[2]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd0) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd1) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] != 2'd0 && + coreFix_memExe_lsq$firstLd[1:0] != 2'd1) + $write("Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && + !coreFix_memExe_lsq$firstLd[2]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write("MMIOCRq { ", "addr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write("'h%h", coreFix_memExe_lsq$firstLd[97:34]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "func: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write("tagged Ld ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write("[doDeqLdQ_MMIO_fault] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write("LdQDeqEntry { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write("'h%h", coreFix_memExe_lsq$firstLd[143:139]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write("'h%h", coreFix_memExe_lsq$firstLd[138]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write("'h%h", coreFix_memExe_lsq$firstLd[137:133]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write("'h%h", coreFix_memExe_lsq$firstLd[132:127], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[126]) + $write("Lr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[126]) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "unsignedLd: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[109]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[109]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[108]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[108]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[107]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[107]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[106]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[106]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[106]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[106]) + $write("'h%h", coreFix_memExe_lsq$firstLd[105:99]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[106]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[106] && + coreFix_memExe_lsq$firstLd[98]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[106] && + !coreFix_memExe_lsq$firstLd[98]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[106]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write("'h%h", coreFix_memExe_lsq$firstLd[97:34]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[33]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[33]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[16]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write("tagged CapException "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1) + $write("tagged Exception "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1) + $write("tagged Interrupt "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd0) + $write("UserSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd1) + $write("SupervisorSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd3) + $write("MachineSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd4) + $write("UserTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd5) + $write("SupervisorTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd7) + $write("MachineTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd8) + $write("UserExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd9) + $write("SupervisorExternel"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd11) + $write("MachineExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd14) + $write("DebugHalt"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd0 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd1 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd3 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd4 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd5 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd7 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd8 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd9 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd11 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd14) + $write("DebugStep"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd0) + $write("InstAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd1) + $write("InstAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd2) + $write("IllegalInst"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd3) + $write("Breakpoint"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd4) + $write("LoadAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd5) + $write("LoadAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd6) + $write("StoreAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd7) + $write("StoreAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd8) + $write("EnvCallU"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd9) + $write("EnvCallS"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd11) + $write("EnvCallM"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd12) + $write("InstPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd13) + $write("LoadPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd15) + $write("StorePageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd0 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd1 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd2 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd3 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd4 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd5 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd6 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd7 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd8 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd9 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd11 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd12 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd13 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd15) + $write("CHERIFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write("CSR_XCapCause { ", "cheri_exc_reg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write("'h%h", coreFix_memExe_lsq$firstLd[13:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(", ", "cheri_exc_code: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd0) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd1) + $write("LengthViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd2) + $write("TagViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd3) + $write("SealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd4) + $write("TypeViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd5) + $write("CallTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd6) + $write("ReturnTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd7) + $write("StackUnderflow"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd8) + $write("SoftwarePermViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd9) + $write("MMUStoreCapProhibit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd10) + $write("RepresentViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd11) + $write("UnalignedBase"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd16) + $write("GlobalViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd17) + $write("PermitXViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd18) + $write("PermitRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd19) + $write("PermitWViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd20) + $write("PermitRCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd21) + $write("PermitWCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd22) + $write("PermitWLocalCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd23) + $write("PermitSealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd24) + $write("PermitASRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd25) + $write("PermitCCallViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd26) + $write("PermitUnsealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd0 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd1 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd2 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd3 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd4 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd5 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd6 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd7 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd8 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd9 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd10 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd11 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd16 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd17 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd18 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd19 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd20 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd21 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd22 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd23 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd24 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd25 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd26) + $write("PermitSetCIDViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) + $write(", ", "killed: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[2]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[2]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd0) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd1) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] != 2'd0 && + coreFix_memExe_lsq$firstLd[1:0] != 2'd1) + $write("Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !coreFix_memExe_lsq$firstLd[2]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) + $write("[Lr/Sc/Amo resp] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) + $write("'h%h", + coreFix_memExe_dMem_cache_m_banks_0_processAmo[230:226]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo && + (coreFix_memExe_dMem_cache_m_banks_0_processAmo[7:6] != 2'd0 || + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4882)) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo && + coreFix_memExe_dMem_cache_m_banks_0_processAmo[7:6] == 2'd0 && + !SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4882) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) + $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush) $write("instret:%0d PC:0x%0h instr:0x%08h", - commitStage_rg_instret, - rob$deqPort_0_deq_data[282:219], - rob$deqPort_0_deq_data[218:187], + commitStage_rg_serial_num, + rob$deqPort_0_deq_data[630:502], + rob$deqPort_0_deq_data[501:470], " iType:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd0) + rob$deqPort_0_deq_data[469:465] == 5'd0) $write("Unsupported"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd1) + rob$deqPort_0_deq_data[469:465] == 5'd1) $write("Nop"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd2) + rob$deqPort_0_deq_data[469:465] == 5'd2) $write("Amo"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd3) + rob$deqPort_0_deq_data[469:465] == 5'd3) $write("Alu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd4) + rob$deqPort_0_deq_data[469:465] == 5'd4) $write("Ld"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd5) + rob$deqPort_0_deq_data[469:465] == 5'd5) $write("St"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd6) + rob$deqPort_0_deq_data[469:465] == 5'd6) $write("Lr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd7) + rob$deqPort_0_deq_data[469:465] == 5'd7) $write("Sc"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd8) + rob$deqPort_0_deq_data[469:465] == 5'd8) $write("J"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd9) + rob$deqPort_0_deq_data[469:465] == 5'd9) $write("Jr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd10) + rob$deqPort_0_deq_data[469:465] == 5'd10) $write("Br"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd11) + rob$deqPort_0_deq_data[469:465] == 5'd11) + $write("CCall"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && + rob$deqPort_0_deq_data[469:465] == 5'd12) + $write("CJALR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && + rob$deqPort_0_deq_data[469:465] == 5'd13) + $write("Cap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && + rob$deqPort_0_deq_data[469:465] == 5'd14) $write("Auipc"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd12) + rob$deqPort_0_deq_data[469:465] == 5'd15) + $write("Auipcc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && + rob$deqPort_0_deq_data[469:465] == 5'd16) $write("Fpu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd13) + rob$deqPort_0_deq_data[469:465] == 5'd17) $write("Csr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd14) + rob$deqPort_0_deq_data[469:465] == 5'd18) + $write("Scr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && + rob$deqPort_0_deq_data[469:465] == 5'd19) $write("Fence"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd15) + rob$deqPort_0_deq_data[469:465] == 5'd20) $write("FenceI"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd16) + rob$deqPort_0_deq_data[469:465] == 5'd21) $write("SFence"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd17) + rob$deqPort_0_deq_data[469:465] == 5'd22) $write("Ecall"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd18) + rob$deqPort_0_deq_data[469:465] == 5'd23) $write("Ebreak"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd19) + rob$deqPort_0_deq_data[469:465] == 5'd24) $write("Sret"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] == 5'd20) + rob$deqPort_0_deq_data[469:465] == 5'd25) $write("Mret"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && - rob$deqPort_0_deq_data[186:182] != 5'd0 && - rob$deqPort_0_deq_data[186:182] != 5'd1 && - rob$deqPort_0_deq_data[186:182] != 5'd2 && - rob$deqPort_0_deq_data[186:182] != 5'd3 && - rob$deqPort_0_deq_data[186:182] != 5'd4 && - rob$deqPort_0_deq_data[186:182] != 5'd5 && - rob$deqPort_0_deq_data[186:182] != 5'd6 && - rob$deqPort_0_deq_data[186:182] != 5'd7 && - rob$deqPort_0_deq_data[186:182] != 5'd8 && - rob$deqPort_0_deq_data[186:182] != 5'd9 && - rob$deqPort_0_deq_data[186:182] != 5'd10 && - rob$deqPort_0_deq_data[186:182] != 5'd11 && - rob$deqPort_0_deq_data[186:182] != 5'd12 && - rob$deqPort_0_deq_data[186:182] != 5'd13 && - rob$deqPort_0_deq_data[186:182] != 5'd14 && - rob$deqPort_0_deq_data[186:182] != 5'd15 && - rob$deqPort_0_deq_data[186:182] != 5'd16 && - rob$deqPort_0_deq_data[186:182] != 5'd17 && - rob$deqPort_0_deq_data[186:182] != 5'd18 && - rob$deqPort_0_deq_data[186:182] != 5'd19 && - rob$deqPort_0_deq_data[186:182] != 5'd20) + rob$deqPort_0_deq_data[469:465] != 5'd0 && + rob$deqPort_0_deq_data[469:465] != 5'd1 && + rob$deqPort_0_deq_data[469:465] != 5'd2 && + rob$deqPort_0_deq_data[469:465] != 5'd3 && + rob$deqPort_0_deq_data[469:465] != 5'd4 && + rob$deqPort_0_deq_data[469:465] != 5'd5 && + rob$deqPort_0_deq_data[469:465] != 5'd6 && + rob$deqPort_0_deq_data[469:465] != 5'd7 && + rob$deqPort_0_deq_data[469:465] != 5'd8 && + rob$deqPort_0_deq_data[469:465] != 5'd9 && + rob$deqPort_0_deq_data[469:465] != 5'd10 && + rob$deqPort_0_deq_data[469:465] != 5'd11 && + rob$deqPort_0_deq_data[469:465] != 5'd12 && + rob$deqPort_0_deq_data[469:465] != 5'd13 && + rob$deqPort_0_deq_data[469:465] != 5'd14 && + rob$deqPort_0_deq_data[469:465] != 5'd15 && + rob$deqPort_0_deq_data[469:465] != 5'd16 && + rob$deqPort_0_deq_data[469:465] != 5'd17 && + rob$deqPort_0_deq_data[469:465] != 5'd18 && + rob$deqPort_0_deq_data[469:465] != 5'd19 && + rob$deqPort_0_deq_data[469:465] != 5'd20 && + rob$deqPort_0_deq_data[469:465] != 5'd21 && + rob$deqPort_0_deq_data[469:465] != 5'd22 && + rob$deqPort_0_deq_data[469:465] != 5'd23 && + rob$deqPort_0_deq_data[469:465] != 5'd24 && + rob$deqPort_0_deq_data[469:465] != 5'd25) $write("Interrupt"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush) @@ -37361,216 +52720,265 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst) $write("instret:%0d PC:0x%0h instr:0x%08h", - commitStage_rg_instret, - rob$deqPort_0_deq_data[282:219], - rob$deqPort_0_deq_data[218:187], + commitStage_rg_serial_num, + rob$deqPort_0_deq_data[630:502], + rob$deqPort_0_deq_data[501:470], " iType:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd0) + rob$deqPort_0_deq_data[469:465] == 5'd0) $write("Unsupported"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd1) + rob$deqPort_0_deq_data[469:465] == 5'd1) $write("Nop"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd2) + rob$deqPort_0_deq_data[469:465] == 5'd2) $write("Amo"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd3) + rob$deqPort_0_deq_data[469:465] == 5'd3) $write("Alu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd4) + rob$deqPort_0_deq_data[469:465] == 5'd4) $write("Ld"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd5) + rob$deqPort_0_deq_data[469:465] == 5'd5) $write("St"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd6) + rob$deqPort_0_deq_data[469:465] == 5'd6) $write("Lr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd7) + rob$deqPort_0_deq_data[469:465] == 5'd7) $write("Sc"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd8) + rob$deqPort_0_deq_data[469:465] == 5'd8) $write("J"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd9) + rob$deqPort_0_deq_data[469:465] == 5'd9) $write("Jr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd10) + rob$deqPort_0_deq_data[469:465] == 5'd10) $write("Br"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd11) + rob$deqPort_0_deq_data[469:465] == 5'd11) + $write("CCall"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd12) + $write("CJALR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd13) + $write("Cap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd14) $write("Auipc"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd12) + rob$deqPort_0_deq_data[469:465] == 5'd15) + $write("Auipcc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd16) $write("Fpu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13) + rob$deqPort_0_deq_data[469:465] == 5'd17) $write("Csr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd14) + rob$deqPort_0_deq_data[469:465] == 5'd18) + $write("Scr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[469:465] == 5'd19) $write("Fence"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd15) + rob$deqPort_0_deq_data[469:465] == 5'd20) $write("FenceI"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd16) + rob$deqPort_0_deq_data[469:465] == 5'd21) $write("SFence"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd17) + rob$deqPort_0_deq_data[469:465] == 5'd22) $write("Ecall"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd18) + rob$deqPort_0_deq_data[469:465] == 5'd23) $write("Ebreak"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd19) + rob$deqPort_0_deq_data[469:465] == 5'd24) $write("Sret"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd20) + rob$deqPort_0_deq_data[469:465] == 5'd25) $write("Mret"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] != 5'd0 && - rob$deqPort_0_deq_data[186:182] != 5'd1 && - rob$deqPort_0_deq_data[186:182] != 5'd2 && - rob$deqPort_0_deq_data[186:182] != 5'd3 && - rob$deqPort_0_deq_data[186:182] != 5'd4 && - rob$deqPort_0_deq_data[186:182] != 5'd5 && - rob$deqPort_0_deq_data[186:182] != 5'd6 && - rob$deqPort_0_deq_data[186:182] != 5'd7 && - rob$deqPort_0_deq_data[186:182] != 5'd8 && - rob$deqPort_0_deq_data[186:182] != 5'd9 && - rob$deqPort_0_deq_data[186:182] != 5'd10 && - rob$deqPort_0_deq_data[186:182] != 5'd11 && - rob$deqPort_0_deq_data[186:182] != 5'd12 && - rob$deqPort_0_deq_data[186:182] != 5'd13 && - rob$deqPort_0_deq_data[186:182] != 5'd14 && - rob$deqPort_0_deq_data[186:182] != 5'd15 && - rob$deqPort_0_deq_data[186:182] != 5'd16 && - rob$deqPort_0_deq_data[186:182] != 5'd17 && - rob$deqPort_0_deq_data[186:182] != 5'd18 && - rob$deqPort_0_deq_data[186:182] != 5'd19 && - rob$deqPort_0_deq_data[186:182] != 5'd20) + rob$deqPort_0_deq_data[469:465] != 5'd0 && + rob$deqPort_0_deq_data[469:465] != 5'd1 && + rob$deqPort_0_deq_data[469:465] != 5'd2 && + rob$deqPort_0_deq_data[469:465] != 5'd3 && + rob$deqPort_0_deq_data[469:465] != 5'd4 && + rob$deqPort_0_deq_data[469:465] != 5'd5 && + rob$deqPort_0_deq_data[469:465] != 5'd6 && + rob$deqPort_0_deq_data[469:465] != 5'd7 && + rob$deqPort_0_deq_data[469:465] != 5'd8 && + rob$deqPort_0_deq_data[469:465] != 5'd9 && + rob$deqPort_0_deq_data[469:465] != 5'd10 && + rob$deqPort_0_deq_data[469:465] != 5'd11 && + rob$deqPort_0_deq_data[469:465] != 5'd12 && + rob$deqPort_0_deq_data[469:465] != 5'd13 && + rob$deqPort_0_deq_data[469:465] != 5'd14 && + rob$deqPort_0_deq_data[469:465] != 5'd15 && + rob$deqPort_0_deq_data[469:465] != 5'd16 && + rob$deqPort_0_deq_data[469:465] != 5'd17 && + rob$deqPort_0_deq_data[469:465] != 5'd18 && + rob$deqPort_0_deq_data[469:465] != 5'd19 && + rob$deqPort_0_deq_data[469:465] != 5'd20 && + rob$deqPort_0_deq_data[469:465] != 5'd21 && + rob$deqPort_0_deq_data[469:465] != 5'd22 && + rob$deqPort_0_deq_data[469:465] != 5'd23 && + rob$deqPort_0_deq_data[469:465] != 5'd24 && + rob$deqPort_0_deq_data[469:465] != 5'd25) $write("Interrupt"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst) $write(" [doCommitSystemInst]", "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == 6'd6) + rob$deqPort_0_deq_data[469:465] == 5'd17 && + IF_rob_deqPort_0_deq_data__2022_BIT_288_2691_T_ETC___d22785 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq) $write("instret:%0d PC:0x%0h instr:0x%08h", - commitStage_rg_instret, - rob$deqPort_0_deq_data[282:219], - rob$deqPort_0_deq_data[218:187], + commitStage_rg_serial_num, + rob$deqPort_0_deq_data[630:502], + rob$deqPort_0_deq_data[501:470], " iType:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] == 5'd1) + rob$deqPort_0_deq_data[469:465] == 5'd1) $write("Nop"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] == 5'd2) + rob$deqPort_0_deq_data[469:465] == 5'd2) $write("Amo"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] == 5'd3) + rob$deqPort_0_deq_data[469:465] == 5'd3) $write("Alu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] == 5'd4) + rob$deqPort_0_deq_data[469:465] == 5'd4) $write("Ld"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] == 5'd5) + rob$deqPort_0_deq_data[469:465] == 5'd5) $write("St"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] == 5'd6) + rob$deqPort_0_deq_data[469:465] == 5'd6) $write("Lr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] == 5'd7) + rob$deqPort_0_deq_data[469:465] == 5'd7) $write("Sc"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] == 5'd8) + rob$deqPort_0_deq_data[469:465] == 5'd8) $write("J"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] == 5'd9) + rob$deqPort_0_deq_data[469:465] == 5'd9) $write("Jr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] == 5'd10) + rob$deqPort_0_deq_data[469:465] == 5'd10) $write("Br"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] == 5'd11) + rob$deqPort_0_deq_data[469:465] == 5'd11) + $write("CCall"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitNormalInst && + rob$deqPort_0_canDeq && + rob$deqPort_0_deq_data[469:465] == 5'd12) + $write("CJALR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitNormalInst && + rob$deqPort_0_canDeq && + rob$deqPort_0_deq_data[469:465] == 5'd13) + $write("Cap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitNormalInst && + rob$deqPort_0_canDeq && + rob$deqPort_0_deq_data[469:465] == 5'd14) $write("Auipc"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] == 5'd12) + rob$deqPort_0_deq_data[469:465] == 5'd15) + $write("Auipcc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitNormalInst && + rob$deqPort_0_canDeq && + rob$deqPort_0_deq_data[469:465] == 5'd16) $write("Fpu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] == 5'd14) + rob$deqPort_0_deq_data[469:465] == 5'd19) $write("Fence"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && - rob$deqPort_0_deq_data[186:182] != 5'd1 && - rob$deqPort_0_deq_data[186:182] != 5'd2 && - rob$deqPort_0_deq_data[186:182] != 5'd3 && - rob$deqPort_0_deq_data[186:182] != 5'd4 && - rob$deqPort_0_deq_data[186:182] != 5'd5 && - rob$deqPort_0_deq_data[186:182] != 5'd6 && - rob$deqPort_0_deq_data[186:182] != 5'd7 && - rob$deqPort_0_deq_data[186:182] != 5'd8 && - rob$deqPort_0_deq_data[186:182] != 5'd9 && - rob$deqPort_0_deq_data[186:182] != 5'd10 && - rob$deqPort_0_deq_data[186:182] != 5'd11 && - rob$deqPort_0_deq_data[186:182] != 5'd12 && - rob$deqPort_0_deq_data[186:182] != 5'd14) + rob$deqPort_0_deq_data[469:465] != 5'd1 && + rob$deqPort_0_deq_data[469:465] != 5'd2 && + rob$deqPort_0_deq_data[469:465] != 5'd3 && + rob$deqPort_0_deq_data[469:465] != 5'd4 && + rob$deqPort_0_deq_data[469:465] != 5'd5 && + rob$deqPort_0_deq_data[469:465] != 5'd6 && + rob$deqPort_0_deq_data[469:465] != 5'd7 && + rob$deqPort_0_deq_data[469:465] != 5'd8 && + rob$deqPort_0_deq_data[469:465] != 5'd9 && + rob$deqPort_0_deq_data[469:465] != 5'd10 && + rob$deqPort_0_deq_data[469:465] != 5'd11 && + rob$deqPort_0_deq_data[469:465] != 5'd12 && + rob$deqPort_0_deq_data[469:465] != 5'd13 && + rob$deqPort_0_deq_data[469:465] != 5'd14 && + rob$deqPort_0_deq_data[469:465] != 5'd15 && + rob$deqPort_0_deq_data[469:465] != 5'd16 && + rob$deqPort_0_deq_data[469:465] != 5'd19) $write("Interrupt"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq) @@ -37580,178 +52988,19042 @@ module mkCore(CLK, rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] != 5'd0 && - rob$deqPort_1_deq_data[186:182] != 5'd21 && - rob$deqPort_1_deq_data[186:182] != 5'd17 && - rob$deqPort_1_deq_data[186:182] != 5'd18 && - rob$deqPort_1_deq_data[186:182] != 5'd13 && - rob$deqPort_1_deq_data[186:182] != 5'd16 && - rob$deqPort_1_deq_data[186:182] != 5'd15 && - rob$deqPort_1_deq_data[186:182] != 5'd19 && - rob$deqPort_1_deq_data[186:182] != 5'd20) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] != 5'd0 && + rob$deqPort_1_deq_data[469:465] != 5'd26 && + rob$deqPort_1_deq_data[469:465] != 5'd22 && + rob$deqPort_1_deq_data[469:465] != 5'd23 && + rob$deqPort_1_deq_data[469:465] != 5'd17 && + rob$deqPort_1_deq_data[469:465] != 5'd18 && + rob$deqPort_1_deq_data[469:465] != 5'd21 && + rob$deqPort_1_deq_data[469:465] != 5'd20 && + rob$deqPort_1_deq_data[469:465] != 5'd24 && + rob$deqPort_1_deq_data[469:465] != 5'd25) $write("instret:%0d PC:0x%0h instr:0x%08h", - commitStage_rg_instret + - IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663, - rob$deqPort_1_deq_data[282:219], - rob$deqPort_1_deq_data[218:187], + commitStage_rg_serial_num + + IF_rob_deqPort_0_canDeq__3151_THEN_IF_NOT_rob__ETC___d23272, + rob$deqPort_1_deq_data[630:502], + rob$deqPort_1_deq_data[501:470], " iType:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] == 5'd1) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd1) $write("Nop"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] == 5'd2) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd2) $write("Amo"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] == 5'd3) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd3) $write("Alu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] == 5'd4) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd4) $write("Ld"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] == 5'd5) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd5) $write("St"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] == 5'd6) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd6) $write("Lr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] == 5'd7) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd7) $write("Sc"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] == 5'd8) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd8) $write("J"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] == 5'd9) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd9) $write("Jr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] == 5'd10) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd10) $write("Br"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] == 5'd11) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd11) + $write("CCall"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitNormalInst && + rob$deqPort_1_canDeq && + rob$deqPort_1_deq_data[25] && + !rob$deqPort_1_deq_data[18] && + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd12) + $write("CJALR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitNormalInst && + rob$deqPort_1_canDeq && + rob$deqPort_1_deq_data[25] && + !rob$deqPort_1_deq_data[18] && + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd13) + $write("Cap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitNormalInst && + rob$deqPort_1_canDeq && + rob$deqPort_1_deq_data[25] && + !rob$deqPort_1_deq_data[18] && + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd14) $write("Auipc"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] == 5'd12) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd15) + $write("Auipcc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_commitStage_doCommitNormalInst && + rob$deqPort_1_canDeq && + rob$deqPort_1_deq_data[25] && + !rob$deqPort_1_deq_data[18] && + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd16) $write("Fpu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] == 5'd14) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] == 5'd19) $write("Fence"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] != 5'd0 && - rob$deqPort_1_deq_data[186:182] != 5'd21 && - rob$deqPort_1_deq_data[186:182] != 5'd17 && - rob$deqPort_1_deq_data[186:182] != 5'd18 && - rob$deqPort_1_deq_data[186:182] != 5'd13 && - rob$deqPort_1_deq_data[186:182] != 5'd16 && - rob$deqPort_1_deq_data[186:182] != 5'd15 && - rob$deqPort_1_deq_data[186:182] != 5'd19 && - rob$deqPort_1_deq_data[186:182] != 5'd20 && - rob$deqPort_1_deq_data[186:182] != 5'd1 && - rob$deqPort_1_deq_data[186:182] != 5'd2 && - rob$deqPort_1_deq_data[186:182] != 5'd3 && - rob$deqPort_1_deq_data[186:182] != 5'd4 && - rob$deqPort_1_deq_data[186:182] != 5'd5 && - rob$deqPort_1_deq_data[186:182] != 5'd6 && - rob$deqPort_1_deq_data[186:182] != 5'd7 && - rob$deqPort_1_deq_data[186:182] != 5'd8 && - rob$deqPort_1_deq_data[186:182] != 5'd9 && - rob$deqPort_1_deq_data[186:182] != 5'd10 && - rob$deqPort_1_deq_data[186:182] != 5'd11 && - rob$deqPort_1_deq_data[186:182] != 5'd12 && - rob$deqPort_1_deq_data[186:182] != 5'd14) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] != 5'd0 && + rob$deqPort_1_deq_data[469:465] != 5'd26 && + rob$deqPort_1_deq_data[469:465] != 5'd22 && + rob$deqPort_1_deq_data[469:465] != 5'd23 && + rob$deqPort_1_deq_data[469:465] != 5'd17 && + rob$deqPort_1_deq_data[469:465] != 5'd18 && + rob$deqPort_1_deq_data[469:465] != 5'd21 && + rob$deqPort_1_deq_data[469:465] != 5'd20 && + rob$deqPort_1_deq_data[469:465] != 5'd24 && + rob$deqPort_1_deq_data[469:465] != 5'd25 && + rob$deqPort_1_deq_data[469:465] != 5'd1 && + rob$deqPort_1_deq_data[469:465] != 5'd2 && + rob$deqPort_1_deq_data[469:465] != 5'd3 && + rob$deqPort_1_deq_data[469:465] != 5'd4 && + rob$deqPort_1_deq_data[469:465] != 5'd5 && + rob$deqPort_1_deq_data[469:465] != 5'd6 && + rob$deqPort_1_deq_data[469:465] != 5'd7 && + rob$deqPort_1_deq_data[469:465] != 5'd8 && + rob$deqPort_1_deq_data[469:465] != 5'd9 && + rob$deqPort_1_deq_data[469:465] != 5'd10 && + rob$deqPort_1_deq_data[469:465] != 5'd11 && + rob$deqPort_1_deq_data[469:465] != 5'd12 && + rob$deqPort_1_deq_data[469:465] != 5'd13 && + rob$deqPort_1_deq_data[469:465] != 5'd14 && + rob$deqPort_1_deq_data[469:465] != 5'd15 && + rob$deqPort_1_deq_data[469:465] != 5'd16 && + rob$deqPort_1_deq_data[469:465] != 5'd19) $write("Interrupt"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && rob$deqPort_1_deq_data[25] && !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] != 5'd0 && - rob$deqPort_1_deq_data[186:182] != 5'd21 && - rob$deqPort_1_deq_data[186:182] != 5'd17 && - rob$deqPort_1_deq_data[186:182] != 5'd18 && - rob$deqPort_1_deq_data[186:182] != 5'd13 && - rob$deqPort_1_deq_data[186:182] != 5'd16 && - rob$deqPort_1_deq_data[186:182] != 5'd15 && - rob$deqPort_1_deq_data[186:182] != 5'd19 && - rob$deqPort_1_deq_data[186:182] != 5'd20) + !rob$deqPort_1_deq_data[274] && + rob$deqPort_1_deq_data[469:465] != 5'd0 && + rob$deqPort_1_deq_data[469:465] != 5'd26 && + rob$deqPort_1_deq_data[469:465] != 5'd22 && + rob$deqPort_1_deq_data[469:465] != 5'd23 && + rob$deqPort_1_deq_data[469:465] != 5'd17 && + rob$deqPort_1_deq_data[469:465] != 5'd18 && + rob$deqPort_1_deq_data[469:465] != 5'd21 && + rob$deqPort_1_deq_data[469:465] != 5'd20 && + rob$deqPort_1_deq_data[469:465] != 5'd24 && + rob$deqPort_1_deq_data[469:465] != 5'd25) $write(" [doCommitNormalInst [%0d]]", $signed(32'd1), "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write("[doDeqLdQ_Lr_deq] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write("LdQDeqEntry { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write("'h%h", coreFix_memExe_lsq$firstLd[143:139]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write(", ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write("'h%h", coreFix_memExe_lsq$firstLd[138]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write("'h%h", coreFix_memExe_lsq$firstLd[137:133]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write("'h%h", coreFix_memExe_lsq$firstLd[132:127], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[126]) + $write("Lr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[126]) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write(", ", "unsignedLd: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[109]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[109]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[108]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[108]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[107]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[107]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[106]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[106]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[106]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[106]) + $write("'h%h", coreFix_memExe_lsq$firstLd[105:99]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[106]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[106] && + coreFix_memExe_lsq$firstLd[98]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[106] && + !coreFix_memExe_lsq$firstLd[98]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[106]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write("'h%h", coreFix_memExe_lsq$firstLd[97:34]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[33]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[33]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write("tagged CapException "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1) + $write("tagged Exception "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1) + $write("tagged Interrupt "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd0) + $write("UserSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd1) + $write("SupervisorSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd3) + $write("MachineSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd4) + $write("UserTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd5) + $write("SupervisorTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd7) + $write("MachineTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd8) + $write("UserExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd9) + $write("SupervisorExternel"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd11) + $write("MachineExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd14) + $write("DebugHalt"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd0 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd1 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd3 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd4 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd5 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd7 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd8 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd9 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd11 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd14) + $write("DebugStep"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd0) + $write("InstAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd1) + $write("InstAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd2) + $write("IllegalInst"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd3) + $write("Breakpoint"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd4) + $write("LoadAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd5) + $write("LoadAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd6) + $write("StoreAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd7) + $write("StoreAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd8) + $write("EnvCallU"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd9) + $write("EnvCallS"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd11) + $write("EnvCallM"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd12) + $write("InstPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd13) + $write("LoadPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd15) + $write("StorePageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd0 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd1 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd2 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd3 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd4 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd5 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd6 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd7 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd8 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd9 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd11 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd12 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd13 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd15) + $write("CHERIFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write("CSR_XCapCause { ", "cheri_exc_reg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write("'h%h", coreFix_memExe_lsq$firstLd[13:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(", ", "cheri_exc_code: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd0) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd1) + $write("LengthViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd2) + $write("TagViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd3) + $write("SealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd4) + $write("TypeViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd5) + $write("CallTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd6) + $write("ReturnTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd7) + $write("StackUnderflow"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd8) + $write("SoftwarePermViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd9) + $write("MMUStoreCapProhibit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd10) + $write("RepresentViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd11) + $write("UnalignedBase"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd16) + $write("GlobalViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd17) + $write("PermitXViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd18) + $write("PermitRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd19) + $write("PermitWViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd20) + $write("PermitRCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd21) + $write("PermitWCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd22) + $write("PermitWLocalCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd23) + $write("PermitSealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd24) + $write("PermitASRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd25) + $write("PermitCCallViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd26) + $write("PermitUnsealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd0 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd1 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd2 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd3 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd4 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd5 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd6 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd7 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd8 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd9 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd10 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd11 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd16 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd17 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd18 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd19 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd20 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd21 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd22 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd23 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd24 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd25 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd26) + $write("PermitSetCIDViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write(", ", "killed: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[2]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[2]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd0) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd1) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] != 2'd0 && + coreFix_memExe_lsq$firstLd[1:0] != 2'd1) + $write("Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_lsq$firstLd[2]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_respLrScAmoQ_data_0[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + !coreFix_memExe_respLrScAmoQ_data_0[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + (coreFix_memExe_lsq$firstLd[125:110] != 16'd65535 || + !coreFix_memExe_respLrScAmoQ_data_0[128])) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && + coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && + coreFix_memExe_respLrScAmoQ_data_0[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write("[doDeqLdQ_MMIO_deq] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write("LdQDeqEntry { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write("'h%h", coreFix_memExe_lsq$firstLd[143:139]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write("'h%h", coreFix_memExe_lsq$firstLd[138]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write("'h%h", coreFix_memExe_lsq$firstLd[137:133]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write("'h%h", coreFix_memExe_lsq$firstLd[132:127], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[126]) + $write("Lr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[126]) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "unsignedLd: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[109]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[109]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[108]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[108]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[107]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[107]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[106]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[106]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[106]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[106]) + $write("'h%h", coreFix_memExe_lsq$firstLd[105:99]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[106]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[106] && + coreFix_memExe_lsq$firstLd[98]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[106] && + !coreFix_memExe_lsq$firstLd[98]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[106]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write("'h%h", coreFix_memExe_lsq$firstLd[97:34]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[33]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[33]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write("tagged CapException "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1) + $write("tagged Exception "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1) + $write("tagged Interrupt "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd0) + $write("UserSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd1) + $write("SupervisorSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd3) + $write("MachineSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd4) + $write("UserTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd5) + $write("SupervisorTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd7) + $write("MachineTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd8) + $write("UserExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd9) + $write("SupervisorExternel"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd11) + $write("MachineExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] == 4'd14) + $write("DebugHalt"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd0 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd1 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd3 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd4 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd5 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd7 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd8 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd9 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd11 && + coreFix_memExe_lsq$firstLd[6:3] != 4'd14) + $write("DebugStep"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd0) + $write("InstAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd1) + $write("InstAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd2) + $write("IllegalInst"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd3) + $write("Breakpoint"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd4) + $write("LoadAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd5) + $write("LoadAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd6) + $write("StoreAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd7) + $write("StoreAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd8) + $write("EnvCallU"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd9) + $write("EnvCallS"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd11) + $write("EnvCallM"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd12) + $write("InstPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd13) + $write("LoadPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd15) + $write("StorePageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd1 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd0 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd1 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd2 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd3 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd4 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd5 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd6 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd7 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd8 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd9 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd11 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd12 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd13 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd15) + $write("CHERIFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0 && + coreFix_memExe_lsq$firstLd[15:14] != 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write("CSR_XCapCause { ", "cheri_exc_reg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write("'h%h", coreFix_memExe_lsq$firstLd[13:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(", ", "cheri_exc_code: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd0) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd1) + $write("LengthViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd2) + $write("TagViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd3) + $write("SealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd4) + $write("TypeViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd5) + $write("CallTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd6) + $write("ReturnTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd7) + $write("StackUnderflow"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd8) + $write("SoftwarePermViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd9) + $write("MMUStoreCapProhibit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd10) + $write("RepresentViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd11) + $write("UnalignedBase"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd16) + $write("GlobalViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd17) + $write("PermitXViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd18) + $write("PermitRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd19) + $write("PermitWViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd20) + $write("PermitRCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd21) + $write("PermitWCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd22) + $write("PermitWLocalCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd23) + $write("PermitSealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd24) + $write("PermitASRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd25) + $write("PermitCCallViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] == 5'd26) + $write("PermitUnsealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd0 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd1 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd2 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd3 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd4 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd5 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd6 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd7 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd8 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd9 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd10 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd11 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd16 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd17 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd18 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd19 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd20 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd21 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd22 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd23 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd24 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd25 && + coreFix_memExe_lsq$firstLd[7:3] != 5'd26) + $write("PermitSetCIDViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] == 2'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[16] && + coreFix_memExe_lsq$firstLd[15:14] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[16]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "killed: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[2]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[2]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd0) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] == 2'd1) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[2] && + coreFix_memExe_lsq$firstLd[1:0] != 2'd0 && + coreFix_memExe_lsq$firstLd[1:0] != 2'd1) + $write("Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !coreFix_memExe_lsq$firstLd[2]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + mmio_dataRespQ_data_0[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + !mmio_dataRespQ_data_0[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + (coreFix_memExe_lsq$firstLd[125:110] != 16'd65535 || + !mmio_dataRespQ_data_0[128])) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && + coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && + mmio_dataRespQ_data_0[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write("[doFinishMem] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("DTlbResp { ", "resp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write("<"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("'h%h", coreFix_memExe_dTlb$procResp[560:497]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(","); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[496]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd0) + $write("InstAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd1) + $write("InstAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd2) + $write("IllegalInst"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd3) + $write("Breakpoint"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd4) + $write("LoadAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd5) + $write("LoadAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd6) + $write("StoreAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd7) + $write("StoreAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd8) + $write("EnvCallU"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd9) + $write("EnvCallS"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd11) + $write("EnvCallM"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd12) + $write("InstPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd13) + $write("LoadPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] == 5'd15) + $write("StorePageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496] && + coreFix_memExe_dTlb$procResp[495:491] != 5'd0 && + coreFix_memExe_dTlb$procResp[495:491] != 5'd1 && + coreFix_memExe_dTlb$procResp[495:491] != 5'd2 && + coreFix_memExe_dTlb$procResp[495:491] != 5'd3 && + coreFix_memExe_dTlb$procResp[495:491] != 5'd4 && + coreFix_memExe_dTlb$procResp[495:491] != 5'd5 && + coreFix_memExe_dTlb$procResp[495:491] != 5'd6 && + coreFix_memExe_dTlb$procResp[495:491] != 5'd7 && + coreFix_memExe_dTlb$procResp[495:491] != 5'd8 && + coreFix_memExe_dTlb$procResp[495:491] != 5'd9 && + coreFix_memExe_dTlb$procResp[495:491] != 5'd11 && + coreFix_memExe_dTlb$procResp[495:491] != 5'd12 && + coreFix_memExe_dTlb$procResp[495:491] != 5'd13 && + coreFix_memExe_dTlb$procResp[495:491] != 5'd15) + $write("CHERIFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[496]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(">"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(", ", "inst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("MemExeToFinish { ", "mem_func: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[490:488] == 3'd0) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[490:488] == 3'd1) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[490:488] == 3'd2) + $write("Lr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[490:488] == 3'd3) + $write("Sc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[490:488] == 3'd4) + $write("Amo"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[490:488] != 3'd0 && + coreFix_memExe_dTlb$procResp[490:488] != 3'd1 && + coreFix_memExe_dTlb$procResp[490:488] != 3'd2 && + coreFix_memExe_dTlb$procResp[490:488] != 3'd3 && + coreFix_memExe_dTlb$procResp[490:488] != 3'd4) + $write("Fence"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(", ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("'h%h", coreFix_memExe_dTlb$procResp[487]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("'h%h", coreFix_memExe_dTlb$procResp[486:482]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("'h%h", coreFix_memExe_dTlb$procResp[481:476], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write(", ", "ldstq_tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[475]) + $write("tagged St ", "'h%h", coreFix_memExe_dTlb$procResp[473:470]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[475]) + $write("tagged Ld ", "'h%h", coreFix_memExe_dTlb$procResp[474:470]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(", ", "vaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write("v: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[453]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[453]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" a: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("'h%h", coreFix_memExe_dTlb$procResp[450:387]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" o: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("'h%h", value__h254401); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" b: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("'h%h", value__h254565); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("'h%h", x__h254677[64:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" sp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("'h%h", { 12'd0, coreFix_memExe_dTlb$procResp[372:369] }); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" hp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("'h%h", coreFix_memExe_dTlb$procResp[368:357]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" ot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("'h%h", coreFix_memExe_dTlb$procResp[353:336]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write(" f: ", "'h%h", coreFix_memExe_dTlb$procResp[356]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write(", ", "misaligned: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[290]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[290]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write(", ", "capException: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[289]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289]) + $write("CSR_XCapCause { ", "cheri_exc_reg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[289]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289]) + $write("'h%h", coreFix_memExe_dTlb$procResp[288:283]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[289]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289]) + $write(", ", "cheri_exc_code: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[289]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd0) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd1) + $write("LengthViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd2) + $write("TagViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd3) + $write("SealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd4) + $write("TypeViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd5) + $write("CallTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd6) + $write("ReturnTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd7) + $write("StackUnderflow"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd8) + $write("SoftwarePermViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd9) + $write("MMUStoreCapProhibit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd10) + $write("RepresentViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd11) + $write("UnalignedBase"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd16) + $write("GlobalViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd17) + $write("PermitXViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd18) + $write("PermitRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd19) + $write("PermitWViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd20) + $write("PermitRCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd21) + $write("PermitWCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd22) + $write("PermitWLocalCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd23) + $write("PermitSealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd24) + $write("PermitASRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd25) + $write("PermitCCallViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] == 5'd26) + $write("PermitUnsealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289] && + coreFix_memExe_dTlb$procResp[282:278] != 5'd0 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd1 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd2 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd3 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd4 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd5 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd6 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd7 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd8 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd9 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd10 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd11 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd16 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd17 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd18 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd19 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd20 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd21 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd22 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd23 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd24 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd25 && + coreFix_memExe_dTlb$procResp[282:278] != 5'd26) + $write("PermitSetCIDViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[289]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[289]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[289]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(", ", "check: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277]) + $write("BoundsCheck { ", "authority_base: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277]) + $write("'h%h", coreFix_memExe_dTlb$procResp[276:213]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277]) + $write(", ", "authority_top: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277]) + $write("'h%h", coreFix_memExe_dTlb$procResp[212:148]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277]) + $write(", ", "authority_idx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277]) + $write("'h%h", coreFix_memExe_dTlb$procResp[147:142]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277]) + $write(", ", "check_low: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277]) + $write("'h%h", coreFix_memExe_dTlb$procResp[141:78]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277]) + $write(", ", "check_high: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277]) + $write("'h%h", coreFix_memExe_dTlb$procResp[77:13]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277]) + $write(", ", "check_inclusive: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277] && + coreFix_memExe_dTlb$procResp[12]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277] && + !coreFix_memExe_dTlb$procResp[12]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[277]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !coreFix_memExe_dTlb$procResp[277]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(", ", "specBits: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) + $write("'h%h", coreFix_memExe_dTlb$procResp[11:0], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doFinishMem && + coreFix_memExe_dTlb$procResp[496]) + $display(" [doFinishMem - dTlb response] PAGEFAULT!"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("[doDeqStQ_ScAmo_issue] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("StQDeqEntry { ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("'h%h", coreFix_memExe_lsq$firstSt[252]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("'h%h", coreFix_memExe_lsq$firstSt[251:247]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("'h%h", coreFix_memExe_lsq$firstSt[246:241], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd0) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd1) + $write("Sc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2) + $write("Amo"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "amoFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd0) + $write("Swap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd1) + $write("Add"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd2) + $write("Xor"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd3) + $write("And"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd4) + $write("Or"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd5) + $write("Min"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd6) + $write("Max"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd7) + $write("Minu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd8) + $write("Maxu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] != 4'd0 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd1 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd2 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd3 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd4 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd5 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd6 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd7 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd8) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[234]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + !coreFix_memExe_lsq$firstSt[234]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[233]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + !coreFix_memExe_lsq$firstSt[233]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[232]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + !coreFix_memExe_lsq$firstSt[232]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[232]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[232]) + $write("'h%h", coreFix_memExe_lsq$firstSt[231:225]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[232]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[232] && + coreFix_memExe_lsq$firstSt[224]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[232] && + !coreFix_memExe_lsq$firstSt[224]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[232]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("'h%h", coreFix_memExe_lsq$firstSt[223:160]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "stData: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[142]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + !coreFix_memExe_lsq$firstSt[142]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("ProcRq { ", "id: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("'h%h", 5'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "addr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("'h%h", coreFix_memExe_lsq$firstSt[223:160]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "toState: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write("M"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "op: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd1) + $write("Sc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[240:239] != 2'd1) + $write("Amo"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[142]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + !coreFix_memExe_lsq$firstSt[142]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "amoInst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write("AmoInst { ", "func: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd0) + $write("Swap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd1) + $write("Add"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd2) + $write("Xor"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd3) + $write("And"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd4) + $write("Or"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd5) + $write("Min"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd6) + $write("Max"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd7) + $write("Minu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd8) + $write("Maxu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[238:235] != 4'd0 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd1 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd2 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd3 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd4 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd5 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd6 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd7 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd8) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "width: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[158:143] == 16'd65535) + $write("QWord"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[158:143] != 16'd65535 && + (coreFix_memExe_lsq$firstSt[158:151] == 8'd255 || + coreFix_memExe_lsq$firstSt[150:143] == 8'd255)) + $write("DWord"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[158:143] != 16'd65535 && + coreFix_memExe_lsq$firstSt[158:151] != 8'd255 && + coreFix_memExe_lsq$firstSt[150:143] != 8'd255) + $write("Word"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "aq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[234]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + !coreFix_memExe_lsq$firstSt[234]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) + $write(", ", "rl: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + coreFix_memExe_lsq$firstSt[233]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && + !coreFix_memExe_lsq$firstSt[233]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write("[doDeqStQ_MMIO_issue] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write("StQDeqEntry { ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write("'h%h", coreFix_memExe_lsq$firstSt[252]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write("'h%h", coreFix_memExe_lsq$firstSt[251:247]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write("'h%h", coreFix_memExe_lsq$firstSt[246:241], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd0) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd1) + $write("Sc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2) + $write("Amo"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] != 2'd0 && + coreFix_memExe_lsq$firstSt[240:239] != 2'd1 && + coreFix_memExe_lsq$firstSt[240:239] != 2'd2) + $write("Fence"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "amoFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd0) + $write("Swap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd1) + $write("Add"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd2) + $write("Xor"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd3) + $write("And"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd4) + $write("Or"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd5) + $write("Min"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd6) + $write("Max"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd7) + $write("Minu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[238:235] == 4'd8) + $write("Maxu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[238:235] != 4'd0 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd1 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd2 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd3 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd4 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd5 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd6 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd7 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd8) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[234]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + !coreFix_memExe_lsq$firstSt[234]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[233]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + !coreFix_memExe_lsq$firstSt[233]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[232]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + !coreFix_memExe_lsq$firstSt[232]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[232]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[232]) + $write("'h%h", coreFix_memExe_lsq$firstSt[231:225]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[232]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[232] && + coreFix_memExe_lsq$firstSt[224]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[232] && + !coreFix_memExe_lsq$firstSt[224]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[232]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write("'h%h", coreFix_memExe_lsq$firstSt[223:160]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "stData: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[142]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + !coreFix_memExe_lsq$firstSt[142]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write("MMIOCRq { ", "addr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write("'h%h", coreFix_memExe_lsq$firstSt[223:160]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "func: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd0) + $write("tagged St ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] != 2'd0) + $write("tagged Amo "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2 && + coreFix_memExe_lsq$firstSt[238:235] == 4'd0) + $write("Swap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2 && + coreFix_memExe_lsq$firstSt[238:235] == 4'd1) + $write("Add"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2 && + coreFix_memExe_lsq$firstSt[238:235] == 4'd2) + $write("Xor"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2 && + coreFix_memExe_lsq$firstSt[238:235] == 4'd3) + $write("And"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2 && + coreFix_memExe_lsq$firstSt[238:235] == 4'd4) + $write("Or"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2 && + coreFix_memExe_lsq$firstSt[238:235] == 4'd5) + $write("Min"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2 && + coreFix_memExe_lsq$firstSt[238:235] == 4'd6) + $write("Max"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2 && + coreFix_memExe_lsq$firstSt[238:235] == 4'd7) + $write("Minu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2 && + coreFix_memExe_lsq$firstSt[238:235] == 4'd8) + $write("Maxu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[240:239] != 2'd0 && + (coreFix_memExe_lsq$firstSt[240:239] != 2'd2 || + coreFix_memExe_lsq$firstSt[238:235] != 4'd0) && + (coreFix_memExe_lsq$firstSt[240:239] != 2'd2 || + coreFix_memExe_lsq$firstSt[238:235] != 4'd1) && + (coreFix_memExe_lsq$firstSt[240:239] != 2'd2 || + coreFix_memExe_lsq$firstSt[238:235] != 4'd2) && + (coreFix_memExe_lsq$firstSt[240:239] != 2'd2 || + coreFix_memExe_lsq$firstSt[238:235] != 4'd3) && + (coreFix_memExe_lsq$firstSt[240:239] != 2'd2 || + coreFix_memExe_lsq$firstSt[238:235] != 4'd4) && + (coreFix_memExe_lsq$firstSt[240:239] != 2'd2 || + coreFix_memExe_lsq$firstSt[238:235] != 4'd5) && + (coreFix_memExe_lsq$firstSt[240:239] != 2'd2 || + coreFix_memExe_lsq$firstSt[238:235] != 4'd6) && + (coreFix_memExe_lsq$firstSt[240:239] != 2'd2 || + coreFix_memExe_lsq$firstSt[238:235] != 4'd7) && + (coreFix_memExe_lsq$firstSt[240:239] != 2'd2 || + coreFix_memExe_lsq$firstSt[238:235] != 4'd8)) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + coreFix_memExe_lsq$firstSt[142]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && + !coreFix_memExe_lsq$firstSt[142]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) + begin + v__h213381 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) + $write("%t : ", v__h213381, "[doRespLdMem]", " "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h212809); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + SEL_ARR_NOT_coreFix_memExe_memRespLdQ_data_0_1_ETC___d2157) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + !SEL_ARR_NOT_coreFix_memExe_memRespLdQ_data_0_1_ETC___d2157) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) + $write("LSQRespLdResult { ", "wrongPath: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + coreFix_memExe_lsq$respLd[138]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + !coreFix_memExe_lsq$respLd[138]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + coreFix_memExe_lsq$respLd[137]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + !coreFix_memExe_lsq$respLd[137]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + coreFix_memExe_lsq$respLd[137]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + !coreFix_memExe_lsq$respLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + coreFix_memExe_lsq$respLd[137]) + $write("'h%h", coreFix_memExe_lsq$respLd[136:130]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + !coreFix_memExe_lsq$respLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + coreFix_memExe_lsq$respLd[137]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + !coreFix_memExe_lsq$respLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + coreFix_memExe_lsq$respLd[137] && + coreFix_memExe_lsq$respLd[129]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + coreFix_memExe_lsq$respLd[137] && + !coreFix_memExe_lsq$respLd[129]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + !coreFix_memExe_lsq$respLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + coreFix_memExe_lsq$respLd[137]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + !coreFix_memExe_lsq$respLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + coreFix_memExe_lsq$respLd[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + !coreFix_memExe_lsq$respLd[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) + begin + v__h215650 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) + $write("%t : ", v__h215650, "[doRespLdForward]", " "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) + $write("'h%h", t__h215095); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + SEL_ARR_NOT_coreFix_memExe_forwardQ_data_0_216_ETC___d2240) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + !SEL_ARR_NOT_coreFix_memExe_forwardQ_data_0_216_ETC___d2240) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) + $write("LSQRespLdResult { ", "wrongPath: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + coreFix_memExe_lsq$respLd[138]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + !coreFix_memExe_lsq$respLd[138]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + coreFix_memExe_lsq$respLd[137]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + !coreFix_memExe_lsq$respLd[137]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + coreFix_memExe_lsq$respLd[137]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + !coreFix_memExe_lsq$respLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + coreFix_memExe_lsq$respLd[137]) + $write("'h%h", coreFix_memExe_lsq$respLd[136:130]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + !coreFix_memExe_lsq$respLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + coreFix_memExe_lsq$respLd[137]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + !coreFix_memExe_lsq$respLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + coreFix_memExe_lsq$respLd[137] && + coreFix_memExe_lsq$respLd[129]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + coreFix_memExe_lsq$respLd[137] && + !coreFix_memExe_lsq$respLd[129]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + !coreFix_memExe_lsq$respLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + coreFix_memExe_lsq$respLd[137]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + !coreFix_memExe_lsq$respLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + coreFix_memExe_lsq$respLd[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + !coreFix_memExe_lsq$respLd[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write("[doExeMem] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("ToSpecFifo { ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("MemRegReadToExe { ", "mem_func: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[436:434] == 3'd0) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[436:434] == 3'd1) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[436:434] == 3'd2) + $write("Lr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[436:434] == 3'd3) + $write("Sc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[436:434] == 3'd4) + $write("Amo"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[436:434] != 3'd0 && + coreFix_memExe_regToExeQ$first[436:434] != 3'd1 && + coreFix_memExe_regToExeQ$first[436:434] != 3'd2 && + coreFix_memExe_regToExeQ$first[436:434] != 3'd3 && + coreFix_memExe_regToExeQ$first[436:434] != 3'd4) + $write("Fence"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(", ", "imm: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", coreFix_memExe_regToExeQ$first[433:402]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(", ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", coreFix_memExe_regToExeQ$first[401]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", coreFix_memExe_regToExeQ$first[400:396]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", coreFix_memExe_regToExeQ$first[395:390], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(", ", "ldstq_tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[389]) + $write("tagged St ", "'h%h", coreFix_memExe_regToExeQ$first[387:384]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[389]) + $write("tagged Ld ", "'h%h", coreFix_memExe_regToExeQ$first[388:384]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(", ", "rVal1: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write("v: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[383]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[383]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" a: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", coreFix_memExe_regToExeQ$first[380:317]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", value__h239635); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", value__h239799); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", x__h239911[64:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", { 12'd0, coreFix_memExe_regToExeQ$first[302:299] }); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" hp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", coreFix_memExe_regToExeQ$first[298:287]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" ot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", coreFix_memExe_regToExeQ$first[283:266]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write(" f: ", "'h%h", coreFix_memExe_regToExeQ$first[286]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(", ", "rVal2: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write("v: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[220]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[220]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" a: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", coreFix_memExe_regToExeQ$first[217:154]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", value__h240792); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", value__h240956); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", x__h241068[64:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", { 12'd0, coreFix_memExe_regToExeQ$first[139:136] }); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" hp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", coreFix_memExe_regToExeQ$first[135:124]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" ot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", coreFix_memExe_regToExeQ$first[120:103]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write(" f: ", "'h%h", coreFix_memExe_regToExeQ$first[123]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(", ", "cap_checks: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write("CapChecks {", "rn1 "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write("CapChecks {", "rn1 "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write("'h%h", coreFix_memExe_regToExeQ$first[23:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(", rn2 ", "'h%h", coreFix_memExe_regToExeQ$first[17:12]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[57]) + $write(", ", "ddc_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[57]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[56]) + $write(", ", "src1_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[56]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[55]) + $write(", ", "src2_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[55]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[54]) + $write(", ", "src1_sealed_with_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[54]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[53]) + $write(", ", "src2_sealed_with_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[53]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[52]) + $write(", ", "ddc_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[52]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[51]) + $write(", ", "src1_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[51]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[50]) + $write(", ", "src2_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[50]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[49]) + $write(", ", "src1_src2_types_match"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[49]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[48]) + $write(", ", "src1_permit_ccall"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[48]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[47]) + $write(", ", "src2_permit_ccall"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[47]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[46]) + $write(", ", "src1_permit_x"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[46]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[45]) + $write(", ", "src2_no_permit_x"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[45]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[44]) + $write(", ", "src2_permit_unseal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[44]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[43]) + $write(", ", "src2_permit_seal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[43]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[42]) + $write(", ", "src2_points_to_src1_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[42]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[41]) + $write(", ", "src2_addr_valid_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[41]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[40]) + $write(", ", "src1_type_not_reserved"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[40]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[39]) + $write(", ", "src1_perm_subset_src2"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[39]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[38]) + $write(", ", "src1_derivable"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[38]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[37]) + $write(", ", "scr_read_only"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[37]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[36]) + $write(", ", "cfromptr_bypass"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[36]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[35]) + $write(", ", "ccseal_bypass"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[35]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[34]) + $write(", ", "cap_exact"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write("'h%h", coreFix_memExe_regToExeQ$first[23:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(", rn2 ", "'h%h", coreFix_memExe_regToExeQ$first[17:12]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[57]) + $write(", ", "ddc_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[57]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[56]) + $write(", ", "src1_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[56]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[55]) + $write(", ", "src2_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[55]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[54]) + $write(", ", "src1_sealed_with_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[54]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[53]) + $write(", ", "src2_sealed_with_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[53]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[52]) + $write(", ", "ddc_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[52]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[51]) + $write(", ", "src1_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[51]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[50]) + $write(", ", "src2_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[50]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[49]) + $write(", ", "src1_src2_types_match"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[49]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[48]) + $write(", ", "src1_permit_ccall"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[48]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[47]) + $write(", ", "src2_permit_ccall"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[47]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[46]) + $write(", ", "src1_permit_x"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[46]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[45]) + $write(", ", "src2_no_permit_x"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[45]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[44]) + $write(", ", "src2_permit_unseal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[44]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[43]) + $write(", ", "src2_permit_seal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[43]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[42]) + $write(", ", "src2_points_to_src1_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[42]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[41]) + $write(", ", "src2_addr_valid_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[41]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[40]) + $write(", ", "src1_type_not_reserved"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[40]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[39]) + $write(", ", "src1_perm_subset_src2"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[39]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[38]) + $write(", ", "src1_derivable"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[38]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[37]) + $write(", ", "scr_read_only"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[37]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[36]) + $write(", ", "cfromptr_bypass"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[36]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[35]) + $write(", ", "ccseal_bypass"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[35]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[34]) + $write(", ", "cap_exact"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(", bounds check: ", "auth "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[32:31] == 2'd0) + $write("Src1"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[32:31] == 2'd1) + $write("Src2"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[32:31] == 2'd2) + $write("Pcc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[32:31] != 2'd0 && + coreFix_memExe_regToExeQ$first[32:31] != 2'd1 && + coreFix_memExe_regToExeQ$first[32:31] != 2'd2) + $write("Ddc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(", ", "low "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[30:28] == 3'd0) + $write("Src1Addr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[30:28] == 3'd1) + $write("Src1Base"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[30:28] == 3'd2) + $write("Src1Type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[30:28] == 3'd3) + $write("Src2Addr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[30:28] != 3'd0 && + coreFix_memExe_regToExeQ$first[30:28] != 3'd1 && + coreFix_memExe_regToExeQ$first[30:28] != 3'd2 && + coreFix_memExe_regToExeQ$first[30:28] != 3'd3) + $write("Vaddr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(", ", "high "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[27:25] == 3'd0) + $write("Src1AddrPlus2"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[27:25] == 3'd1) + $write("Src1Top"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[27:25] == 3'd2) + $write("Src1Type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[27:25] == 3'd3) + $write("Src2Addr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[27:25] == 3'd4) + $write("ResultTop"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[27:25] != 3'd0 && + coreFix_memExe_regToExeQ$first[27:25] != 3'd1 && + coreFix_memExe_regToExeQ$first[27:25] != 3'd2 && + coreFix_memExe_regToExeQ$first[27:25] != 3'd3 && + coreFix_memExe_regToExeQ$first[27:25] != 3'd4) + $write("VaddrPlusSize"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33]) + $write(", ", "inclusive "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + coreFix_memExe_regToExeQ$first[24]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + coreFix_memExe_regToExeQ$first[33] && + !coreFix_memExe_regToExeQ$first[24]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem && + !coreFix_memExe_regToExeQ$first[33]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write("}"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(", ", "spec_bits: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) + $write("'h%h", coreFix_memExe_regToExeQ$first[11:0], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) $write("[doRegReadMem] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) + $write("ToSpecFifo { ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) + $write("MemDispatchToRegRead { ", "mem_func: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[144:142] == 3'd0) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[144:142] == 3'd1) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[144:142] == 3'd2) + $write("Lr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[144:142] == 3'd3) + $write("Sc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[144:142] == 3'd4) + $write("Amo"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[144:142] != 3'd0 && + coreFix_memExe_dispToRegQ$first[144:142] != 3'd1 && + coreFix_memExe_dispToRegQ$first[144:142] != 3'd2 && + coreFix_memExe_dispToRegQ$first[144:142] != 3'd3 && + coreFix_memExe_dispToRegQ$first[144:142] != 3'd4) + $write("Fence"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) $write(", ", "imm: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) + $write("'h%h", coreFix_memExe_dispToRegQ$first[141:110]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) $write(", ", "regs: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) + $write("PhyRegs { ", "src1: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[109]) + $write("tagged Valid ", + "'h%h", + coreFix_memExe_dispToRegQ$first[108:102]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[109]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) $write(", ", "src2: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[101]) + $write("tagged Valid ", + "'h%h", + coreFix_memExe_dispToRegQ$first[100:94]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[101]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) $write(", ", "src3: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[93]) + $write("tagged Valid ", + "'h%h", + coreFix_memExe_dispToRegQ$first[92:86]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[93]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[85]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[85]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[85]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[85]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[85]) + $write("'h%h", coreFix_memExe_dispToRegQ$first[84:78]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[85]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[85]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[85]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[85] && + coreFix_memExe_dispToRegQ$first[77]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[85] && + !coreFix_memExe_dispToRegQ$first[77]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[85]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[85]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[85]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) $write(", ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) + $write("'h%h", coreFix_memExe_dispToRegQ$first[76]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) + $write("'h%h", coreFix_memExe_dispToRegQ$first[75:71]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) + $write("'h%h", coreFix_memExe_dispToRegQ$first[70:65], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) + $write(", ", "ldstq_tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[64]) + $write("tagged St ", "'h%h", coreFix_memExe_dispToRegQ$first[62:59]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[64]) + $write("tagged Ld ", "'h%h", coreFix_memExe_dispToRegQ$first[63:59]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) + $write(", ", "cap_checks: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write("CapChecks {", "rn1 "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write("CapChecks {", "rn1 "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write("'h%h", coreFix_memExe_dispToRegQ$first[24:19]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(", rn2 ", "'h%h", coreFix_memExe_dispToRegQ$first[18:13]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[58]) + $write(", ", "ddc_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[58]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[57]) + $write(", ", "src1_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[57]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[56]) + $write(", ", "src2_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[56]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[55]) + $write(", ", "src1_sealed_with_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[55]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[54]) + $write(", ", "src2_sealed_with_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[54]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[53]) + $write(", ", "ddc_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[53]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[52]) + $write(", ", "src1_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[52]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[51]) + $write(", ", "src2_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[51]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[50]) + $write(", ", "src1_src2_types_match"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[50]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[49]) + $write(", ", "src1_permit_ccall"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[49]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[48]) + $write(", ", "src2_permit_ccall"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[48]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[47]) + $write(", ", "src1_permit_x"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[47]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[46]) + $write(", ", "src2_no_permit_x"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[46]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[45]) + $write(", ", "src2_permit_unseal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[45]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[44]) + $write(", ", "src2_permit_seal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[44]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[43]) + $write(", ", "src2_points_to_src1_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[43]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[42]) + $write(", ", "src2_addr_valid_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[42]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[41]) + $write(", ", "src1_type_not_reserved"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[41]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[40]) + $write(", ", "src1_perm_subset_src2"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[40]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[39]) + $write(", ", "src1_derivable"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[39]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[38]) + $write(", ", "scr_read_only"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[38]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[37]) + $write(", ", "cfromptr_bypass"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[37]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[36]) + $write(", ", "ccseal_bypass"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[36]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[35]) + $write(", ", "cap_exact"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[35]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write("'h%h", coreFix_memExe_dispToRegQ$first[24:19]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(", rn2 ", "'h%h", coreFix_memExe_dispToRegQ$first[18:13]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[58]) + $write(", ", "ddc_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[58]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[57]) + $write(", ", "src1_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[57]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[56]) + $write(", ", "src2_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[56]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[55]) + $write(", ", "src1_sealed_with_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[55]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[54]) + $write(", ", "src2_sealed_with_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[54]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[53]) + $write(", ", "ddc_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[53]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[52]) + $write(", ", "src1_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[52]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[51]) + $write(", ", "src2_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[51]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[50]) + $write(", ", "src1_src2_types_match"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[50]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[49]) + $write(", ", "src1_permit_ccall"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[49]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[48]) + $write(", ", "src2_permit_ccall"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[48]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[47]) + $write(", ", "src1_permit_x"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[47]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[46]) + $write(", ", "src2_no_permit_x"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[46]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[45]) + $write(", ", "src2_permit_unseal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[45]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[44]) + $write(", ", "src2_permit_seal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[44]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[43]) + $write(", ", "src2_points_to_src1_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[43]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[42]) + $write(", ", "src2_addr_valid_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[42]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[41]) + $write(", ", "src1_type_not_reserved"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[41]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[40]) + $write(", ", "src1_perm_subset_src2"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[40]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[39]) + $write(", ", "src1_derivable"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[39]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[38]) + $write(", ", "scr_read_only"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[38]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[37]) + $write(", ", "cfromptr_bypass"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[37]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[36]) + $write(", ", "ccseal_bypass"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[36]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[35]) + $write(", ", "cap_exact"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[35]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(", bounds check: ", "auth "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[33:32] == 2'd0) + $write("Src1"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[33:32] == 2'd1) + $write("Src2"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[33:32] == 2'd2) + $write("Pcc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[33:32] != 2'd0 && + coreFix_memExe_dispToRegQ$first[33:32] != 2'd1 && + coreFix_memExe_dispToRegQ$first[33:32] != 2'd2) + $write("Ddc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(", ", "low "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[31:29] == 3'd0) + $write("Src1Addr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[31:29] == 3'd1) + $write("Src1Base"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[31:29] == 3'd2) + $write("Src1Type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[31:29] == 3'd3) + $write("Src2Addr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[31:29] != 3'd0 && + coreFix_memExe_dispToRegQ$first[31:29] != 3'd1 && + coreFix_memExe_dispToRegQ$first[31:29] != 3'd2 && + coreFix_memExe_dispToRegQ$first[31:29] != 3'd3) + $write("Vaddr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(", ", "high "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[28:26] == 3'd0) + $write("Src1AddrPlus2"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[28:26] == 3'd1) + $write("Src1Top"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[28:26] == 3'd2) + $write("Src1Type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[28:26] == 3'd3) + $write("Src2Addr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[28:26] == 3'd4) + $write("ResultTop"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[28:26] != 3'd0 && + coreFix_memExe_dispToRegQ$first[28:26] != 3'd1 && + coreFix_memExe_dispToRegQ$first[28:26] != 3'd2 && + coreFix_memExe_dispToRegQ$first[28:26] != 3'd3 && + coreFix_memExe_dispToRegQ$first[28:26] != 3'd4) + $write("VaddrPlusSize"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34]) + $write(", ", "inclusive "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + coreFix_memExe_dispToRegQ$first[25]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[34] && + !coreFix_memExe_dispToRegQ$first[25]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[34]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) $write("}"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) + $write(", ", "ddc_offset: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + coreFix_memExe_dispToRegQ$first[12]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem && + !coreFix_memExe_dispToRegQ$first[12]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) + $write(", ", "spec_bits: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) + $write("'h%h", coreFix_memExe_dispToRegQ$first[11:0], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write("[doDispatchMem] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write("ToReservationStation { ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write("MemRSData { ", "mem_func: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[153:151] == 3'd0) + $write("Ld"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[153:151] == 3'd1) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[153:151] == 3'd2) + $write("Lr"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[153:151] == 3'd3) + $write("Sc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[153:151] == 3'd4) + $write("Amo"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[153:151] != 3'd0 && + coreFix_memExe_rsMem$dispatchData[153:151] != 3'd1 && + coreFix_memExe_rsMem$dispatchData[153:151] != 3'd2 && + coreFix_memExe_rsMem$dispatchData[153:151] != 3'd3 && + coreFix_memExe_rsMem$dispatchData[153:151] != 3'd4) + $write("Fence"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) $write(", ", "imm: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write("'h%h", coreFix_memExe_rsMem$dispatchData[150:119]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write(", ", "ldstq_tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[118]) + $write("tagged St ", + "'h%h", + coreFix_memExe_rsMem$dispatchData[116:113]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[118]) + $write("tagged Ld ", + "'h%h", + coreFix_memExe_rsMem$dispatchData[117:113]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write(", ", "cap_checks: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[88]) + $write("CapChecks {", "rn1 "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88]) + $write("CapChecks {", "rn1 "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[88]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88]) + $write("'h%h", coreFix_memExe_rsMem$dispatchData[78:73]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[88]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88]) + $write(", rn2 ", "'h%h", coreFix_memExe_rsMem$dispatchData[72:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[88]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88] && + coreFix_memExe_rsMem$dispatchData[112]) + $write(", ", "ddc_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88] && + !coreFix_memExe_rsMem$dispatchData[112]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[88]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88] && + coreFix_memExe_rsMem$dispatchData[111]) + $write(", ", "src1_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88] && + !coreFix_memExe_rsMem$dispatchData[111]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[88]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88] && + coreFix_memExe_rsMem$dispatchData[110]) + $write(", ", "src2_tag"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88] && + !coreFix_memExe_rsMem$dispatchData[110]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[88]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88] && + coreFix_memExe_rsMem$dispatchData[109]) + $write(", ", "src1_sealed_with_type"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88] && + !coreFix_memExe_rsMem$dispatchData[109]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[88]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if 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coreFix_memExe_rsMem$dispatchData[88]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88] && + coreFix_memExe_rsMem$dispatchData[106]) + $write(", ", "src1_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88] && + !coreFix_memExe_rsMem$dispatchData[106]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[88]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88] && + coreFix_memExe_rsMem$dispatchData[105]) + $write(", ", "src2_unsealed"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[88] && + !coreFix_memExe_rsMem$dispatchData[105]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) 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!coreFix_memExe_rsMem$dispatchData[41]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) $write(", ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write("'h%h", coreFix_memExe_rsMem$dispatchData[32]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write("'h%h", coreFix_memExe_rsMem$dispatchData[31:27]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write("'h%h", coreFix_memExe_rsMem$dispatchData[26:21], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write(", ", "spec_bits: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write("'h%h", coreFix_memExe_rsMem$dispatchData[20:9]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write(", ", "spec_tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[8]) + $write("tagged Valid ", + "'h%h", + coreFix_memExe_rsMem$dispatchData[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[8]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write(", ", "regs_ready: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) + $write("RegsReady { ", "src1: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[3]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[3]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) $write(", ", "src2: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[2]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[2]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) $write(", ", "src3: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[1]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[1]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + coreFix_memExe_rsMem$dispatchData[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem && + !coreFix_memExe_rsMem$dispatchData[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) + $write("[doIssueLd] fromIssueQ: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) $write(" ; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) + $write("LSQIssueLdInfo { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) + $write("'h%h", coreFix_memExe_lsq$getIssueLd[84:80]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) + $write("'h%h", coreFix_memExe_lsq$getIssueLd[79:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) $write(" ; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) + $write("SBSearchRes { ", "matchIdx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_stb$search[132]) + $write("tagged Valid ", "'h%h", coreFix_memExe_stb$search[131:130]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + !coreFix_memExe_stb$search[132]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) + $write(", ", "forwardData: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_stb$search[129]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + !coreFix_memExe_stb$search[129]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_stb$search[129]) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + !coreFix_memExe_stb$search[129]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_stb$search[129] && + coreFix_memExe_stb$search[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_stb$search[129] && + !coreFix_memExe_stb$search[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + !coreFix_memExe_stb$search[129]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_stb$search[129]) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + !coreFix_memExe_stb$search[129]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_stb$search[129]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + !coreFix_memExe_stb$search[129]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_stb$search[129]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + !coreFix_memExe_stb$search[129]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) $write(" ; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write("tagged ToCache ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write("tagged Stall "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write("tagged Forward "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write("LSQForwardResult { ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[137]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137]) + $write("'h%h", coreFix_memExe_lsq$issueLd[136:130]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137] && + coreFix_memExe_lsq$issueLd[129]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137] && + !coreFix_memExe_lsq$issueLd[129]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1 && + coreFix_memExe_lsq$issueLd[1:0] == 2'd0) + $write("LdQ"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1 && + coreFix_memExe_lsq$issueLd[1:0] == 2'd1) + $write("StQ"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1 && + coreFix_memExe_lsq$issueLd[1:0] != 2'd0 && + coreFix_memExe_lsq$issueLd[1:0] != 2'd1) + $write("SB"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) + $write("[doIssueLd] fromIssueQ: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) $write(" ; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) + $write("LSQIssueLdInfo { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) + $write("'h%h", coreFix_memExe_issueLd$wget[84:80]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) + $write("'h%h", coreFix_memExe_issueLd$wget[79:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) $write(" ; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) + $write("SBSearchRes { ", "matchIdx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_stb$search[132]) + $write("tagged Valid ", "'h%h", coreFix_memExe_stb$search[131:130]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + !coreFix_memExe_stb$search[132]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) + $write(", ", "forwardData: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_stb$search[129]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + !coreFix_memExe_stb$search[129]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_stb$search[129]) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + !coreFix_memExe_stb$search[129]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_stb$search[129] && + coreFix_memExe_stb$search[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_stb$search[129] && + !coreFix_memExe_stb$search[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + !coreFix_memExe_stb$search[129]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_stb$search[129]) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + !coreFix_memExe_stb$search[129]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_stb$search[129]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + !coreFix_memExe_stb$search[129]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_stb$search[129]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + !coreFix_memExe_stb$search[129]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) $write(" ; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write("tagged ToCache ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write("tagged Stall "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write("tagged Forward "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write("LSQForwardResult { ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[137]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137]) + $write("'h%h", coreFix_memExe_lsq$issueLd[136:130]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137] && + coreFix_memExe_lsq$issueLd[129]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137] && + !coreFix_memExe_lsq$issueLd[129]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[137]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[137]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + coreFix_memExe_lsq$issueLd[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1 && + !coreFix_memExe_lsq$issueLd[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1 && + coreFix_memExe_lsq$issueLd[1:0] == 2'd0) + $write("LdQ"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1 && + coreFix_memExe_lsq$issueLd[1:0] == 2'd1) + $write("StQ"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] == 2'd1 && + coreFix_memExe_lsq$issueLd[1:0] != 2'd0 && + coreFix_memExe_lsq$issueLd[1:0] != 2'd1) + $write("SB"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && + coreFix_memExe_lsq$issueLd[139:138] != 2'd0 && + coreFix_memExe_lsq$issueLd[139:138] != 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) + $write("[doDeqStQ_fault] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) + $write("StQDeqEntry { ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) + $write("'h%h", coreFix_memExe_lsq$firstSt[252]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) + $write("'h%h", coreFix_memExe_lsq$firstSt[251:247]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) + $write("'h%h", coreFix_memExe_lsq$firstSt[246:241], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[240:239] == 2'd0) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[240:239] == 2'd1) + $write("Sc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2) + $write("Amo"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[240:239] != 2'd0 && + coreFix_memExe_lsq$firstSt[240:239] != 2'd1 && + coreFix_memExe_lsq$firstSt[240:239] != 2'd2) + $write("Fence"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) + $write(", ", "amoFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd0) + $write("Swap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd1) + $write("Add"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd2) + $write("Xor"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd3) + $write("And"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd4) + $write("Or"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd5) + $write("Min"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd6) + $write("Max"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd7) + $write("Minu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd8) + $write("Maxu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[238:235] != 4'd0 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd1 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd2 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd3 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd4 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd5 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd6 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd7 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd8) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[234]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + !coreFix_memExe_lsq$firstSt[234]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[233]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + !coreFix_memExe_lsq$firstSt[233]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[232]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + !coreFix_memExe_lsq$firstSt[232]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[232]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[232]) + $write("'h%h", coreFix_memExe_lsq$firstSt[231:225]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[232]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[232] && + coreFix_memExe_lsq$firstSt[224]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[232] && + !coreFix_memExe_lsq$firstSt[224]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[232]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) + $write("'h%h", coreFix_memExe_lsq$firstSt[223:160]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[159]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + !coreFix_memExe_lsq$firstSt[159]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) + $write(", ", "stData: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[142]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + !coreFix_memExe_lsq$firstSt[142]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write("tagged CapException "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1) + $write("tagged Exception "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1) + $write("tagged Interrupt "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd0) + $write("UserSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd1) + $write("SupervisorSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd3) + $write("MachineSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd4) + $write("UserTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd5) + $write("SupervisorTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd7) + $write("MachineTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd8) + $write("UserExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd9) + $write("SupervisorExternel"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd11) + $write("MachineExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd14) + $write("DebugHalt"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd0 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd1 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd3 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd4 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd5 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd7 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd8 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd9 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd11 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd14) + $write("DebugStep"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd0) + $write("InstAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd1) + $write("InstAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd2) + $write("IllegalInst"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd3) + $write("Breakpoint"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd4) + $write("LoadAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd5) + $write("LoadAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd6) + $write("StoreAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd7) + $write("StoreAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd8) + $write("EnvCallU"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd9) + $write("EnvCallS"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd11) + $write("EnvCallM"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd12) + $write("InstPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd13) + $write("LoadPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd15) + $write("StorePageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd0 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd1 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd2 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd3 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd4 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd5 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd6 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd7 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd8 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd9 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd11 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd12 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd13 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd15) + $write("CHERIFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write("CSR_XCapCause { ", "cheri_exc_reg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write("'h%h", coreFix_memExe_lsq$firstSt[10:5]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(", ", "cheri_exc_code: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd0) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd1) + $write("LengthViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd2) + $write("TagViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd3) + $write("SealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd4) + $write("TypeViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd5) + $write("CallTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd6) + $write("ReturnTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd7) + $write("StackUnderflow"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd8) + $write("SoftwarePermViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd9) + $write("MMUStoreCapProhibit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd10) + $write("RepresentViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd11) + $write("UnalignedBase"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd16) + $write("GlobalViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd17) + $write("PermitXViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd18) + $write("PermitRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd19) + $write("PermitWViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd20) + $write("PermitRCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd21) + $write("PermitWCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd22) + $write("PermitWLocalCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd23) + $write("PermitSealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd24) + $write("PermitASRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd25) + $write("PermitCCallViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd26) + $write("PermitUnsealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd0 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd1 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd2 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd3 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd4 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd5 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd6 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd7 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd8 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd9 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd10 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd11 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd16 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd17 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd18 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd19 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd20 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd21 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd22 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd23 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd24 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd25 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd26) + $write("PermitSetCIDViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write("[doDeqStQ_Fence] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write("StQDeqEntry { ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write("'h%h", coreFix_memExe_lsq$firstSt[252]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write("'h%h", coreFix_memExe_lsq$firstSt[251:247]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write("'h%h", coreFix_memExe_lsq$firstSt[246:241], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write("Fence"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write(", ", "amoFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[238:235] == 4'd0) + $write("Swap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[238:235] == 4'd1) + $write("Add"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[238:235] == 4'd2) + $write("Xor"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[238:235] == 4'd3) + $write("And"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[238:235] == 4'd4) + $write("Or"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[238:235] == 4'd5) + $write("Min"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[238:235] == 4'd6) + $write("Max"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[238:235] == 4'd7) + $write("Minu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[238:235] == 4'd8) + $write("Maxu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[238:235] != 4'd0 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd1 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd2 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd3 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd4 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd5 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd6 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd7 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd8) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[234]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + !coreFix_memExe_lsq$firstSt[234]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[233]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + !coreFix_memExe_lsq$firstSt[233]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[232]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + !coreFix_memExe_lsq$firstSt[232]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[232]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[232]) + $write("'h%h", coreFix_memExe_lsq$firstSt[231:225]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[232]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[232] && + coreFix_memExe_lsq$firstSt[224]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[232] && + !coreFix_memExe_lsq$firstSt[224]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[232]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write("'h%h", coreFix_memExe_lsq$firstSt[223:160]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[159]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + !coreFix_memExe_lsq$firstSt[159]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write(", ", "stData: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + coreFix_memExe_lsq$firstSt[142]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + !coreFix_memExe_lsq$firstSt[142]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write("[doDeqStQ_ScAmo_deq] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write("StQDeqEntry { ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write("'h%h", coreFix_memExe_lsq$firstSt[252]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write("'h%h", coreFix_memExe_lsq$firstSt[251:247]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write("'h%h", coreFix_memExe_lsq$firstSt[246:241], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[240:239] == 2'd0) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[240:239] == 2'd1) + $write("Sc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2) + $write("Amo"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[240:239] != 2'd0 && + coreFix_memExe_lsq$firstSt[240:239] != 2'd1 && + coreFix_memExe_lsq$firstSt[240:239] != 2'd2) + $write("Fence"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write(", ", "amoFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd0) + $write("Swap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd1) + $write("Add"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd2) + $write("Xor"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd3) + $write("And"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd4) + $write("Or"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd5) + $write("Min"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd6) + $write("Max"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd7) + $write("Minu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd8) + $write("Maxu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[238:235] != 4'd0 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd1 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd2 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd3 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd4 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd5 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd6 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd7 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd8) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[234]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[234]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[233]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[233]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[232]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[232]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[232]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[232]) + $write("'h%h", coreFix_memExe_lsq$firstSt[231:225]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[232]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[232] && + coreFix_memExe_lsq$firstSt[224]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[232] && + !coreFix_memExe_lsq$firstSt[224]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[232]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write("'h%h", coreFix_memExe_lsq$firstSt[223:160]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[159]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[159]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write(", ", "stData: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[142]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[142]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write("tagged CapException "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1) + $write("tagged Exception "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1) + $write("tagged Interrupt "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd0) + $write("UserSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd1) + $write("SupervisorSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd3) + $write("MachineSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd4) + $write("UserTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd5) + $write("SupervisorTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd7) + $write("MachineTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd8) + $write("UserExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd9) + $write("SupervisorExternel"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd11) + $write("MachineExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd14) + $write("DebugHalt"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd0 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd1 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd3 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd4 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd5 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd7 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd8 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd9 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd11 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd14) + $write("DebugStep"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd0) + $write("InstAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd1) + $write("InstAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd2) + $write("IllegalInst"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd3) + $write("Breakpoint"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd4) + $write("LoadAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd5) + $write("LoadAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd6) + $write("StoreAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd7) + $write("StoreAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd8) + $write("EnvCallU"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd9) + $write("EnvCallS"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd11) + $write("EnvCallM"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd12) + $write("InstPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd13) + $write("LoadPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd15) + $write("StorePageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd0 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd1 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd2 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd3 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd4 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd5 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd6 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd7 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd8 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd9 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd11 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd12 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd13 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd15) + $write("CHERIFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write("CSR_XCapCause { ", "cheri_exc_reg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write("'h%h", coreFix_memExe_lsq$firstSt[10:5]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(", ", "cheri_exc_code: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd0) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd1) + $write("LengthViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd2) + $write("TagViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd3) + $write("SealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd4) + $write("TypeViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd5) + $write("CallTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd6) + $write("ReturnTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd7) + $write("StackUnderflow"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd8) + $write("SoftwarePermViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd9) + $write("MMUStoreCapProhibit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd10) + $write("RepresentViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd11) + $write("UnalignedBase"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd16) + $write("GlobalViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd17) + $write("PermitXViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd18) + $write("PermitRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd19) + $write("PermitWViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd20) + $write("PermitRCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd21) + $write("PermitWCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd22) + $write("PermitWLocalCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd23) + $write("PermitSealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd24) + $write("PermitASRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd25) + $write("PermitCCallViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd26) + $write("PermitUnsealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd0 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd1 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd2 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd3 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd4 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd5 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd6 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd7 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd8 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd9 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd10 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd11 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd16 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd17 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd18 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd19 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd20 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd21 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd22 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd23 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd24 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd25 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd26) + $write("PermitSetCIDViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + coreFix_memExe_respLrScAmoQ_data_0[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !coreFix_memExe_respLrScAmoQ_data_0[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write("[doDeqStQ_MMIO_deq] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write("StQDeqEntry { ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write("'h%h", coreFix_memExe_lsq$firstSt[252]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write("'h%h", coreFix_memExe_lsq$firstSt[251:247]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write("'h%h", coreFix_memExe_lsq$firstSt[246:241], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[240:239] == 2'd0) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[240:239] == 2'd1) + $write("Sc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2) + $write("Amo"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[240:239] != 2'd0 && + coreFix_memExe_lsq$firstSt[240:239] != 2'd1 && + coreFix_memExe_lsq$firstSt[240:239] != 2'd2) + $write("Fence"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write(", ", "amoFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd0) + $write("Swap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd1) + $write("Add"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd2) + $write("Xor"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd3) + $write("And"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd4) + $write("Or"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd5) + $write("Min"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd6) + $write("Max"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd7) + $write("Minu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[238:235] == 4'd8) + $write("Maxu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[238:235] != 4'd0 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd1 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd2 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd3 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd4 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd5 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd6 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd7 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd8) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[234]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[234]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[233]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[233]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[232]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[232]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[232]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[232]) + $write("'h%h", coreFix_memExe_lsq$firstSt[231:225]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[232]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[232] && + coreFix_memExe_lsq$firstSt[224]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[232] && + !coreFix_memExe_lsq$firstSt[224]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[232]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write("'h%h", coreFix_memExe_lsq$firstSt[223:160]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[159]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[159]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write(", ", "stData: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[142]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[142]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write("tagged CapException "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1) + $write("tagged Exception "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1) + $write("tagged Interrupt "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd0) + $write("UserSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd1) + $write("SupervisorSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd3) + $write("MachineSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd4) + $write("UserTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd5) + $write("SupervisorTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd7) + $write("MachineTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd8) + $write("UserExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd9) + $write("SupervisorExternel"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd11) + $write("MachineExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd14) + $write("DebugHalt"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd0 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd1 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd3 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd4 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd5 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd7 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd8 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd9 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd11 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd14) + $write("DebugStep"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd0) + $write("InstAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd1) + $write("InstAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd2) + $write("IllegalInst"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd3) + $write("Breakpoint"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd4) + $write("LoadAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd5) + $write("LoadAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd6) + $write("StoreAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd7) + $write("StoreAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd8) + $write("EnvCallU"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd9) + $write("EnvCallS"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd11) + $write("EnvCallM"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd12) + $write("InstPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd13) + $write("LoadPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd15) + $write("StorePageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd0 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd1 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd2 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd3 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd4 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd5 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd6 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd7 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd8 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd9 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd11 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd12 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd13 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd15) + $write("CHERIFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write("CSR_XCapCause { ", "cheri_exc_reg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write("'h%h", coreFix_memExe_lsq$firstSt[10:5]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(", ", "cheri_exc_code: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd0) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd1) + $write("LengthViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd2) + $write("TagViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd3) + $write("SealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd4) + $write("TypeViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd5) + $write("CallTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd6) + $write("ReturnTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd7) + $write("StackUnderflow"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd8) + $write("SoftwarePermViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd9) + $write("MMUStoreCapProhibit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd10) + $write("RepresentViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd11) + $write("UnalignedBase"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd16) + $write("GlobalViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd17) + $write("PermitXViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd18) + $write("PermitRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd19) + $write("PermitWViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd20) + $write("PermitRCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd21) + $write("PermitWCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd22) + $write("PermitWLocalCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd23) + $write("PermitSealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd24) + $write("PermitASRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd25) + $write("PermitCCallViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd26) + $write("PermitUnsealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd0 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd1 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd2 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd3 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd4 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd5 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd6 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd7 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd8 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd9 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd10 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd11 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd16 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd17 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd18 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd19 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd20 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd21 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd22 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd23 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd24 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd25 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd26) + $write("PermitSetCIDViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + mmio_dataRespQ_data_0[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + !mmio_dataRespQ_data_0[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write("[doDeqStQ_MMIO_fault] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write("StQDeqEntry { ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write("'h%h", coreFix_memExe_lsq$firstSt[252]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write("'h%h", coreFix_memExe_lsq$firstSt[251:247]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write("'h%h", coreFix_memExe_lsq$firstSt[246:241], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[240:239] == 2'd0) + $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[240:239] == 2'd1) + $write("Sc"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[240:239] == 2'd2) + $write("Amo"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[240:239] != 2'd0 && + coreFix_memExe_lsq$firstSt[240:239] != 2'd1 && + coreFix_memExe_lsq$firstSt[240:239] != 2'd2) + $write("Fence"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write(", ", "amoFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd0) + $write("Swap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd1) + $write("Add"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd2) + $write("Xor"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd3) + $write("And"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd4) + $write("Or"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd5) + $write("Min"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd6) + $write("Max"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd7) + $write("Minu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[238:235] == 4'd8) + $write("Maxu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[238:235] != 4'd0 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd1 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd2 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd3 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd4 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd5 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd6 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd7 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd8) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[234]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[234]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[233]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[233]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[232]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[232]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[232]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[232]) + $write("'h%h", coreFix_memExe_lsq$firstSt[231:225]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[232]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[232] && + coreFix_memExe_lsq$firstSt[224]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[232] && + !coreFix_memExe_lsq$firstSt[224]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[232]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write("'h%h", coreFix_memExe_lsq$firstSt[223:160]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[159]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[159]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write(", ", "stData: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[142]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[142]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) + $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[13]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write("tagged CapException "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1) + $write("tagged Exception "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1) + $write("tagged Interrupt "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd0) + $write("UserSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd1) + $write("SupervisorSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd3) + $write("MachineSoftware"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd4) + $write("UserTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd5) + $write("SupervisorTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd7) + $write("MachineTimer"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd8) + $write("UserExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd9) + $write("SupervisorExternel"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd11) + $write("MachineExternal"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] == 4'd14) + $write("DebugHalt"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd0 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd1 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd3 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd4 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd5 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd7 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd8 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd9 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd11 && + coreFix_memExe_lsq$firstSt[3:0] != 4'd14) + $write("DebugStep"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd0) + $write("InstAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd1) + $write("InstAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd2) + $write("IllegalInst"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd3) + $write("Breakpoint"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd4) + $write("LoadAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd5) + $write("LoadAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd6) + $write("StoreAddrMisaligned"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd7) + $write("StoreAccessFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd8) + $write("EnvCallU"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd9) + $write("EnvCallS"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd11) + $write("EnvCallM"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd12) + $write("InstPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd13) + $write("LoadPageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd15) + $write("StorePageFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd1 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd0 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd1 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd2 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd3 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd4 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd5 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd6 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd7 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd8 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd9 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd11 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd12 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd13 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd15) + $write("CHERIFault"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0 && + coreFix_memExe_lsq$firstSt[12:11] != 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write("CSR_XCapCause { ", "cheri_exc_reg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write("'h%h", coreFix_memExe_lsq$firstSt[10:5]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(", ", "cheri_exc_code: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd0) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd1) + $write("LengthViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd2) + $write("TagViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd3) + $write("SealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd4) + $write("TypeViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd5) + $write("CallTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd6) + $write("ReturnTrap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd7) + $write("StackUnderflow"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd8) + $write("SoftwarePermViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd9) + $write("MMUStoreCapProhibit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd10) + $write("RepresentViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd11) + $write("UnalignedBase"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd16) + $write("GlobalViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd17) + $write("PermitXViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd18) + $write("PermitRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd19) + $write("PermitWViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd20) + $write("PermitRCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd21) + $write("PermitWCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd22) + $write("PermitWLocalCapViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd23) + $write("PermitSealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd24) + $write("PermitASRViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd25) + $write("PermitCCallViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] == 5'd26) + $write("PermitUnsealViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd0 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd1 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd2 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd3 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd4 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd5 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd6 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd7 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd8 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd9 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd10 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd11 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd16 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd17 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd18 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd19 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd20 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd21 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd22 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd23 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd24 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd25 && + coreFix_memExe_lsq$firstSt[4:0] != 5'd26) + $write("PermitSetCIDViolation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] == 2'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + coreFix_memExe_lsq$firstSt[13] && + coreFix_memExe_lsq$firstSt[12:11] != 2'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && + !coreFix_memExe_lsq$firstSt[13]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) + begin + v__h271867 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) + $write("%t : [Ld resp] ", v__h271867); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) + $write("'h%h", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[226:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5641) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5646) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) + $write("LSQHitInfo { ", "waitWPResp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5650) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5654) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) + $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5658) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5663) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5658) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5663) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5658) + $write("'h%h", coreFix_memExe_lsq$getHit[7:1]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5663) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5658) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5663) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[8] && + coreFix_memExe_lsq$getHit[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4940 || + !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4942) && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[8] && + !coreFix_memExe_lsq$getHit[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5663) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5658) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5663) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5677) + $write("[Lr/Sc/Amo resp] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5677) + $write("'h%h", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[226:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5677) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5677) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5681) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5685) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5677) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5677) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5677) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5677) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5688) + $write("[Lr/Sc/Amo resp] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5688) + $write("'h%h", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[226:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5688) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5688) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5688) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5688) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5688) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5688) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5688) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write("[Store resp] idx = %x, ", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[223:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write("SBEntry { ", "addr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write("'h%h", coreFix_memExe_stb$deq[637:580]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(", ", "line: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write("CLine { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(" >"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5598) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5526) + $write("[Lr/Sc/Amo resp] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5526) + $write("'h%h", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[226:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5526) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5526) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5526) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5526) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5526) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5526) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d4932 && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5526) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) + begin + v__h347385 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) + $write("%t : [Ld resp] ", v__h347385); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) + $write("'h%h", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[226:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6314) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6317) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) + $write("LSQHitInfo { ", "waitWPResp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6320) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6323) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) + $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6328) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6331) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6328) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6331) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6328) + $write("'h%h", coreFix_memExe_lsq$getHit[7:1]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6331) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6328) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6331) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6332) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6335) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6331) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6328) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6331) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6339) + $write("[Lr/Sc/Amo resp] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6339) + $write("'h%h", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[226:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6339) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6339) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6340) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] || + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState != + 3'd1) && + coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d6343) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6339) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6339) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6339) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6339) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6348) + $write("[Lr/Sc/Amo resp] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6348) + $write("'h%h", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[226:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6348) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6348) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6348) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6348) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6348) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6348) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6348) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write("[Store resp] idx = %x, ", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[223:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write("SBEntry { ", "addr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write("'h%h", coreFix_memExe_stb$deq[637:580]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(", ", "line: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write("CLine { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(" >"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5602) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6758) + $write("[Lr/Sc/Amo resp] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6758) + $write("'h%h", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[226:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6758) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6758) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6758) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6758) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6758) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6758) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d6758) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0) + begin + v__h423711 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0) + $write("%t : [Ld resp] ", v__h423711); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0) + $write("'h%h", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[226:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0) + $write("LSQHitInfo { ", "waitWPResp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[9]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !coreFix_memExe_lsq$getHit[9]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0) + $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[8]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !coreFix_memExe_lsq$getHit[8]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[8]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !coreFix_memExe_lsq$getHit[8]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[8]) + $write("'h%h", coreFix_memExe_lsq$getHit[7:1]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !coreFix_memExe_lsq$getHit[8]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[8]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !coreFix_memExe_lsq$getHit[8]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[8] && + coreFix_memExe_lsq$getHit[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[8] && + !coreFix_memExe_lsq$getHit[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !coreFix_memExe_lsq$getHit[8]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + coreFix_memExe_lsq$getHit[8]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0 && + !coreFix_memExe_lsq$getHit[8]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2) + $write("[Lr/Sc/Amo resp] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2) + $write("'h%h", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[226:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2 && + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2 && + !SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5638) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd2) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3) + $write("[Lr/Sc/Amo resp] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3) + $write("'h%h", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[226:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3) + $write("; "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd3) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write("[Store resp] idx = %x, ", + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[223:222]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write("SBEntry { ", "addr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write("'h%h", coreFix_memExe_stb$deq[637:580]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(", ", "byteEn: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(", ", "line: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write("CLine { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(" >"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == + 3'd1) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write("[doDeqStQ_St] "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write("StQDeqEntry { ", "instTag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write("InstTag { ", "way: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write("'h%h", coreFix_memExe_lsq$firstSt[252]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(", ", "ptr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write("'h%h", coreFix_memExe_lsq$firstSt[251:247]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(", ", "t: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write("'h%h", coreFix_memExe_lsq$firstSt[246:241], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write(", ", "memFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write("St"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write(", ", "amoFunc: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[238:235] == 4'd0) + $write("Swap"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[238:235] == 4'd1) + $write("Add"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[238:235] == 4'd2) + $write("Xor"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[238:235] == 4'd3) + $write("And"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[238:235] == 4'd4) + $write("Or"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[238:235] == 4'd5) + $write("Min"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[238:235] == 4'd6) + $write("Max"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[238:235] == 4'd7) + $write("Minu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[238:235] == 4'd8) + $write("Maxu"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[238:235] != 4'd0 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd1 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd2 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd3 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd4 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd5 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd6 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd7 && + coreFix_memExe_lsq$firstSt[238:235] != 4'd8) + $write("None"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(", ", "acq: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[234]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + !coreFix_memExe_lsq$firstSt[234]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(", ", "rel: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[233]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + !coreFix_memExe_lsq$firstSt[233]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(", ", "dst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[232]) + $write("tagged Valid "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + !coreFix_memExe_lsq$firstSt[232]) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[232]) + $write("PhyDst { ", "indx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[232]) + $write("'h%h", coreFix_memExe_lsq$firstSt[231:225]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[232]) + $write(", ", "isFpuReg: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[232] && + coreFix_memExe_lsq$firstSt[224]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[232] && + !coreFix_memExe_lsq$firstSt[224]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[232]) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + !coreFix_memExe_lsq$firstSt[232]) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write(", ", "paddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write("'h%h", coreFix_memExe_lsq$firstSt[223:160]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write(", ", "isMMIO: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write(", ", "shiftedBE: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write(", ", "stData: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + coreFix_memExe_lsq$firstSt[142]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem && + !coreFix_memExe_lsq$firstSt[142]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write(", ", "fault: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas && coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit == 2'd3) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h600772 == 2'd0) + v__h836568 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL/mkCoreW.v b/src_SSITH_P3/Verilog_RTL/mkCoreW.v index 88a0737..b9ebe40 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL/mkCoreW.v @@ -1,105 +1,98 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// +// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // +// On Fri Jun 5 17:48:52 BST 2020 // // // Ports: // Name I/O size props // RDY_set_verbosity O 1 const -// RDY_set_htif_addrs O 1 const -// RDY_cpu_reset_server_request_put O 1 reg -// RDY_cpu_reset_server_response_get O 1 reg +// RDY_start O 1 +// cpu_imem_master_awid O 6 +// cpu_imem_master_awaddr O 64 +// cpu_imem_master_awlen O 8 +// cpu_imem_master_awsize O 3 +// cpu_imem_master_awburst O 2 +// cpu_imem_master_awlock O 1 +// cpu_imem_master_awcache O 4 +// cpu_imem_master_awprot O 3 +// cpu_imem_master_awqos O 4 +// cpu_imem_master_awregion O 4 // cpu_imem_master_awvalid O 1 -// cpu_imem_master_awid O 4 reg -// cpu_imem_master_awaddr O 64 reg -// cpu_imem_master_awlen O 8 reg -// cpu_imem_master_awsize O 3 reg -// cpu_imem_master_awburst O 2 reg -// cpu_imem_master_awlock O 1 reg -// cpu_imem_master_awcache O 4 reg -// cpu_imem_master_awprot O 3 reg -// cpu_imem_master_awqos O 4 reg -// cpu_imem_master_awregion O 4 reg +// cpu_imem_master_wdata O 64 +// cpu_imem_master_wstrb O 8 +// cpu_imem_master_wlast O 1 // cpu_imem_master_wvalid O 1 -// cpu_imem_master_wid O 4 reg -// cpu_imem_master_wdata O 64 reg -// cpu_imem_master_wstrb O 8 reg -// cpu_imem_master_wlast O 1 reg // cpu_imem_master_bready O 1 +// cpu_imem_master_arid O 6 +// cpu_imem_master_araddr O 64 +// cpu_imem_master_arlen O 8 +// cpu_imem_master_arsize O 3 +// cpu_imem_master_arburst O 2 +// cpu_imem_master_arlock O 1 +// cpu_imem_master_arcache O 4 +// cpu_imem_master_arprot O 3 +// cpu_imem_master_arqos O 4 +// cpu_imem_master_arregion O 4 // cpu_imem_master_arvalid O 1 -// cpu_imem_master_arid O 4 reg -// cpu_imem_master_araddr O 64 reg -// cpu_imem_master_arlen O 8 reg -// cpu_imem_master_arsize O 3 reg -// cpu_imem_master_arburst O 2 reg -// cpu_imem_master_arlock O 1 reg -// cpu_imem_master_arcache O 4 reg -// cpu_imem_master_arprot O 3 reg -// cpu_imem_master_arqos O 4 reg -// cpu_imem_master_arregion O 4 reg // cpu_imem_master_rready O 1 +// cpu_dmem_master_awid O 6 +// cpu_dmem_master_awaddr O 64 +// cpu_dmem_master_awlen O 8 +// cpu_dmem_master_awsize O 3 +// cpu_dmem_master_awburst O 2 +// cpu_dmem_master_awlock O 1 +// cpu_dmem_master_awcache O 4 +// cpu_dmem_master_awprot O 3 +// cpu_dmem_master_awqos O 4 +// cpu_dmem_master_awregion O 4 // cpu_dmem_master_awvalid O 1 reg -// cpu_dmem_master_awid O 4 reg -// cpu_dmem_master_awaddr O 64 reg -// cpu_dmem_master_awlen O 8 reg -// cpu_dmem_master_awsize O 3 reg -// cpu_dmem_master_awburst O 2 reg -// cpu_dmem_master_awlock O 1 reg -// cpu_dmem_master_awcache O 4 reg -// cpu_dmem_master_awprot O 3 reg -// cpu_dmem_master_awqos O 4 reg -// cpu_dmem_master_awregion O 4 reg -// cpu_dmem_master_wvalid O 1 reg -// cpu_dmem_master_wid O 4 reg // cpu_dmem_master_wdata O 64 reg // cpu_dmem_master_wstrb O 8 reg // cpu_dmem_master_wlast O 1 reg +// cpu_dmem_master_wvalid O 1 reg // cpu_dmem_master_bready O 1 reg +// cpu_dmem_master_arid O 6 +// cpu_dmem_master_araddr O 64 +// cpu_dmem_master_arlen O 8 +// cpu_dmem_master_arsize O 3 +// cpu_dmem_master_arburst O 2 +// cpu_dmem_master_arlock O 1 +// cpu_dmem_master_arcache O 4 +// cpu_dmem_master_arprot O 3 +// cpu_dmem_master_arqos O 4 +// cpu_dmem_master_arregion O 4 // cpu_dmem_master_arvalid O 1 reg -// cpu_dmem_master_arid O 4 reg -// cpu_dmem_master_araddr O 64 reg -// cpu_dmem_master_arlen O 8 reg -// cpu_dmem_master_arsize O 3 reg -// cpu_dmem_master_arburst O 2 reg -// cpu_dmem_master_arlock O 1 reg -// cpu_dmem_master_arcache O 4 reg -// cpu_dmem_master_arprot O 3 reg -// cpu_dmem_master_arqos O 4 reg -// cpu_dmem_master_arregion O 4 reg // cpu_dmem_master_rready O 1 reg -// tv_verifier_info_get_get O 608 reg -// RDY_tv_verifier_info_get_get O 1 reg -// RDY_dm_dmi_read_addr O 1 -// dm_dmi_read_data O 32 -// RDY_dm_dmi_read_data O 1 -// RDY_dm_dmi_write O 1 -// RDY_dm_ndm_reset_req_get_get O 1 reg +// RDY_dmi_read_addr O 1 +// dmi_read_data O 32 +// RDY_dmi_read_data O 1 +// RDY_dmi_write O 1 +// ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_response_put O 1 reg +// RST_N_dm_power_on_reset I 1 reset // CLK I 1 clock // RST_N I 1 reset -// set_verbosity_verbosity I 4 reg +// set_verbosity_verbosity I 4 // set_verbosity_logdelay I 64 unused -// set_htif_addrs_tohost_addr I 64 reg -// set_htif_addrs_fromhost_addr I 64 reg +// start_tohost_addr I 64 +// start_fromhost_addr I 64 // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_bid I 4 reg -// cpu_imem_master_bresp I 2 reg +// cpu_imem_master_bid I 6 +// cpu_imem_master_bresp I 2 // cpu_imem_master_arready I 1 -// cpu_imem_master_rvalid I 1 -// cpu_imem_master_rid I 4 reg -// cpu_imem_master_rdata I 64 reg -// cpu_imem_master_rresp I 2 reg -// cpu_imem_master_rlast I 1 reg +// cpu_imem_master_rid I 6 +// cpu_imem_master_rdata I 64 +// cpu_imem_master_rresp I 2 +// cpu_imem_master_rlast I 1 // cpu_dmem_master_awready I 1 // cpu_dmem_master_wready I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_bid I 4 reg +// cpu_dmem_master_bid I 6 reg // cpu_dmem_master_bresp I 2 reg // cpu_dmem_master_arready I 1 -// cpu_dmem_master_rvalid I 1 -// cpu_dmem_master_rid I 4 reg +// cpu_dmem_master_rid I 6 reg // cpu_dmem_master_rdata I 64 reg // cpu_dmem_master_rresp I 2 reg // cpu_dmem_master_rlast I 1 reg @@ -119,26 +112,25 @@ // core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 -// debug_external_interrupt_req_set_not_clear I 1 -// dm_dmi_read_addr_dm_addr I 7 -// dm_dmi_write_dm_addr I 7 -// dm_dmi_write_dm_word I 32 +// nmi_req_set_not_clear I 1 unused +// dmi_read_addr_dm_addr I 7 reg +// dmi_write_dm_addr I 7 +// dmi_write_dm_word I 32 +// ndm_reset_client_response_put I 1 reg // EN_set_verbosity I 1 -// EN_set_htif_addrs I 1 -// EN_cpu_reset_server_request_put I 1 -// EN_cpu_reset_server_response_get I 1 -// EN_dm_dmi_read_addr I 1 -// EN_dm_dmi_write I 1 -// EN_dm_ndm_reset_req_get_get I 1 -// EN_tv_verifier_info_get_get I 1 -// EN_dm_dmi_read_data I 1 +// EN_start I 1 +// cpu_imem_master_bvalid I 1 +// cpu_imem_master_rvalid I 1 +// cpu_dmem_master_bvalid I 1 +// cpu_dmem_master_rvalid I 1 +// EN_dmi_read_addr I 1 +// EN_dmi_write I 1 +// EN_ndm_reset_client_response_put I 1 +// EN_dmi_read_data I 1 +// EN_ndm_reset_client_request_get I 1 // // Combinational paths from inputs to outputs: -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (dm_dmi_read_addr_dm_addr, EN_dm_dmi_read_addr) -> RDY_dm_dmi_read_data -// (dm_dmi_read_addr_dm_addr, -// EN_dm_dmi_read_addr, -// EN_dm_dmi_read_data) -> dm_dmi_read_data +// EN_dmi_read_data -> dmi_read_data // // @@ -155,7 +147,8 @@ `define BSV_RESET_EDGE negedge `endif -module mkCoreW(CLK, +module mkCoreW(RST_N_dm_power_on_reset, + CLK, RST_N, set_verbosity_verbosity, @@ -163,18 +156,10 @@ module mkCoreW(CLK, EN_set_verbosity, RDY_set_verbosity, - set_htif_addrs_tohost_addr, - set_htif_addrs_fromhost_addr, - EN_set_htif_addrs, - RDY_set_htif_addrs, - - EN_cpu_reset_server_request_put, - RDY_cpu_reset_server_request_put, - - EN_cpu_reset_server_response_get, - RDY_cpu_reset_server_response_get, - - cpu_imem_master_awvalid, + start_tohost_addr, + start_fromhost_addr, + EN_start, + RDY_start, cpu_imem_master_awid, @@ -196,28 +181,26 @@ module mkCoreW(CLK, cpu_imem_master_awregion, + cpu_imem_master_awvalid, + cpu_imem_master_awready, - cpu_imem_master_wvalid, - - cpu_imem_master_wid, - cpu_imem_master_wdata, cpu_imem_master_wstrb, cpu_imem_master_wlast, + cpu_imem_master_wvalid, + cpu_imem_master_wready, - cpu_imem_master_bvalid, cpu_imem_master_bid, cpu_imem_master_bresp, + cpu_imem_master_bvalid, cpu_imem_master_bready, - cpu_imem_master_arvalid, - cpu_imem_master_arid, cpu_imem_master_araddr, @@ -238,18 +221,18 @@ module mkCoreW(CLK, cpu_imem_master_arregion, + cpu_imem_master_arvalid, + cpu_imem_master_arready, - cpu_imem_master_rvalid, cpu_imem_master_rid, cpu_imem_master_rdata, cpu_imem_master_rresp, cpu_imem_master_rlast, + cpu_imem_master_rvalid, cpu_imem_master_rready, - cpu_dmem_master_awvalid, - cpu_dmem_master_awid, cpu_dmem_master_awaddr, @@ -270,28 +253,26 @@ module mkCoreW(CLK, cpu_dmem_master_awregion, + cpu_dmem_master_awvalid, + cpu_dmem_master_awready, - cpu_dmem_master_wvalid, - - cpu_dmem_master_wid, - cpu_dmem_master_wdata, cpu_dmem_master_wstrb, cpu_dmem_master_wlast, + cpu_dmem_master_wvalid, + cpu_dmem_master_wready, - cpu_dmem_master_bvalid, cpu_dmem_master_bid, cpu_dmem_master_bresp, + cpu_dmem_master_bvalid, cpu_dmem_master_bready, - cpu_dmem_master_arvalid, - cpu_dmem_master_arid, cpu_dmem_master_araddr, @@ -312,13 +293,15 @@ module mkCoreW(CLK, cpu_dmem_master_arregion, + cpu_dmem_master_arvalid, + cpu_dmem_master_arready, - cpu_dmem_master_rvalid, cpu_dmem_master_rid, cpu_dmem_master_rdata, cpu_dmem_master_rresp, cpu_dmem_master_rlast, + cpu_dmem_master_rvalid, cpu_dmem_master_rready, @@ -354,27 +337,29 @@ module mkCoreW(CLK, core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - debug_external_interrupt_req_set_not_clear, + nmi_req_set_not_clear, - EN_tv_verifier_info_get_get, - tv_verifier_info_get_get, - RDY_tv_verifier_info_get_get, + dmi_read_addr_dm_addr, + EN_dmi_read_addr, + RDY_dmi_read_addr, - dm_dmi_read_addr_dm_addr, - EN_dm_dmi_read_addr, - RDY_dm_dmi_read_addr, + EN_dmi_read_data, + dmi_read_data, + RDY_dmi_read_data, - EN_dm_dmi_read_data, - dm_dmi_read_data, - RDY_dm_dmi_read_data, + dmi_write_dm_addr, + dmi_write_dm_word, + EN_dmi_write, + RDY_dmi_write, - dm_dmi_write_dm_addr, - dm_dmi_write_dm_word, - EN_dm_dmi_write, - RDY_dm_dmi_write, + EN_ndm_reset_client_request_get, + ndm_reset_client_request_get, + RDY_ndm_reset_client_request_get, - EN_dm_ndm_reset_req_get_get, - RDY_dm_ndm_reset_req_get_get); + ndm_reset_client_response_put, + EN_ndm_reset_client_response_put, + RDY_ndm_reset_client_response_put); + input RST_N_dm_power_on_reset; input CLK; input RST_N; @@ -384,246 +369,232 @@ module mkCoreW(CLK, input EN_set_verbosity; output RDY_set_verbosity; - // action method set_htif_addrs - input [63 : 0] set_htif_addrs_tohost_addr; - input [63 : 0] set_htif_addrs_fromhost_addr; - input EN_set_htif_addrs; - output RDY_set_htif_addrs; + // action method start + input [63 : 0] start_tohost_addr; + input [63 : 0] start_fromhost_addr; + input EN_start; + output RDY_start; - // action method cpu_reset_server_request_put - input EN_cpu_reset_server_request_put; - output RDY_cpu_reset_server_request_put; + // value method cpu_imem_master_aw_awid + output [5 : 0] cpu_imem_master_awid; - // action method cpu_reset_server_response_get - input EN_cpu_reset_server_response_get; - output RDY_cpu_reset_server_response_get; - - // value method cpu_imem_master_m_awvalid - output cpu_imem_master_awvalid; - - // value method cpu_imem_master_m_awid - output [3 : 0] cpu_imem_master_awid; - - // value method cpu_imem_master_m_awaddr + // value method cpu_imem_master_aw_awaddr output [63 : 0] cpu_imem_master_awaddr; - // value method cpu_imem_master_m_awlen + // value method cpu_imem_master_aw_awlen output [7 : 0] cpu_imem_master_awlen; - // value method cpu_imem_master_m_awsize + // value method cpu_imem_master_aw_awsize output [2 : 0] cpu_imem_master_awsize; - // value method cpu_imem_master_m_awburst + // value method cpu_imem_master_aw_awburst output [1 : 0] cpu_imem_master_awburst; - // value method cpu_imem_master_m_awlock + // value method cpu_imem_master_aw_awlock output cpu_imem_master_awlock; - // value method cpu_imem_master_m_awcache + // value method cpu_imem_master_aw_awcache output [3 : 0] cpu_imem_master_awcache; - // value method cpu_imem_master_m_awprot + // value method cpu_imem_master_aw_awprot output [2 : 0] cpu_imem_master_awprot; - // value method cpu_imem_master_m_awqos + // value method cpu_imem_master_aw_awqos output [3 : 0] cpu_imem_master_awqos; - // value method cpu_imem_master_m_awregion + // value method cpu_imem_master_aw_awregion output [3 : 0] cpu_imem_master_awregion; - // value method cpu_imem_master_m_awuser + // value method cpu_imem_master_aw_awuser - // action method cpu_imem_master_m_awready + // value method cpu_imem_master_aw_awvalid + output cpu_imem_master_awvalid; + + // action method cpu_imem_master_aw_awready input cpu_imem_master_awready; - // value method cpu_imem_master_m_wvalid - output cpu_imem_master_wvalid; - - // value method cpu_imem_master_m_wid - output [3 : 0] cpu_imem_master_wid; - - // value method cpu_imem_master_m_wdata + // value method cpu_imem_master_w_wdata output [63 : 0] cpu_imem_master_wdata; - // value method cpu_imem_master_m_wstrb + // value method cpu_imem_master_w_wstrb output [7 : 0] cpu_imem_master_wstrb; - // value method cpu_imem_master_m_wlast + // value method cpu_imem_master_w_wlast output cpu_imem_master_wlast; - // value method cpu_imem_master_m_wuser + // value method cpu_imem_master_w_wuser - // action method cpu_imem_master_m_wready + // value method cpu_imem_master_w_wvalid + output cpu_imem_master_wvalid; + + // action method cpu_imem_master_w_wready input cpu_imem_master_wready; - // action method cpu_imem_master_m_bvalid - input cpu_imem_master_bvalid; - input [3 : 0] cpu_imem_master_bid; + // action method cpu_imem_master_b_bflit + input [5 : 0] cpu_imem_master_bid; input [1 : 0] cpu_imem_master_bresp; + input cpu_imem_master_bvalid; - // value method cpu_imem_master_m_bready + // value method cpu_imem_master_b_bready output cpu_imem_master_bready; - // value method cpu_imem_master_m_arvalid - output cpu_imem_master_arvalid; + // value method cpu_imem_master_ar_arid + output [5 : 0] cpu_imem_master_arid; - // value method cpu_imem_master_m_arid - output [3 : 0] cpu_imem_master_arid; - - // value method cpu_imem_master_m_araddr + // value method cpu_imem_master_ar_araddr output [63 : 0] cpu_imem_master_araddr; - // value method cpu_imem_master_m_arlen + // value method cpu_imem_master_ar_arlen output [7 : 0] cpu_imem_master_arlen; - // value method cpu_imem_master_m_arsize + // value method cpu_imem_master_ar_arsize output [2 : 0] cpu_imem_master_arsize; - // value method cpu_imem_master_m_arburst + // value method cpu_imem_master_ar_arburst output [1 : 0] cpu_imem_master_arburst; - // value method cpu_imem_master_m_arlock + // value method cpu_imem_master_ar_arlock output cpu_imem_master_arlock; - // value method cpu_imem_master_m_arcache + // value method cpu_imem_master_ar_arcache output [3 : 0] cpu_imem_master_arcache; - // value method cpu_imem_master_m_arprot + // value method cpu_imem_master_ar_arprot output [2 : 0] cpu_imem_master_arprot; - // value method cpu_imem_master_m_arqos + // value method cpu_imem_master_ar_arqos output [3 : 0] cpu_imem_master_arqos; - // value method cpu_imem_master_m_arregion + // value method cpu_imem_master_ar_arregion output [3 : 0] cpu_imem_master_arregion; - // value method cpu_imem_master_m_aruser + // value method cpu_imem_master_ar_aruser - // action method cpu_imem_master_m_arready + // value method cpu_imem_master_ar_arvalid + output cpu_imem_master_arvalid; + + // action method cpu_imem_master_ar_arready input cpu_imem_master_arready; - // action method cpu_imem_master_m_rvalid - input cpu_imem_master_rvalid; - input [3 : 0] cpu_imem_master_rid; + // action method cpu_imem_master_r_rflit + input [5 : 0] cpu_imem_master_rid; input [63 : 0] cpu_imem_master_rdata; input [1 : 0] cpu_imem_master_rresp; input cpu_imem_master_rlast; + input cpu_imem_master_rvalid; - // value method cpu_imem_master_m_rready + // value method cpu_imem_master_r_rready output cpu_imem_master_rready; - // value method cpu_dmem_master_m_awvalid - output cpu_dmem_master_awvalid; + // value method cpu_dmem_master_aw_awid + output [5 : 0] cpu_dmem_master_awid; - // value method cpu_dmem_master_m_awid - output [3 : 0] cpu_dmem_master_awid; - - // value method cpu_dmem_master_m_awaddr + // value method cpu_dmem_master_aw_awaddr output [63 : 0] cpu_dmem_master_awaddr; - // value method cpu_dmem_master_m_awlen + // value method cpu_dmem_master_aw_awlen output [7 : 0] cpu_dmem_master_awlen; - // value method cpu_dmem_master_m_awsize + // value method cpu_dmem_master_aw_awsize output [2 : 0] cpu_dmem_master_awsize; - // value method cpu_dmem_master_m_awburst + // value method cpu_dmem_master_aw_awburst output [1 : 0] cpu_dmem_master_awburst; - // value method cpu_dmem_master_m_awlock + // value method cpu_dmem_master_aw_awlock output cpu_dmem_master_awlock; - // value method cpu_dmem_master_m_awcache + // value method cpu_dmem_master_aw_awcache output [3 : 0] cpu_dmem_master_awcache; - // value method cpu_dmem_master_m_awprot + // value method cpu_dmem_master_aw_awprot output [2 : 0] cpu_dmem_master_awprot; - // value method cpu_dmem_master_m_awqos + // value method cpu_dmem_master_aw_awqos output [3 : 0] cpu_dmem_master_awqos; - // value method cpu_dmem_master_m_awregion + // value method cpu_dmem_master_aw_awregion output [3 : 0] cpu_dmem_master_awregion; - // value method cpu_dmem_master_m_awuser + // value method cpu_dmem_master_aw_awuser - // action method cpu_dmem_master_m_awready + // value method cpu_dmem_master_aw_awvalid + output cpu_dmem_master_awvalid; + + // action method cpu_dmem_master_aw_awready input cpu_dmem_master_awready; - // value method cpu_dmem_master_m_wvalid - output cpu_dmem_master_wvalid; - - // value method cpu_dmem_master_m_wid - output [3 : 0] cpu_dmem_master_wid; - - // value method cpu_dmem_master_m_wdata + // value method cpu_dmem_master_w_wdata output [63 : 0] cpu_dmem_master_wdata; - // value method cpu_dmem_master_m_wstrb + // value method cpu_dmem_master_w_wstrb output [7 : 0] cpu_dmem_master_wstrb; - // value method cpu_dmem_master_m_wlast + // value method cpu_dmem_master_w_wlast output cpu_dmem_master_wlast; - // value method cpu_dmem_master_m_wuser + // value method cpu_dmem_master_w_wuser - // action method cpu_dmem_master_m_wready + // value method cpu_dmem_master_w_wvalid + output cpu_dmem_master_wvalid; + + // action method cpu_dmem_master_w_wready input cpu_dmem_master_wready; - // action method cpu_dmem_master_m_bvalid - input cpu_dmem_master_bvalid; - input [3 : 0] cpu_dmem_master_bid; + // action method cpu_dmem_master_b_bflit + input [5 : 0] cpu_dmem_master_bid; input [1 : 0] cpu_dmem_master_bresp; + input cpu_dmem_master_bvalid; - // value method cpu_dmem_master_m_bready + // value method cpu_dmem_master_b_bready output cpu_dmem_master_bready; - // value method cpu_dmem_master_m_arvalid - output cpu_dmem_master_arvalid; + // value method cpu_dmem_master_ar_arid + output [5 : 0] cpu_dmem_master_arid; - // value method cpu_dmem_master_m_arid - output [3 : 0] cpu_dmem_master_arid; - - // value method cpu_dmem_master_m_araddr + // value method cpu_dmem_master_ar_araddr output [63 : 0] cpu_dmem_master_araddr; - // value method cpu_dmem_master_m_arlen + // value method cpu_dmem_master_ar_arlen output [7 : 0] cpu_dmem_master_arlen; - // value method cpu_dmem_master_m_arsize + // value method cpu_dmem_master_ar_arsize output [2 : 0] cpu_dmem_master_arsize; - // value method cpu_dmem_master_m_arburst + // value method cpu_dmem_master_ar_arburst output [1 : 0] cpu_dmem_master_arburst; - // value method cpu_dmem_master_m_arlock + // value method cpu_dmem_master_ar_arlock output cpu_dmem_master_arlock; - // value method cpu_dmem_master_m_arcache + // value method cpu_dmem_master_ar_arcache output [3 : 0] cpu_dmem_master_arcache; - // value method cpu_dmem_master_m_arprot + // value method cpu_dmem_master_ar_arprot output [2 : 0] cpu_dmem_master_arprot; - // value method cpu_dmem_master_m_arqos + // value method cpu_dmem_master_ar_arqos output [3 : 0] cpu_dmem_master_arqos; - // value method cpu_dmem_master_m_arregion + // value method cpu_dmem_master_ar_arregion output [3 : 0] cpu_dmem_master_arregion; - // value method cpu_dmem_master_m_aruser + // value method cpu_dmem_master_ar_aruser - // action method cpu_dmem_master_m_arready + // value method cpu_dmem_master_ar_arvalid + output cpu_dmem_master_arvalid; + + // action method cpu_dmem_master_ar_arready input cpu_dmem_master_arready; - // action method cpu_dmem_master_m_rvalid - input cpu_dmem_master_rvalid; - input [3 : 0] cpu_dmem_master_rid; + // action method cpu_dmem_master_r_rflit + input [5 : 0] cpu_dmem_master_rid; input [63 : 0] cpu_dmem_master_rdata; input [1 : 0] cpu_dmem_master_rresp; input cpu_dmem_master_rlast; + input cpu_dmem_master_rvalid; - // value method cpu_dmem_master_m_rready + // value method cpu_dmem_master_r_rready output cpu_dmem_master_rready; // action method core_external_interrupt_sources_0_m_interrupt_req @@ -674,67 +645,65 @@ module mkCoreW(CLK, // action method core_external_interrupt_sources_15_m_interrupt_req input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; - // action method debug_external_interrupt_req - input debug_external_interrupt_req_set_not_clear; + // action method nmi_req + input nmi_req_set_not_clear; - // actionvalue method tv_verifier_info_get_get - input EN_tv_verifier_info_get_get; - output [607 : 0] tv_verifier_info_get_get; - output RDY_tv_verifier_info_get_get; + // action method dmi_read_addr + input [6 : 0] dmi_read_addr_dm_addr; + input EN_dmi_read_addr; + output RDY_dmi_read_addr; - // action method dm_dmi_read_addr - input [6 : 0] dm_dmi_read_addr_dm_addr; - input EN_dm_dmi_read_addr; - output RDY_dm_dmi_read_addr; + // actionvalue method dmi_read_data + input EN_dmi_read_data; + output [31 : 0] dmi_read_data; + output RDY_dmi_read_data; - // actionvalue method dm_dmi_read_data - input EN_dm_dmi_read_data; - output [31 : 0] dm_dmi_read_data; - output RDY_dm_dmi_read_data; + // action method dmi_write + input [6 : 0] dmi_write_dm_addr; + input [31 : 0] dmi_write_dm_word; + input EN_dmi_write; + output RDY_dmi_write; - // action method dm_dmi_write - input [6 : 0] dm_dmi_write_dm_addr; - input [31 : 0] dm_dmi_write_dm_word; - input EN_dm_dmi_write; - output RDY_dm_dmi_write; + // actionvalue method ndm_reset_client_request_get + input EN_ndm_reset_client_request_get; + output ndm_reset_client_request_get; + output RDY_ndm_reset_client_request_get; - // action method dm_ndm_reset_req_get_get - input EN_dm_ndm_reset_req_get_get; - output RDY_dm_ndm_reset_req_get_get; + // action method ndm_reset_client_response_put + input ndm_reset_client_response_put; + input EN_ndm_reset_client_response_put; + output RDY_ndm_reset_client_response_put; // signals for module outputs - wire [607 : 0] tv_verifier_info_get_get; wire [63 : 0] cpu_dmem_master_araddr, cpu_dmem_master_awaddr, cpu_dmem_master_wdata, cpu_imem_master_araddr, cpu_imem_master_awaddr, cpu_imem_master_wdata; - wire [31 : 0] dm_dmi_read_data; + wire [31 : 0] dmi_read_data; wire [7 : 0] cpu_dmem_master_arlen, cpu_dmem_master_awlen, cpu_dmem_master_wstrb, cpu_imem_master_arlen, cpu_imem_master_awlen, cpu_imem_master_wstrb; + wire [5 : 0] cpu_dmem_master_arid, + cpu_dmem_master_awid, + cpu_imem_master_arid, + cpu_imem_master_awid; wire [3 : 0] cpu_dmem_master_arcache, - cpu_dmem_master_arid, cpu_dmem_master_arqos, cpu_dmem_master_arregion, cpu_dmem_master_awcache, - cpu_dmem_master_awid, cpu_dmem_master_awqos, cpu_dmem_master_awregion, - cpu_dmem_master_wid, cpu_imem_master_arcache, - cpu_imem_master_arid, cpu_imem_master_arqos, cpu_imem_master_arregion, cpu_imem_master_awcache, - cpu_imem_master_awid, cpu_imem_master_awqos, - cpu_imem_master_awregion, - cpu_imem_master_wid; + cpu_imem_master_awregion; wire [2 : 0] cpu_dmem_master_arprot, cpu_dmem_master_arsize, cpu_dmem_master_awprot, @@ -747,15 +716,13 @@ module mkCoreW(CLK, cpu_dmem_master_awburst, cpu_imem_master_arburst, cpu_imem_master_awburst; - wire RDY_cpu_reset_server_request_put, - RDY_cpu_reset_server_response_get, - RDY_dm_dmi_read_addr, - RDY_dm_dmi_read_data, - RDY_dm_dmi_write, - RDY_dm_ndm_reset_req_get_get, - RDY_set_htif_addrs, + wire RDY_dmi_read_addr, + RDY_dmi_read_data, + RDY_dmi_write, + RDY_ndm_reset_client_request_get, + RDY_ndm_reset_client_response_put, RDY_set_verbosity, - RDY_tv_verifier_info_get_get, + RDY_start, cpu_dmem_master_arlock, cpu_dmem_master_arvalid, cpu_dmem_master_awlock, @@ -771,36 +738,452 @@ module mkCoreW(CLK, cpu_imem_master_bready, cpu_imem_master_rready, cpu_imem_master_wlast, - cpu_imem_master_wvalid; + cpu_imem_master_wvalid, + ndm_reset_client_request_get; - // register hart0_halt - reg hart0_halt; - wire hart0_halt$D_IN, hart0_halt$EN; + // inlined wires + wire [172 : 0] split_0_doPut$wget, split_1_doPut$wget, split_2_doPut$wget; + wire [99 : 0] tagController_tmp_shimMaster_arff_rv$port0__write_1, + tagController_tmp_shimMaster_arff_rv$port1__read, + tagController_tmp_shimMaster_arff_rv$port2__read, + tagController_tmp_shimMaster_arff_rv$port3__read, + tagController_tmp_shimMaster_awff_rv$port0__write_1, + tagController_tmp_shimMaster_awff_rv$port1__read, + tagController_tmp_shimMaster_awff_rv$port2__read, + tagController_tmp_shimMaster_awff_rv$port3__read; + wire [98 : 0] tagController_tmp_shimSlave_arff_rv$port0__write_1, + tagController_tmp_shimSlave_arff_rv$port1__read, + tagController_tmp_shimSlave_arff_rv$port2__read, + tagController_tmp_shimSlave_arff_rv$port3__read, + tagController_tmp_shimSlave_awff_rv$port0__write_1, + tagController_tmp_shimSlave_awff_rv$port1__read, + tagController_tmp_shimSlave_awff_rv$port2__read, + tagController_tmp_shimSlave_awff_rv$port3__read, + ug_uncached_mem_shim_master_u_ar_peekWire$wget, + ug_uncached_mem_shim_master_u_aw_peekWire$wget; + wire [97 : 0] ssNoSynth_0_ar_buffer_enqw$wget, + ssNoSynth_1_ar_buffer_enqw$wget, + ssNoSynth_1_aw_buffer_enqw$wget, + ssNoSynth_2_ar_buffer_enqw$wget, + ssNoSynth_2_aw_buffer_enqw$wget, + tagController_tmp_ug_slave_u_ar_putWire$wget, + tagController_tmp_ug_slave_u_aw_putWire$wget; + wire [96 : 0] ifcs_0_1_noRoute_currentReq$port0__write_1, + ifcs_0_1_noRoute_currentReq$port1__read, + ifcs_0_noRoute_inner_currentReq$port0__write_1, + ifcs_0_noRoute_inner_currentReq$port1__read, + ifcs_1_1_noRoute_currentReq$port0__write_1, + ifcs_1_1_noRoute_currentReq$port1__read, + ifcs_1_noRoute_inner_currentReq$port0__write_1, + ifcs_1_noRoute_inner_currentReq$port1__read; + wire [74 : 0] tagController_tmp_shimSlave_wff_rv$port0__write_1, + tagController_tmp_shimSlave_wff_rv$port1__read, + tagController_tmp_shimSlave_wff_rv$port2__read, + tagController_tmp_shimSlave_wff_rv$port3__read; + wire [73 : 0] ssNoSynth_1_w_buffer_enqw$wget, + ssNoSynth_2_w_buffer_enqw$wget, + tagController_tmp_shimMaster_rff_rv$port0__write_1, + tagController_tmp_shimMaster_rff_rv$port1__read, + tagController_tmp_shimMaster_rff_rv$port2__read, + tagController_tmp_shimMaster_rff_rv$port3__read, + tagController_tmp_shimMaster_wff_rv$port0__write_1, + tagController_tmp_shimMaster_wff_rv$port1__read, + tagController_tmp_shimMaster_wff_rv$port2__read, + tagController_tmp_shimMaster_wff_rv$port3__read, + tagController_tmp_shimSlave_rff_rv$port0__write_1, + tagController_tmp_shimSlave_rff_rv$port1__read, + tagController_tmp_shimSlave_rff_rv$port2__read, + tagController_tmp_shimSlave_rff_rv$port3__read, + tagController_tmp_ug_slave_u_w_putWire$wget; + wire [72 : 0] tagController_tmp_ug_master_u_r_putWire$wget, + tmp2_r_buffer_enqw$wget, + ug_uncached_mem_shim_master_u_r_putWire$wget; + wire [71 : 0] msNoSynth_0_r_buffer_enqw$wget, + msNoSynth_1_r_buffer_enqw$wget, + tmp0_r_buffer_enqw$wget; + wire [8 : 0] ifcs_0_1_noRoute_flitCount$port0__write_1, + ifcs_0_1_noRoute_flitCount$port1__write_1, + ifcs_0_1_noRoute_flitCount$port2__read, + ifcs_1_1_noRoute_flitCount$port0__write_1, + ifcs_1_1_noRoute_flitCount$port1__write_1, + ifcs_1_1_noRoute_flitCount$port2__read, + tagController_tmp_shimMaster_bff_rv$port0__write_1, + tagController_tmp_shimMaster_bff_rv$port1__read, + tagController_tmp_shimMaster_bff_rv$port2__read, + tagController_tmp_shimMaster_bff_rv$port3__read; + wire [7 : 0] tagController_tmp_shimSlave_bff_rv$port0__write_1, + tagController_tmp_shimSlave_bff_rv$port1__read, + tagController_tmp_shimSlave_bff_rv$port2__read, + tagController_tmp_shimSlave_bff_rv$port3__read, + tagController_tmp_ug_master_u_b_putWire$wget, + ug_uncached_mem_shim_master_u_b_putWire$wget; + wire [6 : 0] tmp2_b_buffer_enqw$wget; + wire [5 : 0] msNoSynth_0_b_buffer_enqw$wget, + msNoSynth_1_b_buffer_enqw$wget, + tmp0_b_buffer_enqw$wget; + wire flitToSink_0$whas, + flitToSink_1$whas, + flitToSink_1_0$whas, + flitToSink_1_0_1$whas, + flitToSink_1_1$whas, + flitToSink_1_1_0$whas, + flitToSink_1_1_1$whas, + flitToSink_1_1_1_1$whas, + flitToSink_1_2$whas, + flitToSink_2$whas, + ifcs_0_noRoute_inner_currentReq$EN_port0__write, + ifcs_0_noRoute_inner_pendingReq$EN_port0__write, + ifcs_0_noRoute_inner_pendingReq$port1__read, + ifcs_0_noRoute_inner_pendingReq$port2__read, + ifcs_1_noRoute_inner_currentReq$EN_port0__write, + ifcs_1_noRoute_inner_pendingReq$EN_port0__write, + ifcs_1_noRoute_inner_pendingReq$port1__read, + ifcs_1_noRoute_inner_pendingReq$port2__read, + merged_0_doDrop$whas, + merged_1_doDrop$whas, + msNoSynth_0_ar_dwReady$whas, + msNoSynth_0_b_buffer_enqw$whas, + msNoSynth_0_r_buffer_enqw$whas, + msNoSynth_0_w_dwReady$whas, + msNoSynth_1_ar_dwReady$whas, + msNoSynth_1_b_buffer_enqw$whas, + msNoSynth_1_r_buffer_enqw$whas, + msNoSynth_1_w_dwReady$whas, + reqWires_0$wget, + reqWires_1$wget, + reqWires_1_0$wget, + reqWires_1_0_1$wget, + reqWires_1_1$wget, + reqWires_1_1_0$wget, + reqWires_1_1_1$wget, + reqWires_1_1_1_1$wget, + reqWires_1_1_2$wget, + reqWires_1_2$wget, + sourceSelect_1_0$whas, + sourceSelect_1_0_1$whas, + sourceSelect_1_1$whas, + sourceSelect_1_1_1$whas, + sourceSelect_1_2$whas, + ssNoSynth_0_b_dwReady$whas, + ssNoSynth_0_r_dwReady$whas, + ssNoSynth_0_w_buffer_enqw$whas, + ssNoSynth_1_b_dwReady$whas, + ssNoSynth_1_r_dwReady$whas, + ssNoSynth_1_w_buffer_enqw$whas, + ssNoSynth_2_b_dwReady$whas, + ssNoSynth_2_r_dwReady$whas, + ssNoSynth_2_w_buffer_enqw$whas, + tagController_tmp_shimMaster_arff_rv$EN_port0__write, + tagController_tmp_shimMaster_awff_rv$EN_port0__write, + tagController_tmp_shimMaster_wff_rv$EN_port0__write, + tagController_tmp_shimSlave_bff_rv$EN_port0__write, + tagController_tmp_shimSlave_rff_rv$EN_port0__write, + tagController_tmp_ug_master_u_ar_dropWire$whas, + tagController_tmp_ug_master_u_aw_dropWire$whas, + tagController_tmp_ug_master_u_b_putWire$whas, + tagController_tmp_ug_master_u_r_putWire$whas, + tagController_tmp_ug_master_u_w_dropWire$whas, + tmp0_ar_dwReady$whas, + tmp0_aw_dwReady$whas, + tmp0_b_buffer_enqw$whas, + tmp0_r_buffer_enqw$whas, + tmp0_w_dwReady$whas, + ug_uncached_mem_shim_master_u_ar_dropWire$whas, + ug_uncached_mem_shim_master_u_aw_dropWire$whas, + ug_uncached_mem_shim_master_u_b_putWire$whas, + ug_uncached_mem_shim_master_u_r_putWire$whas, + ug_uncached_mem_shim_master_u_w_dropWire$whas; - // register once - reg once; - wire once$D_IN, once$EN; + // register activeSource_0 + reg activeSource_0; + wire activeSource_0$D_IN, activeSource_0$EN; + + // register activeSource_1 + reg activeSource_1; + wire activeSource_1$D_IN, activeSource_1$EN; + + // register activeSource_1_0 + reg activeSource_1_0; + wire activeSource_1_0$D_IN, activeSource_1_0$EN; + + // register activeSource_1_0_1 + reg activeSource_1_0_1; + wire activeSource_1_0_1$D_IN, activeSource_1_0_1$EN; + + // register activeSource_1_1 + reg activeSource_1_1; + wire activeSource_1_1$D_IN, activeSource_1_1$EN; + + // register activeSource_1_1_0 + reg activeSource_1_1_0; + reg activeSource_1_1_0$D_IN; + wire activeSource_1_1_0$EN; + + // register activeSource_1_1_1 + reg activeSource_1_1_1; + wire activeSource_1_1_1$D_IN, activeSource_1_1_1$EN; + + // register activeSource_1_1_1_1 + reg activeSource_1_1_1_1; + reg activeSource_1_1_1_1$D_IN; + wire activeSource_1_1_1_1$EN; + + // register activeSource_1_1_2 + reg activeSource_1_1_2; + reg activeSource_1_1_2$D_IN; + wire activeSource_1_1_2$EN; + + // register activeSource_1_2 + reg activeSource_1_2; + wire activeSource_1_2$D_IN, activeSource_1_2$EN; + + // register arbiter_1_1_firstHot + reg arbiter_1_1_firstHot; + wire arbiter_1_1_firstHot$D_IN, arbiter_1_1_firstHot$EN; + + // register arbiter_1_1_lastSelect + reg arbiter_1_1_lastSelect; + wire arbiter_1_1_lastSelect$D_IN, arbiter_1_1_lastSelect$EN; + + // register arbiter_1_1_lastSelect_1 + reg arbiter_1_1_lastSelect_1; + wire arbiter_1_1_lastSelect_1$D_IN, arbiter_1_1_lastSelect_1$EN; + + // register arbiter_1_firstHot + reg arbiter_1_firstHot; + wire arbiter_1_firstHot$D_IN, arbiter_1_firstHot$EN; + + // register arbiter_1_firstHot_1 + reg arbiter_1_firstHot_1; + wire arbiter_1_firstHot_1$D_IN, arbiter_1_firstHot_1$EN; + + // register arbiter_1_lastSelect + reg arbiter_1_lastSelect; + wire arbiter_1_lastSelect$D_IN, arbiter_1_lastSelect$EN; + + // register arbiter_1_lastSelect_1 + reg arbiter_1_lastSelect_1; + wire arbiter_1_lastSelect_1$D_IN, arbiter_1_lastSelect_1$EN; + + // register arbiter_1_lastSelect_2 + reg arbiter_1_lastSelect_2; + wire arbiter_1_lastSelect_2$D_IN, arbiter_1_lastSelect_2$EN; + + // register arbiter_firstHot + reg arbiter_firstHot; + wire arbiter_firstHot$D_IN, arbiter_firstHot$EN; + + // register arbiter_lastSelect + reg arbiter_lastSelect; + wire arbiter_lastSelect$D_IN, arbiter_lastSelect$EN; + + // register ifcs_0_1_noRoute_currentReq + reg [96 : 0] ifcs_0_1_noRoute_currentReq; + wire [96 : 0] ifcs_0_1_noRoute_currentReq$D_IN; + wire ifcs_0_1_noRoute_currentReq$EN; + + // register ifcs_0_1_noRoute_flitCount + reg [8 : 0] ifcs_0_1_noRoute_flitCount; + wire [8 : 0] ifcs_0_1_noRoute_flitCount$D_IN; + wire ifcs_0_1_noRoute_flitCount$EN; + + // register ifcs_0_1_state + reg [1 : 0] ifcs_0_1_state; + wire [1 : 0] ifcs_0_1_state$D_IN; + wire ifcs_0_1_state$EN; + + // register ifcs_0_1_state_1 + reg ifcs_0_1_state_1; + wire ifcs_0_1_state_1$D_IN, ifcs_0_1_state_1$EN; + + // register ifcs_0_noRoute_inner_currentReq + reg [96 : 0] ifcs_0_noRoute_inner_currentReq; + wire [96 : 0] ifcs_0_noRoute_inner_currentReq$D_IN; + wire ifcs_0_noRoute_inner_currentReq$EN; + + // register ifcs_0_noRoute_inner_pendingReq + reg ifcs_0_noRoute_inner_pendingReq; + wire ifcs_0_noRoute_inner_pendingReq$D_IN, + ifcs_0_noRoute_inner_pendingReq$EN; + + // register ifcs_0_state + reg [1 : 0] ifcs_0_state; + reg [1 : 0] ifcs_0_state$D_IN; + wire ifcs_0_state$EN; + + // register ifcs_0_state_1 + reg ifcs_0_state_1; + wire ifcs_0_state_1$D_IN, ifcs_0_state_1$EN; + + // register ifcs_1_1_noRoute_currentReq + reg [96 : 0] ifcs_1_1_noRoute_currentReq; + wire [96 : 0] ifcs_1_1_noRoute_currentReq$D_IN; + wire ifcs_1_1_noRoute_currentReq$EN; + + // register ifcs_1_1_noRoute_flitCount + reg [8 : 0] ifcs_1_1_noRoute_flitCount; + wire [8 : 0] ifcs_1_1_noRoute_flitCount$D_IN; + wire ifcs_1_1_noRoute_flitCount$EN; + + // register ifcs_1_1_state + reg [1 : 0] ifcs_1_1_state; + wire [1 : 0] ifcs_1_1_state$D_IN; + wire ifcs_1_1_state$EN; + + // register ifcs_1_1_state_1 + reg ifcs_1_1_state_1; + wire ifcs_1_1_state_1$D_IN, ifcs_1_1_state_1$EN; + + // register ifcs_1_noRoute_inner_currentReq + reg [96 : 0] ifcs_1_noRoute_inner_currentReq; + wire [96 : 0] ifcs_1_noRoute_inner_currentReq$D_IN; + wire ifcs_1_noRoute_inner_currentReq$EN; + + // register ifcs_1_noRoute_inner_pendingReq + reg ifcs_1_noRoute_inner_pendingReq; + wire ifcs_1_noRoute_inner_pendingReq$D_IN, + ifcs_1_noRoute_inner_pendingReq$EN; + + // register ifcs_1_state + reg [1 : 0] ifcs_1_state; + reg [1 : 0] ifcs_1_state$D_IN; + wire ifcs_1_state$EN; + + // register ifcs_1_state_1 + reg ifcs_1_state_1; + wire ifcs_1_state_1$D_IN, ifcs_1_state_1$EN; + + // register ifcs_2_1_state + reg ifcs_2_1_state; + wire ifcs_2_1_state$D_IN, ifcs_2_1_state$EN; + + // register ifcs_2_state + reg ifcs_2_state; + wire ifcs_2_state$D_IN, ifcs_2_state$EN; + + // register merged_0_flitLeft + reg [7 : 0] merged_0_flitLeft; + wire [7 : 0] merged_0_flitLeft$D_IN; + wire merged_0_flitLeft$EN; + + // register merged_1_flitLeft + reg [7 : 0] merged_1_flitLeft; + wire [7 : 0] merged_1_flitLeft$D_IN; + wire merged_1_flitLeft$EN; // register rg_fromhost_addr reg [63 : 0] rg_fromhost_addr; wire [63 : 0] rg_fromhost_addr$D_IN; wire rg_fromhost_addr$EN; + // register rg_hart0_reset_delay + reg [7 : 0] rg_hart0_reset_delay; + wire [7 : 0] rg_hart0_reset_delay$D_IN; + wire rg_hart0_reset_delay$EN; + // register rg_tohost_addr reg [63 : 0] rg_tohost_addr; wire [63 : 0] rg_tohost_addr$D_IN; wire rg_tohost_addr$EN; - // ports of submodule cpu_halt - wire cpu_halt$ASSERT_IN, cpu_halt$ASSERT_OUT, cpu_halt$OUT_RST; + // register split_0_flitLeft + reg [7 : 0] split_0_flitLeft; + wire [7 : 0] split_0_flitLeft$D_IN; + wire split_0_flitLeft$EN; - // ports of submodule cpu_reset - wire cpu_reset$ASSERT_IN, cpu_reset$ASSERT_OUT, cpu_reset$OUT_RST; + // register split_1_flitLeft + reg [7 : 0] split_1_flitLeft; + wire [7 : 0] split_1_flitLeft$D_IN; + wire split_1_flitLeft$EN; - // ports of submodule cpu_reset_either - wire cpu_reset_either$RST_OUT; + // register split_2_flitLeft + reg [7 : 0] split_2_flitLeft; + wire [7 : 0] split_2_flitLeft$D_IN; + wire split_2_flitLeft$EN; + + // register state + reg state; + wire state$D_IN, state$EN; + + // register state_1 + reg state_1; + wire state_1$D_IN, state_1$EN; + + // register state_1_1 + reg state_1_1; + wire state_1_1$D_IN, state_1_1$EN; + + // register state_1_1_1 + reg state_1_1_1; + wire state_1_1_1$D_IN, state_1_1_1$EN; + + // register tagController_tmp_addrOffset + reg [63 : 0] tagController_tmp_addrOffset; + wire [63 : 0] tagController_tmp_addrOffset$D_IN; + wire tagController_tmp_addrOffset$EN; + + // register tagController_tmp_doneSendingAW + reg tagController_tmp_doneSendingAW; + wire tagController_tmp_doneSendingAW$D_IN, + tagController_tmp_doneSendingAW$EN; + + // register tagController_tmp_reset_done + reg tagController_tmp_reset_done; + wire tagController_tmp_reset_done$D_IN, tagController_tmp_reset_done$EN; + + // register tagController_tmp_shimMaster_arff_rv + reg [99 : 0] tagController_tmp_shimMaster_arff_rv; + wire [99 : 0] tagController_tmp_shimMaster_arff_rv$D_IN; + wire tagController_tmp_shimMaster_arff_rv$EN; + + // register tagController_tmp_shimMaster_awff_rv + reg [99 : 0] tagController_tmp_shimMaster_awff_rv; + wire [99 : 0] tagController_tmp_shimMaster_awff_rv$D_IN; + wire tagController_tmp_shimMaster_awff_rv$EN; + + // register tagController_tmp_shimMaster_bff_rv + reg [8 : 0] tagController_tmp_shimMaster_bff_rv; + wire [8 : 0] tagController_tmp_shimMaster_bff_rv$D_IN; + wire tagController_tmp_shimMaster_bff_rv$EN; + + // register tagController_tmp_shimMaster_rff_rv + reg [73 : 0] tagController_tmp_shimMaster_rff_rv; + wire [73 : 0] tagController_tmp_shimMaster_rff_rv$D_IN; + wire tagController_tmp_shimMaster_rff_rv$EN; + + // register tagController_tmp_shimMaster_wff_rv + reg [73 : 0] tagController_tmp_shimMaster_wff_rv; + wire [73 : 0] tagController_tmp_shimMaster_wff_rv$D_IN; + wire tagController_tmp_shimMaster_wff_rv$EN; + + // register tagController_tmp_shimSlave_arff_rv + reg [98 : 0] tagController_tmp_shimSlave_arff_rv; + wire [98 : 0] tagController_tmp_shimSlave_arff_rv$D_IN; + wire tagController_tmp_shimSlave_arff_rv$EN; + + // register tagController_tmp_shimSlave_awff_rv + reg [98 : 0] tagController_tmp_shimSlave_awff_rv; + wire [98 : 0] tagController_tmp_shimSlave_awff_rv$D_IN; + wire tagController_tmp_shimSlave_awff_rv$EN; + + // register tagController_tmp_shimSlave_bff_rv + reg [7 : 0] tagController_tmp_shimSlave_bff_rv; + wire [7 : 0] tagController_tmp_shimSlave_bff_rv$D_IN; + wire tagController_tmp_shimSlave_bff_rv$EN; + + // register tagController_tmp_shimSlave_rff_rv + reg [73 : 0] tagController_tmp_shimSlave_rff_rv; + wire [73 : 0] tagController_tmp_shimSlave_rff_rv$D_IN; + wire tagController_tmp_shimSlave_rff_rv$EN; + + // register tagController_tmp_shimSlave_wff_rv + reg [74 : 0] tagController_tmp_shimSlave_wff_rv; + wire [74 : 0] tagController_tmp_shimSlave_wff_rv$D_IN; + wire tagController_tmp_shimSlave_wff_rv$EN; // ports of submodule debug_module + wire [76 : 0] debug_module$hart0_csr_mem_client_request_get; + wire [69 : 0] debug_module$hart0_gpr_mem_client_request_get; wire [64 : 0] debug_module$hart0_csr_mem_client_response_put, debug_module$hart0_fpr_mem_client_response_put, debug_module$hart0_gpr_mem_client_response_put; @@ -814,7 +1197,8 @@ module mkCoreW(CLK, debug_module$master_wstrb; wire [6 : 0] debug_module$dmi_read_addr_dm_addr, debug_module$dmi_write_dm_addr; - wire [3 : 0] debug_module$master_arcache, + wire [3 : 0] debug_module$hart0_get_other_req_get, + debug_module$master_arcache, debug_module$master_arid, debug_module$master_arqos, debug_module$master_arregion, @@ -823,8 +1207,7 @@ module mkCoreW(CLK, debug_module$master_awqos, debug_module$master_awregion, debug_module$master_bid, - debug_module$master_rid, - debug_module$master_wid; + debug_module$master_rid; wire [2 : 0] debug_module$master_arprot, debug_module$master_arsize, debug_module$master_awprot, @@ -836,7 +1219,6 @@ module mkCoreW(CLK, wire debug_module$EN_dmi_read_addr, debug_module$EN_dmi_read_data, debug_module$EN_dmi_write, - debug_module$EN_get_ndm_reset_req_get, debug_module$EN_hart0_client_run_halt_request_get, debug_module$EN_hart0_client_run_halt_response_put, debug_module$EN_hart0_csr_mem_client_request_get, @@ -844,24 +1226,29 @@ module mkCoreW(CLK, debug_module$EN_hart0_fpr_mem_client_request_get, debug_module$EN_hart0_fpr_mem_client_response_put, debug_module$EN_hart0_get_other_req_get, - debug_module$EN_hart0_get_reset_req_get, debug_module$EN_hart0_gpr_mem_client_request_get, debug_module$EN_hart0_gpr_mem_client_response_put, + debug_module$EN_hart0_reset_client_request_get, + debug_module$EN_hart0_reset_client_response_put, + debug_module$EN_ndm_reset_client_request_get, + debug_module$EN_ndm_reset_client_response_put, debug_module$RDY_dmi_read_addr, debug_module$RDY_dmi_read_data, debug_module$RDY_dmi_write, - debug_module$RDY_get_ndm_reset_req_get, debug_module$RDY_hart0_client_run_halt_request_get, debug_module$RDY_hart0_client_run_halt_response_put, debug_module$RDY_hart0_csr_mem_client_request_get, debug_module$RDY_hart0_csr_mem_client_response_put, - debug_module$RDY_hart0_fpr_mem_client_request_get, - debug_module$RDY_hart0_fpr_mem_client_response_put, - debug_module$RDY_hart0_get_reset_req_get, + debug_module$RDY_hart0_get_other_req_get, debug_module$RDY_hart0_gpr_mem_client_request_get, debug_module$RDY_hart0_gpr_mem_client_response_put, + debug_module$RDY_hart0_reset_client_request_get, + debug_module$RDY_hart0_reset_client_response_put, + debug_module$RDY_ndm_reset_client_request_get, + debug_module$RDY_ndm_reset_client_response_put, debug_module$hart0_client_run_halt_request_get, debug_module$hart0_client_run_halt_response_put, + debug_module$hart0_reset_client_response_put, debug_module$master_arlock, debug_module$master_arready, debug_module$master_arvalid, @@ -872,303 +1259,264 @@ module mkCoreW(CLK, debug_module$master_bvalid, debug_module$master_rlast, debug_module$master_rready, + debug_module$master_ruser, debug_module$master_rvalid, debug_module$master_wlast, debug_module$master_wready, - debug_module$master_wvalid; + debug_module$master_wuser, + debug_module$master_wvalid, + debug_module$ndm_reset_client_request_get, + debug_module$ndm_reset_client_response_put; - // ports of submodule dm_mem_tap - wire [361 : 0] dm_mem_tap$trace_data_out_get; - wire [63 : 0] dm_mem_tap$master_araddr, - dm_mem_tap$master_awaddr, - dm_mem_tap$master_rdata, - dm_mem_tap$master_wdata, - dm_mem_tap$slave_araddr, - dm_mem_tap$slave_awaddr, - dm_mem_tap$slave_rdata, - dm_mem_tap$slave_wdata; - wire [7 : 0] dm_mem_tap$master_arlen, - dm_mem_tap$master_awlen, - dm_mem_tap$master_wstrb, - dm_mem_tap$slave_arlen, - dm_mem_tap$slave_awlen, - dm_mem_tap$slave_wstrb; - wire [3 : 0] dm_mem_tap$master_arcache, - dm_mem_tap$master_arid, - dm_mem_tap$master_arqos, - dm_mem_tap$master_arregion, - dm_mem_tap$master_awcache, - dm_mem_tap$master_awid, - dm_mem_tap$master_awqos, - dm_mem_tap$master_awregion, - dm_mem_tap$master_bid, - dm_mem_tap$master_rid, - dm_mem_tap$master_wid, - dm_mem_tap$slave_arcache, - dm_mem_tap$slave_arid, - dm_mem_tap$slave_arqos, - dm_mem_tap$slave_arregion, - dm_mem_tap$slave_awcache, - dm_mem_tap$slave_awid, - dm_mem_tap$slave_awqos, - dm_mem_tap$slave_awregion, - dm_mem_tap$slave_bid, - dm_mem_tap$slave_rid, - dm_mem_tap$slave_wid; - wire [2 : 0] dm_mem_tap$master_arprot, - dm_mem_tap$master_arsize, - dm_mem_tap$master_awprot, - dm_mem_tap$master_awsize, - dm_mem_tap$slave_arprot, - dm_mem_tap$slave_arsize, - dm_mem_tap$slave_awprot, - dm_mem_tap$slave_awsize; - wire [1 : 0] dm_mem_tap$master_arburst, - dm_mem_tap$master_awburst, - dm_mem_tap$master_bresp, - dm_mem_tap$master_rresp, - dm_mem_tap$slave_arburst, - dm_mem_tap$slave_awburst, - dm_mem_tap$slave_bresp, - dm_mem_tap$slave_rresp; - wire dm_mem_tap$EN_trace_data_out_get, - dm_mem_tap$RDY_trace_data_out_get, - dm_mem_tap$master_arlock, - dm_mem_tap$master_arready, - dm_mem_tap$master_arvalid, - dm_mem_tap$master_awlock, - dm_mem_tap$master_awready, - dm_mem_tap$master_awvalid, - dm_mem_tap$master_bready, - dm_mem_tap$master_bvalid, - dm_mem_tap$master_rlast, - dm_mem_tap$master_rready, - dm_mem_tap$master_rvalid, - dm_mem_tap$master_wlast, - dm_mem_tap$master_wready, - dm_mem_tap$master_wvalid, - dm_mem_tap$slave_arlock, - dm_mem_tap$slave_arready, - dm_mem_tap$slave_arvalid, - dm_mem_tap$slave_awlock, - dm_mem_tap$slave_awready, - dm_mem_tap$slave_awvalid, - dm_mem_tap$slave_bready, - dm_mem_tap$slave_bvalid, - dm_mem_tap$slave_rlast, - dm_mem_tap$slave_rready, - dm_mem_tap$slave_rvalid, - dm_mem_tap$slave_wlast, - dm_mem_tap$slave_wready, - dm_mem_tap$slave_wvalid; + // ports of submodule dm_hart0_reset_controller + wire dm_hart0_reset_controller$ASSERT_IN, dm_hart0_reset_controller$OUT_RST; - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; + // ports of submodule hart0_reset + wire hart0_reset$RST_OUT; - // ports of submodule f_reset_requestor - wire f_reset_requestor$CLR, - f_reset_requestor$DEQ, - f_reset_requestor$D_IN, - f_reset_requestor$D_OUT, - f_reset_requestor$EMPTY_N, - f_reset_requestor$ENQ, - f_reset_requestor$FULL_N; + // ports of submodule ifcs_0_1_innerReq + wire [97 : 0] ifcs_0_1_innerReq$D_IN, ifcs_0_1_innerReq$D_OUT; + wire ifcs_0_1_innerReq$CLR, + ifcs_0_1_innerReq$DEQ, + ifcs_0_1_innerReq$EMPTY_N, + ifcs_0_1_innerReq$ENQ, + ifcs_0_1_innerReq$FULL_N; - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; + // ports of submodule ifcs_0_1_innerRoute + wire [2 : 0] ifcs_0_1_innerRoute$D_IN, ifcs_0_1_innerRoute$D_OUT; + wire ifcs_0_1_innerRoute$CLR, + ifcs_0_1_innerRoute$DEQ, + ifcs_0_1_innerRoute$EMPTY_N, + ifcs_0_1_innerRoute$ENQ, + ifcs_0_1_innerRoute$FULL_N; - // ports of submodule f_trace_data_merged - wire [361 : 0] f_trace_data_merged$D_IN, f_trace_data_merged$D_OUT; - wire f_trace_data_merged$CLR, - f_trace_data_merged$DEQ, - f_trace_data_merged$EMPTY_N, - f_trace_data_merged$ENQ, - f_trace_data_merged$FULL_N; + // ports of submodule ifcs_0_1_noRouteRsp + wire [71 : 0] ifcs_0_1_noRouteRsp$D_IN, ifcs_0_1_noRouteRsp$D_OUT; + wire ifcs_0_1_noRouteRsp$CLR, + ifcs_0_1_noRouteRsp$DEQ, + ifcs_0_1_noRouteRsp$EMPTY_N, + ifcs_0_1_noRouteRsp$ENQ, + ifcs_0_1_noRouteRsp$FULL_N; - // ports of submodule fabric_2x3 - wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, - fabric_2x3$v_from_masters_0_awaddr, - fabric_2x3$v_from_masters_0_rdata, - fabric_2x3$v_from_masters_0_wdata, - fabric_2x3$v_from_masters_1_araddr, - fabric_2x3$v_from_masters_1_awaddr, - fabric_2x3$v_from_masters_1_rdata, - fabric_2x3$v_from_masters_1_wdata, - fabric_2x3$v_to_slaves_0_araddr, - fabric_2x3$v_to_slaves_0_awaddr, - fabric_2x3$v_to_slaves_0_rdata, - fabric_2x3$v_to_slaves_0_wdata, - fabric_2x3$v_to_slaves_1_araddr, - fabric_2x3$v_to_slaves_1_awaddr, - fabric_2x3$v_to_slaves_1_rdata, - fabric_2x3$v_to_slaves_1_wdata, - fabric_2x3$v_to_slaves_2_rdata; - wire [7 : 0] fabric_2x3$v_from_masters_0_arlen, - fabric_2x3$v_from_masters_0_awlen, - fabric_2x3$v_from_masters_0_wstrb, - fabric_2x3$v_from_masters_1_arlen, - fabric_2x3$v_from_masters_1_awlen, - fabric_2x3$v_from_masters_1_wstrb, - fabric_2x3$v_to_slaves_0_arlen, - fabric_2x3$v_to_slaves_0_awlen, - fabric_2x3$v_to_slaves_0_wstrb, - fabric_2x3$v_to_slaves_1_arlen, - fabric_2x3$v_to_slaves_1_awlen, - fabric_2x3$v_to_slaves_1_wstrb; - wire [3 : 0] fabric_2x3$set_verbosity_verbosity, - fabric_2x3$v_from_masters_0_arcache, - fabric_2x3$v_from_masters_0_arid, - fabric_2x3$v_from_masters_0_arqos, - fabric_2x3$v_from_masters_0_arregion, - fabric_2x3$v_from_masters_0_awcache, - fabric_2x3$v_from_masters_0_awid, - fabric_2x3$v_from_masters_0_awqos, - fabric_2x3$v_from_masters_0_awregion, - fabric_2x3$v_from_masters_0_bid, - fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_0_wid, - fabric_2x3$v_from_masters_1_arcache, - fabric_2x3$v_from_masters_1_arid, - fabric_2x3$v_from_masters_1_arqos, - fabric_2x3$v_from_masters_1_arregion, - fabric_2x3$v_from_masters_1_awcache, - fabric_2x3$v_from_masters_1_awid, - fabric_2x3$v_from_masters_1_awqos, - fabric_2x3$v_from_masters_1_awregion, - fabric_2x3$v_from_masters_1_bid, - fabric_2x3$v_from_masters_1_rid, - fabric_2x3$v_from_masters_1_wid, - fabric_2x3$v_to_slaves_0_arcache, - fabric_2x3$v_to_slaves_0_arid, - fabric_2x3$v_to_slaves_0_arqos, - fabric_2x3$v_to_slaves_0_arregion, - fabric_2x3$v_to_slaves_0_awcache, - fabric_2x3$v_to_slaves_0_awid, - fabric_2x3$v_to_slaves_0_awqos, - fabric_2x3$v_to_slaves_0_awregion, - fabric_2x3$v_to_slaves_0_bid, - fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_0_wid, - fabric_2x3$v_to_slaves_1_arcache, - fabric_2x3$v_to_slaves_1_arid, - fabric_2x3$v_to_slaves_1_arqos, - fabric_2x3$v_to_slaves_1_arregion, - fabric_2x3$v_to_slaves_1_awcache, - fabric_2x3$v_to_slaves_1_awid, - fabric_2x3$v_to_slaves_1_awqos, - fabric_2x3$v_to_slaves_1_awregion, - fabric_2x3$v_to_slaves_1_bid, - fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_1_wid, - fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid; - wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, - fabric_2x3$v_from_masters_0_arsize, - fabric_2x3$v_from_masters_0_awprot, - fabric_2x3$v_from_masters_0_awsize, - fabric_2x3$v_from_masters_1_arprot, - fabric_2x3$v_from_masters_1_arsize, - fabric_2x3$v_from_masters_1_awprot, - fabric_2x3$v_from_masters_1_awsize, - fabric_2x3$v_to_slaves_0_arprot, - fabric_2x3$v_to_slaves_0_arsize, - fabric_2x3$v_to_slaves_0_awprot, - fabric_2x3$v_to_slaves_0_awsize, - fabric_2x3$v_to_slaves_1_arprot, - fabric_2x3$v_to_slaves_1_arsize, - fabric_2x3$v_to_slaves_1_awprot, - fabric_2x3$v_to_slaves_1_awsize; - wire [1 : 0] fabric_2x3$v_from_masters_0_arburst, - fabric_2x3$v_from_masters_0_awburst, - fabric_2x3$v_from_masters_0_bresp, - fabric_2x3$v_from_masters_0_rresp, - fabric_2x3$v_from_masters_1_arburst, - fabric_2x3$v_from_masters_1_awburst, - fabric_2x3$v_from_masters_1_bresp, - fabric_2x3$v_from_masters_1_rresp, - fabric_2x3$v_to_slaves_0_arburst, - fabric_2x3$v_to_slaves_0_awburst, - fabric_2x3$v_to_slaves_0_bresp, - fabric_2x3$v_to_slaves_0_rresp, - fabric_2x3$v_to_slaves_1_arburst, - fabric_2x3$v_to_slaves_1_awburst, - fabric_2x3$v_to_slaves_1_bresp, - fabric_2x3$v_to_slaves_1_rresp, - fabric_2x3$v_to_slaves_2_bresp, - fabric_2x3$v_to_slaves_2_rresp; - wire fabric_2x3$EN_reset, - fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, - fabric_2x3$v_from_masters_0_arlock, - fabric_2x3$v_from_masters_0_arready, - fabric_2x3$v_from_masters_0_arvalid, - fabric_2x3$v_from_masters_0_awlock, - fabric_2x3$v_from_masters_0_awready, - fabric_2x3$v_from_masters_0_awvalid, - fabric_2x3$v_from_masters_0_bready, - fabric_2x3$v_from_masters_0_bvalid, - fabric_2x3$v_from_masters_0_rlast, - fabric_2x3$v_from_masters_0_rready, - fabric_2x3$v_from_masters_0_rvalid, - fabric_2x3$v_from_masters_0_wlast, - fabric_2x3$v_from_masters_0_wready, - fabric_2x3$v_from_masters_0_wvalid, - fabric_2x3$v_from_masters_1_arlock, - fabric_2x3$v_from_masters_1_arready, - fabric_2x3$v_from_masters_1_arvalid, - fabric_2x3$v_from_masters_1_awlock, - fabric_2x3$v_from_masters_1_awready, - fabric_2x3$v_from_masters_1_awvalid, - fabric_2x3$v_from_masters_1_bready, - fabric_2x3$v_from_masters_1_bvalid, - fabric_2x3$v_from_masters_1_rlast, - fabric_2x3$v_from_masters_1_rready, - fabric_2x3$v_from_masters_1_rvalid, - fabric_2x3$v_from_masters_1_wlast, - fabric_2x3$v_from_masters_1_wready, - fabric_2x3$v_from_masters_1_wvalid, - fabric_2x3$v_to_slaves_0_arlock, - fabric_2x3$v_to_slaves_0_arready, - fabric_2x3$v_to_slaves_0_arvalid, - fabric_2x3$v_to_slaves_0_awlock, - fabric_2x3$v_to_slaves_0_awready, - fabric_2x3$v_to_slaves_0_awvalid, - fabric_2x3$v_to_slaves_0_bready, - fabric_2x3$v_to_slaves_0_bvalid, - fabric_2x3$v_to_slaves_0_rlast, - fabric_2x3$v_to_slaves_0_rready, - fabric_2x3$v_to_slaves_0_rvalid, - fabric_2x3$v_to_slaves_0_wlast, - fabric_2x3$v_to_slaves_0_wready, - fabric_2x3$v_to_slaves_0_wvalid, - fabric_2x3$v_to_slaves_1_arlock, - fabric_2x3$v_to_slaves_1_arready, - fabric_2x3$v_to_slaves_1_arvalid, - fabric_2x3$v_to_slaves_1_awlock, - fabric_2x3$v_to_slaves_1_awready, - fabric_2x3$v_to_slaves_1_awvalid, - fabric_2x3$v_to_slaves_1_bready, - fabric_2x3$v_to_slaves_1_bvalid, - fabric_2x3$v_to_slaves_1_rlast, - fabric_2x3$v_to_slaves_1_rready, - fabric_2x3$v_to_slaves_1_rvalid, - fabric_2x3$v_to_slaves_1_wlast, - fabric_2x3$v_to_slaves_1_wready, - fabric_2x3$v_to_slaves_1_wvalid, - fabric_2x3$v_to_slaves_2_arready, - fabric_2x3$v_to_slaves_2_awready, - fabric_2x3$v_to_slaves_2_bvalid, - fabric_2x3$v_to_slaves_2_rlast, - fabric_2x3$v_to_slaves_2_rvalid, - fabric_2x3$v_to_slaves_2_wready; + // ports of submodule ifcs_0_1_routeBack + wire [1 : 0] ifcs_0_1_routeBack$D_IN, ifcs_0_1_routeBack$D_OUT; + wire ifcs_0_1_routeBack$CLR, + ifcs_0_1_routeBack$DEQ, + ifcs_0_1_routeBack$EMPTY_N, + ifcs_0_1_routeBack$ENQ, + ifcs_0_1_routeBack$FULL_N; + + // ports of submodule ifcs_0_1_rspBack + wire [71 : 0] ifcs_0_1_rspBack$D_IN, ifcs_0_1_rspBack$D_OUT; + wire ifcs_0_1_rspBack$CLR, + ifcs_0_1_rspBack$DEQ, + ifcs_0_1_rspBack$EMPTY_N, + ifcs_0_1_rspBack$ENQ, + ifcs_0_1_rspBack$FULL_N; + + // ports of submodule ifcs_0_innerReq + wire [172 : 0] ifcs_0_innerReq$D_IN, ifcs_0_innerReq$D_OUT; + wire ifcs_0_innerReq$CLR, + ifcs_0_innerReq$DEQ, + ifcs_0_innerReq$EMPTY_N, + ifcs_0_innerReq$ENQ, + ifcs_0_innerReq$FULL_N; + + // ports of submodule ifcs_0_innerRoute + wire [2 : 0] ifcs_0_innerRoute$D_IN, ifcs_0_innerRoute$D_OUT; + wire ifcs_0_innerRoute$CLR, + ifcs_0_innerRoute$DEQ, + ifcs_0_innerRoute$EMPTY_N, + ifcs_0_innerRoute$ENQ, + ifcs_0_innerRoute$FULL_N; + + // ports of submodule ifcs_0_noRouteRsp + wire [5 : 0] ifcs_0_noRouteRsp$D_IN, ifcs_0_noRouteRsp$D_OUT; + wire ifcs_0_noRouteRsp$CLR, + ifcs_0_noRouteRsp$DEQ, + ifcs_0_noRouteRsp$EMPTY_N, + ifcs_0_noRouteRsp$ENQ, + ifcs_0_noRouteRsp$FULL_N; + + // ports of submodule ifcs_0_routeBack + wire [1 : 0] ifcs_0_routeBack$D_IN, ifcs_0_routeBack$D_OUT; + wire ifcs_0_routeBack$CLR, + ifcs_0_routeBack$DEQ, + ifcs_0_routeBack$EMPTY_N, + ifcs_0_routeBack$ENQ, + ifcs_0_routeBack$FULL_N; + + // ports of submodule ifcs_0_rspBack + wire [5 : 0] ifcs_0_rspBack$D_IN, ifcs_0_rspBack$D_OUT; + wire ifcs_0_rspBack$CLR, + ifcs_0_rspBack$DEQ, + ifcs_0_rspBack$EMPTY_N, + ifcs_0_rspBack$ENQ, + ifcs_0_rspBack$FULL_N; + + // ports of submodule ifcs_1_1_innerReq + wire [97 : 0] ifcs_1_1_innerReq$D_IN, ifcs_1_1_innerReq$D_OUT; + wire ifcs_1_1_innerReq$CLR, + ifcs_1_1_innerReq$DEQ, + ifcs_1_1_innerReq$EMPTY_N, + ifcs_1_1_innerReq$ENQ, + ifcs_1_1_innerReq$FULL_N; + + // ports of submodule ifcs_1_1_innerRoute + wire [2 : 0] ifcs_1_1_innerRoute$D_IN, ifcs_1_1_innerRoute$D_OUT; + wire ifcs_1_1_innerRoute$CLR, + ifcs_1_1_innerRoute$DEQ, + ifcs_1_1_innerRoute$EMPTY_N, + ifcs_1_1_innerRoute$ENQ, + ifcs_1_1_innerRoute$FULL_N; + + // ports of submodule ifcs_1_1_noRouteRsp + wire [71 : 0] ifcs_1_1_noRouteRsp$D_IN, ifcs_1_1_noRouteRsp$D_OUT; + wire ifcs_1_1_noRouteRsp$CLR, + ifcs_1_1_noRouteRsp$DEQ, + ifcs_1_1_noRouteRsp$EMPTY_N, + ifcs_1_1_noRouteRsp$ENQ, + ifcs_1_1_noRouteRsp$FULL_N; + + // ports of submodule ifcs_1_1_routeBack + wire [1 : 0] ifcs_1_1_routeBack$D_IN, ifcs_1_1_routeBack$D_OUT; + wire ifcs_1_1_routeBack$CLR, + ifcs_1_1_routeBack$DEQ, + ifcs_1_1_routeBack$EMPTY_N, + ifcs_1_1_routeBack$ENQ, + ifcs_1_1_routeBack$FULL_N; + + // ports of submodule ifcs_1_1_rspBack + wire [71 : 0] ifcs_1_1_rspBack$D_IN, ifcs_1_1_rspBack$D_OUT; + wire ifcs_1_1_rspBack$CLR, + ifcs_1_1_rspBack$DEQ, + ifcs_1_1_rspBack$EMPTY_N, + ifcs_1_1_rspBack$ENQ, + ifcs_1_1_rspBack$FULL_N; + + // ports of submodule ifcs_1_innerReq + wire [172 : 0] ifcs_1_innerReq$D_IN, ifcs_1_innerReq$D_OUT; + wire ifcs_1_innerReq$CLR, + ifcs_1_innerReq$DEQ, + ifcs_1_innerReq$EMPTY_N, + ifcs_1_innerReq$ENQ, + ifcs_1_innerReq$FULL_N; + + // ports of submodule ifcs_1_innerRoute + wire [2 : 0] ifcs_1_innerRoute$D_IN, ifcs_1_innerRoute$D_OUT; + wire ifcs_1_innerRoute$CLR, + ifcs_1_innerRoute$DEQ, + ifcs_1_innerRoute$EMPTY_N, + ifcs_1_innerRoute$ENQ, + ifcs_1_innerRoute$FULL_N; + + // ports of submodule ifcs_1_noRouteRsp + wire [5 : 0] ifcs_1_noRouteRsp$D_IN, ifcs_1_noRouteRsp$D_OUT; + wire ifcs_1_noRouteRsp$CLR, + ifcs_1_noRouteRsp$DEQ, + ifcs_1_noRouteRsp$EMPTY_N, + ifcs_1_noRouteRsp$ENQ, + ifcs_1_noRouteRsp$FULL_N; + + // ports of submodule ifcs_1_routeBack + wire [1 : 0] ifcs_1_routeBack$D_IN, ifcs_1_routeBack$D_OUT; + wire ifcs_1_routeBack$CLR, + ifcs_1_routeBack$DEQ, + ifcs_1_routeBack$EMPTY_N, + ifcs_1_routeBack$ENQ, + ifcs_1_routeBack$FULL_N; + + // ports of submodule ifcs_1_rspBack + wire [5 : 0] ifcs_1_rspBack$D_IN, ifcs_1_rspBack$D_OUT; + wire ifcs_1_rspBack$CLR, + ifcs_1_rspBack$DEQ, + ifcs_1_rspBack$EMPTY_N, + ifcs_1_rspBack$ENQ, + ifcs_1_rspBack$FULL_N; + + // ports of submodule ifcs_2_1_routeBack + wire [1 : 0] ifcs_2_1_routeBack$D_IN, ifcs_2_1_routeBack$D_OUT; + wire ifcs_2_1_routeBack$CLR, + ifcs_2_1_routeBack$DEQ, + ifcs_2_1_routeBack$EMPTY_N, + ifcs_2_1_routeBack$ENQ, + ifcs_2_1_routeBack$FULL_N; + + // ports of submodule ifcs_2_1_rspBack + wire [71 : 0] ifcs_2_1_rspBack$D_IN, ifcs_2_1_rspBack$D_OUT; + wire ifcs_2_1_rspBack$CLR, + ifcs_2_1_rspBack$DEQ, + ifcs_2_1_rspBack$EMPTY_N, + ifcs_2_1_rspBack$ENQ, + ifcs_2_1_rspBack$FULL_N; + + // ports of submodule ifcs_2_routeBack + wire [1 : 0] ifcs_2_routeBack$D_IN, ifcs_2_routeBack$D_OUT; + wire ifcs_2_routeBack$CLR, + ifcs_2_routeBack$DEQ, + ifcs_2_routeBack$EMPTY_N, + ifcs_2_routeBack$ENQ, + ifcs_2_routeBack$FULL_N; + + // ports of submodule ifcs_2_rspBack + wire [5 : 0] ifcs_2_rspBack$D_IN, ifcs_2_rspBack$D_OUT; + wire ifcs_2_rspBack$CLR, + ifcs_2_rspBack$DEQ, + ifcs_2_rspBack$EMPTY_N, + ifcs_2_rspBack$ENQ, + ifcs_2_rspBack$FULL_N; + + // ports of submodule msNoSynth_0_b_buffer_ff + wire [5 : 0] msNoSynth_0_b_buffer_ff$D_IN, msNoSynth_0_b_buffer_ff$D_OUT; + wire msNoSynth_0_b_buffer_ff$CLR, + msNoSynth_0_b_buffer_ff$DEQ, + msNoSynth_0_b_buffer_ff$EMPTY_N, + msNoSynth_0_b_buffer_ff$ENQ, + msNoSynth_0_b_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_b_buffer_firstValid + wire msNoSynth_0_b_buffer_firstValid$D_IN, + msNoSynth_0_b_buffer_firstValid$EN, + msNoSynth_0_b_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_0_r_buffer_ff + wire [71 : 0] msNoSynth_0_r_buffer_ff$D_IN, msNoSynth_0_r_buffer_ff$D_OUT; + wire msNoSynth_0_r_buffer_ff$CLR, + msNoSynth_0_r_buffer_ff$DEQ, + msNoSynth_0_r_buffer_ff$EMPTY_N, + msNoSynth_0_r_buffer_ff$ENQ, + msNoSynth_0_r_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_r_buffer_firstValid + wire msNoSynth_0_r_buffer_firstValid$D_IN, + msNoSynth_0_r_buffer_firstValid$EN, + msNoSynth_0_r_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_b_buffer_ff + wire [5 : 0] msNoSynth_1_b_buffer_ff$D_IN, msNoSynth_1_b_buffer_ff$D_OUT; + wire msNoSynth_1_b_buffer_ff$CLR, + msNoSynth_1_b_buffer_ff$DEQ, + msNoSynth_1_b_buffer_ff$EMPTY_N, + msNoSynth_1_b_buffer_ff$ENQ, + msNoSynth_1_b_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_b_buffer_firstValid + wire msNoSynth_1_b_buffer_firstValid$D_IN, + msNoSynth_1_b_buffer_firstValid$EN, + msNoSynth_1_b_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_r_buffer_ff + wire [71 : 0] msNoSynth_1_r_buffer_ff$D_IN, msNoSynth_1_r_buffer_ff$D_OUT; + wire msNoSynth_1_r_buffer_ff$CLR, + msNoSynth_1_r_buffer_ff$DEQ, + msNoSynth_1_r_buffer_ff$EMPTY_N, + msNoSynth_1_r_buffer_ff$ENQ, + msNoSynth_1_r_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_r_buffer_firstValid + wire msNoSynth_1_r_buffer_firstValid$D_IN, + msNoSynth_1_r_buffer_firstValid$EN, + msNoSynth_1_r_buffer_firstValid$Q_OUT; // ports of submodule plic wire [63 : 0] plic$axi4_slave_araddr, @@ -1180,17 +1528,16 @@ module mkCoreW(CLK, wire [7 : 0] plic$axi4_slave_arlen, plic$axi4_slave_awlen, plic$axi4_slave_wstrb; + wire [4 : 0] plic$axi4_slave_arid, + plic$axi4_slave_awid, + plic$axi4_slave_bid, + plic$axi4_slave_rid; wire [3 : 0] plic$axi4_slave_arcache, - plic$axi4_slave_arid, plic$axi4_slave_arqos, plic$axi4_slave_arregion, plic$axi4_slave_awcache, - plic$axi4_slave_awid, plic$axi4_slave_awqos, plic$axi4_slave_awregion, - plic$axi4_slave_bid, - plic$axi4_slave_rid, - plic$axi4_slave_wid, plic$set_verbosity_verbosity; wire [2 : 0] plic$axi4_slave_arprot, plic$axi4_slave_arsize, @@ -1205,8 +1552,6 @@ module mkCoreW(CLK, plic$EN_set_addr_map, plic$EN_set_verbosity, plic$EN_show_PLIC_state, - plic$RDY_server_reset_request_put, - plic$RDY_server_reset_response_get, plic$axi4_slave_arlock, plic$axi4_slave_arready, plic$axi4_slave_arvalid, @@ -1217,9 +1562,11 @@ module mkCoreW(CLK, plic$axi4_slave_bvalid, plic$axi4_slave_rlast, plic$axi4_slave_rready, + plic$axi4_slave_ruser, plic$axi4_slave_rvalid, plic$axi4_slave_wlast, plic$axi4_slave_wready, + plic$axi4_slave_wuser, plic$axi4_slave_wvalid, plic$v_sources_0_m_interrupt_req_set_not_clear, plic$v_sources_10_m_interrupt_req_set_not_clear, @@ -1241,11 +1588,16 @@ module mkCoreW(CLK, plic$v_targets_1_m_eip; // ports of submodule proc - wire [361 : 0] proc$trace_data_out_get; wire [76 : 0] proc$hart0_csr_mem_server_request_put; wire [69 : 0] proc$hart0_fpr_mem_server_request_put, proc$hart0_gpr_mem_server_request_put; - wire [63 : 0] proc$master0_araddr, + wire [64 : 0] proc$hart0_csr_mem_server_response_get, + proc$hart0_gpr_mem_server_response_get; + wire [63 : 0] proc$debug_module_mem_server_araddr, + proc$debug_module_mem_server_awaddr, + proc$debug_module_mem_server_rdata, + proc$debug_module_mem_server_wdata, + proc$master0_araddr, proc$master0_awaddr, proc$master0_rdata, proc$master0_wdata, @@ -1256,24 +1608,36 @@ module mkCoreW(CLK, proc$start_fromhostAddr, proc$start_startpc, proc$start_tohostAddr; - wire [7 : 0] proc$master0_arlen, + wire [7 : 0] proc$debug_module_mem_server_arlen, + proc$debug_module_mem_server_awlen, + proc$debug_module_mem_server_wstrb, + proc$master0_arlen, proc$master0_awlen, proc$master0_wstrb, proc$master1_arlen, proc$master1_awlen, proc$master1_wstrb; - wire [3 : 0] proc$hart0_put_other_req_put, - proc$master0_arcache, + wire [4 : 0] proc$debug_module_mem_server_arid, + proc$debug_module_mem_server_awid, + proc$debug_module_mem_server_bid, + proc$debug_module_mem_server_rid, proc$master0_arid, + proc$master0_awid, + proc$master0_bid, + proc$master0_rid; + wire [3 : 0] proc$debug_module_mem_server_arcache, + proc$debug_module_mem_server_arqos, + proc$debug_module_mem_server_arregion, + proc$debug_module_mem_server_awcache, + proc$debug_module_mem_server_awqos, + proc$debug_module_mem_server_awregion, + proc$hart0_put_other_req_put, + proc$master0_arcache, proc$master0_arqos, proc$master0_arregion, proc$master0_awcache, - proc$master0_awid, proc$master0_awqos, proc$master0_awregion, - proc$master0_bid, - proc$master0_rid, - proc$master0_wid, proc$master1_arcache, proc$master1_arid, proc$master1_arqos, @@ -1284,9 +1648,12 @@ module mkCoreW(CLK, proc$master1_awregion, proc$master1_bid, proc$master1_rid, - proc$master1_wid, proc$set_verbosity_verbosity; - wire [2 : 0] proc$master0_arprot, + wire [2 : 0] proc$debug_module_mem_server_arprot, + proc$debug_module_mem_server_arsize, + proc$debug_module_mem_server_awprot, + proc$debug_module_mem_server_awsize, + proc$master0_arprot, proc$master0_arsize, proc$master0_awprot, proc$master0_awsize, @@ -1294,7 +1661,11 @@ module mkCoreW(CLK, proc$master1_arsize, proc$master1_awprot, proc$master1_awsize; - wire [1 : 0] proc$master0_arburst, + wire [1 : 0] proc$debug_module_mem_server_arburst, + proc$debug_module_mem_server_awburst, + proc$debug_module_mem_server_bresp, + proc$debug_module_mem_server_rresp, + proc$master0_arburst, proc$master0_awburst, proc$master0_bresp, proc$master0_rresp, @@ -1309,19 +1680,35 @@ module mkCoreW(CLK, proc$EN_hart0_gpr_mem_server_request_put, proc$EN_hart0_gpr_mem_server_response_get, proc$EN_hart0_put_other_req_put, - proc$EN_hart0_server_reset_request_put, - proc$EN_hart0_server_reset_response_get, - proc$EN_hart0_server_run_halt_request_put, - proc$EN_hart0_server_run_halt_response_get, + proc$EN_hart0_run_halt_server_request_put, + proc$EN_hart0_run_halt_server_response_get, proc$EN_set_verbosity, proc$EN_start, - proc$EN_trace_data_out_get, - proc$RDY_hart0_server_reset_request_put, - proc$RDY_hart0_server_reset_response_get, + proc$RDY_hart0_csr_mem_server_request_put, + proc$RDY_hart0_csr_mem_server_response_get, + proc$RDY_hart0_gpr_mem_server_request_put, + proc$RDY_hart0_gpr_mem_server_response_get, + proc$RDY_hart0_run_halt_server_request_put, + proc$RDY_hart0_run_halt_server_response_get, proc$RDY_start, - proc$RDY_trace_data_out_get, - proc$debug_external_interrupt_req_set_not_clear, - proc$hart0_server_run_halt_request_put, + proc$debug_module_mem_server_arlock, + proc$debug_module_mem_server_arready, + proc$debug_module_mem_server_arvalid, + proc$debug_module_mem_server_awlock, + proc$debug_module_mem_server_awready, + proc$debug_module_mem_server_awvalid, + proc$debug_module_mem_server_bready, + proc$debug_module_mem_server_bvalid, + proc$debug_module_mem_server_rlast, + proc$debug_module_mem_server_rready, + proc$debug_module_mem_server_ruser, + proc$debug_module_mem_server_rvalid, + proc$debug_module_mem_server_wlast, + proc$debug_module_mem_server_wready, + proc$debug_module_mem_server_wuser, + proc$debug_module_mem_server_wvalid, + proc$hart0_run_halt_server_request_put, + proc$hart0_run_halt_server_response_get, proc$m_external_interrupt_req_set_not_clear, proc$master0_arlock, proc$master0_arready, @@ -1333,9 +1720,11 @@ module mkCoreW(CLK, proc$master0_bvalid, proc$master0_rlast, proc$master0_rready, + proc$master0_ruser, proc$master0_rvalid, proc$master0_wlast, proc$master0_wready, + proc$master0_wuser, proc$master0_wvalid, proc$master1_arlock, proc$master1_arready, @@ -1347,6 +1736,7 @@ module mkCoreW(CLK, proc$master1_bvalid, proc$master1_rlast, proc$master1_rready, + proc$master1_ruser, proc$master1_rvalid, proc$master1_wlast, proc$master1_wready, @@ -1355,64 +1745,535 @@ module mkCoreW(CLK, proc$s_external_interrupt_req_set_not_clear; // ports of submodule soc_map + wire [127 : 0] soc_map$m_mem0_controller_addr_range, + soc_map$m_plic_addr_range; wire [63 : 0] soc_map$m_is_IO_addr_addr, soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; + soc_map$m_is_near_mem_IO_addr_addr; - // ports of submodule tv_encode - wire [607 : 0] tv_encode$tv_vb_out_get; - wire [361 : 0] tv_encode$trace_data_in_put; - wire tv_encode$EN_reset, - tv_encode$EN_trace_data_in_put, - tv_encode$EN_tv_vb_out_get, - tv_encode$RDY_trace_data_in_put, - tv_encode$RDY_tv_vb_out_get; + // ports of submodule ssNoSynth_0_ar_buffer_ff + wire [97 : 0] ssNoSynth_0_ar_buffer_ff$D_IN, ssNoSynth_0_ar_buffer_ff$D_OUT; + wire ssNoSynth_0_ar_buffer_ff$CLR, + ssNoSynth_0_ar_buffer_ff$DEQ, + ssNoSynth_0_ar_buffer_ff$EMPTY_N, + ssNoSynth_0_ar_buffer_ff$ENQ, + ssNoSynth_0_ar_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_0_ar_buffer_firstValid + wire ssNoSynth_0_ar_buffer_firstValid$D_IN, + ssNoSynth_0_ar_buffer_firstValid$EN, + ssNoSynth_0_ar_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_0_aw_buffer_ff + wire [97 : 0] ssNoSynth_0_aw_buffer_ff$D_IN, ssNoSynth_0_aw_buffer_ff$D_OUT; + wire ssNoSynth_0_aw_buffer_ff$CLR, + ssNoSynth_0_aw_buffer_ff$DEQ, + ssNoSynth_0_aw_buffer_ff$EMPTY_N, + ssNoSynth_0_aw_buffer_ff$ENQ, + ssNoSynth_0_aw_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_0_aw_buffer_firstValid + wire ssNoSynth_0_aw_buffer_firstValid$D_IN, + ssNoSynth_0_aw_buffer_firstValid$EN, + ssNoSynth_0_aw_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_0_w_buffer_ff + wire [73 : 0] ssNoSynth_0_w_buffer_ff$D_IN, ssNoSynth_0_w_buffer_ff$D_OUT; + wire ssNoSynth_0_w_buffer_ff$CLR, + ssNoSynth_0_w_buffer_ff$DEQ, + ssNoSynth_0_w_buffer_ff$EMPTY_N, + ssNoSynth_0_w_buffer_ff$ENQ, + ssNoSynth_0_w_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_0_w_buffer_firstValid + wire ssNoSynth_0_w_buffer_firstValid$D_IN, + ssNoSynth_0_w_buffer_firstValid$EN, + ssNoSynth_0_w_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_1_ar_buffer_ff + wire [97 : 0] ssNoSynth_1_ar_buffer_ff$D_IN, ssNoSynth_1_ar_buffer_ff$D_OUT; + wire ssNoSynth_1_ar_buffer_ff$CLR, + ssNoSynth_1_ar_buffer_ff$DEQ, + ssNoSynth_1_ar_buffer_ff$EMPTY_N, + ssNoSynth_1_ar_buffer_ff$ENQ, + ssNoSynth_1_ar_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_1_ar_buffer_firstValid + wire ssNoSynth_1_ar_buffer_firstValid$D_IN, + ssNoSynth_1_ar_buffer_firstValid$EN, + ssNoSynth_1_ar_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_1_aw_buffer_ff + wire [97 : 0] ssNoSynth_1_aw_buffer_ff$D_IN, ssNoSynth_1_aw_buffer_ff$D_OUT; + wire ssNoSynth_1_aw_buffer_ff$CLR, + ssNoSynth_1_aw_buffer_ff$DEQ, + ssNoSynth_1_aw_buffer_ff$EMPTY_N, + ssNoSynth_1_aw_buffer_ff$ENQ, + ssNoSynth_1_aw_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_1_aw_buffer_firstValid + wire ssNoSynth_1_aw_buffer_firstValid$D_IN, + ssNoSynth_1_aw_buffer_firstValid$EN, + ssNoSynth_1_aw_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_1_w_buffer_ff + wire [73 : 0] ssNoSynth_1_w_buffer_ff$D_IN, ssNoSynth_1_w_buffer_ff$D_OUT; + wire ssNoSynth_1_w_buffer_ff$CLR, + ssNoSynth_1_w_buffer_ff$DEQ, + ssNoSynth_1_w_buffer_ff$EMPTY_N, + ssNoSynth_1_w_buffer_ff$ENQ, + ssNoSynth_1_w_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_1_w_buffer_firstValid + wire ssNoSynth_1_w_buffer_firstValid$D_IN, + ssNoSynth_1_w_buffer_firstValid$EN, + ssNoSynth_1_w_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_ar_buffer_ff + wire [97 : 0] ssNoSynth_2_ar_buffer_ff$D_IN, ssNoSynth_2_ar_buffer_ff$D_OUT; + wire ssNoSynth_2_ar_buffer_ff$CLR, + ssNoSynth_2_ar_buffer_ff$DEQ, + ssNoSynth_2_ar_buffer_ff$EMPTY_N, + ssNoSynth_2_ar_buffer_ff$ENQ, + ssNoSynth_2_ar_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_ar_buffer_firstValid + wire ssNoSynth_2_ar_buffer_firstValid$D_IN, + ssNoSynth_2_ar_buffer_firstValid$EN, + ssNoSynth_2_ar_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_aw_buffer_ff + wire [97 : 0] ssNoSynth_2_aw_buffer_ff$D_IN, ssNoSynth_2_aw_buffer_ff$D_OUT; + wire ssNoSynth_2_aw_buffer_ff$CLR, + ssNoSynth_2_aw_buffer_ff$DEQ, + ssNoSynth_2_aw_buffer_ff$EMPTY_N, + ssNoSynth_2_aw_buffer_ff$ENQ, + ssNoSynth_2_aw_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_aw_buffer_firstValid + wire ssNoSynth_2_aw_buffer_firstValid$D_IN, + ssNoSynth_2_aw_buffer_firstValid$EN, + ssNoSynth_2_aw_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_w_buffer_ff + wire [73 : 0] ssNoSynth_2_w_buffer_ff$D_IN, ssNoSynth_2_w_buffer_ff$D_OUT; + wire ssNoSynth_2_w_buffer_ff$CLR, + ssNoSynth_2_w_buffer_ff$DEQ, + ssNoSynth_2_w_buffer_ff$EMPTY_N, + ssNoSynth_2_w_buffer_ff$ENQ, + ssNoSynth_2_w_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_w_buffer_firstValid + wire ssNoSynth_2_w_buffer_firstValid$D_IN, + ssNoSynth_2_w_buffer_firstValid$EN, + ssNoSynth_2_w_buffer_firstValid$Q_OUT; + + // ports of submodule tagController_tmp_awreqff + wire [97 : 0] tagController_tmp_awreqff$D_IN, + tagController_tmp_awreqff$D_OUT; + wire tagController_tmp_awreqff$CLR, + tagController_tmp_awreqff$DEQ, + tagController_tmp_awreqff$EMPTY_N, + tagController_tmp_awreqff$ENQ, + tagController_tmp_awreqff$FULL_N; + + // ports of submodule tagController_tmp_newRst + wire tagController_tmp_newRst$ASSERT_IN, tagController_tmp_newRst$OUT_RST; + + // ports of submodule tagController_tmp_tagCon + wire [140 : 0] tagController_tmp_tagCon$cache_request_put_val, + tagController_tmp_tagCon$memory_request_get; + wire [76 : 0] tagController_tmp_tagCon$cache_response_get, + tagController_tmp_tagCon$memory_response_put_val; + wire tagController_tmp_tagCon$EN_cache_request_put, + tagController_tmp_tagCon$EN_cache_response_get, + tagController_tmp_tagCon$EN_memory_request_get, + tagController_tmp_tagCon$EN_memory_response_put, + tagController_tmp_tagCon$RDY_cache_request_put, + tagController_tmp_tagCon$RDY_cache_response_get, + tagController_tmp_tagCon$RDY_memory_request_get, + tagController_tmp_tagCon$RDY_memory_response_put; + + // ports of submodule tmp0_b_buffer_ff + wire [5 : 0] tmp0_b_buffer_ff$D_IN, tmp0_b_buffer_ff$D_OUT; + wire tmp0_b_buffer_ff$CLR, + tmp0_b_buffer_ff$DEQ, + tmp0_b_buffer_ff$EMPTY_N, + tmp0_b_buffer_ff$ENQ, + tmp0_b_buffer_ff$FULL_N; + + // ports of submodule tmp0_b_buffer_firstValid + wire tmp0_b_buffer_firstValid$D_IN, + tmp0_b_buffer_firstValid$EN, + tmp0_b_buffer_firstValid$Q_OUT; + + // ports of submodule tmp0_r_buffer_ff + wire [71 : 0] tmp0_r_buffer_ff$D_IN, tmp0_r_buffer_ff$D_OUT; + wire tmp0_r_buffer_ff$CLR, + tmp0_r_buffer_ff$DEQ, + tmp0_r_buffer_ff$EMPTY_N, + tmp0_r_buffer_ff$ENQ, + tmp0_r_buffer_ff$FULL_N; + + // ports of submodule tmp0_r_buffer_firstValid + wire tmp0_r_buffer_firstValid$D_IN, + tmp0_r_buffer_firstValid$EN, + tmp0_r_buffer_firstValid$Q_OUT; + + // ports of submodule tmp2_b_buffer_ff + wire [6 : 0] tmp2_b_buffer_ff$D_IN, tmp2_b_buffer_ff$D_OUT; + wire tmp2_b_buffer_ff$CLR, + tmp2_b_buffer_ff$DEQ, + tmp2_b_buffer_ff$EMPTY_N, + tmp2_b_buffer_ff$ENQ, + tmp2_b_buffer_ff$FULL_N; + + // ports of submodule tmp2_b_buffer_firstValid + wire tmp2_b_buffer_firstValid$D_IN, + tmp2_b_buffer_firstValid$EN, + tmp2_b_buffer_firstValid$Q_OUT; + + // ports of submodule tmp2_r_buffer_ff + wire [72 : 0] tmp2_r_buffer_ff$D_IN, tmp2_r_buffer_ff$D_OUT; + wire tmp2_r_buffer_ff$CLR, + tmp2_r_buffer_ff$DEQ, + tmp2_r_buffer_ff$EMPTY_N, + tmp2_r_buffer_ff$ENQ, + tmp2_r_buffer_ff$FULL_N; + + // ports of submodule tmp2_r_buffer_firstValid + wire tmp2_r_buffer_firstValid$D_IN, + tmp2_r_buffer_firstValid$EN, + tmp2_r_buffer_firstValid$Q_OUT; + + // ports of submodule uncached_mem_shim_arff + wire [97 : 0] uncached_mem_shim_arff$D_IN, uncached_mem_shim_arff$D_OUT; + wire uncached_mem_shim_arff$CLR, + uncached_mem_shim_arff$DEQ, + uncached_mem_shim_arff$EMPTY_N, + uncached_mem_shim_arff$ENQ, + uncached_mem_shim_arff$FULL_N; + + // ports of submodule uncached_mem_shim_awff + wire [97 : 0] uncached_mem_shim_awff$D_IN, uncached_mem_shim_awff$D_OUT; + wire uncached_mem_shim_awff$CLR, + uncached_mem_shim_awff$DEQ, + uncached_mem_shim_awff$EMPTY_N, + uncached_mem_shim_awff$ENQ, + uncached_mem_shim_awff$FULL_N; + + // ports of submodule uncached_mem_shim_bff + wire [6 : 0] uncached_mem_shim_bff$D_IN, uncached_mem_shim_bff$D_OUT; + wire uncached_mem_shim_bff$CLR, + uncached_mem_shim_bff$DEQ, + uncached_mem_shim_bff$EMPTY_N, + uncached_mem_shim_bff$ENQ, + uncached_mem_shim_bff$FULL_N; + + // ports of submodule uncached_mem_shim_rff + wire [72 : 0] uncached_mem_shim_rff$D_IN, uncached_mem_shim_rff$D_OUT; + wire uncached_mem_shim_rff$CLR, + uncached_mem_shim_rff$DEQ, + uncached_mem_shim_rff$EMPTY_N, + uncached_mem_shim_rff$ENQ, + uncached_mem_shim_rff$FULL_N; + + // ports of submodule uncached_mem_shim_wff + wire [73 : 0] uncached_mem_shim_wff$D_IN, uncached_mem_shim_wff$D_OUT; + wire uncached_mem_shim_wff$CLR, + uncached_mem_shim_wff$DEQ, + uncached_mem_shim_wff$EMPTY_N, + uncached_mem_shim_wff$ENQ, + uncached_mem_shim_wff$FULL_N; // rule scheduling signals - wire CAN_FIRE_RL_merge_cpu_trace_data, - CAN_FIRE_RL_merge_dm_mem_trace_data, + wire CAN_FIRE_RL_ClientServerRequest, + CAN_FIRE_RL_ClientServerRequest_1, + CAN_FIRE_RL_ClientServerRequest_2, + CAN_FIRE_RL_ClientServerResponse, + CAN_FIRE_RL_ClientServerResponse_1, + CAN_FIRE_RL_ClientServerResponse_2, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut, + CAN_FIRE_RL_arbitrate, + CAN_FIRE_RL_arbitrate_1, + CAN_FIRE_RL_arbitrate_2, + CAN_FIRE_RL_arbitrate_3, + CAN_FIRE_RL_burst, + CAN_FIRE_RL_burst_1, + CAN_FIRE_RL_burst_2, + CAN_FIRE_RL_burst_3, + CAN_FIRE_RL_burst_4, + CAN_FIRE_RL_burst_5, + CAN_FIRE_RL_burst_6, + CAN_FIRE_RL_burst_7, + CAN_FIRE_RL_burst_8, + CAN_FIRE_RL_burst_9, + CAN_FIRE_RL_checkSinkReady, + CAN_FIRE_RL_checkSinkReady_1, + CAN_FIRE_RL_checkSinkReady_2, + CAN_FIRE_RL_checkSinkReady_3, + CAN_FIRE_RL_checkSinkReady_4, + CAN_FIRE_RL_checkSinkReady_5, + CAN_FIRE_RL_checkSinkReady_6, + CAN_FIRE_RL_checkSinkReady_7, + CAN_FIRE_RL_checkSinkReady_8, + CAN_FIRE_RL_checkSinkReady_9, + CAN_FIRE_RL_craftReq, + CAN_FIRE_RL_craftReq_1, + CAN_FIRE_RL_craftReq_2, + CAN_FIRE_RL_craftReq_3, + CAN_FIRE_RL_craftReq_4, + CAN_FIRE_RL_craftReq_5, + CAN_FIRE_RL_craftReq_6, + CAN_FIRE_RL_craftReq_7, + CAN_FIRE_RL_craftReq_8, + CAN_FIRE_RL_craftReq_9, + CAN_FIRE_RL_ifcs_0_1_drainFlits, + CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse, + CAN_FIRE_RL_ifcs_0_1_firstFlit, + CAN_FIRE_RL_ifcs_0_1_firstFlit_1, + CAN_FIRE_RL_ifcs_0_1_followFlits, + CAN_FIRE_RL_ifcs_0_1_followFlits_1, + CAN_FIRE_RL_ifcs_0_1_forwardRsp, + CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit, + CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_0_drainFlits, + CAN_FIRE_RL_ifcs_0_drainNoRouteResponse, + CAN_FIRE_RL_ifcs_0_firstFlit, + CAN_FIRE_RL_ifcs_0_firstFlit_1, + CAN_FIRE_RL_ifcs_0_followFlits, + CAN_FIRE_RL_ifcs_0_followFlits_1, + CAN_FIRE_RL_ifcs_0_forwardRsp, + CAN_FIRE_RL_ifcs_0_nonRoutableFlit, + CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_1_1_drainFlits, + CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse, + CAN_FIRE_RL_ifcs_1_1_firstFlit, + CAN_FIRE_RL_ifcs_1_1_firstFlit_1, + CAN_FIRE_RL_ifcs_1_1_followFlits, + CAN_FIRE_RL_ifcs_1_1_followFlits_1, + CAN_FIRE_RL_ifcs_1_1_forwardRsp, + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit, + CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_1_drainFlits, + CAN_FIRE_RL_ifcs_1_drainNoRouteResponse, + CAN_FIRE_RL_ifcs_1_firstFlit, + CAN_FIRE_RL_ifcs_1_firstFlit_1, + CAN_FIRE_RL_ifcs_1_followFlits, + CAN_FIRE_RL_ifcs_1_followFlits_1, + CAN_FIRE_RL_ifcs_1_forwardRsp, + CAN_FIRE_RL_ifcs_1_nonRoutableFlit, + CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_2_1_firstFlit, + CAN_FIRE_RL_ifcs_2_1_followFlits, + CAN_FIRE_RL_ifcs_2_firstFlit, + CAN_FIRE_RL_ifcs_2_followFlits, + CAN_FIRE_RL_merged_0_genFirst, + CAN_FIRE_RL_merged_0_genOther, + CAN_FIRE_RL_merged_1_genFirst, + CAN_FIRE_RL_merged_1_genOther, CAN_FIRE_RL_mkConnectionGetPut, - CAN_FIRE_RL_rl_cpu_hart0_reset_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - CAN_FIRE_RL_rl_csr, - CAN_FIRE_RL_rl_fpr, - CAN_FIRE_RL_rl_gpr, - CAN_FIRE_RL_rl_halt, - CAN_FIRE_RL_rl_halt_reset, - CAN_FIRE_RL_rl_hart0_server_reset, - CAN_FIRE_RL_rl_hart0_server_run_halt, - CAN_FIRE_RL_rl_once, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_addr_channel_4, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_rd_data_channel_4, + CAN_FIRE_RL_msNoSynth_0_ar_forwardReady, + CAN_FIRE_RL_msNoSynth_0_aw_forwardReady, + CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_b_dropFlit, + CAN_FIRE_RL_msNoSynth_0_b_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_r_dropFlit, + CAN_FIRE_RL_msNoSynth_0_r_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_w_forwardReady, + CAN_FIRE_RL_msNoSynth_1_ar_forwardReady, + CAN_FIRE_RL_msNoSynth_1_aw_forwardReady, + CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_b_dropFlit, + CAN_FIRE_RL_msNoSynth_1_b_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_r_dropFlit, + CAN_FIRE_RL_msNoSynth_1_r_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_w_forwardReady, + CAN_FIRE_RL_rl_dm_hart0_reset, + CAN_FIRE_RL_rl_dm_hart0_reset_wait, CAN_FIRE_RL_rl_relay_external_interrupts, - CAN_FIRE_RL_rl_relay_non_maskable_interrupt, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_addr_channel_4, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_data_channel_4, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_RL_rl_wr_response_channel_4, + CAN_FIRE_RL_sink_selected, + CAN_FIRE_RL_sink_selected_1, + CAN_FIRE_RL_sink_selected_2, + CAN_FIRE_RL_sink_selected_3, + CAN_FIRE_RL_sink_selected_4, + CAN_FIRE_RL_sink_selected_5, + CAN_FIRE_RL_sink_selected_6, + CAN_FIRE_RL_sink_selected_7, + CAN_FIRE_RL_sink_selected_8, + CAN_FIRE_RL_sink_selected_9, + CAN_FIRE_RL_source_selected, + CAN_FIRE_RL_source_selected_1, + CAN_FIRE_RL_source_selected_2, + CAN_FIRE_RL_source_selected_3, + CAN_FIRE_RL_source_selected_4, + CAN_FIRE_RL_source_selected_5, + CAN_FIRE_RL_source_selected_6, + CAN_FIRE_RL_source_selected_7, + CAN_FIRE_RL_source_selected_8, + CAN_FIRE_RL_source_selected_9, + CAN_FIRE_RL_split_0_putFirst, + CAN_FIRE_RL_split_0_putOther, + CAN_FIRE_RL_split_1_putFirst, + CAN_FIRE_RL_split_1_putOther, + CAN_FIRE_RL_split_2_putFirst, + CAN_FIRE_RL_split_2_putOther, + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_b_forwardReady, + CAN_FIRE_RL_ssNoSynth_0_r_forwardReady, + CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_w_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_b_forwardReady, + CAN_FIRE_RL_ssNoSynth_1_r_forwardReady, + CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_w_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_b_forwardReady, + CAN_FIRE_RL_ssNoSynth_2_r_forwardReady, + CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_w_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit, + CAN_FIRE_RL_tagController_tmp_getCacheAW, + CAN_FIRE_RL_tagController_tmp_passCacheRead, + CAN_FIRE_RL_tagController_tmp_passCacheResponse, + CAN_FIRE_RL_tagController_tmp_passCacheWrite, + CAN_FIRE_RL_tagController_tmp_passMemoryRequest, + CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead, + CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite, + CAN_FIRE_RL_tagController_tmp_propagateReset, + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop, + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek, + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop, + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop, + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek, + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop, + CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut, + CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut, + CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut, + CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut, + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop, + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek, + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut, + CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut, + CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut, + CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut, + CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop, + CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_setPeek, + CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop, + CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop, + CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_setPeek, + CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop, + CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut, + CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut, + CAN_FIRE_RL_tmp0_ar_forwardReady, + CAN_FIRE_RL_tmp0_aw_forwardReady, + CAN_FIRE_RL_tmp0_b_buffer_dequeue, + CAN_FIRE_RL_tmp0_b_buffer_enqueue, + CAN_FIRE_RL_tmp0_b_dropFlit, + CAN_FIRE_RL_tmp0_b_forwardFlit, + CAN_FIRE_RL_tmp0_r_buffer_dequeue, + CAN_FIRE_RL_tmp0_r_buffer_enqueue, + CAN_FIRE_RL_tmp0_r_dropFlit, + CAN_FIRE_RL_tmp0_r_forwardFlit, + CAN_FIRE_RL_tmp0_w_forwardReady, + CAN_FIRE_RL_tmp2_ar_forwardReady, + CAN_FIRE_RL_tmp2_aw_forwardReady, + CAN_FIRE_RL_tmp2_b_buffer_dequeue, + CAN_FIRE_RL_tmp2_b_buffer_enqueue, + CAN_FIRE_RL_tmp2_b_dropFlit, + CAN_FIRE_RL_tmp2_b_forwardFlit, + CAN_FIRE_RL_tmp2_r_buffer_dequeue, + CAN_FIRE_RL_tmp2_r_buffer_enqueue, + CAN_FIRE_RL_tmp2_r_dropFlit, + CAN_FIRE_RL_tmp2_r_forwardFlit, + CAN_FIRE_RL_tmp2_w_forwardReady, + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop, + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek, + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop, + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop, + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek, + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop, + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut, + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut, + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut, + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut, + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop, + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek, + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop, + CAN_FIRE___me_check_156, + CAN_FIRE___me_check_157, + CAN_FIRE___me_check_158, + CAN_FIRE___me_check_160, + CAN_FIRE___me_check_163, + CAN_FIRE___me_check_164, + CAN_FIRE___me_check_165, + CAN_FIRE___me_check_167, + CAN_FIRE___me_check_170, + CAN_FIRE___me_check_172, + CAN_FIRE___me_check_174, + CAN_FIRE___me_check_182, + CAN_FIRE___me_check_184, + CAN_FIRE___me_check_186, + CAN_FIRE___me_check_195, + CAN_FIRE___me_check_197, + CAN_FIRE___me_check_199, + CAN_FIRE___me_check_201, + CAN_FIRE___me_check_203, + CAN_FIRE___me_check_204, + CAN_FIRE___me_check_205, + CAN_FIRE___me_check_207, + CAN_FIRE___me_check_210, + CAN_FIRE___me_check_211, + CAN_FIRE___me_check_212, + CAN_FIRE___me_check_214, + CAN_FIRE___me_check_217, + CAN_FIRE___me_check_219, + CAN_FIRE___me_check_221, + CAN_FIRE___me_check_229, + CAN_FIRE___me_check_231, + CAN_FIRE___me_check_233, + CAN_FIRE___me_check_242, + CAN_FIRE___me_check_244, + CAN_FIRE___me_check_246, + CAN_FIRE___me_check_248, CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -1429,68 +2290,311 @@ module mkCoreW(CLK, CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - CAN_FIRE_cpu_dmem_master_m_arready, - CAN_FIRE_cpu_dmem_master_m_awready, - CAN_FIRE_cpu_dmem_master_m_bvalid, - CAN_FIRE_cpu_dmem_master_m_rvalid, - CAN_FIRE_cpu_dmem_master_m_wready, - CAN_FIRE_cpu_imem_master_m_arready, - CAN_FIRE_cpu_imem_master_m_awready, - CAN_FIRE_cpu_imem_master_m_bvalid, - CAN_FIRE_cpu_imem_master_m_rvalid, - CAN_FIRE_cpu_imem_master_m_wready, - CAN_FIRE_cpu_reset_server_request_put, - CAN_FIRE_cpu_reset_server_response_get, - CAN_FIRE_debug_external_interrupt_req, - CAN_FIRE_dm_dmi_read_addr, - CAN_FIRE_dm_dmi_read_data, - CAN_FIRE_dm_dmi_write, - CAN_FIRE_dm_ndm_reset_req_get_get, - CAN_FIRE_set_htif_addrs, + CAN_FIRE_cpu_dmem_master_ar_arready, + CAN_FIRE_cpu_dmem_master_aw_awready, + CAN_FIRE_cpu_dmem_master_b_bflit, + CAN_FIRE_cpu_dmem_master_r_rflit, + CAN_FIRE_cpu_dmem_master_w_wready, + CAN_FIRE_cpu_imem_master_ar_arready, + CAN_FIRE_cpu_imem_master_aw_awready, + CAN_FIRE_cpu_imem_master_b_bflit, + CAN_FIRE_cpu_imem_master_r_rflit, + CAN_FIRE_cpu_imem_master_w_wready, + CAN_FIRE_dmi_read_addr, + CAN_FIRE_dmi_read_data, + CAN_FIRE_dmi_write, + CAN_FIRE_ndm_reset_client_request_get, + CAN_FIRE_ndm_reset_client_response_put, + CAN_FIRE_nmi_req, CAN_FIRE_set_verbosity, - CAN_FIRE_tv_verifier_info_get_get, - WILL_FIRE_RL_merge_cpu_trace_data, - WILL_FIRE_RL_merge_dm_mem_trace_data, + CAN_FIRE_start, + WILL_FIRE_RL_ClientServerRequest, + WILL_FIRE_RL_ClientServerRequest_1, + WILL_FIRE_RL_ClientServerRequest_2, + WILL_FIRE_RL_ClientServerResponse, + WILL_FIRE_RL_ClientServerResponse_1, + WILL_FIRE_RL_ClientServerResponse_2, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut, + WILL_FIRE_RL_arbitrate, + WILL_FIRE_RL_arbitrate_1, + WILL_FIRE_RL_arbitrate_2, + WILL_FIRE_RL_arbitrate_3, + WILL_FIRE_RL_burst, + WILL_FIRE_RL_burst_1, + WILL_FIRE_RL_burst_2, + WILL_FIRE_RL_burst_3, + WILL_FIRE_RL_burst_4, + WILL_FIRE_RL_burst_5, + WILL_FIRE_RL_burst_6, + WILL_FIRE_RL_burst_7, + WILL_FIRE_RL_burst_8, + WILL_FIRE_RL_burst_9, + WILL_FIRE_RL_checkSinkReady, + WILL_FIRE_RL_checkSinkReady_1, + WILL_FIRE_RL_checkSinkReady_2, + WILL_FIRE_RL_checkSinkReady_3, + WILL_FIRE_RL_checkSinkReady_4, + WILL_FIRE_RL_checkSinkReady_5, + WILL_FIRE_RL_checkSinkReady_6, + WILL_FIRE_RL_checkSinkReady_7, + WILL_FIRE_RL_checkSinkReady_8, + WILL_FIRE_RL_checkSinkReady_9, + WILL_FIRE_RL_craftReq, + WILL_FIRE_RL_craftReq_1, + WILL_FIRE_RL_craftReq_2, + WILL_FIRE_RL_craftReq_3, + WILL_FIRE_RL_craftReq_4, + WILL_FIRE_RL_craftReq_5, + WILL_FIRE_RL_craftReq_6, + WILL_FIRE_RL_craftReq_7, + WILL_FIRE_RL_craftReq_8, + WILL_FIRE_RL_craftReq_9, + WILL_FIRE_RL_ifcs_0_1_drainFlits, + WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse, + WILL_FIRE_RL_ifcs_0_1_firstFlit, + WILL_FIRE_RL_ifcs_0_1_firstFlit_1, + WILL_FIRE_RL_ifcs_0_1_followFlits, + WILL_FIRE_RL_ifcs_0_1_followFlits_1, + WILL_FIRE_RL_ifcs_0_1_forwardRsp, + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit, + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_0_drainFlits, + WILL_FIRE_RL_ifcs_0_drainNoRouteResponse, + WILL_FIRE_RL_ifcs_0_firstFlit, + WILL_FIRE_RL_ifcs_0_firstFlit_1, + WILL_FIRE_RL_ifcs_0_followFlits, + WILL_FIRE_RL_ifcs_0_followFlits_1, + WILL_FIRE_RL_ifcs_0_forwardRsp, + WILL_FIRE_RL_ifcs_0_nonRoutableFlit, + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_1_1_drainFlits, + WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse, + WILL_FIRE_RL_ifcs_1_1_firstFlit, + WILL_FIRE_RL_ifcs_1_1_firstFlit_1, + WILL_FIRE_RL_ifcs_1_1_followFlits, + WILL_FIRE_RL_ifcs_1_1_followFlits_1, + WILL_FIRE_RL_ifcs_1_1_forwardRsp, + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit, + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_1_drainFlits, + WILL_FIRE_RL_ifcs_1_drainNoRouteResponse, + WILL_FIRE_RL_ifcs_1_firstFlit, + WILL_FIRE_RL_ifcs_1_firstFlit_1, + WILL_FIRE_RL_ifcs_1_followFlits, + WILL_FIRE_RL_ifcs_1_followFlits_1, + WILL_FIRE_RL_ifcs_1_forwardRsp, + WILL_FIRE_RL_ifcs_1_nonRoutableFlit, + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_2_1_firstFlit, + WILL_FIRE_RL_ifcs_2_1_followFlits, + WILL_FIRE_RL_ifcs_2_firstFlit, + WILL_FIRE_RL_ifcs_2_followFlits, + WILL_FIRE_RL_merged_0_genFirst, + WILL_FIRE_RL_merged_0_genOther, + WILL_FIRE_RL_merged_1_genFirst, + WILL_FIRE_RL_merged_1_genOther, WILL_FIRE_RL_mkConnectionGetPut, - WILL_FIRE_RL_rl_cpu_hart0_reset_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - WILL_FIRE_RL_rl_csr, - WILL_FIRE_RL_rl_fpr, - WILL_FIRE_RL_rl_gpr, - WILL_FIRE_RL_rl_halt, - WILL_FIRE_RL_rl_halt_reset, - WILL_FIRE_RL_rl_hart0_server_reset, - WILL_FIRE_RL_rl_hart0_server_run_halt, - WILL_FIRE_RL_rl_once, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_addr_channel_4, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_rd_data_channel_4, + WILL_FIRE_RL_msNoSynth_0_ar_forwardReady, + WILL_FIRE_RL_msNoSynth_0_aw_forwardReady, + WILL_FIRE_RL_msNoSynth_0_b_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_b_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_b_dropFlit, + WILL_FIRE_RL_msNoSynth_0_b_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_r_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_r_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_r_dropFlit, + WILL_FIRE_RL_msNoSynth_0_r_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_w_forwardReady, + WILL_FIRE_RL_msNoSynth_1_ar_forwardReady, + WILL_FIRE_RL_msNoSynth_1_aw_forwardReady, + WILL_FIRE_RL_msNoSynth_1_b_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_b_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_b_dropFlit, + WILL_FIRE_RL_msNoSynth_1_b_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_r_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_r_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_r_dropFlit, + WILL_FIRE_RL_msNoSynth_1_r_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_w_forwardReady, + WILL_FIRE_RL_rl_dm_hart0_reset, + WILL_FIRE_RL_rl_dm_hart0_reset_wait, WILL_FIRE_RL_rl_relay_external_interrupts, - WILL_FIRE_RL_rl_relay_non_maskable_interrupt, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_addr_channel_4, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_data_channel_4, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_RL_rl_wr_response_channel_4, + WILL_FIRE_RL_sink_selected, + WILL_FIRE_RL_sink_selected_1, + WILL_FIRE_RL_sink_selected_2, + WILL_FIRE_RL_sink_selected_3, + WILL_FIRE_RL_sink_selected_4, + WILL_FIRE_RL_sink_selected_5, + WILL_FIRE_RL_sink_selected_6, + WILL_FIRE_RL_sink_selected_7, + WILL_FIRE_RL_sink_selected_8, + WILL_FIRE_RL_sink_selected_9, + WILL_FIRE_RL_source_selected, + WILL_FIRE_RL_source_selected_1, + WILL_FIRE_RL_source_selected_2, + WILL_FIRE_RL_source_selected_3, + WILL_FIRE_RL_source_selected_4, + WILL_FIRE_RL_source_selected_5, + WILL_FIRE_RL_source_selected_6, + WILL_FIRE_RL_source_selected_7, + WILL_FIRE_RL_source_selected_8, + WILL_FIRE_RL_source_selected_9, + WILL_FIRE_RL_split_0_putFirst, + WILL_FIRE_RL_split_0_putOther, + WILL_FIRE_RL_split_1_putFirst, + WILL_FIRE_RL_split_1_putOther, + WILL_FIRE_RL_split_2_putFirst, + WILL_FIRE_RL_split_2_putOther, + WILL_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_b_forwardReady, + WILL_FIRE_RL_ssNoSynth_0_r_forwardReady, + WILL_FIRE_RL_ssNoSynth_0_w_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_w_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_w_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_ar_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_ar_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_aw_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_aw_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_b_forwardReady, + WILL_FIRE_RL_ssNoSynth_1_r_forwardReady, + WILL_FIRE_RL_ssNoSynth_1_w_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_w_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_w_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_w_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_ar_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_ar_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_aw_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_aw_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_b_forwardReady, + WILL_FIRE_RL_ssNoSynth_2_r_forwardReady, + WILL_FIRE_RL_ssNoSynth_2_w_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_w_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_w_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_w_forwardFlit, + WILL_FIRE_RL_tagController_tmp_getCacheAW, + WILL_FIRE_RL_tagController_tmp_passCacheRead, + WILL_FIRE_RL_tagController_tmp_passCacheResponse, + WILL_FIRE_RL_tagController_tmp_passCacheWrite, + WILL_FIRE_RL_tagController_tmp_passMemoryRequest, + WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead, + WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite, + WILL_FIRE_RL_tagController_tmp_propagateReset, + WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop, + WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek, + WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop, + WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop, + WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek, + WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop, + WILL_FIRE_RL_tagController_tmp_ug_master_u_b_doPut, + WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut, + WILL_FIRE_RL_tagController_tmp_ug_master_u_r_doPut, + WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut, + WILL_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop, + WILL_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek, + WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop, + WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut, + WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut, + WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut, + WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut, + WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop, + WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_setPeek, + WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop, + WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop, + WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_setPeek, + WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop, + WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut, + WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut, + WILL_FIRE_RL_tmp0_ar_forwardReady, + WILL_FIRE_RL_tmp0_aw_forwardReady, + WILL_FIRE_RL_tmp0_b_buffer_dequeue, + WILL_FIRE_RL_tmp0_b_buffer_enqueue, + WILL_FIRE_RL_tmp0_b_dropFlit, + WILL_FIRE_RL_tmp0_b_forwardFlit, + WILL_FIRE_RL_tmp0_r_buffer_dequeue, + WILL_FIRE_RL_tmp0_r_buffer_enqueue, + WILL_FIRE_RL_tmp0_r_dropFlit, + WILL_FIRE_RL_tmp0_r_forwardFlit, + WILL_FIRE_RL_tmp0_w_forwardReady, + WILL_FIRE_RL_tmp2_ar_forwardReady, + WILL_FIRE_RL_tmp2_aw_forwardReady, + WILL_FIRE_RL_tmp2_b_buffer_dequeue, + WILL_FIRE_RL_tmp2_b_buffer_enqueue, + WILL_FIRE_RL_tmp2_b_dropFlit, + WILL_FIRE_RL_tmp2_b_forwardFlit, + WILL_FIRE_RL_tmp2_r_buffer_dequeue, + WILL_FIRE_RL_tmp2_r_buffer_enqueue, + WILL_FIRE_RL_tmp2_r_dropFlit, + WILL_FIRE_RL_tmp2_r_forwardFlit, + WILL_FIRE_RL_tmp2_w_forwardReady, + WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop, + WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek, + WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop, + WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop, + WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek, + WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop, + WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut, + WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut, + WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut, + WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut, + WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop, + WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek, + WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop, + WILL_FIRE___me_check_156, + WILL_FIRE___me_check_157, + WILL_FIRE___me_check_158, + WILL_FIRE___me_check_160, + WILL_FIRE___me_check_163, + WILL_FIRE___me_check_164, + WILL_FIRE___me_check_165, + WILL_FIRE___me_check_167, + WILL_FIRE___me_check_170, + WILL_FIRE___me_check_172, + WILL_FIRE___me_check_174, + WILL_FIRE___me_check_182, + WILL_FIRE___me_check_184, + WILL_FIRE___me_check_186, + WILL_FIRE___me_check_195, + WILL_FIRE___me_check_197, + WILL_FIRE___me_check_199, + WILL_FIRE___me_check_201, + WILL_FIRE___me_check_203, + WILL_FIRE___me_check_204, + WILL_FIRE___me_check_205, + WILL_FIRE___me_check_207, + WILL_FIRE___me_check_210, + WILL_FIRE___me_check_211, + WILL_FIRE___me_check_212, + WILL_FIRE___me_check_214, + WILL_FIRE___me_check_217, + WILL_FIRE___me_check_219, + WILL_FIRE___me_check_221, + WILL_FIRE___me_check_229, + WILL_FIRE___me_check_231, + WILL_FIRE___me_check_233, + WILL_FIRE___me_check_242, + WILL_FIRE___me_check_244, + WILL_FIRE___me_check_246, + WILL_FIRE___me_check_248, WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -1507,270 +2611,621 @@ module mkCoreW(CLK, WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - WILL_FIRE_cpu_dmem_master_m_arready, - WILL_FIRE_cpu_dmem_master_m_awready, - WILL_FIRE_cpu_dmem_master_m_bvalid, - WILL_FIRE_cpu_dmem_master_m_rvalid, - WILL_FIRE_cpu_dmem_master_m_wready, - WILL_FIRE_cpu_imem_master_m_arready, - WILL_FIRE_cpu_imem_master_m_awready, - WILL_FIRE_cpu_imem_master_m_bvalid, - WILL_FIRE_cpu_imem_master_m_rvalid, - WILL_FIRE_cpu_imem_master_m_wready, - WILL_FIRE_cpu_reset_server_request_put, - WILL_FIRE_cpu_reset_server_response_get, - WILL_FIRE_debug_external_interrupt_req, - WILL_FIRE_dm_dmi_read_addr, - WILL_FIRE_dm_dmi_read_data, - WILL_FIRE_dm_dmi_write, - WILL_FIRE_dm_ndm_reset_req_get_get, - WILL_FIRE_set_htif_addrs, + WILL_FIRE_cpu_dmem_master_ar_arready, + WILL_FIRE_cpu_dmem_master_aw_awready, + WILL_FIRE_cpu_dmem_master_b_bflit, + WILL_FIRE_cpu_dmem_master_r_rflit, + WILL_FIRE_cpu_dmem_master_w_wready, + WILL_FIRE_cpu_imem_master_ar_arready, + WILL_FIRE_cpu_imem_master_aw_awready, + WILL_FIRE_cpu_imem_master_b_bflit, + WILL_FIRE_cpu_imem_master_r_rflit, + WILL_FIRE_cpu_imem_master_w_wready, + WILL_FIRE_dmi_read_addr, + WILL_FIRE_dmi_read_data, + WILL_FIRE_dmi_write, + WILL_FIRE_ndm_reset_client_request_get, + WILL_FIRE_ndm_reset_client_response_put, + WILL_FIRE_nmi_req, WILL_FIRE_set_verbosity, - WILL_FIRE_tv_verifier_info_get_get; + WILL_FIRE_start; + + // inputs to muxes for submodule ports + reg [71 : 0] MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2, + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2; + reg [5 : 0] MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2, + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2; + wire [140 : 0] MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_1, + MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_2; + wire [76 : 0] MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_1, + MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_2; + wire [7 : 0] MUX_merged_0_flitLeft$write_1__VAL_1, + MUX_merged_1_flitLeft$write_1__VAL_1, + MUX_rg_hart0_reset_delay$write_1__VAL_1, + MUX_split_0_flitLeft$write_1__VAL_1, + MUX_split_1_flitLeft$write_1__VAL_1, + MUX_split_2_flitLeft$write_1__VAL_1; + wire MUX_activeSource_0$write_1__SEL_1, + MUX_activeSource_0$write_1__VAL_1, + MUX_activeSource_1$write_1__VAL_1, + MUX_activeSource_1_1_0$write_1__SEL_1, + MUX_activeSource_1_1_0$write_1__SEL_2, + MUX_activeSource_1_1_0$write_1__SEL_3, + MUX_activeSource_1_1_0$write_1__VAL_1, + MUX_activeSource_1_1_1_1$write_1__VAL_1, + MUX_activeSource_1_1_2$write_1__VAL_1, + MUX_flitToSink_0$wset_1__SEL_1, + MUX_flitToSink_0$wset_1__SEL_3, + MUX_flitToSink_1$wset_1__SEL_1, + MUX_flitToSink_1$wset_1__SEL_3, + MUX_flitToSink_1_0$wset_1__SEL_1, + MUX_flitToSink_1_0$wset_1__SEL_2, + MUX_flitToSink_1_0$wset_1__SEL_3, + MUX_flitToSink_1_0$wset_1__SEL_4, + MUX_flitToSink_1_0$wset_1__SEL_5, + MUX_flitToSink_1_0$wset_1__SEL_6, + MUX_flitToSink_1_0_1$wset_1__SEL_1, + MUX_flitToSink_1_0_1$wset_1__SEL_3, + MUX_flitToSink_1_1$wset_1__SEL_1, + MUX_flitToSink_1_1$wset_1__SEL_2, + MUX_flitToSink_1_1$wset_1__SEL_3, + MUX_flitToSink_1_1$wset_1__SEL_4, + MUX_flitToSink_1_1$wset_1__SEL_5, + MUX_flitToSink_1_1$wset_1__SEL_6, + MUX_flitToSink_1_1_0$wset_1__SEL_1, + MUX_flitToSink_1_1_0$wset_1__SEL_2, + MUX_flitToSink_1_1_0$wset_1__SEL_3, + MUX_flitToSink_1_1_0$wset_1__SEL_4, + MUX_flitToSink_1_1_0$wset_1__SEL_5, + MUX_flitToSink_1_1_0$wset_1__SEL_6, + MUX_flitToSink_1_1_1$wset_1__SEL_1, + MUX_flitToSink_1_1_1$wset_1__SEL_3, + MUX_flitToSink_1_1_1_1$wset_1__SEL_1, + MUX_flitToSink_1_1_1_1$wset_1__SEL_2, + MUX_flitToSink_1_1_1_1$wset_1__SEL_3, + MUX_flitToSink_1_1_1_1$wset_1__SEL_4, + MUX_flitToSink_1_1_1_1$wset_1__SEL_5, + MUX_flitToSink_1_1_1_1$wset_1__SEL_6, + MUX_flitToSink_1_2$wset_1__SEL_1, + MUX_flitToSink_1_2$wset_1__SEL_3, + MUX_flitToSink_2$wset_1__SEL_1, + MUX_flitToSink_2$wset_1__SEL_3, + MUX_ifcs_0_1_state_1$write_1__SEL_1, + MUX_ifcs_0_state$write_1__PSEL_1, + MUX_ifcs_0_state$write_1__SEL_1, + MUX_ifcs_0_state$write_1__SEL_2, + MUX_ifcs_0_state$write_1__SEL_3, + MUX_ifcs_1_1_state_1$write_1__SEL_1, + MUX_ifcs_1_state$write_1__PSEL_1, + MUX_ifcs_1_state$write_1__SEL_1, + MUX_ifcs_1_state$write_1__SEL_2, + MUX_ifcs_1_state$write_1__SEL_3, + MUX_ifcs_2_1_state$write_1__SEL_1, + MUX_proc$start_1__SEL_1, + MUX_split_0_flitLeft$write_1__SEL_1, + MUX_split_0_flitLeft$write_1__SEL_2, + MUX_split_1_flitLeft$write_1__SEL_1, + MUX_split_1_flitLeft$write_1__SEL_2, + MUX_split_2_flitLeft$write_1__SEL_1, + MUX_split_2_flitLeft$write_1__SEL_2, + MUX_state$write_1__SEL_1, + MUX_state$write_1__SEL_2, + MUX_state_1_1_1$write_1__SEL_1, + MUX_state_1_1_1$write_1__SEL_2, + MUX_state_1_1_1$write_1__SEL_3; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h5014; - reg [31 : 0] v__h4855; - reg [31 : 0] v__h4849; - reg [31 : 0] v__h5008; + reg [31 : 0] v__h22817; + reg [31 : 0] v__h22960; + reg [63 : 0] v__h50643; + reg [63 : 0] v__h50032; + reg [63 : 0] v__h54652; + reg [63 : 0] v__h54041; + reg [63 : 0] v__h84586; + reg [63 : 0] v__h83975; + reg [63 : 0] v__h87479; + reg [63 : 0] v__h86868; + reg [63 : 0] v__h65347; + reg [63 : 0] v__h64966; + reg [63 : 0] v__h67417; + reg [63 : 0] v__h67036; + reg [63 : 0] v__h69316; + reg [63 : 0] v__h68935; + reg [63 : 0] v__h96759; + reg [63 : 0] v__h96378; + reg [63 : 0] v__h99250; + reg [63 : 0] v__h98869; + reg [63 : 0] v__h101560; + reg [63 : 0] v__h101179; + reg [31 : 0] v__h104002; + reg [31 : 0] v__h22811; + reg [31 : 0] v__h22954; + reg [31 : 0] v__h103996; // synopsys translate_on + // remaining internal signals + wire [98 : 0] tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4, + tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2; + wire [72 : 0] tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3, + uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1; + wire [63 : 0] araddr__h15532, + aw_awaddr__h10800, + tmp__h10583, + tmp__h8358, + v_araddr__h15549, + x__h37445, + x__h37480, + x__h40257, + x__h40282, + x__h71927, + x__h71952, + x__h74407, + x__h74432, + x__h8199, + x_rdata__h25037; + wire [39 : 0] x__h10832; + wire [8 : 0] x_port1__read__h73054, x_port1__read__h75518; + wire [7 : 0] arlen__h15533, v_arlen__h15550; + wire [5 : 0] v_arid__h15548; + wire [4 : 0] a_awid__h38608, + a_awid__h41374, + fatReq_arid__h72495, + fatReq_arid__h74960; + wire [3 : 0] _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245, + arcache__h15537, + x__h10875, + x__h12609, + x__h12621, + x__h12633, + x__h12645, + x__h12657, + x__h12669, + x__h12681, + x__h14205, + x__h15613, + x_rid__h25036, + y__h12610, + y__h12622, + y__h12634, + y__h12646, + y__h12658, + y__h12670, + y__h12682; + wire [2 : 0] aw_awsize_val__h12539, v_arsize_val__h15595; + wire [1 : 0] IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1221, + IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1325, + IF_debug_module_master_ar_araddr__944_BITS_63__ETC___d1970, + IF_proc_master1_ar_araddr__852_BITS_63_TO_40_8_ETC___d1878, + SEXT_SEXT_arbiter_1_1_firstHot_335_336_BIT_0_3_ETC__q22, + SEXT_SEXT_arbiter_1_firstHot_1_150_151_BIT_0_1_ETC__q17, + SEXT_SEXT_arbiter_1_firstHot_692_693_BIT_0_694_ETC__q12, + SEXT_SEXT_arbiter_firstHot_497_498_BIT_0_499_A_ETC__q7, + SEXT_arbiter_1_1_firstHot__q19, + SEXT_arbiter_1_1_lastSelect_1__q21, + SEXT_arbiter_1_1_lastSelect__q20, + SEXT_arbiter_1_firstHot_1__q15, + SEXT_arbiter_1_firstHot__q9, + SEXT_arbiter_1_lastSelect_1__q11, + SEXT_arbiter_1_lastSelect_2__q16, + SEXT_arbiter_1_lastSelect__q10, + SEXT_arbiter_firstHot__q5, + SEXT_arbiter_lastSelect__q6, + SEXT_x3111__q18, + SEXT_x3648__q13, + SEXT_x3682__q14, + SEXT_x5056__q23, + SEXT_x5090__q24, + SEXT_x9162__q8; + wire IF_NOT_ifcs_0_1_innerRoute_first__096_BIT_1_10_ETC___d2118, + IF_NOT_ifcs_0_innerRoute_first__443_BIT_1_452__ETC___d1465, + IF_NOT_ifcs_1_1_innerRoute_first__125_BIT_1_12_ETC___d2134, + IF_NOT_ifcs_1_innerRoute_first__472_BIT_1_476__ETC___d1481, + IF_SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_3_ETC___d2370, + IF_SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_3_ETC___d2376, + IF_SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_3_ETC___d2382, + IF_SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_1_ETC___d2170, + IF_SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_1_ETC___d2174, + IF_SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_ETC___d1727, + IF_SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_ETC___d1733, + IF_SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_ETC___d1739, + IF_SEXT_arbiter_lastSelect_493_494_BIT_0_495_A_ETC___d1517, + IF_SEXT_arbiter_lastSelect_493_494_BIT_0_495_A_ETC___d1521, + IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180, + IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1255, + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173, + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1194, + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1197, + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1202, + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1205, + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1209, + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1214, + IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1290, + IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1360, + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1283, + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302, + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1304, + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1307, + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1309, + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1313, + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1318, + IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1435, + IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1436, + IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1437, + SEXT_arbiter_1_1_firstHot_335_336_BIT_0_337_AN_ETC___d2351, + SEXT_arbiter_1_1_lastSelect_1_330_331_BIT_0_33_ETC___d2345, + SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_328__ETC___d2339, + SEXT_arbiter_1_firstHot_1_150_151_BIT_0_152_AN_ETC___d2158, + SEXT_arbiter_1_firstHot_692_693_BIT_0_694_AND__ETC___d1708, + SEXT_arbiter_1_lastSelect_1_687_688_BIT_0_689__ETC___d1702, + SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_148__ETC___d2154, + SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_AN_ETC___d1696, + SEXT_arbiter_firstHot_497_498_BIT_0_499_AND_re_ETC___d1505, + SEXT_arbiter_lastSelect_493_494_BIT_0_495_AND__ETC___d1501, + debug_module_master_ar_araddr__944_BITS_63_TO__ETC___d1958, + debug_module_master_ar_araddr__944_BITS_63_TO__ETC___d1963, + debug_module_master_ar_araddr__944_MINUS_soc_m_ETC___d1949, + debug_module_master_ar_araddr__944_MINUS_soc_m_ETC___d1954, + debug_module_master_ar_araddr__944_ULT_soc_map_ETC___d1947, + debug_module_master_ar_araddr__944_ULT_soc_map_ETC___d1952, + proc_master1_ar_araddr__852_BITS_63_TO_40_853__ETC___d1866, + proc_master1_ar_araddr__852_BITS_63_TO_40_853__ETC___d1871, + proc_master1_ar_araddr__852_MINUS_soc_map_m_me_ETC___d1857, + proc_master1_ar_araddr__852_MINUS_soc_map_m_pl_ETC___d1862, + proc_master1_ar_araddr__852_ULT_soc_map_m_mem0_ETC___d1855, + proc_master1_ar_araddr__852_ULT_soc_map_m_plic_ETC___d1860, + reqWires_1_0_whas__669_AND_reqWires_1_0_wget___ETC___d1679, + reqWires_1_1_0_whas__312_AND_reqWires_1_1_0_wg_ETC___d2322, + split_0_doPut_whas__086_AND_split_0_doPut_wget_ETC___d1093, + split_1_doPut_whas__115_AND_split_1_doPut_wget_ETC___d1122, + split_2_doPut_whas__144_AND_split_2_doPut_wget_ETC___d1151, + state_1_1_143_AND_activeSource_1_0_1_210_211_A_ETC___d2213, + state_1_1_143_AND_activeSource_1_1_1_250_251_A_ETC___d2253, + state_1_1_1_323_AND_activeSource_1_1_0_417_418_ETC___d2420, + state_1_1_1_323_AND_activeSource_1_1_1_1_453_4_ETC___d2456, + state_1_1_1_323_AND_activeSource_1_1_2_489_490_ETC___d2492, + state_1_680_AND_activeSource_1_0_768_769_AND_i_ETC___d1771, + state_1_680_AND_activeSource_1_1_801_802_AND_i_ETC___d1804, + state_1_680_AND_activeSource_1_2_835_836_AND_i_ETC___d1838, + state_490_AND_activeSource_0_563_564_AND_ifcs__ETC___d1566, + state_490_AND_activeSource_1_607_608_AND_ifcs__ETC___d1610, + x__h48635, + x__h48738, + x__h49103, + x__h49162, + x__h49244, + x__h62827, + x__h62829, + x__h62978, + x__h62980, + x__h63114, + x__h63116, + x__h63586, + x__h63588, + x__h63648, + x__h63682, + x__h63774, + x__h63776, + x__h63955, + x__h63957, + x__h82584, + x__h82687, + x__h83052, + x__h83111, + x__h83193, + x__h94235, + x__h94237, + x__h94386, + x__h94388, + x__h94522, + x__h94524, + x__h94994, + x__h94996, + x__h95056, + x__h95090, + x__h95182, + x__h95184, + x__h95363, + x__h95365, + y__h48636, + y__h48739, + y__h49104, + y__h49245, + y__h62828, + y__h62830, + y__h62979, + y__h62981, + y__h63115, + y__h63117, + y__h63587, + y__h63589, + y__h63775, + y__h63777, + y__h63956, + y__h63958, + y__h82585, + y__h82688, + y__h83053, + y__h83194, + y__h94236, + y__h94238, + y__h94387, + y__h94389, + y__h94523, + y__h94525, + y__h94995, + y__h94997, + y__h95183, + y__h95185, + y__h95364, + y__h95366; + // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; assign CAN_FIRE_set_verbosity = 1'd1 ; assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - // action method set_htif_addrs - assign RDY_set_htif_addrs = 1'd1 ; - assign CAN_FIRE_set_htif_addrs = 1'd1 ; - assign WILL_FIRE_set_htif_addrs = EN_set_htif_addrs ; + // action method start + assign RDY_start = proc$RDY_start ; + assign CAN_FIRE_start = proc$RDY_start ; + assign WILL_FIRE_start = EN_start ; - // action method cpu_reset_server_request_put - assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_cpu_reset_server_request_put = - EN_cpu_reset_server_request_put ; + // value method cpu_imem_master_aw_awid + assign cpu_imem_master_awid = + tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[98:93] ; - // action method cpu_reset_server_response_get - assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_cpu_reset_server_response_get = - EN_cpu_reset_server_response_get ; + // value method cpu_imem_master_aw_awaddr + assign cpu_imem_master_awaddr = + tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[92:29] ; - // value method cpu_imem_master_m_awvalid - assign cpu_imem_master_awvalid = proc$master0_awvalid ; + // value method cpu_imem_master_aw_awlen + assign cpu_imem_master_awlen = + tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[28:21] ; - // value method cpu_imem_master_m_awid - assign cpu_imem_master_awid = proc$master0_awid ; + // value method cpu_imem_master_aw_awsize + assign cpu_imem_master_awsize = + tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[20:18] ; - // value method cpu_imem_master_m_awaddr - assign cpu_imem_master_awaddr = proc$master0_awaddr ; + // value method cpu_imem_master_aw_awburst + assign cpu_imem_master_awburst = + tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[17:16] ; - // value method cpu_imem_master_m_awlen - assign cpu_imem_master_awlen = proc$master0_awlen ; + // value method cpu_imem_master_aw_awlock + assign cpu_imem_master_awlock = + tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[15] ; - // value method cpu_imem_master_m_awsize - assign cpu_imem_master_awsize = proc$master0_awsize ; + // value method cpu_imem_master_aw_awcache + assign cpu_imem_master_awcache = + tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[14:11] ; - // value method cpu_imem_master_m_awburst - assign cpu_imem_master_awburst = proc$master0_awburst ; + // value method cpu_imem_master_aw_awprot + assign cpu_imem_master_awprot = + tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[10:8] ; - // value method cpu_imem_master_m_awlock - assign cpu_imem_master_awlock = proc$master0_awlock ; + // value method cpu_imem_master_aw_awqos + assign cpu_imem_master_awqos = + tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[7:4] ; - // value method cpu_imem_master_m_awcache - assign cpu_imem_master_awcache = proc$master0_awcache ; + // value method cpu_imem_master_aw_awregion + assign cpu_imem_master_awregion = + tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[3:0] ; - // value method cpu_imem_master_m_awprot - assign cpu_imem_master_awprot = proc$master0_awprot ; + // value method cpu_imem_master_aw_awvalid + assign cpu_imem_master_awvalid = + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek ; - // value method cpu_imem_master_m_awqos - assign cpu_imem_master_awqos = proc$master0_awqos ; + // action method cpu_imem_master_aw_awready + assign CAN_FIRE_cpu_imem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_aw_awready = 1'd1 ; - // value method cpu_imem_master_m_awregion - assign cpu_imem_master_awregion = proc$master0_awregion ; + // value method cpu_imem_master_w_wdata + assign cpu_imem_master_wdata = + tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3[72:9] ; - // action method cpu_imem_master_m_awready - assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ; + // value method cpu_imem_master_w_wstrb + assign cpu_imem_master_wstrb = + tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3[8:1] ; - // value method cpu_imem_master_m_wvalid - assign cpu_imem_master_wvalid = proc$master0_wvalid ; + // value method cpu_imem_master_w_wlast + assign cpu_imem_master_wlast = + tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3[0] ; - // value method cpu_imem_master_m_wid - assign cpu_imem_master_wid = proc$master0_wid ; + // value method cpu_imem_master_w_wvalid + assign cpu_imem_master_wvalid = + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek ; - // value method cpu_imem_master_m_wdata - assign cpu_imem_master_wdata = proc$master0_wdata ; + // action method cpu_imem_master_w_wready + assign CAN_FIRE_cpu_imem_master_w_wready = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_w_wready = 1'd1 ; - // value method cpu_imem_master_m_wstrb - assign cpu_imem_master_wstrb = proc$master0_wstrb ; + // action method cpu_imem_master_b_bflit + assign CAN_FIRE_cpu_imem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_b_bflit = cpu_imem_master_bvalid ; - // value method cpu_imem_master_m_wlast - assign cpu_imem_master_wlast = proc$master0_wlast ; + // value method cpu_imem_master_b_bready + assign cpu_imem_master_bready = !tagController_tmp_shimMaster_bff_rv[8] ; - // action method cpu_imem_master_m_wready - assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ; + // value method cpu_imem_master_ar_arid + assign cpu_imem_master_arid = + tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[98:93] ; - // action method cpu_imem_master_m_bvalid - assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; + // value method cpu_imem_master_ar_araddr + assign cpu_imem_master_araddr = + tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[92:29] ; - // value method cpu_imem_master_m_bready - assign cpu_imem_master_bready = proc$master0_bready ; + // value method cpu_imem_master_ar_arlen + assign cpu_imem_master_arlen = + tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[28:21] ; - // value method cpu_imem_master_m_arvalid - assign cpu_imem_master_arvalid = proc$master0_arvalid ; + // value method cpu_imem_master_ar_arsize + assign cpu_imem_master_arsize = + tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[20:18] ; - // value method cpu_imem_master_m_arid - assign cpu_imem_master_arid = proc$master0_arid ; + // value method cpu_imem_master_ar_arburst + assign cpu_imem_master_arburst = + tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[17:16] ; - // value method cpu_imem_master_m_araddr - assign cpu_imem_master_araddr = proc$master0_araddr ; + // value method cpu_imem_master_ar_arlock + assign cpu_imem_master_arlock = + tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[15] ; - // value method cpu_imem_master_m_arlen - assign cpu_imem_master_arlen = proc$master0_arlen ; + // value method cpu_imem_master_ar_arcache + assign cpu_imem_master_arcache = + tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[14:11] ; - // value method cpu_imem_master_m_arsize - assign cpu_imem_master_arsize = proc$master0_arsize ; + // value method cpu_imem_master_ar_arprot + assign cpu_imem_master_arprot = + tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[10:8] ; - // value method cpu_imem_master_m_arburst - assign cpu_imem_master_arburst = proc$master0_arburst ; + // value method cpu_imem_master_ar_arqos + assign cpu_imem_master_arqos = + tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[7:4] ; - // value method cpu_imem_master_m_arlock - assign cpu_imem_master_arlock = proc$master0_arlock ; + // value method cpu_imem_master_ar_arregion + assign cpu_imem_master_arregion = + tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[3:0] ; - // value method cpu_imem_master_m_arcache - assign cpu_imem_master_arcache = proc$master0_arcache ; + // value method cpu_imem_master_ar_arvalid + assign cpu_imem_master_arvalid = + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek ; - // value method cpu_imem_master_m_arprot - assign cpu_imem_master_arprot = proc$master0_arprot ; + // action method cpu_imem_master_ar_arready + assign CAN_FIRE_cpu_imem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_ar_arready = 1'd1 ; - // value method cpu_imem_master_m_arqos - assign cpu_imem_master_arqos = proc$master0_arqos ; + // action method cpu_imem_master_r_rflit + assign CAN_FIRE_cpu_imem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_r_rflit = cpu_imem_master_rvalid ; - // value method cpu_imem_master_m_arregion - assign cpu_imem_master_arregion = proc$master0_arregion ; + // value method cpu_imem_master_r_rready + assign cpu_imem_master_rready = !tagController_tmp_shimMaster_rff_rv[73] ; - // action method cpu_imem_master_m_arready - assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ; + // value method cpu_dmem_master_aw_awid + assign cpu_dmem_master_awid = + ug_uncached_mem_shim_master_u_aw_peekWire$wget[98:93] ; - // action method cpu_imem_master_m_rvalid - assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; + // value method cpu_dmem_master_aw_awaddr + assign cpu_dmem_master_awaddr = + ug_uncached_mem_shim_master_u_aw_peekWire$wget[92:29] ; - // value method cpu_imem_master_m_rready - assign cpu_imem_master_rready = proc$master0_rready ; + // value method cpu_dmem_master_aw_awlen + assign cpu_dmem_master_awlen = + ug_uncached_mem_shim_master_u_aw_peekWire$wget[28:21] ; - // value method cpu_dmem_master_m_awvalid - assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ; + // value method cpu_dmem_master_aw_awsize + assign cpu_dmem_master_awsize = + ug_uncached_mem_shim_master_u_aw_peekWire$wget[20:18] ; - // value method cpu_dmem_master_m_awid - assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ; + // value method cpu_dmem_master_aw_awburst + assign cpu_dmem_master_awburst = + ug_uncached_mem_shim_master_u_aw_peekWire$wget[17:16] ; - // value method cpu_dmem_master_m_awaddr - assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ; + // value method cpu_dmem_master_aw_awlock + assign cpu_dmem_master_awlock = + ug_uncached_mem_shim_master_u_aw_peekWire$wget[15] ; - // value method cpu_dmem_master_m_awlen - assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ; + // value method cpu_dmem_master_aw_awcache + assign cpu_dmem_master_awcache = + ug_uncached_mem_shim_master_u_aw_peekWire$wget[14:11] ; - // value method cpu_dmem_master_m_awsize - assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ; + // value method cpu_dmem_master_aw_awprot + assign cpu_dmem_master_awprot = + ug_uncached_mem_shim_master_u_aw_peekWire$wget[10:8] ; - // value method cpu_dmem_master_m_awburst - assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ; + // value method cpu_dmem_master_aw_awqos + assign cpu_dmem_master_awqos = + ug_uncached_mem_shim_master_u_aw_peekWire$wget[7:4] ; - // value method cpu_dmem_master_m_awlock - assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ; + // value method cpu_dmem_master_aw_awregion + assign cpu_dmem_master_awregion = + ug_uncached_mem_shim_master_u_aw_peekWire$wget[3:0] ; - // value method cpu_dmem_master_m_awcache - assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ; + // value method cpu_dmem_master_aw_awvalid + assign cpu_dmem_master_awvalid = uncached_mem_shim_awff$EMPTY_N ; - // value method cpu_dmem_master_m_awprot - assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ; + // action method cpu_dmem_master_aw_awready + assign CAN_FIRE_cpu_dmem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_aw_awready = 1'd1 ; - // value method cpu_dmem_master_m_awqos - assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ; + // value method cpu_dmem_master_w_wdata + assign cpu_dmem_master_wdata = + uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1[72:9] ; - // value method cpu_dmem_master_m_awregion - assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ; + // value method cpu_dmem_master_w_wstrb + assign cpu_dmem_master_wstrb = + uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1[8:1] ; - // action method cpu_dmem_master_m_awready - assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ; + // value method cpu_dmem_master_w_wlast + assign cpu_dmem_master_wlast = + uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1[0] ; - // value method cpu_dmem_master_m_wvalid - assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; + // value method cpu_dmem_master_w_wvalid + assign cpu_dmem_master_wvalid = uncached_mem_shim_wff$EMPTY_N ; - // value method cpu_dmem_master_m_wid - assign cpu_dmem_master_wid = fabric_2x3$v_to_slaves_0_wid ; + // action method cpu_dmem_master_w_wready + assign CAN_FIRE_cpu_dmem_master_w_wready = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_w_wready = 1'd1 ; - // value method cpu_dmem_master_m_wdata - assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; + // action method cpu_dmem_master_b_bflit + assign CAN_FIRE_cpu_dmem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_b_bflit = cpu_dmem_master_bvalid ; - // value method cpu_dmem_master_m_wstrb - assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ; + // value method cpu_dmem_master_b_bready + assign cpu_dmem_master_bready = uncached_mem_shim_bff$FULL_N ; - // value method cpu_dmem_master_m_wlast - assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ; + // value method cpu_dmem_master_ar_arid + assign cpu_dmem_master_arid = + ug_uncached_mem_shim_master_u_ar_peekWire$wget[98:93] ; - // action method cpu_dmem_master_m_wready - assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ; + // value method cpu_dmem_master_ar_araddr + assign cpu_dmem_master_araddr = + ug_uncached_mem_shim_master_u_ar_peekWire$wget[92:29] ; - // action method cpu_dmem_master_m_bvalid - assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; + // value method cpu_dmem_master_ar_arlen + assign cpu_dmem_master_arlen = + ug_uncached_mem_shim_master_u_ar_peekWire$wget[28:21] ; - // value method cpu_dmem_master_m_bready - assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ; + // value method cpu_dmem_master_ar_arsize + assign cpu_dmem_master_arsize = + ug_uncached_mem_shim_master_u_ar_peekWire$wget[20:18] ; - // value method cpu_dmem_master_m_arvalid - assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ; + // value method cpu_dmem_master_ar_arburst + assign cpu_dmem_master_arburst = + ug_uncached_mem_shim_master_u_ar_peekWire$wget[17:16] ; - // value method cpu_dmem_master_m_arid - assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ; + // value method cpu_dmem_master_ar_arlock + assign cpu_dmem_master_arlock = + ug_uncached_mem_shim_master_u_ar_peekWire$wget[15] ; - // value method cpu_dmem_master_m_araddr - assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ; + // value method cpu_dmem_master_ar_arcache + assign cpu_dmem_master_arcache = + ug_uncached_mem_shim_master_u_ar_peekWire$wget[14:11] ; - // value method cpu_dmem_master_m_arlen - assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ; + // value method cpu_dmem_master_ar_arprot + assign cpu_dmem_master_arprot = + ug_uncached_mem_shim_master_u_ar_peekWire$wget[10:8] ; - // value method cpu_dmem_master_m_arsize - assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ; + // value method cpu_dmem_master_ar_arqos + assign cpu_dmem_master_arqos = + ug_uncached_mem_shim_master_u_ar_peekWire$wget[7:4] ; - // value method cpu_dmem_master_m_arburst - assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ; + // value method cpu_dmem_master_ar_arregion + assign cpu_dmem_master_arregion = + ug_uncached_mem_shim_master_u_ar_peekWire$wget[3:0] ; - // value method cpu_dmem_master_m_arlock - assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ; + // value method cpu_dmem_master_ar_arvalid + assign cpu_dmem_master_arvalid = uncached_mem_shim_arff$EMPTY_N ; - // value method cpu_dmem_master_m_arcache - assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ; + // action method cpu_dmem_master_ar_arready + assign CAN_FIRE_cpu_dmem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_ar_arready = 1'd1 ; - // value method cpu_dmem_master_m_arprot - assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ; + // action method cpu_dmem_master_r_rflit + assign CAN_FIRE_cpu_dmem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_r_rflit = cpu_dmem_master_rvalid ; - // value method cpu_dmem_master_m_arqos - assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ; - - // value method cpu_dmem_master_m_arregion - assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ; - - // action method cpu_dmem_master_m_arready - assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - - // action method cpu_dmem_master_m_rvalid - assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - - // value method cpu_dmem_master_m_rready - assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ; + // value method cpu_dmem_master_r_rready + assign cpu_dmem_master_rready = uncached_mem_shim_rff$FULL_N ; // action method core_external_interrupt_sources_0_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; @@ -1836,63 +3291,47 @@ module mkCoreW(CLK, assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - // action method debug_external_interrupt_req - assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ; + // action method nmi_req + assign CAN_FIRE_nmi_req = 1'd1 ; + assign WILL_FIRE_nmi_req = 1'd1 ; - // actionvalue method tv_verifier_info_get_get - assign tv_verifier_info_get_get = tv_encode$tv_vb_out_get ; - assign RDY_tv_verifier_info_get_get = tv_encode$RDY_tv_vb_out_get ; - assign CAN_FIRE_tv_verifier_info_get_get = tv_encode$RDY_tv_vb_out_get ; - assign WILL_FIRE_tv_verifier_info_get_get = EN_tv_verifier_info_get_get ; + // action method dmi_read_addr + assign RDY_dmi_read_addr = debug_module$RDY_dmi_read_addr ; + assign CAN_FIRE_dmi_read_addr = debug_module$RDY_dmi_read_addr ; + assign WILL_FIRE_dmi_read_addr = EN_dmi_read_addr ; - // action method dm_dmi_read_addr - assign RDY_dm_dmi_read_addr = debug_module$RDY_dmi_read_addr ; - assign CAN_FIRE_dm_dmi_read_addr = debug_module$RDY_dmi_read_addr ; - assign WILL_FIRE_dm_dmi_read_addr = EN_dm_dmi_read_addr ; + // actionvalue method dmi_read_data + assign dmi_read_data = debug_module$dmi_read_data ; + assign RDY_dmi_read_data = debug_module$RDY_dmi_read_data ; + assign CAN_FIRE_dmi_read_data = debug_module$RDY_dmi_read_data ; + assign WILL_FIRE_dmi_read_data = EN_dmi_read_data ; - // actionvalue method dm_dmi_read_data - assign dm_dmi_read_data = debug_module$dmi_read_data ; - assign RDY_dm_dmi_read_data = debug_module$RDY_dmi_read_data ; - assign CAN_FIRE_dm_dmi_read_data = debug_module$RDY_dmi_read_data ; - assign WILL_FIRE_dm_dmi_read_data = EN_dm_dmi_read_data ; + // action method dmi_write + assign RDY_dmi_write = debug_module$RDY_dmi_write ; + assign CAN_FIRE_dmi_write = debug_module$RDY_dmi_write ; + assign WILL_FIRE_dmi_write = EN_dmi_write ; - // action method dm_dmi_write - assign RDY_dm_dmi_write = debug_module$RDY_dmi_write ; - assign CAN_FIRE_dm_dmi_write = debug_module$RDY_dmi_write ; - assign WILL_FIRE_dm_dmi_write = EN_dm_dmi_write ; + // actionvalue method ndm_reset_client_request_get + assign ndm_reset_client_request_get = + debug_module$ndm_reset_client_request_get ; + assign RDY_ndm_reset_client_request_get = + debug_module$RDY_ndm_reset_client_request_get ; + assign CAN_FIRE_ndm_reset_client_request_get = + debug_module$RDY_ndm_reset_client_request_get ; + assign WILL_FIRE_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; - // action method dm_ndm_reset_req_get_get - assign RDY_dm_ndm_reset_req_get_get = - debug_module$RDY_get_ndm_reset_req_get ; - assign CAN_FIRE_dm_ndm_reset_req_get_get = - debug_module$RDY_get_ndm_reset_req_get ; - assign WILL_FIRE_dm_ndm_reset_req_get_get = EN_dm_ndm_reset_req_get_get ; - - // submodule cpu_halt - MakeResetA #(.RSTDELAY(32'd50), .init(1'd0)) cpu_halt(.CLK(CLK), - .RST(RST_N), - .DST_CLK(CLK), - .ASSERT_IN(cpu_halt$ASSERT_IN), - .ASSERT_OUT(cpu_halt$ASSERT_OUT), - .OUT_RST(cpu_halt$OUT_RST)); - - // submodule cpu_reset - MakeResetA #(.RSTDELAY(32'd50), .init(1'd0)) cpu_reset(.CLK(CLK), - .RST(RST_N), - .DST_CLK(CLK), - .ASSERT_IN(cpu_reset$ASSERT_IN), - .ASSERT_OUT(cpu_reset$ASSERT_OUT), - .OUT_RST(cpu_reset$OUT_RST)); - - // submodule cpu_reset_either - ResetEither cpu_reset_either(.A_RST(cpu_reset$OUT_RST), - .B_RST(cpu_halt$OUT_RST), - .RST_OUT(cpu_reset_either$RST_OUT)); + // action method ndm_reset_client_response_put + assign RDY_ndm_reset_client_response_put = + debug_module$RDY_ndm_reset_client_response_put ; + assign CAN_FIRE_ndm_reset_client_response_put = + debug_module$RDY_ndm_reset_client_response_put ; + assign WILL_FIRE_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // submodule debug_module mkDebug_Module debug_module(.CLK(CLK), - .RST_N(RST_N), + .RST_N(RST_N_dm_power_on_reset), .dmi_read_addr_dm_addr(debug_module$dmi_read_addr_dm_addr), .dmi_write_dm_addr(debug_module$dmi_write_dm_addr), .dmi_write_dm_word(debug_module$dmi_write_dm_word), @@ -1900,21 +3339,23 @@ module mkCoreW(CLK, .hart0_csr_mem_client_response_put(debug_module$hart0_csr_mem_client_response_put), .hart0_fpr_mem_client_response_put(debug_module$hart0_fpr_mem_client_response_put), .hart0_gpr_mem_client_response_put(debug_module$hart0_gpr_mem_client_response_put), + .hart0_reset_client_response_put(debug_module$hart0_reset_client_response_put), .master_arready(debug_module$master_arready), .master_awready(debug_module$master_awready), .master_bid(debug_module$master_bid), .master_bresp(debug_module$master_bresp), - .master_bvalid(debug_module$master_bvalid), .master_rdata(debug_module$master_rdata), .master_rid(debug_module$master_rid), .master_rlast(debug_module$master_rlast), .master_rresp(debug_module$master_rresp), - .master_rvalid(debug_module$master_rvalid), + .master_ruser(debug_module$master_ruser), .master_wready(debug_module$master_wready), + .ndm_reset_client_response_put(debug_module$ndm_reset_client_response_put), .EN_dmi_read_addr(debug_module$EN_dmi_read_addr), .EN_dmi_read_data(debug_module$EN_dmi_read_data), .EN_dmi_write(debug_module$EN_dmi_write), - .EN_hart0_get_reset_req_get(debug_module$EN_hart0_get_reset_req_get), + .EN_hart0_reset_client_request_get(debug_module$EN_hart0_reset_client_request_get), + .EN_hart0_reset_client_response_put(debug_module$EN_hart0_reset_client_response_put), .EN_hart0_client_run_halt_request_get(debug_module$EN_hart0_client_run_halt_request_get), .EN_hart0_client_run_halt_response_put(debug_module$EN_hart0_client_run_halt_response_put), .EN_hart0_get_other_req_get(debug_module$EN_hart0_get_other_req_get), @@ -1924,28 +3365,34 @@ module mkCoreW(CLK, .EN_hart0_fpr_mem_client_response_put(debug_module$EN_hart0_fpr_mem_client_response_put), .EN_hart0_csr_mem_client_request_get(debug_module$EN_hart0_csr_mem_client_request_get), .EN_hart0_csr_mem_client_response_put(debug_module$EN_hart0_csr_mem_client_response_put), - .EN_get_ndm_reset_req_get(debug_module$EN_get_ndm_reset_req_get), + .EN_ndm_reset_client_request_get(debug_module$EN_ndm_reset_client_request_get), + .EN_ndm_reset_client_response_put(debug_module$EN_ndm_reset_client_response_put), + .master_bvalid(debug_module$master_bvalid), + .master_rvalid(debug_module$master_rvalid), .RDY_dmi_read_addr(debug_module$RDY_dmi_read_addr), .dmi_read_data(debug_module$dmi_read_data), .RDY_dmi_read_data(debug_module$RDY_dmi_read_data), .RDY_dmi_write(debug_module$RDY_dmi_write), - .RDY_hart0_get_reset_req_get(debug_module$RDY_hart0_get_reset_req_get), + .hart0_reset_client_request_get(), + .RDY_hart0_reset_client_request_get(debug_module$RDY_hart0_reset_client_request_get), + .RDY_hart0_reset_client_response_put(debug_module$RDY_hart0_reset_client_response_put), .hart0_client_run_halt_request_get(debug_module$hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_request_get(debug_module$RDY_hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_response_put(debug_module$RDY_hart0_client_run_halt_response_put), - .hart0_get_other_req_get(), - .RDY_hart0_get_other_req_get(), - .hart0_gpr_mem_client_request_get(), + .hart0_get_other_req_get(debug_module$hart0_get_other_req_get), + .RDY_hart0_get_other_req_get(debug_module$RDY_hart0_get_other_req_get), + .hart0_gpr_mem_client_request_get(debug_module$hart0_gpr_mem_client_request_get), .RDY_hart0_gpr_mem_client_request_get(debug_module$RDY_hart0_gpr_mem_client_request_get), .RDY_hart0_gpr_mem_client_response_put(debug_module$RDY_hart0_gpr_mem_client_response_put), .hart0_fpr_mem_client_request_get(), - .RDY_hart0_fpr_mem_client_request_get(debug_module$RDY_hart0_fpr_mem_client_request_get), - .RDY_hart0_fpr_mem_client_response_put(debug_module$RDY_hart0_fpr_mem_client_response_put), - .hart0_csr_mem_client_request_get(), + .RDY_hart0_fpr_mem_client_request_get(), + .RDY_hart0_fpr_mem_client_response_put(), + .hart0_csr_mem_client_request_get(debug_module$hart0_csr_mem_client_request_get), .RDY_hart0_csr_mem_client_request_get(debug_module$RDY_hart0_csr_mem_client_request_get), .RDY_hart0_csr_mem_client_response_put(debug_module$RDY_hart0_csr_mem_client_response_put), - .RDY_get_ndm_reset_req_get(debug_module$RDY_get_ndm_reset_req_get), - .master_awvalid(debug_module$master_awvalid), + .ndm_reset_client_request_get(debug_module$ndm_reset_client_request_get), + .RDY_ndm_reset_client_request_get(debug_module$RDY_ndm_reset_client_request_get), + .RDY_ndm_reset_client_response_put(debug_module$RDY_ndm_reset_client_response_put), .master_awid(debug_module$master_awid), .master_awaddr(debug_module$master_awaddr), .master_awlen(debug_module$master_awlen), @@ -1956,13 +3403,13 @@ module mkCoreW(CLK, .master_awprot(debug_module$master_awprot), .master_awqos(debug_module$master_awqos), .master_awregion(debug_module$master_awregion), - .master_wvalid(debug_module$master_wvalid), - .master_wid(debug_module$master_wid), + .master_awvalid(debug_module$master_awvalid), .master_wdata(debug_module$master_wdata), .master_wstrb(debug_module$master_wstrb), .master_wlast(debug_module$master_wlast), + .master_wuser(debug_module$master_wuser), + .master_wvalid(debug_module$master_wvalid), .master_bready(debug_module$master_bready), - .master_arvalid(debug_module$master_arvalid), .master_arid(debug_module$master_arid), .master_araddr(debug_module$master_araddr), .master_arlen(debug_module$master_arlen), @@ -1973,343 +3420,360 @@ module mkCoreW(CLK, .master_arprot(debug_module$master_arprot), .master_arqos(debug_module$master_arqos), .master_arregion(debug_module$master_arregion), + .master_arvalid(debug_module$master_arvalid), .master_rready(debug_module$master_rready)); - // submodule dm_mem_tap - mkDM_Mem_Tap dm_mem_tap(.CLK(CLK), - .RST_N(RST_N), - .master_arready(dm_mem_tap$master_arready), - .master_awready(dm_mem_tap$master_awready), - .master_bid(dm_mem_tap$master_bid), - .master_bresp(dm_mem_tap$master_bresp), - .master_bvalid(dm_mem_tap$master_bvalid), - .master_rdata(dm_mem_tap$master_rdata), - .master_rid(dm_mem_tap$master_rid), - .master_rlast(dm_mem_tap$master_rlast), - .master_rresp(dm_mem_tap$master_rresp), - .master_rvalid(dm_mem_tap$master_rvalid), - .master_wready(dm_mem_tap$master_wready), - .slave_araddr(dm_mem_tap$slave_araddr), - .slave_arburst(dm_mem_tap$slave_arburst), - .slave_arcache(dm_mem_tap$slave_arcache), - .slave_arid(dm_mem_tap$slave_arid), - .slave_arlen(dm_mem_tap$slave_arlen), - .slave_arlock(dm_mem_tap$slave_arlock), - .slave_arprot(dm_mem_tap$slave_arprot), - .slave_arqos(dm_mem_tap$slave_arqos), - .slave_arregion(dm_mem_tap$slave_arregion), - .slave_arsize(dm_mem_tap$slave_arsize), - .slave_arvalid(dm_mem_tap$slave_arvalid), - .slave_awaddr(dm_mem_tap$slave_awaddr), - .slave_awburst(dm_mem_tap$slave_awburst), - .slave_awcache(dm_mem_tap$slave_awcache), - .slave_awid(dm_mem_tap$slave_awid), - .slave_awlen(dm_mem_tap$slave_awlen), - .slave_awlock(dm_mem_tap$slave_awlock), - .slave_awprot(dm_mem_tap$slave_awprot), - .slave_awqos(dm_mem_tap$slave_awqos), - .slave_awregion(dm_mem_tap$slave_awregion), - .slave_awsize(dm_mem_tap$slave_awsize), - .slave_awvalid(dm_mem_tap$slave_awvalid), - .slave_bready(dm_mem_tap$slave_bready), - .slave_rready(dm_mem_tap$slave_rready), - .slave_wdata(dm_mem_tap$slave_wdata), - .slave_wid(dm_mem_tap$slave_wid), - .slave_wlast(dm_mem_tap$slave_wlast), - .slave_wstrb(dm_mem_tap$slave_wstrb), - .slave_wvalid(dm_mem_tap$slave_wvalid), - .EN_trace_data_out_get(dm_mem_tap$EN_trace_data_out_get), - .slave_awready(dm_mem_tap$slave_awready), - .slave_wready(dm_mem_tap$slave_wready), - .slave_bvalid(dm_mem_tap$slave_bvalid), - .slave_bid(dm_mem_tap$slave_bid), - .slave_bresp(dm_mem_tap$slave_bresp), - .slave_arready(dm_mem_tap$slave_arready), - .slave_rvalid(dm_mem_tap$slave_rvalid), - .slave_rid(dm_mem_tap$slave_rid), - .slave_rdata(dm_mem_tap$slave_rdata), - .slave_rresp(dm_mem_tap$slave_rresp), - .slave_rlast(dm_mem_tap$slave_rlast), - .master_awvalid(dm_mem_tap$master_awvalid), - .master_awid(dm_mem_tap$master_awid), - .master_awaddr(dm_mem_tap$master_awaddr), - .master_awlen(dm_mem_tap$master_awlen), - .master_awsize(dm_mem_tap$master_awsize), - .master_awburst(dm_mem_tap$master_awburst), - .master_awlock(dm_mem_tap$master_awlock), - .master_awcache(dm_mem_tap$master_awcache), - .master_awprot(dm_mem_tap$master_awprot), - .master_awqos(dm_mem_tap$master_awqos), - .master_awregion(dm_mem_tap$master_awregion), - .master_wvalid(dm_mem_tap$master_wvalid), - .master_wid(dm_mem_tap$master_wid), - .master_wdata(dm_mem_tap$master_wdata), - .master_wstrb(dm_mem_tap$master_wstrb), - .master_wlast(dm_mem_tap$master_wlast), - .master_bready(dm_mem_tap$master_bready), - .master_arvalid(dm_mem_tap$master_arvalid), - .master_arid(dm_mem_tap$master_arid), - .master_araddr(dm_mem_tap$master_araddr), - .master_arlen(dm_mem_tap$master_arlen), - .master_arsize(dm_mem_tap$master_arsize), - .master_arburst(dm_mem_tap$master_arburst), - .master_arlock(dm_mem_tap$master_arlock), - .master_arcache(dm_mem_tap$master_arcache), - .master_arprot(dm_mem_tap$master_arprot), - .master_arqos(dm_mem_tap$master_arqos), - .master_arregion(dm_mem_tap$master_arregion), - .master_rready(dm_mem_tap$master_rready), - .trace_data_out_get(dm_mem_tap$trace_data_out_get), - .RDY_trace_data_out_get(dm_mem_tap$RDY_trace_data_out_get)); + // submodule dm_hart0_reset_controller + MakeResetA #(.RSTDELAY(32'd10), + .init(1'd1)) dm_hart0_reset_controller(.CLK(CLK), + .RST(RST_N), + .DST_CLK(CLK), + .ASSERT_IN(dm_hart0_reset_controller$ASSERT_IN), + .ASSERT_OUT(), + .OUT_RST(dm_hart0_reset_controller$OUT_RST)); - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); + // submodule hart0_reset + ResetEither hart0_reset(.A_RST(RST_N), + .B_RST(dm_hart0_reset_controller$OUT_RST), + .RST_OUT(hart0_reset$RST_OUT)); - // submodule f_reset_requestor - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_requestor(.RST(RST_N), + // submodule ifcs_0_1_innerReq + FIFO2 #(.width(32'd98), .guarded(32'd1)) ifcs_0_1_innerReq(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_innerReq$D_IN), + .ENQ(ifcs_0_1_innerReq$ENQ), + .DEQ(ifcs_0_1_innerReq$DEQ), + .CLR(ifcs_0_1_innerReq$CLR), + .D_OUT(ifcs_0_1_innerReq$D_OUT), + .FULL_N(ifcs_0_1_innerReq$FULL_N), + .EMPTY_N(ifcs_0_1_innerReq$EMPTY_N)); + + // submodule ifcs_0_1_innerRoute + FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_0_1_innerRoute(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_innerRoute$D_IN), + .ENQ(ifcs_0_1_innerRoute$ENQ), + .DEQ(ifcs_0_1_innerRoute$DEQ), + .CLR(ifcs_0_1_innerRoute$CLR), + .D_OUT(ifcs_0_1_innerRoute$D_OUT), + .FULL_N(ifcs_0_1_innerRoute$FULL_N), + .EMPTY_N(ifcs_0_1_innerRoute$EMPTY_N)); + + // submodule ifcs_0_1_noRouteRsp + FIFO2 #(.width(32'd72), .guarded(32'd1)) ifcs_0_1_noRouteRsp(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_noRouteRsp$D_IN), + .ENQ(ifcs_0_1_noRouteRsp$ENQ), + .DEQ(ifcs_0_1_noRouteRsp$DEQ), + .CLR(ifcs_0_1_noRouteRsp$CLR), + .D_OUT(ifcs_0_1_noRouteRsp$D_OUT), + .FULL_N(ifcs_0_1_noRouteRsp$FULL_N), + .EMPTY_N(ifcs_0_1_noRouteRsp$EMPTY_N)); + + // submodule ifcs_0_1_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_0_1_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_routeBack$D_IN), + .ENQ(ifcs_0_1_routeBack$ENQ), + .DEQ(ifcs_0_1_routeBack$DEQ), + .CLR(ifcs_0_1_routeBack$CLR), + .D_OUT(ifcs_0_1_routeBack$D_OUT), + .FULL_N(ifcs_0_1_routeBack$FULL_N), + .EMPTY_N(ifcs_0_1_routeBack$EMPTY_N)); + + // submodule ifcs_0_1_rspBack + FIFO2 #(.width(32'd72), .guarded(32'd1)) ifcs_0_1_rspBack(.RST(RST_N), .CLK(CLK), - .D_IN(f_reset_requestor$D_IN), - .ENQ(f_reset_requestor$ENQ), - .DEQ(f_reset_requestor$DEQ), - .CLR(f_reset_requestor$CLR), - .D_OUT(f_reset_requestor$D_OUT), - .FULL_N(f_reset_requestor$FULL_N), - .EMPTY_N(f_reset_requestor$EMPTY_N)); + .D_IN(ifcs_0_1_rspBack$D_IN), + .ENQ(ifcs_0_1_rspBack$ENQ), + .DEQ(ifcs_0_1_rspBack$DEQ), + .CLR(ifcs_0_1_rspBack$CLR), + .D_OUT(ifcs_0_1_rspBack$D_OUT), + .FULL_N(ifcs_0_1_rspBack$FULL_N), + .EMPTY_N(ifcs_0_1_rspBack$EMPTY_N)); - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); + // submodule ifcs_0_innerReq + FIFO2 #(.width(32'd173), .guarded(32'd1)) ifcs_0_innerReq(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_innerReq$D_IN), + .ENQ(ifcs_0_innerReq$ENQ), + .DEQ(ifcs_0_innerReq$DEQ), + .CLR(ifcs_0_innerReq$CLR), + .D_OUT(ifcs_0_innerReq$D_OUT), + .FULL_N(ifcs_0_innerReq$FULL_N), + .EMPTY_N(ifcs_0_innerReq$EMPTY_N)); - // submodule f_trace_data_merged - FIFO2 #(.width(32'd362), .guarded(32'd1)) f_trace_data_merged(.RST(RST_N), - .CLK(CLK), - .D_IN(f_trace_data_merged$D_IN), - .ENQ(f_trace_data_merged$ENQ), - .DEQ(f_trace_data_merged$DEQ), - .CLR(f_trace_data_merged$CLR), - .D_OUT(f_trace_data_merged$D_OUT), - .FULL_N(f_trace_data_merged$FULL_N), - .EMPTY_N(f_trace_data_merged$EMPTY_N)); + // submodule ifcs_0_innerRoute + FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_0_innerRoute(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_innerRoute$D_IN), + .ENQ(ifcs_0_innerRoute$ENQ), + .DEQ(ifcs_0_innerRoute$DEQ), + .CLR(ifcs_0_innerRoute$CLR), + .D_OUT(ifcs_0_innerRoute$D_OUT), + .FULL_N(ifcs_0_innerRoute$FULL_N), + .EMPTY_N(ifcs_0_innerRoute$EMPTY_N)); - // submodule fabric_2x3 - mkFabric_2x3 fabric_2x3(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric_2x3$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric_2x3$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), - .EN_reset(fabric_2x3$EN_reset), - .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast), - .v_from_masters_1_awready(fabric_2x3$v_from_masters_1_awready), - .v_from_masters_1_wready(fabric_2x3$v_from_masters_1_wready), - .v_from_masters_1_bvalid(fabric_2x3$v_from_masters_1_bvalid), - .v_from_masters_1_bid(fabric_2x3$v_from_masters_1_bid), - .v_from_masters_1_bresp(fabric_2x3$v_from_masters_1_bresp), - .v_from_masters_1_arready(fabric_2x3$v_from_masters_1_arready), - .v_from_masters_1_rvalid(fabric_2x3$v_from_masters_1_rvalid), - .v_from_masters_1_rid(fabric_2x3$v_from_masters_1_rid), - .v_from_masters_1_rdata(fabric_2x3$v_from_masters_1_rdata), - .v_from_masters_1_rresp(fabric_2x3$v_from_masters_1_rresp), - .v_from_masters_1_rlast(fabric_2x3$v_from_masters_1_rlast), - .v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric_2x3$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric_2x3$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(), - .v_to_slaves_2_awid(), - .v_to_slaves_2_awaddr(), - .v_to_slaves_2_awlen(), - .v_to_slaves_2_awsize(), - .v_to_slaves_2_awburst(), - .v_to_slaves_2_awlock(), - .v_to_slaves_2_awcache(), - .v_to_slaves_2_awprot(), - .v_to_slaves_2_awqos(), - .v_to_slaves_2_awregion(), - .v_to_slaves_2_wvalid(), - .v_to_slaves_2_wid(), - .v_to_slaves_2_wdata(), - .v_to_slaves_2_wstrb(), - .v_to_slaves_2_wlast(), - .v_to_slaves_2_bready(), - .v_to_slaves_2_arvalid(), - .v_to_slaves_2_arid(), - .v_to_slaves_2_araddr(), - .v_to_slaves_2_arlen(), - .v_to_slaves_2_arsize(), - .v_to_slaves_2_arburst(), - .v_to_slaves_2_arlock(), - .v_to_slaves_2_arcache(), - .v_to_slaves_2_arprot(), - .v_to_slaves_2_arqos(), - .v_to_slaves_2_arregion(), - .v_to_slaves_2_rready()); + // submodule ifcs_0_noRouteRsp + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_0_noRouteRsp(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_noRouteRsp$D_IN), + .ENQ(ifcs_0_noRouteRsp$ENQ), + .DEQ(ifcs_0_noRouteRsp$DEQ), + .CLR(ifcs_0_noRouteRsp$CLR), + .D_OUT(ifcs_0_noRouteRsp$D_OUT), + .FULL_N(ifcs_0_noRouteRsp$FULL_N), + .EMPTY_N(ifcs_0_noRouteRsp$EMPTY_N)); + + // submodule ifcs_0_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_0_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_routeBack$D_IN), + .ENQ(ifcs_0_routeBack$ENQ), + .DEQ(ifcs_0_routeBack$DEQ), + .CLR(ifcs_0_routeBack$CLR), + .D_OUT(ifcs_0_routeBack$D_OUT), + .FULL_N(ifcs_0_routeBack$FULL_N), + .EMPTY_N(ifcs_0_routeBack$EMPTY_N)); + + // submodule ifcs_0_rspBack + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_0_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_rspBack$D_IN), + .ENQ(ifcs_0_rspBack$ENQ), + .DEQ(ifcs_0_rspBack$DEQ), + .CLR(ifcs_0_rspBack$CLR), + .D_OUT(ifcs_0_rspBack$D_OUT), + .FULL_N(ifcs_0_rspBack$FULL_N), + .EMPTY_N(ifcs_0_rspBack$EMPTY_N)); + + // submodule ifcs_1_1_innerReq + FIFO2 #(.width(32'd98), .guarded(32'd1)) ifcs_1_1_innerReq(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_innerReq$D_IN), + .ENQ(ifcs_1_1_innerReq$ENQ), + .DEQ(ifcs_1_1_innerReq$DEQ), + .CLR(ifcs_1_1_innerReq$CLR), + .D_OUT(ifcs_1_1_innerReq$D_OUT), + .FULL_N(ifcs_1_1_innerReq$FULL_N), + .EMPTY_N(ifcs_1_1_innerReq$EMPTY_N)); + + // submodule ifcs_1_1_innerRoute + FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_1_1_innerRoute(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_innerRoute$D_IN), + .ENQ(ifcs_1_1_innerRoute$ENQ), + .DEQ(ifcs_1_1_innerRoute$DEQ), + .CLR(ifcs_1_1_innerRoute$CLR), + .D_OUT(ifcs_1_1_innerRoute$D_OUT), + .FULL_N(ifcs_1_1_innerRoute$FULL_N), + .EMPTY_N(ifcs_1_1_innerRoute$EMPTY_N)); + + // submodule ifcs_1_1_noRouteRsp + FIFO2 #(.width(32'd72), .guarded(32'd1)) ifcs_1_1_noRouteRsp(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_noRouteRsp$D_IN), + .ENQ(ifcs_1_1_noRouteRsp$ENQ), + .DEQ(ifcs_1_1_noRouteRsp$DEQ), + .CLR(ifcs_1_1_noRouteRsp$CLR), + .D_OUT(ifcs_1_1_noRouteRsp$D_OUT), + .FULL_N(ifcs_1_1_noRouteRsp$FULL_N), + .EMPTY_N(ifcs_1_1_noRouteRsp$EMPTY_N)); + + // submodule ifcs_1_1_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_1_1_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_routeBack$D_IN), + .ENQ(ifcs_1_1_routeBack$ENQ), + .DEQ(ifcs_1_1_routeBack$DEQ), + .CLR(ifcs_1_1_routeBack$CLR), + .D_OUT(ifcs_1_1_routeBack$D_OUT), + .FULL_N(ifcs_1_1_routeBack$FULL_N), + .EMPTY_N(ifcs_1_1_routeBack$EMPTY_N)); + + // submodule ifcs_1_1_rspBack + FIFO2 #(.width(32'd72), .guarded(32'd1)) ifcs_1_1_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_rspBack$D_IN), + .ENQ(ifcs_1_1_rspBack$ENQ), + .DEQ(ifcs_1_1_rspBack$DEQ), + .CLR(ifcs_1_1_rspBack$CLR), + .D_OUT(ifcs_1_1_rspBack$D_OUT), + .FULL_N(ifcs_1_1_rspBack$FULL_N), + .EMPTY_N(ifcs_1_1_rspBack$EMPTY_N)); + + // submodule ifcs_1_innerReq + FIFO2 #(.width(32'd173), .guarded(32'd1)) ifcs_1_innerReq(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_innerReq$D_IN), + .ENQ(ifcs_1_innerReq$ENQ), + .DEQ(ifcs_1_innerReq$DEQ), + .CLR(ifcs_1_innerReq$CLR), + .D_OUT(ifcs_1_innerReq$D_OUT), + .FULL_N(ifcs_1_innerReq$FULL_N), + .EMPTY_N(ifcs_1_innerReq$EMPTY_N)); + + // submodule ifcs_1_innerRoute + FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_1_innerRoute(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_innerRoute$D_IN), + .ENQ(ifcs_1_innerRoute$ENQ), + .DEQ(ifcs_1_innerRoute$DEQ), + .CLR(ifcs_1_innerRoute$CLR), + .D_OUT(ifcs_1_innerRoute$D_OUT), + .FULL_N(ifcs_1_innerRoute$FULL_N), + .EMPTY_N(ifcs_1_innerRoute$EMPTY_N)); + + // submodule ifcs_1_noRouteRsp + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_1_noRouteRsp(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_noRouteRsp$D_IN), + .ENQ(ifcs_1_noRouteRsp$ENQ), + .DEQ(ifcs_1_noRouteRsp$DEQ), + .CLR(ifcs_1_noRouteRsp$CLR), + .D_OUT(ifcs_1_noRouteRsp$D_OUT), + .FULL_N(ifcs_1_noRouteRsp$FULL_N), + .EMPTY_N(ifcs_1_noRouteRsp$EMPTY_N)); + + // submodule ifcs_1_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_1_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_routeBack$D_IN), + .ENQ(ifcs_1_routeBack$ENQ), + .DEQ(ifcs_1_routeBack$DEQ), + .CLR(ifcs_1_routeBack$CLR), + .D_OUT(ifcs_1_routeBack$D_OUT), + .FULL_N(ifcs_1_routeBack$FULL_N), + .EMPTY_N(ifcs_1_routeBack$EMPTY_N)); + + // submodule ifcs_1_rspBack + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_1_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_rspBack$D_IN), + .ENQ(ifcs_1_rspBack$ENQ), + .DEQ(ifcs_1_rspBack$DEQ), + .CLR(ifcs_1_rspBack$CLR), + .D_OUT(ifcs_1_rspBack$D_OUT), + .FULL_N(ifcs_1_rspBack$FULL_N), + .EMPTY_N(ifcs_1_rspBack$EMPTY_N)); + + // submodule ifcs_2_1_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_2_1_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_2_1_routeBack$D_IN), + .ENQ(ifcs_2_1_routeBack$ENQ), + .DEQ(ifcs_2_1_routeBack$DEQ), + .CLR(ifcs_2_1_routeBack$CLR), + .D_OUT(ifcs_2_1_routeBack$D_OUT), + .FULL_N(ifcs_2_1_routeBack$FULL_N), + .EMPTY_N(ifcs_2_1_routeBack$EMPTY_N)); + + // submodule ifcs_2_1_rspBack + FIFO2 #(.width(32'd72), .guarded(32'd1)) ifcs_2_1_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_2_1_rspBack$D_IN), + .ENQ(ifcs_2_1_rspBack$ENQ), + .DEQ(ifcs_2_1_rspBack$DEQ), + .CLR(ifcs_2_1_rspBack$CLR), + .D_OUT(ifcs_2_1_rspBack$D_OUT), + .FULL_N(ifcs_2_1_rspBack$FULL_N), + .EMPTY_N(ifcs_2_1_rspBack$EMPTY_N)); + + // submodule ifcs_2_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_2_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_2_routeBack$D_IN), + .ENQ(ifcs_2_routeBack$ENQ), + .DEQ(ifcs_2_routeBack$DEQ), + .CLR(ifcs_2_routeBack$CLR), + .D_OUT(ifcs_2_routeBack$D_OUT), + .FULL_N(ifcs_2_routeBack$FULL_N), + .EMPTY_N(ifcs_2_routeBack$EMPTY_N)); + + // submodule ifcs_2_rspBack + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_2_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_2_rspBack$D_IN), + .ENQ(ifcs_2_rspBack$ENQ), + .DEQ(ifcs_2_rspBack$DEQ), + .CLR(ifcs_2_rspBack$CLR), + .D_OUT(ifcs_2_rspBack$D_OUT), + .FULL_N(ifcs_2_rspBack$FULL_N), + .EMPTY_N(ifcs_2_rspBack$EMPTY_N)); + + // submodule msNoSynth_0_b_buffer_ff + FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_0_b_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_b_buffer_ff$D_IN), + .ENQ(msNoSynth_0_b_buffer_ff$ENQ), + .DEQ(msNoSynth_0_b_buffer_ff$DEQ), + .CLR(msNoSynth_0_b_buffer_ff$CLR), + .D_OUT(msNoSynth_0_b_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_b_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_b_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_b_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_0_b_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_b_buffer_firstValid$D_IN), + .EN(msNoSynth_0_b_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_b_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_0_r_buffer_ff + FIFO1 #(.width(32'd72), + .guarded(32'd0)) msNoSynth_0_r_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_r_buffer_ff$D_IN), + .ENQ(msNoSynth_0_r_buffer_ff$ENQ), + .DEQ(msNoSynth_0_r_buffer_ff$DEQ), + .CLR(msNoSynth_0_r_buffer_ff$CLR), + .D_OUT(msNoSynth_0_r_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_r_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_r_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_r_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_0_r_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_r_buffer_firstValid$D_IN), + .EN(msNoSynth_0_r_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_r_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_b_buffer_ff + FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_1_b_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_b_buffer_ff$D_IN), + .ENQ(msNoSynth_1_b_buffer_ff$ENQ), + .DEQ(msNoSynth_1_b_buffer_ff$DEQ), + .CLR(msNoSynth_1_b_buffer_ff$CLR), + .D_OUT(msNoSynth_1_b_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_b_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_b_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_b_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_b_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_b_buffer_firstValid$D_IN), + .EN(msNoSynth_1_b_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_b_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_r_buffer_ff + FIFO1 #(.width(32'd72), + .guarded(32'd0)) msNoSynth_1_r_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_r_buffer_ff$D_IN), + .ENQ(msNoSynth_1_r_buffer_ff$ENQ), + .DEQ(msNoSynth_1_r_buffer_ff$DEQ), + .CLR(msNoSynth_1_r_buffer_ff$CLR), + .D_OUT(msNoSynth_1_r_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_r_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_r_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_r_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_r_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_r_buffer_firstValid$D_IN), + .EN(msNoSynth_1_r_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_r_buffer_firstValid$Q_OUT)); // submodule plic mkPLIC_16_2_7 plic(.CLK(CLK), @@ -2324,7 +3788,6 @@ module mkCoreW(CLK, .axi4_slave_arqos(plic$axi4_slave_arqos), .axi4_slave_arregion(plic$axi4_slave_arregion), .axi4_slave_arsize(plic$axi4_slave_arsize), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), .axi4_slave_awaddr(plic$axi4_slave_awaddr), .axi4_slave_awburst(plic$axi4_slave_awburst), .axi4_slave_awcache(plic$axi4_slave_awcache), @@ -2335,14 +3798,12 @@ module mkCoreW(CLK, .axi4_slave_awqos(plic$axi4_slave_awqos), .axi4_slave_awregion(plic$axi4_slave_awregion), .axi4_slave_awsize(plic$axi4_slave_awsize), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), .axi4_slave_bready(plic$axi4_slave_bready), .axi4_slave_rready(plic$axi4_slave_rready), .axi4_slave_wdata(plic$axi4_slave_wdata), - .axi4_slave_wid(plic$axi4_slave_wid), .axi4_slave_wlast(plic$axi4_slave_wlast), .axi4_slave_wstrb(plic$axi4_slave_wstrb), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), + .axi4_slave_wuser(plic$axi4_slave_wuser), .set_addr_map_addr_base(plic$set_addr_map_addr_base), .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), .set_verbosity_verbosity(plic$set_verbosity_verbosity), @@ -2367,56 +3828,83 @@ module mkCoreW(CLK, .EN_server_reset_request_put(plic$EN_server_reset_request_put), .EN_server_reset_response_get(plic$EN_server_reset_response_get), .EN_set_addr_map(plic$EN_set_addr_map), + .axi4_slave_awvalid(plic$axi4_slave_awvalid), + .axi4_slave_wvalid(plic$axi4_slave_wvalid), + .axi4_slave_arvalid(plic$axi4_slave_arvalid), .RDY_set_verbosity(), .RDY_show_PLIC_state(), - .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), - .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), + .RDY_server_reset_request_put(), + .RDY_server_reset_response_get(), .RDY_set_addr_map(), .axi4_slave_awready(plic$axi4_slave_awready), .axi4_slave_wready(plic$axi4_slave_wready), - .axi4_slave_bvalid(plic$axi4_slave_bvalid), .axi4_slave_bid(plic$axi4_slave_bid), .axi4_slave_bresp(plic$axi4_slave_bresp), + .axi4_slave_bvalid(plic$axi4_slave_bvalid), .axi4_slave_arready(plic$axi4_slave_arready), - .axi4_slave_rvalid(plic$axi4_slave_rvalid), .axi4_slave_rid(plic$axi4_slave_rid), .axi4_slave_rdata(plic$axi4_slave_rdata), .axi4_slave_rresp(plic$axi4_slave_rresp), .axi4_slave_rlast(plic$axi4_slave_rlast), + .axi4_slave_ruser(plic$axi4_slave_ruser), + .axi4_slave_rvalid(plic$axi4_slave_rvalid), .v_targets_0_m_eip(plic$v_targets_0_m_eip), .v_targets_1_m_eip(plic$v_targets_1_m_eip)); // submodule proc mkProc proc(.CLK(CLK), - .RST_N(cpu_reset_either$RST_OUT), - .debug_external_interrupt_req_set_not_clear(proc$debug_external_interrupt_req_set_not_clear), + .RST_N(hart0_reset$RST_OUT), + .debug_module_mem_server_araddr(proc$debug_module_mem_server_araddr), + .debug_module_mem_server_arburst(proc$debug_module_mem_server_arburst), + .debug_module_mem_server_arcache(proc$debug_module_mem_server_arcache), + .debug_module_mem_server_arid(proc$debug_module_mem_server_arid), + .debug_module_mem_server_arlen(proc$debug_module_mem_server_arlen), + .debug_module_mem_server_arlock(proc$debug_module_mem_server_arlock), + .debug_module_mem_server_arprot(proc$debug_module_mem_server_arprot), + .debug_module_mem_server_arqos(proc$debug_module_mem_server_arqos), + .debug_module_mem_server_arregion(proc$debug_module_mem_server_arregion), + .debug_module_mem_server_arsize(proc$debug_module_mem_server_arsize), + .debug_module_mem_server_awaddr(proc$debug_module_mem_server_awaddr), + .debug_module_mem_server_awburst(proc$debug_module_mem_server_awburst), + .debug_module_mem_server_awcache(proc$debug_module_mem_server_awcache), + .debug_module_mem_server_awid(proc$debug_module_mem_server_awid), + .debug_module_mem_server_awlen(proc$debug_module_mem_server_awlen), + .debug_module_mem_server_awlock(proc$debug_module_mem_server_awlock), + .debug_module_mem_server_awprot(proc$debug_module_mem_server_awprot), + .debug_module_mem_server_awqos(proc$debug_module_mem_server_awqos), + .debug_module_mem_server_awregion(proc$debug_module_mem_server_awregion), + .debug_module_mem_server_awsize(proc$debug_module_mem_server_awsize), + .debug_module_mem_server_bready(proc$debug_module_mem_server_bready), + .debug_module_mem_server_rready(proc$debug_module_mem_server_rready), + .debug_module_mem_server_wdata(proc$debug_module_mem_server_wdata), + .debug_module_mem_server_wlast(proc$debug_module_mem_server_wlast), + .debug_module_mem_server_wstrb(proc$debug_module_mem_server_wstrb), + .debug_module_mem_server_wuser(proc$debug_module_mem_server_wuser), .hart0_csr_mem_server_request_put(proc$hart0_csr_mem_server_request_put), .hart0_fpr_mem_server_request_put(proc$hart0_fpr_mem_server_request_put), .hart0_gpr_mem_server_request_put(proc$hart0_gpr_mem_server_request_put), .hart0_put_other_req_put(proc$hart0_put_other_req_put), - .hart0_server_run_halt_request_put(proc$hart0_server_run_halt_request_put), + .hart0_run_halt_server_request_put(proc$hart0_run_halt_server_request_put), .m_external_interrupt_req_set_not_clear(proc$m_external_interrupt_req_set_not_clear), .master0_arready(proc$master0_arready), .master0_awready(proc$master0_awready), .master0_bid(proc$master0_bid), .master0_bresp(proc$master0_bresp), - .master0_bvalid(proc$master0_bvalid), .master0_rdata(proc$master0_rdata), .master0_rid(proc$master0_rid), .master0_rlast(proc$master0_rlast), .master0_rresp(proc$master0_rresp), - .master0_rvalid(proc$master0_rvalid), + .master0_ruser(proc$master0_ruser), .master0_wready(proc$master0_wready), .master1_arready(proc$master1_arready), .master1_awready(proc$master1_awready), .master1_bid(proc$master1_bid), .master1_bresp(proc$master1_bresp), - .master1_bvalid(proc$master1_bvalid), .master1_rdata(proc$master1_rdata), .master1_rid(proc$master1_rid), .master1_rlast(proc$master1_rlast), .master1_rresp(proc$master1_rresp), - .master1_rvalid(proc$master1_rvalid), + .master1_ruser(proc$master1_ruser), .master1_wready(proc$master1_wready), .non_maskable_interrupt_req_set_not_clear(proc$non_maskable_interrupt_req_set_not_clear), .s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear), @@ -2424,24 +3912,25 @@ module mkCoreW(CLK, .start_fromhostAddr(proc$start_fromhostAddr), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), - .EN_hart0_server_reset_request_put(proc$EN_hart0_server_reset_request_put), - .EN_hart0_server_reset_response_get(proc$EN_hart0_server_reset_response_get), .EN_start(proc$EN_start), + .master0_bvalid(proc$master0_bvalid), + .master0_rvalid(proc$master0_rvalid), + .master1_bvalid(proc$master1_bvalid), + .master1_rvalid(proc$master1_rvalid), .EN_set_verbosity(proc$EN_set_verbosity), - .EN_trace_data_out_get(proc$EN_trace_data_out_get), - .EN_hart0_server_run_halt_request_put(proc$EN_hart0_server_run_halt_request_put), - .EN_hart0_server_run_halt_response_get(proc$EN_hart0_server_run_halt_response_get), - .EN_hart0_put_other_req_put(proc$EN_hart0_put_other_req_put), + .debug_module_mem_server_awvalid(proc$debug_module_mem_server_awvalid), + .debug_module_mem_server_wvalid(proc$debug_module_mem_server_wvalid), + .debug_module_mem_server_arvalid(proc$debug_module_mem_server_arvalid), + .EN_hart0_run_halt_server_request_put(proc$EN_hart0_run_halt_server_request_put), + .EN_hart0_run_halt_server_response_get(proc$EN_hart0_run_halt_server_response_get), .EN_hart0_gpr_mem_server_request_put(proc$EN_hart0_gpr_mem_server_request_put), .EN_hart0_gpr_mem_server_response_get(proc$EN_hart0_gpr_mem_server_response_get), .EN_hart0_fpr_mem_server_request_put(proc$EN_hart0_fpr_mem_server_request_put), .EN_hart0_fpr_mem_server_response_get(proc$EN_hart0_fpr_mem_server_response_get), .EN_hart0_csr_mem_server_request_put(proc$EN_hart0_csr_mem_server_request_put), .EN_hart0_csr_mem_server_response_get(proc$EN_hart0_csr_mem_server_response_get), - .RDY_hart0_server_reset_request_put(proc$RDY_hart0_server_reset_request_put), - .RDY_hart0_server_reset_response_get(proc$RDY_hart0_server_reset_response_get), + .EN_hart0_put_other_req_put(proc$EN_hart0_put_other_req_put), .RDY_start(proc$RDY_start), - .master0_awvalid(proc$master0_awvalid), .master0_awid(proc$master0_awid), .master0_awaddr(proc$master0_awaddr), .master0_awlen(proc$master0_awlen), @@ -2452,13 +3941,13 @@ module mkCoreW(CLK, .master0_awprot(proc$master0_awprot), .master0_awqos(proc$master0_awqos), .master0_awregion(proc$master0_awregion), - .master0_wvalid(proc$master0_wvalid), - .master0_wid(proc$master0_wid), + .master0_awvalid(proc$master0_awvalid), .master0_wdata(proc$master0_wdata), .master0_wstrb(proc$master0_wstrb), .master0_wlast(proc$master0_wlast), + .master0_wuser(proc$master0_wuser), + .master0_wvalid(proc$master0_wvalid), .master0_bready(proc$master0_bready), - .master0_arvalid(proc$master0_arvalid), .master0_arid(proc$master0_arid), .master0_araddr(proc$master0_araddr), .master0_arlen(proc$master0_arlen), @@ -2469,8 +3958,8 @@ module mkCoreW(CLK, .master0_arprot(proc$master0_arprot), .master0_arqos(proc$master0_arqos), .master0_arregion(proc$master0_arregion), + .master0_arvalid(proc$master0_arvalid), .master0_rready(proc$master0_rready), - .master1_awvalid(proc$master1_awvalid), .master1_awid(proc$master1_awid), .master1_awaddr(proc$master1_awaddr), .master1_awlen(proc$master1_awlen), @@ -2481,13 +3970,13 @@ module mkCoreW(CLK, .master1_awprot(proc$master1_awprot), .master1_awqos(proc$master1_awqos), .master1_awregion(proc$master1_awregion), - .master1_wvalid(proc$master1_wvalid), - .master1_wid(proc$master1_wid), + .master1_awvalid(proc$master1_awvalid), .master1_wdata(proc$master1_wdata), .master1_wstrb(proc$master1_wstrb), .master1_wlast(proc$master1_wlast), + .master1_wuser(), + .master1_wvalid(proc$master1_wvalid), .master1_bready(proc$master1_bready), - .master1_arvalid(proc$master1_arvalid), .master1_arid(proc$master1_arid), .master1_araddr(proc$master1_araddr), .master1_arlen(proc$master1_arlen), @@ -2498,23 +3987,34 @@ module mkCoreW(CLK, .master1_arprot(proc$master1_arprot), .master1_arqos(proc$master1_arqos), .master1_arregion(proc$master1_arregion), + .master1_arvalid(proc$master1_arvalid), .master1_rready(proc$master1_rready), .RDY_set_verbosity(), - .trace_data_out_get(proc$trace_data_out_get), - .RDY_trace_data_out_get(proc$RDY_trace_data_out_get), - .RDY_hart0_server_run_halt_request_put(), - .hart0_server_run_halt_response_get(), - .RDY_hart0_server_run_halt_response_get(), - .RDY_hart0_put_other_req_put(), - .RDY_hart0_gpr_mem_server_request_put(), - .hart0_gpr_mem_server_response_get(), - .RDY_hart0_gpr_mem_server_response_get(), + .debug_module_mem_server_awready(proc$debug_module_mem_server_awready), + .debug_module_mem_server_wready(proc$debug_module_mem_server_wready), + .debug_module_mem_server_bid(proc$debug_module_mem_server_bid), + .debug_module_mem_server_bresp(proc$debug_module_mem_server_bresp), + .debug_module_mem_server_bvalid(proc$debug_module_mem_server_bvalid), + .debug_module_mem_server_arready(proc$debug_module_mem_server_arready), + .debug_module_mem_server_rid(proc$debug_module_mem_server_rid), + .debug_module_mem_server_rdata(proc$debug_module_mem_server_rdata), + .debug_module_mem_server_rresp(proc$debug_module_mem_server_rresp), + .debug_module_mem_server_rlast(proc$debug_module_mem_server_rlast), + .debug_module_mem_server_ruser(proc$debug_module_mem_server_ruser), + .debug_module_mem_server_rvalid(proc$debug_module_mem_server_rvalid), + .RDY_hart0_run_halt_server_request_put(proc$RDY_hart0_run_halt_server_request_put), + .hart0_run_halt_server_response_get(proc$hart0_run_halt_server_response_get), + .RDY_hart0_run_halt_server_response_get(proc$RDY_hart0_run_halt_server_response_get), + .RDY_hart0_gpr_mem_server_request_put(proc$RDY_hart0_gpr_mem_server_request_put), + .hart0_gpr_mem_server_response_get(proc$hart0_gpr_mem_server_response_get), + .RDY_hart0_gpr_mem_server_response_get(proc$RDY_hart0_gpr_mem_server_response_get), .RDY_hart0_fpr_mem_server_request_put(), .hart0_fpr_mem_server_response_get(), .RDY_hart0_fpr_mem_server_response_get(), - .RDY_hart0_csr_mem_server_request_put(), - .hart0_csr_mem_server_response_get(), - .RDY_hart0_csr_mem_server_response_get()); + .RDY_hart0_csr_mem_server_request_put(proc$RDY_hart0_csr_mem_server_request_put), + .hart0_csr_mem_server_response_get(proc$hart0_csr_mem_server_response_get), + .RDY_hart0_csr_mem_server_response_get(proc$RDY_hart0_csr_mem_server_response_get), + .RDY_hart0_put_other_req_put()); // submodule soc_map mkSoC_Map soc_map(.CLK(CLK), @@ -2522,36 +4022,17 @@ module mkCoreW(CLK, .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_flash_mem_addr_base(), - .m_flash_mem_addr_size(), - .m_flash_mem_addr_lim(), - .m_ethernet_0_addr_base(), - .m_ethernet_0_addr_size(), - .m_ethernet_0_addr_lim(), - .m_dma_0_addr_base(), - .m_dma_0_addr_size(), - .m_dma_0_addr_lim(), - .m_uart16550_0_addr_base(), - .m_uart16550_0_addr_size(), - .m_uart16550_0_addr_lim(), - .m_gpio_0_addr_base(), - .m_gpio_0_addr_size(), - .m_gpio_0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_ddr4_0_uncached_addr_base(), - .m_ddr4_0_uncached_addr_size(), - .m_ddr4_0_uncached_addr_lim(), - .m_ddr4_0_cached_addr_base(), - .m_ddr4_0_cached_addr_size(), - .m_ddr4_0_cached_addr_lim(), + .m_plic_addr_range(soc_map$m_plic_addr_range), + .m_near_mem_io_addr_range(), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), + .m_mem0_controller_addr_range(soc_map$m_mem0_controller_addr_range), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), @@ -2559,494 +4040,4104 @@ module mkCoreW(CLK, .m_mtvec_reset_value(), .m_nmivec_reset_value()); - // submodule tv_encode - mkTV_Encode tv_encode(.CLK(CLK), - .RST_N(RST_N), - .trace_data_in_put(tv_encode$trace_data_in_put), - .EN_reset(tv_encode$EN_reset), - .EN_trace_data_in_put(tv_encode$EN_trace_data_in_put), - .EN_tv_vb_out_get(tv_encode$EN_tv_vb_out_get), - .RDY_reset(), - .RDY_trace_data_in_put(tv_encode$RDY_trace_data_in_put), - .tv_vb_out_get(tv_encode$tv_vb_out_get), - .RDY_tv_vb_out_get(tv_encode$RDY_tv_vb_out_get)); + // submodule ssNoSynth_0_ar_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_0_ar_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_ar_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_ar_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_ar_buffer_ff$DEQ), + .CLR(ssNoSynth_0_ar_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_ar_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_ar_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_ar_buffer_ff$EMPTY_N)); - // rule RL_rl_once - assign CAN_FIRE_RL_rl_once = - proc$RDY_hart0_server_reset_request_put && !once && - !cpu_reset$ASSERT_OUT && - !cpu_halt$ASSERT_OUT ; - assign WILL_FIRE_RL_rl_once = CAN_FIRE_RL_rl_once ; + // submodule ssNoSynth_0_ar_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_ar_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_ar_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_ar_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_ar_buffer_firstValid$Q_OUT)); - // rule RL_rl_hart0_server_reset - assign CAN_FIRE_RL_rl_hart0_server_reset = - proc$RDY_start && proc$RDY_hart0_server_reset_response_get ; - assign WILL_FIRE_RL_rl_hart0_server_reset = - CAN_FIRE_RL_rl_hart0_server_reset ; + // submodule ssNoSynth_0_aw_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_0_aw_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_aw_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_aw_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_aw_buffer_ff$DEQ), + .CLR(ssNoSynth_0_aw_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_aw_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_aw_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_aw_buffer_ff$EMPTY_N)); - // rule RL_rl_hart0_server_run_halt - assign CAN_FIRE_RL_rl_hart0_server_run_halt = 1'd1 ; - assign WILL_FIRE_RL_rl_hart0_server_run_halt = 1'd1 ; + // submodule ssNoSynth_0_aw_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_aw_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_aw_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_aw_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_aw_buffer_firstValid$Q_OUT)); - // rule RL_rl_halt_reset - assign CAN_FIRE_RL_rl_halt_reset = hart0_halt ; - assign WILL_FIRE_RL_rl_halt_reset = hart0_halt ; + // submodule ssNoSynth_0_w_buffer_ff + FIFO1 #(.width(32'd74), + .guarded(32'd0)) ssNoSynth_0_w_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_w_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_w_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_w_buffer_ff$DEQ), + .CLR(ssNoSynth_0_w_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_w_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_w_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_w_buffer_ff$EMPTY_N)); - // rule RL_rl_halt - assign CAN_FIRE_RL_rl_halt = - debug_module$RDY_hart0_client_run_halt_response_put && + // submodule ssNoSynth_0_w_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_w_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_w_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_w_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_w_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_ar_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_1_ar_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_ar_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_ar_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_ar_buffer_ff$DEQ), + .CLR(ssNoSynth_1_ar_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_ar_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_ar_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_ar_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_ar_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_ar_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_ar_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_ar_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_ar_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_aw_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_1_aw_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_aw_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_aw_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_aw_buffer_ff$DEQ), + .CLR(ssNoSynth_1_aw_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_aw_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_aw_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_aw_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_aw_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_aw_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_aw_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_aw_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_aw_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_w_buffer_ff + FIFO1 #(.width(32'd74), + .guarded(32'd0)) ssNoSynth_1_w_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_w_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_w_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_w_buffer_ff$DEQ), + .CLR(ssNoSynth_1_w_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_w_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_w_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_w_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_w_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_w_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_w_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_w_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_w_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_ar_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_2_ar_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_ar_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_ar_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_ar_buffer_ff$DEQ), + .CLR(ssNoSynth_2_ar_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_ar_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_ar_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_ar_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_ar_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_ar_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_ar_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_ar_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_ar_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_aw_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_2_aw_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_aw_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_aw_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_aw_buffer_ff$DEQ), + .CLR(ssNoSynth_2_aw_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_aw_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_aw_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_aw_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_aw_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_aw_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_aw_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_aw_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_aw_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_w_buffer_ff + FIFO1 #(.width(32'd74), + .guarded(32'd0)) ssNoSynth_2_w_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_w_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_w_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_w_buffer_ff$DEQ), + .CLR(ssNoSynth_2_w_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_w_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_w_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_w_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_w_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_w_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_w_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_w_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_w_buffer_firstValid$Q_OUT)); + + // submodule tagController_tmp_awreqff + FIFO2 #(.width(32'd98), + .guarded(32'd1)) tagController_tmp_awreqff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tagController_tmp_awreqff$D_IN), + .ENQ(tagController_tmp_awreqff$ENQ), + .DEQ(tagController_tmp_awreqff$DEQ), + .CLR(tagController_tmp_awreqff$CLR), + .D_OUT(tagController_tmp_awreqff$D_OUT), + .FULL_N(tagController_tmp_awreqff$FULL_N), + .EMPTY_N(tagController_tmp_awreqff$EMPTY_N)); + + // submodule tagController_tmp_newRst + MakeReset0 #(.init(1'd0)) tagController_tmp_newRst(.CLK(CLK), + .RST(hart0_reset$RST_OUT), + .ASSERT_IN(tagController_tmp_newRst$ASSERT_IN), + .ASSERT_OUT(), + .OUT_RST(tagController_tmp_newRst$OUT_RST)); + + // submodule tagController_tmp_tagCon + mkTagController tagController_tmp_tagCon(.CLK(CLK), + .RST_N(tagController_tmp_newRst$OUT_RST), + .cache_request_put_val(tagController_tmp_tagCon$cache_request_put_val), + .memory_response_put_val(tagController_tmp_tagCon$memory_response_put_val), + .EN_cache_request_put(tagController_tmp_tagCon$EN_cache_request_put), + .EN_cache_response_get(tagController_tmp_tagCon$EN_cache_response_get), + .EN_memory_request_get(tagController_tmp_tagCon$EN_memory_request_get), + .EN_memory_response_put(tagController_tmp_tagCon$EN_memory_response_put), + .cache_request_canPut(), + .RDY_cache_request_put(tagController_tmp_tagCon$RDY_cache_request_put), + .cache_response_canGet(), + .cache_response_peek(), + .RDY_cache_response_peek(), + .cache_response_get(tagController_tmp_tagCon$cache_response_get), + .RDY_cache_response_get(tagController_tmp_tagCon$RDY_cache_response_get), + .memory_request_canGet(), + .memory_request_peek(), + .RDY_memory_request_peek(), + .memory_request_get(tagController_tmp_tagCon$memory_request_get), + .RDY_memory_request_get(tagController_tmp_tagCon$RDY_memory_request_get), + .memory_response_canPut(), + .RDY_memory_response_put(tagController_tmp_tagCon$RDY_memory_response_put)); + + // submodule tmp0_b_buffer_ff + FIFO1 #(.width(32'd6), + .guarded(32'd0)) tmp0_b_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp0_b_buffer_ff$D_IN), + .ENQ(tmp0_b_buffer_ff$ENQ), + .DEQ(tmp0_b_buffer_ff$DEQ), + .CLR(tmp0_b_buffer_ff$CLR), + .D_OUT(tmp0_b_buffer_ff$D_OUT), + .FULL_N(tmp0_b_buffer_ff$FULL_N), + .EMPTY_N(tmp0_b_buffer_ff$EMPTY_N)); + + // submodule tmp0_b_buffer_firstValid + RevertReg #(.width(32'd1), .init(1'd1)) tmp0_b_buffer_firstValid(.CLK(CLK), + .D_IN(tmp0_b_buffer_firstValid$D_IN), + .EN(tmp0_b_buffer_firstValid$EN), + .Q_OUT(tmp0_b_buffer_firstValid$Q_OUT)); + + // submodule tmp0_r_buffer_ff + FIFO1 #(.width(32'd72), + .guarded(32'd0)) tmp0_r_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp0_r_buffer_ff$D_IN), + .ENQ(tmp0_r_buffer_ff$ENQ), + .DEQ(tmp0_r_buffer_ff$DEQ), + .CLR(tmp0_r_buffer_ff$CLR), + .D_OUT(tmp0_r_buffer_ff$D_OUT), + .FULL_N(tmp0_r_buffer_ff$FULL_N), + .EMPTY_N(tmp0_r_buffer_ff$EMPTY_N)); + + // submodule tmp0_r_buffer_firstValid + RevertReg #(.width(32'd1), .init(1'd1)) tmp0_r_buffer_firstValid(.CLK(CLK), + .D_IN(tmp0_r_buffer_firstValid$D_IN), + .EN(tmp0_r_buffer_firstValid$EN), + .Q_OUT(tmp0_r_buffer_firstValid$Q_OUT)); + + // submodule tmp2_b_buffer_ff + FIFO1 #(.width(32'd7), + .guarded(32'd0)) tmp2_b_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_b_buffer_ff$D_IN), + .ENQ(tmp2_b_buffer_ff$ENQ), + .DEQ(tmp2_b_buffer_ff$DEQ), + .CLR(tmp2_b_buffer_ff$CLR), + .D_OUT(tmp2_b_buffer_ff$D_OUT), + .FULL_N(tmp2_b_buffer_ff$FULL_N), + .EMPTY_N(tmp2_b_buffer_ff$EMPTY_N)); + + // submodule tmp2_b_buffer_firstValid + RevertReg #(.width(32'd1), .init(1'd1)) tmp2_b_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_b_buffer_firstValid$D_IN), + .EN(tmp2_b_buffer_firstValid$EN), + .Q_OUT(tmp2_b_buffer_firstValid$Q_OUT)); + + // submodule tmp2_r_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) tmp2_r_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_r_buffer_ff$D_IN), + .ENQ(tmp2_r_buffer_ff$ENQ), + .DEQ(tmp2_r_buffer_ff$DEQ), + .CLR(tmp2_r_buffer_ff$CLR), + .D_OUT(tmp2_r_buffer_ff$D_OUT), + .FULL_N(tmp2_r_buffer_ff$FULL_N), + .EMPTY_N(tmp2_r_buffer_ff$EMPTY_N)); + + // submodule tmp2_r_buffer_firstValid + RevertReg #(.width(32'd1), .init(1'd1)) tmp2_r_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_r_buffer_firstValid$D_IN), + .EN(tmp2_r_buffer_firstValid$EN), + .Q_OUT(tmp2_r_buffer_firstValid$Q_OUT)); + + // submodule uncached_mem_shim_arff + FIFO2 #(.width(32'd98), + .guarded(32'd1)) uncached_mem_shim_arff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(uncached_mem_shim_arff$D_IN), + .ENQ(uncached_mem_shim_arff$ENQ), + .DEQ(uncached_mem_shim_arff$DEQ), + .CLR(uncached_mem_shim_arff$CLR), + .D_OUT(uncached_mem_shim_arff$D_OUT), + .FULL_N(uncached_mem_shim_arff$FULL_N), + .EMPTY_N(uncached_mem_shim_arff$EMPTY_N)); + + // submodule uncached_mem_shim_awff + FIFO2 #(.width(32'd98), + .guarded(32'd1)) uncached_mem_shim_awff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(uncached_mem_shim_awff$D_IN), + .ENQ(uncached_mem_shim_awff$ENQ), + .DEQ(uncached_mem_shim_awff$DEQ), + .CLR(uncached_mem_shim_awff$CLR), + .D_OUT(uncached_mem_shim_awff$D_OUT), + .FULL_N(uncached_mem_shim_awff$FULL_N), + .EMPTY_N(uncached_mem_shim_awff$EMPTY_N)); + + // submodule uncached_mem_shim_bff + FIFO2 #(.width(32'd7), + .guarded(32'd1)) uncached_mem_shim_bff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(uncached_mem_shim_bff$D_IN), + .ENQ(uncached_mem_shim_bff$ENQ), + .DEQ(uncached_mem_shim_bff$DEQ), + .CLR(uncached_mem_shim_bff$CLR), + .D_OUT(uncached_mem_shim_bff$D_OUT), + .FULL_N(uncached_mem_shim_bff$FULL_N), + .EMPTY_N(uncached_mem_shim_bff$EMPTY_N)); + + // submodule uncached_mem_shim_rff + FIFO2 #(.width(32'd73), + .guarded(32'd1)) uncached_mem_shim_rff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(uncached_mem_shim_rff$D_IN), + .ENQ(uncached_mem_shim_rff$ENQ), + .DEQ(uncached_mem_shim_rff$DEQ), + .CLR(uncached_mem_shim_rff$CLR), + .D_OUT(uncached_mem_shim_rff$D_OUT), + .FULL_N(uncached_mem_shim_rff$FULL_N), + .EMPTY_N(uncached_mem_shim_rff$EMPTY_N)); + + // submodule uncached_mem_shim_wff + FIFO2 #(.width(32'd74), + .guarded(32'd1)) uncached_mem_shim_wff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(uncached_mem_shim_wff$D_IN), + .ENQ(uncached_mem_shim_wff$ENQ), + .DEQ(uncached_mem_shim_wff$DEQ), + .CLR(uncached_mem_shim_wff$CLR), + .D_OUT(uncached_mem_shim_wff$D_OUT), + .FULL_N(uncached_mem_shim_wff$FULL_N), + .EMPTY_N(uncached_mem_shim_wff$EMPTY_N)); + + // rule RL_rl_dm_hart0_reset + assign CAN_FIRE_RL_rl_dm_hart0_reset = + debug_module$RDY_hart0_reset_client_request_get && + rg_hart0_reset_delay == 8'd0 ; + assign WILL_FIRE_RL_rl_dm_hart0_reset = CAN_FIRE_RL_rl_dm_hart0_reset ; + + // rule RL_rl_dm_hart0_reset_wait + assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = + (rg_hart0_reset_delay != 8'd1 || + proc$RDY_start && + debug_module$RDY_hart0_reset_client_response_put) && + rg_hart0_reset_delay != 8'd0 ; + assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = + CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; + + // rule RL_ClientServerRequest + assign CAN_FIRE_RL_ClientServerRequest = + proc$RDY_hart0_run_halt_server_request_put && debug_module$RDY_hart0_client_run_halt_request_get ; - assign WILL_FIRE_RL_rl_halt = CAN_FIRE_RL_rl_halt ; + assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; - // rule RL_rl_gpr - assign CAN_FIRE_RL_rl_gpr = - debug_module$RDY_hart0_gpr_mem_client_response_put && - debug_module$RDY_hart0_gpr_mem_client_request_get ; - assign WILL_FIRE_RL_rl_gpr = CAN_FIRE_RL_rl_gpr ; - - // rule RL_rl_fpr - assign CAN_FIRE_RL_rl_fpr = - debug_module$RDY_hart0_fpr_mem_client_response_put && - debug_module$RDY_hart0_fpr_mem_client_request_get ; - assign WILL_FIRE_RL_rl_fpr = CAN_FIRE_RL_rl_fpr ; - - // rule RL_rl_csr - assign CAN_FIRE_RL_rl_csr = - debug_module$RDY_hart0_csr_mem_client_response_put && - debug_module$RDY_hart0_csr_mem_client_request_get ; - assign WILL_FIRE_RL_rl_csr = CAN_FIRE_RL_rl_csr ; - - // rule RL_rl_cpu_hart0_reset_from_dm_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_complete = - f_reset_requestor$EMPTY_N && !f_reset_requestor$D_OUT && - !cpu_reset$ASSERT_OUT ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_complete ; + // rule RL_ClientServerResponse + assign CAN_FIRE_RL_ClientServerResponse = + proc$RDY_hart0_run_halt_server_response_get && + debug_module$RDY_hart0_client_run_halt_response_put ; + assign WILL_FIRE_RL_ClientServerResponse = + CAN_FIRE_RL_ClientServerResponse ; // rule RL_mkConnectionGetPut assign CAN_FIRE_RL_mkConnectionGetPut = - tv_encode$RDY_trace_data_in_put && f_trace_data_merged$EMPTY_N ; - assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ; + debug_module$RDY_hart0_get_other_req_get ; + assign WILL_FIRE_RL_mkConnectionGetPut = + debug_module$RDY_hart0_get_other_req_get ; - // rule RL_merge_cpu_trace_data - assign CAN_FIRE_RL_merge_cpu_trace_data = - proc$RDY_trace_data_out_get && f_trace_data_merged$FULL_N ; - assign WILL_FIRE_RL_merge_cpu_trace_data = - CAN_FIRE_RL_merge_cpu_trace_data ; + // rule RL_ClientServerResponse_1 + assign CAN_FIRE_RL_ClientServerResponse_1 = + proc$RDY_hart0_gpr_mem_server_response_get && + debug_module$RDY_hart0_gpr_mem_client_response_put ; + assign WILL_FIRE_RL_ClientServerResponse_1 = + CAN_FIRE_RL_ClientServerResponse_1 ; - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; + // rule RL_ClientServerResponse_2 + assign CAN_FIRE_RL_ClientServerResponse_2 = + proc$RDY_hart0_csr_mem_server_response_get && + debug_module$RDY_hart0_csr_mem_client_response_put ; + assign WILL_FIRE_RL_ClientServerResponse_2 = + CAN_FIRE_RL_ClientServerResponse_2 ; - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; + // rule RL_checkSinkReady + assign CAN_FIRE_RL_checkSinkReady = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady = 1'd1 ; - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; + // rule RL_checkSinkReady_1 + assign CAN_FIRE_RL_checkSinkReady_1 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_1 = 1'd1 ; - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; + // rule RL_checkSinkReady_2 + assign CAN_FIRE_RL_checkSinkReady_2 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_2 = 1'd1 ; - // rule RL_merge_dm_mem_trace_data - assign CAN_FIRE_RL_merge_dm_mem_trace_data = - dm_mem_tap$RDY_trace_data_out_get && f_trace_data_merged$FULL_N ; - assign WILL_FIRE_RL_merge_dm_mem_trace_data = - CAN_FIRE_RL_merge_dm_mem_trace_data && - !WILL_FIRE_RL_merge_cpu_trace_data ; + // rule RL_craftReq + assign CAN_FIRE_RL_craftReq = + ifcs_0_innerRoute$EMPTY_N && ifcs_0_innerReq$EMPTY_N ; + assign WILL_FIRE_RL_craftReq = CAN_FIRE_RL_craftReq ; - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; + // rule RL_craftReq_1 + assign CAN_FIRE_RL_craftReq_1 = + ifcs_1_innerRoute$EMPTY_N && ifcs_1_innerReq$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_1 = CAN_FIRE_RL_craftReq_1 ; - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; + // rule RL_arbitrate + assign CAN_FIRE_RL_arbitrate = + (CAN_FIRE_RL_craftReq && reqWires_0$wget || + CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) && + !state ; + assign WILL_FIRE_RL_arbitrate = CAN_FIRE_RL_arbitrate ; - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; + // rule RL_source_selected + assign CAN_FIRE_RL_source_selected = + (!ifcs_0_innerRoute$EMPTY_N || ifcs_0_innerReq$EMPTY_N) && + !state && + MUX_activeSource_0$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected = CAN_FIRE_RL_source_selected ; - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; + // rule RL_burst + assign CAN_FIRE_RL_burst = + ifcs_0_innerReq$EMPTY_N && ifcs_0_innerRoute$EMPTY_N && + state_490_AND_activeSource_0_563_564_AND_ifcs__ETC___d1566 ; + assign WILL_FIRE_RL_burst = CAN_FIRE_RL_burst ; - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; + // rule RL_source_selected_1 + assign CAN_FIRE_RL_source_selected_1 = + (!ifcs_1_innerRoute$EMPTY_N || ifcs_1_innerReq$EMPTY_N) && + !state && + MUX_activeSource_1$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_1 = CAN_FIRE_RL_source_selected_1 ; - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; + // rule RL_burst_1 + assign CAN_FIRE_RL_burst_1 = + ifcs_1_innerReq$EMPTY_N && ifcs_1_innerRoute$EMPTY_N && + state_490_AND_activeSource_1_607_608_AND_ifcs__ETC___d1610 ; + assign WILL_FIRE_RL_burst_1 = CAN_FIRE_RL_burst_1 ; - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; + // rule __me_check_182 + assign CAN_FIRE___me_check_182 = 1'b1 ; + assign WILL_FIRE___me_check_182 = 1'b1 ; - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; + // rule __me_check_184 + assign CAN_FIRE___me_check_184 = 1'b1 ; + assign WILL_FIRE___me_check_184 = 1'b1 ; - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; + // rule RL_sink_selected + assign CAN_FIRE_RL_sink_selected = + IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1435 && + flitToSink_0$whas ; + assign WILL_FIRE_RL_sink_selected = CAN_FIRE_RL_sink_selected ; - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; + // rule RL_sink_selected_1 + assign CAN_FIRE_RL_sink_selected_1 = + IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1436 && + flitToSink_1$whas ; + assign WILL_FIRE_RL_sink_selected_1 = CAN_FIRE_RL_sink_selected_1 ; - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; + // rule RL_sink_selected_2 + assign CAN_FIRE_RL_sink_selected_2 = + IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1437 && + flitToSink_2$whas ; + assign WILL_FIRE_RL_sink_selected_2 = CAN_FIRE_RL_sink_selected_2 ; - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; + // rule __me_check_186 + assign CAN_FIRE___me_check_186 = 1'b1 ; + assign WILL_FIRE___me_check_186 = 1'b1 ; - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; + // rule RL_checkSinkReady_5 + assign CAN_FIRE_RL_checkSinkReady_5 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_5 = 1'd1 ; - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; + // rule RL_checkSinkReady_6 + assign CAN_FIRE_RL_checkSinkReady_6 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_6 = 1'd1 ; - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; + // rule RL_checkSinkReady_7 + assign CAN_FIRE_RL_checkSinkReady_7 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_7 = 1'd1 ; - // rule RL_rl_wr_addr_channel_4 - assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; + // rule RL_craftReq_5 + assign CAN_FIRE_RL_craftReq_5 = + ifcs_0_1_innerRoute$EMPTY_N && ifcs_0_1_innerReq$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_5 = CAN_FIRE_RL_craftReq_5 ; - // rule RL_rl_wr_data_channel_4 - assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; + // rule RL_craftReq_6 + assign CAN_FIRE_RL_craftReq_6 = + ifcs_1_1_innerRoute$EMPTY_N && ifcs_1_1_innerReq$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_6 = CAN_FIRE_RL_craftReq_6 ; - // rule RL_rl_wr_response_channel_4 - assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; + // rule RL_arbitrate_2 + assign CAN_FIRE_RL_arbitrate_2 = + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget || + CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) && + !state_1_1 ; + assign WILL_FIRE_RL_arbitrate_2 = CAN_FIRE_RL_arbitrate_2 ; - // rule RL_rl_rd_addr_channel_4 - assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; + // rule RL_source_selected_5 + assign CAN_FIRE_RL_source_selected_5 = + (!ifcs_0_1_innerRoute$EMPTY_N || ifcs_0_1_innerReq$EMPTY_N) && + !state_1_1 && + sourceSelect_1_0_1$whas ; + assign WILL_FIRE_RL_source_selected_5 = CAN_FIRE_RL_source_selected_5 ; - // rule RL_rl_rd_data_channel_4 - assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; + // rule RL_burst_5 + assign CAN_FIRE_RL_burst_5 = + ifcs_0_1_innerReq$EMPTY_N && ifcs_0_1_innerRoute$EMPTY_N && + state_1_1_143_AND_activeSource_1_0_1_210_211_A_ETC___d2213 ; + assign WILL_FIRE_RL_burst_5 = CAN_FIRE_RL_burst_5 ; + + // rule RL_source_selected_6 + assign CAN_FIRE_RL_source_selected_6 = + (!ifcs_1_1_innerRoute$EMPTY_N || ifcs_1_1_innerReq$EMPTY_N) && + !state_1_1 && + sourceSelect_1_1_1$whas ; + assign WILL_FIRE_RL_source_selected_6 = CAN_FIRE_RL_source_selected_6 ; + + // rule RL_burst_6 + assign CAN_FIRE_RL_burst_6 = + ifcs_1_1_innerReq$EMPTY_N && ifcs_1_1_innerRoute$EMPTY_N && + state_1_1_143_AND_activeSource_1_1_1_250_251_A_ETC___d2253 ; + assign WILL_FIRE_RL_burst_6 = CAN_FIRE_RL_burst_6 ; + + // rule __me_check_229 + assign CAN_FIRE___me_check_229 = 1'b1 ; + assign WILL_FIRE___me_check_229 = 1'b1 ; + + // rule __me_check_231 + assign CAN_FIRE___me_check_231 = 1'b1 ; + assign WILL_FIRE___me_check_231 = 1'b1 ; + + // rule RL_sink_selected_5 + assign CAN_FIRE_RL_sink_selected_5 = + ssNoSynth_0_ar_buffer_ff$FULL_N && flitToSink_1_0_1$whas ; + assign WILL_FIRE_RL_sink_selected_5 = CAN_FIRE_RL_sink_selected_5 ; + + // rule RL_sink_selected_6 + assign CAN_FIRE_RL_sink_selected_6 = + ssNoSynth_1_ar_buffer_ff$FULL_N && flitToSink_1_1_1$whas ; + assign WILL_FIRE_RL_sink_selected_6 = CAN_FIRE_RL_sink_selected_6 ; + + // rule RL_sink_selected_7 + assign CAN_FIRE_RL_sink_selected_7 = + ssNoSynth_2_ar_buffer_ff$FULL_N && flitToSink_1_2$whas ; + assign WILL_FIRE_RL_sink_selected_7 = CAN_FIRE_RL_sink_selected_7 ; + + // rule __me_check_233 + assign CAN_FIRE___me_check_233 = 1'b1 ; + assign WILL_FIRE___me_check_233 = 1'b1 ; // rule RL_rl_relay_external_interrupts assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - // rule RL_rl_cpu_hart0_reset_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - plic$RDY_server_reset_response_get && f_reset_rsps$FULL_N && - !cpu_reset$ASSERT_OUT ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + // rule RL_ug_uncached_mem_shim_master_u_aw_setPeek + assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek = + uncached_mem_shim_awff$EMPTY_N ; + assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek = + uncached_mem_shim_awff$EMPTY_N ; - // rule RL_rl_cpu_hart0_reset_from_soc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; + // rule RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop = + ug_uncached_mem_shim_master_u_aw_dropWire$whas && + !uncached_mem_shim_awff$EMPTY_N ; + assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop ; - // rule RL_rl_cpu_hart0_reset_from_dm_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = - debug_module$RDY_hart0_get_reset_req_get && - f_reset_requestor$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start && - !WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; + // rule RL_ug_uncached_mem_shim_master_u_w_setPeek + assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek = + uncached_mem_shim_wff$EMPTY_N ; + assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek = + uncached_mem_shim_wff$EMPTY_N ; - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; + // rule RL_ug_uncached_mem_shim_master_u_w_warnDoDrop + assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop = + ug_uncached_mem_shim_master_u_w_dropWire$whas && + !uncached_mem_shim_wff$EMPTY_N ; + assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop ; - // rule RL_rl_relay_non_maskable_interrupt - assign CAN_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; - assign WILL_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; + // rule RL_ug_uncached_mem_shim_master_u_b_warnDoPut + assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut = + ug_uncached_mem_shim_master_u_b_putWire$whas && + !uncached_mem_shim_bff$FULL_N ; + assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut ; - // register hart0_halt - assign hart0_halt$D_IN = !debug_module$hart0_client_run_halt_request_get ; - assign hart0_halt$EN = CAN_FIRE_RL_rl_halt ; + // rule RL_ug_uncached_mem_shim_master_u_ar_setPeek + assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek = + uncached_mem_shim_arff$EMPTY_N ; + assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek = + uncached_mem_shim_arff$EMPTY_N ; - // register once - assign once$D_IN = 1'd1 ; - assign once$EN = CAN_FIRE_RL_rl_once ; + // rule RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop = + ug_uncached_mem_shim_master_u_ar_dropWire$whas && + !uncached_mem_shim_arff$EMPTY_N ; + assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop ; + + // rule RL_ug_uncached_mem_shim_master_u_r_warnDoPut + assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut = + ug_uncached_mem_shim_master_u_r_putWire$whas && + !uncached_mem_shim_rff$FULL_N ; + assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut ; + + // rule RL_tagController_tmp_passCacheResponse + assign CAN_FIRE_RL_tagController_tmp_passCacheResponse = + tagController_tmp_tagCon$RDY_cache_response_get && + !tagController_tmp_shimSlave_bff_rv[7] && + !tagController_tmp_shimSlave_rff_rv[73] ; + assign WILL_FIRE_RL_tagController_tmp_passCacheResponse = + CAN_FIRE_RL_tagController_tmp_passCacheResponse ; + + // rule RL_tagController_tmp_passMemoryRequest + assign CAN_FIRE_RL_tagController_tmp_passMemoryRequest = + tagController_tmp_tagCon$RDY_memory_request_get && + !tagController_tmp_shimMaster_wff_rv[73] && + (tagController_tmp_doneSendingAW || + !tagController_tmp_shimMaster_awff_rv[99]) && + !tagController_tmp_shimMaster_arff_rv[99] ; + assign WILL_FIRE_RL_tagController_tmp_passMemoryRequest = + CAN_FIRE_RL_tagController_tmp_passMemoryRequest ; + + // rule RL_tagController_tmp_ug_slave_u_b_setPeek + assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_setPeek = + tagController_tmp_shimSlave_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_setPeek = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_setPeek ; + + // rule RL_tagController_tmp_ug_slave_u_r_setPeek + assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_setPeek = + tagController_tmp_shimSlave_rff_rv$port1__read[73] ; + assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_setPeek = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_setPeek ; + + // rule RL_tagController_tmp_ug_master_u_aw_setPeek + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek = + tagController_tmp_shimMaster_awff_rv$port1__read[99] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek = + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek ; + + // rule RL_tagController_tmp_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = + tagController_tmp_ug_master_u_aw_dropWire$whas && + !tagController_tmp_shimMaster_awff_rv$port1__read[99] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop ; + + // rule RL_tagController_tmp_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = + tagController_tmp_shimMaster_awff_rv$port1__read[99] && + tagController_tmp_ug_master_u_aw_dropWire$whas ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop ; + + // rule RL_tagController_tmp_ug_master_u_w_setPeek + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek = + tagController_tmp_shimMaster_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek = + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek ; + + // rule RL_tagController_tmp_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = + tagController_tmp_ug_master_u_w_dropWire$whas && + !tagController_tmp_shimMaster_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop ; + + // rule RL_tagController_tmp_ug_master_u_w_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = + tagController_tmp_shimMaster_wff_rv$port1__read[73] && + tagController_tmp_ug_master_u_w_dropWire$whas ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop ; + + // rule RL_tagController_tmp_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = + tagController_tmp_ug_master_u_b_putWire$whas && + tagController_tmp_shimMaster_bff_rv[8] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut ; + + // rule RL_tagController_tmp_ug_master_u_b_doPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = + !tagController_tmp_shimMaster_bff_rv[8] && + tagController_tmp_ug_master_u_b_putWire$whas ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut ; + + // rule RL_tagController_tmp_ug_master_u_ar_setPeek + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek = + tagController_tmp_shimMaster_arff_rv$port1__read[99] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek = + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek ; + + // rule RL_tagController_tmp_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = + tagController_tmp_ug_master_u_ar_dropWire$whas && + !tagController_tmp_shimMaster_arff_rv$port1__read[99] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop ; + + // rule RL_tagController_tmp_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = + tagController_tmp_shimMaster_arff_rv$port1__read[99] && + tagController_tmp_ug_master_u_ar_dropWire$whas ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop ; + + // rule RL_tagController_tmp_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = + tagController_tmp_ug_master_u_r_putWire$whas && + tagController_tmp_shimMaster_rff_rv[73] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut ; + + // rule RL_tagController_tmp_ug_master_u_r_doPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = + !tagController_tmp_shimMaster_rff_rv[73] && + tagController_tmp_ug_master_u_r_putWire$whas ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut ; + + // rule RL_tagController_tmp_passMemoryResponseWrite + assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite = + tagController_tmp_shimMaster_bff_rv$port1__read[8] && + tagController_tmp_tagCon$RDY_memory_response_put ; + assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite = + CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite && + !WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + + // rule RL_tagController_tmp_passMemoryResponseRead + assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead = + tagController_tmp_shimMaster_rff_rv$port1__read[73] && + tagController_tmp_tagCon$RDY_memory_response_put ; + assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead = + CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + + // rule RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut = + !tagController_tmp_shimSlave_awff_rv[98] && + proc$master0_awvalid ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut ; + + // rule RL_tagController_tmp_ug_slave_u_aw_warnDoPut + assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut && + tagController_tmp_shimSlave_awff_rv[98] ; + assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut ; + + // rule RL_tagController_tmp_ug_slave_u_aw_doPut + assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut = + !tagController_tmp_shimSlave_awff_rv[98] && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut ; + assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut ; + + // rule RL_tagController_tmp_getCacheAW + assign CAN_FIRE_RL_tagController_tmp_getCacheAW = + tagController_tmp_shimSlave_awff_rv$port1__read[98] && + tagController_tmp_awreqff$FULL_N ; + assign WILL_FIRE_RL_tagController_tmp_getCacheAW = + CAN_FIRE_RL_tagController_tmp_getCacheAW ; + + // rule RL_tmp2_aw_forwardReady + assign CAN_FIRE_RL_tmp2_aw_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp2_aw_forwardReady = 1'd1 ; + + // rule RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut = + !tagController_tmp_shimSlave_wff_rv[74] && proc$master0_wvalid ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut ; + + // rule RL_tagController_tmp_ug_slave_u_w_warnDoPut + assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut && + tagController_tmp_shimSlave_wff_rv[74] ; + assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut ; + + // rule RL_tagController_tmp_ug_slave_u_w_doPut + assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut = + !tagController_tmp_shimSlave_wff_rv[74] && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut ; + assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut ; + + // rule RL_tmp2_w_forwardReady + assign CAN_FIRE_RL_tmp2_w_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp2_w_forwardReady = 1'd1 ; + + // rule RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut = + tagController_tmp_shimSlave_bff_rv$port1__read[7] && + tmp2_b_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut ; + + // rule RL_tagController_tmp_ug_slave_u_b_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut && + !tagController_tmp_shimSlave_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop ; + + // rule RL_tagController_tmp_ug_slave_u_b_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop = + tagController_tmp_shimSlave_bff_rv$port1__read[7] && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut ; + assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop ; + + // rule RL_tmp2_b_forwardFlit + assign CAN_FIRE_RL_tmp2_b_forwardFlit = + tmp2_b_buffer_firstValid$Q_OUT && + (tmp2_b_buffer_ff$EMPTY_N || + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut) ; + assign WILL_FIRE_RL_tmp2_b_forwardFlit = CAN_FIRE_RL_tmp2_b_forwardFlit ; + + // rule RL_tmp2_b_dropFlit + assign CAN_FIRE_RL_tmp2_b_dropFlit = + (tmp2_b_buffer_ff$EMPTY_N || + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut) && + proc$master0_bready ; + assign WILL_FIRE_RL_tmp2_b_dropFlit = CAN_FIRE_RL_tmp2_b_dropFlit ; + + // rule RL_tmp2_b_buffer_enqueue + assign CAN_FIRE_RL_tmp2_b_buffer_enqueue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut && + (!CAN_FIRE_RL_tmp2_b_dropFlit || tmp2_b_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_b_buffer_enqueue = + CAN_FIRE_RL_tmp2_b_buffer_enqueue ; + + // rule RL_tmp2_b_buffer_dequeue + assign CAN_FIRE_RL_tmp2_b_buffer_dequeue = + CAN_FIRE_RL_tmp2_b_dropFlit && tmp2_b_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_b_buffer_dequeue = + CAN_FIRE_RL_tmp2_b_buffer_dequeue ; + + // rule RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut = + !tagController_tmp_shimSlave_arff_rv[98] && + proc$master0_arvalid ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut ; + + // rule RL_tagController_tmp_ug_slave_u_ar_warnDoPut + assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut && + tagController_tmp_shimSlave_arff_rv[98] ; + assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut ; + + // rule RL_tagController_tmp_ug_slave_u_ar_doPut + assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut = + !tagController_tmp_shimSlave_arff_rv[98] && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut ; + assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut ; + + // rule RL_tagController_tmp_passCacheWrite + assign CAN_FIRE_RL_tagController_tmp_passCacheWrite = + tagController_tmp_shimSlave_wff_rv$port1__read[74] && + tagController_tmp_tagCon$RDY_cache_request_put && + tagController_tmp_awreqff$EMPTY_N ; + assign WILL_FIRE_RL_tagController_tmp_passCacheWrite = + CAN_FIRE_RL_tagController_tmp_passCacheWrite && + !WILL_FIRE_RL_tagController_tmp_passCacheRead ; + + // rule RL_tagController_tmp_passCacheRead + assign CAN_FIRE_RL_tagController_tmp_passCacheRead = + tagController_tmp_shimSlave_arff_rv$port1__read[98] && + tagController_tmp_tagCon$RDY_cache_request_put ; + assign WILL_FIRE_RL_tagController_tmp_passCacheRead = + CAN_FIRE_RL_tagController_tmp_passCacheRead ; + + // rule RL_tmp2_ar_forwardReady + assign CAN_FIRE_RL_tmp2_ar_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp2_ar_forwardReady = 1'd1 ; + + // rule RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut = + tagController_tmp_shimSlave_rff_rv$port1__read[73] && + tmp2_r_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut ; + + // rule RL_tagController_tmp_ug_slave_u_r_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut && + !tagController_tmp_shimSlave_rff_rv$port1__read[73] ; + assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop ; + + // rule RL_tagController_tmp_ug_slave_u_r_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop = + tagController_tmp_shimSlave_rff_rv$port1__read[73] && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut ; + assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop ; + + // rule RL_tagController_tmp_propagateReset + assign CAN_FIRE_RL_tagController_tmp_propagateReset = + !tagController_tmp_reset_done ; + assign WILL_FIRE_RL_tagController_tmp_propagateReset = + CAN_FIRE_RL_tagController_tmp_propagateReset ; + + // rule RL_tmp2_r_forwardFlit + assign CAN_FIRE_RL_tmp2_r_forwardFlit = + tmp2_r_buffer_firstValid$Q_OUT && + (tmp2_r_buffer_ff$EMPTY_N || + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut) ; + assign WILL_FIRE_RL_tmp2_r_forwardFlit = CAN_FIRE_RL_tmp2_r_forwardFlit ; + + // rule RL_tmp2_r_dropFlit + assign CAN_FIRE_RL_tmp2_r_dropFlit = + (tmp2_r_buffer_ff$EMPTY_N || + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut) && + proc$master0_rready ; + assign WILL_FIRE_RL_tmp2_r_dropFlit = CAN_FIRE_RL_tmp2_r_dropFlit ; + + // rule RL_tmp2_r_buffer_enqueue + assign CAN_FIRE_RL_tmp2_r_buffer_enqueue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut && + (!CAN_FIRE_RL_tmp2_r_dropFlit || tmp2_r_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_r_buffer_enqueue = + CAN_FIRE_RL_tmp2_r_buffer_enqueue ; + + // rule RL_tmp2_r_buffer_dequeue + assign CAN_FIRE_RL_tmp2_r_buffer_dequeue = + CAN_FIRE_RL_tmp2_r_dropFlit && tmp2_r_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_r_buffer_dequeue = + CAN_FIRE_RL_tmp2_r_buffer_dequeue ; + + // rule RL_ssNoSynth_0_ar_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit = + !uncached_mem_shim_arff$FULL_N || + ssNoSynth_0_ar_buffer_firstValid$Q_OUT && + (ssNoSynth_0_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_5) && + uncached_mem_shim_arff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit && + !WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop ; + + // rule RL_ssNoSynth_0_ar_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit = + (ssNoSynth_0_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_5) && + uncached_mem_shim_arff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit && + !WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit ; + + // rule RL_ug_uncached_mem_shim_master_u_ar_doDrop + assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop = + uncached_mem_shim_arff$EMPTY_N && + ug_uncached_mem_shim_master_u_ar_dropWire$whas ; + assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop ; + + // rule RL_ssNoSynth_0_ar_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue = + CAN_FIRE_RL_sink_selected_5 && + (!WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit || + ssNoSynth_0_ar_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue ; + + // rule RL_ssNoSynth_0_ar_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue = + WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit && + ssNoSynth_0_ar_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue ; + + // rule RL_ssNoSynth_1_ar_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit = + ssNoSynth_1_ar_buffer_firstValid$Q_OUT && + (ssNoSynth_1_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_6) ; + assign WILL_FIRE_RL_ssNoSynth_1_ar_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit ; + + // rule RL_ssNoSynth_1_ar_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit = + (ssNoSynth_1_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_6) && + plic$axi4_slave_arready ; + assign WILL_FIRE_RL_ssNoSynth_1_ar_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit ; + + // rule RL_ssNoSynth_1_ar_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue = + CAN_FIRE_RL_sink_selected_6 && + (!CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit || + ssNoSynth_1_ar_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue ; + + // rule RL_ssNoSynth_1_ar_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit && + ssNoSynth_1_ar_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue ; + + // rule RL_ssNoSynth_2_ar_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit = + ssNoSynth_2_ar_buffer_firstValid$Q_OUT && + (ssNoSynth_2_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_7) ; + assign WILL_FIRE_RL_ssNoSynth_2_ar_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit ; + + // rule RL_ssNoSynth_2_ar_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit = + (ssNoSynth_2_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_7) && + proc$debug_module_mem_server_arready ; + assign WILL_FIRE_RL_ssNoSynth_2_ar_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit ; + + // rule RL_ssNoSynth_2_ar_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue = + CAN_FIRE_RL_sink_selected_7 && + (!CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit || + ssNoSynth_2_ar_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue ; + + // rule RL_ssNoSynth_2_ar_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit && + ssNoSynth_2_ar_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue ; + + // rule RL_split_0_putFirst + assign CAN_FIRE_RL_split_0_putFirst = + split_0_doPut_whas__086_AND_split_0_doPut_wget_ETC___d1093 && + split_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_0_putFirst = CAN_FIRE_RL_split_0_putFirst ; + + // rule RL_ssNoSynth_0_aw_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit = + !uncached_mem_shim_awff$FULL_N || + ssNoSynth_0_aw_buffer_firstValid$Q_OUT && + (ssNoSynth_0_aw_buffer_ff$EMPTY_N || + MUX_split_0_flitLeft$write_1__SEL_2) && + uncached_mem_shim_awff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit && + !WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop ; + + // rule RL_ssNoSynth_0_aw_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit = + (ssNoSynth_0_aw_buffer_ff$EMPTY_N || + MUX_split_0_flitLeft$write_1__SEL_2) && + uncached_mem_shim_awff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit && + !WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit ; + + // rule RL_ug_uncached_mem_shim_master_u_aw_doDrop + assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop = + uncached_mem_shim_awff$EMPTY_N && + ug_uncached_mem_shim_master_u_aw_dropWire$whas ; + assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop ; + + // rule RL_ssNoSynth_0_aw_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue = + MUX_split_0_flitLeft$write_1__SEL_2 && + (!WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit || + ssNoSynth_0_aw_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue ; + + // rule RL_ssNoSynth_0_aw_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue = + WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit && + ssNoSynth_0_aw_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue ; + + // rule RL_split_0_putOther + assign CAN_FIRE_RL_split_0_putOther = + CAN_FIRE_RL_sink_selected && + (!split_0_doPut$wget[172] || ssNoSynth_0_w_buffer_ff$FULL_N) && + split_0_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_0_putOther = CAN_FIRE_RL_split_0_putOther ; + + // rule RL_ssNoSynth_0_w_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit = + !uncached_mem_shim_wff$FULL_N || + ssNoSynth_0_w_buffer_firstValid$Q_OUT && + (ssNoSynth_0_w_buffer_ff$EMPTY_N || + ssNoSynth_0_w_buffer_enqw$whas) && + uncached_mem_shim_wff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit && + !WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop ; + + // rule RL_ssNoSynth_0_w_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_w_dropFlit = + (ssNoSynth_0_w_buffer_ff$EMPTY_N || + ssNoSynth_0_w_buffer_enqw$whas) && + uncached_mem_shim_wff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_w_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_w_dropFlit && + !WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit ; + + // rule RL_ug_uncached_mem_shim_master_u_w_doDrop + assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop = + uncached_mem_shim_wff$EMPTY_N && + ug_uncached_mem_shim_master_u_w_dropWire$whas ; + assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop ; + + // rule RL_ssNoSynth_0_w_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue = + ssNoSynth_0_w_buffer_enqw$whas && + (!WILL_FIRE_RL_ssNoSynth_0_w_dropFlit || + ssNoSynth_0_w_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_w_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue ; + + // rule RL_ssNoSynth_0_w_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue = + WILL_FIRE_RL_ssNoSynth_0_w_dropFlit && + ssNoSynth_0_w_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue ; + + // rule RL_split_1_putFirst + assign CAN_FIRE_RL_split_1_putFirst = + split_1_doPut_whas__115_AND_split_1_doPut_wget_ETC___d1122 && + split_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_1_putFirst = CAN_FIRE_RL_split_1_putFirst ; + + // rule RL_ssNoSynth_1_aw_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit = + ssNoSynth_1_aw_buffer_firstValid$Q_OUT && + (ssNoSynth_1_aw_buffer_ff$EMPTY_N || + MUX_split_1_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_1_aw_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit ; + + // rule RL_ssNoSynth_1_aw_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit = + (ssNoSynth_1_aw_buffer_ff$EMPTY_N || + MUX_split_1_flitLeft$write_1__SEL_2) && + plic$axi4_slave_awready ; + assign WILL_FIRE_RL_ssNoSynth_1_aw_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit ; + + // rule RL_ssNoSynth_1_aw_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue = + MUX_split_1_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit || + ssNoSynth_1_aw_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue ; + + // rule RL_ssNoSynth_1_aw_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit && + ssNoSynth_1_aw_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue ; + + // rule RL_split_1_putOther + assign CAN_FIRE_RL_split_1_putOther = + CAN_FIRE_RL_sink_selected_1 && + (!split_1_doPut$wget[172] || ssNoSynth_1_w_buffer_ff$FULL_N) && + split_1_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_1_putOther = CAN_FIRE_RL_split_1_putOther ; + + // rule RL_ssNoSynth_1_w_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit = + ssNoSynth_1_w_buffer_firstValid$Q_OUT && + (ssNoSynth_1_w_buffer_ff$EMPTY_N || + ssNoSynth_1_w_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_1_w_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit ; + + // rule RL_ssNoSynth_1_w_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_w_dropFlit = + (ssNoSynth_1_w_buffer_ff$EMPTY_N || + ssNoSynth_1_w_buffer_enqw$whas) && + plic$axi4_slave_wready ; + assign WILL_FIRE_RL_ssNoSynth_1_w_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_w_dropFlit ; + + // rule RL_ssNoSynth_1_w_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue = + ssNoSynth_1_w_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_1_w_dropFlit || + ssNoSynth_1_w_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_w_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue ; + + // rule RL_ssNoSynth_1_w_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_w_dropFlit && + ssNoSynth_1_w_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue ; + + // rule RL_split_2_putFirst + assign CAN_FIRE_RL_split_2_putFirst = + split_2_doPut_whas__144_AND_split_2_doPut_wget_ETC___d1151 && + split_2_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_2_putFirst = CAN_FIRE_RL_split_2_putFirst ; + + // rule RL_ssNoSynth_2_aw_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit = + ssNoSynth_2_aw_buffer_firstValid$Q_OUT && + (ssNoSynth_2_aw_buffer_ff$EMPTY_N || + MUX_split_2_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_2_aw_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit ; + + // rule RL_ssNoSynth_2_aw_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit = + (ssNoSynth_2_aw_buffer_ff$EMPTY_N || + MUX_split_2_flitLeft$write_1__SEL_2) && + proc$debug_module_mem_server_awready ; + assign WILL_FIRE_RL_ssNoSynth_2_aw_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit ; + + // rule RL_ssNoSynth_2_aw_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue = + MUX_split_2_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit || + ssNoSynth_2_aw_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue ; + + // rule RL_ssNoSynth_2_aw_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit && + ssNoSynth_2_aw_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue ; + + // rule RL_split_2_putOther + assign CAN_FIRE_RL_split_2_putOther = + CAN_FIRE_RL_sink_selected_2 && + (!split_2_doPut$wget[172] || ssNoSynth_2_w_buffer_ff$FULL_N) && + split_2_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_2_putOther = CAN_FIRE_RL_split_2_putOther ; + + // rule RL_ssNoSynth_2_w_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit = + ssNoSynth_2_w_buffer_firstValid$Q_OUT && + (ssNoSynth_2_w_buffer_ff$EMPTY_N || + ssNoSynth_2_w_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_2_w_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit ; + + // rule RL_ssNoSynth_2_w_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_w_dropFlit = + (ssNoSynth_2_w_buffer_ff$EMPTY_N || + ssNoSynth_2_w_buffer_enqw$whas) && + proc$debug_module_mem_server_wready ; + assign WILL_FIRE_RL_ssNoSynth_2_w_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_w_dropFlit ; + + // rule RL_ssNoSynth_2_w_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue = + ssNoSynth_2_w_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_2_w_dropFlit || + ssNoSynth_2_w_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_w_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue ; + + // rule RL_ssNoSynth_2_w_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_w_dropFlit && + ssNoSynth_2_w_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue ; + + // rule RL_ifcs_0_firstFlit + assign CAN_FIRE_RL_ifcs_0_firstFlit = + proc$master1_wvalid && + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && + ifcs_0_innerReq$FULL_N && + ifcs_0_innerRoute$FULL_N && + (IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 || + proc$master1_awvalid) && + ifcs_0_state == 2'd0 && + IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1221 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_firstFlit = CAN_FIRE_RL_ifcs_0_firstFlit ; + + // rule RL_ifcs_0_followFlits + assign CAN_FIRE_RL_ifcs_0_followFlits = + proc$master1_wvalid && + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && + ifcs_0_innerReq$FULL_N && + (IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 || + proc$master1_awvalid) && + ifcs_0_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_followFlits = CAN_FIRE_RL_ifcs_0_followFlits ; + + // rule RL_ifcs_0_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_0_nonRoutableFlit = + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && + IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1255 && + ifcs_0_state == 2'd0 && + IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1221 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_nonRoutableFlit = + CAN_FIRE_RL_ifcs_0_nonRoutableFlit ; + + // rule RL_ifcs_0_drainFlits + assign CAN_FIRE_RL_ifcs_0_drainFlits = + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && + proc$master1_wvalid && + ifcs_0_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_0_drainFlits = CAN_FIRE_RL_ifcs_0_drainFlits ; + + // rule __me_check_158 + assign CAN_FIRE___me_check_158 = 1'b1 ; + assign WILL_FIRE___me_check_158 = 1'b1 ; + + // rule RL_ifcs_0_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_0_drainNoRouteResponse = + msNoSynth_0_b_buffer_ff$FULL_N && ifcs_0_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_0_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_0_drainNoRouteResponse ; + + // rule RL_checkSinkReady_3 + assign CAN_FIRE_RL_checkSinkReady_3 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_3 = 1'd1 ; + + // rule RL_ifcs_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_1_drainNoRouteResponse = + msNoSynth_1_b_buffer_ff$FULL_N && ifcs_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_1_drainNoRouteResponse ; + + // rule RL_checkSinkReady_4 + assign CAN_FIRE_RL_checkSinkReady_4 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_4 = 1'd1 ; + + // rule RL_craftReq_2 + assign CAN_FIRE_RL_craftReq_2 = + ifcs_0_routeBack$EMPTY_N && ifcs_0_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_2 = CAN_FIRE_RL_craftReq_2 ; + + // rule RL_craftReq_3 + assign CAN_FIRE_RL_craftReq_3 = + ifcs_1_routeBack$EMPTY_N && ifcs_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_3 = CAN_FIRE_RL_craftReq_3 ; + + // rule RL_craftReq_4 + assign CAN_FIRE_RL_craftReq_4 = + ifcs_2_routeBack$EMPTY_N && ifcs_2_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_4 = CAN_FIRE_RL_craftReq_4 ; + + // rule RL_arbitrate_1 + assign CAN_FIRE_RL_arbitrate_1 = + reqWires_1_0_whas__669_AND_reqWires_1_0_wget___ETC___d1679 && + !state_1 ; + assign WILL_FIRE_RL_arbitrate_1 = CAN_FIRE_RL_arbitrate_1 ; + + // rule RL_source_selected_2 + assign CAN_FIRE_RL_source_selected_2 = + (!ifcs_0_routeBack$EMPTY_N || ifcs_0_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_0$whas ; + assign WILL_FIRE_RL_source_selected_2 = CAN_FIRE_RL_source_selected_2 ; + + // rule RL_burst_2 + assign CAN_FIRE_RL_burst_2 = + ifcs_0_rspBack$EMPTY_N && ifcs_0_routeBack$EMPTY_N && + state_1_680_AND_activeSource_1_0_768_769_AND_i_ETC___d1771 ; + assign WILL_FIRE_RL_burst_2 = CAN_FIRE_RL_burst_2 ; + + // rule RL_source_selected_3 + assign CAN_FIRE_RL_source_selected_3 = + (!ifcs_1_routeBack$EMPTY_N || ifcs_1_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_1$whas ; + assign WILL_FIRE_RL_source_selected_3 = CAN_FIRE_RL_source_selected_3 ; + + // rule RL_burst_3 + assign CAN_FIRE_RL_burst_3 = + ifcs_1_rspBack$EMPTY_N && ifcs_1_routeBack$EMPTY_N && + state_1_680_AND_activeSource_1_1_801_802_AND_i_ETC___d1804 ; + assign WILL_FIRE_RL_burst_3 = CAN_FIRE_RL_burst_3 ; + + // rule __me_check_197 + assign CAN_FIRE___me_check_197 = 1'b1 ; + assign WILL_FIRE___me_check_197 = 1'b1 ; + + // rule RL_source_selected_4 + assign CAN_FIRE_RL_source_selected_4 = + (!ifcs_2_routeBack$EMPTY_N || ifcs_2_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_2$whas ; + assign WILL_FIRE_RL_source_selected_4 = CAN_FIRE_RL_source_selected_4 ; + + // rule RL_burst_4 + assign CAN_FIRE_RL_burst_4 = + ifcs_2_rspBack$EMPTY_N && ifcs_2_routeBack$EMPTY_N && + state_1_680_AND_activeSource_1_2_835_836_AND_i_ETC___d1838 ; + assign WILL_FIRE_RL_burst_4 = CAN_FIRE_RL_burst_4 ; + + // rule __me_check_195 + assign CAN_FIRE___me_check_195 = 1'b1 ; + assign WILL_FIRE___me_check_195 = 1'b1 ; + + // rule __me_check_199 + assign CAN_FIRE___me_check_199 = 1'b1 ; + assign WILL_FIRE___me_check_199 = 1'b1 ; + + // rule RL_sink_selected_3 + assign CAN_FIRE_RL_sink_selected_3 = + !CAN_FIRE_RL_ifcs_0_drainNoRouteResponse && flitToSink_1_0$whas ; + assign WILL_FIRE_RL_sink_selected_3 = CAN_FIRE_RL_sink_selected_3 ; + + // rule RL_sink_selected_4 + assign CAN_FIRE_RL_sink_selected_4 = + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse && flitToSink_1_1$whas ; + assign WILL_FIRE_RL_sink_selected_4 = CAN_FIRE_RL_sink_selected_4 ; + + // rule __me_check_201 + assign CAN_FIRE___me_check_201 = 1'b1 ; + assign WILL_FIRE___me_check_201 = 1'b1 ; + + // rule RL_ifcs_0_forwardRsp + assign CAN_FIRE_RL_ifcs_0_forwardRsp = + msNoSynth_0_b_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_3 && + !ifcs_0_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_0_forwardRsp = CAN_FIRE_RL_ifcs_0_forwardRsp ; + + // rule RL_msNoSynth_0_b_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_b_forwardFlit = + !tmp0_b_buffer_ff$FULL_N || + msNoSynth_0_b_buffer_firstValid$Q_OUT && + (msNoSynth_0_b_buffer_ff$EMPTY_N || + msNoSynth_0_b_buffer_enqw$whas) ; + assign WILL_FIRE_RL_msNoSynth_0_b_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_b_forwardFlit ; + + // rule RL_tmp0_b_forwardFlit + assign CAN_FIRE_RL_tmp0_b_forwardFlit = + tmp0_b_buffer_firstValid$Q_OUT && + (tmp0_b_buffer_ff$EMPTY_N || tmp0_b_buffer_enqw$whas) ; + assign WILL_FIRE_RL_tmp0_b_forwardFlit = CAN_FIRE_RL_tmp0_b_forwardFlit ; + + // rule RL_tmp0_b_dropFlit + assign CAN_FIRE_RL_tmp0_b_dropFlit = + (tmp0_b_buffer_ff$EMPTY_N || tmp0_b_buffer_enqw$whas) && + proc$master1_bready ; + assign WILL_FIRE_RL_tmp0_b_dropFlit = CAN_FIRE_RL_tmp0_b_dropFlit ; + + // rule RL_tmp0_b_buffer_enqueue + assign CAN_FIRE_RL_tmp0_b_buffer_enqueue = + tmp0_b_buffer_enqw$whas && + (!CAN_FIRE_RL_tmp0_b_dropFlit || tmp0_b_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp0_b_buffer_enqueue = + CAN_FIRE_RL_tmp0_b_buffer_enqueue ; + + // rule RL_tmp0_b_buffer_dequeue + assign CAN_FIRE_RL_tmp0_b_buffer_dequeue = + CAN_FIRE_RL_tmp0_b_dropFlit && tmp0_b_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp0_b_buffer_dequeue = + CAN_FIRE_RL_tmp0_b_buffer_dequeue ; + + // rule RL_msNoSynth_0_b_dropFlit + assign CAN_FIRE_RL_msNoSynth_0_b_dropFlit = + (msNoSynth_0_b_buffer_ff$EMPTY_N || + msNoSynth_0_b_buffer_enqw$whas) && + tmp0_b_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_b_dropFlit = + CAN_FIRE_RL_msNoSynth_0_b_dropFlit ; + + // rule RL_msNoSynth_0_b_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue = + msNoSynth_0_b_buffer_enqw$whas && + (!CAN_FIRE_RL_msNoSynth_0_b_dropFlit || + msNoSynth_0_b_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_b_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue ; + + // rule RL_msNoSynth_0_b_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_b_dropFlit && + msNoSynth_0_b_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_b_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue ; + + // rule RL_ifcs_0_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp = + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && + ifcs_0_noRoute_inner_pendingReq$port1__read && + ifcs_0_noRouteRsp$FULL_N && + proc$master1_wvalid ; + assign WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; + + // rule __me_check_156 + assign CAN_FIRE___me_check_156 = 1'b1 ; + assign WILL_FIRE___me_check_156 = 1'b1 ; + + // rule __me_check_157 + assign CAN_FIRE___me_check_157 = 1'b1 ; + assign WILL_FIRE___me_check_157 = 1'b1 ; + + // rule __me_check_160 + assign CAN_FIRE___me_check_160 = 1'b1 ; + assign WILL_FIRE___me_check_160 = 1'b1 ; + + // rule RL_merged_0_genFirst + assign CAN_FIRE_RL_merged_0_genFirst = + proc$master1_awvalid && proc$master1_wvalid && + merged_0_doDrop$whas && + merged_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_0_genFirst = CAN_FIRE_RL_merged_0_genFirst ; + + // rule RL_msNoSynth_0_aw_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_aw_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_aw_forwardReady = 1'd1 ; + + // rule RL_tmp0_aw_forwardReady + assign CAN_FIRE_RL_tmp0_aw_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp0_aw_forwardReady = 1'd1 ; + + // rule RL_merged_0_genOther + assign CAN_FIRE_RL_merged_0_genOther = + proc$master1_wvalid && merged_0_doDrop$whas && + merged_0_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_merged_0_genOther = CAN_FIRE_RL_merged_0_genOther ; + + // rule RL_msNoSynth_0_w_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_w_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_w_forwardReady = 1'd1 ; + + // rule RL_tmp0_w_forwardReady + assign CAN_FIRE_RL_tmp0_w_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp0_w_forwardReady = 1'd1 ; + + // rule RL_ifcs_1_forwardRsp + assign CAN_FIRE_RL_ifcs_1_forwardRsp = + msNoSynth_1_b_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_4 && + !ifcs_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_forwardRsp = CAN_FIRE_RL_ifcs_1_forwardRsp ; + + // rule RL_msNoSynth_1_b_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_b_forwardFlit = + msNoSynth_1_b_buffer_firstValid$Q_OUT && + (msNoSynth_1_b_buffer_ff$EMPTY_N || + msNoSynth_1_b_buffer_enqw$whas) ; + assign WILL_FIRE_RL_msNoSynth_1_b_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_b_forwardFlit ; + + // rule RL_msNoSynth_1_b_dropFlit + assign CAN_FIRE_RL_msNoSynth_1_b_dropFlit = + (msNoSynth_1_b_buffer_ff$EMPTY_N || + msNoSynth_1_b_buffer_enqw$whas) && + debug_module$master_bready ; + assign WILL_FIRE_RL_msNoSynth_1_b_dropFlit = + CAN_FIRE_RL_msNoSynth_1_b_dropFlit ; + + // rule RL_msNoSynth_1_b_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue = + msNoSynth_1_b_buffer_enqw$whas && + (!CAN_FIRE_RL_msNoSynth_1_b_dropFlit || + msNoSynth_1_b_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_b_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue ; + + // rule RL_msNoSynth_1_b_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_b_dropFlit && + msNoSynth_1_b_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_b_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue ; + + // rule RL_ifcs_0_firstFlit_1 + assign CAN_FIRE_RL_ifcs_0_firstFlit_1 = + uncached_mem_shim_bff$EMPTY_N && ifcs_0_rspBack$FULL_N && + ifcs_0_routeBack$FULL_N && + !ifcs_0_state_1 ; + assign WILL_FIRE_RL_ifcs_0_firstFlit_1 = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; + + // rule RL_ifcs_0_followFlits_1 + assign CAN_FIRE_RL_ifcs_0_followFlits_1 = + uncached_mem_shim_bff$EMPTY_N && ifcs_0_rspBack$FULL_N && + ifcs_0_state_1 ; + assign WILL_FIRE_RL_ifcs_0_followFlits_1 = + CAN_FIRE_RL_ifcs_0_followFlits_1 ; + + // rule __me_check_170 + assign CAN_FIRE___me_check_170 = 1'b1 ; + assign WILL_FIRE___me_check_170 = 1'b1 ; + + // rule RL_ssNoSynth_0_b_forwardReady + assign CAN_FIRE_RL_ssNoSynth_0_b_forwardReady = 1'b1 ; + assign WILL_FIRE_RL_ssNoSynth_0_b_forwardReady = 1'b1 ; + + // rule RL_ug_uncached_mem_shim_master_u_b_doPut + assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut = + uncached_mem_shim_bff$FULL_N && + ug_uncached_mem_shim_master_u_b_putWire$whas ; + assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut ; + + // rule RL_ifcs_1_firstFlit_1 + assign CAN_FIRE_RL_ifcs_1_firstFlit_1 = + plic$axi4_slave_bvalid && ifcs_1_rspBack$FULL_N && + ifcs_1_routeBack$FULL_N && + !ifcs_1_state_1 ; + assign WILL_FIRE_RL_ifcs_1_firstFlit_1 = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; + + // rule RL_ifcs_1_followFlits_1 + assign CAN_FIRE_RL_ifcs_1_followFlits_1 = + plic$axi4_slave_bvalid && ifcs_1_rspBack$FULL_N && + ifcs_1_state_1 ; + assign WILL_FIRE_RL_ifcs_1_followFlits_1 = + CAN_FIRE_RL_ifcs_1_followFlits_1 ; + + // rule __me_check_172 + assign CAN_FIRE___me_check_172 = 1'b1 ; + assign WILL_FIRE___me_check_172 = 1'b1 ; + + // rule RL_ssNoSynth_1_b_forwardReady + assign CAN_FIRE_RL_ssNoSynth_1_b_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_b_forwardReady = 1'd1 ; + + // rule RL_ifcs_2_firstFlit + assign CAN_FIRE_RL_ifcs_2_firstFlit = + proc$debug_module_mem_server_bvalid && ifcs_2_rspBack$FULL_N && + ifcs_2_routeBack$FULL_N && + !ifcs_2_state ; + assign WILL_FIRE_RL_ifcs_2_firstFlit = CAN_FIRE_RL_ifcs_2_firstFlit ; + + // rule RL_ifcs_2_followFlits + assign CAN_FIRE_RL_ifcs_2_followFlits = + proc$debug_module_mem_server_bvalid && ifcs_2_rspBack$FULL_N && + ifcs_2_state ; + assign WILL_FIRE_RL_ifcs_2_followFlits = CAN_FIRE_RL_ifcs_2_followFlits ; + + // rule __me_check_174 + assign CAN_FIRE___me_check_174 = 1'b1 ; + assign WILL_FIRE___me_check_174 = 1'b1 ; + + // rule RL_ssNoSynth_2_b_forwardReady + assign CAN_FIRE_RL_ssNoSynth_2_b_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_b_forwardReady = 1'd1 ; + + // rule RL_ifcs_0_1_firstFlit + assign CAN_FIRE_RL_ifcs_0_1_firstFlit = + proc$master1_arvalid && ifcs_0_1_innerReq$FULL_N && + ifcs_0_1_innerRoute$FULL_N && + ifcs_0_1_state == 2'd0 && + IF_proc_master1_ar_araddr__852_BITS_63_TO_40_8_ETC___d1878 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_1_firstFlit = CAN_FIRE_RL_ifcs_0_1_firstFlit ; + + // rule RL_ifcs_0_1_followFlits + assign CAN_FIRE_RL_ifcs_0_1_followFlits = + proc$master1_arvalid && ifcs_0_1_innerReq$FULL_N && + ifcs_0_1_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_1_followFlits = + CAN_FIRE_RL_ifcs_0_1_followFlits ; + + // rule RL_ifcs_0_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit = + ifcs_0_1_noRoute_flitCount == 9'd0 && proc$master1_arvalid && + ifcs_0_1_state == 2'd0 && + IF_proc_master1_ar_araddr__852_BITS_63_TO_40_8_ETC___d1878 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ; + + // rule RL_ifcs_0_1_drainFlits + assign CAN_FIRE_RL_ifcs_0_1_drainFlits = + proc$master1_arvalid && ifcs_0_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_0_1_drainFlits = CAN_FIRE_RL_ifcs_0_1_drainFlits ; + + // rule __me_check_205 + assign CAN_FIRE___me_check_205 = 1'b1 ; + assign WILL_FIRE___me_check_205 = 1'b1 ; + + // rule RL_ifcs_0_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse = + msNoSynth_0_r_buffer_ff$FULL_N && ifcs_0_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + + // rule RL_checkSinkReady_8 + assign CAN_FIRE_RL_checkSinkReady_8 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_8 = 1'd1 ; + + // rule RL_ifcs_1_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse = + msNoSynth_1_r_buffer_ff$FULL_N && ifcs_1_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; + + // rule RL_checkSinkReady_9 + assign CAN_FIRE_RL_checkSinkReady_9 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_9 = 1'd1 ; + + // rule RL_craftReq_7 + assign CAN_FIRE_RL_craftReq_7 = + ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_7 = CAN_FIRE_RL_craftReq_7 ; + + // rule RL_craftReq_8 + assign CAN_FIRE_RL_craftReq_8 = + ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_8 = CAN_FIRE_RL_craftReq_8 ; + + // rule RL_craftReq_9 + assign CAN_FIRE_RL_craftReq_9 = + ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_9 = CAN_FIRE_RL_craftReq_9 ; + + // rule RL_arbitrate_3 + assign CAN_FIRE_RL_arbitrate_3 = + reqWires_1_1_0_whas__312_AND_reqWires_1_1_0_wg_ETC___d2322 && + !state_1_1_1 ; + assign WILL_FIRE_RL_arbitrate_3 = CAN_FIRE_RL_arbitrate_3 ; + + // rule RL_source_selected_7 + assign CAN_FIRE_RL_source_selected_7 = + (!ifcs_0_1_routeBack$EMPTY_N || ifcs_0_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_0$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_7 = CAN_FIRE_RL_source_selected_7 ; + + // rule RL_burst_7 + assign CAN_FIRE_RL_burst_7 = + ifcs_0_1_rspBack$EMPTY_N && ifcs_0_1_routeBack$EMPTY_N && + state_1_1_1_323_AND_activeSource_1_1_0_417_418_ETC___d2420 ; + assign WILL_FIRE_RL_burst_7 = CAN_FIRE_RL_burst_7 ; + + // rule RL_source_selected_8 + assign CAN_FIRE_RL_source_selected_8 = + (!ifcs_1_1_routeBack$EMPTY_N || ifcs_1_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_1_1$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_8 = CAN_FIRE_RL_source_selected_8 ; + + // rule RL_burst_8 + assign CAN_FIRE_RL_burst_8 = + ifcs_1_1_rspBack$EMPTY_N && ifcs_1_1_routeBack$EMPTY_N && + state_1_1_1_323_AND_activeSource_1_1_1_1_453_4_ETC___d2456 ; + assign WILL_FIRE_RL_burst_8 = CAN_FIRE_RL_burst_8 ; + + // rule __me_check_244 + assign CAN_FIRE___me_check_244 = 1'b1 ; + assign WILL_FIRE___me_check_244 = 1'b1 ; + + // rule RL_source_selected_9 + assign CAN_FIRE_RL_source_selected_9 = + (!ifcs_2_1_routeBack$EMPTY_N || ifcs_2_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_2$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_9 = CAN_FIRE_RL_source_selected_9 ; + + // rule RL_burst_9 + assign CAN_FIRE_RL_burst_9 = + ifcs_2_1_rspBack$EMPTY_N && ifcs_2_1_routeBack$EMPTY_N && + state_1_1_1_323_AND_activeSource_1_1_2_489_490_ETC___d2492 ; + assign WILL_FIRE_RL_burst_9 = CAN_FIRE_RL_burst_9 ; + + // rule __me_check_242 + assign CAN_FIRE___me_check_242 = 1'b1 ; + assign WILL_FIRE___me_check_242 = 1'b1 ; + + // rule __me_check_246 + assign CAN_FIRE___me_check_246 = 1'b1 ; + assign WILL_FIRE___me_check_246 = 1'b1 ; + + // rule RL_sink_selected_8 + assign CAN_FIRE_RL_sink_selected_8 = + !CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse && + flitToSink_1_1_0$whas ; + assign WILL_FIRE_RL_sink_selected_8 = CAN_FIRE_RL_sink_selected_8 ; + + // rule RL_sink_selected_9 + assign CAN_FIRE_RL_sink_selected_9 = + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse && + flitToSink_1_1_1_1$whas ; + assign WILL_FIRE_RL_sink_selected_9 = CAN_FIRE_RL_sink_selected_9 ; + + // rule __me_check_248 + assign CAN_FIRE___me_check_248 = 1'b1 ; + assign WILL_FIRE___me_check_248 = 1'b1 ; + + // rule RL_ifcs_0_1_forwardRsp + assign CAN_FIRE_RL_ifcs_0_1_forwardRsp = + msNoSynth_0_r_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_8 && + !ifcs_0_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_0_1_forwardRsp = CAN_FIRE_RL_ifcs_0_1_forwardRsp ; + + // rule RL_msNoSynth_0_r_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_r_forwardFlit = + !tmp0_r_buffer_ff$FULL_N || + msNoSynth_0_r_buffer_firstValid$Q_OUT && + (msNoSynth_0_r_buffer_ff$EMPTY_N || + msNoSynth_0_r_buffer_enqw$whas) ; + assign WILL_FIRE_RL_msNoSynth_0_r_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_r_forwardFlit ; + + // rule RL_tmp0_r_forwardFlit + assign CAN_FIRE_RL_tmp0_r_forwardFlit = + tmp0_r_buffer_firstValid$Q_OUT && + (tmp0_r_buffer_ff$EMPTY_N || tmp0_r_buffer_enqw$whas) ; + assign WILL_FIRE_RL_tmp0_r_forwardFlit = CAN_FIRE_RL_tmp0_r_forwardFlit ; + + // rule RL_tmp0_r_dropFlit + assign CAN_FIRE_RL_tmp0_r_dropFlit = + (tmp0_r_buffer_ff$EMPTY_N || tmp0_r_buffer_enqw$whas) && + proc$master1_rready ; + assign WILL_FIRE_RL_tmp0_r_dropFlit = CAN_FIRE_RL_tmp0_r_dropFlit ; + + // rule RL_tmp0_r_buffer_enqueue + assign CAN_FIRE_RL_tmp0_r_buffer_enqueue = + tmp0_r_buffer_enqw$whas && + (!CAN_FIRE_RL_tmp0_r_dropFlit || tmp0_r_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp0_r_buffer_enqueue = + CAN_FIRE_RL_tmp0_r_buffer_enqueue ; + + // rule RL_tmp0_r_buffer_dequeue + assign CAN_FIRE_RL_tmp0_r_buffer_dequeue = + CAN_FIRE_RL_tmp0_r_dropFlit && tmp0_r_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp0_r_buffer_dequeue = + CAN_FIRE_RL_tmp0_r_buffer_dequeue ; + + // rule RL_msNoSynth_0_r_dropFlit + assign CAN_FIRE_RL_msNoSynth_0_r_dropFlit = + (msNoSynth_0_r_buffer_ff$EMPTY_N || + msNoSynth_0_r_buffer_enqw$whas) && + tmp0_r_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_r_dropFlit = + CAN_FIRE_RL_msNoSynth_0_r_dropFlit ; + + // rule RL_msNoSynth_0_r_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue = + msNoSynth_0_r_buffer_enqw$whas && + (!CAN_FIRE_RL_msNoSynth_0_r_dropFlit || + msNoSynth_0_r_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_r_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue ; + + // rule RL_msNoSynth_0_r_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_r_dropFlit && + msNoSynth_0_r_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_r_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue ; + + // rule RL_ifcs_0_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = + x_port1__read__h73054 != 9'd0 && ifcs_0_1_noRouteRsp$FULL_N && + (x_port1__read__h73054 != 9'd1 || proc$master1_arvalid) ; + assign WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; + + // rule __me_check_203 + assign CAN_FIRE___me_check_203 = 1'b1 ; + assign WILL_FIRE___me_check_203 = 1'b1 ; + + // rule __me_check_204 + assign CAN_FIRE___me_check_204 = 1'b1 ; + assign WILL_FIRE___me_check_204 = 1'b1 ; + + // rule __me_check_207 + assign CAN_FIRE___me_check_207 = 1'b1 ; + assign WILL_FIRE___me_check_207 = 1'b1 ; + + // rule RL_msNoSynth_0_ar_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_ar_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_ar_forwardReady = 1'd1 ; + + // rule RL_tmp0_ar_forwardReady + assign CAN_FIRE_RL_tmp0_ar_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp0_ar_forwardReady = 1'd1 ; + + // rule RL_ifcs_1_1_forwardRsp + assign CAN_FIRE_RL_ifcs_1_1_forwardRsp = + msNoSynth_1_r_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_9 && + !ifcs_1_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_1_forwardRsp = CAN_FIRE_RL_ifcs_1_1_forwardRsp ; + + // rule RL_msNoSynth_1_r_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_r_forwardFlit = + msNoSynth_1_r_buffer_firstValid$Q_OUT && + (msNoSynth_1_r_buffer_ff$EMPTY_N || + msNoSynth_1_r_buffer_enqw$whas) ; + assign WILL_FIRE_RL_msNoSynth_1_r_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_r_forwardFlit ; + + // rule RL_msNoSynth_1_r_dropFlit + assign CAN_FIRE_RL_msNoSynth_1_r_dropFlit = + (msNoSynth_1_r_buffer_ff$EMPTY_N || + msNoSynth_1_r_buffer_enqw$whas) && + debug_module$master_rready ; + assign WILL_FIRE_RL_msNoSynth_1_r_dropFlit = + CAN_FIRE_RL_msNoSynth_1_r_dropFlit ; + + // rule RL_msNoSynth_1_r_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue = + msNoSynth_1_r_buffer_enqw$whas && + (!CAN_FIRE_RL_msNoSynth_1_r_dropFlit || + msNoSynth_1_r_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_r_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue ; + + // rule RL_msNoSynth_1_r_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_r_dropFlit && + msNoSynth_1_r_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_r_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue ; + + // rule RL_ifcs_1_firstFlit + assign CAN_FIRE_RL_ifcs_1_firstFlit = + debug_module$master_wvalid && + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1283 && + ifcs_1_innerReq$FULL_N && + ifcs_1_innerRoute$FULL_N && + (IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1290 || + debug_module$master_awvalid) && + ifcs_1_state == 2'd0 && + IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1325 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_firstFlit = CAN_FIRE_RL_ifcs_1_firstFlit ; + + // rule RL_ifcs_1_followFlits + assign CAN_FIRE_RL_ifcs_1_followFlits = + debug_module$master_wvalid && + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1283 && + ifcs_1_innerReq$FULL_N && + (IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1290 || + debug_module$master_awvalid) && + ifcs_1_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_followFlits = CAN_FIRE_RL_ifcs_1_followFlits ; + + // rule RL_ifcs_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_1_nonRoutableFlit = + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1283 && + IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1360 && + ifcs_1_state == 2'd0 && + IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1325 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_1_nonRoutableFlit ; + + // rule RL_ifcs_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp = + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1283 && + ifcs_1_noRoute_inner_pendingReq$port1__read && + ifcs_1_noRouteRsp$FULL_N && + debug_module$master_wvalid ; + assign WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; + + // rule RL_ifcs_1_drainFlits + assign CAN_FIRE_RL_ifcs_1_drainFlits = + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1283 && + debug_module$master_wvalid && + ifcs_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_1_drainFlits = CAN_FIRE_RL_ifcs_1_drainFlits ; + + // rule __me_check_163 + assign CAN_FIRE___me_check_163 = 1'b1 ; + assign WILL_FIRE___me_check_163 = 1'b1 ; + + // rule __me_check_164 + assign CAN_FIRE___me_check_164 = 1'b1 ; + assign WILL_FIRE___me_check_164 = 1'b1 ; + + // rule __me_check_165 + assign CAN_FIRE___me_check_165 = 1'b1 ; + assign WILL_FIRE___me_check_165 = 1'b1 ; + + // rule __me_check_167 + assign CAN_FIRE___me_check_167 = 1'b1 ; + assign WILL_FIRE___me_check_167 = 1'b1 ; + + // rule RL_merged_1_genFirst + assign CAN_FIRE_RL_merged_1_genFirst = + debug_module$master_awvalid && debug_module$master_wvalid && + merged_1_doDrop$whas && + merged_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_1_genFirst = CAN_FIRE_RL_merged_1_genFirst ; + + // rule RL_msNoSynth_1_aw_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_aw_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_aw_forwardReady = 1'd1 ; + + // rule RL_merged_1_genOther + assign CAN_FIRE_RL_merged_1_genOther = + debug_module$master_wvalid && merged_1_doDrop$whas && + merged_1_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_merged_1_genOther = CAN_FIRE_RL_merged_1_genOther ; + + // rule RL_msNoSynth_1_w_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_w_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_w_forwardReady = 1'd1 ; + + // rule RL_ifcs_1_1_firstFlit + assign CAN_FIRE_RL_ifcs_1_1_firstFlit = + debug_module$master_arvalid && ifcs_1_1_innerReq$FULL_N && + ifcs_1_1_innerRoute$FULL_N && + ifcs_1_1_state == 2'd0 && + IF_debug_module_master_ar_araddr__944_BITS_63__ETC___d1970 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_firstFlit = CAN_FIRE_RL_ifcs_1_1_firstFlit ; + + // rule RL_ifcs_1_1_followFlits + assign CAN_FIRE_RL_ifcs_1_1_followFlits = + debug_module$master_arvalid && ifcs_1_1_innerReq$FULL_N && + ifcs_1_1_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_followFlits = + CAN_FIRE_RL_ifcs_1_1_followFlits ; + + // rule RL_ifcs_1_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit = + ifcs_1_1_noRoute_flitCount == 9'd0 && + debug_module$master_arvalid && + ifcs_1_1_state == 2'd0 && + IF_debug_module_master_ar_araddr__944_BITS_63__ETC___d1970 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ; + + // rule RL_ifcs_1_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = + x_port1__read__h75518 != 9'd0 && ifcs_1_1_noRouteRsp$FULL_N && + (x_port1__read__h75518 != 9'd1 || debug_module$master_arvalid) ; + assign WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; + + // rule RL_ifcs_1_1_drainFlits + assign CAN_FIRE_RL_ifcs_1_1_drainFlits = + debug_module$master_arvalid && ifcs_1_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_1_1_drainFlits = CAN_FIRE_RL_ifcs_1_1_drainFlits ; + + // rule __me_check_210 + assign CAN_FIRE___me_check_210 = 1'b1 ; + assign WILL_FIRE___me_check_210 = 1'b1 ; + + // rule __me_check_211 + assign CAN_FIRE___me_check_211 = 1'b1 ; + assign WILL_FIRE___me_check_211 = 1'b1 ; + + // rule __me_check_212 + assign CAN_FIRE___me_check_212 = 1'b1 ; + assign WILL_FIRE___me_check_212 = 1'b1 ; + + // rule __me_check_214 + assign CAN_FIRE___me_check_214 = 1'b1 ; + assign WILL_FIRE___me_check_214 = 1'b1 ; + + // rule RL_msNoSynth_1_ar_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_ar_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_ar_forwardReady = 1'd1 ; + + // rule RL_ifcs_0_1_firstFlit_1 + assign CAN_FIRE_RL_ifcs_0_1_firstFlit_1 = + uncached_mem_shim_rff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && + ifcs_0_1_routeBack$FULL_N && + !ifcs_0_1_state_1 ; + assign WILL_FIRE_RL_ifcs_0_1_firstFlit_1 = + CAN_FIRE_RL_ifcs_0_1_firstFlit_1 ; + + // rule RL_ifcs_0_1_followFlits_1 + assign CAN_FIRE_RL_ifcs_0_1_followFlits_1 = + uncached_mem_shim_rff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && + ifcs_0_1_state_1 ; + assign WILL_FIRE_RL_ifcs_0_1_followFlits_1 = + CAN_FIRE_RL_ifcs_0_1_followFlits_1 ; + + // rule __me_check_217 + assign CAN_FIRE___me_check_217 = 1'b1 ; + assign WILL_FIRE___me_check_217 = 1'b1 ; + + // rule RL_ssNoSynth_0_r_forwardReady + assign CAN_FIRE_RL_ssNoSynth_0_r_forwardReady = 1'b1 ; + assign WILL_FIRE_RL_ssNoSynth_0_r_forwardReady = 1'b1 ; + + // rule RL_ug_uncached_mem_shim_master_u_r_doPut + assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut = + uncached_mem_shim_rff$FULL_N && + ug_uncached_mem_shim_master_u_r_putWire$whas ; + assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut ; + + // rule RL_ifcs_1_1_firstFlit_1 + assign CAN_FIRE_RL_ifcs_1_1_firstFlit_1 = + plic$axi4_slave_rvalid && ifcs_1_1_rspBack$FULL_N && + ifcs_1_1_routeBack$FULL_N && + !ifcs_1_1_state_1 ; + assign WILL_FIRE_RL_ifcs_1_1_firstFlit_1 = + CAN_FIRE_RL_ifcs_1_1_firstFlit_1 ; + + // rule RL_ifcs_1_1_followFlits_1 + assign CAN_FIRE_RL_ifcs_1_1_followFlits_1 = + plic$axi4_slave_rvalid && ifcs_1_1_rspBack$FULL_N && + ifcs_1_1_state_1 ; + assign WILL_FIRE_RL_ifcs_1_1_followFlits_1 = + CAN_FIRE_RL_ifcs_1_1_followFlits_1 ; + + // rule __me_check_219 + assign CAN_FIRE___me_check_219 = 1'b1 ; + assign WILL_FIRE___me_check_219 = 1'b1 ; + + // rule RL_ssNoSynth_1_r_forwardReady + assign CAN_FIRE_RL_ssNoSynth_1_r_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_r_forwardReady = 1'd1 ; + + // rule RL_ClientServerRequest_1 + assign CAN_FIRE_RL_ClientServerRequest_1 = + proc$RDY_hart0_gpr_mem_server_request_put && + debug_module$RDY_hart0_gpr_mem_client_request_get ; + assign WILL_FIRE_RL_ClientServerRequest_1 = + CAN_FIRE_RL_ClientServerRequest_1 ; + + // rule RL_ClientServerRequest_2 + assign CAN_FIRE_RL_ClientServerRequest_2 = + proc$RDY_hart0_csr_mem_server_request_put && + debug_module$RDY_hart0_csr_mem_client_request_get ; + assign WILL_FIRE_RL_ClientServerRequest_2 = + CAN_FIRE_RL_ClientServerRequest_2 ; + + // rule RL_ifcs_2_1_firstFlit + assign CAN_FIRE_RL_ifcs_2_1_firstFlit = + proc$debug_module_mem_server_rvalid && ifcs_2_1_rspBack$FULL_N && + ifcs_2_1_routeBack$FULL_N && + !ifcs_2_1_state ; + assign WILL_FIRE_RL_ifcs_2_1_firstFlit = CAN_FIRE_RL_ifcs_2_1_firstFlit ; + + // rule RL_ifcs_2_1_followFlits + assign CAN_FIRE_RL_ifcs_2_1_followFlits = + proc$debug_module_mem_server_rvalid && ifcs_2_1_rspBack$FULL_N && + ifcs_2_1_state ; + assign WILL_FIRE_RL_ifcs_2_1_followFlits = + CAN_FIRE_RL_ifcs_2_1_followFlits ; + + // rule __me_check_221 + assign CAN_FIRE___me_check_221 = 1'b1 ; + assign WILL_FIRE___me_check_221 = 1'b1 ; + + // rule RL_ssNoSynth_2_r_forwardReady + assign CAN_FIRE_RL_ssNoSynth_2_r_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_r_forwardReady = 1'd1 ; + + // inputs to muxes for submodule ports + assign MUX_activeSource_0$write_1__SEL_1 = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + !ifcs_0_innerReq$D_OUT[1] ; + assign MUX_activeSource_1_1_0$write_1__SEL_1 = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[1] ; + assign MUX_activeSource_1_1_0$write_1__SEL_2 = + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[1] ; + assign MUX_activeSource_1_1_0$write_1__SEL_3 = + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[1] ; + assign MUX_flitToSink_0$wset_1__SEL_1 = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[0] ; + assign MUX_flitToSink_0$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[0] ; + assign MUX_flitToSink_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[1] ; + assign MUX_flitToSink_1$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[1] ; + assign MUX_flitToSink_1_0$wset_1__SEL_1 = + WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_2 = + WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_3 = + WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_4 = + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + ifcs_0_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_5 = + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + ifcs_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_6 = + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + ifcs_2_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[0] ; + assign MUX_flitToSink_1_0_1$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[0] ; + assign MUX_flitToSink_1_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_2 = + WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_3 = + WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_4 = + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + ifcs_0_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_5 = + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + ifcs_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_6 = + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + ifcs_2_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_1 = + WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_2 = + WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_3 = + WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_4 = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_5 = + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_6 = + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[1] ; + assign MUX_flitToSink_1_1_1$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_2 = + WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_3 = + WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_4 = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_5 = + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_6 = + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_2$wset_1__SEL_1 = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[2] ; + assign MUX_flitToSink_1_2$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[2] ; + assign MUX_flitToSink_2$wset_1__SEL_1 = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[2] ; + assign MUX_flitToSink_2$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[2] ; + assign MUX_ifcs_0_1_state_1$write_1__SEL_1 = + WILL_FIRE_RL_ifcs_0_1_followFlits_1 && + uncached_mem_shim_rff$D_OUT[1] ; + assign MUX_ifcs_0_state$write_1__PSEL_1 = + WILL_FIRE_RL_ifcs_0_drainFlits || + WILL_FIRE_RL_ifcs_0_followFlits ; + assign MUX_ifcs_0_state$write_1__SEL_1 = + MUX_ifcs_0_state$write_1__PSEL_1 && proc$master1_wlast ; + assign MUX_ifcs_0_state$write_1__SEL_2 = + WILL_FIRE_RL_ifcs_0_firstFlit && !proc$master1_wlast ; + assign MUX_ifcs_0_state$write_1__SEL_3 = + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && !proc$master1_wlast ; + assign MUX_ifcs_1_1_state_1$write_1__SEL_1 = + WILL_FIRE_RL_ifcs_1_1_followFlits_1 && plic$axi4_slave_rlast ; + assign MUX_ifcs_1_state$write_1__PSEL_1 = + WILL_FIRE_RL_ifcs_1_drainFlits || + WILL_FIRE_RL_ifcs_1_followFlits ; + assign MUX_ifcs_1_state$write_1__SEL_1 = + MUX_ifcs_1_state$write_1__PSEL_1 && debug_module$master_wlast ; + assign MUX_ifcs_1_state$write_1__SEL_2 = + WILL_FIRE_RL_ifcs_1_firstFlit && !debug_module$master_wlast ; + assign MUX_ifcs_1_state$write_1__SEL_3 = + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && + !debug_module$master_wlast ; + assign MUX_ifcs_2_1_state$write_1__SEL_1 = + WILL_FIRE_RL_ifcs_2_1_followFlits && + proc$debug_module_mem_server_rlast ; + assign MUX_proc$start_1__SEL_1 = + WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1 ; + assign MUX_split_0_flitLeft$write_1__SEL_1 = + WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] ; + assign MUX_split_0_flitLeft$write_1__SEL_2 = + WILL_FIRE_RL_split_0_putFirst && !split_0_doPut$wget[172] ; + assign MUX_split_1_flitLeft$write_1__SEL_1 = + WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] ; + assign MUX_split_1_flitLeft$write_1__SEL_2 = + WILL_FIRE_RL_split_1_putFirst && !split_1_doPut$wget[172] ; + assign MUX_split_2_flitLeft$write_1__SEL_1 = + WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] ; + assign MUX_split_2_flitLeft$write_1__SEL_2 = + WILL_FIRE_RL_split_2_putFirst && !split_2_doPut$wget[172] ; + assign MUX_state$write_1__SEL_1 = + WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[1] ; + assign MUX_state$write_1__SEL_2 = + WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[1] ; + assign MUX_state_1_1_1$write_1__SEL_1 = + WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[1] ; + assign MUX_state_1_1_1$write_1__SEL_2 = + WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[1] ; + assign MUX_state_1_1_1$write_1__SEL_3 = + WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[1] ; + assign MUX_activeSource_0$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate && + IF_SEXT_arbiter_lastSelect_493_494_BIT_0_495_A_ETC___d1517 ; + assign MUX_activeSource_1$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate && + IF_SEXT_arbiter_lastSelect_493_494_BIT_0_495_A_ETC___d1521 ; + assign MUX_activeSource_1_1_0$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate_3 && + IF_SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_3_ETC___d2370 ; + assign MUX_activeSource_1_1_1_1$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate_3 && + IF_SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_3_ETC___d2376 ; + assign MUX_activeSource_1_1_2$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate_3 && + IF_SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_3_ETC___d2382 ; + assign MUX_merged_0_flitLeft$write_1__VAL_1 = merged_0_flitLeft - 8'd1 ; + assign MUX_merged_1_flitLeft$write_1__VAL_1 = merged_1_flitLeft - 8'd1 ; + always@(MUX_flitToSink_1_0$wset_1__SEL_1 or + MUX_flitToSink_1_0$wset_1__SEL_4 or + ifcs_0_rspBack$D_OUT or + MUX_flitToSink_1_0$wset_1__SEL_2 or + MUX_flitToSink_1_0$wset_1__SEL_5 or + ifcs_1_rspBack$D_OUT or + MUX_flitToSink_1_0$wset_1__SEL_3 or + MUX_flitToSink_1_0$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_0$wset_1__SEL_1 || MUX_flitToSink_1_0$wset_1__SEL_4: + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = ifcs_0_rspBack$D_OUT; + MUX_flitToSink_1_0$wset_1__SEL_2 || MUX_flitToSink_1_0$wset_1__SEL_5: + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = ifcs_1_rspBack$D_OUT; + MUX_flitToSink_1_0$wset_1__SEL_3 || MUX_flitToSink_1_0$wset_1__SEL_6: + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = ifcs_2_rspBack$D_OUT; + default: MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = + 6'b101010 /* unspecified value */ ; + endcase + end + always@(MUX_flitToSink_1_1_0$wset_1__SEL_1 or + MUX_flitToSink_1_1_0$wset_1__SEL_4 or + ifcs_0_1_rspBack$D_OUT or + MUX_flitToSink_1_1_0$wset_1__SEL_2 or + MUX_flitToSink_1_1_0$wset_1__SEL_5 or + ifcs_1_1_rspBack$D_OUT or + MUX_flitToSink_1_1_0$wset_1__SEL_3 or + MUX_flitToSink_1_1_0$wset_1__SEL_6 or ifcs_2_1_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_1_0$wset_1__SEL_1 || + MUX_flitToSink_1_1_0$wset_1__SEL_4: + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = + ifcs_0_1_rspBack$D_OUT; + MUX_flitToSink_1_1_0$wset_1__SEL_2 || + MUX_flitToSink_1_1_0$wset_1__SEL_5: + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = + ifcs_1_1_rspBack$D_OUT; + MUX_flitToSink_1_1_0$wset_1__SEL_3 || + MUX_flitToSink_1_1_0$wset_1__SEL_6: + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = + ifcs_2_1_rspBack$D_OUT; + default: MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + always@(MUX_flitToSink_1_1$wset_1__SEL_1 or + MUX_flitToSink_1_1$wset_1__SEL_4 or + ifcs_0_rspBack$D_OUT or + MUX_flitToSink_1_1$wset_1__SEL_2 or + MUX_flitToSink_1_1$wset_1__SEL_5 or + ifcs_1_rspBack$D_OUT or + MUX_flitToSink_1_1$wset_1__SEL_3 or + MUX_flitToSink_1_1$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1$wset_1__SEL_4: + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = ifcs_0_rspBack$D_OUT; + MUX_flitToSink_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1$wset_1__SEL_5: + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = ifcs_1_rspBack$D_OUT; + MUX_flitToSink_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1$wset_1__SEL_6: + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = ifcs_2_rspBack$D_OUT; + default: MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = + 6'b101010 /* unspecified value */ ; + endcase + end + always@(MUX_flitToSink_1_1_1_1$wset_1__SEL_1 or + MUX_flitToSink_1_1_1_1$wset_1__SEL_4 or + ifcs_0_1_rspBack$D_OUT or + MUX_flitToSink_1_1_1_1$wset_1__SEL_2 or + MUX_flitToSink_1_1_1_1$wset_1__SEL_5 or + ifcs_1_1_rspBack$D_OUT or + MUX_flitToSink_1_1_1_1$wset_1__SEL_3 or + MUX_flitToSink_1_1_1_1$wset_1__SEL_6 or ifcs_2_1_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_1_1_1$wset_1__SEL_1 || + MUX_flitToSink_1_1_1_1$wset_1__SEL_4: + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = + ifcs_0_1_rspBack$D_OUT; + MUX_flitToSink_1_1_1_1$wset_1__SEL_2 || + MUX_flitToSink_1_1_1_1$wset_1__SEL_5: + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = + ifcs_1_1_rspBack$D_OUT; + MUX_flitToSink_1_1_1_1$wset_1__SEL_3 || + MUX_flitToSink_1_1_1_1$wset_1__SEL_6: + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = + ifcs_2_1_rspBack$D_OUT; + default: MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_rg_hart0_reset_delay$write_1__VAL_1 = + rg_hart0_reset_delay - 8'd1 ; + assign MUX_split_0_flitLeft$write_1__VAL_1 = split_0_flitLeft - 8'd1 ; + assign MUX_split_1_flitLeft$write_1__VAL_1 = split_1_flitLeft - 8'd1 ; + assign MUX_split_2_flitLeft$write_1__VAL_1 = split_2_flitLeft - 8'd1 ; + assign MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_1 = + { tmp__h8358[39:3], + 4'd0, + tagController_tmp_awreqff$D_OUT[97:93], + 3'd1, + tagController_tmp_shimSlave_wff_rv$port1__read[1], + tagController_tmp_awreqff$D_OUT[14:11] < 4'd4, + 1'd0, + tagController_tmp_shimSlave_wff_rv$port1__read[9:2], + 8'd255, + tagController_tmp_shimSlave_wff_rv$port1__read[0], + tagController_tmp_shimSlave_wff_rv$port1__read[73:10], + tagController_tmp_awreqff$D_OUT[28:21] } ; + assign MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_2 = + { tagController_tmp_shimSlave_arff_rv$port1__read[68:29], + 1'b0, + tagController_tmp_shimSlave_arff_rv$port1__read[97:93], + 86'h02AAAAAAAAAAAAAAAAAAAA, + tagController_tmp_shimSlave_arff_rv$port1__read[14:11] < 4'd4, + 2'd0, + tagController_tmp_shimSlave_arff_rv$port1__read[23:18] } ; + assign MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_1 = + { tagController_tmp_shimMaster_bff_rv$port1__read[7:2], + 71'h0CAAAAAAAAAAAAAAAA } ; + assign MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_2 = + { tagController_tmp_shimMaster_rff_rv$port1__read[72:67], + 4'd0, + tagController_tmp_shimMaster_rff_rv$port1__read[0], + 1'd0, + tagController_tmp_shimMaster_rff_rv$port1__read[67:3] } ; + + // inlined wires + assign tmp0_aw_dwReady$whas = + proc$master1_awvalid && CAN_FIRE_RL_merged_0_genFirst ; + assign tmp0_w_dwReady$whas = + proc$master1_wvalid && msNoSynth_0_w_dwReady$whas ; + assign tmp0_b_buffer_enqw$wget = + msNoSynth_0_b_buffer_ff$EMPTY_N ? + msNoSynth_0_b_buffer_ff$D_OUT : + msNoSynth_0_b_buffer_enqw$wget ; + assign tmp0_b_buffer_enqw$whas = + WILL_FIRE_RL_msNoSynth_0_b_forwardFlit && + tmp0_b_buffer_ff$FULL_N ; + assign tmp0_ar_dwReady$whas = + proc$master1_arvalid && msNoSynth_0_ar_dwReady$whas ; + assign tmp0_r_buffer_enqw$wget = + { x_rid__h25036, + x_rdata__h25037, + msNoSynth_0_r_buffer_ff$EMPTY_N ? + msNoSynth_0_r_buffer_ff$D_OUT[3:2] : + msNoSynth_0_r_buffer_enqw$wget[3:2], + msNoSynth_0_r_buffer_ff$EMPTY_N ? + msNoSynth_0_r_buffer_ff$D_OUT[1] : + msNoSynth_0_r_buffer_enqw$wget[1], + 1'd0 } ; + assign tmp0_r_buffer_enqw$whas = + WILL_FIRE_RL_msNoSynth_0_r_forwardFlit && + tmp0_r_buffer_ff$FULL_N ; + assign ug_uncached_mem_shim_master_u_aw_peekWire$wget = + { 1'd0, uncached_mem_shim_awff$D_OUT } ; + assign ug_uncached_mem_shim_master_u_b_putWire$wget = + { cpu_dmem_master_bid, cpu_dmem_master_bresp } ; + assign ug_uncached_mem_shim_master_u_b_putWire$whas = + cpu_dmem_master_bvalid && uncached_mem_shim_bff$FULL_N ; + assign ug_uncached_mem_shim_master_u_ar_peekWire$wget = + { 1'd0, uncached_mem_shim_arff$D_OUT } ; + assign ug_uncached_mem_shim_master_u_r_putWire$wget = + { cpu_dmem_master_rid, + cpu_dmem_master_rdata, + cpu_dmem_master_rresp, + cpu_dmem_master_rlast } ; + assign ug_uncached_mem_shim_master_u_r_putWire$whas = + cpu_dmem_master_rvalid && uncached_mem_shim_rff$FULL_N ; + assign tagController_tmp_ug_slave_u_aw_putWire$wget = + { proc$master0_awid, + proc$master0_awaddr, + proc$master0_awlen, + proc$master0_awsize, + proc$master0_awburst, + proc$master0_awlock, + proc$master0_awcache, + proc$master0_awprot, + proc$master0_awqos, + proc$master0_awregion } ; + assign tagController_tmp_ug_slave_u_w_putWire$wget = + { proc$master0_wdata, + proc$master0_wstrb, + proc$master0_wlast, + proc$master0_wuser } ; + assign tagController_tmp_ug_slave_u_ar_putWire$wget = + { proc$master0_arid, + proc$master0_araddr, + proc$master0_arlen, + proc$master0_arsize, + proc$master0_arburst, + proc$master0_arlock, + proc$master0_arcache, + proc$master0_arprot, + proc$master0_arqos, + proc$master0_arregion } ; + assign tagController_tmp_ug_master_u_b_putWire$wget = + { cpu_imem_master_bid, cpu_imem_master_bresp } ; + assign tagController_tmp_ug_master_u_b_putWire$whas = + cpu_imem_master_bvalid && + !tagController_tmp_shimMaster_bff_rv[8] ; + assign tagController_tmp_ug_master_u_r_putWire$wget = + { cpu_imem_master_rid, + cpu_imem_master_rdata, + cpu_imem_master_rresp, + cpu_imem_master_rlast } ; + assign tagController_tmp_ug_master_u_r_putWire$whas = + cpu_imem_master_rvalid && + !tagController_tmp_shimMaster_rff_rv[73] ; + assign tmp2_b_buffer_enqw$wget = + tagController_tmp_shimSlave_bff_rv$port1__read[6:0] ; + assign tmp2_r_buffer_enqw$wget = + tagController_tmp_shimSlave_rff_rv$port1__read[72:0] ; + assign msNoSynth_0_w_dwReady$whas = + WILL_FIRE_RL_merged_0_genOther || + WILL_FIRE_RL_merged_0_genFirst ; + assign msNoSynth_0_b_buffer_enqw$wget = + WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ? + ifcs_0_noRouteRsp$D_OUT : + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 ; + assign msNoSynth_0_b_buffer_enqw$whas = + WILL_FIRE_RL_ifcs_0_drainNoRouteResponse || + WILL_FIRE_RL_ifcs_0_forwardRsp ; + assign msNoSynth_0_ar_dwReady$whas = + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp && + x_port1__read__h73054 == 9'd1 || + WILL_FIRE_RL_ifcs_0_1_drainFlits || + WILL_FIRE_RL_ifcs_0_1_followFlits || + WILL_FIRE_RL_ifcs_0_1_firstFlit ; + assign msNoSynth_0_r_buffer_enqw$wget = + WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ? + ifcs_0_1_noRouteRsp$D_OUT : + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 ; + assign msNoSynth_0_r_buffer_enqw$whas = + WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse || + WILL_FIRE_RL_ifcs_0_1_forwardRsp ; + assign msNoSynth_1_w_dwReady$whas = + WILL_FIRE_RL_merged_1_genOther || + WILL_FIRE_RL_merged_1_genFirst ; + assign msNoSynth_1_b_buffer_enqw$wget = + WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ? + ifcs_1_noRouteRsp$D_OUT : + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 ; + assign msNoSynth_1_b_buffer_enqw$whas = + WILL_FIRE_RL_ifcs_1_drainNoRouteResponse || + WILL_FIRE_RL_ifcs_1_forwardRsp ; + assign msNoSynth_1_ar_dwReady$whas = + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp && + x_port1__read__h75518 == 9'd1 || + WILL_FIRE_RL_ifcs_1_1_drainFlits || + WILL_FIRE_RL_ifcs_1_1_followFlits || + WILL_FIRE_RL_ifcs_1_1_firstFlit ; + assign msNoSynth_1_r_buffer_enqw$wget = + WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ? + ifcs_1_1_noRouteRsp$D_OUT : + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 ; + assign msNoSynth_1_r_buffer_enqw$whas = + WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse || + WILL_FIRE_RL_ifcs_1_1_forwardRsp ; + assign ssNoSynth_0_w_buffer_enqw$whas = + WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] || + WILL_FIRE_RL_split_0_putFirst && !split_0_doPut$wget[172] ; + assign ssNoSynth_0_b_dwReady$whas = + WILL_FIRE_RL_ifcs_0_followFlits_1 || + WILL_FIRE_RL_ifcs_0_firstFlit_1 ; + assign ssNoSynth_0_ar_buffer_enqw$wget = + (MUX_flitToSink_1_0_1$wset_1__SEL_1 || + MUX_flitToSink_1_0_1$wset_1__SEL_3) ? + ifcs_0_1_innerReq$D_OUT : + ifcs_1_1_innerReq$D_OUT ; + assign ssNoSynth_0_r_dwReady$whas = + WILL_FIRE_RL_ifcs_0_1_followFlits_1 || + WILL_FIRE_RL_ifcs_0_1_firstFlit_1 ; + assign ssNoSynth_1_aw_buffer_enqw$wget = split_1_doPut$wget[171:74] ; + assign ssNoSynth_1_w_buffer_enqw$wget = split_1_doPut$wget[73:0] ; + assign ssNoSynth_1_w_buffer_enqw$whas = + WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] || + WILL_FIRE_RL_split_1_putFirst && !split_1_doPut$wget[172] ; + assign ssNoSynth_1_b_dwReady$whas = + WILL_FIRE_RL_ifcs_1_followFlits_1 || + WILL_FIRE_RL_ifcs_1_firstFlit_1 ; + assign ssNoSynth_1_ar_buffer_enqw$wget = + (MUX_flitToSink_1_1_1$wset_1__SEL_1 || + MUX_flitToSink_1_1_1$wset_1__SEL_3) ? + ifcs_0_1_innerReq$D_OUT : + ifcs_1_1_innerReq$D_OUT ; + assign ssNoSynth_1_r_dwReady$whas = + WILL_FIRE_RL_ifcs_1_1_followFlits_1 || + WILL_FIRE_RL_ifcs_1_1_firstFlit_1 ; + assign ssNoSynth_2_aw_buffer_enqw$wget = split_2_doPut$wget[171:74] ; + assign ssNoSynth_2_w_buffer_enqw$wget = split_2_doPut$wget[73:0] ; + assign ssNoSynth_2_w_buffer_enqw$whas = + WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] || + WILL_FIRE_RL_split_2_putFirst && !split_2_doPut$wget[172] ; + assign ssNoSynth_2_b_dwReady$whas = + WILL_FIRE_RL_ifcs_2_followFlits || + WILL_FIRE_RL_ifcs_2_firstFlit ; + assign ssNoSynth_2_ar_buffer_enqw$wget = + (MUX_flitToSink_1_2$wset_1__SEL_1 || + MUX_flitToSink_1_2$wset_1__SEL_3) ? + ifcs_0_1_innerReq$D_OUT : + ifcs_1_1_innerReq$D_OUT ; + assign ssNoSynth_2_r_dwReady$whas = + WILL_FIRE_RL_ifcs_2_1_followFlits || + WILL_FIRE_RL_ifcs_2_1_firstFlit ; + assign split_0_doPut$wget = + (MUX_flitToSink_0$wset_1__SEL_1 || + MUX_flitToSink_0$wset_1__SEL_3) ? + ifcs_0_innerReq$D_OUT : + ifcs_1_innerReq$D_OUT ; + assign split_1_doPut$wget = + (MUX_flitToSink_1$wset_1__SEL_1 || + MUX_flitToSink_1$wset_1__SEL_3) ? + ifcs_0_innerReq$D_OUT : + ifcs_1_innerReq$D_OUT ; + assign split_2_doPut$wget = + (MUX_flitToSink_2$wset_1__SEL_1 || + MUX_flitToSink_2$wset_1__SEL_3) ? + ifcs_0_innerReq$D_OUT : + ifcs_1_innerReq$D_OUT ; + assign reqWires_0$wget = + (!ifcs_0_innerRoute$D_OUT[0] || + !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1435) ? + IF_NOT_ifcs_0_innerRoute_first__443_BIT_1_452__ETC___d1465 : + ifcs_0_innerRoute$D_OUT[0] ; + assign reqWires_1$wget = + (!ifcs_1_innerRoute$D_OUT[0] || + !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1435) ? + IF_NOT_ifcs_1_innerRoute_first__472_BIT_1_476__ETC___d1481 : + ifcs_1_innerRoute$D_OUT[0] ; + assign flitToSink_0$whas = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[0] || + WILL_FIRE_RL_burst_1 && ifcs_1_innerRoute$D_OUT[0] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[0] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + ifcs_1_innerRoute$D_OUT[0] ; + assign flitToSink_1$whas = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[1] || + WILL_FIRE_RL_burst_1 && ifcs_1_innerRoute$D_OUT[1] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[1] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + ifcs_1_innerRoute$D_OUT[1] ; + assign flitToSink_2$whas = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[2] || + WILL_FIRE_RL_burst_1 && ifcs_1_innerRoute$D_OUT[2] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[2] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + ifcs_1_innerRoute$D_OUT[2] ; + assign reqWires_1_0$wget = + (!ifcs_0_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_0_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_0_routeBack$D_OUT[0] ; + assign reqWires_1_1$wget = + (!ifcs_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_1_routeBack$D_OUT[0] ; + assign reqWires_1_2$wget = + (!ifcs_2_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_2_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_2_routeBack$D_OUT[0] ; + assign flitToSink_1_0$whas = + WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[0] || + WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + ifcs_0_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + ifcs_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + ifcs_2_routeBack$D_OUT[0] ; + assign flitToSink_1_1$whas = + WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[1] || + WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + ifcs_0_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + ifcs_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + ifcs_2_routeBack$D_OUT[1] ; + assign reqWires_1_0_1$wget = + (!ifcs_0_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_ar_buffer_ff$FULL_N) ? + IF_NOT_ifcs_0_1_innerRoute_first__096_BIT_1_10_ETC___d2118 : + ifcs_0_1_innerRoute$D_OUT[0] ; + assign reqWires_1_1_1$wget = + (!ifcs_1_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_ar_buffer_ff$FULL_N) ? + IF_NOT_ifcs_1_1_innerRoute_first__125_BIT_1_12_ETC___d2134 : + ifcs_1_1_innerRoute$D_OUT[0] ; + assign flitToSink_1_0_1$whas = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[0] || + WILL_FIRE_RL_burst_6 && ifcs_1_1_innerRoute$D_OUT[0] || + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[0] || + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + ifcs_1_1_innerRoute$D_OUT[0] ; + assign flitToSink_1_1_1$whas = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[1] || + WILL_FIRE_RL_burst_6 && ifcs_1_1_innerRoute$D_OUT[1] || + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[1] || + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + ifcs_1_1_innerRoute$D_OUT[1] ; + assign flitToSink_1_2$whas = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[2] || + WILL_FIRE_RL_burst_6 && ifcs_1_1_innerRoute$D_OUT[2] || + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[2] || + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + ifcs_1_1_innerRoute$D_OUT[2] ; + assign reqWires_1_1_0$wget = + (!ifcs_0_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_0_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_0_1_routeBack$D_OUT[0] ; + assign reqWires_1_1_1_1$wget = + (!ifcs_1_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_1_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_1_1_routeBack$D_OUT[0] ; + assign reqWires_1_1_2$wget = + (!ifcs_2_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_2_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_2_1_routeBack$D_OUT[0] ; + assign flitToSink_1_1_0$whas = + WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_routeBack$D_OUT[0] ; + assign flitToSink_1_1_1_1$whas = + WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_routeBack$D_OUT[1] ; + assign ug_uncached_mem_shim_master_u_aw_dropWire$whas = + uncached_mem_shim_awff$EMPTY_N && cpu_dmem_master_awready ; + assign ug_uncached_mem_shim_master_u_w_dropWire$whas = + uncached_mem_shim_wff$EMPTY_N && cpu_dmem_master_wready ; + assign ug_uncached_mem_shim_master_u_ar_dropWire$whas = + uncached_mem_shim_arff$EMPTY_N && cpu_dmem_master_arready ; + assign tagController_tmp_ug_master_u_aw_dropWire$whas = + tagController_tmp_shimMaster_awff_rv$port1__read[99] && + cpu_imem_master_awready ; + assign tagController_tmp_ug_master_u_w_dropWire$whas = + tagController_tmp_shimMaster_wff_rv$port1__read[73] && + cpu_imem_master_wready ; + assign tagController_tmp_ug_master_u_ar_dropWire$whas = + tagController_tmp_shimMaster_arff_rv$port1__read[99] && + cpu_imem_master_arready ; + assign merged_0_doDrop$whas = + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp || + WILL_FIRE_RL_ifcs_0_drainFlits || + WILL_FIRE_RL_ifcs_0_followFlits || + WILL_FIRE_RL_ifcs_0_firstFlit ; + assign merged_1_doDrop$whas = + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp || + WILL_FIRE_RL_ifcs_1_drainFlits || + WILL_FIRE_RL_ifcs_1_followFlits || + WILL_FIRE_RL_ifcs_1_firstFlit ; + assign sourceSelect_1_0$whas = + WILL_FIRE_RL_arbitrate_1 && + IF_SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_ETC___d1727 ; + assign sourceSelect_1_1$whas = + WILL_FIRE_RL_arbitrate_1 && + IF_SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_ETC___d1733 ; + assign sourceSelect_1_2$whas = + WILL_FIRE_RL_arbitrate_1 && + IF_SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_ETC___d1739 ; + assign sourceSelect_1_0_1$whas = + WILL_FIRE_RL_arbitrate_2 && + IF_SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_1_ETC___d2170 ; + assign sourceSelect_1_1_1$whas = + WILL_FIRE_RL_arbitrate_2 && + IF_SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_1_ETC___d2174 ; + assign tagController_tmp_shimSlave_awff_rv$port0__write_1 = + { 1'd1, tagController_tmp_ug_slave_u_aw_putWire$wget } ; + assign tagController_tmp_shimSlave_awff_rv$port1__read = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut ? + tagController_tmp_shimSlave_awff_rv$port0__write_1 : + tagController_tmp_shimSlave_awff_rv ; + assign tagController_tmp_shimSlave_awff_rv$port2__read = + CAN_FIRE_RL_tagController_tmp_getCacheAW ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + tagController_tmp_shimSlave_awff_rv$port1__read ; + assign tagController_tmp_shimSlave_awff_rv$port3__read = + (!tagController_tmp_reset_done) ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + tagController_tmp_shimSlave_awff_rv$port2__read ; + assign tagController_tmp_shimSlave_wff_rv$port0__write_1 = + { 1'd1, tagController_tmp_ug_slave_u_w_putWire$wget } ; + assign tagController_tmp_shimSlave_wff_rv$port1__read = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut ? + tagController_tmp_shimSlave_wff_rv$port0__write_1 : + tagController_tmp_shimSlave_wff_rv ; + assign tagController_tmp_shimSlave_wff_rv$port2__read = + WILL_FIRE_RL_tagController_tmp_passCacheWrite ? + 75'h2AAAAAAAAAAAAAAAAAA : + tagController_tmp_shimSlave_wff_rv$port1__read ; + assign tagController_tmp_shimSlave_wff_rv$port3__read = + (!tagController_tmp_reset_done) ? + 75'h2AAAAAAAAAAAAAAAAAA : + tagController_tmp_shimSlave_wff_rv$port2__read ; + assign tagController_tmp_shimSlave_bff_rv$EN_port0__write = + WILL_FIRE_RL_tagController_tmp_passCacheResponse && + tagController_tmp_tagCon$cache_response_get[68:67] != 2'd0 ; + assign tagController_tmp_shimSlave_bff_rv$port0__write_1 = + { 1'd1, + (tagController_tmp_tagCon$cache_response_get[68:67] == 2'd1) ? + tagController_tmp_tagCon$cache_response_get[75:71] : + 5'd0, + 2'd0 } ; + assign tagController_tmp_shimSlave_bff_rv$port1__read = + tagController_tmp_shimSlave_bff_rv$EN_port0__write ? + tagController_tmp_shimSlave_bff_rv$port0__write_1 : + tagController_tmp_shimSlave_bff_rv ; + assign tagController_tmp_shimSlave_bff_rv$port2__read = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop ? + 8'd42 : + tagController_tmp_shimSlave_bff_rv$port1__read ; + assign tagController_tmp_shimSlave_bff_rv$port3__read = + (!tagController_tmp_reset_done) ? + 8'd42 : + tagController_tmp_shimSlave_bff_rv$port2__read ; + assign tagController_tmp_shimSlave_arff_rv$port0__write_1 = + { 1'd1, tagController_tmp_ug_slave_u_ar_putWire$wget } ; + assign tagController_tmp_shimSlave_arff_rv$port1__read = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut ? + tagController_tmp_shimSlave_arff_rv$port0__write_1 : + tagController_tmp_shimSlave_arff_rv ; + assign tagController_tmp_shimSlave_arff_rv$port2__read = + CAN_FIRE_RL_tagController_tmp_passCacheRead ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + tagController_tmp_shimSlave_arff_rv$port1__read ; + assign tagController_tmp_shimSlave_arff_rv$port3__read = + (!tagController_tmp_reset_done) ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + tagController_tmp_shimSlave_arff_rv$port2__read ; + assign tagController_tmp_shimSlave_rff_rv$EN_port0__write = + WILL_FIRE_RL_tagController_tmp_passCacheResponse && + tagController_tmp_tagCon$cache_response_get[68:67] == 2'd0 ; + assign tagController_tmp_shimSlave_rff_rv$port0__write_1 = + { 1'd1, + tagController_tmp_tagCon$cache_response_get[75:71], + tagController_tmp_tagCon$cache_response_get[63:0], + 2'd0, + tagController_tmp_tagCon$cache_response_get[66], + tagController_tmp_tagCon$cache_response_get[64] } ; + assign tagController_tmp_shimSlave_rff_rv$port1__read = + tagController_tmp_shimSlave_rff_rv$EN_port0__write ? + tagController_tmp_shimSlave_rff_rv$port0__write_1 : + tagController_tmp_shimSlave_rff_rv ; + assign tagController_tmp_shimSlave_rff_rv$port2__read = + CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop ? + 74'h0AAAAAAAAAAAAAAAAAA : + tagController_tmp_shimSlave_rff_rv$port1__read ; + assign tagController_tmp_shimSlave_rff_rv$port3__read = + (!tagController_tmp_reset_done) ? + 74'h0AAAAAAAAAAAAAAAAAA : + tagController_tmp_shimSlave_rff_rv$port2__read ; + assign tagController_tmp_shimMaster_awff_rv$EN_port0__write = + WILL_FIRE_RL_tagController_tmp_passMemoryRequest && + tagController_tmp_tagCon$memory_request_get[93:92] == 2'd1 && + !tagController_tmp_doneSendingAW ; + assign tagController_tmp_shimMaster_awff_rv$port0__write_1 = + { 1'd1, + tagController_tmp_tagCon$memory_request_get[100:95], + aw_awaddr__h10800, + tagController_tmp_tagCon$memory_request_get[7:0], + aw_awsize_val__h12539, + 3'd2, + x__h14205, + 11'd0 } ; + assign tagController_tmp_shimMaster_awff_rv$port1__read = + tagController_tmp_shimMaster_awff_rv$EN_port0__write ? + tagController_tmp_shimMaster_awff_rv$port0__write_1 : + tagController_tmp_shimMaster_awff_rv ; + assign tagController_tmp_shimMaster_awff_rv$port2__read = + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop ? + 100'h2AAAAAAAAAAAAAAAAAAAAAAAA : + tagController_tmp_shimMaster_awff_rv$port1__read ; + assign tagController_tmp_shimMaster_awff_rv$port3__read = + (!tagController_tmp_reset_done) ? + 100'h2AAAAAAAAAAAAAAAAAAAAAAAA : + tagController_tmp_shimMaster_awff_rv$port2__read ; + assign tagController_tmp_shimMaster_wff_rv$EN_port0__write = + WILL_FIRE_RL_tagController_tmp_passMemoryRequest && + tagController_tmp_tagCon$memory_request_get[93:92] == 2'd1 ; + assign tagController_tmp_shimMaster_wff_rv$port0__write_1 = + { 1'd1, + tagController_tmp_tagCon$memory_request_get[71:8], + tagController_tmp_tagCon$memory_request_get[88:81], + tagController_tmp_tagCon$memory_request_get[91] } ; + assign tagController_tmp_shimMaster_wff_rv$port1__read = + tagController_tmp_shimMaster_wff_rv$EN_port0__write ? + tagController_tmp_shimMaster_wff_rv$port0__write_1 : + tagController_tmp_shimMaster_wff_rv ; + assign tagController_tmp_shimMaster_wff_rv$port2__read = + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop ? + 74'h0AAAAAAAAAAAAAAAAAA : + tagController_tmp_shimMaster_wff_rv$port1__read ; + assign tagController_tmp_shimMaster_wff_rv$port3__read = + (!tagController_tmp_reset_done) ? + 74'h0AAAAAAAAAAAAAAAAAA : + tagController_tmp_shimMaster_wff_rv$port2__read ; + assign tagController_tmp_shimMaster_bff_rv$port0__write_1 = + { 1'd1, tagController_tmp_ug_master_u_b_putWire$wget } ; + assign tagController_tmp_shimMaster_bff_rv$port1__read = + CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut ? + tagController_tmp_shimMaster_bff_rv$port0__write_1 : + tagController_tmp_shimMaster_bff_rv ; + assign tagController_tmp_shimMaster_bff_rv$port2__read = + WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite ? + 9'd170 : + tagController_tmp_shimMaster_bff_rv$port1__read ; + assign tagController_tmp_shimMaster_bff_rv$port3__read = + (!tagController_tmp_reset_done) ? + 9'd170 : + tagController_tmp_shimMaster_bff_rv$port2__read ; + assign tagController_tmp_shimMaster_arff_rv$EN_port0__write = + WILL_FIRE_RL_tagController_tmp_passMemoryRequest && + tagController_tmp_tagCon$memory_request_get[93:92] != 2'd1 ; + assign tagController_tmp_shimMaster_arff_rv$port0__write_1 = + { 1'd1, + v_arid__h15548, + v_araddr__h15549, + v_arlen__h15550, + v_arsize_val__h15595, + 3'd2, + x__h15613, + 11'd0 } ; + assign tagController_tmp_shimMaster_arff_rv$port1__read = + tagController_tmp_shimMaster_arff_rv$EN_port0__write ? + tagController_tmp_shimMaster_arff_rv$port0__write_1 : + tagController_tmp_shimMaster_arff_rv ; + assign tagController_tmp_shimMaster_arff_rv$port2__read = + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop ? + 100'h2AAAAAAAAAAAAAAAAAAAAAAAA : + tagController_tmp_shimMaster_arff_rv$port1__read ; + assign tagController_tmp_shimMaster_arff_rv$port3__read = + (!tagController_tmp_reset_done) ? + 100'h2AAAAAAAAAAAAAAAAAAAAAAAA : + tagController_tmp_shimMaster_arff_rv$port2__read ; + assign tagController_tmp_shimMaster_rff_rv$port0__write_1 = + { 1'd1, tagController_tmp_ug_master_u_r_putWire$wget } ; + assign tagController_tmp_shimMaster_rff_rv$port1__read = + CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut ? + tagController_tmp_shimMaster_rff_rv$port0__write_1 : + tagController_tmp_shimMaster_rff_rv ; + assign tagController_tmp_shimMaster_rff_rv$port2__read = + CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead ? + 74'h0AAAAAAAAAAAAAAAAAA : + tagController_tmp_shimMaster_rff_rv$port1__read ; + assign tagController_tmp_shimMaster_rff_rv$port3__read = + (!tagController_tmp_reset_done) ? + 74'h0AAAAAAAAAAAAAAAAAA : + tagController_tmp_shimMaster_rff_rv$port2__read ; + assign ifcs_0_noRoute_inner_currentReq$EN_port0__write = + WILL_FIRE_RL_ifcs_0_nonRoutableFlit && + merged_0_flitLeft == 8'd0 ; + assign ifcs_0_noRoute_inner_currentReq$port0__write_1 = + { proc$master1_awid, + proc$master1_awaddr, + proc$master1_awlen, + proc$master1_awsize, + proc$master1_awburst, + proc$master1_awlock, + proc$master1_awcache, + proc$master1_awprot, + proc$master1_awqos, + proc$master1_awregion } ; + assign ifcs_0_noRoute_inner_currentReq$port1__read = + ifcs_0_noRoute_inner_currentReq$EN_port0__write ? + ifcs_0_noRoute_inner_currentReq$port0__write_1 : + ifcs_0_noRoute_inner_currentReq ; + assign ifcs_0_noRoute_inner_pendingReq$EN_port0__write = + WILL_FIRE_RL_ifcs_0_nonRoutableFlit && + merged_0_flitLeft == 8'd0 ; + assign ifcs_0_noRoute_inner_pendingReq$port1__read = + ifcs_0_noRoute_inner_pendingReq$EN_port0__write || + ifcs_0_noRoute_inner_pendingReq ; + assign ifcs_0_noRoute_inner_pendingReq$port2__read = + !CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp && + ifcs_0_noRoute_inner_pendingReq$port1__read ; + assign ifcs_1_noRoute_inner_currentReq$EN_port0__write = + WILL_FIRE_RL_ifcs_1_nonRoutableFlit && + merged_1_flitLeft == 8'd0 ; + assign ifcs_1_noRoute_inner_currentReq$port0__write_1 = + { debug_module$master_awid, + debug_module$master_awaddr, + debug_module$master_awlen, + debug_module$master_awsize, + debug_module$master_awburst, + debug_module$master_awlock, + debug_module$master_awcache, + debug_module$master_awprot, + debug_module$master_awqos, + debug_module$master_awregion } ; + assign ifcs_1_noRoute_inner_currentReq$port1__read = + ifcs_1_noRoute_inner_currentReq$EN_port0__write ? + ifcs_1_noRoute_inner_currentReq$port0__write_1 : + ifcs_1_noRoute_inner_currentReq ; + assign ifcs_1_noRoute_inner_pendingReq$EN_port0__write = + WILL_FIRE_RL_ifcs_1_nonRoutableFlit && + merged_1_flitLeft == 8'd0 ; + assign ifcs_1_noRoute_inner_pendingReq$port1__read = + ifcs_1_noRoute_inner_pendingReq$EN_port0__write || + ifcs_1_noRoute_inner_pendingReq ; + assign ifcs_1_noRoute_inner_pendingReq$port2__read = + !CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp && + ifcs_1_noRoute_inner_pendingReq$port1__read ; + assign ifcs_0_1_noRoute_currentReq$port0__write_1 = + { proc$master1_arid, + proc$master1_araddr, + proc$master1_arlen, + proc$master1_arsize, + proc$master1_arburst, + proc$master1_arlock, + proc$master1_arcache, + proc$master1_arprot, + proc$master1_arqos, + proc$master1_arregion } ; + assign ifcs_0_1_noRoute_currentReq$port1__read = + CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? + ifcs_0_1_noRoute_currentReq$port0__write_1 : + ifcs_0_1_noRoute_currentReq ; + assign ifcs_0_1_noRoute_flitCount$port0__write_1 = + { 1'd0, proc$master1_arlen } + 9'd1 ; + assign ifcs_0_1_noRoute_flitCount$port1__write_1 = + x_port1__read__h73054 - 9'd1 ; + assign ifcs_0_1_noRoute_flitCount$port2__read = + CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ? + ifcs_0_1_noRoute_flitCount$port1__write_1 : + x_port1__read__h73054 ; + assign ifcs_1_1_noRoute_currentReq$port0__write_1 = + { debug_module$master_arid, + debug_module$master_araddr, + debug_module$master_arlen, + debug_module$master_arsize, + debug_module$master_arburst, + debug_module$master_arlock, + debug_module$master_arcache, + debug_module$master_arprot, + debug_module$master_arqos, + debug_module$master_arregion } ; + assign ifcs_1_1_noRoute_currentReq$port1__read = + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? + ifcs_1_1_noRoute_currentReq$port0__write_1 : + ifcs_1_1_noRoute_currentReq ; + assign ifcs_1_1_noRoute_flitCount$port0__write_1 = + { 1'd0, debug_module$master_arlen } + 9'd1 ; + assign ifcs_1_1_noRoute_flitCount$port1__write_1 = + x_port1__read__h75518 - 9'd1 ; + assign ifcs_1_1_noRoute_flitCount$port2__read = + CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ? + ifcs_1_1_noRoute_flitCount$port1__write_1 : + x_port1__read__h75518 ; + + // register activeSource_0 + assign activeSource_0$D_IN = + MUX_activeSource_0$write_1__SEL_1 ? + MUX_activeSource_0$write_1__VAL_1 : + MUX_activeSource_0$write_1__VAL_1 ; + assign activeSource_0$EN = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + !ifcs_0_innerReq$D_OUT[1] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + !ifcs_1_innerReq$D_OUT[1] ; + + // register activeSource_1 + assign activeSource_1$D_IN = + MUX_activeSource_0$write_1__SEL_1 ? + MUX_activeSource_1$write_1__VAL_1 : + MUX_activeSource_1$write_1__VAL_1 ; + assign activeSource_1$EN = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + !ifcs_0_innerReq$D_OUT[1] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + !ifcs_1_innerReq$D_OUT[1] ; + + // register activeSource_1_0 + assign activeSource_1_0$D_IN = 1'b0 ; + assign activeSource_1_0$EN = 1'b0 ; + + // register activeSource_1_0_1 + assign activeSource_1_0_1$D_IN = 1'b0 ; + assign activeSource_1_0_1$EN = 1'b0 ; + + // register activeSource_1_1 + assign activeSource_1_1$D_IN = 1'b0 ; + assign activeSource_1_1$EN = 1'b0 ; + + // register activeSource_1_1_0 + always@(MUX_activeSource_1_1_0$write_1__SEL_1 or + MUX_activeSource_1_1_0$write_1__VAL_1 or + MUX_activeSource_1_1_0$write_1__SEL_2 or + MUX_activeSource_1_1_0$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_activeSource_1_1_0$write_1__SEL_1: + activeSource_1_1_0$D_IN = MUX_activeSource_1_1_0$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_2: + activeSource_1_1_0$D_IN = MUX_activeSource_1_1_0$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_3: + activeSource_1_1_0$D_IN = MUX_activeSource_1_1_0$write_1__VAL_1; + default: activeSource_1_1_0$D_IN = 1'b0 /* unspecified value */ ; + endcase + end + assign activeSource_1_1_0$EN = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[1] ; + + // register activeSource_1_1_1 + assign activeSource_1_1_1$D_IN = 1'b0 ; + assign activeSource_1_1_1$EN = 1'b0 ; + + // register activeSource_1_1_1_1 + always@(MUX_activeSource_1_1_0$write_1__SEL_1 or + MUX_activeSource_1_1_1_1$write_1__VAL_1 or + MUX_activeSource_1_1_0$write_1__SEL_2 or + MUX_activeSource_1_1_0$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_activeSource_1_1_0$write_1__SEL_1: + activeSource_1_1_1_1$D_IN = MUX_activeSource_1_1_1_1$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_2: + activeSource_1_1_1_1$D_IN = MUX_activeSource_1_1_1_1$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_3: + activeSource_1_1_1_1$D_IN = MUX_activeSource_1_1_1_1$write_1__VAL_1; + default: activeSource_1_1_1_1$D_IN = 1'b0 /* unspecified value */ ; + endcase + end + assign activeSource_1_1_1_1$EN = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[1] ; + + // register activeSource_1_1_2 + always@(MUX_activeSource_1_1_0$write_1__SEL_1 or + MUX_activeSource_1_1_2$write_1__VAL_1 or + MUX_activeSource_1_1_0$write_1__SEL_2 or + MUX_activeSource_1_1_0$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_activeSource_1_1_0$write_1__SEL_1: + activeSource_1_1_2$D_IN = MUX_activeSource_1_1_2$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_2: + activeSource_1_1_2$D_IN = MUX_activeSource_1_1_2$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_3: + activeSource_1_1_2$D_IN = MUX_activeSource_1_1_2$write_1__VAL_1; + default: activeSource_1_1_2$D_IN = 1'b0 /* unspecified value */ ; + endcase + end + assign activeSource_1_1_2$EN = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[1] ; + + // register activeSource_1_2 + assign activeSource_1_2$D_IN = 1'b0 ; + assign activeSource_1_2$EN = 1'b0 ; + + // register arbiter_1_1_firstHot + assign arbiter_1_1_firstHot$D_IN = + IF_SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_3_ETC___d2382 ; + assign arbiter_1_1_firstHot$EN = CAN_FIRE_RL_arbitrate_3 ; + + // register arbiter_1_1_lastSelect + assign arbiter_1_1_lastSelect$D_IN = + IF_SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_3_ETC___d2370 ; + assign arbiter_1_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_3 ; + + // register arbiter_1_1_lastSelect_1 + assign arbiter_1_1_lastSelect_1$D_IN = + IF_SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_3_ETC___d2376 ; + assign arbiter_1_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_3 ; + + // register arbiter_1_firstHot + assign arbiter_1_firstHot$D_IN = + IF_SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_ETC___d1739 ; + assign arbiter_1_firstHot$EN = CAN_FIRE_RL_arbitrate_1 ; + + // register arbiter_1_firstHot_1 + assign arbiter_1_firstHot_1$D_IN = + IF_SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_1_ETC___d2174 ; + assign arbiter_1_firstHot_1$EN = CAN_FIRE_RL_arbitrate_2 ; + + // register arbiter_1_lastSelect + assign arbiter_1_lastSelect$D_IN = + IF_SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_ETC___d1727 ; + assign arbiter_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_1 ; + + // register arbiter_1_lastSelect_1 + assign arbiter_1_lastSelect_1$D_IN = + IF_SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_ETC___d1733 ; + assign arbiter_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_1 ; + + // register arbiter_1_lastSelect_2 + assign arbiter_1_lastSelect_2$D_IN = + IF_SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_1_ETC___d2170 ; + assign arbiter_1_lastSelect_2$EN = CAN_FIRE_RL_arbitrate_2 ; + + // register arbiter_firstHot + assign arbiter_firstHot$D_IN = + IF_SEXT_arbiter_lastSelect_493_494_BIT_0_495_A_ETC___d1521 ; + assign arbiter_firstHot$EN = CAN_FIRE_RL_arbitrate ; + + // register arbiter_lastSelect + assign arbiter_lastSelect$D_IN = + IF_SEXT_arbiter_lastSelect_493_494_BIT_0_495_A_ETC___d1517 ; + assign arbiter_lastSelect$EN = CAN_FIRE_RL_arbitrate ; + + // register ifcs_0_1_noRoute_currentReq + assign ifcs_0_1_noRoute_currentReq$D_IN = + ifcs_0_1_noRoute_currentReq$port1__read ; + assign ifcs_0_1_noRoute_currentReq$EN = 1'b1 ; + + // register ifcs_0_1_noRoute_flitCount + assign ifcs_0_1_noRoute_flitCount$D_IN = + ifcs_0_1_noRoute_flitCount$port2__read ; + assign ifcs_0_1_noRoute_flitCount$EN = 1'b1 ; + + // register ifcs_0_1_state + assign ifcs_0_1_state$D_IN = 2'd0 ; + assign ifcs_0_1_state$EN = + WILL_FIRE_RL_ifcs_0_1_drainFlits || + WILL_FIRE_RL_ifcs_0_1_followFlits ; + + // register ifcs_0_1_state_1 + assign ifcs_0_1_state_1$D_IN = !MUX_ifcs_0_1_state_1$write_1__SEL_1 ; + assign ifcs_0_1_state_1$EN = + WILL_FIRE_RL_ifcs_0_1_followFlits_1 && + uncached_mem_shim_rff$D_OUT[1] || + WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && + !uncached_mem_shim_rff$D_OUT[1] ; + + // register ifcs_0_noRoute_inner_currentReq + assign ifcs_0_noRoute_inner_currentReq$D_IN = + ifcs_0_noRoute_inner_currentReq$port1__read ; + assign ifcs_0_noRoute_inner_currentReq$EN = 1'b1 ; + + // register ifcs_0_noRoute_inner_pendingReq + assign ifcs_0_noRoute_inner_pendingReq$D_IN = + ifcs_0_noRoute_inner_pendingReq$port2__read ; + assign ifcs_0_noRoute_inner_pendingReq$EN = 1'b1 ; + + // register ifcs_0_state + always@(MUX_ifcs_0_state$write_1__SEL_1 or + MUX_ifcs_0_state$write_1__SEL_2 or MUX_ifcs_0_state$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_ifcs_0_state$write_1__SEL_1: ifcs_0_state$D_IN = 2'd0; + MUX_ifcs_0_state$write_1__SEL_2: ifcs_0_state$D_IN = 2'd1; + MUX_ifcs_0_state$write_1__SEL_3: ifcs_0_state$D_IN = 2'd2; + default: ifcs_0_state$D_IN = 2'b10 /* unspecified value */ ; + endcase + end + assign ifcs_0_state$EN = + (WILL_FIRE_RL_ifcs_0_drainFlits || + WILL_FIRE_RL_ifcs_0_followFlits) && + proc$master1_wlast || + WILL_FIRE_RL_ifcs_0_firstFlit && !proc$master1_wlast || + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && !proc$master1_wlast ; + + // register ifcs_0_state_1 + assign ifcs_0_state_1$D_IN = 1'd0 ; + assign ifcs_0_state_1$EN = CAN_FIRE_RL_ifcs_0_followFlits_1 ; + + // register ifcs_1_1_noRoute_currentReq + assign ifcs_1_1_noRoute_currentReq$D_IN = + ifcs_1_1_noRoute_currentReq$port1__read ; + assign ifcs_1_1_noRoute_currentReq$EN = 1'b1 ; + + // register ifcs_1_1_noRoute_flitCount + assign ifcs_1_1_noRoute_flitCount$D_IN = + ifcs_1_1_noRoute_flitCount$port2__read ; + assign ifcs_1_1_noRoute_flitCount$EN = 1'b1 ; + + // register ifcs_1_1_state + assign ifcs_1_1_state$D_IN = 2'd0 ; + assign ifcs_1_1_state$EN = + WILL_FIRE_RL_ifcs_1_1_drainFlits || + WILL_FIRE_RL_ifcs_1_1_followFlits ; + + // register ifcs_1_1_state_1 + assign ifcs_1_1_state_1$D_IN = !MUX_ifcs_1_1_state_1$write_1__SEL_1 ; + assign ifcs_1_1_state_1$EN = + WILL_FIRE_RL_ifcs_1_1_followFlits_1 && plic$axi4_slave_rlast || + WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && !plic$axi4_slave_rlast ; + + // register ifcs_1_noRoute_inner_currentReq + assign ifcs_1_noRoute_inner_currentReq$D_IN = + ifcs_1_noRoute_inner_currentReq$port1__read ; + assign ifcs_1_noRoute_inner_currentReq$EN = 1'b1 ; + + // register ifcs_1_noRoute_inner_pendingReq + assign ifcs_1_noRoute_inner_pendingReq$D_IN = + ifcs_1_noRoute_inner_pendingReq$port2__read ; + assign ifcs_1_noRoute_inner_pendingReq$EN = 1'b1 ; + + // register ifcs_1_state + always@(MUX_ifcs_1_state$write_1__SEL_1 or + MUX_ifcs_1_state$write_1__SEL_2 or MUX_ifcs_1_state$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_ifcs_1_state$write_1__SEL_1: ifcs_1_state$D_IN = 2'd0; + MUX_ifcs_1_state$write_1__SEL_2: ifcs_1_state$D_IN = 2'd1; + MUX_ifcs_1_state$write_1__SEL_3: ifcs_1_state$D_IN = 2'd2; + default: ifcs_1_state$D_IN = 2'b10 /* unspecified value */ ; + endcase + end + assign ifcs_1_state$EN = + (WILL_FIRE_RL_ifcs_1_drainFlits || + WILL_FIRE_RL_ifcs_1_followFlits) && + debug_module$master_wlast || + WILL_FIRE_RL_ifcs_1_firstFlit && !debug_module$master_wlast || + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && + !debug_module$master_wlast ; + + // register ifcs_1_state_1 + assign ifcs_1_state_1$D_IN = 1'd0 ; + assign ifcs_1_state_1$EN = CAN_FIRE_RL_ifcs_1_followFlits_1 ; + + // register ifcs_2_1_state + assign ifcs_2_1_state$D_IN = !MUX_ifcs_2_1_state$write_1__SEL_1 ; + assign ifcs_2_1_state$EN = + WILL_FIRE_RL_ifcs_2_1_followFlits && + proc$debug_module_mem_server_rlast || + WILL_FIRE_RL_ifcs_2_1_firstFlit && + !proc$debug_module_mem_server_rlast ; + + // register ifcs_2_state + assign ifcs_2_state$D_IN = 1'd0 ; + assign ifcs_2_state$EN = CAN_FIRE_RL_ifcs_2_followFlits ; + + // register merged_0_flitLeft + assign merged_0_flitLeft$D_IN = + WILL_FIRE_RL_merged_0_genOther ? + MUX_merged_0_flitLeft$write_1__VAL_1 : + proc$master1_awlen ; + assign merged_0_flitLeft$EN = msNoSynth_0_w_dwReady$whas ; + + // register merged_1_flitLeft + assign merged_1_flitLeft$D_IN = + WILL_FIRE_RL_merged_1_genOther ? + MUX_merged_1_flitLeft$write_1__VAL_1 : + debug_module$master_awlen ; + assign merged_1_flitLeft$EN = msNoSynth_1_w_dwReady$whas ; // register rg_fromhost_addr - assign rg_fromhost_addr$D_IN = set_htif_addrs_fromhost_addr ; - assign rg_fromhost_addr$EN = EN_set_htif_addrs ; + assign rg_fromhost_addr$D_IN = start_fromhost_addr ; + assign rg_fromhost_addr$EN = EN_start ; + + // register rg_hart0_reset_delay + assign rg_hart0_reset_delay$D_IN = + WILL_FIRE_RL_rl_dm_hart0_reset_wait ? + MUX_rg_hart0_reset_delay$write_1__VAL_1 : + 8'd210 ; + assign rg_hart0_reset_delay$EN = + WILL_FIRE_RL_rl_dm_hart0_reset_wait || + WILL_FIRE_RL_rl_dm_hart0_reset ; // register rg_tohost_addr - assign rg_tohost_addr$D_IN = set_htif_addrs_tohost_addr ; - assign rg_tohost_addr$EN = EN_set_htif_addrs ; + assign rg_tohost_addr$D_IN = start_tohost_addr ; + assign rg_tohost_addr$EN = EN_start ; - // submodule cpu_halt - assign cpu_halt$ASSERT_IN = hart0_halt ; + // register split_0_flitLeft + assign split_0_flitLeft$D_IN = + MUX_split_0_flitLeft$write_1__SEL_1 ? + MUX_split_0_flitLeft$write_1__VAL_1 : + split_0_doPut$wget[102:95] ; + assign split_0_flitLeft$EN = ssNoSynth_0_w_buffer_enqw$whas ; - // submodule cpu_reset - assign cpu_reset$ASSERT_IN = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; + // register split_1_flitLeft + assign split_1_flitLeft$D_IN = + MUX_split_1_flitLeft$write_1__SEL_1 ? + MUX_split_1_flitLeft$write_1__VAL_1 : + split_1_doPut$wget[102:95] ; + assign split_1_flitLeft$EN = ssNoSynth_1_w_buffer_enqw$whas ; + + // register split_2_flitLeft + assign split_2_flitLeft$D_IN = + MUX_split_2_flitLeft$write_1__SEL_1 ? + MUX_split_2_flitLeft$write_1__VAL_1 : + split_2_doPut$wget[102:95] ; + assign split_2_flitLeft$EN = ssNoSynth_2_w_buffer_enqw$whas ; + + // register state + assign state$D_IN = !MUX_state$write_1__SEL_1 && !MUX_state$write_1__SEL_2 ; + assign state$EN = + WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[1] || + WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[1] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + !ifcs_0_innerReq$D_OUT[1] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + !ifcs_1_innerReq$D_OUT[1] ; + + // register state_1 + assign state_1$D_IN = 1'd0 ; + assign state_1$EN = + WILL_FIRE_RL_burst_4 || WILL_FIRE_RL_burst_3 || + WILL_FIRE_RL_burst_2 ; + + // register state_1_1 + assign state_1_1$D_IN = 1'd0 ; + assign state_1_1$EN = WILL_FIRE_RL_burst_6 || WILL_FIRE_RL_burst_5 ; + + // register state_1_1_1 + assign state_1_1_1$D_IN = + !MUX_state_1_1_1$write_1__SEL_1 && + !MUX_state_1_1_1$write_1__SEL_2 && + !MUX_state_1_1_1$write_1__SEL_3 ; + assign state_1_1_1$EN = + WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[1] ; + + // register tagController_tmp_addrOffset + assign tagController_tmp_addrOffset$D_IN = + tagController_tmp_shimSlave_wff_rv$port1__read[1] ? + 64'd0 : + x__h8199 ; + assign tagController_tmp_addrOffset$EN = + WILL_FIRE_RL_tagController_tmp_passCacheWrite ; + + // register tagController_tmp_doneSendingAW + assign tagController_tmp_doneSendingAW$D_IN = + !tagController_tmp_tagCon$memory_request_get[91] ; + assign tagController_tmp_doneSendingAW$EN = + WILL_FIRE_RL_tagController_tmp_passMemoryRequest && + tagController_tmp_tagCon$memory_request_get[93:92] == 2'd1 ; + + // register tagController_tmp_reset_done + assign tagController_tmp_reset_done$D_IN = 1'd1 ; + assign tagController_tmp_reset_done$EN = + CAN_FIRE_RL_tagController_tmp_propagateReset ; + + // register tagController_tmp_shimMaster_arff_rv + assign tagController_tmp_shimMaster_arff_rv$D_IN = + tagController_tmp_shimMaster_arff_rv$port3__read ; + assign tagController_tmp_shimMaster_arff_rv$EN = 1'b1 ; + + // register tagController_tmp_shimMaster_awff_rv + assign tagController_tmp_shimMaster_awff_rv$D_IN = + tagController_tmp_shimMaster_awff_rv$port3__read ; + assign tagController_tmp_shimMaster_awff_rv$EN = 1'b1 ; + + // register tagController_tmp_shimMaster_bff_rv + assign tagController_tmp_shimMaster_bff_rv$D_IN = + tagController_tmp_shimMaster_bff_rv$port3__read ; + assign tagController_tmp_shimMaster_bff_rv$EN = 1'b1 ; + + // register tagController_tmp_shimMaster_rff_rv + assign tagController_tmp_shimMaster_rff_rv$D_IN = + tagController_tmp_shimMaster_rff_rv$port3__read ; + assign tagController_tmp_shimMaster_rff_rv$EN = 1'b1 ; + + // register tagController_tmp_shimMaster_wff_rv + assign tagController_tmp_shimMaster_wff_rv$D_IN = + tagController_tmp_shimMaster_wff_rv$port3__read ; + assign tagController_tmp_shimMaster_wff_rv$EN = 1'b1 ; + + // register tagController_tmp_shimSlave_arff_rv + assign tagController_tmp_shimSlave_arff_rv$D_IN = + tagController_tmp_shimSlave_arff_rv$port3__read ; + assign tagController_tmp_shimSlave_arff_rv$EN = 1'b1 ; + + // register tagController_tmp_shimSlave_awff_rv + assign tagController_tmp_shimSlave_awff_rv$D_IN = + tagController_tmp_shimSlave_awff_rv$port3__read ; + assign tagController_tmp_shimSlave_awff_rv$EN = 1'b1 ; + + // register tagController_tmp_shimSlave_bff_rv + assign tagController_tmp_shimSlave_bff_rv$D_IN = + tagController_tmp_shimSlave_bff_rv$port3__read ; + assign tagController_tmp_shimSlave_bff_rv$EN = 1'b1 ; + + // register tagController_tmp_shimSlave_rff_rv + assign tagController_tmp_shimSlave_rff_rv$D_IN = + tagController_tmp_shimSlave_rff_rv$port3__read ; + assign tagController_tmp_shimSlave_rff_rv$EN = 1'b1 ; + + // register tagController_tmp_shimSlave_wff_rv + assign tagController_tmp_shimSlave_wff_rv$D_IN = + tagController_tmp_shimSlave_wff_rv$port3__read ; + assign tagController_tmp_shimSlave_wff_rv$EN = 1'b1 ; // submodule debug_module - assign debug_module$dmi_read_addr_dm_addr = dm_dmi_read_addr_dm_addr ; - assign debug_module$dmi_write_dm_addr = dm_dmi_write_dm_addr ; - assign debug_module$dmi_write_dm_word = dm_dmi_write_dm_word ; + assign debug_module$dmi_read_addr_dm_addr = dmi_read_addr_dm_addr ; + assign debug_module$dmi_write_dm_addr = dmi_write_dm_addr ; + assign debug_module$dmi_write_dm_word = dmi_write_dm_word ; assign debug_module$hart0_client_run_halt_response_put = - debug_module$hart0_client_run_halt_request_get ; + proc$hart0_run_halt_server_response_get ; assign debug_module$hart0_csr_mem_client_response_put = - 65'h10000000000000000 ; - assign debug_module$hart0_fpr_mem_client_response_put = - 65'h10000000000000000 ; + proc$hart0_csr_mem_server_response_get ; + assign debug_module$hart0_fpr_mem_client_response_put = 65'h0 ; assign debug_module$hart0_gpr_mem_client_response_put = - 65'h10000000000000000 ; - assign debug_module$master_arready = dm_mem_tap$slave_arready ; - assign debug_module$master_awready = dm_mem_tap$slave_awready ; - assign debug_module$master_bid = dm_mem_tap$slave_bid ; - assign debug_module$master_bresp = dm_mem_tap$slave_bresp ; - assign debug_module$master_bvalid = dm_mem_tap$slave_bvalid ; - assign debug_module$master_rdata = dm_mem_tap$slave_rdata ; - assign debug_module$master_rid = dm_mem_tap$slave_rid ; - assign debug_module$master_rlast = dm_mem_tap$slave_rlast ; - assign debug_module$master_rresp = dm_mem_tap$slave_rresp ; - assign debug_module$master_rvalid = dm_mem_tap$slave_rvalid ; - assign debug_module$master_wready = dm_mem_tap$slave_wready ; - assign debug_module$EN_dmi_read_addr = EN_dm_dmi_read_addr ; - assign debug_module$EN_dmi_read_data = EN_dm_dmi_read_data ; - assign debug_module$EN_dmi_write = EN_dm_dmi_write ; - assign debug_module$EN_hart0_get_reset_req_get = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start ; + proc$hart0_gpr_mem_server_response_get ; + assign debug_module$hart0_reset_client_response_put = 1'd1 ; + assign debug_module$master_arready = msNoSynth_1_ar_dwReady$whas ; + assign debug_module$master_awready = CAN_FIRE_RL_merged_1_genFirst ; + assign debug_module$master_bid = + msNoSynth_1_b_buffer_ff$EMPTY_N ? + msNoSynth_1_b_buffer_ff$D_OUT[5:2] : + msNoSynth_1_b_buffer_enqw$wget[5:2] ; + assign debug_module$master_bresp = + msNoSynth_1_b_buffer_ff$EMPTY_N ? + msNoSynth_1_b_buffer_ff$D_OUT[1:0] : + msNoSynth_1_b_buffer_enqw$wget[1:0] ; + assign debug_module$master_rdata = + msNoSynth_1_r_buffer_ff$EMPTY_N ? + msNoSynth_1_r_buffer_ff$D_OUT[67:4] : + msNoSynth_1_r_buffer_enqw$wget[67:4] ; + assign debug_module$master_rid = + msNoSynth_1_r_buffer_ff$EMPTY_N ? + msNoSynth_1_r_buffer_ff$D_OUT[71:68] : + msNoSynth_1_r_buffer_enqw$wget[71:68] ; + assign debug_module$master_rlast = + msNoSynth_1_r_buffer_ff$EMPTY_N ? + msNoSynth_1_r_buffer_ff$D_OUT[1] : + msNoSynth_1_r_buffer_enqw$wget[1] ; + assign debug_module$master_rresp = + msNoSynth_1_r_buffer_ff$EMPTY_N ? + msNoSynth_1_r_buffer_ff$D_OUT[3:2] : + msNoSynth_1_r_buffer_enqw$wget[3:2] ; + assign debug_module$master_ruser = + msNoSynth_1_r_buffer_ff$EMPTY_N ? + msNoSynth_1_r_buffer_ff$D_OUT[0] : + msNoSynth_1_r_buffer_enqw$wget[0] ; + assign debug_module$master_wready = msNoSynth_1_w_dwReady$whas ; + assign debug_module$ndm_reset_client_response_put = + ndm_reset_client_response_put ; + assign debug_module$EN_dmi_read_addr = EN_dmi_read_addr ; + assign debug_module$EN_dmi_read_data = EN_dmi_read_data ; + assign debug_module$EN_dmi_write = EN_dmi_write ; + assign debug_module$EN_hart0_reset_client_request_get = + CAN_FIRE_RL_rl_dm_hart0_reset ; + assign debug_module$EN_hart0_reset_client_response_put = + MUX_proc$start_1__SEL_1 ; assign debug_module$EN_hart0_client_run_halt_request_get = - CAN_FIRE_RL_rl_halt ; + CAN_FIRE_RL_ClientServerRequest ; assign debug_module$EN_hart0_client_run_halt_response_put = - CAN_FIRE_RL_rl_halt ; - assign debug_module$EN_hart0_get_other_req_get = 1'b0 ; + CAN_FIRE_RL_ClientServerResponse ; + assign debug_module$EN_hart0_get_other_req_get = + debug_module$RDY_hart0_get_other_req_get ; assign debug_module$EN_hart0_gpr_mem_client_request_get = - CAN_FIRE_RL_rl_gpr ; + CAN_FIRE_RL_ClientServerRequest_1 ; assign debug_module$EN_hart0_gpr_mem_client_response_put = - CAN_FIRE_RL_rl_gpr ; - assign debug_module$EN_hart0_fpr_mem_client_request_get = - CAN_FIRE_RL_rl_fpr ; - assign debug_module$EN_hart0_fpr_mem_client_response_put = - CAN_FIRE_RL_rl_fpr ; + CAN_FIRE_RL_ClientServerResponse_1 ; + assign debug_module$EN_hart0_fpr_mem_client_request_get = 1'b0 ; + assign debug_module$EN_hart0_fpr_mem_client_response_put = 1'b0 ; assign debug_module$EN_hart0_csr_mem_client_request_get = - CAN_FIRE_RL_rl_csr ; + CAN_FIRE_RL_ClientServerRequest_2 ; assign debug_module$EN_hart0_csr_mem_client_response_put = - CAN_FIRE_RL_rl_csr ; - assign debug_module$EN_get_ndm_reset_req_get = EN_dm_ndm_reset_req_get_get ; + CAN_FIRE_RL_ClientServerResponse_2 ; + assign debug_module$EN_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + assign debug_module$EN_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; + assign debug_module$master_bvalid = CAN_FIRE_RL_msNoSynth_1_b_forwardFlit ; + assign debug_module$master_rvalid = CAN_FIRE_RL_msNoSynth_1_r_forwardFlit ; - // submodule dm_mem_tap - assign dm_mem_tap$master_arready = fabric_2x3$v_from_masters_1_arready ; - assign dm_mem_tap$master_awready = fabric_2x3$v_from_masters_1_awready ; - assign dm_mem_tap$master_bid = fabric_2x3$v_from_masters_1_bid ; - assign dm_mem_tap$master_bresp = fabric_2x3$v_from_masters_1_bresp ; - assign dm_mem_tap$master_bvalid = fabric_2x3$v_from_masters_1_bvalid ; - assign dm_mem_tap$master_rdata = fabric_2x3$v_from_masters_1_rdata ; - assign dm_mem_tap$master_rid = fabric_2x3$v_from_masters_1_rid ; - assign dm_mem_tap$master_rlast = fabric_2x3$v_from_masters_1_rlast ; - assign dm_mem_tap$master_rresp = fabric_2x3$v_from_masters_1_rresp ; - assign dm_mem_tap$master_rvalid = fabric_2x3$v_from_masters_1_rvalid ; - assign dm_mem_tap$master_wready = fabric_2x3$v_from_masters_1_wready ; - assign dm_mem_tap$slave_araddr = debug_module$master_araddr ; - assign dm_mem_tap$slave_arburst = debug_module$master_arburst ; - assign dm_mem_tap$slave_arcache = debug_module$master_arcache ; - assign dm_mem_tap$slave_arid = debug_module$master_arid ; - assign dm_mem_tap$slave_arlen = debug_module$master_arlen ; - assign dm_mem_tap$slave_arlock = debug_module$master_arlock ; - assign dm_mem_tap$slave_arprot = debug_module$master_arprot ; - assign dm_mem_tap$slave_arqos = debug_module$master_arqos ; - assign dm_mem_tap$slave_arregion = debug_module$master_arregion ; - assign dm_mem_tap$slave_arsize = debug_module$master_arsize ; - assign dm_mem_tap$slave_arvalid = debug_module$master_arvalid ; - assign dm_mem_tap$slave_awaddr = debug_module$master_awaddr ; - assign dm_mem_tap$slave_awburst = debug_module$master_awburst ; - assign dm_mem_tap$slave_awcache = debug_module$master_awcache ; - assign dm_mem_tap$slave_awid = debug_module$master_awid ; - assign dm_mem_tap$slave_awlen = debug_module$master_awlen ; - assign dm_mem_tap$slave_awlock = debug_module$master_awlock ; - assign dm_mem_tap$slave_awprot = debug_module$master_awprot ; - assign dm_mem_tap$slave_awqos = debug_module$master_awqos ; - assign dm_mem_tap$slave_awregion = debug_module$master_awregion ; - assign dm_mem_tap$slave_awsize = debug_module$master_awsize ; - assign dm_mem_tap$slave_awvalid = debug_module$master_awvalid ; - assign dm_mem_tap$slave_bready = debug_module$master_bready ; - assign dm_mem_tap$slave_rready = debug_module$master_rready ; - assign dm_mem_tap$slave_wdata = debug_module$master_wdata ; - assign dm_mem_tap$slave_wid = debug_module$master_wid ; - assign dm_mem_tap$slave_wlast = debug_module$master_wlast ; - assign dm_mem_tap$slave_wstrb = debug_module$master_wstrb ; - assign dm_mem_tap$slave_wvalid = debug_module$master_wvalid ; - assign dm_mem_tap$EN_trace_data_out_get = - WILL_FIRE_RL_merge_dm_mem_trace_data ; + // submodule dm_hart0_reset_controller + assign dm_hart0_reset_controller$ASSERT_IN = CAN_FIRE_RL_rl_dm_hart0_reset ; - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; - assign f_reset_reqs$DEQ = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - f_reset_reqs$EMPTY_N ; - assign f_reset_reqs$CLR = 1'b0 ; + // submodule ifcs_0_1_innerReq + assign ifcs_0_1_innerReq$D_IN = + { fatReq_arid__h72495, + proc$master1_araddr, + proc$master1_arlen, + proc$master1_arsize, + proc$master1_arburst, + proc$master1_arlock, + proc$master1_arcache, + proc$master1_arprot, + proc$master1_arqos, + proc$master1_arregion } ; + assign ifcs_0_1_innerReq$ENQ = + WILL_FIRE_RL_ifcs_0_1_followFlits || + WILL_FIRE_RL_ifcs_0_1_firstFlit ; + assign ifcs_0_1_innerReq$DEQ = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_5 ; + assign ifcs_0_1_innerReq$CLR = 1'b0 ; - // submodule f_reset_requestor - assign f_reset_requestor$D_IN = 1'd0 ; - assign f_reset_requestor$ENQ = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start ; - assign f_reset_requestor$DEQ = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_complete ; - assign f_reset_requestor$CLR = 1'b0 ; + // submodule ifcs_0_1_innerRoute + assign ifcs_0_1_innerRoute$D_IN = + { proc$master1_araddr[63:40] == 24'd0 && + !proc_master1_ar_araddr__852_ULT_soc_map_m_mem0_ETC___d1855 && + proc_master1_ar_araddr__852_MINUS_soc_map_m_me_ETC___d1857, + proc_master1_ar_araddr__852_BITS_63_TO_40_853__ETC___d1871, + proc_master1_ar_araddr__852_BITS_63_TO_40_853__ETC___d1866 } ; + assign ifcs_0_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit ; + assign ifcs_0_1_innerRoute$DEQ = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_5 ; + assign ifcs_0_1_innerRoute$CLR = 1'b0 ; - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = - plic$RDY_server_reset_response_get && f_reset_rsps$FULL_N && - !cpu_reset$ASSERT_OUT ; - assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; + // submodule ifcs_0_1_noRouteRsp + assign ifcs_0_1_noRouteRsp$D_IN = + { ifcs_0_1_noRoute_currentReq$port1__read[96:93], + 66'h2AAAAAAAAAAAAAAAB, + x_port1__read__h73054 == 9'd1, + 1'h0 } ; + assign ifcs_0_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; + assign ifcs_0_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + assign ifcs_0_1_noRouteRsp$CLR = 1'b0 ; - // submodule f_trace_data_merged - assign f_trace_data_merged$D_IN = - WILL_FIRE_RL_merge_cpu_trace_data ? - proc$trace_data_out_get : - dm_mem_tap$trace_data_out_get ; - assign f_trace_data_merged$ENQ = - WILL_FIRE_RL_merge_cpu_trace_data || - WILL_FIRE_RL_merge_dm_mem_trace_data ; - assign f_trace_data_merged$DEQ = CAN_FIRE_RL_mkConnectionGetPut ; - assign f_trace_data_merged$CLR = 1'b0 ; + // submodule ifcs_0_1_routeBack + assign ifcs_0_1_routeBack$D_IN = 2'd1 << uncached_mem_shim_rff$D_OUT[72] ; + assign ifcs_0_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit_1 ; + assign ifcs_0_1_routeBack$DEQ = + WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_rspBack$D_OUT[1] ; + assign ifcs_0_1_routeBack$CLR = 1'b0 ; - // submodule fabric_2x3 - assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; - assign fabric_2x3$v_from_masters_0_araddr = proc$master1_araddr ; - assign fabric_2x3$v_from_masters_0_arburst = proc$master1_arburst ; - assign fabric_2x3$v_from_masters_0_arcache = proc$master1_arcache ; - assign fabric_2x3$v_from_masters_0_arid = proc$master1_arid ; - assign fabric_2x3$v_from_masters_0_arlen = proc$master1_arlen ; - assign fabric_2x3$v_from_masters_0_arlock = proc$master1_arlock ; - assign fabric_2x3$v_from_masters_0_arprot = proc$master1_arprot ; - assign fabric_2x3$v_from_masters_0_arqos = proc$master1_arqos ; - assign fabric_2x3$v_from_masters_0_arregion = proc$master1_arregion ; - assign fabric_2x3$v_from_masters_0_arsize = proc$master1_arsize ; - assign fabric_2x3$v_from_masters_0_arvalid = proc$master1_arvalid ; - assign fabric_2x3$v_from_masters_0_awaddr = proc$master1_awaddr ; - assign fabric_2x3$v_from_masters_0_awburst = proc$master1_awburst ; - assign fabric_2x3$v_from_masters_0_awcache = proc$master1_awcache ; - assign fabric_2x3$v_from_masters_0_awid = proc$master1_awid ; - assign fabric_2x3$v_from_masters_0_awlen = proc$master1_awlen ; - assign fabric_2x3$v_from_masters_0_awlock = proc$master1_awlock ; - assign fabric_2x3$v_from_masters_0_awprot = proc$master1_awprot ; - assign fabric_2x3$v_from_masters_0_awqos = proc$master1_awqos ; - assign fabric_2x3$v_from_masters_0_awregion = proc$master1_awregion ; - assign fabric_2x3$v_from_masters_0_awsize = proc$master1_awsize ; - assign fabric_2x3$v_from_masters_0_awvalid = proc$master1_awvalid ; - assign fabric_2x3$v_from_masters_0_bready = proc$master1_bready ; - assign fabric_2x3$v_from_masters_0_rready = proc$master1_rready ; - assign fabric_2x3$v_from_masters_0_wdata = proc$master1_wdata ; - assign fabric_2x3$v_from_masters_0_wid = proc$master1_wid ; - assign fabric_2x3$v_from_masters_0_wlast = proc$master1_wlast ; - assign fabric_2x3$v_from_masters_0_wstrb = proc$master1_wstrb ; - assign fabric_2x3$v_from_masters_0_wvalid = proc$master1_wvalid ; - assign fabric_2x3$v_from_masters_1_araddr = dm_mem_tap$master_araddr ; - assign fabric_2x3$v_from_masters_1_arburst = dm_mem_tap$master_arburst ; - assign fabric_2x3$v_from_masters_1_arcache = dm_mem_tap$master_arcache ; - assign fabric_2x3$v_from_masters_1_arid = dm_mem_tap$master_arid ; - assign fabric_2x3$v_from_masters_1_arlen = dm_mem_tap$master_arlen ; - assign fabric_2x3$v_from_masters_1_arlock = dm_mem_tap$master_arlock ; - assign fabric_2x3$v_from_masters_1_arprot = dm_mem_tap$master_arprot ; - assign fabric_2x3$v_from_masters_1_arqos = dm_mem_tap$master_arqos ; - assign fabric_2x3$v_from_masters_1_arregion = dm_mem_tap$master_arregion ; - assign fabric_2x3$v_from_masters_1_arsize = dm_mem_tap$master_arsize ; - assign fabric_2x3$v_from_masters_1_arvalid = dm_mem_tap$master_arvalid ; - assign fabric_2x3$v_from_masters_1_awaddr = dm_mem_tap$master_awaddr ; - assign fabric_2x3$v_from_masters_1_awburst = dm_mem_tap$master_awburst ; - assign fabric_2x3$v_from_masters_1_awcache = dm_mem_tap$master_awcache ; - assign fabric_2x3$v_from_masters_1_awid = dm_mem_tap$master_awid ; - assign fabric_2x3$v_from_masters_1_awlen = dm_mem_tap$master_awlen ; - assign fabric_2x3$v_from_masters_1_awlock = dm_mem_tap$master_awlock ; - assign fabric_2x3$v_from_masters_1_awprot = dm_mem_tap$master_awprot ; - assign fabric_2x3$v_from_masters_1_awqos = dm_mem_tap$master_awqos ; - assign fabric_2x3$v_from_masters_1_awregion = dm_mem_tap$master_awregion ; - assign fabric_2x3$v_from_masters_1_awsize = dm_mem_tap$master_awsize ; - assign fabric_2x3$v_from_masters_1_awvalid = dm_mem_tap$master_awvalid ; - assign fabric_2x3$v_from_masters_1_bready = dm_mem_tap$master_bready ; - assign fabric_2x3$v_from_masters_1_rready = dm_mem_tap$master_rready ; - assign fabric_2x3$v_from_masters_1_wdata = dm_mem_tap$master_wdata ; - assign fabric_2x3$v_from_masters_1_wid = dm_mem_tap$master_wid ; - assign fabric_2x3$v_from_masters_1_wlast = dm_mem_tap$master_wlast ; - assign fabric_2x3$v_from_masters_1_wstrb = dm_mem_tap$master_wstrb ; - assign fabric_2x3$v_from_masters_1_wvalid = dm_mem_tap$master_wvalid ; - assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ; - assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ; - assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ; - assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ; - assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ; - assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ; - assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ; - assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ; - assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ; - assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ; - assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ; - assign fabric_2x3$v_to_slaves_1_arready = plic$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_1_awready = plic$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_1_bid = plic$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_1_bresp = plic$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_1_bvalid = plic$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_1_rdata = plic$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_1_rid = plic$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_1_rlast = plic$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_1_rresp = plic$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_1_rvalid = plic$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_1_wready = plic$axi4_slave_wready ; - assign fabric_2x3$v_to_slaves_2_arready = 1'd0 ; - assign fabric_2x3$v_to_slaves_2_awready = 1'd0 ; - assign fabric_2x3$v_to_slaves_2_bid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_to_slaves_2_bresp = 2'd0 ; - assign fabric_2x3$v_to_slaves_2_bvalid = 1'd0 ; - assign fabric_2x3$v_to_slaves_2_rdata = 64'd0 ; - assign fabric_2x3$v_to_slaves_2_rid = 4'd0 ; - assign fabric_2x3$v_to_slaves_2_rlast = 1'd1 ; - assign fabric_2x3$v_to_slaves_2_rresp = 2'd0 ; - assign fabric_2x3$v_to_slaves_2_rvalid = 1'd0 ; - assign fabric_2x3$v_to_slaves_2_wready = 1'd0 ; - assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign fabric_2x3$EN_set_verbosity = 1'b0 ; + // submodule ifcs_0_1_rspBack + assign ifcs_0_1_rspBack$D_IN = uncached_mem_shim_rff$D_OUT[71:0] ; + assign ifcs_0_1_rspBack$ENQ = ssNoSynth_0_r_dwReady$whas ; + assign ifcs_0_1_rspBack$DEQ = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_7 ; + assign ifcs_0_1_rspBack$CLR = 1'b0 ; + + // submodule ifcs_0_innerReq + assign ifcs_0_innerReq$D_IN = + { merged_0_flitLeft != 8'd0, + a_awid__h38608, + proc$master1_awaddr, + proc$master1_awlen, + proc$master1_awsize, + proc$master1_awburst, + proc$master1_awlock, + proc$master1_awcache, + proc$master1_awprot, + proc$master1_awqos, + proc$master1_awregion, + proc$master1_wdata, + proc$master1_wstrb, + proc$master1_wlast, + 1'd0 } ; + assign ifcs_0_innerReq$ENQ = + WILL_FIRE_RL_ifcs_0_followFlits || + WILL_FIRE_RL_ifcs_0_firstFlit ; + assign ifcs_0_innerReq$DEQ = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst ; + assign ifcs_0_innerReq$CLR = 1'b0 ; + + // submodule ifcs_0_innerRoute + assign ifcs_0_innerRoute$D_IN = + { proc$master1_awaddr[63:40] == 24'd0 && + !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1194 && + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1197, + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1214, + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1209 } ; + assign ifcs_0_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit ; + assign ifcs_0_innerRoute$DEQ = + WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[1] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerReq$D_OUT[1] ; + assign ifcs_0_innerRoute$CLR = 1'b0 ; + + // submodule ifcs_0_noRouteRsp + assign ifcs_0_noRouteRsp$D_IN = + { ifcs_0_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; + assign ifcs_0_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; + assign ifcs_0_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_0_drainNoRouteResponse ; + assign ifcs_0_noRouteRsp$CLR = 1'b0 ; + + // submodule ifcs_0_routeBack + assign ifcs_0_routeBack$D_IN = 2'd1 << uncached_mem_shim_bff$D_OUT[6] ; + assign ifcs_0_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; + assign ifcs_0_routeBack$DEQ = + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_2 ; + assign ifcs_0_routeBack$CLR = 1'b0 ; + + // submodule ifcs_0_rspBack + assign ifcs_0_rspBack$D_IN = uncached_mem_shim_bff$D_OUT[5:0] ; + assign ifcs_0_rspBack$ENQ = ssNoSynth_0_b_dwReady$whas ; + assign ifcs_0_rspBack$DEQ = + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_2 ; + assign ifcs_0_rspBack$CLR = 1'b0 ; + + // submodule ifcs_1_1_innerReq + assign ifcs_1_1_innerReq$D_IN = + { fatReq_arid__h74960, + debug_module$master_araddr, + debug_module$master_arlen, + debug_module$master_arsize, + debug_module$master_arburst, + debug_module$master_arlock, + debug_module$master_arcache, + debug_module$master_arprot, + debug_module$master_arqos, + debug_module$master_arregion } ; + assign ifcs_1_1_innerReq$ENQ = + WILL_FIRE_RL_ifcs_1_1_followFlits || + WILL_FIRE_RL_ifcs_1_1_firstFlit ; + assign ifcs_1_1_innerReq$DEQ = + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_6 ; + assign ifcs_1_1_innerReq$CLR = 1'b0 ; + + // submodule ifcs_1_1_innerRoute + assign ifcs_1_1_innerRoute$D_IN = + { debug_module$master_araddr[63:40] == 24'd0 && + !debug_module_master_ar_araddr__944_ULT_soc_map_ETC___d1947 && + debug_module_master_ar_araddr__944_MINUS_soc_m_ETC___d1949, + debug_module_master_ar_araddr__944_BITS_63_TO__ETC___d1963, + debug_module_master_ar_araddr__944_BITS_63_TO__ETC___d1958 } ; + assign ifcs_1_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit ; + assign ifcs_1_1_innerRoute$DEQ = + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_6 ; + assign ifcs_1_1_innerRoute$CLR = 1'b0 ; + + // submodule ifcs_1_1_noRouteRsp + assign ifcs_1_1_noRouteRsp$D_IN = + { ifcs_1_1_noRoute_currentReq$port1__read[96:93], + 66'h2AAAAAAAAAAAAAAAB, + x_port1__read__h75518 == 9'd1, + 1'h0 } ; + assign ifcs_1_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; + assign ifcs_1_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; + assign ifcs_1_1_noRouteRsp$CLR = 1'b0 ; + + // submodule ifcs_1_1_routeBack + assign ifcs_1_1_routeBack$D_IN = 2'd1 << plic$axi4_slave_rid[4] ; + assign ifcs_1_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit_1 ; + assign ifcs_1_1_routeBack$DEQ = + WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_rspBack$D_OUT[1] ; + assign ifcs_1_1_routeBack$CLR = 1'b0 ; + + // submodule ifcs_1_1_rspBack + assign ifcs_1_1_rspBack$D_IN = + { plic$axi4_slave_rid[3:0], + plic$axi4_slave_rdata, + plic$axi4_slave_rresp, + plic$axi4_slave_rlast, + plic$axi4_slave_ruser } ; + assign ifcs_1_1_rspBack$ENQ = ssNoSynth_1_r_dwReady$whas ; + assign ifcs_1_1_rspBack$DEQ = + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_8 ; + assign ifcs_1_1_rspBack$CLR = 1'b0 ; + + // submodule ifcs_1_innerReq + assign ifcs_1_innerReq$D_IN = + { merged_1_flitLeft != 8'd0, + a_awid__h41374, + debug_module$master_awaddr, + debug_module$master_awlen, + debug_module$master_awsize, + debug_module$master_awburst, + debug_module$master_awlock, + debug_module$master_awcache, + debug_module$master_awprot, + debug_module$master_awqos, + debug_module$master_awregion, + debug_module$master_wdata, + debug_module$master_wstrb, + debug_module$master_wlast, + debug_module$master_wuser } ; + assign ifcs_1_innerReq$ENQ = + WILL_FIRE_RL_ifcs_1_followFlits || + WILL_FIRE_RL_ifcs_1_firstFlit ; + assign ifcs_1_innerReq$DEQ = + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_1 ; + assign ifcs_1_innerReq$CLR = 1'b0 ; + + // submodule ifcs_1_innerRoute + assign ifcs_1_innerRoute$D_IN = + { debug_module$master_awaddr[63:40] == 24'd0 && + !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302 && + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1304, + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1318, + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1313 } ; + assign ifcs_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit ; + assign ifcs_1_innerRoute$DEQ = + WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[1] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + ifcs_1_innerReq$D_OUT[1] ; + assign ifcs_1_innerRoute$CLR = 1'b0 ; + + // submodule ifcs_1_noRouteRsp + assign ifcs_1_noRouteRsp$D_IN = + { ifcs_1_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; + assign ifcs_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; + assign ifcs_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_1_drainNoRouteResponse ; + assign ifcs_1_noRouteRsp$CLR = 1'b0 ; + + // submodule ifcs_1_routeBack + assign ifcs_1_routeBack$D_IN = 2'd1 << plic$axi4_slave_bid[4] ; + assign ifcs_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; + assign ifcs_1_routeBack$DEQ = + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_3 ; + assign ifcs_1_routeBack$CLR = 1'b0 ; + + // submodule ifcs_1_rspBack + assign ifcs_1_rspBack$D_IN = + { plic$axi4_slave_bid[3:0], plic$axi4_slave_bresp } ; + assign ifcs_1_rspBack$ENQ = ssNoSynth_1_b_dwReady$whas ; + assign ifcs_1_rspBack$DEQ = + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_3 ; + assign ifcs_1_rspBack$CLR = 1'b0 ; + + // submodule ifcs_2_1_routeBack + assign ifcs_2_1_routeBack$D_IN = + 2'd1 << proc$debug_module_mem_server_rid[4] ; + assign ifcs_2_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_1_firstFlit ; + assign ifcs_2_1_routeBack$DEQ = + WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_rspBack$D_OUT[1] ; + assign ifcs_2_1_routeBack$CLR = 1'b0 ; + + // submodule ifcs_2_1_rspBack + assign ifcs_2_1_rspBack$D_IN = + { proc$debug_module_mem_server_rid[3:0], + proc$debug_module_mem_server_rdata, + proc$debug_module_mem_server_rresp, + proc$debug_module_mem_server_rlast, + proc$debug_module_mem_server_ruser } ; + assign ifcs_2_1_rspBack$ENQ = ssNoSynth_2_r_dwReady$whas ; + assign ifcs_2_1_rspBack$DEQ = + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_9 ; + assign ifcs_2_1_rspBack$CLR = 1'b0 ; + + // submodule ifcs_2_routeBack + assign ifcs_2_routeBack$D_IN = 2'd1 << proc$debug_module_mem_server_bid[4] ; + assign ifcs_2_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_firstFlit ; + assign ifcs_2_routeBack$DEQ = + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_4 ; + assign ifcs_2_routeBack$CLR = 1'b0 ; + + // submodule ifcs_2_rspBack + assign ifcs_2_rspBack$D_IN = + { proc$debug_module_mem_server_bid[3:0], + proc$debug_module_mem_server_bresp } ; + assign ifcs_2_rspBack$ENQ = ssNoSynth_2_b_dwReady$whas ; + assign ifcs_2_rspBack$DEQ = + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_4 ; + assign ifcs_2_rspBack$CLR = 1'b0 ; + + // submodule msNoSynth_0_b_buffer_ff + assign msNoSynth_0_b_buffer_ff$D_IN = msNoSynth_0_b_buffer_enqw$wget ; + assign msNoSynth_0_b_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue ; + assign msNoSynth_0_b_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue ; + assign msNoSynth_0_b_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_b_buffer_firstValid + assign msNoSynth_0_b_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_b_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_0_b_dropFlit ; + + // submodule msNoSynth_0_r_buffer_ff + assign msNoSynth_0_r_buffer_ff$D_IN = msNoSynth_0_r_buffer_enqw$wget ; + assign msNoSynth_0_r_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue ; + assign msNoSynth_0_r_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue ; + assign msNoSynth_0_r_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_r_buffer_firstValid + assign msNoSynth_0_r_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_r_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_0_r_dropFlit ; + + // submodule msNoSynth_1_b_buffer_ff + assign msNoSynth_1_b_buffer_ff$D_IN = msNoSynth_1_b_buffer_enqw$wget ; + assign msNoSynth_1_b_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue ; + assign msNoSynth_1_b_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue ; + assign msNoSynth_1_b_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_b_buffer_firstValid + assign msNoSynth_1_b_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_b_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_1_b_dropFlit ; + + // submodule msNoSynth_1_r_buffer_ff + assign msNoSynth_1_r_buffer_ff$D_IN = msNoSynth_1_r_buffer_enqw$wget ; + assign msNoSynth_1_r_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue ; + assign msNoSynth_1_r_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue ; + assign msNoSynth_1_r_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_r_buffer_firstValid + assign msNoSynth_1_r_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_r_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_1_r_dropFlit ; // submodule plic - assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ; - assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ; - assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ; - assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ; - assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ; - assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ; - assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ; - assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ; - assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ; - assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ; - assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ; - assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ; - assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ; - assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ; - assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ; - assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ; - assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ; - assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ; - assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ; - assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ; - assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ; - assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ; - assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; - assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; - assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign plic$axi4_slave_wid = fabric_2x3$v_to_slaves_1_wid ; - assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; - assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; - assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; - assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ; - assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ; + assign plic$axi4_slave_araddr = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[92:29] : + ssNoSynth_1_ar_buffer_enqw$wget[92:29] ; + assign plic$axi4_slave_arburst = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[17:16] : + ssNoSynth_1_ar_buffer_enqw$wget[17:16] ; + assign plic$axi4_slave_arcache = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[14:11] : + ssNoSynth_1_ar_buffer_enqw$wget[14:11] ; + assign plic$axi4_slave_arid = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[97:93] : + ssNoSynth_1_ar_buffer_enqw$wget[97:93] ; + assign plic$axi4_slave_arlen = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[28:21] : + ssNoSynth_1_ar_buffer_enqw$wget[28:21] ; + assign plic$axi4_slave_arlock = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[15] : + ssNoSynth_1_ar_buffer_enqw$wget[15] ; + assign plic$axi4_slave_arprot = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[10:8] : + ssNoSynth_1_ar_buffer_enqw$wget[10:8] ; + assign plic$axi4_slave_arqos = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[7:4] : + ssNoSynth_1_ar_buffer_enqw$wget[7:4] ; + assign plic$axi4_slave_arregion = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[3:0] : + ssNoSynth_1_ar_buffer_enqw$wget[3:0] ; + assign plic$axi4_slave_arsize = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[20:18] : + ssNoSynth_1_ar_buffer_enqw$wget[20:18] ; + assign plic$axi4_slave_awaddr = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[92:29] : + ssNoSynth_1_aw_buffer_enqw$wget[92:29] ; + assign plic$axi4_slave_awburst = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[17:16] : + ssNoSynth_1_aw_buffer_enqw$wget[17:16] ; + assign plic$axi4_slave_awcache = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[14:11] : + ssNoSynth_1_aw_buffer_enqw$wget[14:11] ; + assign plic$axi4_slave_awid = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[97:93] : + ssNoSynth_1_aw_buffer_enqw$wget[97:93] ; + assign plic$axi4_slave_awlen = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[28:21] : + ssNoSynth_1_aw_buffer_enqw$wget[28:21] ; + assign plic$axi4_slave_awlock = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[15] : + ssNoSynth_1_aw_buffer_enqw$wget[15] ; + assign plic$axi4_slave_awprot = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[10:8] : + ssNoSynth_1_aw_buffer_enqw$wget[10:8] ; + assign plic$axi4_slave_awqos = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[7:4] : + ssNoSynth_1_aw_buffer_enqw$wget[7:4] ; + assign plic$axi4_slave_awregion = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[3:0] : + ssNoSynth_1_aw_buffer_enqw$wget[3:0] ; + assign plic$axi4_slave_awsize = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[20:18] : + ssNoSynth_1_aw_buffer_enqw$wget[20:18] ; + assign plic$axi4_slave_bready = ssNoSynth_1_b_dwReady$whas ; + assign plic$axi4_slave_rready = ssNoSynth_1_r_dwReady$whas ; + assign plic$axi4_slave_wdata = + ssNoSynth_1_w_buffer_ff$EMPTY_N ? + ssNoSynth_1_w_buffer_ff$D_OUT[73:10] : + ssNoSynth_1_w_buffer_enqw$wget[73:10] ; + assign plic$axi4_slave_wlast = + ssNoSynth_1_w_buffer_ff$EMPTY_N ? + ssNoSynth_1_w_buffer_ff$D_OUT[1] : + ssNoSynth_1_w_buffer_enqw$wget[1] ; + assign plic$axi4_slave_wstrb = + ssNoSynth_1_w_buffer_ff$EMPTY_N ? + ssNoSynth_1_w_buffer_ff$D_OUT[9:2] : + ssNoSynth_1_w_buffer_enqw$wget[9:2] ; + assign plic$axi4_slave_wuser = + ssNoSynth_1_w_buffer_ff$EMPTY_N ? + ssNoSynth_1_w_buffer_ff$D_OUT[0] : + ssNoSynth_1_w_buffer_enqw$wget[0] ; + assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_range[127:64] ; + assign plic$set_addr_map_addr_lim = + soc_map$m_plic_addr_range[127:64] + + soc_map$m_plic_addr_range[63:0] ; assign plic$set_verbosity_verbosity = 4'h0 ; assign plic$v_sources_0_m_interrupt_req_set_not_clear = core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; @@ -3082,77 +8173,1167 @@ module mkCoreW(CLK, core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; assign plic$EN_set_verbosity = 1'b0 ; assign plic$EN_show_PLIC_state = 1'b0 ; - assign plic$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign plic$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign plic$EN_server_reset_request_put = 1'b0 ; + assign plic$EN_server_reset_response_get = 1'b0 ; + assign plic$EN_set_addr_map = EN_start ; + assign plic$axi4_slave_awvalid = CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit ; + assign plic$axi4_slave_wvalid = CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit ; + assign plic$axi4_slave_arvalid = CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit ; // submodule proc - assign proc$debug_external_interrupt_req_set_not_clear = - debug_external_interrupt_req_set_not_clear ; - assign proc$hart0_csr_mem_server_request_put = 77'h0 ; + assign proc$debug_module_mem_server_araddr = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[92:29] : + ssNoSynth_2_ar_buffer_enqw$wget[92:29] ; + assign proc$debug_module_mem_server_arburst = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[17:16] : + ssNoSynth_2_ar_buffer_enqw$wget[17:16] ; + assign proc$debug_module_mem_server_arcache = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[14:11] : + ssNoSynth_2_ar_buffer_enqw$wget[14:11] ; + assign proc$debug_module_mem_server_arid = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[97:93] : + ssNoSynth_2_ar_buffer_enqw$wget[97:93] ; + assign proc$debug_module_mem_server_arlen = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[28:21] : + ssNoSynth_2_ar_buffer_enqw$wget[28:21] ; + assign proc$debug_module_mem_server_arlock = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[15] : + ssNoSynth_2_ar_buffer_enqw$wget[15] ; + assign proc$debug_module_mem_server_arprot = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[10:8] : + ssNoSynth_2_ar_buffer_enqw$wget[10:8] ; + assign proc$debug_module_mem_server_arqos = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[7:4] : + ssNoSynth_2_ar_buffer_enqw$wget[7:4] ; + assign proc$debug_module_mem_server_arregion = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[3:0] : + ssNoSynth_2_ar_buffer_enqw$wget[3:0] ; + assign proc$debug_module_mem_server_arsize = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[20:18] : + ssNoSynth_2_ar_buffer_enqw$wget[20:18] ; + assign proc$debug_module_mem_server_awaddr = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[92:29] : + ssNoSynth_2_aw_buffer_enqw$wget[92:29] ; + assign proc$debug_module_mem_server_awburst = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[17:16] : + ssNoSynth_2_aw_buffer_enqw$wget[17:16] ; + assign proc$debug_module_mem_server_awcache = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[14:11] : + ssNoSynth_2_aw_buffer_enqw$wget[14:11] ; + assign proc$debug_module_mem_server_awid = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[97:93] : + ssNoSynth_2_aw_buffer_enqw$wget[97:93] ; + assign proc$debug_module_mem_server_awlen = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[28:21] : + ssNoSynth_2_aw_buffer_enqw$wget[28:21] ; + assign proc$debug_module_mem_server_awlock = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[15] : + ssNoSynth_2_aw_buffer_enqw$wget[15] ; + assign proc$debug_module_mem_server_awprot = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[10:8] : + ssNoSynth_2_aw_buffer_enqw$wget[10:8] ; + assign proc$debug_module_mem_server_awqos = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[7:4] : + ssNoSynth_2_aw_buffer_enqw$wget[7:4] ; + assign proc$debug_module_mem_server_awregion = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[3:0] : + ssNoSynth_2_aw_buffer_enqw$wget[3:0] ; + assign proc$debug_module_mem_server_awsize = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[20:18] : + ssNoSynth_2_aw_buffer_enqw$wget[20:18] ; + assign proc$debug_module_mem_server_bready = ssNoSynth_2_b_dwReady$whas ; + assign proc$debug_module_mem_server_rready = ssNoSynth_2_r_dwReady$whas ; + assign proc$debug_module_mem_server_wdata = + ssNoSynth_2_w_buffer_ff$EMPTY_N ? + ssNoSynth_2_w_buffer_ff$D_OUT[73:10] : + ssNoSynth_2_w_buffer_enqw$wget[73:10] ; + assign proc$debug_module_mem_server_wlast = + ssNoSynth_2_w_buffer_ff$EMPTY_N ? + ssNoSynth_2_w_buffer_ff$D_OUT[1] : + ssNoSynth_2_w_buffer_enqw$wget[1] ; + assign proc$debug_module_mem_server_wstrb = + ssNoSynth_2_w_buffer_ff$EMPTY_N ? + ssNoSynth_2_w_buffer_ff$D_OUT[9:2] : + ssNoSynth_2_w_buffer_enqw$wget[9:2] ; + assign proc$debug_module_mem_server_wuser = + ssNoSynth_2_w_buffer_ff$EMPTY_N ? + ssNoSynth_2_w_buffer_ff$D_OUT[0] : + ssNoSynth_2_w_buffer_enqw$wget[0] ; + assign proc$hart0_csr_mem_server_request_put = + debug_module$hart0_csr_mem_client_request_get ; assign proc$hart0_fpr_mem_server_request_put = 70'h0 ; - assign proc$hart0_gpr_mem_server_request_put = 70'h0 ; - assign proc$hart0_put_other_req_put = 4'h0 ; - assign proc$hart0_server_run_halt_request_put = 1'b0 ; + assign proc$hart0_gpr_mem_server_request_put = + debug_module$hart0_gpr_mem_client_request_get ; + assign proc$hart0_put_other_req_put = debug_module$hart0_get_other_req_get ; + assign proc$hart0_run_halt_server_request_put = + debug_module$hart0_client_run_halt_request_get ; assign proc$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign proc$master0_arready = cpu_imem_master_arready ; - assign proc$master0_awready = cpu_imem_master_awready ; - assign proc$master0_bid = cpu_imem_master_bid ; - assign proc$master0_bresp = cpu_imem_master_bresp ; - assign proc$master0_bvalid = cpu_imem_master_bvalid ; - assign proc$master0_rdata = cpu_imem_master_rdata ; - assign proc$master0_rid = cpu_imem_master_rid ; - assign proc$master0_rlast = cpu_imem_master_rlast ; - assign proc$master0_rresp = cpu_imem_master_rresp ; - assign proc$master0_rvalid = cpu_imem_master_rvalid ; - assign proc$master0_wready = cpu_imem_master_wready ; - assign proc$master1_arready = fabric_2x3$v_from_masters_0_arready ; - assign proc$master1_awready = fabric_2x3$v_from_masters_0_awready ; - assign proc$master1_bid = fabric_2x3$v_from_masters_0_bid ; - assign proc$master1_bresp = fabric_2x3$v_from_masters_0_bresp ; - assign proc$master1_bvalid = fabric_2x3$v_from_masters_0_bvalid ; - assign proc$master1_rdata = fabric_2x3$v_from_masters_0_rdata ; - assign proc$master1_rid = fabric_2x3$v_from_masters_0_rid ; - assign proc$master1_rlast = fabric_2x3$v_from_masters_0_rlast ; - assign proc$master1_rresp = fabric_2x3$v_from_masters_0_rresp ; - assign proc$master1_rvalid = fabric_2x3$v_from_masters_0_rvalid ; - assign proc$master1_wready = fabric_2x3$v_from_masters_0_wready ; + assign proc$master0_arready = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut ; + assign proc$master0_awready = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut ; + assign proc$master0_bid = + tmp2_b_buffer_ff$EMPTY_N ? + tmp2_b_buffer_ff$D_OUT[6:2] : + tmp2_b_buffer_enqw$wget[6:2] ; + assign proc$master0_bresp = + tmp2_b_buffer_ff$EMPTY_N ? + tmp2_b_buffer_ff$D_OUT[1:0] : + tmp2_b_buffer_enqw$wget[1:0] ; + assign proc$master0_rdata = + tmp2_r_buffer_ff$EMPTY_N ? + tmp2_r_buffer_ff$D_OUT[67:4] : + tmp2_r_buffer_enqw$wget[67:4] ; + assign proc$master0_rid = + tmp2_r_buffer_ff$EMPTY_N ? + tmp2_r_buffer_ff$D_OUT[72:68] : + tmp2_r_buffer_enqw$wget[72:68] ; + assign proc$master0_rlast = + tmp2_r_buffer_ff$EMPTY_N ? + tmp2_r_buffer_ff$D_OUT[1] : + tmp2_r_buffer_enqw$wget[1] ; + assign proc$master0_rresp = + tmp2_r_buffer_ff$EMPTY_N ? + tmp2_r_buffer_ff$D_OUT[3:2] : + tmp2_r_buffer_enqw$wget[3:2] ; + assign proc$master0_ruser = + tmp2_r_buffer_ff$EMPTY_N ? + tmp2_r_buffer_ff$D_OUT[0] : + tmp2_r_buffer_enqw$wget[0] ; + assign proc$master0_wready = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut ; + assign proc$master1_arready = tmp0_ar_dwReady$whas ; + assign proc$master1_awready = tmp0_aw_dwReady$whas ; + assign proc$master1_bid = + tmp0_b_buffer_ff$EMPTY_N ? + tmp0_b_buffer_ff$D_OUT[5:2] : + tmp0_b_buffer_enqw$wget[5:2] ; + assign proc$master1_bresp = + tmp0_b_buffer_ff$EMPTY_N ? + tmp0_b_buffer_ff$D_OUT[1:0] : + tmp0_b_buffer_enqw$wget[1:0] ; + assign proc$master1_rdata = + tmp0_r_buffer_ff$EMPTY_N ? + tmp0_r_buffer_ff$D_OUT[67:4] : + tmp0_r_buffer_enqw$wget[67:4] ; + assign proc$master1_rid = + tmp0_r_buffer_ff$EMPTY_N ? + tmp0_r_buffer_ff$D_OUT[71:68] : + tmp0_r_buffer_enqw$wget[71:68] ; + assign proc$master1_rlast = + tmp0_r_buffer_ff$EMPTY_N ? + tmp0_r_buffer_ff$D_OUT[1] : + tmp0_r_buffer_enqw$wget[1] ; + assign proc$master1_rresp = + tmp0_r_buffer_ff$EMPTY_N ? + tmp0_r_buffer_ff$D_OUT[3:2] : + tmp0_r_buffer_enqw$wget[3:2] ; + assign proc$master1_ruser = + tmp0_r_buffer_ff$EMPTY_N ? + tmp0_r_buffer_ff$D_OUT[0] : + tmp0_r_buffer_enqw$wget[0] ; + assign proc$master1_wready = tmp0_w_dwReady$whas ; assign proc$non_maskable_interrupt_req_set_not_clear = 1'd0 ; assign proc$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; assign proc$set_verbosity_verbosity = set_verbosity_verbosity ; - assign proc$start_fromhostAddr = rg_fromhost_addr ; + assign proc$start_fromhostAddr = + MUX_proc$start_1__SEL_1 ? + rg_fromhost_addr : + start_fromhost_addr ; assign proc$start_startpc = 64'h0000000070000000 ; - assign proc$start_tohostAddr = rg_tohost_addr ; - assign proc$EN_hart0_server_reset_request_put = CAN_FIRE_RL_rl_once ; - assign proc$EN_hart0_server_reset_response_get = - CAN_FIRE_RL_rl_hart0_server_reset ; - assign proc$EN_start = CAN_FIRE_RL_rl_hart0_server_reset ; + assign proc$start_tohostAddr = + MUX_proc$start_1__SEL_1 ? rg_tohost_addr : start_tohost_addr ; + assign proc$EN_start = + WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1 || + EN_start ; + assign proc$master0_bvalid = CAN_FIRE_RL_tmp2_b_forwardFlit ; + assign proc$master0_rvalid = CAN_FIRE_RL_tmp2_r_forwardFlit ; + assign proc$master1_bvalid = CAN_FIRE_RL_tmp0_b_forwardFlit ; + assign proc$master1_rvalid = CAN_FIRE_RL_tmp0_r_forwardFlit ; assign proc$EN_set_verbosity = EN_set_verbosity ; - assign proc$EN_trace_data_out_get = CAN_FIRE_RL_merge_cpu_trace_data ; - assign proc$EN_hart0_server_run_halt_request_put = 1'b0 ; - assign proc$EN_hart0_server_run_halt_response_get = 1'd1 ; - assign proc$EN_hart0_put_other_req_put = 1'b0 ; - assign proc$EN_hart0_gpr_mem_server_request_put = 1'b0 ; - assign proc$EN_hart0_gpr_mem_server_response_get = 1'b0 ; + assign proc$debug_module_mem_server_awvalid = + CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit ; + assign proc$debug_module_mem_server_wvalid = + CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit ; + assign proc$debug_module_mem_server_arvalid = + CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit ; + assign proc$EN_hart0_run_halt_server_request_put = + CAN_FIRE_RL_ClientServerRequest ; + assign proc$EN_hart0_run_halt_server_response_get = + CAN_FIRE_RL_ClientServerResponse ; + assign proc$EN_hart0_gpr_mem_server_request_put = + CAN_FIRE_RL_ClientServerRequest_1 ; + assign proc$EN_hart0_gpr_mem_server_response_get = + CAN_FIRE_RL_ClientServerResponse_1 ; assign proc$EN_hart0_fpr_mem_server_request_put = 1'b0 ; assign proc$EN_hart0_fpr_mem_server_response_get = 1'b0 ; - assign proc$EN_hart0_csr_mem_server_request_put = 1'b0 ; - assign proc$EN_hart0_csr_mem_server_response_get = 1'b0 ; + assign proc$EN_hart0_csr_mem_server_request_put = + CAN_FIRE_RL_ClientServerRequest_2 ; + assign proc$EN_hart0_csr_mem_server_response_get = + CAN_FIRE_RL_ClientServerResponse_2 ; + assign proc$EN_hart0_put_other_req_put = + debug_module$RDY_hart0_get_other_req_get ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - // submodule tv_encode - assign tv_encode$trace_data_in_put = f_trace_data_merged$D_OUT ; - assign tv_encode$EN_reset = 1'b0 ; - assign tv_encode$EN_trace_data_in_put = CAN_FIRE_RL_mkConnectionGetPut ; - assign tv_encode$EN_tv_vb_out_get = EN_tv_verifier_info_get_get ; + // submodule ssNoSynth_0_ar_buffer_ff + assign ssNoSynth_0_ar_buffer_ff$D_IN = ssNoSynth_0_ar_buffer_enqw$wget ; + assign ssNoSynth_0_ar_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue ; + assign ssNoSynth_0_ar_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue ; + assign ssNoSynth_0_ar_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_0_ar_buffer_firstValid + assign ssNoSynth_0_ar_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_ar_buffer_firstValid$EN = + WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit ; + + // submodule ssNoSynth_0_aw_buffer_ff + assign ssNoSynth_0_aw_buffer_ff$D_IN = split_0_doPut$wget[171:74] ; + assign ssNoSynth_0_aw_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue ; + assign ssNoSynth_0_aw_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue ; + assign ssNoSynth_0_aw_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_0_aw_buffer_firstValid + assign ssNoSynth_0_aw_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_aw_buffer_firstValid$EN = + WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit ; + + // submodule ssNoSynth_0_w_buffer_ff + assign ssNoSynth_0_w_buffer_ff$D_IN = split_0_doPut$wget[73:0] ; + assign ssNoSynth_0_w_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue ; + assign ssNoSynth_0_w_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue ; + assign ssNoSynth_0_w_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_0_w_buffer_firstValid + assign ssNoSynth_0_w_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_w_buffer_firstValid$EN = + WILL_FIRE_RL_ssNoSynth_0_w_dropFlit ; + + // submodule ssNoSynth_1_ar_buffer_ff + assign ssNoSynth_1_ar_buffer_ff$D_IN = ssNoSynth_1_ar_buffer_enqw$wget ; + assign ssNoSynth_1_ar_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue ; + assign ssNoSynth_1_ar_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue ; + assign ssNoSynth_1_ar_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_1_ar_buffer_firstValid + assign ssNoSynth_1_ar_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_ar_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit ; + + // submodule ssNoSynth_1_aw_buffer_ff + assign ssNoSynth_1_aw_buffer_ff$D_IN = split_1_doPut$wget[171:74] ; + assign ssNoSynth_1_aw_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue ; + assign ssNoSynth_1_aw_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue ; + assign ssNoSynth_1_aw_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_1_aw_buffer_firstValid + assign ssNoSynth_1_aw_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_aw_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit ; + + // submodule ssNoSynth_1_w_buffer_ff + assign ssNoSynth_1_w_buffer_ff$D_IN = split_1_doPut$wget[73:0] ; + assign ssNoSynth_1_w_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue ; + assign ssNoSynth_1_w_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue ; + assign ssNoSynth_1_w_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_1_w_buffer_firstValid + assign ssNoSynth_1_w_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_w_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_w_dropFlit ; + + // submodule ssNoSynth_2_ar_buffer_ff + assign ssNoSynth_2_ar_buffer_ff$D_IN = ssNoSynth_2_ar_buffer_enqw$wget ; + assign ssNoSynth_2_ar_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue ; + assign ssNoSynth_2_ar_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue ; + assign ssNoSynth_2_ar_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_ar_buffer_firstValid + assign ssNoSynth_2_ar_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_ar_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit ; + + // submodule ssNoSynth_2_aw_buffer_ff + assign ssNoSynth_2_aw_buffer_ff$D_IN = split_2_doPut$wget[171:74] ; + assign ssNoSynth_2_aw_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue ; + assign ssNoSynth_2_aw_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue ; + assign ssNoSynth_2_aw_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_aw_buffer_firstValid + assign ssNoSynth_2_aw_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_aw_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit ; + + // submodule ssNoSynth_2_w_buffer_ff + assign ssNoSynth_2_w_buffer_ff$D_IN = split_2_doPut$wget[73:0] ; + assign ssNoSynth_2_w_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue ; + assign ssNoSynth_2_w_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue ; + assign ssNoSynth_2_w_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_w_buffer_firstValid + assign ssNoSynth_2_w_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_w_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_w_dropFlit ; + + // submodule tagController_tmp_awreqff + assign tagController_tmp_awreqff$D_IN = + tagController_tmp_shimSlave_awff_rv$port1__read[97:0] ; + assign tagController_tmp_awreqff$ENQ = + CAN_FIRE_RL_tagController_tmp_getCacheAW ; + assign tagController_tmp_awreqff$DEQ = + WILL_FIRE_RL_tagController_tmp_passCacheWrite && + tagController_tmp_shimSlave_wff_rv$port1__read[1] ; + assign tagController_tmp_awreqff$CLR = 1'b0 ; + + // submodule tagController_tmp_newRst + assign tagController_tmp_newRst$ASSERT_IN = + CAN_FIRE_RL_tagController_tmp_propagateReset ; + + // submodule tagController_tmp_tagCon + assign tagController_tmp_tagCon$cache_request_put_val = + WILL_FIRE_RL_tagController_tmp_passCacheWrite ? + MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_1 : + MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_2 ; + assign tagController_tmp_tagCon$memory_response_put_val = + WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite ? + MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_1 : + MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_2 ; + assign tagController_tmp_tagCon$EN_cache_request_put = + WILL_FIRE_RL_tagController_tmp_passCacheWrite || + WILL_FIRE_RL_tagController_tmp_passCacheRead ; + assign tagController_tmp_tagCon$EN_cache_response_get = + CAN_FIRE_RL_tagController_tmp_passCacheResponse ; + assign tagController_tmp_tagCon$EN_memory_request_get = + CAN_FIRE_RL_tagController_tmp_passMemoryRequest ; + assign tagController_tmp_tagCon$EN_memory_response_put = + WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite || + WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + + // submodule tmp0_b_buffer_ff + assign tmp0_b_buffer_ff$D_IN = tmp0_b_buffer_enqw$wget ; + assign tmp0_b_buffer_ff$ENQ = CAN_FIRE_RL_tmp0_b_buffer_enqueue ; + assign tmp0_b_buffer_ff$DEQ = CAN_FIRE_RL_tmp0_b_buffer_dequeue ; + assign tmp0_b_buffer_ff$CLR = 1'b0 ; + + // submodule tmp0_b_buffer_firstValid + assign tmp0_b_buffer_firstValid$D_IN = 1'd1 ; + assign tmp0_b_buffer_firstValid$EN = CAN_FIRE_RL_tmp0_b_dropFlit ; + + // submodule tmp0_r_buffer_ff + assign tmp0_r_buffer_ff$D_IN = tmp0_r_buffer_enqw$wget ; + assign tmp0_r_buffer_ff$ENQ = CAN_FIRE_RL_tmp0_r_buffer_enqueue ; + assign tmp0_r_buffer_ff$DEQ = CAN_FIRE_RL_tmp0_r_buffer_dequeue ; + assign tmp0_r_buffer_ff$CLR = 1'b0 ; + + // submodule tmp0_r_buffer_firstValid + assign tmp0_r_buffer_firstValid$D_IN = 1'd1 ; + assign tmp0_r_buffer_firstValid$EN = CAN_FIRE_RL_tmp0_r_dropFlit ; + + // submodule tmp2_b_buffer_ff + assign tmp2_b_buffer_ff$D_IN = + tagController_tmp_shimSlave_bff_rv$port1__read[6:0] ; + assign tmp2_b_buffer_ff$ENQ = CAN_FIRE_RL_tmp2_b_buffer_enqueue ; + assign tmp2_b_buffer_ff$DEQ = CAN_FIRE_RL_tmp2_b_buffer_dequeue ; + assign tmp2_b_buffer_ff$CLR = 1'b0 ; + + // submodule tmp2_b_buffer_firstValid + assign tmp2_b_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_b_buffer_firstValid$EN = CAN_FIRE_RL_tmp2_b_dropFlit ; + + // submodule tmp2_r_buffer_ff + assign tmp2_r_buffer_ff$D_IN = + tagController_tmp_shimSlave_rff_rv$port1__read[72:0] ; + assign tmp2_r_buffer_ff$ENQ = CAN_FIRE_RL_tmp2_r_buffer_enqueue ; + assign tmp2_r_buffer_ff$DEQ = CAN_FIRE_RL_tmp2_r_buffer_dequeue ; + assign tmp2_r_buffer_ff$CLR = 1'b0 ; + + // submodule tmp2_r_buffer_firstValid + assign tmp2_r_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_r_buffer_firstValid$EN = CAN_FIRE_RL_tmp2_r_dropFlit ; + + // submodule uncached_mem_shim_arff + assign uncached_mem_shim_arff$D_IN = + ssNoSynth_0_ar_buffer_ff$EMPTY_N ? + ssNoSynth_0_ar_buffer_ff$D_OUT : + ssNoSynth_0_ar_buffer_enqw$wget ; + assign uncached_mem_shim_arff$ENQ = + WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit && + uncached_mem_shim_arff$FULL_N ; + assign uncached_mem_shim_arff$DEQ = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop ; + assign uncached_mem_shim_arff$CLR = 1'b0 ; + + // submodule uncached_mem_shim_awff + assign uncached_mem_shim_awff$D_IN = + ssNoSynth_0_aw_buffer_ff$EMPTY_N ? + ssNoSynth_0_aw_buffer_ff$D_OUT : + split_0_doPut$wget[171:74] ; + assign uncached_mem_shim_awff$ENQ = + WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit && + uncached_mem_shim_awff$FULL_N ; + assign uncached_mem_shim_awff$DEQ = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop ; + assign uncached_mem_shim_awff$CLR = 1'b0 ; + + // submodule uncached_mem_shim_bff + assign uncached_mem_shim_bff$D_IN = + ug_uncached_mem_shim_master_u_b_putWire$wget[6:0] ; + assign uncached_mem_shim_bff$ENQ = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut ; + assign uncached_mem_shim_bff$DEQ = + uncached_mem_shim_bff$EMPTY_N && ssNoSynth_0_b_dwReady$whas ; + assign uncached_mem_shim_bff$CLR = 1'b0 ; + + // submodule uncached_mem_shim_rff + assign uncached_mem_shim_rff$D_IN = + { ug_uncached_mem_shim_master_u_r_putWire$wget[71:0], 1'd0 } ; + assign uncached_mem_shim_rff$ENQ = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut ; + assign uncached_mem_shim_rff$DEQ = + uncached_mem_shim_rff$EMPTY_N && ssNoSynth_0_r_dwReady$whas ; + assign uncached_mem_shim_rff$CLR = 1'b0 ; + + // submodule uncached_mem_shim_wff + assign uncached_mem_shim_wff$D_IN = + ssNoSynth_0_w_buffer_ff$EMPTY_N ? + ssNoSynth_0_w_buffer_ff$D_OUT : + split_0_doPut$wget[73:0] ; + assign uncached_mem_shim_wff$ENQ = + WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit && + uncached_mem_shim_wff$FULL_N ; + assign uncached_mem_shim_wff$DEQ = + CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop ; + assign uncached_mem_shim_wff$CLR = 1'b0 ; + + // remaining internal signals + assign IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1221 = + (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1209 ? + 2'd1 : + 2'd0) + + (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1214 ? + 2'd1 : + 2'd0) + + ((proc$master1_awaddr[63:40] == 24'd0 && + !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1194 && + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1197) ? + 2'd1 : + 2'd0) ; + assign IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1325 = + (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1313 ? + 2'd1 : + 2'd0) + + (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1318 ? + 2'd1 : + 2'd0) + + ((debug_module$master_awaddr[63:40] == 24'd0 && + !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302 && + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1304) ? + 2'd1 : + 2'd0) ; + assign IF_NOT_ifcs_0_1_innerRoute_first__096_BIT_1_10_ETC___d2118 = + (!ifcs_0_1_innerRoute$D_OUT[1] || + !ssNoSynth_1_ar_buffer_ff$FULL_N) ? + ifcs_0_1_innerRoute$D_OUT[2] && + ssNoSynth_2_ar_buffer_ff$FULL_N : + ifcs_0_1_innerRoute$D_OUT[1] ; + assign IF_NOT_ifcs_0_innerRoute_first__443_BIT_1_452__ETC___d1465 = + (!ifcs_0_innerRoute$D_OUT[1] || + !IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1436) ? + ifcs_0_innerRoute$D_OUT[2] && + IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1437 : + ifcs_0_innerRoute$D_OUT[1] ; + assign IF_NOT_ifcs_1_1_innerRoute_first__125_BIT_1_12_ETC___d2134 = + (!ifcs_1_1_innerRoute$D_OUT[1] || + !ssNoSynth_1_ar_buffer_ff$FULL_N) ? + ifcs_1_1_innerRoute$D_OUT[2] && + ssNoSynth_2_ar_buffer_ff$FULL_N : + ifcs_1_1_innerRoute$D_OUT[1] ; + assign IF_NOT_ifcs_1_innerRoute_first__472_BIT_1_476__ETC___d1481 = + (!ifcs_1_innerRoute$D_OUT[1] || + !IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1436) ? + ifcs_1_innerRoute$D_OUT[2] && + IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1437 : + ifcs_1_innerRoute$D_OUT[1] ; + assign IF_SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_3_ETC___d2370 = + (SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_328__ETC___d2339 || + SEXT_arbiter_1_1_lastSelect_1_330_331_BIT_0_33_ETC___d2345 || + SEXT_arbiter_1_1_firstHot_335_336_BIT_0_337_AN_ETC___d2351) ? + x__h94994 | y__h94995 : + arbiter_1_1_lastSelect ; + assign IF_SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_3_ETC___d2376 = + (SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_328__ETC___d2339 || + SEXT_arbiter_1_1_lastSelect_1_330_331_BIT_0_33_ETC___d2345 || + SEXT_arbiter_1_1_firstHot_335_336_BIT_0_337_AN_ETC___d2351) ? + x__h95182 | y__h95183 : + arbiter_1_1_lastSelect_1 ; + assign IF_SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_3_ETC___d2382 = + (SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_328__ETC___d2339 || + SEXT_arbiter_1_1_lastSelect_1_330_331_BIT_0_33_ETC___d2345 || + SEXT_arbiter_1_1_firstHot_335_336_BIT_0_337_AN_ETC___d2351) ? + x__h95363 | y__h95364 : + arbiter_1_1_firstHot ; + assign IF_SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_1_ETC___d2170 = + (SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_148__ETC___d2154 || + SEXT_arbiter_1_firstHot_1_150_151_BIT_0_152_AN_ETC___d2158) ? + x__h83052 | y__h83053 : + arbiter_1_lastSelect_2 ; + assign IF_SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_1_ETC___d2174 = + (SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_148__ETC___d2154 || + SEXT_arbiter_1_firstHot_1_150_151_BIT_0_152_AN_ETC___d2158) ? + x__h83193 | y__h83194 : + arbiter_1_firstHot_1 ; + assign IF_SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_ETC___d1727 = + (SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_AN_ETC___d1696 || + SEXT_arbiter_1_lastSelect_1_687_688_BIT_0_689__ETC___d1702 || + SEXT_arbiter_1_firstHot_692_693_BIT_0_694_AND__ETC___d1708) ? + x__h63586 | y__h63587 : + arbiter_1_lastSelect ; + assign IF_SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_ETC___d1733 = + (SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_AN_ETC___d1696 || + SEXT_arbiter_1_lastSelect_1_687_688_BIT_0_689__ETC___d1702 || + SEXT_arbiter_1_firstHot_692_693_BIT_0_694_AND__ETC___d1708) ? + x__h63774 | y__h63775 : + arbiter_1_lastSelect_1 ; + assign IF_SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_ETC___d1739 = + (SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_AN_ETC___d1696 || + SEXT_arbiter_1_lastSelect_1_687_688_BIT_0_689__ETC___d1702 || + SEXT_arbiter_1_firstHot_692_693_BIT_0_694_AND__ETC___d1708) ? + x__h63955 | y__h63956 : + arbiter_1_firstHot ; + assign IF_SEXT_arbiter_lastSelect_493_494_BIT_0_495_A_ETC___d1517 = + (SEXT_arbiter_lastSelect_493_494_BIT_0_495_AND__ETC___d1501 || + SEXT_arbiter_firstHot_497_498_BIT_0_499_AND_re_ETC___d1505) ? + x__h49103 | y__h49104 : + arbiter_lastSelect ; + assign IF_SEXT_arbiter_lastSelect_493_494_BIT_0_495_A_ETC___d1521 = + (SEXT_arbiter_lastSelect_493_494_BIT_0_495_AND__ETC___d1501 || + SEXT_arbiter_firstHot_497_498_BIT_0_499_AND_re_ETC___d1505) ? + x__h49244 | y__h49245 : + arbiter_firstHot ; + assign IF_debug_module_master_ar_araddr__944_BITS_63__ETC___d1970 = + (debug_module_master_ar_araddr__944_BITS_63_TO__ETC___d1958 ? + 2'd1 : + 2'd0) + + (debug_module_master_ar_araddr__944_BITS_63_TO__ETC___d1963 ? + 2'd1 : + 2'd0) + + ((debug_module$master_araddr[63:40] == 24'd0 && + !debug_module_master_ar_araddr__944_ULT_soc_map_ETC___d1947 && + debug_module_master_ar_araddr__944_MINUS_soc_m_ETC___d1949) ? + 2'd1 : + 2'd0) ; + assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 = + ((merged_0_flitLeft == 8'd0) ? + !proc$master1_awvalid || !proc$master1_wvalid : + !proc$master1_wvalid) || + merged_0_flitLeft != 8'd0 ; + assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1255 = + (IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 || + proc$master1_awvalid) && + (merged_0_flitLeft != 8'd0 || + !ifcs_0_noRoute_inner_pendingReq && proc$master1_awvalid) ; + assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 = + (merged_0_flitLeft == 8'd0) ? + proc$master1_awvalid && proc$master1_wvalid : + proc$master1_wvalid ; + assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1194 = + proc$master1_awaddr < + soc_map$m_mem0_controller_addr_range[127:64] ; + assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1197 = + x__h37445 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1202 = + proc$master1_awaddr < soc_map$m_plic_addr_range[127:64] ; + assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1205 = + x__h37480 < soc_map$m_plic_addr_range[63:0] ; + assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1209 = + proc$master1_awaddr[63:40] == 24'd0 && + (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1194 || + !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1197) && + (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1202 || + !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1205) ; + assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1214 = + proc$master1_awaddr[63:40] == 24'd0 && + (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1194 || + !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1197) && + !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1202 && + IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1205 ; + assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1290 = + ((merged_1_flitLeft == 8'd0) ? + !debug_module$master_awvalid || !debug_module$master_wvalid : + !debug_module$master_wvalid) || + merged_1_flitLeft != 8'd0 ; + assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1360 = + (IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1290 || + debug_module$master_awvalid) && + (merged_1_flitLeft != 8'd0 || + !ifcs_1_noRoute_inner_pendingReq && + debug_module$master_awvalid) ; + assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1283 = + (merged_1_flitLeft == 8'd0) ? + debug_module$master_awvalid && debug_module$master_wvalid : + debug_module$master_wvalid ; + assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302 = + debug_module$master_awaddr < + soc_map$m_mem0_controller_addr_range[127:64] ; + assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1304 = + x__h40257 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1307 = + debug_module$master_awaddr < soc_map$m_plic_addr_range[127:64] ; + assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1309 = + x__h40282 < soc_map$m_plic_addr_range[63:0] ; + assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1313 = + debug_module$master_awaddr[63:40] == 24'd0 && + (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302 || + !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1304) && + (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1307 || + !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1309) ; + assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1318 = + debug_module$master_awaddr[63:40] == 24'd0 && + (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302 || + !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1304) && + !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1307 && + IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1309 ; + assign IF_proc_master1_ar_araddr__852_BITS_63_TO_40_8_ETC___d1878 = + (proc_master1_ar_araddr__852_BITS_63_TO_40_853__ETC___d1866 ? + 2'd1 : + 2'd0) + + (proc_master1_ar_araddr__852_BITS_63_TO_40_853__ETC___d1871 ? + 2'd1 : + 2'd0) + + ((proc$master1_araddr[63:40] == 24'd0 && + !proc_master1_ar_araddr__852_ULT_soc_map_m_mem0_ETC___d1855 && + proc_master1_ar_araddr__852_MINUS_soc_map_m_me_ETC___d1857) ? + 2'd1 : + 2'd0) ; + assign IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1435 = + (split_0_flitLeft == 8'd0) ? + ssNoSynth_0_aw_buffer_ff$FULL_N && + ssNoSynth_0_w_buffer_ff$FULL_N : + ssNoSynth_0_w_buffer_ff$FULL_N ; + assign IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1436 = + (split_1_flitLeft == 8'd0) ? + ssNoSynth_1_aw_buffer_ff$FULL_N && + ssNoSynth_1_w_buffer_ff$FULL_N : + ssNoSynth_1_w_buffer_ff$FULL_N ; + assign IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1437 = + (split_2_flitLeft == 8'd0) ? + ssNoSynth_2_aw_buffer_ff$FULL_N && + ssNoSynth_2_w_buffer_ff$FULL_N : + ssNoSynth_2_w_buffer_ff$FULL_N ; + assign SEXT_SEXT_arbiter_1_1_firstHot_335_336_BIT_0_3_ETC__q22 = + {2{SEXT_arbiter_1_1_firstHot_335_336_BIT_0_337_AN_ETC___d2351}} ; + assign SEXT_SEXT_arbiter_1_firstHot_1_150_151_BIT_0_1_ETC__q17 = + {2{SEXT_arbiter_1_firstHot_1_150_151_BIT_0_152_AN_ETC___d2158}} ; + assign SEXT_SEXT_arbiter_1_firstHot_692_693_BIT_0_694_ETC__q12 = + {2{SEXT_arbiter_1_firstHot_692_693_BIT_0_694_AND__ETC___d1708}} ; + assign SEXT_SEXT_arbiter_firstHot_497_498_BIT_0_499_A_ETC__q7 = + {2{SEXT_arbiter_firstHot_497_498_BIT_0_499_AND_re_ETC___d1505}} ; + assign SEXT_arbiter_1_1_firstHot_335_336_BIT_0_337_AN_ETC___d2351 = + x__h94522 | y__h94523 ; + assign SEXT_arbiter_1_1_firstHot__q19 = {2{arbiter_1_1_firstHot}} ; + assign SEXT_arbiter_1_1_lastSelect_1_330_331_BIT_0_33_ETC___d2345 = + x__h94386 | y__h94387 ; + assign SEXT_arbiter_1_1_lastSelect_1__q21 = {2{arbiter_1_1_lastSelect_1}} ; + assign SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_328__ETC___d2339 = + x__h94235 | y__h94236 ; + assign SEXT_arbiter_1_1_lastSelect__q20 = {2{arbiter_1_1_lastSelect}} ; + assign SEXT_arbiter_1_firstHot_1_150_151_BIT_0_152_AN_ETC___d2158 = + x__h82687 | y__h82688 ; + assign SEXT_arbiter_1_firstHot_1__q15 = {2{arbiter_1_firstHot_1}} ; + assign SEXT_arbiter_1_firstHot_692_693_BIT_0_694_AND__ETC___d1708 = + x__h63114 | y__h63115 ; + assign SEXT_arbiter_1_firstHot__q9 = {2{arbiter_1_firstHot}} ; + assign SEXT_arbiter_1_lastSelect_1_687_688_BIT_0_689__ETC___d1702 = + x__h62978 | y__h62979 ; + assign SEXT_arbiter_1_lastSelect_1__q11 = {2{arbiter_1_lastSelect_1}} ; + assign SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_148__ETC___d2154 = + x__h82584 | y__h82585 ; + assign SEXT_arbiter_1_lastSelect_2__q16 = {2{arbiter_1_lastSelect_2}} ; + assign SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_AN_ETC___d1696 = + x__h62827 | y__h62828 ; + assign SEXT_arbiter_1_lastSelect__q10 = {2{arbiter_1_lastSelect}} ; + assign SEXT_arbiter_firstHot_497_498_BIT_0_499_AND_re_ETC___d1505 = + x__h48738 | y__h48739 ; + assign SEXT_arbiter_firstHot__q5 = {2{arbiter_firstHot}} ; + assign SEXT_arbiter_lastSelect_493_494_BIT_0_495_AND__ETC___d1501 = + x__h48635 | y__h48636 ; + assign SEXT_arbiter_lastSelect__q6 = {2{arbiter_lastSelect}} ; + assign SEXT_x3111__q18 = {2{x__h83111}} ; + assign SEXT_x3648__q13 = {2{x__h63648}} ; + assign SEXT_x3682__q14 = {2{x__h63682}} ; + assign SEXT_x5056__q23 = {2{x__h95056}} ; + assign SEXT_x5090__q24 = {2{x__h95090}} ; + assign SEXT_x9162__q8 = {2{x__h49162}} ; + assign _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245 = + x__h12609 + y__h12610 ; + assign a_awid__h38608 = { 1'd0, proc$master1_awid } ; + assign a_awid__h41374 = { 1'd1, debug_module$master_awid } ; + assign araddr__h15532 = + { 24'd0, tagController_tmp_tagCon$memory_request_get[140:101] } ; + assign arcache__h15537 = + tagController_tmp_tagCon$memory_request_get[8] ? 4'd0 : 4'd15 ; + assign arlen__h15533 = + { 5'd0, tagController_tmp_tagCon$memory_request_get[5:3] } ; + assign aw_awaddr__h10800 = tmp__h10583 + { 60'd0, x__h10875 } ; + assign aw_awsize_val__h12539 = + _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[0] ? + 3'd0 : + (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[1] ? + 3'd1 : + (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[2] ? + 3'd2 : + (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[3] ? + 3'd3 : + 3'd4))) ; + assign debug_module_master_ar_araddr__944_BITS_63_TO__ETC___d1958 = + debug_module$master_araddr[63:40] == 24'd0 && + (debug_module_master_ar_araddr__944_ULT_soc_map_ETC___d1947 || + !debug_module_master_ar_araddr__944_MINUS_soc_m_ETC___d1949) && + (debug_module_master_ar_araddr__944_ULT_soc_map_ETC___d1952 || + !debug_module_master_ar_araddr__944_MINUS_soc_m_ETC___d1954) ; + assign debug_module_master_ar_araddr__944_BITS_63_TO__ETC___d1963 = + debug_module$master_araddr[63:40] == 24'd0 && + (debug_module_master_ar_araddr__944_ULT_soc_map_ETC___d1947 || + !debug_module_master_ar_araddr__944_MINUS_soc_m_ETC___d1949) && + !debug_module_master_ar_araddr__944_ULT_soc_map_ETC___d1952 && + debug_module_master_ar_araddr__944_MINUS_soc_m_ETC___d1954 ; + assign debug_module_master_ar_araddr__944_MINUS_soc_m_ETC___d1949 = + x__h74407 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign debug_module_master_ar_araddr__944_MINUS_soc_m_ETC___d1954 = + x__h74432 < soc_map$m_plic_addr_range[63:0] ; + assign debug_module_master_ar_araddr__944_ULT_soc_map_ETC___d1947 = + debug_module$master_araddr < + soc_map$m_mem0_controller_addr_range[127:64] ; + assign debug_module_master_ar_araddr__944_ULT_soc_map_ETC___d1952 = + debug_module$master_araddr < soc_map$m_plic_addr_range[127:64] ; + assign fatReq_arid__h72495 = { 1'd0, proc$master1_arid } ; + assign fatReq_arid__h74960 = { 1'd1, debug_module$master_arid } ; + assign proc_master1_ar_araddr__852_BITS_63_TO_40_853__ETC___d1866 = + proc$master1_araddr[63:40] == 24'd0 && + (proc_master1_ar_araddr__852_ULT_soc_map_m_mem0_ETC___d1855 || + !proc_master1_ar_araddr__852_MINUS_soc_map_m_me_ETC___d1857) && + (proc_master1_ar_araddr__852_ULT_soc_map_m_plic_ETC___d1860 || + !proc_master1_ar_araddr__852_MINUS_soc_map_m_pl_ETC___d1862) ; + assign proc_master1_ar_araddr__852_BITS_63_TO_40_853__ETC___d1871 = + proc$master1_araddr[63:40] == 24'd0 && + (proc_master1_ar_araddr__852_ULT_soc_map_m_mem0_ETC___d1855 || + !proc_master1_ar_araddr__852_MINUS_soc_map_m_me_ETC___d1857) && + !proc_master1_ar_araddr__852_ULT_soc_map_m_plic_ETC___d1860 && + proc_master1_ar_araddr__852_MINUS_soc_map_m_pl_ETC___d1862 ; + assign proc_master1_ar_araddr__852_MINUS_soc_map_m_me_ETC___d1857 = + x__h71927 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign proc_master1_ar_araddr__852_MINUS_soc_map_m_pl_ETC___d1862 = + x__h71952 < soc_map$m_plic_addr_range[63:0] ; + assign proc_master1_ar_araddr__852_ULT_soc_map_m_mem0_ETC___d1855 = + proc$master1_araddr < + soc_map$m_mem0_controller_addr_range[127:64] ; + assign proc_master1_ar_araddr__852_ULT_soc_map_m_plic_ETC___d1860 = + proc$master1_araddr < soc_map$m_plic_addr_range[127:64] ; + assign reqWires_1_0_whas__669_AND_reqWires_1_0_wget___ETC___d1679 = + CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget || + CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget || + CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget ; + assign reqWires_1_1_0_whas__312_AND_reqWires_1_1_0_wg_ETC___d2322 = + CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget || + CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget || + CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget ; + assign split_0_doPut_whas__086_AND_split_0_doPut_wget_ETC___d1093 = + CAN_FIRE_RL_sink_selected && + (split_0_doPut$wget[172] || + ssNoSynth_0_aw_buffer_ff$FULL_N && + ssNoSynth_0_w_buffer_ff$FULL_N) ; + assign split_1_doPut_whas__115_AND_split_1_doPut_wget_ETC___d1122 = + CAN_FIRE_RL_sink_selected_1 && + (split_1_doPut$wget[172] || + ssNoSynth_1_aw_buffer_ff$FULL_N && + ssNoSynth_1_w_buffer_ff$FULL_N) ; + assign split_2_doPut_whas__144_AND_split_2_doPut_wget_ETC___d1151 = + CAN_FIRE_RL_sink_selected_2 && + (split_2_doPut$wget[172] || + ssNoSynth_2_aw_buffer_ff$FULL_N && + ssNoSynth_2_w_buffer_ff$FULL_N) ; + assign state_1_1_143_AND_activeSource_1_0_1_210_211_A_ETC___d2213 = + state_1_1 && activeSource_1_0_1 && ifcs_0_1_innerRoute$EMPTY_N && + ((!ifcs_0_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_ar_buffer_ff$FULL_N) ? + IF_NOT_ifcs_0_1_innerRoute_first__096_BIT_1_10_ETC___d2118 : + ifcs_0_1_innerRoute$D_OUT[0]) ; + assign state_1_1_143_AND_activeSource_1_1_1_250_251_A_ETC___d2253 = + state_1_1 && activeSource_1_1_1 && ifcs_1_1_innerRoute$EMPTY_N && + ((!ifcs_1_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_ar_buffer_ff$FULL_N) ? + IF_NOT_ifcs_1_1_innerRoute_first__125_BIT_1_12_ETC___d2134 : + ifcs_1_1_innerRoute$D_OUT[0]) ; + assign state_1_1_1_323_AND_activeSource_1_1_0_417_418_ETC___d2420 = + state_1_1_1 && activeSource_1_1_0 && + ifcs_0_1_routeBack$EMPTY_N && + ((!ifcs_0_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_0_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_0_1_routeBack$D_OUT[0]) ; + assign state_1_1_1_323_AND_activeSource_1_1_1_1_453_4_ETC___d2456 = + state_1_1_1 && activeSource_1_1_1_1 && + ifcs_1_1_routeBack$EMPTY_N && + ((!ifcs_1_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_1_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_1_1_routeBack$D_OUT[0]) ; + assign state_1_1_1_323_AND_activeSource_1_1_2_489_490_ETC___d2492 = + state_1_1_1 && activeSource_1_1_2 && + ifcs_2_1_routeBack$EMPTY_N && + ((!ifcs_2_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_2_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_2_1_routeBack$D_OUT[0]) ; + assign state_1_680_AND_activeSource_1_0_768_769_AND_i_ETC___d1771 = + state_1 && activeSource_1_0 && ifcs_0_routeBack$EMPTY_N && + ((!ifcs_0_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_0_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_0_routeBack$D_OUT[0]) ; + assign state_1_680_AND_activeSource_1_1_801_802_AND_i_ETC___d1804 = + state_1 && activeSource_1_1 && ifcs_1_routeBack$EMPTY_N && + ((!ifcs_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_1_routeBack$D_OUT[0]) ; + assign state_1_680_AND_activeSource_1_2_835_836_AND_i_ETC___d1838 = + state_1 && activeSource_1_2 && ifcs_2_routeBack$EMPTY_N && + ((!ifcs_2_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_2_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_2_routeBack$D_OUT[0]) ; + assign state_490_AND_activeSource_0_563_564_AND_ifcs__ETC___d1566 = + state && activeSource_0 && ifcs_0_innerRoute$EMPTY_N && + ((!ifcs_0_innerRoute$D_OUT[0] || + !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1435) ? + IF_NOT_ifcs_0_innerRoute_first__443_BIT_1_452__ETC___d1465 : + ifcs_0_innerRoute$D_OUT[0]) ; + assign state_490_AND_activeSource_1_607_608_AND_ifcs__ETC___d1610 = + state && activeSource_1 && ifcs_1_innerRoute$EMPTY_N && + ((!ifcs_1_innerRoute$D_OUT[0] || + !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1435) ? + IF_NOT_ifcs_1_innerRoute_first__472_BIT_1_476__ETC___d1481 : + ifcs_1_innerRoute$D_OUT[0]) ; + assign tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4 = + tagController_tmp_shimMaster_arff_rv$port1__read[98:0] ; + assign tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2 = + tagController_tmp_shimMaster_awff_rv$port1__read[98:0] ; + assign tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3 = + tagController_tmp_shimMaster_wff_rv$port1__read[72:0] ; + assign tmp__h10583 = { 24'd0, x__h10832 } ; + assign tmp__h8358 = + tagController_tmp_awreqff$D_OUT[92:29] + + tagController_tmp_addrOffset ; + assign uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1 = + uncached_mem_shim_wff$D_OUT[73:1] ; + assign v_araddr__h15549 = + (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? + araddr__h15532 : + 64'hAAAAAAAAAAAAAAAA ; + assign v_arid__h15548 = + (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? + tagController_tmp_tagCon$memory_request_get[100:95] : + 6'd0 ; + assign v_arlen__h15550 = + (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? + arlen__h15533 : + 8'd0 ; + assign v_arsize_val__h15595 = + (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? + tagController_tmp_tagCon$memory_request_get[2:0] : + 3'b0 ; + assign x__h10832 = + { tagController_tmp_tagCon$memory_request_get[140:104], 3'd0 } ; + assign x__h10875 = + tagController_tmp_tagCon$memory_request_get[81] ? + 4'd0 : + (tagController_tmp_tagCon$memory_request_get[82] ? + 4'd1 : + (tagController_tmp_tagCon$memory_request_get[83] ? + 4'd2 : + (tagController_tmp_tagCon$memory_request_get[84] ? + 4'd3 : + (tagController_tmp_tagCon$memory_request_get[85] ? + 4'd4 : + (tagController_tmp_tagCon$memory_request_get[86] ? + 4'd5 : + (tagController_tmp_tagCon$memory_request_get[87] ? + 4'd6 : + (tagController_tmp_tagCon$memory_request_get[88] ? + 4'd7 : + 4'd8))))))) ; + assign x__h12609 = x__h12621 + y__h12622 ; + assign x__h12621 = x__h12633 + y__h12634 ; + assign x__h12633 = x__h12645 + y__h12646 ; + assign x__h12645 = x__h12657 + y__h12658 ; + assign x__h12657 = x__h12669 + y__h12670 ; + assign x__h12669 = x__h12681 + y__h12682 ; + assign x__h12681 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[88] } ; + assign x__h14205 = + tagController_tmp_tagCon$memory_request_get[90] ? 4'd0 : 4'd15 ; + assign x__h15613 = + (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? + arcache__h15537 : + 4'd0 ; + assign x__h37445 = + proc$master1_awaddr - + soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h37480 = proc$master1_awaddr - soc_map$m_plic_addr_range[127:64] ; + assign x__h40257 = + debug_module$master_awaddr - + soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h40282 = + debug_module$master_awaddr - soc_map$m_plic_addr_range[127:64] ; + assign x__h48635 = + SEXT_arbiter_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; + assign x__h48738 = + SEXT_arbiter_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; + assign x__h49103 = + SEXT_SEXT_arbiter_firstHot_497_498_BIT_0_499_A_ETC__q7[0] & + arbiter_firstHot ; + assign x__h49162 = + !SEXT_arbiter_firstHot_497_498_BIT_0_499_AND_re_ETC___d1505 && + SEXT_arbiter_lastSelect_493_494_BIT_0_495_AND__ETC___d1501 ; + assign x__h49244 = SEXT_x9162__q8[0] & arbiter_firstHot ; + assign x__h62827 = x__h62829 | y__h62830 ; + assign x__h62829 = + SEXT_arbiter_1_lastSelect__q10[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h62978 = x__h62980 | y__h62981 ; + assign x__h62980 = + SEXT_arbiter_1_lastSelect_1__q11[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h63114 = x__h63116 | y__h63117 ; + assign x__h63116 = + SEXT_arbiter_1_firstHot__q9[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h63586 = x__h63588 | y__h63589 ; + assign x__h63588 = + SEXT_SEXT_arbiter_1_firstHot_692_693_BIT_0_694_ETC__q12[0] & + arbiter_1_firstHot ; + assign x__h63648 = + !SEXT_arbiter_1_firstHot_692_693_BIT_0_694_AND__ETC___d1708 && + SEXT_arbiter_1_lastSelect_1_687_688_BIT_0_689__ETC___d1702 ; + assign x__h63682 = + !SEXT_arbiter_1_lastSelect_1_687_688_BIT_0_689__ETC___d1702 && + !SEXT_arbiter_1_firstHot_692_693_BIT_0_694_AND__ETC___d1708 && + SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_AN_ETC___d1696 ; + assign x__h63774 = x__h63776 | y__h63777 ; + assign x__h63776 = SEXT_x3648__q13[0] & arbiter_1_firstHot ; + assign x__h63955 = x__h63957 | y__h63958 ; + assign x__h63957 = SEXT_x3682__q14[0] & arbiter_1_firstHot ; + assign x__h71927 = + proc$master1_araddr - + soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h71952 = proc$master1_araddr - soc_map$m_plic_addr_range[127:64] ; + assign x__h74407 = + debug_module$master_araddr - + soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h74432 = + debug_module$master_araddr - soc_map$m_plic_addr_range[127:64] ; + assign x__h8199 = + tagController_tmp_addrOffset + + (64'd1 << tagController_tmp_awreqff$D_OUT[20:18]) ; + assign x__h82584 = + SEXT_arbiter_1_lastSelect_2__q16[0] & + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; + assign x__h82687 = + SEXT_arbiter_1_firstHot_1__q15[0] & + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; + assign x__h83052 = + SEXT_SEXT_arbiter_1_firstHot_1_150_151_BIT_0_1_ETC__q17[0] & + arbiter_1_firstHot_1 ; + assign x__h83111 = + !SEXT_arbiter_1_firstHot_1_150_151_BIT_0_152_AN_ETC___d2158 && + SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_148__ETC___d2154 ; + assign x__h83193 = SEXT_x3111__q18[0] & arbiter_1_firstHot_1 ; + assign x__h94235 = x__h94237 | y__h94238 ; + assign x__h94237 = + SEXT_arbiter_1_1_lastSelect__q20[0] & + (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; + assign x__h94386 = x__h94388 | y__h94389 ; + assign x__h94388 = + SEXT_arbiter_1_1_lastSelect_1__q21[0] & + (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; + assign x__h94522 = x__h94524 | y__h94525 ; + assign x__h94524 = + SEXT_arbiter_1_1_firstHot__q19[0] & + (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; + assign x__h94994 = x__h94996 | y__h94997 ; + assign x__h94996 = + SEXT_SEXT_arbiter_1_1_firstHot_335_336_BIT_0_3_ETC__q22[0] & + arbiter_1_1_firstHot ; + assign x__h95056 = + !SEXT_arbiter_1_1_firstHot_335_336_BIT_0_337_AN_ETC___d2351 && + SEXT_arbiter_1_1_lastSelect_1_330_331_BIT_0_33_ETC___d2345 ; + assign x__h95090 = + !SEXT_arbiter_1_1_lastSelect_1_330_331_BIT_0_33_ETC___d2345 && + !SEXT_arbiter_1_1_firstHot_335_336_BIT_0_337_AN_ETC___d2351 && + SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_328__ETC___d2339 ; + assign x__h95182 = x__h95184 | y__h95185 ; + assign x__h95184 = SEXT_x5056__q23[0] & arbiter_1_1_firstHot ; + assign x__h95363 = x__h95365 | y__h95366 ; + assign x__h95365 = SEXT_x5090__q24[0] & arbiter_1_1_firstHot ; + assign x_port1__read__h73054 = + CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? + ifcs_0_1_noRoute_flitCount$port0__write_1 : + ifcs_0_1_noRoute_flitCount ; + assign x_port1__read__h75518 = + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? + ifcs_1_1_noRoute_flitCount$port0__write_1 : + ifcs_1_1_noRoute_flitCount ; + assign x_rdata__h25037 = + msNoSynth_0_r_buffer_ff$EMPTY_N ? + msNoSynth_0_r_buffer_ff$D_OUT[67:4] : + msNoSynth_0_r_buffer_enqw$wget[67:4] ; + assign x_rid__h25036 = + msNoSynth_0_r_buffer_ff$EMPTY_N ? + msNoSynth_0_r_buffer_ff$D_OUT[71:68] : + msNoSynth_0_r_buffer_enqw$wget[71:68] ; + assign y__h12610 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[81] } ; + assign y__h12622 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[82] } ; + assign y__h12634 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[83] } ; + assign y__h12646 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[84] } ; + assign y__h12658 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[85] } ; + assign y__h12670 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[86] } ; + assign y__h12682 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[87] } ; + assign y__h48636 = + SEXT_arbiter_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; + assign y__h48739 = + SEXT_arbiter_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; + assign y__h49104 = SEXT_x9162__q8[0] & arbiter_lastSelect ; + assign y__h49245 = + SEXT_SEXT_arbiter_firstHot_497_498_BIT_0_499_A_ETC__q7[0] & + arbiter_lastSelect ; + assign y__h62828 = + SEXT_arbiter_1_firstHot__q9[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h62830 = + SEXT_arbiter_1_lastSelect_1__q11[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h62979 = + SEXT_arbiter_1_lastSelect__q10[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h62981 = + SEXT_arbiter_1_firstHot__q9[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h63115 = + SEXT_arbiter_1_lastSelect_1__q11[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h63117 = + SEXT_arbiter_1_lastSelect__q10[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h63587 = SEXT_x3682__q14[0] & arbiter_1_lastSelect ; + assign y__h63589 = SEXT_x3648__q13[0] & arbiter_1_lastSelect_1 ; + assign y__h63775 = + SEXT_SEXT_arbiter_1_firstHot_692_693_BIT_0_694_ETC__q12[0] & + arbiter_1_lastSelect ; + assign y__h63777 = SEXT_x3682__q14[0] & arbiter_1_lastSelect_1 ; + assign y__h63956 = SEXT_x3648__q13[0] & arbiter_1_lastSelect ; + assign y__h63958 = + SEXT_SEXT_arbiter_1_firstHot_692_693_BIT_0_694_ETC__q12[0] & + arbiter_1_lastSelect_1 ; + assign y__h82585 = + SEXT_arbiter_1_firstHot_1__q15[0] & + (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; + assign y__h82688 = + SEXT_arbiter_1_lastSelect_2__q16[0] & + (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; + assign y__h83053 = SEXT_x3111__q18[0] & arbiter_1_lastSelect_2 ; + assign y__h83194 = + SEXT_SEXT_arbiter_1_firstHot_1_150_151_BIT_0_1_ETC__q17[0] & + arbiter_1_lastSelect_2 ; + assign y__h94236 = + SEXT_arbiter_1_1_firstHot__q19[0] & + (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; + assign y__h94238 = + SEXT_arbiter_1_1_lastSelect_1__q21[0] & + (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; + assign y__h94387 = + SEXT_arbiter_1_1_lastSelect__q20[0] & + (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; + assign y__h94389 = + SEXT_arbiter_1_1_firstHot__q19[0] & + (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; + assign y__h94523 = + SEXT_arbiter_1_1_lastSelect_1__q21[0] & + (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; + assign y__h94525 = + SEXT_arbiter_1_1_lastSelect__q20[0] & + (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; + assign y__h94995 = SEXT_x5090__q24[0] & arbiter_1_1_lastSelect ; + assign y__h94997 = SEXT_x5056__q23[0] & arbiter_1_1_lastSelect_1 ; + assign y__h95183 = + SEXT_SEXT_arbiter_1_1_firstHot_335_336_BIT_0_3_ETC__q22[0] & + arbiter_1_1_lastSelect ; + assign y__h95185 = SEXT_x5090__q24[0] & arbiter_1_1_lastSelect_1 ; + assign y__h95364 = SEXT_x5056__q23[0] & arbiter_1_1_lastSelect ; + assign y__h95366 = + SEXT_SEXT_arbiter_1_1_firstHot_335_336_BIT_0_3_ETC__q22[0] & + arbiter_1_1_lastSelect_1 ; // handling of inlined registers @@ -3160,26 +9341,243 @@ module mkCoreW(CLK, begin if (RST_N == `BSV_RESET_VALUE) begin - hart0_halt <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_1_firstHot <= `BSV_ASSIGNMENT_DELAY 1'd1; + arbiter_1_1_lastSelect <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_firstHot <= `BSV_ASSIGNMENT_DELAY 1'd1; + arbiter_1_firstHot_1 <= `BSV_ASSIGNMENT_DELAY 1'd1; + arbiter_1_lastSelect <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_lastSelect_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_firstHot <= `BSV_ASSIGNMENT_DELAY 1'd1; + arbiter_lastSelect <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_0_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_0_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY 9'd0; + ifcs_0_1_state <= `BSV_ASSIGNMENT_DELAY 2'd0; + ifcs_0_1_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_0_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_0_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_0_state <= `BSV_ASSIGNMENT_DELAY 2'd0; + ifcs_0_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_1_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_1_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY 9'd0; + ifcs_1_1_state <= `BSV_ASSIGNMENT_DELAY 2'd0; + ifcs_1_1_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_1_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_1_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_1_state <= `BSV_ASSIGNMENT_DELAY 2'd0; + ifcs_1_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_2_1_state <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_2_state <= `BSV_ASSIGNMENT_DELAY 1'd0; + merged_0_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + merged_1_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; + rg_hart0_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; + split_0_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + split_1_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + split_2_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + state <= `BSV_ASSIGNMENT_DELAY 1'd0; + state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + state_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + state_1_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin - if (hart0_halt$EN) - hart0_halt <= `BSV_ASSIGNMENT_DELAY hart0_halt$D_IN; + if (activeSource_0$EN) + activeSource_0 <= `BSV_ASSIGNMENT_DELAY activeSource_0$D_IN; + if (activeSource_1$EN) + activeSource_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1$D_IN; + if (activeSource_1_0$EN) + activeSource_1_0 <= `BSV_ASSIGNMENT_DELAY activeSource_1_0$D_IN; + if (activeSource_1_0_1$EN) + activeSource_1_0_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1_0_1$D_IN; + if (activeSource_1_1$EN) + activeSource_1_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1$D_IN; + if (activeSource_1_1_0$EN) + activeSource_1_1_0 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1_0$D_IN; + if (activeSource_1_1_1$EN) + activeSource_1_1_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1_1$D_IN; + if (activeSource_1_1_1_1$EN) + activeSource_1_1_1_1 <= `BSV_ASSIGNMENT_DELAY + activeSource_1_1_1_1$D_IN; + if (activeSource_1_1_2$EN) + activeSource_1_1_2 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1_2$D_IN; + if (activeSource_1_2$EN) + activeSource_1_2 <= `BSV_ASSIGNMENT_DELAY activeSource_1_2$D_IN; + if (arbiter_1_1_firstHot$EN) + arbiter_1_1_firstHot <= `BSV_ASSIGNMENT_DELAY + arbiter_1_1_firstHot$D_IN; + if (arbiter_1_1_lastSelect$EN) + arbiter_1_1_lastSelect <= `BSV_ASSIGNMENT_DELAY + arbiter_1_1_lastSelect$D_IN; + if (arbiter_1_1_lastSelect_1$EN) + arbiter_1_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY + arbiter_1_1_lastSelect_1$D_IN; + if (arbiter_1_firstHot$EN) + arbiter_1_firstHot <= `BSV_ASSIGNMENT_DELAY arbiter_1_firstHot$D_IN; + if (arbiter_1_firstHot_1$EN) + arbiter_1_firstHot_1 <= `BSV_ASSIGNMENT_DELAY + arbiter_1_firstHot_1$D_IN; + if (arbiter_1_lastSelect$EN) + arbiter_1_lastSelect <= `BSV_ASSIGNMENT_DELAY + arbiter_1_lastSelect$D_IN; + if (arbiter_1_lastSelect_1$EN) + arbiter_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY + arbiter_1_lastSelect_1$D_IN; + if (arbiter_1_lastSelect_2$EN) + arbiter_1_lastSelect_2 <= `BSV_ASSIGNMENT_DELAY + arbiter_1_lastSelect_2$D_IN; + if (arbiter_firstHot$EN) + arbiter_firstHot <= `BSV_ASSIGNMENT_DELAY arbiter_firstHot$D_IN; + if (arbiter_lastSelect$EN) + arbiter_lastSelect <= `BSV_ASSIGNMENT_DELAY arbiter_lastSelect$D_IN; + if (ifcs_0_1_noRoute_currentReq$EN) + ifcs_0_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY + ifcs_0_1_noRoute_currentReq$D_IN; + if (ifcs_0_1_noRoute_flitCount$EN) + ifcs_0_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY + ifcs_0_1_noRoute_flitCount$D_IN; + if (ifcs_0_1_state$EN) + ifcs_0_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_0_1_state$D_IN; + if (ifcs_0_1_state_1$EN) + ifcs_0_1_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_0_1_state_1$D_IN; + if (ifcs_0_noRoute_inner_currentReq$EN) + ifcs_0_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY + ifcs_0_noRoute_inner_currentReq$D_IN; + if (ifcs_0_noRoute_inner_pendingReq$EN) + ifcs_0_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY + ifcs_0_noRoute_inner_pendingReq$D_IN; + if (ifcs_0_state$EN) + ifcs_0_state <= `BSV_ASSIGNMENT_DELAY ifcs_0_state$D_IN; + if (ifcs_0_state_1$EN) + ifcs_0_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_0_state_1$D_IN; + if (ifcs_1_1_noRoute_currentReq$EN) + ifcs_1_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY + ifcs_1_1_noRoute_currentReq$D_IN; + if (ifcs_1_1_noRoute_flitCount$EN) + ifcs_1_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY + ifcs_1_1_noRoute_flitCount$D_IN; + if (ifcs_1_1_state$EN) + ifcs_1_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_1_1_state$D_IN; + if (ifcs_1_1_state_1$EN) + ifcs_1_1_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_1_1_state_1$D_IN; + if (ifcs_1_noRoute_inner_currentReq$EN) + ifcs_1_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY + ifcs_1_noRoute_inner_currentReq$D_IN; + if (ifcs_1_noRoute_inner_pendingReq$EN) + ifcs_1_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY + ifcs_1_noRoute_inner_pendingReq$D_IN; + if (ifcs_1_state$EN) + ifcs_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_1_state$D_IN; + if (ifcs_1_state_1$EN) + ifcs_1_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_1_state_1$D_IN; + if (ifcs_2_1_state$EN) + ifcs_2_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_2_1_state$D_IN; + if (ifcs_2_state$EN) + ifcs_2_state <= `BSV_ASSIGNMENT_DELAY ifcs_2_state$D_IN; + if (merged_0_flitLeft$EN) + merged_0_flitLeft <= `BSV_ASSIGNMENT_DELAY merged_0_flitLeft$D_IN; + if (merged_1_flitLeft$EN) + merged_1_flitLeft <= `BSV_ASSIGNMENT_DELAY merged_1_flitLeft$D_IN; if (rg_fromhost_addr$EN) rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY rg_fromhost_addr$D_IN; + if (rg_hart0_reset_delay$EN) + rg_hart0_reset_delay <= `BSV_ASSIGNMENT_DELAY + rg_hart0_reset_delay$D_IN; if (rg_tohost_addr$EN) rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; + if (split_0_flitLeft$EN) + split_0_flitLeft <= `BSV_ASSIGNMENT_DELAY split_0_flitLeft$D_IN; + if (split_1_flitLeft$EN) + split_1_flitLeft <= `BSV_ASSIGNMENT_DELAY split_1_flitLeft$D_IN; + if (split_2_flitLeft$EN) + split_2_flitLeft <= `BSV_ASSIGNMENT_DELAY split_2_flitLeft$D_IN; + if (state$EN) state <= `BSV_ASSIGNMENT_DELAY state$D_IN; + if (state_1$EN) state_1 <= `BSV_ASSIGNMENT_DELAY state_1$D_IN; + if (state_1_1$EN) state_1_1 <= `BSV_ASSIGNMENT_DELAY state_1_1$D_IN; + if (state_1_1_1$EN) + state_1_1_1 <= `BSV_ASSIGNMENT_DELAY state_1_1_1$D_IN; end - if (cpu_reset_either$RST_OUT == `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT == `BSV_RESET_VALUE) begin - once <= `BSV_ASSIGNMENT_DELAY 1'd0; + tagController_tmp_addrOffset <= `BSV_ASSIGNMENT_DELAY 64'd0; + tagController_tmp_doneSendingAW <= `BSV_ASSIGNMENT_DELAY 1'd0; + tagController_tmp_reset_done <= `BSV_ASSIGNMENT_DELAY 1'd0; + tagController_tmp_shimMaster_arff_rv <= `BSV_ASSIGNMENT_DELAY + 100'h2AAAAAAAAAAAAAAAAAAAAAAAA; + tagController_tmp_shimMaster_awff_rv <= `BSV_ASSIGNMENT_DELAY + 100'h2AAAAAAAAAAAAAAAAAAAAAAAA; + tagController_tmp_shimMaster_bff_rv <= `BSV_ASSIGNMENT_DELAY 9'd170; + tagController_tmp_shimMaster_rff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; + tagController_tmp_shimMaster_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; + tagController_tmp_shimSlave_arff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + tagController_tmp_shimSlave_awff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + tagController_tmp_shimSlave_bff_rv <= `BSV_ASSIGNMENT_DELAY 8'd42; + tagController_tmp_shimSlave_rff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; + tagController_tmp_shimSlave_wff_rv <= `BSV_ASSIGNMENT_DELAY + 75'h2AAAAAAAAAAAAAAAAAA; end else begin - if (once$EN) once <= `BSV_ASSIGNMENT_DELAY once$D_IN; + if (tagController_tmp_addrOffset$EN) + tagController_tmp_addrOffset <= `BSV_ASSIGNMENT_DELAY + tagController_tmp_addrOffset$D_IN; + if (tagController_tmp_doneSendingAW$EN) + tagController_tmp_doneSendingAW <= `BSV_ASSIGNMENT_DELAY + tagController_tmp_doneSendingAW$D_IN; + if (tagController_tmp_reset_done$EN) + tagController_tmp_reset_done <= `BSV_ASSIGNMENT_DELAY + tagController_tmp_reset_done$D_IN; + if (tagController_tmp_shimMaster_arff_rv$EN) + tagController_tmp_shimMaster_arff_rv <= `BSV_ASSIGNMENT_DELAY + tagController_tmp_shimMaster_arff_rv$D_IN; + if (tagController_tmp_shimMaster_awff_rv$EN) + tagController_tmp_shimMaster_awff_rv <= `BSV_ASSIGNMENT_DELAY + tagController_tmp_shimMaster_awff_rv$D_IN; + if (tagController_tmp_shimMaster_bff_rv$EN) + tagController_tmp_shimMaster_bff_rv <= `BSV_ASSIGNMENT_DELAY + tagController_tmp_shimMaster_bff_rv$D_IN; + if (tagController_tmp_shimMaster_rff_rv$EN) + tagController_tmp_shimMaster_rff_rv <= `BSV_ASSIGNMENT_DELAY + tagController_tmp_shimMaster_rff_rv$D_IN; + if (tagController_tmp_shimMaster_wff_rv$EN) + tagController_tmp_shimMaster_wff_rv <= `BSV_ASSIGNMENT_DELAY + tagController_tmp_shimMaster_wff_rv$D_IN; + if (tagController_tmp_shimSlave_arff_rv$EN) + tagController_tmp_shimSlave_arff_rv <= `BSV_ASSIGNMENT_DELAY + tagController_tmp_shimSlave_arff_rv$D_IN; + if (tagController_tmp_shimSlave_awff_rv$EN) + tagController_tmp_shimSlave_awff_rv <= `BSV_ASSIGNMENT_DELAY + tagController_tmp_shimSlave_awff_rv$D_IN; + if (tagController_tmp_shimSlave_bff_rv$EN) + tagController_tmp_shimSlave_bff_rv <= `BSV_ASSIGNMENT_DELAY + tagController_tmp_shimSlave_bff_rv$D_IN; + if (tagController_tmp_shimSlave_rff_rv$EN) + tagController_tmp_shimSlave_rff_rv <= `BSV_ASSIGNMENT_DELAY + tagController_tmp_shimSlave_rff_rv$D_IN; + if (tagController_tmp_shimSlave_wff_rv$EN) + tagController_tmp_shimSlave_wff_rv <= `BSV_ASSIGNMENT_DELAY + tagController_tmp_shimSlave_wff_rv$D_IN; end end @@ -3188,10 +9586,69 @@ module mkCoreW(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - hart0_halt = 1'h0; - once = 1'h0; + activeSource_0 = 1'h0; + activeSource_1 = 1'h0; + activeSource_1_0 = 1'h0; + activeSource_1_0_1 = 1'h0; + activeSource_1_1 = 1'h0; + activeSource_1_1_0 = 1'h0; + activeSource_1_1_1 = 1'h0; + activeSource_1_1_1_1 = 1'h0; + activeSource_1_1_2 = 1'h0; + activeSource_1_2 = 1'h0; + arbiter_1_1_firstHot = 1'h0; + arbiter_1_1_lastSelect = 1'h0; + arbiter_1_1_lastSelect_1 = 1'h0; + arbiter_1_firstHot = 1'h0; + arbiter_1_firstHot_1 = 1'h0; + arbiter_1_lastSelect = 1'h0; + arbiter_1_lastSelect_1 = 1'h0; + arbiter_1_lastSelect_2 = 1'h0; + arbiter_firstHot = 1'h0; + arbiter_lastSelect = 1'h0; + ifcs_0_1_noRoute_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_0_1_noRoute_flitCount = 9'h0AA; + ifcs_0_1_state = 2'h2; + ifcs_0_1_state_1 = 1'h0; + ifcs_0_noRoute_inner_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_0_noRoute_inner_pendingReq = 1'h0; + ifcs_0_state = 2'h2; + ifcs_0_state_1 = 1'h0; + ifcs_1_1_noRoute_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_1_1_noRoute_flitCount = 9'h0AA; + ifcs_1_1_state = 2'h2; + ifcs_1_1_state_1 = 1'h0; + ifcs_1_noRoute_inner_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_1_noRoute_inner_pendingReq = 1'h0; + ifcs_1_state = 2'h2; + ifcs_1_state_1 = 1'h0; + ifcs_2_1_state = 1'h0; + ifcs_2_state = 1'h0; + merged_0_flitLeft = 8'hAA; + merged_1_flitLeft = 8'hAA; rg_fromhost_addr = 64'hAAAAAAAAAAAAAAAA; + rg_hart0_reset_delay = 8'hAA; rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; + split_0_flitLeft = 8'hAA; + split_1_flitLeft = 8'hAA; + split_2_flitLeft = 8'hAA; + state = 1'h0; + state_1 = 1'h0; + state_1_1 = 1'h0; + state_1_1_1 = 1'h0; + tagController_tmp_addrOffset = 64'hAAAAAAAAAAAAAAAA; + tagController_tmp_doneSendingAW = 1'h0; + tagController_tmp_reset_done = 1'h0; + tagController_tmp_shimMaster_arff_rv = 100'hAAAAAAAAAAAAAAAAAAAAAAAAA; + tagController_tmp_shimMaster_awff_rv = 100'hAAAAAAAAAAAAAAAAAAAAAAAAA; + tagController_tmp_shimMaster_bff_rv = 9'h0AA; + tagController_tmp_shimMaster_rff_rv = 74'h2AAAAAAAAAAAAAAAAAA; + tagController_tmp_shimMaster_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; + tagController_tmp_shimSlave_arff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + tagController_tmp_shimSlave_awff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + tagController_tmp_shimSlave_bff_rv = 8'hAA; + tagController_tmp_shimSlave_rff_rv = 74'h2AAAAAAAAAAAAAAAAAA; + tagController_tmp_shimSlave_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -3203,26 +9660,1713 @@ module mkCoreW(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset) + begin + v__h22817 = $stime; + #0; + end + v__h22811 = v__h22817 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset) + $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", + v__h22811, + $signed(32'd10)); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1) + begin + v__h22960 = $stime; + #0; + end + v__h22954 = v__h22960 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1) + $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", + v__h22954, + 64'h0000000070000000, + rg_tohost_addr, + rg_fromhost_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate && + !SEXT_arbiter_lastSelect_493_494_BIT_0_495_AND__ETC___d1501 && + !SEXT_arbiter_firstHot_497_498_BIT_0_499_AND_re_ETC___d1505) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate && + !SEXT_arbiter_lastSelect_493_494_BIT_0_495_AND__ETC___d1501 && + !SEXT_arbiter_firstHot_497_498_BIT_0_499_AND_re_ETC___d1505) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) begin - v__h5014 = $stime; + v__h50643 = $time; #0; end - v__h5008 = v__h5014 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete; started running proc", - v__h5008); + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h50643, + $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) begin - v__h4855 = $stime; + v__h50032 = $time; #0; end - v__h4849 = v__h4855 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4849); + if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h50032, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h54652 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h54652, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) + begin + v__h54041 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h54041, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && WILL_FIRE_RL_burst) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 113, column 32: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected] and\n [RL_burst] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected || WILL_FIRE_RL_burst) && + (WILL_FIRE_RL_source_selected_1 || WILL_FIRE_RL_burst_1)) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected, RL_burst]\n and [RL_source_selected_1, RL_burst_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && WILL_FIRE_RL_burst_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_1] and\n [RL_burst_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected && WILL_FIRE_RL_sink_selected_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected] and\n [RL_sink_selected_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_sink_selected || WILL_FIRE_RL_sink_selected_1) && + WILL_FIRE_RL_sink_selected_2) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected,\n RL_sink_selected_1] and [RL_sink_selected_2] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_2 && + !SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_148__ETC___d2154 && + !SEXT_arbiter_1_firstHot_1_150_151_BIT_0_152_AN_ETC___d2158) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_2 && + !SEXT_arbiter_1_lastSelect_2_146_147_BIT_0_148__ETC___d2154 && + !SEXT_arbiter_1_firstHot_1_150_151_BIT_0_152_AN_ETC___d2158) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h84586 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h84586, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) + begin + v__h83975 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h83975, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h87479 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h87479, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) + begin + v__h86868 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h86868, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && WILL_FIRE_RL_burst_5) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_5] and\n [RL_burst_5] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_5 || WILL_FIRE_RL_burst_5) && + (WILL_FIRE_RL_source_selected_6 || WILL_FIRE_RL_burst_6)) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_5,\n RL_burst_5] and [RL_source_selected_6, RL_burst_6] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && WILL_FIRE_RL_burst_6) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_6] and\n [RL_burst_6] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected_5 && WILL_FIRE_RL_sink_selected_6) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_5] and\n [RL_sink_selected_6] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_sink_selected_5 || WILL_FIRE_RL_sink_selected_6) && + WILL_FIRE_RL_sink_selected_7) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_5,\n RL_sink_selected_6] and [RL_sink_selected_7] ) fired in the same clock\n cycle.\n"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) + $display("Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + split_0_doPut$wget[1] && + split_0_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + split_0_doPut$wget[1] && + split_0_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + !split_0_doPut$wget[1] && + split_0_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + !split_0_doPut$wget[1] && + split_0_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) + $display("Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) + $display("Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + split_1_doPut$wget[1] && + split_1_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + split_1_doPut$wget[1] && + split_1_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + !split_1_doPut$wget[1] && + split_1_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + !split_1_doPut$wget[1] && + split_1_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) + $display("Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) + $display("Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + split_2_doPut$wget[1] && + split_2_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + split_2_doPut$wget[1] && + split_2_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + !split_2_doPut$wget[1] && + split_2_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + !split_2_doPut$wget[1] && + split_2_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) + $display("Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_nonRoutableFlit && + WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_nonRoutableFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_1 && + !SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_AN_ETC___d1696 && + !SEXT_arbiter_1_lastSelect_1_687_688_BIT_0_689__ETC___d1702 && + !SEXT_arbiter_1_firstHot_692_693_BIT_0_694_AND__ETC___d1708) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_1 && + !SEXT_arbiter_1_lastSelect_683_684_BIT_0_685_AN_ETC___d1696 && + !SEXT_arbiter_1_lastSelect_1_687_688_BIT_0_689__ETC___d1702 && + !SEXT_arbiter_1_firstHot_692_693_BIT_0_694_AND__ETC___d1708) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h65347 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h65347, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + begin + v__h64966 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h64966, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h67417 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h67417, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + begin + v__h67036 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h67036, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && WILL_FIRE_RL_burst_3) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_3] and\n [RL_burst_3] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h69316 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h69316, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + begin + v__h68935 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h68935, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && WILL_FIRE_RL_burst_2) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2] and\n [RL_burst_2] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2) && + (WILL_FIRE_RL_source_selected_3 || WILL_FIRE_RL_burst_3)) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2] and [RL_source_selected_3, RL_burst_3] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2 || + WILL_FIRE_RL_source_selected_3 || + WILL_FIRE_RL_burst_3) && + (WILL_FIRE_RL_source_selected_4 || WILL_FIRE_RL_burst_4)) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2, RL_source_selected_3, RL_burst_3] and [RL_source_selected_4,\n RL_burst_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && WILL_FIRE_RL_burst_4) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_4] and\n [RL_burst_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected_3 && WILL_FIRE_RL_sink_selected_4) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_3] and\n [RL_sink_selected_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && + WILL_FIRE_RL_ifcs_0_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_drainFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_drainFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && proc$master1_wlast && + merged_0_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && proc$master1_wlast && + merged_0_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && !proc$master1_wlast && + merged_0_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && !proc$master1_wlast && + merged_0_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit_1 && + WILL_FIRE_RL_ifcs_0_followFlits_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit_1] and\n [RL_ifcs_0_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_1_followFlits_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit_1] and\n [RL_ifcs_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_2_firstFlit && WILL_FIRE_RL_ifcs_2_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_firstFlit] and\n [RL_ifcs_2_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_nonRoutableFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_3 && + !SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_328__ETC___d2339 && + !SEXT_arbiter_1_1_lastSelect_1_330_331_BIT_0_33_ETC___d2345 && + !SEXT_arbiter_1_1_firstHot_335_336_BIT_0_337_AN_ETC___d2351) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_3 && + !SEXT_arbiter_1_1_lastSelect_326_327_BIT_0_328__ETC___d2339 && + !SEXT_arbiter_1_1_lastSelect_1_330_331_BIT_0_33_ETC___d2345 && + !SEXT_arbiter_1_1_firstHot_335_336_BIT_0_337_AN_ETC___d2351) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h96759 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h96759, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) + begin + v__h96378 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h96378, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h99250 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h99250, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) + begin + v__h98869 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h98869, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && WILL_FIRE_RL_burst_8) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_8] and\n [RL_burst_8] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h101560 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h101560, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) + begin + v__h101179 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h101179, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && WILL_FIRE_RL_burst_7) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_7] and\n [RL_burst_7] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_7 || WILL_FIRE_RL_burst_7) && + (WILL_FIRE_RL_source_selected_8 || WILL_FIRE_RL_burst_8)) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_7,\n RL_burst_7] and [RL_source_selected_8, RL_burst_8] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_7 || WILL_FIRE_RL_burst_7 || + WILL_FIRE_RL_source_selected_8 || + WILL_FIRE_RL_burst_8) && + (WILL_FIRE_RL_source_selected_9 || WILL_FIRE_RL_burst_9)) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_7,\n RL_burst_7, RL_source_selected_8, RL_burst_8] and [RL_source_selected_9,\n RL_burst_9] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && WILL_FIRE_RL_burst_9) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_9] and\n [RL_burst_9] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected_8 && WILL_FIRE_RL_sink_selected_9) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_8] and\n [RL_sink_selected_9] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_drainFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_drainFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit && + WILL_FIRE_RL_ifcs_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_followFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_followFlits && WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_followFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_nonRoutableFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_drainFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_drainFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_1_genOther && debug_module$master_wlast && + merged_1_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_1_genOther && debug_module$master_wlast && + merged_1_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_1_genOther && !debug_module$master_wlast && + merged_1_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_1_genOther && !debug_module$master_wlast && + merged_1_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_nonRoutableFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_drainFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_drainFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_0_1_followFlits_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit_1] and\n [RL_ifcs_0_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_1_1_followFlits_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit_1] and\n [RL_ifcs_1_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (EN_start) + begin + v__h104002 = $stime; + #0; + end + v__h103996 = v__h104002 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (EN_start) + $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", + v__h103996, + 64'h0000000070000000, + start_tohost_addr, + start_fromhost_addr); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_2_1_firstFlit && + WILL_FIRE_RL_ifcs_2_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_1_firstFlit] and\n [RL_ifcs_2_1_followFlits] ) fired in the same clock cycle.\n"); end // synopsys translate_on endmodule // mkCoreW diff --git a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v index d9cea29..06039c3 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v +++ b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// +// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // +// On Fri Jun 5 17:46:55 BST 2020 // // // Ports: @@ -9,12 +9,12 @@ // pipelines_0_canDeq O 1 // RDY_pipelines_0_canDeq O 1 const // RDY_pipelines_0_deq O 1 -// pipelines_0_first O 388 +// pipelines_0_first O 591 // RDY_pipelines_0_first O 1 // pipelines_1_canDeq O 1 // RDY_pipelines_1_canDeq O 1 const // RDY_pipelines_1_deq O 1 -// pipelines_1_first O 388 +// pipelines_1_first O 591 // RDY_pipelines_1_first O 1 // iTlbIfc_flush_done O 1 // RDY_iTlbIfc_flush_done O 1 const @@ -23,7 +23,7 @@ // iTlbIfc_noPendingReq O 1 // RDY_iTlbIfc_noPendingReq O 1 const // RDY_iTlbIfc_to_proc_request_put O 1 -// iTlbIfc_to_proc_response_get O 69 +// iTlbIfc_to_proc_response_get O 70 // RDY_iTlbIfc_to_proc_response_get O 1 // iTlbIfc_toParent_rqToP_notEmpty O 1 // RDY_iTlbIfc_toParent_rqToP_notEmpty O 1 const @@ -56,7 +56,7 @@ // iMemIfc_to_parent_rsToP_notEmpty O 1 // RDY_iMemIfc_to_parent_rsToP_notEmpty O 1 const // RDY_iMemIfc_to_parent_rsToP_deq O 1 -// iMemIfc_to_parent_rsToP_first O 579 +// iMemIfc_to_parent_rsToP_first O 583 // RDY_iMemIfc_to_parent_rsToP_first O 1 // iMemIfc_to_parent_rqToP_notEmpty O 1 // RDY_iMemIfc_to_parent_rqToP_notEmpty O 1 const @@ -85,6 +85,7 @@ // RDY_stop O 1 const // RDY_setWaitRedirect O 1 const // RDY_redirect O 1 const +// RDY_setWaitFlush O 1 const // RDY_done_flushing O 1 reg // RDY_train_predictors O 1 const // emptyForFlush O 1 @@ -92,7 +93,7 @@ // RDY_flush_predictors O 1 const // flush_predictors_done O 1 // RDY_flush_predictors_done O 1 const -// getFetchState O 70 +// getFetchState O 70 reg // RDY_getFetchState O 1 const // RDY_perf_setStatus O 1 const // RDY_perf_req O 1 @@ -110,18 +111,19 @@ // iMemIfc_to_proc_request_put I 64 // iMemIfc_perf_setStatus_doStats I 1 unused // iMemIfc_perf_req_r I 2 -// iMemIfc_to_parent_fromP_enq_x I 583 +// iMemIfc_to_parent_fromP_enq_x I 587 // mmioIfc_instResp_enq_x I 66 // mmioIfc_setHtifAddrs_toHost I 64 reg // mmioIfc_setHtifAddrs_fromHost I 64 reg -// start_pc I 64 -// redirect_pc I 64 -// train_predictors_pc I 64 -// train_predictors_next_pc I 64 +// start_pc I 129 +// redirect_pc I 129 +// train_predictors_pc I 129 +// train_predictors_next_pc I 129 // train_predictors_iType I 5 // train_predictors_taken I 1 // train_predictors_dpTrain I 24 // train_predictors_mispred I 1 +// train_predictors_isCompressed I 1 // perf_setStatus_doStats I 1 unused // perf_req_r I 2 // EN_pipelines_0_deq I 1 @@ -149,6 +151,7 @@ // EN_stop I 1 // EN_setWaitRedirect I 1 // EN_redirect I 1 +// EN_setWaitFlush I 1 // EN_done_flushing I 1 // EN_train_predictors I 1 // EN_flush_predictors I 1 unused @@ -358,6 +361,9 @@ module mkFetchStage(CLK, EN_redirect, RDY_redirect, + EN_setWaitFlush, + RDY_setWaitFlush, + EN_done_flushing, RDY_done_flushing, @@ -367,6 +373,7 @@ module mkFetchStage(CLK, train_predictors_taken, train_predictors_dpTrain, train_predictors_mispred, + train_predictors_isCompressed, EN_train_predictors, RDY_train_predictors, @@ -408,7 +415,7 @@ module mkFetchStage(CLK, output RDY_pipelines_0_deq; // value method pipelines_0_first - output [387 : 0] pipelines_0_first; + output [590 : 0] pipelines_0_first; output RDY_pipelines_0_first; // value method pipelines_1_canDeq @@ -420,7 +427,7 @@ module mkFetchStage(CLK, output RDY_pipelines_1_deq; // value method pipelines_1_first - output [387 : 0] pipelines_1_first; + output [590 : 0] pipelines_1_first; output RDY_pipelines_1_first; // value method iTlbIfc_flush_done @@ -447,7 +454,7 @@ module mkFetchStage(CLK, // actionvalue method iTlbIfc_to_proc_response_get input EN_iTlbIfc_to_proc_response_get; - output [68 : 0] iTlbIfc_to_proc_response_get; + output [69 : 0] iTlbIfc_to_proc_response_get; output RDY_iTlbIfc_to_proc_response_get; // value method iTlbIfc_toParent_rqToP_notEmpty @@ -544,7 +551,7 @@ module mkFetchStage(CLK, output RDY_iMemIfc_to_parent_rsToP_deq; // value method iMemIfc_to_parent_rsToP_first - output [578 : 0] iMemIfc_to_parent_rsToP_first; + output [582 : 0] iMemIfc_to_parent_rsToP_first; output RDY_iMemIfc_to_parent_rsToP_first; // value method iMemIfc_to_parent_rqToP_notEmpty @@ -564,7 +571,7 @@ module mkFetchStage(CLK, output RDY_iMemIfc_to_parent_fromP_notFull; // action method iMemIfc_to_parent_fromP_enq - input [582 : 0] iMemIfc_to_parent_fromP_enq_x; + input [586 : 0] iMemIfc_to_parent_fromP_enq_x; input EN_iMemIfc_to_parent_fromP_enq; output RDY_iMemIfc_to_parent_fromP_enq; @@ -610,7 +617,7 @@ module mkFetchStage(CLK, output RDY_mmioIfc_setHtifAddrs; // action method start - input [63 : 0] start_pc; + input [128 : 0] start_pc; input EN_start; output RDY_start; @@ -623,21 +630,26 @@ module mkFetchStage(CLK, output RDY_setWaitRedirect; // action method redirect - input [63 : 0] redirect_pc; + input [128 : 0] redirect_pc; input EN_redirect; output RDY_redirect; + // action method setWaitFlush + input EN_setWaitFlush; + output RDY_setWaitFlush; + // action method done_flushing input EN_done_flushing; output RDY_done_flushing; // action method train_predictors - input [63 : 0] train_predictors_pc; - input [63 : 0] train_predictors_next_pc; + input [128 : 0] train_predictors_pc; + input [128 : 0] train_predictors_next_pc; input [4 : 0] train_predictors_iType; input train_predictors_taken; input [23 : 0] train_predictors_dpTrain; input train_predictors_mispred; + input train_predictors_isCompressed; input EN_train_predictors; output RDY_train_predictors; @@ -678,11 +690,10 @@ module mkFetchStage(CLK, // signals for module outputs reg RDY_pipelines_0_first, RDY_pipelines_1_first; - wire [578 : 0] iMemIfc_to_parent_rsToP_first; - wire [387 : 0] pipelines_0_first, pipelines_1_first; + wire [590 : 0] pipelines_0_first, pipelines_1_first; + wire [582 : 0] iMemIfc_to_parent_rsToP_first; wire [71 : 0] iMemIfc_to_parent_rqToP_first; - wire [69 : 0] getFetchState; - wire [68 : 0] iTlbIfc_to_proc_response_get; + wire [69 : 0] getFetchState, iTlbIfc_to_proc_response_get; wire [67 : 0] iMemIfc_cRqStuck_get, iMemIfc_pRqStuck_get; wire [66 : 0] iTlbIfc_perf_resp; wire [65 : 0] iMemIfc_perf_resp, iMemIfc_to_proc_response_get, perf_resp; @@ -744,6 +755,7 @@ module mkFetchStage(CLK, RDY_pipelines_1_canDeq, RDY_pipelines_1_deq, RDY_redirect, + RDY_setWaitFlush, RDY_setWaitRedirect, RDY_start, RDY_stop, @@ -768,43 +780,50 @@ module mkFetchStage(CLK, pipelines_1_canDeq; // inlined wires - wire [388 : 0] out_fifo_enqueueElement_0_lat_0$wget, + wire [591 : 0] out_fifo_enqueueElement_0_lat_0$wget, out_fifo_enqueueElement_1_lat_0$wget; - wire [268 : 0] f22f3_enqReq_lat_0$wget, f32d_enqReq_lat_0$wget; - wire [134 : 0] f12f2_enqReq_lat_0$wget; - wire [128 : 0] nextAddrPred_updateEn$wget; - wire [127 : 0] napTrainByExe$wget; + wire [338 : 0] f22f3_enqReq_lat_0$wget; + wire [335 : 0] f32d_enqReq_lat_0$wget; + wire [267 : 0] f12f2_enqReq_lat_0$wget; + wire [258 : 0] nextAddrPred_updateEn$wget; + wire [257 : 0] napTrainByExe$wget; + wire [146 : 0] ehr_pending_straddle_lat_0$wget; wire [2 : 0] perfReqQ_enqReq_lat_0$wget; - wire f32d_enqReq_lat_0$whas, + wire decode_epoch_lat_0$wget, + decode_epoch_lat_0$whas, + f22f3_deqReq_lat_0$whas, + f32d_enqReq_lat_0$whas, instdata_empty_lat_0$whas, instdata_full_lat_1$whas, napTrainByDecQ_enqP_lat_0$whas, napTrainByExe$whas, - out_fifo_dequeueFifo_lat_0$whas, - out_fifo_dequeueFifo_lat_1$whas, out_fifo_enqueueElement_0_lat_0$whas, - out_fifo_enqueueElement_1_dummy_1_0$wget, - out_fifo_enqueueFifo_lat_0$whas, - out_fifo_enqueueFifo_lat_1$whas, - pc_reg_dummy_1_0$whas, - pc_reg_lat_0$whas; + out_fifo_enqueueElement_1_lat_0$whas, + pc_reg_lat_0$whas, + pc_reg_lat_1$whas, + pc_reg_lat_2$whas; - // register decode_epoch - reg decode_epoch; - wire decode_epoch$D_IN, decode_epoch$EN; + // register decode_epoch_rl + reg decode_epoch_rl; + wire decode_epoch_rl$D_IN, decode_epoch_rl$EN; + + // register ehr_pending_straddle_rl + reg [146 : 0] ehr_pending_straddle_rl; + wire [146 : 0] ehr_pending_straddle_rl$D_IN; + wire ehr_pending_straddle_rl$EN; // register f12f2_clearReq_rl reg f12f2_clearReq_rl; wire f12f2_clearReq_rl$D_IN, f12f2_clearReq_rl$EN; // register f12f2_data_0 - reg [133 : 0] f12f2_data_0; - wire [133 : 0] f12f2_data_0$D_IN; + reg [266 : 0] f12f2_data_0; + wire [266 : 0] f12f2_data_0$D_IN; wire f12f2_data_0$EN; // register f12f2_data_1 - reg [133 : 0] f12f2_data_1; - wire [133 : 0] f12f2_data_1$D_IN; + reg [266 : 0] f12f2_data_1; + wire [266 : 0] f12f2_data_1$D_IN; wire f12f2_data_1$EN; // register f12f2_deqP @@ -824,8 +843,8 @@ module mkFetchStage(CLK, wire f12f2_enqP$D_IN, f12f2_enqP$EN; // register f12f2_enqReq_rl - reg [134 : 0] f12f2_enqReq_rl; - wire [134 : 0] f12f2_enqReq_rl$D_IN; + reg [267 : 0] f12f2_enqReq_rl; + wire [267 : 0] f12f2_enqReq_rl$D_IN; wire f12f2_enqReq_rl$EN; // register f12f2_full @@ -837,23 +856,23 @@ module mkFetchStage(CLK, wire f22f3_clearReq_rl$D_IN, f22f3_clearReq_rl$EN; // register f22f3_data_0 - reg [267 : 0] f22f3_data_0; - wire [267 : 0] f22f3_data_0$D_IN; + reg [337 : 0] f22f3_data_0; + wire [337 : 0] f22f3_data_0$D_IN; wire f22f3_data_0$EN; // register f22f3_data_1 - reg [267 : 0] f22f3_data_1; - wire [267 : 0] f22f3_data_1$D_IN; + reg [337 : 0] f22f3_data_1; + wire [337 : 0] f22f3_data_1$D_IN; wire f22f3_data_1$EN; // register f22f3_data_2 - reg [267 : 0] f22f3_data_2; - wire [267 : 0] f22f3_data_2$D_IN; + reg [337 : 0] f22f3_data_2; + wire [337 : 0] f22f3_data_2$D_IN; wire f22f3_data_2$EN; // register f22f3_data_3 - reg [267 : 0] f22f3_data_3; - wire [267 : 0] f22f3_data_3$D_IN; + reg [337 : 0] f22f3_data_3; + wire [337 : 0] f22f3_data_3$D_IN; wire f22f3_data_3$EN; // register f22f3_deqP @@ -875,8 +894,8 @@ module mkFetchStage(CLK, wire f22f3_enqP$EN; // register f22f3_enqReq_rl - reg [268 : 0] f22f3_enqReq_rl; - wire [268 : 0] f22f3_enqReq_rl$D_IN; + reg [338 : 0] f22f3_enqReq_rl; + wire [338 : 0] f22f3_enqReq_rl$D_IN; wire f22f3_enqReq_rl$EN; // register f22f3_full @@ -888,13 +907,13 @@ module mkFetchStage(CLK, wire f32d_clearReq_rl$D_IN, f32d_clearReq_rl$EN; // register f32d_data_0 - reg [267 : 0] f32d_data_0; - wire [267 : 0] f32d_data_0$D_IN; + reg [334 : 0] f32d_data_0; + wire [334 : 0] f32d_data_0$D_IN; wire f32d_data_0$EN; // register f32d_data_1 - reg [267 : 0] f32d_data_1; - wire [267 : 0] f32d_data_1$D_IN; + reg [334 : 0] f32d_data_1; + wire [334 : 0] f32d_data_1$D_IN; wire f32d_data_1$EN; // register f32d_deqP @@ -914,8 +933,8 @@ module mkFetchStage(CLK, wire f32d_enqP$D_IN, f32d_enqP$EN; // register f32d_enqReq_rl - reg [268 : 0] f32d_enqReq_rl; - wire [268 : 0] f32d_enqReq_rl$D_IN; + reg [335 : 0] f32d_enqReq_rl; + wire [335 : 0] f32d_enqReq_rl$D_IN; wire f32d_enqReq_rl$EN; // register f32d_full @@ -927,14 +946,18 @@ module mkFetchStage(CLK, wire [3 : 0] f_main_epoch$D_IN; wire f_main_epoch$EN; + // register fetch3_epoch + reg fetch3_epoch; + wire fetch3_epoch$D_IN, fetch3_epoch$EN; + // register instdata_data_0 - reg [259 : 0] instdata_data_0; - wire [259 : 0] instdata_data_0$D_IN; + reg [389 : 0] instdata_data_0; + wire [389 : 0] instdata_data_0$D_IN; wire instdata_data_0$EN; // register instdata_data_1 - reg [259 : 0] instdata_data_1; - wire [259 : 0] instdata_data_1$D_IN; + reg [389 : 0] instdata_data_1; + wire [389 : 0] instdata_data_1$D_IN; wire instdata_data_1$EN; // register instdata_deqP_rl @@ -954,8 +977,8 @@ module mkFetchStage(CLK, wire instdata_full_rl$D_IN, instdata_full_rl$EN; // register napTrainByDecQ_data_0 - reg [127 : 0] napTrainByDecQ_data_0; - wire [127 : 0] napTrainByDecQ_data_0$D_IN; + reg [257 : 0] napTrainByDecQ_data_0; + wire [257 : 0] napTrainByDecQ_data_0$D_IN; wire napTrainByDecQ_data_0$EN; // register napTrainByDecQ_empty_rl @@ -1995,13 +2018,13 @@ module mkFetchStage(CLK, wire out_fifo_dequeueFifo_rl$D_IN, out_fifo_dequeueFifo_rl$EN; // register out_fifo_enqueueElement_0_rl - reg [388 : 0] out_fifo_enqueueElement_0_rl; - wire [388 : 0] out_fifo_enqueueElement_0_rl$D_IN; + reg [591 : 0] out_fifo_enqueueElement_0_rl; + wire [591 : 0] out_fifo_enqueueElement_0_rl$D_IN; wire out_fifo_enqueueElement_0_rl$EN; // register out_fifo_enqueueElement_1_rl - reg [388 : 0] out_fifo_enqueueElement_1_rl; - wire [388 : 0] out_fifo_enqueueElement_1_rl$D_IN; + reg [591 : 0] out_fifo_enqueueElement_1_rl; + wire [591 : 0] out_fifo_enqueueElement_1_rl$D_IN; wire out_fifo_enqueueElement_1_rl$EN; // register out_fifo_enqueueFifo_rl @@ -2017,8 +2040,8 @@ module mkFetchStage(CLK, wire out_fifo_willDequeue_1_rl$D_IN, out_fifo_willDequeue_1_rl$EN; // register pc_reg_rl - reg [63 : 0] pc_reg_rl; - wire [63 : 0] pc_reg_rl$D_IN; + reg [128 : 0] pc_reg_rl; + wire [128 : 0] pc_reg_rl$D_IN; wire pc_reg_rl$EN; // register perfReqQ_clearReq_rl @@ -2047,19 +2070,20 @@ module mkFetchStage(CLK, reg perfReqQ_full; wire perfReqQ_full$D_IN, perfReqQ_full$EN; - // register rg_half_inst_lsbs - reg [15 : 0] rg_half_inst_lsbs; - wire [15 : 0] rg_half_inst_lsbs$D_IN; - wire rg_half_inst_lsbs$EN; + // register rg_pending_decode + reg [584 : 0] rg_pending_decode; + wire [584 : 0] rg_pending_decode$D_IN; + wire rg_pending_decode$EN; - // register rg_half_inst_pc - reg [63 : 0] rg_half_inst_pc; - wire [63 : 0] rg_half_inst_pc$D_IN; - wire rg_half_inst_pc$EN; + // register rg_pending_f32d + reg [333 : 0] rg_pending_f32d; + wire [333 : 0] rg_pending_f32d$D_IN; + wire rg_pending_f32d$EN; - // register rg_pending_straddle - reg rg_pending_straddle; - wire rg_pending_straddle$D_IN, rg_pending_straddle$EN; + // register rg_pending_n_items + reg [1 : 0] rg_pending_n_items; + wire [1 : 0] rg_pending_n_items$D_IN; + wire rg_pending_n_items$EN; // register started reg started; @@ -2075,9 +2099,9 @@ module mkFetchStage(CLK, wire waitForRedirect$EN; // ports of submodule dirPred - wire [63 : 0] dirPred$pred_0_pred_pc, - dirPred$pred_1_pred_pc, - dirPred$update_pc; + wire [128 : 0] dirPred$pred_0_pred_pc, + dirPred$pred_1_pred_pc, + dirPred$update_pc; wire [24 : 0] dirPred$pred_0_pred, dirPred$pred_1_pred; wire [23 : 0] dirPred$update_train; wire dirPred$EN_flush, @@ -2088,99 +2112,9 @@ module mkFetchStage(CLK, dirPred$update_mispred, dirPred$update_taken; - // ports of submodule f12f2_clearReq_dummy2_0 - wire f12f2_clearReq_dummy2_0$D_IN, f12f2_clearReq_dummy2_0$EN; - - // ports of submodule f12f2_clearReq_dummy2_1 - wire f12f2_clearReq_dummy2_1$D_IN, - f12f2_clearReq_dummy2_1$EN, - f12f2_clearReq_dummy2_1$Q_OUT; - - // ports of submodule f12f2_deqReq_dummy2_0 - wire f12f2_deqReq_dummy2_0$D_IN, f12f2_deqReq_dummy2_0$EN; - - // ports of submodule f12f2_deqReq_dummy2_1 - wire f12f2_deqReq_dummy2_1$D_IN, f12f2_deqReq_dummy2_1$EN; - - // ports of submodule f12f2_deqReq_dummy2_2 - wire f12f2_deqReq_dummy2_2$D_IN, - f12f2_deqReq_dummy2_2$EN, - f12f2_deqReq_dummy2_2$Q_OUT; - - // ports of submodule f12f2_enqReq_dummy2_0 - wire f12f2_enqReq_dummy2_0$D_IN, f12f2_enqReq_dummy2_0$EN; - - // ports of submodule f12f2_enqReq_dummy2_1 - wire f12f2_enqReq_dummy2_1$D_IN, f12f2_enqReq_dummy2_1$EN; - - // ports of submodule f12f2_enqReq_dummy2_2 - wire f12f2_enqReq_dummy2_2$D_IN, - f12f2_enqReq_dummy2_2$EN, - f12f2_enqReq_dummy2_2$Q_OUT; - - // ports of submodule f22f3_clearReq_dummy2_0 - wire f22f3_clearReq_dummy2_0$D_IN, f22f3_clearReq_dummy2_0$EN; - - // ports of submodule f22f3_clearReq_dummy2_1 - wire f22f3_clearReq_dummy2_1$D_IN, - f22f3_clearReq_dummy2_1$EN, - f22f3_clearReq_dummy2_1$Q_OUT; - - // ports of submodule f22f3_deqReq_dummy2_0 - wire f22f3_deqReq_dummy2_0$D_IN, f22f3_deqReq_dummy2_0$EN; - - // ports of submodule f22f3_deqReq_dummy2_1 - wire f22f3_deqReq_dummy2_1$D_IN, f22f3_deqReq_dummy2_1$EN; - - // ports of submodule f22f3_deqReq_dummy2_2 - wire f22f3_deqReq_dummy2_2$D_IN, - f22f3_deqReq_dummy2_2$EN, - f22f3_deqReq_dummy2_2$Q_OUT; - - // ports of submodule f22f3_enqReq_dummy2_0 - wire f22f3_enqReq_dummy2_0$D_IN, f22f3_enqReq_dummy2_0$EN; - - // ports of submodule f22f3_enqReq_dummy2_1 - wire f22f3_enqReq_dummy2_1$D_IN, f22f3_enqReq_dummy2_1$EN; - - // ports of submodule f22f3_enqReq_dummy2_2 - wire f22f3_enqReq_dummy2_2$D_IN, - f22f3_enqReq_dummy2_2$EN, - f22f3_enqReq_dummy2_2$Q_OUT; - - // ports of submodule f32d_clearReq_dummy2_0 - wire f32d_clearReq_dummy2_0$D_IN, f32d_clearReq_dummy2_0$EN; - - // ports of submodule f32d_clearReq_dummy2_1 - wire f32d_clearReq_dummy2_1$D_IN, - f32d_clearReq_dummy2_1$EN, - f32d_clearReq_dummy2_1$Q_OUT; - - // ports of submodule f32d_deqReq_dummy2_0 - wire f32d_deqReq_dummy2_0$D_IN, f32d_deqReq_dummy2_0$EN; - - // ports of submodule f32d_deqReq_dummy2_1 - wire f32d_deqReq_dummy2_1$D_IN, f32d_deqReq_dummy2_1$EN; - - // ports of submodule f32d_deqReq_dummy2_2 - wire f32d_deqReq_dummy2_2$D_IN, - f32d_deqReq_dummy2_2$EN, - f32d_deqReq_dummy2_2$Q_OUT; - - // ports of submodule f32d_enqReq_dummy2_0 - wire f32d_enqReq_dummy2_0$D_IN, f32d_enqReq_dummy2_0$EN; - - // ports of submodule f32d_enqReq_dummy2_1 - wire f32d_enqReq_dummy2_1$D_IN, f32d_enqReq_dummy2_1$EN; - - // ports of submodule f32d_enqReq_dummy2_2 - wire f32d_enqReq_dummy2_2$D_IN, - f32d_enqReq_dummy2_2$EN, - f32d_enqReq_dummy2_2$Q_OUT; - // ports of submodule iMem - wire [582 : 0] iMem$to_parent_fromP_enq_x; - wire [578 : 0] iMem$to_parent_rsToP_first; + wire [586 : 0] iMem$to_parent_fromP_enq_x; + wire [582 : 0] iMem$to_parent_rsToP_first; wire [71 : 0] iMem$to_parent_rqToP_first; wire [67 : 0] iMem$cRqStuck_get, iMem$pRqStuck_get; wire [65 : 0] iMem$perf_resp, iMem$to_proc_response_get; @@ -2217,7 +2151,7 @@ module mkFetchStage(CLK, // ports of submodule iTlb wire [80 : 0] iTlb$toParent_rsFromP_enq_x; - wire [68 : 0] iTlb$to_proc_response_get; + wire [69 : 0] iTlb$to_proc_response_get; wire [66 : 0] iTlb$perf_resp; wire [63 : 0] iTlb$to_proc_request_put; wire [48 : 0] iTlb$updateVMInfo_vm; @@ -2251,54 +2185,6 @@ module mkFetchStage(CLK, iTlb$toParent_rqToP_notEmpty, iTlb$toParent_rsFromP_notFull; - // ports of submodule instdata_deqP_dummy2_0 - wire instdata_deqP_dummy2_0$D_IN, - instdata_deqP_dummy2_0$EN, - instdata_deqP_dummy2_0$Q_OUT; - - // ports of submodule instdata_deqP_dummy2_1 - wire instdata_deqP_dummy2_1$D_IN, - instdata_deqP_dummy2_1$EN, - instdata_deqP_dummy2_1$Q_OUT; - - // ports of submodule instdata_empty_dummy2_0 - wire instdata_empty_dummy2_0$D_IN, - instdata_empty_dummy2_0$EN, - instdata_empty_dummy2_0$Q_OUT; - - // ports of submodule instdata_empty_dummy2_1 - wire instdata_empty_dummy2_1$D_IN, - instdata_empty_dummy2_1$EN, - instdata_empty_dummy2_1$Q_OUT; - - // ports of submodule instdata_empty_dummy2_2 - wire instdata_empty_dummy2_2$D_IN, - instdata_empty_dummy2_2$EN, - instdata_empty_dummy2_2$Q_OUT; - - // ports of submodule instdata_enqP_dummy2_0 - wire instdata_enqP_dummy2_0$D_IN, - instdata_enqP_dummy2_0$EN, - instdata_enqP_dummy2_0$Q_OUT; - - // ports of submodule instdata_enqP_dummy2_1 - wire instdata_enqP_dummy2_1$D_IN, - instdata_enqP_dummy2_1$EN, - instdata_enqP_dummy2_1$Q_OUT; - - // ports of submodule instdata_full_dummy2_0 - wire instdata_full_dummy2_0$D_IN, instdata_full_dummy2_0$EN; - - // ports of submodule instdata_full_dummy2_1 - wire instdata_full_dummy2_1$D_IN, - instdata_full_dummy2_1$EN, - instdata_full_dummy2_1$Q_OUT; - - // ports of submodule instdata_full_dummy2_2 - wire instdata_full_dummy2_2$D_IN, - instdata_full_dummy2_2$EN, - instdata_full_dummy2_2$Q_OUT; - // ports of submodule mmio wire [65 : 0] mmio$bootRomResp, mmio$toCore_instResp_enq_x; wire [63 : 0] mmio$bootRomReq_phyPc, @@ -2323,50 +2209,12 @@ module mkFetchStage(CLK, mmio$toCore_instReq_notEmpty, mmio$toCore_instResp_notFull; - // ports of submodule napTrainByDecQ_deqP_dummy2_0 - wire napTrainByDecQ_deqP_dummy2_0$D_IN, napTrainByDecQ_deqP_dummy2_0$EN; - - // ports of submodule napTrainByDecQ_deqP_dummy2_1 - wire napTrainByDecQ_deqP_dummy2_1$D_IN, napTrainByDecQ_deqP_dummy2_1$EN; - - // ports of submodule napTrainByDecQ_empty_dummy2_0 - wire napTrainByDecQ_empty_dummy2_0$D_IN, - napTrainByDecQ_empty_dummy2_0$EN, - napTrainByDecQ_empty_dummy2_0$Q_OUT; - - // ports of submodule napTrainByDecQ_empty_dummy2_1 - wire napTrainByDecQ_empty_dummy2_1$D_IN, - napTrainByDecQ_empty_dummy2_1$EN, - napTrainByDecQ_empty_dummy2_1$Q_OUT; - - // ports of submodule napTrainByDecQ_empty_dummy2_2 - wire napTrainByDecQ_empty_dummy2_2$D_IN, - napTrainByDecQ_empty_dummy2_2$EN, - napTrainByDecQ_empty_dummy2_2$Q_OUT; - - // ports of submodule napTrainByDecQ_enqP_dummy2_0 - wire napTrainByDecQ_enqP_dummy2_0$D_IN, napTrainByDecQ_enqP_dummy2_0$EN; - - // ports of submodule napTrainByDecQ_enqP_dummy2_1 - wire napTrainByDecQ_enqP_dummy2_1$D_IN, napTrainByDecQ_enqP_dummy2_1$EN; - - // ports of submodule napTrainByDecQ_full_dummy2_0 - wire napTrainByDecQ_full_dummy2_0$D_IN, napTrainByDecQ_full_dummy2_0$EN; - - // ports of submodule napTrainByDecQ_full_dummy2_1 - wire napTrainByDecQ_full_dummy2_1$D_IN, - napTrainByDecQ_full_dummy2_1$EN, - napTrainByDecQ_full_dummy2_1$Q_OUT; - - // ports of submodule napTrainByDecQ_full_dummy2_2 - wire napTrainByDecQ_full_dummy2_2$D_IN, - napTrainByDecQ_full_dummy2_2$EN, - napTrainByDecQ_full_dummy2_2$Q_OUT; - // ports of submodule nextAddrPred_next_addrs - wire [63 : 0] nextAddrPred_next_addrs$D_IN, - nextAddrPred_next_addrs$D_OUT_1, - nextAddrPred_next_addrs$D_OUT_2; + wire [128 : 0] nextAddrPred_next_addrs$D_IN, + nextAddrPred_next_addrs$D_OUT_1, + nextAddrPred_next_addrs$D_OUT_2, + nextAddrPred_next_addrs$D_OUT_3, + nextAddrPred_next_addrs$D_OUT_4; wire [7 : 0] nextAddrPred_next_addrs$ADDR_1, nextAddrPred_next_addrs$ADDR_2, nextAddrPred_next_addrs$ADDR_3, @@ -2376,10 +2224,12 @@ module mkFetchStage(CLK, wire nextAddrPred_next_addrs$WE; // ports of submodule nextAddrPred_tags - wire [53 : 0] nextAddrPred_tags$D_IN, + wire [54 : 0] nextAddrPred_tags$D_IN, nextAddrPred_tags$D_OUT_1, nextAddrPred_tags$D_OUT_2, - nextAddrPred_tags$D_OUT_3; + nextAddrPred_tags$D_OUT_3, + nextAddrPred_tags$D_OUT_4, + nextAddrPred_tags$D_OUT_5; wire [7 : 0] nextAddrPred_tags$ADDR_1, nextAddrPred_tags$ADDR_2, nextAddrPred_tags$ADDR_3, @@ -2388,56 +2238,8 @@ module mkFetchStage(CLK, nextAddrPred_tags$ADDR_IN; wire nextAddrPred_tags$WE; - // ports of submodule out_fifo_dequeueFifo_dummy2_0 - wire out_fifo_dequeueFifo_dummy2_0$D_IN, - out_fifo_dequeueFifo_dummy2_0$EN, - out_fifo_dequeueFifo_dummy2_0$Q_OUT; - - // ports of submodule out_fifo_dequeueFifo_dummy2_1 - wire out_fifo_dequeueFifo_dummy2_1$D_IN, - out_fifo_dequeueFifo_dummy2_1$EN, - out_fifo_dequeueFifo_dummy2_1$Q_OUT; - - // ports of submodule out_fifo_dequeueFifo_dummy2_2 - wire out_fifo_dequeueFifo_dummy2_2$D_IN, - out_fifo_dequeueFifo_dummy2_2$EN, - out_fifo_dequeueFifo_dummy2_2$Q_OUT; - - // ports of submodule out_fifo_enqueueElement_0_dummy2_0 - wire out_fifo_enqueueElement_0_dummy2_0$D_IN, - out_fifo_enqueueElement_0_dummy2_0$EN; - - // ports of submodule out_fifo_enqueueElement_0_dummy2_1 - wire out_fifo_enqueueElement_0_dummy2_1$D_IN, - out_fifo_enqueueElement_0_dummy2_1$EN, - out_fifo_enqueueElement_0_dummy2_1$Q_OUT; - - // ports of submodule out_fifo_enqueueElement_1_dummy2_0 - wire out_fifo_enqueueElement_1_dummy2_0$D_IN, - out_fifo_enqueueElement_1_dummy2_0$EN; - - // ports of submodule out_fifo_enqueueElement_1_dummy2_1 - wire out_fifo_enqueueElement_1_dummy2_1$D_IN, - out_fifo_enqueueElement_1_dummy2_1$EN, - out_fifo_enqueueElement_1_dummy2_1$Q_OUT; - - // ports of submodule out_fifo_enqueueFifo_dummy2_0 - wire out_fifo_enqueueFifo_dummy2_0$D_IN, - out_fifo_enqueueFifo_dummy2_0$EN, - out_fifo_enqueueFifo_dummy2_0$Q_OUT; - - // ports of submodule out_fifo_enqueueFifo_dummy2_1 - wire out_fifo_enqueueFifo_dummy2_1$D_IN, - out_fifo_enqueueFifo_dummy2_1$EN, - out_fifo_enqueueFifo_dummy2_1$Q_OUT; - - // ports of submodule out_fifo_enqueueFifo_dummy2_2 - wire out_fifo_enqueueFifo_dummy2_2$D_IN, - out_fifo_enqueueFifo_dummy2_2$EN, - out_fifo_enqueueFifo_dummy2_2$Q_OUT; - // ports of submodule out_fifo_internalFifos_0 - wire [387 : 0] out_fifo_internalFifos_0$D_IN, + wire [590 : 0] out_fifo_internalFifos_0$D_IN, out_fifo_internalFifos_0$D_OUT; wire out_fifo_internalFifos_0$CLR, out_fifo_internalFifos_0$DEQ, @@ -2446,7 +2248,7 @@ module mkFetchStage(CLK, out_fifo_internalFifos_0$FULL_N; // ports of submodule out_fifo_internalFifos_1 - wire [387 : 0] out_fifo_internalFifos_1$D_IN, + wire [590 : 0] out_fifo_internalFifos_1$D_IN, out_fifo_internalFifos_1$D_OUT; wire out_fifo_internalFifos_1$CLR, out_fifo_internalFifos_1$DEQ, @@ -2454,66 +2256,9 @@ module mkFetchStage(CLK, out_fifo_internalFifos_1$ENQ, out_fifo_internalFifos_1$FULL_N; - // ports of submodule out_fifo_willDequeue_0_dummy2_0 - wire out_fifo_willDequeue_0_dummy2_0$D_IN, - out_fifo_willDequeue_0_dummy2_0$EN; - - // ports of submodule out_fifo_willDequeue_0_dummy2_1 - wire out_fifo_willDequeue_0_dummy2_1$D_IN, - out_fifo_willDequeue_0_dummy2_1$EN, - out_fifo_willDequeue_0_dummy2_1$Q_OUT; - - // ports of submodule out_fifo_willDequeue_1_dummy2_0 - wire out_fifo_willDequeue_1_dummy2_0$D_IN, - out_fifo_willDequeue_1_dummy2_0$EN; - - // ports of submodule out_fifo_willDequeue_1_dummy2_1 - wire out_fifo_willDequeue_1_dummy2_1$D_IN, - out_fifo_willDequeue_1_dummy2_1$EN, - out_fifo_willDequeue_1_dummy2_1$Q_OUT; - - // ports of submodule pc_reg_dummy2_0 - wire pc_reg_dummy2_0$D_IN, pc_reg_dummy2_0$EN, pc_reg_dummy2_0$Q_OUT; - - // ports of submodule pc_reg_dummy2_1 - wire pc_reg_dummy2_1$D_IN, pc_reg_dummy2_1$EN, pc_reg_dummy2_1$Q_OUT; - - // ports of submodule pc_reg_dummy2_2 - wire pc_reg_dummy2_2$D_IN, pc_reg_dummy2_2$EN, pc_reg_dummy2_2$Q_OUT; - - // ports of submodule perfReqQ_clearReq_dummy2_0 - wire perfReqQ_clearReq_dummy2_0$D_IN, perfReqQ_clearReq_dummy2_0$EN; - - // ports of submodule perfReqQ_clearReq_dummy2_1 - wire perfReqQ_clearReq_dummy2_1$D_IN, - perfReqQ_clearReq_dummy2_1$EN, - perfReqQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule perfReqQ_deqReq_dummy2_0 - wire perfReqQ_deqReq_dummy2_0$D_IN, perfReqQ_deqReq_dummy2_0$EN; - - // ports of submodule perfReqQ_deqReq_dummy2_1 - wire perfReqQ_deqReq_dummy2_1$D_IN, perfReqQ_deqReq_dummy2_1$EN; - - // ports of submodule perfReqQ_deqReq_dummy2_2 - wire perfReqQ_deqReq_dummy2_2$D_IN, - perfReqQ_deqReq_dummy2_2$EN, - perfReqQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule perfReqQ_enqReq_dummy2_0 - wire perfReqQ_enqReq_dummy2_0$D_IN, perfReqQ_enqReq_dummy2_0$EN; - - // ports of submodule perfReqQ_enqReq_dummy2_1 - wire perfReqQ_enqReq_dummy2_1$D_IN, perfReqQ_enqReq_dummy2_1$EN; - - // ports of submodule perfReqQ_enqReq_dummy2_2 - wire perfReqQ_enqReq_dummy2_2$D_IN, - perfReqQ_enqReq_dummy2_2$EN, - perfReqQ_enqReq_dummy2_2$Q_OUT; - // ports of submodule ras - wire [64 : 0] ras$ras_0_popPush_pushAddr, ras$ras_1_popPush_pushAddr; - wire [63 : 0] ras$ras_0_first, ras$ras_1_first; + wire [129 : 0] ras$ras_0_popPush_pushAddr, ras$ras_1_popPush_pushAddr; + wire [128 : 0] ras$ras_0_first, ras$ras_1_first; wire ras$EN_flush, ras$EN_ras_0_popPush, ras$EN_ras_1_popPush, @@ -2522,11 +2267,13 @@ module mkFetchStage(CLK, ras$ras_1_popPush_pop; // rule scheduling signals - wire CAN_FIRE_RL_doDecode, + wire CAN_FIRE_RL_decode_epoch_canon, + CAN_FIRE_RL_doDecode, CAN_FIRE_RL_doFetch1, CAN_FIRE_RL_doFetch2, CAN_FIRE_RL_doFetch3, CAN_FIRE_RL_doTrainNAP, + CAN_FIRE_RL_ehr_pending_straddle_canon, CAN_FIRE_RL_f12f2_canonicalize, CAN_FIRE_RL_f12f2_clearReq_canon, CAN_FIRE_RL_f12f2_deqReq_canon, @@ -2592,15 +2339,18 @@ module mkFetchStage(CLK, CAN_FIRE_pipelines_0_deq, CAN_FIRE_pipelines_1_deq, CAN_FIRE_redirect, + CAN_FIRE_setWaitFlush, CAN_FIRE_setWaitRedirect, CAN_FIRE_start, CAN_FIRE_stop, CAN_FIRE_train_predictors, + WILL_FIRE_RL_decode_epoch_canon, WILL_FIRE_RL_doDecode, WILL_FIRE_RL_doFetch1, WILL_FIRE_RL_doFetch2, WILL_FIRE_RL_doFetch3, WILL_FIRE_RL_doTrainNAP, + WILL_FIRE_RL_ehr_pending_straddle_canon, WILL_FIRE_RL_f12f2_canonicalize, WILL_FIRE_RL_f12f2_clearReq_canon, WILL_FIRE_RL_f12f2_deqReq_canon, @@ -2666,956 +2416,1788 @@ module mkFetchStage(CLK, WILL_FIRE_pipelines_0_deq, WILL_FIRE_pipelines_1_deq, WILL_FIRE_redirect, + WILL_FIRE_setWaitFlush, WILL_FIRE_setWaitRedirect, WILL_FIRE_start, WILL_FIRE_stop, WILL_FIRE_train_predictors; // inputs to muxes for submodule ports + wire [128 : 0] MUX_pc_reg_lat_0$wset_1__VAL_2; wire [63 : 0] MUX_iTlb$to_proc_request_put_1__VAL_2; - wire MUX_iMem$to_proc_request_put_1__SEL_1, - MUX_rg_pending_straddle$write_1__SEL_1; + wire MUX_iMem$to_proc_request_put_1__SEL_1; // remaining internal signals - reg [63 : 0] SEL_ARR_instdata_data_0_686_BITS_259_TO_196_99_ETC___d4994, - in_ppc__h150788, - start_PC__h117515, - value__h117654, - value__h117656, - value__h118910, - x__h116419, - x__h116447, - x__h143344, - x__h149997, - x__h160939, - x__h161003, - x__h167949, - x__h168127, - x__h168147, - x__h174427; - reg [31 : 0] CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q188, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q177, - SEL_ARR_instdata_data_0_686_BITS_161_TO_130_17_ETC___d5179, - SEL_ARR_instdata_data_0_686_BITS_193_TO_162_16_ETC___d5171, - SEL_ARR_instdata_data_0_686_BITS_31_TO_0_764_i_ETC___d4767, - SEL_ARR_instdata_data_0_686_BITS_63_TO_32_751__ETC___d4754, - x__h161061, - x__h166575, - x__h168161, - x__h173399; - reg [20 : 0] CASE_decode_180_BITS_94_TO_92_0_decode_180_BIT_ETC__q5, - CASE_decode_768_BITS_94_TO_92_0_decode_768_BIT_ETC__q8; - reg [15 : 0] SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4051, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4344; - reg [11 : 0] CASE_decode_180_BITS_72_TO_61_1_decode_180_BIT_ETC__q6, - CASE_decode_768_BITS_72_TO_61_1_decode_768_BIT_ETC__q9, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q210, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206; - reg [9 : 0] CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q211, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207; - reg [4 : 0] CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q185, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q198, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q201, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q39, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q65, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q68, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q174, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q191, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q194, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q60, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q63; - reg [3 : 0] CASE_IF_f22f3_enqReq_lat_0_whas__14_THEN_IF_f2_ETC__q218, - CASE_IF_f32d_enqReq_lat_0_whas__46_THEN_IF_f32_ETC__q221, - CASE_f22f3_enqReq_lat_0wget_BITS_73_TO_70_0_f_ETC__q216, - CASE_f22f3_enqReq_rl_BITS_73_TO_70_0_f22f3_enq_ETC__q217, - CASE_f32d_enqReq_lat_0wget_BITS_73_TO_70_0_f3_ETC__q219, - CASE_f32d_enqReq_rl_BITS_73_TO_70_0_f32d_enqRe_ETC__q220, - CASE_iTlbto_proc_response_get_BITS_3_TO_0_0_i_ETC__q1, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q215, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q55, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q214, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q57, - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599, - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627, - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655, - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683, - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050, - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078, - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031, - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059, - SEL_ARR_f22f3_data_0_470_BITS_3_TO_0_950_f22f3_ETC___d3955, - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4683, - out_main_epoch__h116425; - reg [2 : 0] CASE_decode_180_BITS_77_TO_75_0_decode_180_BIT_ETC__q4, - CASE_decode_768_BITS_77_TO_75_0_decode_768_BIT_ETC__q7, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q181, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q170, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q172, - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671, - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683; - reg [1 : 0] CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q30, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q31, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q32, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q33, - SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713, - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694; - reg CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q203, - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q40, - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q41, - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q42, - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q43, - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q44, - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q45, - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q46, - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q47, - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q48, - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q49, - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q50, - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q51, - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q52, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q154, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q155, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q156, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q157, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q158, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q159, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q160, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q161, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q162, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q163, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q164, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q165, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q166, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q34, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q35, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q36, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q37, - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q38, - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q186, - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q187, - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q196, - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q197, - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q199, - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q200, - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q202, - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q64, - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q66, - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q67, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q105, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q106, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q107, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q108, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q109, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q110, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q111, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q112, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q113, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q114, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q115, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q116, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q117, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q118, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q119, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q120, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q121, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q122, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q123, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q124, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q125, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q126, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q127, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q128, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q129, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q130, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q131, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q132, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q133, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q134, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q135, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q136, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q137, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q138, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q139, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q140, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q178, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q179, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q180, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q182, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q184, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q212, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q213, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q23, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q26, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q27, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q53, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q56, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q13, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q14, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q141, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q142, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q143, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q144, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q145, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q146, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q147, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q148, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q149, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q15, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q150, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q151, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q152, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q153, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q16, - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q17, - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q175, - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q176, - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q189, - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q190, - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q192, - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q193, - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q195, - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q59, - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q61, - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q62, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q10, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q100, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q101, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q102, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q103, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q104, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q11, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q12, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q167, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q168, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q169, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q171, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q173, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q208, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q209, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q24, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q25, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q28, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q29, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q54, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q58, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q69, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q70, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q71, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q72, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q73, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q74, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q75, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q76, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q77, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q78, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q79, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q80, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q81, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q82, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q83, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q84, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q85, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q86, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q87, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q88, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q89, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q90, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q91, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q92, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q93, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q94, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q95, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q96, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q97, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q98, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q99, - CASE_x4600_0_out_fifo_internalFifos_0FULL_N_1_ETC__q2, - CASE_x4856_0_out_fifo_internalFifos_0FULL_N_1_ETC__q3, - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5164, - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5463, - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686, - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697, - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709, - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722, - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736, - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751, - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767, - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3784, - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3802, - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3821, - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3841, - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3862, - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3884, - SEL_ARR_NOT_f22f3_data_0_470_BIT_4_496_937_NOT_ETC___d3942, - SEL_ARR_NOT_f22f3_data_0_470_BIT_5_486_924_NOT_ETC___d3929, - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483, - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763, - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3501, - SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491, - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719, - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4700, - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331, - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5627, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5635, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6165, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6167, - value__h117642, - x__h116417; - wire [259 : 0] SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6132, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6338; - wire [138 : 0] SEL_ARR_f12f2_data_0_378_BITS_68_TO_5_388_f12f_ETC___d3466; - wire [127 : 0] IF_IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AN_ETC___d5480, - IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5483, - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5481, - IF_SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_ETC___d5482; - wire [99 : 0] decode___d4768, decode___d5180; - wire [74 : 0] NOT_f22f3_enqReq_dummy2_2_read__11_45_OR_IF_f2_ETC___d431, - NOT_f32d_enqReq_dummy2_2_read__47_77_OR_IF_f32_ETC___d763; - wire [71 : 0] SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5918, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6275, - decode_180_BITS_99_TO_95_184_CONCAT_IF_decode__ETC___d5381, - decode_768_BITS_99_TO_95_772_CONCAT_IF_decode__ETC___d4969; - wire [69 : 0] IF_iTlb_to_proc_response_get_369_BIT_4_370_THE_ETC___d3465; - wire [68 : 0] NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6129, - NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6335; - wire [65 : 0] IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4340, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4633; - wire [64 : 0] decodeBrPred___d4973, decodeBrPred___d5385; - wire [63 : 0] IF_IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AN_ETC___d5453, - IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5456, - IF_NOT_decode_180_BIT_7_192_203_OR_decode_180__ETC___d5400, - IF_NOT_decode_768_BIT_7_780_791_OR_decode_768__ETC___d4988, - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5454, - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5451, - IF_decode_180_BIT_7_192_AND_NOT_decode_180_BIT_ETC___d5398, - IF_decode_768_BIT_7_780_AND_NOT_decode_768_BIT_ETC___d4986, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1381, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d840, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d845, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1408, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1413, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1948, - IF_pc_reg_dummy2_0_read__063_AND_pc_reg_dummy2_ETC___d3337, - IF_pc_reg_lat_1_whas_THEN_pc_reg_lat_1_wget_EL_ETC___d9, - _theResult___snd_snd_snd_fst__h122369, - decode_pred_next_pc__h146966, - decode_pred_next_pc__h153837, - in_ppc__h143612, - next_PC__h143443, - next_PC__h150615, - next_pc___1__h122112, - next_pc___1__h122117, - pc_start__h119765, - pred_next_pc__h114157, - pred_next_pc__h114166, - pred_next_pc__h115374, - tval__h116722, - upd__h1659, - upd__h1686, - x1_avValue_fst_ppc__h147284, - x1_avValue_fst_ppc__h154042, - x__h115849, - x__h116716, - x__h147295, - x__h154053, - x__h160492, - x__h160545, - x__h16495, - x__h16558, - x__h16572, - x__h27539, - x__h27602, - x__h27616, - y__h117541, - y__h160555, - y_avValue_snd_snd__h119829, - y_avValue_snd_snd_snd_fst__h122323, - y_avValue_snd_snd_snd_fst__h122348; - wire [45 : 0] IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d2037, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d2140, - NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d5917, - NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6274; - wire [31 : 0] IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4304, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4306, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4308, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4310, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4312, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4314, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4316, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4319, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4322, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4324, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4326, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4327, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4329, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4331, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4333, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4335, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4337, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4597, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4599, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4601, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4603, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4605, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4607, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4609, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4612, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4615, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4617, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4619, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4620, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4622, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4624, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4626, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4628, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4630, - IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4012, - IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4020, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1217, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d860, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1428, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1784, - _theResult___snd_fst__h122365, - _theResult___snd_fst__h131373, - instr__h123060, - instr__h123207, - instr__h123401, - instr__h123598, - instr__h123829, - instr__h124285, - instr__h124403, - instr__h124468, - instr__h124787, - instr__h125128, - instr__h125317, - instr__h125449, - instr__h125680, - instr__h125940, - instr__h126113, - instr__h126284, - instr__h126474, - instr__h126664, - instr__h126782, - instr__h126963, - instr__h127084, - instr__h127180, - instr__h127317, - instr__h127454, - instr__h127591, - instr__h127730, - instr__h127869, - instr__h128029, - instr__h128126, - instr__h128281, - instr__h128482, - instr__h128635, - instr__h129736, - instr__h129891, - instr__h130092, - instr__h130245, - instr__h131614, - instr__h131761, - instr__h131955, - instr__h132152, - instr__h132382, - instr__h132836, - instr__h132954, - instr__h133019, - instr__h133338, - instr__h133679, - instr__h133868, - instr__h134000, - instr__h134231, - instr__h134491, - instr__h134664, - instr__h134835, - instr__h135025, - instr__h135215, - instr__h135333, - instr__h135514, - instr__h135635, - instr__h135731, - instr__h135868, - instr__h136005, - instr__h136142, - instr__h136281, - instr__h136420, - instr__h136580, - instr__h136677, - instr__h136832, - instr__h137033, - instr__h137186, - instr__h138231, - instr__h138386, - instr__h138587, - instr__h138740, - orig_inst___1__h122110, - orig_inst___1__h131399, - value__h119455, - value__h119609, - y_avValue_snd_fst__h122334, - y_avValue_snd_fst__h131336; - wire [26 : 0] NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d5997, - NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6304; - wire [23 : 0] IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5007, - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5411, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d855, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1423, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5548, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6142; - wire [20 : 0] IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1994, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1995, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1997, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1998, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2097, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2098, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2100, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2101, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5710, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5711, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5712, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5713, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5714, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6190, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6191, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6192, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6193, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6194, - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4117, - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4410; - wire [19 : 0] imm20__h125182, imm20__h133733; - wire [15 : 0] IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4053, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4346, - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4015, - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4019, - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4023, - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4026; - wire [14 : 0] SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5637, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6169; - wire [12 : 0] NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d5996, - NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6303, - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4142, - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4435; - wire [11 : 0] IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2001, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2003, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2005, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2007, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2009, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2011, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2013, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2015, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2017, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2019, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2021, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2023, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2025, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2027, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2029, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2031, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2033, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2104, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2106, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2108, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2110, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2112, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2114, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2116, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2118, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2120, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2122, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2124, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2126, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2128, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2130, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2132, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2134, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2136, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5869, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5870, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5871, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5872, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5873, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5874, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5875, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5876, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5877, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5878, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5879, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5880, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5881, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5882, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5883, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5884, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5885, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5886, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5887, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5888, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5889, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5890, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5891, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5892, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5893, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5894, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5895, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5896, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5897, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5898, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5899, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5900, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5901, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5902, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5903, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6234, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6235, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6236, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6237, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6238, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6239, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6240, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6241, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6242, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6243, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6244, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6245, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6246, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6247, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6248, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6249, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6250, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6251, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6252, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6253, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6254, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6255, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6256, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6257, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6258, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6259, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6260, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6261, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6262, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6263, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6264, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6265, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6266, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6267, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6268, - imm12__h123061, - imm12__h123402, - imm12__h125051, - imm12__h125735, - imm12__h125953, - imm12__h126150, - imm12__h126490, - imm12__h128127, - imm12__h128483, - imm12__h131615, - imm12__h131956, - imm12__h133602, - imm12__h134286, - imm12__h134504, - imm12__h134701, - imm12__h135041, - imm12__h136678, - imm12__h137034, - offset__h123776, - offset__h132330; - wire [9 : 0] SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5636, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6168, - nzimm10__h125733, - nzimm10__h125951, - nzimm10__h134284, - nzimm10__h134502; - wire [8 : 0] SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5708, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6188, - offset__h124412, - offset__h128040, - offset__h132963, - offset__h136591; - wire [7 : 0] offset__h122904, - offset__h128417, - offset__h131523, - offset__h136968; - wire [6 : 0] SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5623, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6164, - offset__h123344, - offset__h131898; - wire [5 : 0] IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1232, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1248, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1281, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1799, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1815, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1848, - imm6__h125049, - imm6__h133600; - wire [4 : 0] IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1265, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d865, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d878, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1433, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1446, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1832, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5614, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5651, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6161, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6174, - offset_BITS_4_TO_0___h123333, - offset_BITS_4_TO_0___h123768, - offset_BITS_4_TO_0___h128762, - offset_BITS_4_TO_0___h131887, - offset_BITS_4_TO_0___h132322, - offset_BITS_4_TO_0___h137313, - rd__h123404, - rd__h131958, - rs1__h123403, - rs1__h131957; - wire [3 : 0] IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2048, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2050, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2052, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2054, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2056, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2058, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2151, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2153, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2155, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2157, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2159, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2161, - IF_NOT_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758__ETC___d5144, - IF_NOT_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758__ETC___d5145, - IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4649, - IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4651, - IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4653, - IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4655, - IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4657, - IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4659, - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5134, - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5135, - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5136, - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5137, - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5138, - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5139, - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5140, - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5141, - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5142, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6112, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6113, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6114, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6115, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6116, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6117, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6118, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6119, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6120, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6121, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6122, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6123, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6321, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6322, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6323, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6324, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6325, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6326, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6327, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6328, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6329, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6330, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6331, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6332, - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5143, - IF_f22f3_enqReq_lat_0_whas__14_THEN_IF_f22f3_e_ETC___d400, - IF_f32d_enqReq_lat_0_whas__46_THEN_IF_f32d_enq_ETC___d732, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d850, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1418; - wire [2 : 0] IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4042, - IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4047, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1989, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1991, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2092, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2094, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d5704, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d5705, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d5706, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d5707, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6184, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6185, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6186, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6187, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5605, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6158, - _theResult___fst__h122094, - j__h119769, - j__h122111, - n_x16s__h117514, - n_x16s__h119766, - y_avValue_fst__h122004, - y_avValue_fst__h122012, - y_avValue_fst__h122039, - y_avValue_snd_fst__h119828, - y_avValue_snd_fst__h119835; - wire [1 : 0] _theResult_____2__h19260, - next_deqP___1__h19579, - v__h15956, - v__h16239, - x__h119846, - x__h119862, - y__h119863; - wire IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4048, - IF_IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AN_ETC___d5465, - IF_IF_decode_768_BITS_99_TO_95_772_EQ_8_779_AN_ETC___d5160, - IF_IF_decode_768_BITS_99_TO_95_772_EQ_8_779_AN_ETC___d5459, - IF_IF_rg_pending_straddle_514_THEN_IF_SEL_ARR__ETC___d4011, - IF_IF_rg_pending_straddle_514_THEN_IF_SEL_ARR__ETC___d4031, - IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5446, - IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5468, - IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5475, - IF_NOT_decode_180_BIT_26_211_212_AND_NOT_decod_ETC___d5253, - IF_NOT_decode_768_BIT_26_799_800_AND_NOT_decod_ETC___d4841, - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5161, - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5444, - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5460, - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5466, - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5473, - IF_SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_ETC___d5474, - IF_SEL_ARR_instdata_data_0_686_BITS_195_TO_194_ETC___d5447, - IF_SEL_ARR_instdata_data_0_686_BITS_195_TO_194_ETC___d5476, - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5437, - IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5394, - IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5443, - IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5472, - IF_decode_768_BITS_99_TO_95_772_EQ_8_779_AND_d_ETC___d4982, - IF_f12f2_deqReq_dummy2_2_read__2_AND_IF_f12f2__ETC___d80, - IF_f12f2_deqReq_lat_1_whas__3_THEN_f12f2_deqRe_ETC___d49, - IF_f12f2_enqReq_lat_1_whas__4_THEN_f12f2_enqRe_ETC___d23, - IF_f22f3_deqReq_dummy2_2_read__19_AND_IF_f22f3_ETC___d332, - IF_f22f3_deqReq_lat_1_whas__94_THEN_f22f3_deqR_ETC___d300, - IF_f22f3_enqReq_lat_1_whas__11_THEN_NOT_f22f3__ETC___d127, - IF_f22f3_enqReq_lat_1_whas__11_THEN_f22f3_enqR_ETC___d120, - IF_f32d_deqReq_dummy2_2_read__55_AND_IF_f32d_d_ETC___d663, - IF_f32d_deqReq_lat_1_whas__26_THEN_f32d_deqReq_ETC___d632, - IF_f32d_enqReq_lat_1_whas__43_THEN_NOT_f32d_en_ETC___d459, - IF_f32d_enqReq_lat_1_whas__43_THEN_f32d_enqReq_ETC___d452, - IF_instdata_deqP_lat_0_whas__77_THEN_instdata__ETC___d780, - IF_out_fifo_dequeueFifo_lat_1_whas__14_THEN_ou_ETC___d820, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1222, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1238, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1255, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1271, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1289, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d830, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1398, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1789, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1805, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1822, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1838, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1856, - IF_out_fifo_enqueueFifo_lat_1_whas__04_THEN_ou_ETC___d810, - IF_out_fifo_willDequeue_0_lat_0_whas__959_THEN_ETC___d1962, - IF_out_fifo_willDequeue_1_lat_0_whas__966_THEN_ETC___d1969, - IF_perfReqQ_enqReq_lat_1_whas__977_THEN_perfRe_ETC___d2986, - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3773, - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3790, - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3808, - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3827, - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3847, - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3868, - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3890, - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3896, - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3907, - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3913, - NOT_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_47_ETC___d3757, - NOT_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_47_ETC___d3874, - NOT_SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_5_ETC___d3742, - NOT_SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_5_ETC___d3853, - NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_19_ETC___d5188, - NOT_decode_180_BITS_25_TO_21_213_EQ_decode_180_ETC___d5250, - NOT_decode_180_BIT_27_210_220_OR_decode_180_BI_ETC___d5227, - NOT_decode_180_BIT_7_192_203_OR_decode_180_BIT_ETC___d5219, - NOT_decode_180_BIT_7_192_203_OR_decode_180_BIT_ETC___d5392, - NOT_decode_768_BITS_25_TO_21_801_EQ_decode_768_ETC___d4838, - NOT_decode_768_BIT_0_769_770_AND_IF_decode_768_ETC___d5439, - NOT_decode_768_BIT_27_798_808_OR_decode_768_BI_ETC___d4815, - NOT_decode_768_BIT_7_780_791_OR_decode_768_BIT_ETC___d4807, - NOT_decode_768_BIT_7_780_791_OR_decode_768_BIT_ETC___d4980, - NOT_f12f2_clearReq_dummy2_1_read__8_9_OR_IF_f1_ETC___d63, - NOT_f12f2_enqReq_dummy2_2_read__4_4_OR_IF_f12f_ETC___d98, - NOT_f22f3_clearReq_dummy2_1_read__09_27_OR_IF__ETC___d331, - NOT_f22f3_enqReq_dummy2_2_read__11_45_OR_IF_f2_ETC___d349, - NOT_f32d_clearReq_dummy2_1_read__41_42_OR_IF_f_ETC___d646, - NOT_f32d_enqReq_dummy2_2_read__47_77_OR_IF_f32_ETC___d681, - NOT_instdata_full_dummy2_1_read__505_506_OR_NO_ETC___d3536, - NOT_perfReqQ_clearReq_dummy2_1_read__021_022_O_ETC___d3026, - NOT_perfReqQ_enqReq_dummy2_2_read__027_042_OR__ETC___d3047, - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3963, - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3981, - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d5434, - SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523, - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502, - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3569, - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3715, - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3814, - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d4646, - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684, - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d5167, - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d5237, - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701, - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165, - SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4723, - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4708, - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4735, - _dfoo1, - _dfoo2, - _dfoo3, - _dfoo5, - _dfoo523, - _theResult_____2__h28906, - _theResult_____2__h7993, - b__h119858, - b__h119870, - decode_180_BITS_99_TO_95_184_EQ_8_191_AND_deco_ETC___d5232, - decode_180_BIT_7_192_AND_NOT_decode_180_BIT_6__ETC___d5228, - decode_768_BITS_99_TO_95_772_EQ_8_779_AND_deco_ETC___d4820, - decode_768_BIT_7_780_AND_NOT_decode_768_BIT_6__ETC___d4816, - f12f2_enqReq_dummy2_2_read__4_AND_IF_f12f2_enq_ETC___d90, - f22f3_empty_47_OR_NOT_SEL_ARR_NOT_f22f3_data_0_ETC___d3495, - f22f3_empty_47_OR_NOT_SEL_ARR_NOT_f22f3_data_0_ETC___d3539, - f22f3_enqReq_dummy2_2_read__11_AND_IF_f22f3_en_ETC___d342, - f32d_enqReq_dummy2_2_read__47_AND_IF_f32d_enqR_ETC___d673, - n__read__h142595, - next_deqP___1__h29225, - next_deqP___1__h8312, - next_deqP__h142575, - next_enqP__h139674, - perfReqQ_enqReq_dummy2_2_read__027_AND_IF_perf_ETC___d3039, - rg_pending_straddle_514_AND_NOT_SEL_ARR_f22f3__ETC___d3728, - rg_pending_straddle_514_AND_NOT_SEL_ARR_f22f3__ETC___d3833, - upd__h139977, - upd__h32146, - upd__h38127, - upd__h38154, - upd__h39683, - upd__h39710, - v__h27080, - v__h27363, - v__h7269, - v__h7552, - x__h115826, - x__h16438, - x__h27482, - x__h54856, - x__h63120, - x__h64600, - x__h72803; + reg [128 : 0] CASE_decode_047_BITS_171_TO_167_9_IF_NOT_decod_ETC__q21, + CASE_decode_558_BITS_171_TO_167_9_IF_NOT_decod_ETC__q14, + CASE_f12f2_deqP_0_f12f2_data_0_BITS_134_TO_6_1_ETC__q382, + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q379, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5390, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6314, + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_194_ETC___d6727, + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_389_ETC___d6710, + SEL_ARR_f22f3_data_0_920_BITS_205_TO_77_682_f2_ETC___d6687, + SEL_ARR_instdata_data_0_987_BITS_389_TO_261_42_ETC___d7425, + SEL_ARR_rg_pending_decode_631_BITS_389_TO_261__ETC___d6708, + SEL_ARR_rg_pending_decode_631_BITS_584_TO_456__ETC___d6636, + in_ppc__h182302, + out_pc__h112351, + pc_start__h114675, + x__h171664, + x__h195362, + x__h195426, + x__h207703, + x__h207723, + y_avValue_fst_pred_next_pc__h165564; + reg [63 : 0] CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q324, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q332, + out___1_tval__h146073, + tval___2__h171521, + y_avValue_snd_fst__h113417; + reg [31 : 0] CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q312, + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q376, + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q377, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q316, + SEL_ARR_instdata_data_0_987_BITS_226_TO_195_55_ETC___d7556, + SEL_ARR_instdata_data_0_987_BITS_31_TO_0_038_i_ETC___d7041, + SEL_ARR_rg_pending_decode_631_BITS_226_TO_195__ETC___d6720, + SEL_ARR_rg_pending_decode_631_BITS_258_TO_227__ETC___d6716, + SEL_ARR_rg_pending_decode_631_BITS_421_TO_390__ETC___d6657, + SEL_ARR_rg_pending_decode_631_BITS_453_TO_422__ETC___d6650, + x__h152277, + x__h152323, + x__h159975, + x__h159980, + x__h161103, + x__h161115, + x__h165114, + x__h165122, + x__h165191, + x__h165202, + x__h180841, + x__h191306, + x__h195484, + x__h206149, + x__h207737, + x__h217664; + reg [29 : 0] CASE_decode_047_BITS_166_TO_164_0_decode_047_B_ETC__q17, + CASE_decode_558_BITS_166_TO_164_0_decode_558_B_ETC__q10; + reg [15 : 0] CASE_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_ETC__q375, + CASE_y_avValue_fst17191_0_IF_NOT_f22f3_empty_1_ETC__q372, + CASE_y_avValue_fst26140_0_IF_NOT_f22f3_empty_1_ETC__q373, + CASE_y_avValue_fst34851_0_IF_NOT_f22f3_empty_1_ETC__q374, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267; + reg [11 : 0] CASE_decode_047_BITS_78_TO_67_1_decode_047_BIT_ETC__q19, + CASE_decode_558_BITS_78_TO_67_1_decode_558_BIT_ETC__q12, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q351, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q355; + reg [10 : 0] CASE_decode_047_BITS_136_TO_135_0_decode_047_B_ETC__q18, + CASE_decode_558_BITS_136_TO_135_0_decode_558_B_ETC__q11; + reg [9 : 0] CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q352, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q356; + reg [5 : 0] x__h200265, x__h200270, x__h211978, x__h211979; + reg [4 : 0] CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385, + CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388, + CASE_decode_047_BITS_65_TO_61_0_decode_047_BIT_ETC__q20, + CASE_decode_558_BITS_65_TO_61_0_decode_558_BIT_ETC__q13, + CASE_iTlbto_proc_response_get_BITS_4_TO_0_0_i_ETC__q1, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q130, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q133, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q31, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q319, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q322, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q340, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q349, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q135, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q138, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q327, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q330, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q348, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q350, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q72; + reg [3 : 0] CASE_IF_decode_047_BITS_134_TO_131_176_EQ_6_18_ETC__q6, + CASE_IF_decode_558_BITS_134_TO_131_687_EQ_6_69_ETC__q8, + CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383, + CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384, + CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386, + CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q149, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q35, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q359, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q147, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q360, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q76, + IF_decode_047_BITS_134_TO_131_176_EQ_6_188_OR__ETC___d7197, + IF_decode_558_BITS_134_TO_131_687_EQ_6_699_OR__ETC___d7708, + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114, + IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143, + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281, + IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310, + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334, + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363, + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4929, + out_main_epoch__h112357, + out_main_epoch__h177345; + reg [2 : 0] CASE_IF_decode_047_BITS_130_TO_128_219_EQ_2_22_ETC__q5, + CASE_IF_decode_558_BITS_130_TO_128_730_EQ_2_73_ETC__q7, + CASE_decode_047_BITS_140_TO_138_0_decode_047_B_ETC__q16, + CASE_decode_558_BITS_140_TO_138_0_decode_558_B_ETC__q9, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q115, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q116, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q336, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q338, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q113, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q114, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q344, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q346, + IF_decode_047_BITS_130_TO_128_219_EQ_2_223_OR__ETC___d7226, + IF_decode_558_BITS_130_TO_128_730_EQ_2_734_OR__ETC___d7737, + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1233, + IF_out_fifo_enqueueElement_0_rl_07_BITS_231_TO_ETC___d1244, + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2400, + IF_out_fifo_enqueueElement_1_rl_075_BITS_231_T_ETC___d2411, + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425, + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254, + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436, + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266; + reg [1 : 0] CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q120, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q65, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q66, + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q378, + CASE_pending_spaces_ext45988_0_IF_NOT_f22f3_em_ETC__q380, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q118, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q63, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q64, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6322, + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_260_ETC___d6714, + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_455_ETC___d6645, + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_65__ETC___d6731, + SEL_ARR_f12f2_data_0_810_BITS_266_TO_265_811_f_ETC___d4815, + SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009, + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8400, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9329, + SEL_ARR_rg_pending_decode_631_BITS_260_TO_259__ETC___d6712, + SEL_ARR_rg_pending_decode_631_BITS_455_TO_454__ETC___d6643, + nbSupX2In__h113561; + reg CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5127, + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5140, + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5142, + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5124, + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5139, + CASE_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_2_ETC___d5040, + CASE_decode_047_BITS_171_TO_167_9_NOT_decode_0_ETC__q22, + CASE_decode_558_BITS_171_TO_167_9_NOT_decode_5_ETC__q15, + CASE_f12f2_deqP_0_NOT_f12f2_data_0_BIT_135_1_N_ETC__q381, + CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q304, + CASE_f12f2_deqP_0_f12f2_data_0_BIT_5_1_f12f2_d_ETC__q303, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q77, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q78, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q79, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q80, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q81, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q82, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q83, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q84, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q85, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q86, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q87, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q88, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q89, + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q90, + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q26, + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q27, + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q28, + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q29, + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q30, + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q129, + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q131, + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q132, + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q309, + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q310, + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q311, + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q317, + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q318, + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q320, + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q321, + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q323, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q100, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q112, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q119, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q123, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q124, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q127, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q128, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q141, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q142, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q145, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q146, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q150, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q151, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q152, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q157, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q158, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q161, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q162, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q165, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q166, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q169, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q170, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q173, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q174, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q177, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q178, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q181, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q182, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q183, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q184, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q185, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q186, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q187, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q188, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q189, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q190, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q191, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q192, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q193, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q194, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q195, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q196, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q197, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q198, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q199, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q200, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q201, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q202, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q203, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q204, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q205, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q206, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q207, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q208, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q209, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q210, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q211, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q212, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q213, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q214, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q215, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q216, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q217, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q218, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q219, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q220, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q221, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q222, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q223, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q224, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q225, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q226, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q227, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q228, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q23, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q24, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q25, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q275, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q276, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q277, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q278, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q279, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q280, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q281, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q282, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q283, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q284, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q285, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q286, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q287, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q288, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q305, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q306, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q32, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q33, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q333, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q334, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q335, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q337, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q339, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q34, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q353, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q354, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q41, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q42, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q45, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q46, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q49, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q50, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q53, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q54, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q57, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q58, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q61, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q62, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q91, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q92, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q93, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q94, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q95, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q96, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q97, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q98, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q99, + CASE_out_fifo_enqueueFifo_rl_0_out_fifo_intern_ETC__q4, + CASE_pending_spaces45986_0_1_1_NOT_f22f3_empty_ETC__q367, + CASE_pending_spaces_ext45988_0_1_1_1_2_1_3_NOT_ETC__q370, + CASE_pending_spaces_ext45988_0_1_1_1_2_1_3_NOT_ETC__q371, + CASE_pending_spaces_ext45988_0_1_1_1_2_NOT_f22_ETC__q368, + CASE_pending_spaces_ext45988_0_1_1_1_2_NOT_f22_ETC__q369, + CASE_pending_spaces_ext45988_0_1_1_NOT_SEL_ARR_ETC__q365, + CASE_pending_spaces_ext45988_0_1_1_NOT_SEL_ARR_ETC__q366, + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q361, + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q362, + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q363, + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q364, + CASE_x0535_0_out_fifo_internalFifos_0FULL_N_1_ETC__q3, + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q67, + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q68, + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q69, + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q70, + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q71, + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q134, + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q136, + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q137, + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q313, + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q314, + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q315, + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q325, + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q326, + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q328, + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q329, + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q331, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q101, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q102, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q103, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q104, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q105, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q106, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q107, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q108, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q109, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q110, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q111, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q117, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q121, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q122, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q125, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q126, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q139, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q140, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q143, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q144, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q148, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q153, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q154, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q155, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q156, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q159, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q160, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q163, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q164, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q167, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q168, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q171, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q172, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q175, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q176, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q179, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q180, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q229, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q230, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q231, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q232, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q233, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q234, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q235, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q236, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q237, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q238, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q239, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q240, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q241, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q242, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q243, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q244, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q245, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q246, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q247, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q248, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q249, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q250, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q251, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q252, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q253, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q254, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q255, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q256, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q257, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q258, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q259, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q260, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q261, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q262, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q263, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q264, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q265, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q266, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q267, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q268, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q269, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q270, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q271, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q272, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q273, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q274, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q289, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q290, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q291, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q292, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q293, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q294, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q295, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q296, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q297, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q298, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q299, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q300, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q301, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q302, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q307, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q308, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q341, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q342, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q343, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q345, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q347, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q357, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q358, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q36, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q37, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q38, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q39, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q40, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q43, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q44, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q47, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q48, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q51, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q52, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q55, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q56, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q59, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q60, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q73, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q74, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q75, + SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303, + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977, + SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037, + SEL_ARR_NOT_f32d_data_0_979_BIT_75_991_992_NOT_ETC___d7996, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8396, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8417, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8452, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8461, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8469, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8491, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8508, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8524, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8541, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8557, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8573, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8589, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8605, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9328, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9331, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9334, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9336, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9337, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9344, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9346, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9347, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9349, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9350, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9351, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9352, + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9353, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6773, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6783, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6793, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6803, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6813, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6823, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6833, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6843, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6853, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6863, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6873, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6883, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6893, + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6903, + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4937, + SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4946, + SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003, + SEL_ARR_f32d_data_0_979_BIT_334_011_f32d_data__ETC___d7014, + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6997, + SEL_ARR_f32d_data_0_979_BIT_75_991_f32d_data_1_ETC___d7998, + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680, + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700, + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725, + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8209, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8217, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8372, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8441, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9289, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9291, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9324, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9332; + wire [332 : 0] SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9243, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9606; + wire [257 : 0] IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d8028, + IF_IF_decode_558_BITS_171_TO_167_562_EQ_8_568__ETC___d8029, + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d8030, + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_75_991_992__ETC___d8021, + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_75_991_992__ETC___d8027; + wire [206 : 0] IF_f22f3_enqReq_lat_1_whas__77_THEN_NOT_f22f3__ETC___d509; + wire [204 : 0] IF_IF_f32d_enqReq_lat_1_whas__20_THEN_NOT_f32d_ETC___d842; + wire [194 : 0] SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6307; + wire [171 : 0] decode___d7047, decode___d7558; + wire [145 : 0] IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6969, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6966, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6975, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6973, + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d6965, + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d6968, + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d6971, + IF_ehr_pending_straddle_lat_1_whas__1_THEN_ehr_ETC___d40; + wire [143 : 0] SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9076, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9541, + decode_047_BITS_171_TO_167_051_CONCAT_IF_decod_ETC___d7400, + decode_558_BITS_171_TO_167_562_CONCAT_IF_decod_ETC___d7911; + wire [129 : 0] IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4786, + decodeBrPred___d7404, + decodeBrPred___d7915; + wire [128 : 0] IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5345, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5336, + IF_IF_decode_558_BITS_171_TO_167_562_EQ_8_568__ETC___d7979, + IF_NOT_IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15__ETC___d4765, + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5335, + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5344, + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5353, + IF_NOT_decode_047_BIT_7_058_071_OR_decode_047__ETC___d7419, + IF_NOT_decode_558_BIT_7_569_582_OR_decode_558__ETC___d7930, + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4767, + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4768, + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7980, + IF_decode_047_BIT_7_058_AND_NOT_decode_047_BIT_ETC___d7417, + IF_decode_558_BIT_7_569_AND_NOT_decode_558_BIT_ETC___d7928, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d919, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d924, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2087, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2092, + IF_pc_reg_lat_1_whas_THEN_pc_reg_lat_1_wget_EL_ETC___d11, + IF_pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NO_ETC___d4764, + _theResult___snd_snd_fst__h110304, + a__h144061, + cap__h109578, + cap__h110263, + cap__h145069, + decode_pred_next_pc__h177047, + decode_pred_next_pc__h187627, + def__h108385, + def__h161167, + in_ppc__h171466, + last_x16_pc__h177080, + last_x16_pc__h187660, + nextPc__h193173, + pc__h149815, + pc__h149819, + pc__h150157, + pc__h150161, + pc__h150503, + pc__h150507, + pc__h159846, + pc__h159850, + pred_next_pc__h143735, + prev_PC__h109626, + prev_PC__h110311, + train_nextPc__h194872, + upd__h1026, + upd__h972, + upd__h999, + value__h118124, + value__h127057, + value__h135811, + x1_avValue_fst_pc__h146083, + x1_avValue_fst_ppc__h177356, + x1_avValue_fst_ppc__h187823, + x1_avValue_fst_pred_next_pc__h146084, + x1_avValue_fst_pred_next_pc__h146091, + x__h165562, + x__h165577, + x__h177367, + x__h187834, + x__h19157, + x__h19215, + x__h194838, + x__h225902, + x_snd_pc__h11415, + x_snd_pc__h6025, + y_avValue_fst_pc__h146077; + wire [76 : 0] iTlb_to_proc_response_get_801_BIT_5_802_OR_NOT_ETC___d4916; + wire [69 : 0] IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d3383, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3530, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9240, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9603; + wire [68 : 0] IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6934; + wire [63 : 0] IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5351, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5342, + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5333, + _theResult___snd_snd_snd_fst__h117676, + _theResult___snd_snd_snd_fst__h126566, + _theResult___snd_snd_snd_fst__h135277, + _theResult___snd_snd_snd_fst__h144010, + address__h109631, + address__h110316, + address__h111404, + address__h118137, + address__h145071, + address__h161170, + address__h172257, + address__h182904, + address__h193189, + address__h193365, + address__h193564, + address__h194902, + address__h225906, + next_pc___1__h117347, + next_pc___1__h126283, + next_pc___1__h134994, + next_pc___1__h146036, + out_tval__h112353, + tval__h112495, + x1_avValue_fst_tval__h146087, + x__h111368, + y_avValue_fst_tval__h146080, + y_avValue_snd_fst__h117557, + y_avValue_snd_snd_snd_fst__h117651, + y_avValue_snd_snd_snd_fst__h117653, + y_avValue_snd_snd_snd_fst__h126541, + y_avValue_snd_snd_snd_fst__h126543, + y_avValue_snd_snd_snd_fst__h135252, + y_avValue_snd_snd_snd_fst__h135254, + y_avValue_snd_snd_snd_fst__h143853, + y_avValue_snd_snd_snd_fst__h143855, + y_avValue_snd_snd_snd_snd_fst__h117572, + y_avValue_snd_snd_snd_snd_fst__h117603, + y_avValue_snd_snd_snd_snd_fst__h117605, + y_avValue_snd_snd_snd_snd_fst__h126508, + y_avValue_snd_snd_snd_snd_fst__h135219, + y_avValue_snd_snd_snd_snd_fst__h143793; + wire [51 : 0] IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d3358, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3505, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9074, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9539; + wire [45 : 0] IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1500, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2665, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8759, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9414; + wire [43 : 0] SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8758, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9413; + wire [41 : 0] SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8757, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9412; + wire [39 : 0] SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8756, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9411; + wire [37 : 0] SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8755, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9410; + wire [35 : 0] SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8754, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9409; + wire [33 : 0] SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8753, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9408; + wire [31 : 0] IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5686, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5688, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5690, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5692, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5695, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5697, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5699, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5702, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5705, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5707, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5709, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5710, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5712, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5714, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5716, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5718, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5720, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5975, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5977, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5979, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5981, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5984, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5986, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5988, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5991, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5994, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5996, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5998, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5999, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6001, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6003, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6005, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6007, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6009, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6264, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6266, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6268, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6270, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6273, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6275, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6277, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6280, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6283, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6285, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6287, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6288, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6290, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6292, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6294, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6296, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6298, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6586, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6588, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6590, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6592, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6595, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6597, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6599, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6602, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6605, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6607, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6609, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6610, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6612, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6614, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6616, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6618, + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6620, + IF_SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_ETC___d5215, + IF_SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_ETC___d5228, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1890, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d939, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2107, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3055, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8752, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9407, + _theResult___snd_fst__h117672, + _theResult___snd_fst__h126562, + _theResult___snd_fst__h135273, + _theResult___snd_fst__h144006, + inst__h149818, + inst__h149822, + inst__h150160, + inst__h150164, + inst__h150506, + inst__h150510, + inst__h159849, + inst__h159853, + instr__h118639, + instr__h118786, + instr__h118980, + instr__h119177, + instr__h119408, + instr__h119864, + instr__h119982, + instr__h120047, + instr__h120366, + instr__h120707, + instr__h120896, + instr__h121028, + instr__h121259, + instr__h121519, + instr__h121692, + instr__h121863, + instr__h122053, + instr__h122243, + instr__h122361, + instr__h122542, + instr__h122663, + instr__h122759, + instr__h122896, + instr__h123033, + instr__h123170, + instr__h123309, + instr__h123448, + instr__h123608, + instr__h123705, + instr__h123860, + instr__h124061, + instr__h124214, + instr__h124473, + instr__h125288, + instr__h125464, + instr__h125665, + instr__h125818, + instr__h127439, + instr__h127586, + instr__h127780, + instr__h127977, + instr__h128207, + instr__h128661, + instr__h128779, + instr__h128844, + instr__h129163, + instr__h129504, + instr__h129693, + instr__h129825, + instr__h130056, + instr__h130316, + instr__h130489, + instr__h130660, + instr__h130850, + instr__h131040, + instr__h131158, + instr__h131339, + instr__h131460, + instr__h131556, + instr__h131693, + instr__h131830, + instr__h131967, + instr__h132106, + instr__h132245, + instr__h132405, + instr__h132502, + instr__h132657, + instr__h132858, + instr__h133011, + instr__h133215, + instr__h134029, + instr__h134205, + instr__h134406, + instr__h134559, + instr__h136193, + instr__h136340, + instr__h136534, + instr__h136731, + instr__h136961, + instr__h137415, + instr__h137533, + instr__h137598, + instr__h137917, + instr__h138258, + instr__h138447, + instr__h138579, + instr__h138810, + instr__h139070, + instr__h139243, + instr__h139414, + instr__h139604, + instr__h139794, + instr__h139912, + instr__h140093, + instr__h140214, + instr__h140310, + instr__h140447, + instr__h140584, + instr__h140721, + instr__h140860, + instr__h140999, + instr__h141159, + instr__h141256, + instr__h141411, + instr__h141612, + instr__h141765, + instr__h141969, + instr__h142783, + instr__h142959, + instr__h143160, + instr__h143313, + instr__h152465, + instr__h152612, + instr__h152806, + instr__h153003, + instr__h153233, + instr__h153687, + instr__h153805, + instr__h153870, + instr__h154189, + instr__h154530, + instr__h154719, + instr__h154851, + instr__h155082, + instr__h155342, + instr__h155515, + instr__h155686, + instr__h155876, + instr__h156066, + instr__h156184, + instr__h156365, + instr__h156486, + instr__h156582, + instr__h156719, + instr__h156856, + instr__h156993, + instr__h157132, + instr__h157271, + instr__h157431, + instr__h157528, + instr__h157683, + instr__h157884, + instr__h158037, + instr__h158241, + instr__h159055, + instr__h159231, + instr__h159432, + instr__h159585, + n_inst__h118136, + n_inst__h127069, + n_inst__h135823, + n_inst__h150502, + n_orig_inst__h118135, + n_orig_inst__h127068, + n_orig_inst__h135822, + n_orig_inst__h150501, + orig_inst___1__h117345, + orig_inst___1__h126281, + orig_inst___1__h134992, + orig_inst___1__h146034, + orig_inst__h149817, + orig_inst__h149821, + orig_inst__h150159, + orig_inst__h150163, + orig_inst__h150505, + orig_inst__h150509, + orig_inst__h159848, + orig_inst__h159852, + y_avValue_snd_fst__h117639, + y_avValue_snd_fst__h117641, + y_avValue_snd_fst__h126529, + y_avValue_snd_fst__h126531, + y_avValue_snd_fst__h135240, + y_avValue_snd_fst__h135242, + y_avValue_snd_fst__h143841, + y_avValue_snd_fst__h143843, + y_avValue_snd_snd_fst__h117562, + y_avValue_snd_snd_fst__h117591, + y_avValue_snd_snd_fst__h117593, + y_avValue_snd_snd_fst__h117645, + y_avValue_snd_snd_fst__h126498, + y_avValue_snd_snd_fst__h126535, + y_avValue_snd_snd_fst__h135209, + y_avValue_snd_snd_fst__h135246, + y_avValue_snd_snd_fst__h143783, + y_avValue_snd_snd_fst__h143847, + y_avValue_snd_snd_snd_fst__h117567, + y_avValue_snd_snd_snd_fst__h117599, + y_avValue_snd_snd_snd_fst__h126503, + y_avValue_snd_snd_snd_fst__h135214, + y_avValue_snd_snd_snd_fst__h143788; + wire [29 : 0] IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3263, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3264, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3266, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3267, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3410, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3411, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3413, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3414, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8293, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8294, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8295, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8296, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8297, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9315, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9316, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9317, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9318, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9319, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8751, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9406; + wire [27 : 0] SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8750, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9405; + wire [26 : 0] NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9155, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9570; + wire [25 : 0] SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8749, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9404; + wire [23 : 0] IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7438, + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7941, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d934, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2102, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8090, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8220, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8748, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9253, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9294, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9403; + wire [21 : 0] SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8747, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9402; + wire [20 : 0] SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5497, + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5786, + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6075, + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6397; + wire [19 : 0] imm20__h120761, + imm20__h129558, + imm20__h138312, + imm20__h154584; + wire [18 : 0] SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8219, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8746, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9293, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9401; + wire [14 : 0] SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8201, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9287; + wire [12 : 0] NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9154, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9569, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8192, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8745, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9284, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9400, + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5522, + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5811, + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6100, + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6422; + wire [11 : 0] IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3299, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3301, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3303, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3305, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3307, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3309, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3311, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3313, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3315, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3317, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3319, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3321, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3323, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3325, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3327, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3329, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3331, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3333, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3335, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3337, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3339, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3341, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3446, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3448, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3450, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3452, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3454, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3456, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3458, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3460, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3462, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3464, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3466, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3468, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3470, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3472, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3474, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3476, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3478, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3480, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3482, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3484, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3486, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3488, + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4751, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8954, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8955, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8956, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8957, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8958, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8959, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8960, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8961, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8962, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8963, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8964, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8965, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8966, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8967, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8968, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8969, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8970, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8971, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8972, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8973, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8974, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8975, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8976, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8977, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8978, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8979, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8980, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8981, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8982, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8983, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8984, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8985, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8986, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8987, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8988, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8989, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8990, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8991, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8992, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8993, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8994, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8995, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8996, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8997, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8998, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9464, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9465, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9466, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9467, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9468, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9469, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9470, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9471, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9472, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9473, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9474, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9475, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9476, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9477, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9478, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9479, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9480, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9481, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9482, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9483, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9484, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9485, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9486, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9487, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9488, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9489, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9490, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9491, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9492, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9493, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9494, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9495, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9496, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9497, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9498, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9499, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9500, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9501, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9502, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9503, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9504, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9505, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9506, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9507, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9508, + imm12__h118640, + imm12__h118981, + imm12__h120630, + imm12__h121314, + imm12__h121532, + imm12__h121729, + imm12__h122069, + imm12__h123706, + imm12__h124062, + imm12__h127440, + imm12__h127781, + imm12__h129427, + imm12__h130111, + imm12__h130329, + imm12__h130526, + imm12__h130866, + imm12__h132503, + imm12__h132859, + imm12__h136194, + imm12__h136535, + imm12__h138181, + imm12__h138865, + imm12__h139083, + imm12__h139280, + imm12__h139620, + imm12__h141257, + imm12__h141613, + imm12__h152466, + imm12__h152807, + imm12__h154453, + imm12__h155137, + imm12__h155355, + imm12__h155552, + imm12__h155892, + imm12__h157529, + imm12__h157885, + inc__h111403, + inc__h172256, + inc__h182903, + inc__h193188, + inc__h193364, + inc__h225905, + offset__h119355, + offset__h128155, + offset__h136909, + offset__h153181, + x11563_PLUS_1__q2, + x__h111563; + wire [10 : 0] IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3296, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3443, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8619, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8620, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9367, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9368, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8183, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9281; + wire [9 : 0] nzimm10__h121312, + nzimm10__h121530, + nzimm10__h130109, + nzimm10__h130327, + nzimm10__h138863, + nzimm10__h139081, + nzimm10__h155135, + nzimm10__h155353; + wire [8 : 0] IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3290, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3292, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3437, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3439, + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8613, + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8615, + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9361, + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9363, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8617, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9365, + IF_decode_047_BITS_134_TO_131_176_EQ_0_177_OR__ETC___d7270, + IF_decode_047_BITS_134_TO_131_176_EQ_1_178_OR__ETC___d7269, + IF_decode_047_BITS_134_TO_131_176_EQ_2_180_OR__ETC___d7268, + IF_decode_558_BITS_134_TO_131_687_EQ_0_688_OR__ETC___d7781, + IF_decode_558_BITS_134_TO_131_687_EQ_1_689_OR__ETC___d7780, + IF_decode_558_BITS_134_TO_131_687_EQ_2_691_OR__ETC___d7779, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8174, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8291, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9278, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9313, + _2_CONCAT_IF_IF_out_fifo_enqueueElement_0_lat_0_ETC___d3279, + _2_CONCAT_IF_IF_out_fifo_enqueueElement_1_lat_0_ETC___d3426, + _2_CONCAT_IF_SEL_ARR_out_fifo_internalFifos_0_f_ETC___d8475, + _2_CONCAT_IF_SEL_ARR_out_fifo_internalFifos_0_f_ETC___d9343, + offset__h119991, + offset__h123619, + offset__h128788, + offset__h132416, + offset__h137542, + offset__h141170, + offset__h153814, + offset__h157442; + wire [7 : 0] offset__h118483, + offset__h123996, + offset__h127348, + offset__h132793, + offset__h136102, + offset__h141547, + offset__h152374, + offset__h157819; + wire [6 : 0] NOT_iTlb_to_proc_response_get_801_BIT_5_802_80_ETC___d4915, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8165, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9275, + offset__h118923, + offset__h127723, + offset__h136477, + offset__h152749; + wire [5 : 0] IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1905, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1921, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1954, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3070, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3086, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3119, + imm6__h120628, + imm6__h129425, + imm6__h138179, + imm6__h154451; + wire [4 : 0] DONTCARE_CONCAT_SEL_ARR_out_fifo_internalFifos_ETC___d8377, + DONTCARE_CONCAT_SEL_ARR_out_fifo_internalFifos_ETC___d9326, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6907, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6908, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6909, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6910, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6911, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6912, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6913, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6914, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6915, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6916, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6917, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6918, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6919, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6920, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3277, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3346, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3348, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3350, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3352, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3370, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3372, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3374, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3376, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3378, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3380, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3424, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3493, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3495, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3497, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3499, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3517, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3519, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3521, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3523, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3525, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3527, + IF_NOT_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032__ETC___d7532, + IF_NOT_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032__ETC___d7533, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6698, + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7531, + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8473, + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9341, + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7521, + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7522, + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7523, + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7524, + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7525, + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7526, + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7527, + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7528, + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7529, + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7530, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9050, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9051, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9052, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9053, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9054, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9055, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9056, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9057, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9058, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9222, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9223, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9224, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9225, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9226, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9227, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9228, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9229, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9230, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9231, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9232, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9233, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9234, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9523, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9524, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9525, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9526, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9527, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9528, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9529, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9530, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9531, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9588, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9589, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9590, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9591, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9592, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9593, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9594, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9595, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9596, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9597, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9598, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9599, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9600, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1938, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d944, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d957, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2112, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2125, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3103, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8156, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8234, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9272, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9299, + offset_BITS_4_TO_0___h118912, + offset_BITS_4_TO_0___h119347, + offset_BITS_4_TO_0___h124341, + offset_BITS_4_TO_0___h127712, + offset_BITS_4_TO_0___h128147, + offset_BITS_4_TO_0___h133138, + offset_BITS_4_TO_0___h136466, + offset_BITS_4_TO_0___h136901, + offset_BITS_4_TO_0___h141892, + offset_BITS_4_TO_0___h152738, + offset_BITS_4_TO_0___h153173, + offset_BITS_4_TO_0___h158164, + rd__h118983, + rd__h127783, + rd__h136537, + rd__h152809, + rs1__h118982, + rs1__h127782, + rs1__h136536, + rs1__h152808; + wire [3 : 0] IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3284, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3286, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3431, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3433, + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8608, + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8610, + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9356, + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9358, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d929, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2097, + x1_avValue_fst_main_epoch__h146089, + y_avValue_fst_main_epoch__h146082; + wire [2 : 0] IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5265, + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5270, + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5369, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5254, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5367, + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5243, + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5365, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3258, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3260, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3405, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3407, + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d8287, + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d8288, + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d8289, + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d8290, + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d9309, + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d9310, + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d9311, + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d9312, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8147, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9269, + _0_CONCAT_SEL_ARR_f22f3_data_0_920_BITS_337_TO__ETC___d5193, + _theResult___fst__h117329, + _theResult___fst__h126265, + _theResult___fst__h134976, + j__h114680, + j__h117346, + j__h126282, + j__h134993, + n_items__h145984, + n_x16s__h114667, + n_x16s__h114677, + pending_spaces_ext__h145988, + x__h163892, + x__h165559, + y_avValue_fst__h117191, + y_avValue_fst__h117202, + y_avValue_fst__h117230, + y_avValue_fst__h117264, + y_avValue_fst__h126140, + y_avValue_fst__h126151, + y_avValue_fst__h126200, + y_avValue_fst__h134851, + y_avValue_fst__h134862, + y_avValue_fst__h134911, + y_avValue_snd_snd_fst__h146015, + y_avValue_snd_snd_fst__h146024; + wire [1 : 0] IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d5403, + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5398, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5393, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d6317, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6319, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5395, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5400, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5405, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6320, + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4772, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1189, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2356, + _theResult_____2__h14823, + next_deqP___1__h15012, + pending_n_items__h113790, + pending_spaces__h145986, + v__h10967, + v__h11118, + x__h111739, + x__h111757, + x__h11317, + x__h114796, + x__h114812, + x__h5939, + y__h111758, + y__h114813, + y_avValue_snd__h113781, + y_avValue_snd__h168590, + y_avValue_snd_fst__h165552; + wire CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5108, + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5110, + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5112, + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5144, + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5145, + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5147, + IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d5287, + IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d5322, + IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d6674, + IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d6960, + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5266, + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5271, + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5284, + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5316, + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5319, + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6671, + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6957, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5281, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5311, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5314, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6668, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6954, + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244, + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249, + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5309, + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d6665, + IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d7548, + IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d7983, + IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d8000, + IF_IF_decode_558_BITS_171_TO_167_562_EQ_8_568__ETC___d7987, + IF_IF_decode_558_BITS_171_TO_167_562_EQ_8_568__ETC___d8005, + IF_IF_f12f2_deqReq_lat_1_whas__13_THEN_f12f2_d_ETC___d143, + IF_IF_f12f2_deqReq_lat_1_whas__13_THEN_f12f2_d_ETC___d152, + IF_IF_f22f3_deqReq_lat_1_whas__76_THEN_f22f3_d_ETC___d406, + IF_IF_f22f3_deqReq_lat_1_whas__76_THEN_f22f3_d_ETC___d415, + IF_IF_f32d_deqReq_lat_1_whas__11_THEN_f32d_deq_ETC___d741, + IF_IF_f32d_deqReq_lat_1_whas__11_THEN_f32d_deq_ETC___d750, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d5044, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d5308, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d6664, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d5083, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d5379, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6694, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6759, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6775, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6785, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6795, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6805, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6815, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6825, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6835, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6845, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6855, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6865, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6875, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6885, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6895, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6905, + IF_NOT_IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15__ETC___d4732, + IF_NOT_IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15__ETC___d4781, + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5310, + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5315, + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5320, + IF_NOT_SEL_ARR_instdata_data_0_987_BITS_260_TO_ETC___d7977, + IF_NOT_SEL_ARR_instdata_data_0_987_BITS_260_TO_ETC___d8011, + IF_NOT_decode_047_BIT_26_079_080_AND_NOT_decod_ETC___d7120, + IF_NOT_decode_558_BIT_26_590_591_AND_NOT_decod_ETC___d7631, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5084, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5380, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6761, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6945, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6962, + IF_NOT_f22f3_empty_17_919_AND_SEL_ARR_f22f3_da_ETC___d5007, + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4709, + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4729, + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4741, + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4746, + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4783, + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7549, + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7975, + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7988, + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d8009, + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196, + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5203, + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5237, + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5278, + IF_SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_ETC___d7976, + IF_SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_ETC___d7985, + IF_SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_ETC___d8010, + IF_SEL_ARR_instdata_data_0_987_BITS_65_TO_64_9_ETC___d7551, + IF_decode_047_BITS_171_TO_167_051_EQ_8_057_AND_ETC___d7413, + IF_decode_558_BITS_171_TO_167_562_EQ_8_568_AND_ETC___d7924, + IF_decode_558_BITS_171_TO_167_562_EQ_8_568_AND_ETC___d7971, + IF_decode_epoch_lat_0_whas__6_THEN_decode_epoc_ETC___d19, + IF_ehr_pending_straddle_lat_1_whas__1_THEN_ehr_ETC___d30, + IF_f12f2_deqReq_lat_1_whas__13_THEN_f12f2_deqR_ETC___d119, + IF_f12f2_enqReq_lat_1_whas__6_THEN_NOT_f12f2_e_ETC___d62, + IF_f12f2_enqReq_lat_1_whas__6_THEN_f12f2_enqRe_ETC___d55, + IF_f22f3_deqReq_lat_1_whas__76_THEN_f22f3_deqR_ETC___d382, + IF_f22f3_enqReq_lat_1_whas__77_THEN_NOT_f22f3__ETC___d193, + IF_f22f3_enqReq_lat_1_whas__77_THEN_f22f3_enqR_ETC___d186, + IF_f32d_deqReq_lat_1_whas__11_THEN_f32d_deqReq_ETC___d717, + IF_f32d_enqReq_lat_1_whas__20_THEN_NOT_f32d_en_ETC___d536, + IF_f32d_enqReq_lat_1_whas__20_THEN_f32d_enqReq_ETC___d529, + IF_instdata_full_lat_0_whas__75_THEN_NOT_instd_ETC___d5149, + IF_out_fifo_dequeueFifo_lat_1_whas__93_THEN_ou_ETC___d899, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1151, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1156, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1184, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1213, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1248, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1263, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1275, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1286, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1315, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1339, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1363, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1387, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1410, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1433, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1456, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1479, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1895, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1911, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1928, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1944, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d909, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2077, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2318, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2323, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2351, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2380, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2415, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2430, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2442, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2453, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2482, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2506, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2529, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2553, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2576, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2599, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2622, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2645, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3060, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3076, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3093, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3109, + IF_out_fifo_enqueueFifo_lat_1_whas__83_THEN_ou_ETC___d889, + IF_out_fifo_willDequeue_0_lat_0_whas__236_THEN_ETC___d3239, + IF_out_fifo_willDequeue_1_lat_0_whas__243_THEN_ETC___d3246, + IF_pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NO_ETC___d4745, + IF_pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NO_ETC___d4779, + IF_perfReqQ_enqReq_lat_1_whas__342_THEN_perfRe_ETC___d4351, + IF_rg_pending_n_items_951_EQ_0_952_THEN_NOT_eh_ETC___d5077, + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988, + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d4965, + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081, + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5156, + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5163, + NOT_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_20_ETC___d6951, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4994, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4996, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5009, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5037, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5046, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5052, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5055, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5058, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5085, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5090, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5094, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5097, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5130, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5151, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5154, + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d6749, + NOT_SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_96_ETC___d5175, + NOT_SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_96_ETC___d5181, + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5087, + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5093, + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099, + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5106, + NOT_SEL_ARR_instdata_data_0_987_BITS_260_TO_25_ETC___d7566, + NOT_SEL_ARR_instdata_data_0_987_BITS_65_TO_64__ETC___d8003, + NOT_SEL_ARR_nextAddrPred_valid_0_read__422_nex_ETC___d4748, + NOT_decode_047_BITS_25_TO_21_081_EQ_decode_047_ETC___d7117, + NOT_decode_047_BIT_27_078_088_OR_decode_047_BI_ETC___d7095, + NOT_decode_047_BIT_7_058_071_OR_decode_047_BIT_ETC___d7087, + NOT_decode_047_BIT_7_058_071_OR_decode_047_BIT_ETC___d7411, + NOT_decode_558_BITS_25_TO_21_592_EQ_decode_558_ETC___d7628, + NOT_decode_558_BIT_27_589_599_OR_decode_558_BI_ETC___d7606, + NOT_decode_558_BIT_7_569_582_OR_decode_558_BIT_ETC___d7598, + NOT_decode_558_BIT_7_569_582_OR_decode_558_BIT_ETC___d7922, + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950, + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d5069, + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d5134, + NOT_instdata_empty_rl_67_978_AND_NOT_SEL_ARR_f_ETC___d7025, + NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_OR_ETC___d4708, + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d5210, + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d5223, + SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7972, + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4930, + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4980, + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4938, + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4983, + SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4947, + SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d6985, + SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d7615, + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998, + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d7552, + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d8007, + SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7018, + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d7005, + _0_CONCAT_IF_rg_pending_n_items_951_EQ_0_952_TH_ETC___d5375, + _dand1iMem$EN_to_proc_response_get, + _theResult_____2__h20522, + _theResult_____2__h6605, + b__h114808, + b__h114820, + decode_047_BITS_171_TO_167_051_EQ_8_057_AND_de_ETC___d7100, + decode_047_BIT_7_058_AND_NOT_decode_047_BIT_6__ETC___d7096, + decode_558_BITS_171_TO_167_562_EQ_8_568_AND_de_ETC___d7611, + decode_558_BIT_7_569_AND_NOT_decode_558_BIT_6__ETC___d7607, + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012, + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5019, + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5023, + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5039, + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5063, + n__read__h165419, + next_deqP___1__h20711, + next_deqP___1__h6794, + next_deqP__h170905, + next_enqP__h165312, + pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NOT_I_ETC___d4733, + pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NOT_I_ETC___d4749, + pc_reg_rl_BITS_63_TO_0_689_PLUS_2_690_BITS_63__ETC___d4704, + pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684, + rg_pending_f32d_953_BITS_3_TO_0_954_EQ_f_main__ETC___d4955, + rg_pending_f32d_953_BIT_4_957_EQ_IF_decode_epo_ETC___d4958, + upd__h165446, + upd__h21945, + upd__h24504, + upd__h25105, + v__h18830, + v__h18981, + v__h5669, + v__h5820, + x_BIT_109___h171706, + x_BIT_109___h182531, + x__h165551, + x__h19100, + x__h60535, + x__h74473; // value method pipelines_0_canDeq assign pipelines_0_canDeq = RDY_pipelines_0_first ; @@ -3628,14 +4210,14 @@ module mkFetchStage(CLK, // value method pipelines_0_first assign pipelines_0_first = - { x__h160939, - x__h161003, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6132 } ; - always@(x__h63120 or + { x__h195362, + x__h195426, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9243 } ; + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$EMPTY_N or out_fifo_internalFifos_1$EMPTY_N) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: RDY_pipelines_0_first = out_fifo_internalFifos_0$EMPTY_N; 1'd1: RDY_pipelines_0_first = out_fifo_internalFifos_1$EMPTY_N; endcase @@ -3652,14 +4234,14 @@ module mkFetchStage(CLK, // value method pipelines_1_first assign pipelines_1_first = - { x__h168127, - x__h168147, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6338 } ; - always@(x__h72803 or + { x__h207703, + x__h207723, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9606 } ; + always@(x__h74473 or out_fifo_internalFifos_0$EMPTY_N or out_fifo_internalFifos_1$EMPTY_N) begin - case (x__h72803) + case (x__h74473) 1'd0: RDY_pipelines_1_first = out_fifo_internalFifos_0$EMPTY_N; 1'd1: RDY_pipelines_1_first = out_fifo_internalFifos_1$EMPTY_N; endcase @@ -3691,10 +4273,10 @@ module mkFetchStage(CLK, // actionvalue method iTlbIfc_to_proc_response_get assign iTlbIfc_to_proc_response_get = - { iTlb$to_proc_response_get[68:4], - iTlb$to_proc_response_get[4] ? - CASE_iTlbto_proc_response_get_BITS_3_TO_0_0_i_ETC__q1 : - 4'hA } ; + { iTlb$to_proc_response_get[69:5], + iTlb$to_proc_response_get[5] ? + CASE_iTlbto_proc_response_get_BITS_4_TO_0_0_i_ETC__q1 : + 5'h0A } ; assign RDY_iTlbIfc_to_proc_response_get = iTlb$RDY_to_proc_response_get ; assign CAN_FIRE_iTlbIfc_to_proc_response_get = iTlb$RDY_to_proc_response_get ; @@ -3914,6 +4496,11 @@ module mkFetchStage(CLK, assign CAN_FIRE_redirect = 1'd1 ; assign WILL_FIRE_redirect = EN_redirect ; + // action method setWaitFlush + assign RDY_setWaitFlush = 1'd1 ; + assign CAN_FIRE_setWaitFlush = 1'd1 ; + assign WILL_FIRE_setWaitFlush = EN_setWaitFlush ; + // action method done_flushing assign RDY_done_flushing = waitForFlush ; assign CAN_FIRE_done_flushing = waitForFlush ; @@ -3942,7 +4529,10 @@ module mkFetchStage(CLK, // value method getFetchState assign getFetchState = - { x__h115849, f_main_epoch, waitForRedirect, waitForFlush } ; + { pc_reg_rl[63:0], + f_main_epoch, + waitForRedirect, + waitForFlush } ; assign RDY_getFetchState = 1'd1 ; // action method perf_setStatus @@ -3987,150 +4577,6 @@ module mkFetchStage(CLK, .flush_done(dirPred$flush_done), .RDY_flush_done()); - // submodule f12f2_clearReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) f12f2_clearReq_dummy2_0(.CLK(CLK), - .D_IN(f12f2_clearReq_dummy2_0$D_IN), - .EN(f12f2_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule f12f2_clearReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) f12f2_clearReq_dummy2_1(.CLK(CLK), - .D_IN(f12f2_clearReq_dummy2_1$D_IN), - .EN(f12f2_clearReq_dummy2_1$EN), - .Q_OUT(f12f2_clearReq_dummy2_1$Q_OUT)); - - // submodule f12f2_deqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) f12f2_deqReq_dummy2_0(.CLK(CLK), - .D_IN(f12f2_deqReq_dummy2_0$D_IN), - .EN(f12f2_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule f12f2_deqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) f12f2_deqReq_dummy2_1(.CLK(CLK), - .D_IN(f12f2_deqReq_dummy2_1$D_IN), - .EN(f12f2_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule f12f2_deqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) f12f2_deqReq_dummy2_2(.CLK(CLK), - .D_IN(f12f2_deqReq_dummy2_2$D_IN), - .EN(f12f2_deqReq_dummy2_2$EN), - .Q_OUT(f12f2_deqReq_dummy2_2$Q_OUT)); - - // submodule f12f2_enqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) f12f2_enqReq_dummy2_0(.CLK(CLK), - .D_IN(f12f2_enqReq_dummy2_0$D_IN), - .EN(f12f2_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule f12f2_enqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) f12f2_enqReq_dummy2_1(.CLK(CLK), - .D_IN(f12f2_enqReq_dummy2_1$D_IN), - .EN(f12f2_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule f12f2_enqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) f12f2_enqReq_dummy2_2(.CLK(CLK), - .D_IN(f12f2_enqReq_dummy2_2$D_IN), - .EN(f12f2_enqReq_dummy2_2$EN), - .Q_OUT(f12f2_enqReq_dummy2_2$Q_OUT)); - - // submodule f22f3_clearReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) f22f3_clearReq_dummy2_0(.CLK(CLK), - .D_IN(f22f3_clearReq_dummy2_0$D_IN), - .EN(f22f3_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule f22f3_clearReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) f22f3_clearReq_dummy2_1(.CLK(CLK), - .D_IN(f22f3_clearReq_dummy2_1$D_IN), - .EN(f22f3_clearReq_dummy2_1$EN), - .Q_OUT(f22f3_clearReq_dummy2_1$Q_OUT)); - - // submodule f22f3_deqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) f22f3_deqReq_dummy2_0(.CLK(CLK), - .D_IN(f22f3_deqReq_dummy2_0$D_IN), - .EN(f22f3_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule f22f3_deqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) f22f3_deqReq_dummy2_1(.CLK(CLK), - .D_IN(f22f3_deqReq_dummy2_1$D_IN), - .EN(f22f3_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule f22f3_deqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) f22f3_deqReq_dummy2_2(.CLK(CLK), - .D_IN(f22f3_deqReq_dummy2_2$D_IN), - .EN(f22f3_deqReq_dummy2_2$EN), - .Q_OUT(f22f3_deqReq_dummy2_2$Q_OUT)); - - // submodule f22f3_enqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) f22f3_enqReq_dummy2_0(.CLK(CLK), - .D_IN(f22f3_enqReq_dummy2_0$D_IN), - .EN(f22f3_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule f22f3_enqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) f22f3_enqReq_dummy2_1(.CLK(CLK), - .D_IN(f22f3_enqReq_dummy2_1$D_IN), - .EN(f22f3_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule f22f3_enqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) f22f3_enqReq_dummy2_2(.CLK(CLK), - .D_IN(f22f3_enqReq_dummy2_2$D_IN), - .EN(f22f3_enqReq_dummy2_2$EN), - .Q_OUT(f22f3_enqReq_dummy2_2$Q_OUT)); - - // submodule f32d_clearReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) f32d_clearReq_dummy2_0(.CLK(CLK), - .D_IN(f32d_clearReq_dummy2_0$D_IN), - .EN(f32d_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule f32d_clearReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) f32d_clearReq_dummy2_1(.CLK(CLK), - .D_IN(f32d_clearReq_dummy2_1$D_IN), - .EN(f32d_clearReq_dummy2_1$EN), - .Q_OUT(f32d_clearReq_dummy2_1$Q_OUT)); - - // submodule f32d_deqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) f32d_deqReq_dummy2_0(.CLK(CLK), - .D_IN(f32d_deqReq_dummy2_0$D_IN), - .EN(f32d_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule f32d_deqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) f32d_deqReq_dummy2_1(.CLK(CLK), - .D_IN(f32d_deqReq_dummy2_1$D_IN), - .EN(f32d_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule f32d_deqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) f32d_deqReq_dummy2_2(.CLK(CLK), - .D_IN(f32d_deqReq_dummy2_2$D_IN), - .EN(f32d_deqReq_dummy2_2$EN), - .Q_OUT(f32d_deqReq_dummy2_2$Q_OUT)); - - // submodule f32d_enqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) f32d_enqReq_dummy2_0(.CLK(CLK), - .D_IN(f32d_enqReq_dummy2_0$D_IN), - .EN(f32d_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule f32d_enqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) f32d_enqReq_dummy2_1(.CLK(CLK), - .D_IN(f32d_enqReq_dummy2_1$D_IN), - .EN(f32d_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule f32d_enqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) f32d_enqReq_dummy2_2(.CLK(CLK), - .D_IN(f32d_enqReq_dummy2_2$D_IN), - .EN(f32d_enqReq_dummy2_2$EN), - .Q_OUT(f32d_enqReq_dummy2_2$Q_OUT)); - // submodule iMem mkICoCache iMem(.CLK(CLK), .RST_N(RST_N), @@ -4224,66 +4670,6 @@ module mkFetchStage(CLK, .perf_respValid(iTlb$perf_respValid), .RDY_perf_respValid()); - // submodule instdata_deqP_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) instdata_deqP_dummy2_0(.CLK(CLK), - .D_IN(instdata_deqP_dummy2_0$D_IN), - .EN(instdata_deqP_dummy2_0$EN), - .Q_OUT(instdata_deqP_dummy2_0$Q_OUT)); - - // submodule instdata_deqP_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) instdata_deqP_dummy2_1(.CLK(CLK), - .D_IN(instdata_deqP_dummy2_1$D_IN), - .EN(instdata_deqP_dummy2_1$EN), - .Q_OUT(instdata_deqP_dummy2_1$Q_OUT)); - - // submodule instdata_empty_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) instdata_empty_dummy2_0(.CLK(CLK), - .D_IN(instdata_empty_dummy2_0$D_IN), - .EN(instdata_empty_dummy2_0$EN), - .Q_OUT(instdata_empty_dummy2_0$Q_OUT)); - - // submodule instdata_empty_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) instdata_empty_dummy2_1(.CLK(CLK), - .D_IN(instdata_empty_dummy2_1$D_IN), - .EN(instdata_empty_dummy2_1$EN), - .Q_OUT(instdata_empty_dummy2_1$Q_OUT)); - - // submodule instdata_empty_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) instdata_empty_dummy2_2(.CLK(CLK), - .D_IN(instdata_empty_dummy2_2$D_IN), - .EN(instdata_empty_dummy2_2$EN), - .Q_OUT(instdata_empty_dummy2_2$Q_OUT)); - - // submodule instdata_enqP_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) instdata_enqP_dummy2_0(.CLK(CLK), - .D_IN(instdata_enqP_dummy2_0$D_IN), - .EN(instdata_enqP_dummy2_0$EN), - .Q_OUT(instdata_enqP_dummy2_0$Q_OUT)); - - // submodule instdata_enqP_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) instdata_enqP_dummy2_1(.CLK(CLK), - .D_IN(instdata_enqP_dummy2_1$D_IN), - .EN(instdata_enqP_dummy2_1$EN), - .Q_OUT(instdata_enqP_dummy2_1$Q_OUT)); - - // submodule instdata_full_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) instdata_full_dummy2_0(.CLK(CLK), - .D_IN(instdata_full_dummy2_0$D_IN), - .EN(instdata_full_dummy2_0$EN), - .Q_OUT()); - - // submodule instdata_full_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) instdata_full_dummy2_1(.CLK(CLK), - .D_IN(instdata_full_dummy2_1$D_IN), - .EN(instdata_full_dummy2_1$EN), - .Q_OUT(instdata_full_dummy2_1$Q_OUT)); - - // submodule instdata_full_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) instdata_full_dummy2_2(.CLK(CLK), - .D_IN(instdata_full_dummy2_2$D_IN), - .EN(instdata_full_dummy2_2$EN), - .Q_OUT(instdata_full_dummy2_2$Q_OUT)); - // submodule mmio mkMMIOInst mmio(.CLK(CLK), .RST_N(RST_N), @@ -4315,79 +4701,9 @@ module mkFetchStage(CLK, .RDY_toCore_instResp_enq(mmio$RDY_toCore_instResp_enq), .RDY_toCore_setHtifAddrs()); - // submodule napTrainByDecQ_deqP_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) napTrainByDecQ_deqP_dummy2_0(.CLK(CLK), - .D_IN(napTrainByDecQ_deqP_dummy2_0$D_IN), - .EN(napTrainByDecQ_deqP_dummy2_0$EN), - .Q_OUT()); - - // submodule napTrainByDecQ_deqP_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) napTrainByDecQ_deqP_dummy2_1(.CLK(CLK), - .D_IN(napTrainByDecQ_deqP_dummy2_1$D_IN), - .EN(napTrainByDecQ_deqP_dummy2_1$EN), - .Q_OUT()); - - // submodule napTrainByDecQ_empty_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) napTrainByDecQ_empty_dummy2_0(.CLK(CLK), - .D_IN(napTrainByDecQ_empty_dummy2_0$D_IN), - .EN(napTrainByDecQ_empty_dummy2_0$EN), - .Q_OUT(napTrainByDecQ_empty_dummy2_0$Q_OUT)); - - // submodule napTrainByDecQ_empty_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) napTrainByDecQ_empty_dummy2_1(.CLK(CLK), - .D_IN(napTrainByDecQ_empty_dummy2_1$D_IN), - .EN(napTrainByDecQ_empty_dummy2_1$EN), - .Q_OUT(napTrainByDecQ_empty_dummy2_1$Q_OUT)); - - // submodule napTrainByDecQ_empty_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) napTrainByDecQ_empty_dummy2_2(.CLK(CLK), - .D_IN(napTrainByDecQ_empty_dummy2_2$D_IN), - .EN(napTrainByDecQ_empty_dummy2_2$EN), - .Q_OUT(napTrainByDecQ_empty_dummy2_2$Q_OUT)); - - // submodule napTrainByDecQ_enqP_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) napTrainByDecQ_enqP_dummy2_0(.CLK(CLK), - .D_IN(napTrainByDecQ_enqP_dummy2_0$D_IN), - .EN(napTrainByDecQ_enqP_dummy2_0$EN), - .Q_OUT()); - - // submodule napTrainByDecQ_enqP_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) napTrainByDecQ_enqP_dummy2_1(.CLK(CLK), - .D_IN(napTrainByDecQ_enqP_dummy2_1$D_IN), - .EN(napTrainByDecQ_enqP_dummy2_1$EN), - .Q_OUT()); - - // submodule napTrainByDecQ_full_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) napTrainByDecQ_full_dummy2_0(.CLK(CLK), - .D_IN(napTrainByDecQ_full_dummy2_0$D_IN), - .EN(napTrainByDecQ_full_dummy2_0$EN), - .Q_OUT()); - - // submodule napTrainByDecQ_full_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) napTrainByDecQ_full_dummy2_1(.CLK(CLK), - .D_IN(napTrainByDecQ_full_dummy2_1$D_IN), - .EN(napTrainByDecQ_full_dummy2_1$EN), - .Q_OUT(napTrainByDecQ_full_dummy2_1$Q_OUT)); - - // submodule napTrainByDecQ_full_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) napTrainByDecQ_full_dummy2_2(.CLK(CLK), - .D_IN(napTrainByDecQ_full_dummy2_2$D_IN), - .EN(napTrainByDecQ_full_dummy2_2$EN), - .Q_OUT(napTrainByDecQ_full_dummy2_2$Q_OUT)); - // submodule nextAddrPred_next_addrs RegFile #(.addr_width(32'd8), - .data_width(32'd64), + .data_width(32'd129), .lo(8'd0), .hi(8'd255)) nextAddrPred_next_addrs(.CLK(CLK), .ADDR_1(nextAddrPred_next_addrs$ADDR_1), @@ -4400,13 +4716,13 @@ module mkFetchStage(CLK, .WE(nextAddrPred_next_addrs$WE), .D_OUT_1(nextAddrPred_next_addrs$D_OUT_1), .D_OUT_2(nextAddrPred_next_addrs$D_OUT_2), - .D_OUT_3(), - .D_OUT_4(), + .D_OUT_3(nextAddrPred_next_addrs$D_OUT_3), + .D_OUT_4(nextAddrPred_next_addrs$D_OUT_4), .D_OUT_5()); // submodule nextAddrPred_tags RegFile #(.addr_width(32'd8), - .data_width(32'd54), + .data_width(32'd55), .lo(8'd0), .hi(8'd255)) nextAddrPred_tags(.CLK(CLK), .ADDR_1(nextAddrPred_tags$ADDR_1), @@ -4420,81 +4736,11 @@ module mkFetchStage(CLK, .D_OUT_1(nextAddrPred_tags$D_OUT_1), .D_OUT_2(nextAddrPred_tags$D_OUT_2), .D_OUT_3(nextAddrPred_tags$D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule out_fifo_dequeueFifo_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_dequeueFifo_dummy2_0(.CLK(CLK), - .D_IN(out_fifo_dequeueFifo_dummy2_0$D_IN), - .EN(out_fifo_dequeueFifo_dummy2_0$EN), - .Q_OUT(out_fifo_dequeueFifo_dummy2_0$Q_OUT)); - - // submodule out_fifo_dequeueFifo_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_dequeueFifo_dummy2_1(.CLK(CLK), - .D_IN(out_fifo_dequeueFifo_dummy2_1$D_IN), - .EN(out_fifo_dequeueFifo_dummy2_1$EN), - .Q_OUT(out_fifo_dequeueFifo_dummy2_1$Q_OUT)); - - // submodule out_fifo_dequeueFifo_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_dequeueFifo_dummy2_2(.CLK(CLK), - .D_IN(out_fifo_dequeueFifo_dummy2_2$D_IN), - .EN(out_fifo_dequeueFifo_dummy2_2$EN), - .Q_OUT(out_fifo_dequeueFifo_dummy2_2$Q_OUT)); - - // submodule out_fifo_enqueueElement_0_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_enqueueElement_0_dummy2_0(.CLK(CLK), - .D_IN(out_fifo_enqueueElement_0_dummy2_0$D_IN), - .EN(out_fifo_enqueueElement_0_dummy2_0$EN), - .Q_OUT()); - - // submodule out_fifo_enqueueElement_0_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_enqueueElement_0_dummy2_1(.CLK(CLK), - .D_IN(out_fifo_enqueueElement_0_dummy2_1$D_IN), - .EN(out_fifo_enqueueElement_0_dummy2_1$EN), - .Q_OUT(out_fifo_enqueueElement_0_dummy2_1$Q_OUT)); - - // submodule out_fifo_enqueueElement_1_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_enqueueElement_1_dummy2_0(.CLK(CLK), - .D_IN(out_fifo_enqueueElement_1_dummy2_0$D_IN), - .EN(out_fifo_enqueueElement_1_dummy2_0$EN), - .Q_OUT()); - - // submodule out_fifo_enqueueElement_1_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_enqueueElement_1_dummy2_1(.CLK(CLK), - .D_IN(out_fifo_enqueueElement_1_dummy2_1$D_IN), - .EN(out_fifo_enqueueElement_1_dummy2_1$EN), - .Q_OUT(out_fifo_enqueueElement_1_dummy2_1$Q_OUT)); - - // submodule out_fifo_enqueueFifo_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_enqueueFifo_dummy2_0(.CLK(CLK), - .D_IN(out_fifo_enqueueFifo_dummy2_0$D_IN), - .EN(out_fifo_enqueueFifo_dummy2_0$EN), - .Q_OUT(out_fifo_enqueueFifo_dummy2_0$Q_OUT)); - - // submodule out_fifo_enqueueFifo_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_enqueueFifo_dummy2_1(.CLK(CLK), - .D_IN(out_fifo_enqueueFifo_dummy2_1$D_IN), - .EN(out_fifo_enqueueFifo_dummy2_1$EN), - .Q_OUT(out_fifo_enqueueFifo_dummy2_1$Q_OUT)); - - // submodule out_fifo_enqueueFifo_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_enqueueFifo_dummy2_2(.CLK(CLK), - .D_IN(out_fifo_enqueueFifo_dummy2_2$D_IN), - .EN(out_fifo_enqueueFifo_dummy2_2$EN), - .Q_OUT(out_fifo_enqueueFifo_dummy2_2$Q_OUT)); + .D_OUT_4(nextAddrPred_tags$D_OUT_4), + .D_OUT_5(nextAddrPred_tags$D_OUT_5)); // submodule out_fifo_internalFifos_0 - FIFO2 #(.width(32'd388), + FIFO2 #(.width(32'd591), .guarded(32'd0)) out_fifo_internalFifos_0(.RST(RST_N), .CLK(CLK), .D_IN(out_fifo_internalFifos_0$D_IN), @@ -4506,7 +4752,7 @@ module mkFetchStage(CLK, .EMPTY_N(out_fifo_internalFifos_0$EMPTY_N)); // submodule out_fifo_internalFifos_1 - FIFO2 #(.width(32'd388), + FIFO2 #(.width(32'd591), .guarded(32'd0)) out_fifo_internalFifos_1(.RST(RST_N), .CLK(CLK), .D_IN(out_fifo_internalFifos_1$D_IN), @@ -4517,102 +4763,6 @@ module mkFetchStage(CLK, .FULL_N(out_fifo_internalFifos_1$FULL_N), .EMPTY_N(out_fifo_internalFifos_1$EMPTY_N)); - // submodule out_fifo_willDequeue_0_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_willDequeue_0_dummy2_0(.CLK(CLK), - .D_IN(out_fifo_willDequeue_0_dummy2_0$D_IN), - .EN(out_fifo_willDequeue_0_dummy2_0$EN), - .Q_OUT()); - - // submodule out_fifo_willDequeue_0_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_willDequeue_0_dummy2_1(.CLK(CLK), - .D_IN(out_fifo_willDequeue_0_dummy2_1$D_IN), - .EN(out_fifo_willDequeue_0_dummy2_1$EN), - .Q_OUT(out_fifo_willDequeue_0_dummy2_1$Q_OUT)); - - // submodule out_fifo_willDequeue_1_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_willDequeue_1_dummy2_0(.CLK(CLK), - .D_IN(out_fifo_willDequeue_1_dummy2_0$D_IN), - .EN(out_fifo_willDequeue_1_dummy2_0$EN), - .Q_OUT()); - - // submodule out_fifo_willDequeue_1_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) out_fifo_willDequeue_1_dummy2_1(.CLK(CLK), - .D_IN(out_fifo_willDequeue_1_dummy2_1$D_IN), - .EN(out_fifo_willDequeue_1_dummy2_1$EN), - .Q_OUT(out_fifo_willDequeue_1_dummy2_1$Q_OUT)); - - // submodule pc_reg_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) pc_reg_dummy2_0(.CLK(CLK), - .D_IN(pc_reg_dummy2_0$D_IN), - .EN(pc_reg_dummy2_0$EN), - .Q_OUT(pc_reg_dummy2_0$Q_OUT)); - - // submodule pc_reg_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) pc_reg_dummy2_1(.CLK(CLK), - .D_IN(pc_reg_dummy2_1$D_IN), - .EN(pc_reg_dummy2_1$EN), - .Q_OUT(pc_reg_dummy2_1$Q_OUT)); - - // submodule pc_reg_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) pc_reg_dummy2_2(.CLK(CLK), - .D_IN(pc_reg_dummy2_2$D_IN), - .EN(pc_reg_dummy2_2$EN), - .Q_OUT(pc_reg_dummy2_2$Q_OUT)); - - // submodule perfReqQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) perfReqQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(perfReqQ_clearReq_dummy2_0$D_IN), - .EN(perfReqQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule perfReqQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) perfReqQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(perfReqQ_clearReq_dummy2_1$D_IN), - .EN(perfReqQ_clearReq_dummy2_1$EN), - .Q_OUT(perfReqQ_clearReq_dummy2_1$Q_OUT)); - - // submodule perfReqQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(perfReqQ_deqReq_dummy2_0$D_IN), - .EN(perfReqQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule perfReqQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(perfReqQ_deqReq_dummy2_1$D_IN), - .EN(perfReqQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule perfReqQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(perfReqQ_deqReq_dummy2_2$D_IN), - .EN(perfReqQ_deqReq_dummy2_2$EN), - .Q_OUT(perfReqQ_deqReq_dummy2_2$Q_OUT)); - - // submodule perfReqQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(perfReqQ_enqReq_dummy2_0$D_IN), - .EN(perfReqQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule perfReqQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(perfReqQ_enqReq_dummy2_1$D_IN), - .EN(perfReqQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule perfReqQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(perfReqQ_enqReq_dummy2_2$D_IN), - .EN(perfReqQ_enqReq_dummy2_2$EN), - .Q_OUT(perfReqQ_enqReq_dummy2_2$Q_OUT)); - // submodule ras mkRas ras(.CLK(CLK), .RST_N(RST_N), @@ -4652,31 +4802,23 @@ module mkFetchStage(CLK, !EN_iTlbIfc_to_proc_response_get ; // rule RL_setTrainNAPByDec - assign CAN_FIRE_RL_setTrainNAPByDec = - !napTrainByDecQ_empty_dummy2_0$Q_OUT || - !napTrainByDecQ_empty_dummy2_1$Q_OUT || - !napTrainByDecQ_empty_dummy2_2$Q_OUT || - !napTrainByDecQ_empty_rl ; + assign CAN_FIRE_RL_setTrainNAPByDec = !napTrainByDecQ_empty_rl ; assign WILL_FIRE_RL_setTrainNAPByDec = CAN_FIRE_RL_setTrainNAPByDec ; // rule RL_doDecode assign CAN_FIRE_RL_doDecode = !f32d_empty && - (!instdata_empty_dummy2_0$Q_OUT || - !instdata_empty_dummy2_1$Q_OUT || - !instdata_empty_dummy2_2$Q_OUT || - !instdata_empty_rl) && - (!SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 || - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4735) ; + NOT_instdata_empty_rl_67_978_AND_NOT_SEL_ARR_f_ETC___d7025 ; assign WILL_FIRE_RL_doDecode = CAN_FIRE_RL_doDecode ; // rule RL_doFetch3 assign CAN_FIRE_RL_doFetch3 = - !f22f3_empty && - f22f3_empty_47_OR_NOT_SEL_ARR_NOT_f22f3_data_0_ETC___d3539 ; + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5058) && + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5063 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5156 ; assign WILL_FIRE_RL_doFetch3 = - CAN_FIRE_RL_doFetch3 && !WILL_FIRE_RL_doDecode && - !EN_iMemIfc_to_proc_response_get ; + CAN_FIRE_RL_doFetch3 && !EN_iMemIfc_to_proc_response_get ; // rule RL_doTrainNAP assign CAN_FIRE_RL_doTrainNAP = CAN_FIRE_RL_nextAddrPred_canonUpdate ; @@ -4686,6 +4828,14 @@ module mkFetchStage(CLK, assign CAN_FIRE_RL_pc_reg_canon = 1'd1 ; assign WILL_FIRE_RL_pc_reg_canon = 1'd1 ; + // rule RL_decode_epoch_canon + assign CAN_FIRE_RL_decode_epoch_canon = 1'd1 ; + assign WILL_FIRE_RL_decode_epoch_canon = 1'd1 ; + + // rule RL_ehr_pending_straddle_canon + assign CAN_FIRE_RL_ehr_pending_straddle_canon = 1'd1 ; + assign WILL_FIRE_RL_ehr_pending_straddle_canon = 1'd1 ; + // rule RL_f12f2_canonicalize assign CAN_FIRE_RL_f12f2_canonicalize = 1'd1 ; assign WILL_FIRE_RL_f12f2_canonicalize = 1'd1 ; @@ -4780,7 +4930,7 @@ module mkFetchStage(CLK, // rule RL_nextAddrPred_canonUpdate assign CAN_FIRE_RL_nextAddrPred_canonUpdate = - CAN_FIRE_RL_setTrainNAPByDec || napTrainByExe$whas ; + !napTrainByDecQ_empty_rl || napTrainByExe$whas ; assign WILL_FIRE_RL_nextAddrPred_canonUpdate = CAN_FIRE_RL_nextAddrPred_canonUpdate ; @@ -4810,135 +4960,144 @@ module mkFetchStage(CLK, // inputs to muxes for submodule ports assign MUX_iMem$to_proc_request_put_1__SEL_1 = - WILL_FIRE_RL_doFetch2 && !iTlb$to_proc_response_get[4] && + WILL_FIRE_RL_doFetch2 && !iTlb$to_proc_response_get[5] && mmio$getFetchTarget == 2'd0 ; - assign MUX_rg_pending_straddle$write_1__SEL_1 = - WILL_FIRE_RL_doDecode && _dfoo523 ; - assign MUX_iTlb$to_proc_request_put_1__VAL_2 = { x__h115849[63:2], 2'd0 } ; + assign MUX_iTlb$to_proc_request_put_1__VAL_2 = { pc_reg_rl[63:2], 2'd0 } ; + assign MUX_pc_reg_lat_0$wset_1__VAL_2 = + (NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_OR_ETC___d4708 ? + IF_pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NO_ETC___d4745 : + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4746) ? + def__h108385 : + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4768 ; // inlined wires assign pc_reg_lat_0$whas = EN_start || WILL_FIRE_RL_doFetch1 ; - assign pc_reg_dummy_1_0$whas = + assign pc_reg_lat_1$whas = WILL_FIRE_RL_doDecode && - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - IF_SEL_ARR_instdata_data_0_686_BITS_195_TO_194_ETC___d5447 ; + SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d6985 && + IF_NOT_SEL_ARR_instdata_data_0_987_BITS_260_TO_ETC___d7977 ; + assign pc_reg_lat_2$whas = + WILL_FIRE_RL_doFetch3 && + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 && + IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d5322 ; + assign decode_epoch_lat_0$wget = + (SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_334_011_f32d_data__ETC___d7014) ? + (SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d7552 ? + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7988 : + IF_SEL_ARR_instdata_data_0_987_BITS_65_TO_64_9_ETC___d7551) : + IF_SEL_ARR_instdata_data_0_987_BITS_65_TO_64_9_ETC___d7551 ; + assign decode_epoch_lat_0$whas = + WILL_FIRE_RL_doDecode && + SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d6985 ; + assign ehr_pending_straddle_lat_0$wget = + { IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6945, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6975 } ; assign f12f2_enqReq_lat_0$wget = { 1'd1, - x__h115826, - x__h115849, - pred_next_pc__h114166, - decode_epoch, + x__h111739, + pc_reg_rl, + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4786, + fetch3_epoch, + decode_epoch_rl, f_main_epoch } ; assign f22f3_enqReq_lat_0$wget = { 1'd1, - x__h116417, - x__h116419, - iTlb$to_proc_response_get[68:5], - SEL_ARR_f12f2_data_0_378_BITS_68_TO_5_388_f12f_ETC___d3466 } ; + SEL_ARR_f12f2_data_0_810_BITS_266_TO_265_811_f_ETC___d4815, + out_pc__h112351, + !CASE_f12f2_deqP_0_NOT_f12f2_data_0_BIT_135_1_N_ETC__q381, + CASE_f12f2_deqP_0_f12f2_data_0_BITS_134_TO_6_1_ETC__q382, + iTlb_to_proc_response_get_801_BIT_5_802_OR_NOT_ETC___d4916 } ; + assign f22f3_deqReq_lat_0$whas = + WILL_FIRE_RL_doFetch3 && + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ; assign f32d_enqReq_lat_0$wget = { 1'd1, - value__h117642, - start_PC__h117515, - value__h117654, - value__h117656, - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483, - IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4659, - value__h118910, - SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491, - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3501, - SEL_ARR_f22f3_data_0_470_BITS_3_TO_0_950_f22f3_ETC___d3955 } ; + x__h165551, + x__h165562, + x__h165577, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6761, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5084, + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6920, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6934 } ; assign f32d_enqReq_lat_0$whas = WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 ; + (pending_n_items__h113790 != 2'd0 || + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012) && + n_items__h145984 != 3'd0 ; assign instdata_empty_lat_0$whas = - WILL_FIRE_RL_doDecode && - next_deqP__h142575 == - (instdata_enqP_dummy2_0$Q_OUT && instdata_enqP_dummy2_1$Q_OUT && - instdata_enqP_rl) ; + WILL_FIRE_RL_doDecode && next_deqP__h170905 == instdata_enqP_rl ; assign instdata_full_lat_1$whas = WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d4646 ; - assign out_fifo_enqueueFifo_lat_0$whas = - out_fifo_enqueueElement_0_dummy2_1$Q_OUT && - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d830 ; - assign out_fifo_enqueueFifo_lat_1$whas = - out_fifo_enqueueElement_1_dummy2_1$Q_OUT && - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1398 ; - assign out_fifo_dequeueFifo_lat_0$whas = - out_fifo_willDequeue_0_dummy2_1$Q_OUT && - IF_out_fifo_willDequeue_0_lat_0_whas__959_THEN_ETC___d1962 ; - assign out_fifo_dequeueFifo_lat_1$whas = - out_fifo_willDequeue_1_dummy2_1$Q_OUT && - IF_out_fifo_willDequeue_1_lat_0_whas__966_THEN_ETC___d1969 ; + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d6749 ; assign out_fifo_enqueueElement_0_lat_0$wget = { 1'd1, - x__h143344, - x__h147295, - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4683, - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5007, - SEL_ARR_instdata_data_0_686_BITS_31_TO_0_764_i_ETC___d4767, - decode_768_BITS_99_TO_95_772_CONCAT_IF_decode__ETC___d4969, - SEL_ARR_instdata_data_0_686_BITS_63_TO_32_751__ETC___d4754, - decode___d4768[27:1], - !SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 || - decode___d4768[0], - IF_NOT_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758__ETC___d5145, - x__h149997 } ; + x__h171664, + x__h177367, + out_main_epoch__h177345, + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7438, + SEL_ARR_instdata_data_0_987_BITS_31_TO_0_038_i_ETC___d7041, + decode_047_BITS_171_TO_167_051_CONCAT_IF_decod_ETC___d7400, + x__h180841, + decode___d7047[27:1], + !SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 || + decode___d7047[0], + IF_NOT_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032__ETC___d7533, + tval___2__h171521 } ; assign out_fifo_enqueueElement_0_lat_0$whas = WILL_FIRE_RL_doDecode && - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd3 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != + SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d6985 && + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 != 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 ; + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998 ; assign out_fifo_enqueueElement_1_lat_0$wget = { 1'd1, - SEL_ARR_instdata_data_0_686_BITS_259_TO_196_99_ETC___d4994, - x__h154053, - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4683, - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5411, - SEL_ARR_instdata_data_0_686_BITS_161_TO_130_17_ETC___d5179, - decode_180_BITS_99_TO_95_184_CONCAT_IF_decode__ETC___d5381, - SEL_ARR_instdata_data_0_686_BITS_193_TO_162_16_ETC___d5171, - decode___d5180[27:1], - !SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 || - decode___d5180[0], - IF_NOT_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758__ETC___d5145, - x__h149997 } ; - assign out_fifo_enqueueElement_1_dummy_1_0$wget = + SEL_ARR_instdata_data_0_987_BITS_389_TO_261_42_ETC___d7425, + x__h187834, + out_main_epoch__h177345, + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7941, + SEL_ARR_instdata_data_0_987_BITS_226_TO_195_55_ETC___d7556, + decode_558_BITS_171_TO_167_562_CONCAT_IF_decod_ETC___d7911, + x__h191306, + decode___d7558[27:1], + !SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 || + decode___d7558[0], + IF_NOT_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032__ETC___d7533, + tval___2__h171521 } ; + assign out_fifo_enqueueElement_1_lat_0$whas = WILL_FIRE_RL_doDecode && - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 != - 2'd3 && - SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 != + SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d6985 && + SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 != 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165 ; + SEL_ARR_f32d_data_0_979_BIT_334_011_f32d_data__ETC___d7014 && + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d7552 ; assign nextAddrPred_updateEn$wget = - { x__h160492, x__h160545, x__h160545 != y__h160555 } ; - assign napTrainByExe$wget = - { train_predictors_pc, train_predictors_next_pc } ; + { x__h194838, + train_nextPc__h194872, + train_nextPc__h194872 != + { x__h194838[128:64], address__h194902 } } ; + assign napTrainByExe$wget = { x__h225902, train_predictors_next_pc } ; assign napTrainByExe$whas = EN_train_predictors && train_predictors_mispred ; assign perfReqQ_enqReq_lat_0$wget = { 1'd1, perf_req_r } ; assign napTrainByDecQ_enqP_lat_0$whas = WILL_FIRE_RL_doDecode && - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - IF_SEL_ARR_instdata_data_0_686_BITS_195_TO_194_ETC___d5476 ; + SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d6985 && + IF_NOT_SEL_ARR_instdata_data_0_987_BITS_260_TO_ETC___d8011 ; - // register decode_epoch - assign decode_epoch$D_IN = - (SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 == - 2'd3 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719) ? - (SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165 ? - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5463 : - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5164) : - IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5468 ; - assign decode_epoch$EN = - WILL_FIRE_RL_doDecode && - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 ; + // register decode_epoch_rl + assign decode_epoch_rl$D_IN = + IF_decode_epoch_lat_0_whas__6_THEN_decode_epoc_ETC___d19 ; + assign decode_epoch_rl$EN = 1'd1 ; + + // register ehr_pending_straddle_rl + assign ehr_pending_straddle_rl$D_IN = + { IF_ehr_pending_straddle_lat_1_whas__1_THEN_ehr_ETC___d30, + IF_ehr_pending_straddle_lat_1_whas__1_THEN_ehr_ETC___d40 } ; + assign ehr_pending_straddle_rl$EN = 1'd1 ; // register f12f2_clearReq_rl assign f12f2_clearReq_rl$D_IN = 1'd0 ; @@ -4946,30 +5105,30 @@ module mkFetchStage(CLK, // register f12f2_data_0 assign f12f2_data_0$D_IN = - WILL_FIRE_RL_doFetch1 ? - f12f2_enqReq_lat_0$wget[133:0] : - f12f2_enqReq_rl[133:0] ; + { x__h5939, + x_snd_pc__h6025, + IF_f12f2_enqReq_lat_1_whas__6_THEN_NOT_f12f2_e_ETC___d62 || + (WILL_FIRE_RL_doFetch1 ? + f12f2_enqReq_lat_0$wget[135] : + f12f2_enqReq_rl[135]), + WILL_FIRE_RL_doFetch1 ? + f12f2_enqReq_lat_0$wget[134:6] : + f12f2_enqReq_rl[134:6], + WILL_FIRE_RL_doFetch1 ? + f12f2_enqReq_lat_0$wget[5:0] : + f12f2_enqReq_rl[5:0] } ; assign f12f2_data_0$EN = - f12f2_enqP == 1'd0 && - NOT_f12f2_clearReq_dummy2_1_read__8_9_OR_IF_f1_ETC___d63 && - f12f2_enqReq_dummy2_2$Q_OUT && - IF_f12f2_enqReq_lat_1_whas__4_THEN_f12f2_enqRe_ETC___d23 ; + f12f2_enqP == 1'd0 && !f12f2_clearReq_rl && + IF_f12f2_enqReq_lat_1_whas__6_THEN_f12f2_enqRe_ETC___d55 ; // register f12f2_data_1 - assign f12f2_data_1$D_IN = - WILL_FIRE_RL_doFetch1 ? - f12f2_enqReq_lat_0$wget[133:0] : - f12f2_enqReq_rl[133:0] ; + assign f12f2_data_1$D_IN = f12f2_data_0$D_IN ; assign f12f2_data_1$EN = - f12f2_enqP == 1'd1 && - NOT_f12f2_clearReq_dummy2_1_read__8_9_OR_IF_f1_ETC___d63 && - f12f2_enqReq_dummy2_2$Q_OUT && - IF_f12f2_enqReq_lat_1_whas__4_THEN_f12f2_enqRe_ETC___d23 ; + f12f2_enqP == 1'd1 && !f12f2_clearReq_rl && + IF_f12f2_enqReq_lat_1_whas__6_THEN_f12f2_enqRe_ETC___d55 ; // register f12f2_deqP - assign f12f2_deqP$D_IN = - NOT_f12f2_clearReq_dummy2_1_read__8_9_OR_IF_f1_ETC___d63 && - _theResult_____2__h7993 ; + assign f12f2_deqP$D_IN = !f12f2_clearReq_rl && _theResult_____2__h6605 ; assign f12f2_deqP$EN = 1'd1 ; // register f12f2_deqReq_rl @@ -4978,26 +5137,26 @@ module mkFetchStage(CLK, // register f12f2_empty assign f12f2_empty$D_IN = - f12f2_clearReq_dummy2_1$Q_OUT && f12f2_clearReq_rl || - IF_f12f2_deqReq_dummy2_2_read__2_AND_IF_f12f2__ETC___d80 && - NOT_f12f2_enqReq_dummy2_2_read__4_4_OR_IF_f12f_ETC___d98 ; + f12f2_clearReq_rl || + IF_IF_f12f2_deqReq_lat_1_whas__13_THEN_f12f2_d_ETC___d143 && + IF_f12f2_enqReq_lat_1_whas__6_THEN_NOT_f12f2_e_ETC___d62 && + (IF_f12f2_deqReq_lat_1_whas__13_THEN_f12f2_deqR_ETC___d119 || + f12f2_empty) ; assign f12f2_empty$EN = 1'd1 ; // register f12f2_enqP - assign f12f2_enqP$D_IN = - NOT_f12f2_clearReq_dummy2_1_read__8_9_OR_IF_f1_ETC___d63 && - v__h7269 ; + assign f12f2_enqP$D_IN = !f12f2_clearReq_rl && v__h5669 ; assign f12f2_enqP$EN = 1'd1 ; // register f12f2_enqReq_rl - assign f12f2_enqReq_rl$D_IN = 135'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; + assign f12f2_enqReq_rl$D_IN = + 268'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign f12f2_enqReq_rl$EN = 1'd1 ; // register f12f2_full assign f12f2_full$D_IN = - NOT_f12f2_clearReq_dummy2_1_read__8_9_OR_IF_f1_ETC___d63 && - IF_f12f2_deqReq_dummy2_2_read__2_AND_IF_f12f2__ETC___d80 && - f12f2_enqReq_dummy2_2_read__4_AND_IF_f12f2_enq_ETC___d90 ; + !f12f2_clearReq_rl && + IF_IF_f12f2_deqReq_lat_1_whas__13_THEN_f12f2_d_ETC___d152 ; assign f12f2_full$EN = 1'd1 ; // register f22f3_clearReq_rl @@ -5006,46 +5165,34 @@ module mkFetchStage(CLK, // register f22f3_data_0 assign f22f3_data_0$D_IN = - { x__h16438, - x__h16495, - x__h16558, - x__h16572, - NOT_f22f3_enqReq_dummy2_2_read__11_45_OR_IF_f2_ETC___d431 } ; + { x__h11317, + x_snd_pc__h11415, + IF_f22f3_enqReq_lat_1_whas__77_THEN_NOT_f22f3__ETC___d509 } ; assign f22f3_data_0$EN = - f22f3_enqP == 2'd0 && - NOT_f22f3_clearReq_dummy2_1_read__09_27_OR_IF__ETC___d331 && - f22f3_enqReq_dummy2_2$Q_OUT && - IF_f22f3_enqReq_lat_1_whas__11_THEN_f22f3_enqR_ETC___d120 ; + f22f3_enqP == 2'd0 && !f22f3_clearReq_rl && + IF_f22f3_enqReq_lat_1_whas__77_THEN_f22f3_enqR_ETC___d186 ; // register f22f3_data_1 assign f22f3_data_1$D_IN = f22f3_data_0$D_IN ; assign f22f3_data_1$EN = - f22f3_enqP == 2'd1 && - NOT_f22f3_clearReq_dummy2_1_read__09_27_OR_IF__ETC___d331 && - f22f3_enqReq_dummy2_2$Q_OUT && - IF_f22f3_enqReq_lat_1_whas__11_THEN_f22f3_enqR_ETC___d120 ; + f22f3_enqP == 2'd1 && !f22f3_clearReq_rl && + IF_f22f3_enqReq_lat_1_whas__77_THEN_f22f3_enqR_ETC___d186 ; // register f22f3_data_2 assign f22f3_data_2$D_IN = f22f3_data_0$D_IN ; assign f22f3_data_2$EN = - f22f3_enqP == 2'd2 && - NOT_f22f3_clearReq_dummy2_1_read__09_27_OR_IF__ETC___d331 && - f22f3_enqReq_dummy2_2$Q_OUT && - IF_f22f3_enqReq_lat_1_whas__11_THEN_f22f3_enqR_ETC___d120 ; + f22f3_enqP == 2'd2 && !f22f3_clearReq_rl && + IF_f22f3_enqReq_lat_1_whas__77_THEN_f22f3_enqR_ETC___d186 ; // register f22f3_data_3 assign f22f3_data_3$D_IN = f22f3_data_0$D_IN ; assign f22f3_data_3$EN = - f22f3_enqP == 2'd3 && - NOT_f22f3_clearReq_dummy2_1_read__09_27_OR_IF__ETC___d331 && - f22f3_enqReq_dummy2_2$Q_OUT && - IF_f22f3_enqReq_lat_1_whas__11_THEN_f22f3_enqR_ETC___d120 ; + f22f3_enqP == 2'd3 && !f22f3_clearReq_rl && + IF_f22f3_enqReq_lat_1_whas__77_THEN_f22f3_enqR_ETC___d186 ; // register f22f3_deqP assign f22f3_deqP$D_IN = - (f22f3_clearReq_dummy2_1$Q_OUT && f22f3_clearReq_rl) ? - 2'd0 : - _theResult_____2__h19260 ; + f22f3_clearReq_rl ? 2'd0 : _theResult_____2__h14823 ; assign f22f3_deqP$EN = 1'd1 ; // register f22f3_deqReq_rl @@ -5054,28 +5201,26 @@ module mkFetchStage(CLK, // register f22f3_empty assign f22f3_empty$D_IN = - f22f3_clearReq_dummy2_1$Q_OUT && f22f3_clearReq_rl || - IF_f22f3_deqReq_dummy2_2_read__19_AND_IF_f22f3_ETC___d332 && - NOT_f22f3_enqReq_dummy2_2_read__11_45_OR_IF_f2_ETC___d349 ; + f22f3_clearReq_rl || + IF_IF_f22f3_deqReq_lat_1_whas__76_THEN_f22f3_d_ETC___d406 && + IF_f22f3_enqReq_lat_1_whas__77_THEN_NOT_f22f3__ETC___d193 && + (IF_f22f3_deqReq_lat_1_whas__76_THEN_f22f3_deqR_ETC___d382 || + f22f3_empty) ; assign f22f3_empty$EN = 1'd1 ; // register f22f3_enqP - assign f22f3_enqP$D_IN = - (f22f3_clearReq_dummy2_1$Q_OUT && f22f3_clearReq_rl) ? - 2'd0 : - v__h15956 ; + assign f22f3_enqP$D_IN = f22f3_clearReq_rl ? 2'd0 : v__h10967 ; assign f22f3_enqP$EN = 1'd1 ; // register f22f3_enqReq_rl assign f22f3_enqReq_rl$D_IN = - 269'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABEAAAAAAAAAAAAAAAAA ; + 339'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAE2AAAAAAAAAAAAAAAAA ; assign f22f3_enqReq_rl$EN = 1'd1 ; // register f22f3_full assign f22f3_full$D_IN = - NOT_f22f3_clearReq_dummy2_1_read__09_27_OR_IF__ETC___d331 && - IF_f22f3_deqReq_dummy2_2_read__19_AND_IF_f22f3_ETC___d332 && - f22f3_enqReq_dummy2_2_read__11_AND_IF_f22f3_en_ETC___d342 ; + !f22f3_clearReq_rl && + IF_IF_f22f3_deqReq_lat_1_whas__76_THEN_f22f3_d_ETC___d415 ; assign f22f3_full$EN = 1'd1 ; // register f32d_clearReq_rl @@ -5083,30 +5228,25 @@ module mkFetchStage(CLK, assign f32d_clearReq_rl$EN = 1'd1 ; // register f32d_data_0 - assign f32d_data_0$D_IN = f32d_data_1$D_IN ; + assign f32d_data_0$D_IN = + { x__h19100, + x__h19157, + IF_IF_f32d_enqReq_lat_1_whas__20_THEN_NOT_f32d_ETC___d842 } ; assign f32d_data_0$EN = - f32d_enqP == 1'd0 && - NOT_f32d_clearReq_dummy2_1_read__41_42_OR_IF_f_ETC___d646 && - f32d_enqReq_dummy2_2$Q_OUT && - IF_f32d_enqReq_lat_1_whas__43_THEN_f32d_enqReq_ETC___d452 ; + f32d_enqP == 1'd0 && !f32d_clearReq_rl && + IF_f32d_enqReq_lat_1_whas__20_THEN_f32d_enqReq_ETC___d529 ; // register f32d_data_1 assign f32d_data_1$D_IN = - { x__h27482, - x__h27539, - x__h27602, - x__h27616, - NOT_f32d_enqReq_dummy2_2_read__47_77_OR_IF_f32_ETC___d763 } ; + { x__h19100, + x__h19157, + IF_IF_f32d_enqReq_lat_1_whas__20_THEN_NOT_f32d_ETC___d842 } ; assign f32d_data_1$EN = - f32d_enqP == 1'd1 && - NOT_f32d_clearReq_dummy2_1_read__41_42_OR_IF_f_ETC___d646 && - f32d_enqReq_dummy2_2$Q_OUT && - IF_f32d_enqReq_lat_1_whas__43_THEN_f32d_enqReq_ETC___d452 ; + f32d_enqP == 1'd1 && !f32d_clearReq_rl && + IF_f32d_enqReq_lat_1_whas__20_THEN_f32d_enqReq_ETC___d529 ; // register f32d_deqP - assign f32d_deqP$D_IN = - NOT_f32d_clearReq_dummy2_1_read__41_42_OR_IF_f_ETC___d646 && - _theResult_____2__h28906 ; + assign f32d_deqP$D_IN = !f32d_clearReq_rl && _theResult_____2__h20522 ; assign f32d_deqP$EN = 1'd1 ; // register f32d_deqReq_rl @@ -5115,27 +5255,26 @@ module mkFetchStage(CLK, // register f32d_empty assign f32d_empty$D_IN = - f32d_clearReq_dummy2_1$Q_OUT && f32d_clearReq_rl || - IF_f32d_deqReq_dummy2_2_read__55_AND_IF_f32d_d_ETC___d663 && - NOT_f32d_enqReq_dummy2_2_read__47_77_OR_IF_f32_ETC___d681 ; + f32d_clearReq_rl || + IF_IF_f32d_deqReq_lat_1_whas__11_THEN_f32d_deq_ETC___d741 && + IF_f32d_enqReq_lat_1_whas__20_THEN_NOT_f32d_en_ETC___d536 && + (IF_f32d_deqReq_lat_1_whas__11_THEN_f32d_deqReq_ETC___d717 || + f32d_empty) ; assign f32d_empty$EN = 1'd1 ; // register f32d_enqP - assign f32d_enqP$D_IN = - NOT_f32d_clearReq_dummy2_1_read__41_42_OR_IF_f_ETC___d646 && - v__h27080 ; + assign f32d_enqP$D_IN = !f32d_clearReq_rl && v__h18830 ; assign f32d_enqP$EN = 1'd1 ; // register f32d_enqReq_rl assign f32d_enqReq_rl$D_IN = - 269'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABEAAAAAAAAAAAAAAAAA ; + 336'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAB8AAAAAAAAAAAAAAAAA ; assign f32d_enqReq_rl$EN = 1'd1 ; // register f32d_full assign f32d_full$D_IN = - NOT_f32d_clearReq_dummy2_1_read__41_42_OR_IF_f_ETC___d646 && - IF_f32d_deqReq_dummy2_2_read__55_AND_IF_f32d_d_ETC___d663 && - f32d_enqReq_dummy2_2_read__47_AND_IF_f32d_enqR_ETC___d673 ; + !f32d_clearReq_rl && + IF_IF_f32d_deqReq_lat_1_whas__11_THEN_f32d_deq_ETC___d750 ; assign f32d_full$EN = 1'd1 ; // register f_main_epoch @@ -5143,38 +5282,36 @@ module mkFetchStage(CLK, (f_main_epoch == 4'd11) ? 4'd0 : f_main_epoch + 4'd1 ; assign f_main_epoch$EN = EN_redirect ; + // register fetch3_epoch + assign fetch3_epoch$D_IN = !fetch3_epoch ; + assign fetch3_epoch$EN = pc_reg_lat_2$whas ; + // register instdata_data_0 assign instdata_data_0$D_IN = - { IF_IF_rg_pending_straddle_514_THEN_IF_SEL_ARR__ETC___d4011 ? - y_avValue_snd_snd_snd_fst__h122323 : - pc_start__h119765, - (IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4042 < - n_x16s__h119766) ? - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4340 : - 66'd0, - pc_start__h119765, - IF_IF_rg_pending_straddle_514_THEN_IF_SEL_ARR__ETC___d4011 ? - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4633 : - 66'd0 } ; + { SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_389_ETC___d6710, + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_260_ETC___d6714, + x__h165114, + x__h165122, + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_194_ETC___d6727, + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_65__ETC___d6731, + x__h165191, + x__h165202 } ; assign instdata_data_0$EN = - WILL_FIRE_RL_doFetch3 && - (instdata_enqP_dummy2_0$Q_OUT && instdata_enqP_dummy2_1$Q_OUT && - instdata_enqP_rl) == - 1'd0 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 ; + WILL_FIRE_RL_doFetch3 && instdata_enqP_rl == 1'd0 && + (pending_n_items__h113790 != 2'd0 || + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012) && + n_items__h145984 != 3'd0 ; // register instdata_data_1 assign instdata_data_1$D_IN = instdata_data_0$D_IN ; assign instdata_data_1$EN = - WILL_FIRE_RL_doFetch3 && - (instdata_enqP_dummy2_0$Q_OUT && instdata_enqP_dummy2_1$Q_OUT && - instdata_enqP_rl) == - 1'd1 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 ; + WILL_FIRE_RL_doFetch3 && instdata_enqP_rl == 1'd1 && + (pending_n_items__h113790 != 2'd0 || + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012) && + n_items__h145984 != 3'd0 ; // register instdata_deqP_rl - assign instdata_deqP_rl$D_IN = - IF_instdata_deqP_lat_0_whas__77_THEN_instdata__ETC___d780 ; + assign instdata_deqP_rl$D_IN = n__read__h165419 ; assign instdata_deqP_rl$EN = 1'd1 ; // register instdata_empty_rl @@ -5185,7 +5322,7 @@ module mkFetchStage(CLK, // register instdata_enqP_rl assign instdata_enqP_rl$D_IN = - f32d_enqReq_lat_0$whas ? upd__h32146 : instdata_enqP_rl ; + f32d_enqReq_lat_0$whas ? upd__h21945 : instdata_enqP_rl ; assign instdata_enqP_rl$EN = 1'd1 ; // register instdata_full_rl @@ -5196,3371 +5333,3371 @@ module mkFetchStage(CLK, // register napTrainByDecQ_data_0 assign napTrainByDecQ_data_0$D_IN = - (SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 == - 2'd3 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719) ? - { x__h143344, decode_pred_next_pc__h146966 } : - IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5483 ; + (SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_334_011_f32d_data__ETC___d7014) ? + (SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d7552 ? + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d8030 : + IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d8028) : + IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d8028 ; assign napTrainByDecQ_data_0$EN = napTrainByDecQ_enqP_lat_0$whas ; // register napTrainByDecQ_empty_rl - assign napTrainByDecQ_empty_rl$D_IN = - !napTrainByDecQ_enqP_lat_0$whas && - (CAN_FIRE_RL_setTrainNAPByDec || napTrainByDecQ_empty_rl) ; + assign napTrainByDecQ_empty_rl$D_IN = !napTrainByDecQ_enqP_lat_0$whas ; assign napTrainByDecQ_empty_rl$EN = 1'd1 ; // register napTrainByDecQ_full_rl assign napTrainByDecQ_full_rl$D_IN = napTrainByDecQ_enqP_lat_0$whas || - !CAN_FIRE_RL_setTrainNAPByDec && napTrainByDecQ_full_rl ; + !(!napTrainByDecQ_empty_rl) && napTrainByDecQ_full_rl ; assign napTrainByDecQ_full_rl$EN = 1'd1 ; // register nextAddrPred_valid_0 assign nextAddrPred_valid_0$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd0 && + nextAddrPred_updateEn$wget[138:131] == 8'd0 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_0$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd0 && + (nextAddrPred_updateEn$wget[138:131] == 8'd0 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd0 && + nextAddrPred_updateEn$wget[138:131] == 8'd0 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_1 assign nextAddrPred_valid_1$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd1 && + nextAddrPred_updateEn$wget[138:131] == 8'd1 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_1$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd1 && + (nextAddrPred_updateEn$wget[138:131] == 8'd1 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd1 && + nextAddrPred_updateEn$wget[138:131] == 8'd1 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_10 assign nextAddrPred_valid_10$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd10 && + nextAddrPred_updateEn$wget[138:131] == 8'd10 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_10$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd10 && + (nextAddrPred_updateEn$wget[138:131] == 8'd10 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd10 && + nextAddrPred_updateEn$wget[138:131] == 8'd10 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_100 assign nextAddrPred_valid_100$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd100 && + nextAddrPred_updateEn$wget[138:131] == 8'd100 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_100$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd100 && + (nextAddrPred_updateEn$wget[138:131] == 8'd100 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd100 && + nextAddrPred_updateEn$wget[138:131] == 8'd100 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_101 assign nextAddrPred_valid_101$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd101 && + nextAddrPred_updateEn$wget[138:131] == 8'd101 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_101$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd101 && + (nextAddrPred_updateEn$wget[138:131] == 8'd101 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd101 && + nextAddrPred_updateEn$wget[138:131] == 8'd101 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_102 assign nextAddrPred_valid_102$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd102 && + nextAddrPred_updateEn$wget[138:131] == 8'd102 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_102$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd102 && + (nextAddrPred_updateEn$wget[138:131] == 8'd102 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd102 && + nextAddrPred_updateEn$wget[138:131] == 8'd102 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_103 assign nextAddrPred_valid_103$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd103 && + nextAddrPred_updateEn$wget[138:131] == 8'd103 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_103$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd103 && + (nextAddrPred_updateEn$wget[138:131] == 8'd103 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd103 && + nextAddrPred_updateEn$wget[138:131] == 8'd103 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_104 assign nextAddrPred_valid_104$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd104 && + nextAddrPred_updateEn$wget[138:131] == 8'd104 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_104$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd104 && + (nextAddrPred_updateEn$wget[138:131] == 8'd104 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd104 && + nextAddrPred_updateEn$wget[138:131] == 8'd104 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_105 assign nextAddrPred_valid_105$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd105 && + nextAddrPred_updateEn$wget[138:131] == 8'd105 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_105$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd105 && + (nextAddrPred_updateEn$wget[138:131] == 8'd105 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd105 && + nextAddrPred_updateEn$wget[138:131] == 8'd105 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_106 assign nextAddrPred_valid_106$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd106 && + nextAddrPred_updateEn$wget[138:131] == 8'd106 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_106$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd106 && + (nextAddrPred_updateEn$wget[138:131] == 8'd106 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd106 && + nextAddrPred_updateEn$wget[138:131] == 8'd106 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_107 assign nextAddrPred_valid_107$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd107 && + nextAddrPred_updateEn$wget[138:131] == 8'd107 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_107$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd107 && + (nextAddrPred_updateEn$wget[138:131] == 8'd107 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd107 && + nextAddrPred_updateEn$wget[138:131] == 8'd107 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_108 assign nextAddrPred_valid_108$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd108 && + nextAddrPred_updateEn$wget[138:131] == 8'd108 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_108$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd108 && + (nextAddrPred_updateEn$wget[138:131] == 8'd108 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd108 && + nextAddrPred_updateEn$wget[138:131] == 8'd108 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_109 assign nextAddrPred_valid_109$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd109 && + nextAddrPred_updateEn$wget[138:131] == 8'd109 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_109$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd109 && + (nextAddrPred_updateEn$wget[138:131] == 8'd109 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd109 && + nextAddrPred_updateEn$wget[138:131] == 8'd109 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_11 assign nextAddrPred_valid_11$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd11 && + nextAddrPred_updateEn$wget[138:131] == 8'd11 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_11$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd11 && + (nextAddrPred_updateEn$wget[138:131] == 8'd11 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd11 && + nextAddrPred_updateEn$wget[138:131] == 8'd11 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_110 assign nextAddrPred_valid_110$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd110 && + nextAddrPred_updateEn$wget[138:131] == 8'd110 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_110$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd110 && + (nextAddrPred_updateEn$wget[138:131] == 8'd110 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd110 && + nextAddrPred_updateEn$wget[138:131] == 8'd110 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_111 assign nextAddrPred_valid_111$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd111 && + nextAddrPred_updateEn$wget[138:131] == 8'd111 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_111$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd111 && + (nextAddrPred_updateEn$wget[138:131] == 8'd111 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd111 && + nextAddrPred_updateEn$wget[138:131] == 8'd111 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_112 assign nextAddrPred_valid_112$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd112 && + nextAddrPred_updateEn$wget[138:131] == 8'd112 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_112$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd112 && + (nextAddrPred_updateEn$wget[138:131] == 8'd112 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd112 && + nextAddrPred_updateEn$wget[138:131] == 8'd112 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_113 assign nextAddrPred_valid_113$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd113 && + nextAddrPred_updateEn$wget[138:131] == 8'd113 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_113$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd113 && + (nextAddrPred_updateEn$wget[138:131] == 8'd113 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd113 && + nextAddrPred_updateEn$wget[138:131] == 8'd113 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_114 assign nextAddrPred_valid_114$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd114 && + nextAddrPred_updateEn$wget[138:131] == 8'd114 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_114$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd114 && + (nextAddrPred_updateEn$wget[138:131] == 8'd114 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd114 && + nextAddrPred_updateEn$wget[138:131] == 8'd114 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_115 assign nextAddrPred_valid_115$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd115 && + nextAddrPred_updateEn$wget[138:131] == 8'd115 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_115$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd115 && + (nextAddrPred_updateEn$wget[138:131] == 8'd115 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd115 && + nextAddrPred_updateEn$wget[138:131] == 8'd115 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_116 assign nextAddrPred_valid_116$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd116 && + nextAddrPred_updateEn$wget[138:131] == 8'd116 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_116$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd116 && + (nextAddrPred_updateEn$wget[138:131] == 8'd116 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd116 && + nextAddrPred_updateEn$wget[138:131] == 8'd116 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_117 assign nextAddrPred_valid_117$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd117 && + nextAddrPred_updateEn$wget[138:131] == 8'd117 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_117$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd117 && + (nextAddrPred_updateEn$wget[138:131] == 8'd117 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd117 && + nextAddrPred_updateEn$wget[138:131] == 8'd117 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_118 assign nextAddrPred_valid_118$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd118 && + nextAddrPred_updateEn$wget[138:131] == 8'd118 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_118$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd118 && + (nextAddrPred_updateEn$wget[138:131] == 8'd118 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd118 && + nextAddrPred_updateEn$wget[138:131] == 8'd118 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_119 assign nextAddrPred_valid_119$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd119 && + nextAddrPred_updateEn$wget[138:131] == 8'd119 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_119$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd119 && + (nextAddrPred_updateEn$wget[138:131] == 8'd119 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd119 && + nextAddrPred_updateEn$wget[138:131] == 8'd119 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_12 assign nextAddrPred_valid_12$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd12 && + nextAddrPred_updateEn$wget[138:131] == 8'd12 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_12$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd12 && + (nextAddrPred_updateEn$wget[138:131] == 8'd12 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd12 && + nextAddrPred_updateEn$wget[138:131] == 8'd12 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_120 assign nextAddrPred_valid_120$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd120 && + nextAddrPred_updateEn$wget[138:131] == 8'd120 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_120$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd120 && + (nextAddrPred_updateEn$wget[138:131] == 8'd120 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd120 && + nextAddrPred_updateEn$wget[138:131] == 8'd120 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_121 assign nextAddrPred_valid_121$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd121 && + nextAddrPred_updateEn$wget[138:131] == 8'd121 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_121$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd121 && + (nextAddrPred_updateEn$wget[138:131] == 8'd121 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd121 && + nextAddrPred_updateEn$wget[138:131] == 8'd121 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_122 assign nextAddrPred_valid_122$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd122 && + nextAddrPred_updateEn$wget[138:131] == 8'd122 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_122$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd122 && + (nextAddrPred_updateEn$wget[138:131] == 8'd122 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd122 && + nextAddrPred_updateEn$wget[138:131] == 8'd122 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_123 assign nextAddrPred_valid_123$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd123 && + nextAddrPred_updateEn$wget[138:131] == 8'd123 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_123$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd123 && + (nextAddrPred_updateEn$wget[138:131] == 8'd123 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd123 && + nextAddrPred_updateEn$wget[138:131] == 8'd123 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_124 assign nextAddrPred_valid_124$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd124 && + nextAddrPred_updateEn$wget[138:131] == 8'd124 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_124$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd124 && + (nextAddrPred_updateEn$wget[138:131] == 8'd124 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd124 && + nextAddrPred_updateEn$wget[138:131] == 8'd124 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_125 assign nextAddrPred_valid_125$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd125 && + nextAddrPred_updateEn$wget[138:131] == 8'd125 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_125$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd125 && + (nextAddrPred_updateEn$wget[138:131] == 8'd125 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd125 && + nextAddrPred_updateEn$wget[138:131] == 8'd125 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_126 assign nextAddrPred_valid_126$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd126 && + nextAddrPred_updateEn$wget[138:131] == 8'd126 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_126$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd126 && + (nextAddrPred_updateEn$wget[138:131] == 8'd126 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd126 && + nextAddrPred_updateEn$wget[138:131] == 8'd126 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_127 assign nextAddrPred_valid_127$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd127 && + nextAddrPred_updateEn$wget[138:131] == 8'd127 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_127$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd127 && + (nextAddrPred_updateEn$wget[138:131] == 8'd127 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd127 && + nextAddrPred_updateEn$wget[138:131] == 8'd127 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_128 assign nextAddrPred_valid_128$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd128 && + nextAddrPred_updateEn$wget[138:131] == 8'd128 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_128$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd128 && + (nextAddrPred_updateEn$wget[138:131] == 8'd128 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd128 && + nextAddrPred_updateEn$wget[138:131] == 8'd128 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_129 assign nextAddrPred_valid_129$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd129 && + nextAddrPred_updateEn$wget[138:131] == 8'd129 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_129$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd129 && + (nextAddrPred_updateEn$wget[138:131] == 8'd129 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd129 && + nextAddrPred_updateEn$wget[138:131] == 8'd129 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_13 assign nextAddrPred_valid_13$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd13 && + nextAddrPred_updateEn$wget[138:131] == 8'd13 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_13$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd13 && + (nextAddrPred_updateEn$wget[138:131] == 8'd13 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd13 && + nextAddrPred_updateEn$wget[138:131] == 8'd13 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_130 assign nextAddrPred_valid_130$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd130 && + nextAddrPred_updateEn$wget[138:131] == 8'd130 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_130$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd130 && + (nextAddrPred_updateEn$wget[138:131] == 8'd130 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd130 && + nextAddrPred_updateEn$wget[138:131] == 8'd130 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_131 assign nextAddrPred_valid_131$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd131 && + nextAddrPred_updateEn$wget[138:131] == 8'd131 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_131$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd131 && + (nextAddrPred_updateEn$wget[138:131] == 8'd131 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd131 && + nextAddrPred_updateEn$wget[138:131] == 8'd131 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_132 assign nextAddrPred_valid_132$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd132 && + nextAddrPred_updateEn$wget[138:131] == 8'd132 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_132$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd132 && + (nextAddrPred_updateEn$wget[138:131] == 8'd132 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd132 && + nextAddrPred_updateEn$wget[138:131] == 8'd132 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_133 assign nextAddrPred_valid_133$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd133 && + nextAddrPred_updateEn$wget[138:131] == 8'd133 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_133$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd133 && + (nextAddrPred_updateEn$wget[138:131] == 8'd133 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd133 && + nextAddrPred_updateEn$wget[138:131] == 8'd133 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_134 assign nextAddrPred_valid_134$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd134 && + nextAddrPred_updateEn$wget[138:131] == 8'd134 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_134$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd134 && + (nextAddrPred_updateEn$wget[138:131] == 8'd134 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd134 && + nextAddrPred_updateEn$wget[138:131] == 8'd134 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_135 assign nextAddrPred_valid_135$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd135 && + nextAddrPred_updateEn$wget[138:131] == 8'd135 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_135$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd135 && + (nextAddrPred_updateEn$wget[138:131] == 8'd135 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd135 && + nextAddrPred_updateEn$wget[138:131] == 8'd135 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_136 assign nextAddrPred_valid_136$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd136 && + nextAddrPred_updateEn$wget[138:131] == 8'd136 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_136$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd136 && + (nextAddrPred_updateEn$wget[138:131] == 8'd136 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd136 && + nextAddrPred_updateEn$wget[138:131] == 8'd136 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_137 assign nextAddrPred_valid_137$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd137 && + nextAddrPred_updateEn$wget[138:131] == 8'd137 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_137$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd137 && + (nextAddrPred_updateEn$wget[138:131] == 8'd137 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd137 && + nextAddrPred_updateEn$wget[138:131] == 8'd137 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_138 assign nextAddrPred_valid_138$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd138 && + nextAddrPred_updateEn$wget[138:131] == 8'd138 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_138$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd138 && + (nextAddrPred_updateEn$wget[138:131] == 8'd138 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd138 && + nextAddrPred_updateEn$wget[138:131] == 8'd138 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_139 assign nextAddrPred_valid_139$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd139 && + nextAddrPred_updateEn$wget[138:131] == 8'd139 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_139$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd139 && + (nextAddrPred_updateEn$wget[138:131] == 8'd139 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd139 && + nextAddrPred_updateEn$wget[138:131] == 8'd139 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_14 assign nextAddrPred_valid_14$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd14 && + nextAddrPred_updateEn$wget[138:131] == 8'd14 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_14$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd14 && + (nextAddrPred_updateEn$wget[138:131] == 8'd14 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd14 && + nextAddrPred_updateEn$wget[138:131] == 8'd14 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_140 assign nextAddrPred_valid_140$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd140 && + nextAddrPred_updateEn$wget[138:131] == 8'd140 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_140$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd140 && + (nextAddrPred_updateEn$wget[138:131] == 8'd140 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd140 && + nextAddrPred_updateEn$wget[138:131] == 8'd140 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_141 assign nextAddrPred_valid_141$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd141 && + nextAddrPred_updateEn$wget[138:131] == 8'd141 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_141$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd141 && + (nextAddrPred_updateEn$wget[138:131] == 8'd141 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd141 && + nextAddrPred_updateEn$wget[138:131] == 8'd141 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_142 assign nextAddrPred_valid_142$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd142 && + nextAddrPred_updateEn$wget[138:131] == 8'd142 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_142$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd142 && + (nextAddrPred_updateEn$wget[138:131] == 8'd142 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd142 && + nextAddrPred_updateEn$wget[138:131] == 8'd142 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_143 assign nextAddrPred_valid_143$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd143 && + nextAddrPred_updateEn$wget[138:131] == 8'd143 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_143$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd143 && + (nextAddrPred_updateEn$wget[138:131] == 8'd143 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd143 && + nextAddrPred_updateEn$wget[138:131] == 8'd143 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_144 assign nextAddrPred_valid_144$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd144 && + nextAddrPred_updateEn$wget[138:131] == 8'd144 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_144$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd144 && + (nextAddrPred_updateEn$wget[138:131] == 8'd144 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd144 && + nextAddrPred_updateEn$wget[138:131] == 8'd144 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_145 assign nextAddrPred_valid_145$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd145 && + nextAddrPred_updateEn$wget[138:131] == 8'd145 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_145$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd145 && + (nextAddrPred_updateEn$wget[138:131] == 8'd145 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd145 && + nextAddrPred_updateEn$wget[138:131] == 8'd145 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_146 assign nextAddrPred_valid_146$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd146 && + nextAddrPred_updateEn$wget[138:131] == 8'd146 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_146$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd146 && + (nextAddrPred_updateEn$wget[138:131] == 8'd146 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd146 && + nextAddrPred_updateEn$wget[138:131] == 8'd146 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_147 assign nextAddrPred_valid_147$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd147 && + nextAddrPred_updateEn$wget[138:131] == 8'd147 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_147$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd147 && + (nextAddrPred_updateEn$wget[138:131] == 8'd147 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd147 && + nextAddrPred_updateEn$wget[138:131] == 8'd147 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_148 assign nextAddrPred_valid_148$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd148 && + nextAddrPred_updateEn$wget[138:131] == 8'd148 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_148$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd148 && + (nextAddrPred_updateEn$wget[138:131] == 8'd148 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd148 && + nextAddrPred_updateEn$wget[138:131] == 8'd148 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_149 assign nextAddrPred_valid_149$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd149 && + nextAddrPred_updateEn$wget[138:131] == 8'd149 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_149$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd149 && + (nextAddrPred_updateEn$wget[138:131] == 8'd149 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd149 && + nextAddrPred_updateEn$wget[138:131] == 8'd149 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_15 assign nextAddrPred_valid_15$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd15 && + nextAddrPred_updateEn$wget[138:131] == 8'd15 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_15$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd15 && + (nextAddrPred_updateEn$wget[138:131] == 8'd15 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd15 && + nextAddrPred_updateEn$wget[138:131] == 8'd15 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_150 assign nextAddrPred_valid_150$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd150 && + nextAddrPred_updateEn$wget[138:131] == 8'd150 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_150$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd150 && + (nextAddrPred_updateEn$wget[138:131] == 8'd150 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd150 && + nextAddrPred_updateEn$wget[138:131] == 8'd150 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_151 assign nextAddrPred_valid_151$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd151 && + nextAddrPred_updateEn$wget[138:131] == 8'd151 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_151$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd151 && + (nextAddrPred_updateEn$wget[138:131] == 8'd151 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd151 && + nextAddrPred_updateEn$wget[138:131] == 8'd151 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_152 assign nextAddrPred_valid_152$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd152 && + nextAddrPred_updateEn$wget[138:131] == 8'd152 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_152$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd152 && + (nextAddrPred_updateEn$wget[138:131] == 8'd152 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd152 && + nextAddrPred_updateEn$wget[138:131] == 8'd152 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_153 assign nextAddrPred_valid_153$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd153 && + nextAddrPred_updateEn$wget[138:131] == 8'd153 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_153$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd153 && + (nextAddrPred_updateEn$wget[138:131] == 8'd153 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd153 && + nextAddrPred_updateEn$wget[138:131] == 8'd153 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_154 assign nextAddrPred_valid_154$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd154 && + nextAddrPred_updateEn$wget[138:131] == 8'd154 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_154$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd154 && + (nextAddrPred_updateEn$wget[138:131] == 8'd154 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd154 && + nextAddrPred_updateEn$wget[138:131] == 8'd154 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_155 assign nextAddrPred_valid_155$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd155 && + nextAddrPred_updateEn$wget[138:131] == 8'd155 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_155$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd155 && + (nextAddrPred_updateEn$wget[138:131] == 8'd155 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd155 && + nextAddrPred_updateEn$wget[138:131] == 8'd155 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_156 assign nextAddrPred_valid_156$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd156 && + nextAddrPred_updateEn$wget[138:131] == 8'd156 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_156$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd156 && + (nextAddrPred_updateEn$wget[138:131] == 8'd156 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd156 && + nextAddrPred_updateEn$wget[138:131] == 8'd156 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_157 assign nextAddrPred_valid_157$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd157 && + nextAddrPred_updateEn$wget[138:131] == 8'd157 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_157$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd157 && + (nextAddrPred_updateEn$wget[138:131] == 8'd157 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd157 && + nextAddrPred_updateEn$wget[138:131] == 8'd157 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_158 assign nextAddrPred_valid_158$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd158 && + nextAddrPred_updateEn$wget[138:131] == 8'd158 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_158$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd158 && + (nextAddrPred_updateEn$wget[138:131] == 8'd158 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd158 && + nextAddrPred_updateEn$wget[138:131] == 8'd158 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_159 assign nextAddrPred_valid_159$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd159 && + nextAddrPred_updateEn$wget[138:131] == 8'd159 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_159$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd159 && + (nextAddrPred_updateEn$wget[138:131] == 8'd159 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd159 && + nextAddrPred_updateEn$wget[138:131] == 8'd159 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_16 assign nextAddrPred_valid_16$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd16 && + nextAddrPred_updateEn$wget[138:131] == 8'd16 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_16$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd16 && + (nextAddrPred_updateEn$wget[138:131] == 8'd16 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd16 && + nextAddrPred_updateEn$wget[138:131] == 8'd16 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_160 assign nextAddrPred_valid_160$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd160 && + nextAddrPred_updateEn$wget[138:131] == 8'd160 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_160$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd160 && + (nextAddrPred_updateEn$wget[138:131] == 8'd160 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd160 && + nextAddrPred_updateEn$wget[138:131] == 8'd160 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_161 assign nextAddrPred_valid_161$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd161 && + nextAddrPred_updateEn$wget[138:131] == 8'd161 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_161$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd161 && + (nextAddrPred_updateEn$wget[138:131] == 8'd161 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd161 && + nextAddrPred_updateEn$wget[138:131] == 8'd161 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_162 assign nextAddrPred_valid_162$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd162 && + nextAddrPred_updateEn$wget[138:131] == 8'd162 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_162$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd162 && + (nextAddrPred_updateEn$wget[138:131] == 8'd162 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd162 && + nextAddrPred_updateEn$wget[138:131] == 8'd162 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_163 assign nextAddrPred_valid_163$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd163 && + nextAddrPred_updateEn$wget[138:131] == 8'd163 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_163$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd163 && + (nextAddrPred_updateEn$wget[138:131] == 8'd163 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd163 && + nextAddrPred_updateEn$wget[138:131] == 8'd163 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_164 assign nextAddrPred_valid_164$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd164 && + nextAddrPred_updateEn$wget[138:131] == 8'd164 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_164$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd164 && + (nextAddrPred_updateEn$wget[138:131] == 8'd164 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd164 && + nextAddrPred_updateEn$wget[138:131] == 8'd164 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_165 assign nextAddrPred_valid_165$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd165 && + nextAddrPred_updateEn$wget[138:131] == 8'd165 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_165$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd165 && + (nextAddrPred_updateEn$wget[138:131] == 8'd165 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd165 && + nextAddrPred_updateEn$wget[138:131] == 8'd165 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_166 assign nextAddrPred_valid_166$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd166 && + nextAddrPred_updateEn$wget[138:131] == 8'd166 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_166$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd166 && + (nextAddrPred_updateEn$wget[138:131] == 8'd166 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd166 && + nextAddrPred_updateEn$wget[138:131] == 8'd166 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_167 assign nextAddrPred_valid_167$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd167 && + nextAddrPred_updateEn$wget[138:131] == 8'd167 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_167$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd167 && + (nextAddrPred_updateEn$wget[138:131] == 8'd167 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd167 && + nextAddrPred_updateEn$wget[138:131] == 8'd167 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_168 assign nextAddrPred_valid_168$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd168 && + nextAddrPred_updateEn$wget[138:131] == 8'd168 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_168$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd168 && + (nextAddrPred_updateEn$wget[138:131] == 8'd168 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd168 && + nextAddrPred_updateEn$wget[138:131] == 8'd168 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_169 assign nextAddrPred_valid_169$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd169 && + nextAddrPred_updateEn$wget[138:131] == 8'd169 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_169$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd169 && + (nextAddrPred_updateEn$wget[138:131] == 8'd169 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd169 && + nextAddrPred_updateEn$wget[138:131] == 8'd169 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_17 assign nextAddrPred_valid_17$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd17 && + nextAddrPred_updateEn$wget[138:131] == 8'd17 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_17$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd17 && + (nextAddrPred_updateEn$wget[138:131] == 8'd17 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd17 && + nextAddrPred_updateEn$wget[138:131] == 8'd17 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_170 assign nextAddrPred_valid_170$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd170 && + nextAddrPred_updateEn$wget[138:131] == 8'd170 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_170$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd170 && + (nextAddrPred_updateEn$wget[138:131] == 8'd170 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd170 && + nextAddrPred_updateEn$wget[138:131] == 8'd170 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_171 assign nextAddrPred_valid_171$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd171 && + nextAddrPred_updateEn$wget[138:131] == 8'd171 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_171$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd171 && + (nextAddrPred_updateEn$wget[138:131] == 8'd171 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd171 && + nextAddrPred_updateEn$wget[138:131] == 8'd171 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_172 assign nextAddrPred_valid_172$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd172 && + nextAddrPred_updateEn$wget[138:131] == 8'd172 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_172$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd172 && + (nextAddrPred_updateEn$wget[138:131] == 8'd172 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd172 && + nextAddrPred_updateEn$wget[138:131] == 8'd172 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_173 assign nextAddrPred_valid_173$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd173 && + nextAddrPred_updateEn$wget[138:131] == 8'd173 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_173$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd173 && + (nextAddrPred_updateEn$wget[138:131] == 8'd173 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd173 && + nextAddrPred_updateEn$wget[138:131] == 8'd173 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_174 assign nextAddrPred_valid_174$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd174 && + nextAddrPred_updateEn$wget[138:131] == 8'd174 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_174$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd174 && + (nextAddrPred_updateEn$wget[138:131] == 8'd174 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd174 && + nextAddrPred_updateEn$wget[138:131] == 8'd174 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_175 assign nextAddrPred_valid_175$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd175 && + nextAddrPred_updateEn$wget[138:131] == 8'd175 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_175$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd175 && + (nextAddrPred_updateEn$wget[138:131] == 8'd175 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd175 && + nextAddrPred_updateEn$wget[138:131] == 8'd175 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_176 assign nextAddrPred_valid_176$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd176 && + nextAddrPred_updateEn$wget[138:131] == 8'd176 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_176$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd176 && + (nextAddrPred_updateEn$wget[138:131] == 8'd176 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd176 && + nextAddrPred_updateEn$wget[138:131] == 8'd176 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_177 assign nextAddrPred_valid_177$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd177 && + nextAddrPred_updateEn$wget[138:131] == 8'd177 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_177$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd177 && + (nextAddrPred_updateEn$wget[138:131] == 8'd177 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd177 && + nextAddrPred_updateEn$wget[138:131] == 8'd177 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_178 assign nextAddrPred_valid_178$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd178 && + nextAddrPred_updateEn$wget[138:131] == 8'd178 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_178$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd178 && + (nextAddrPred_updateEn$wget[138:131] == 8'd178 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd178 && + nextAddrPred_updateEn$wget[138:131] == 8'd178 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_179 assign nextAddrPred_valid_179$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd179 && + nextAddrPred_updateEn$wget[138:131] == 8'd179 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_179$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd179 && + (nextAddrPred_updateEn$wget[138:131] == 8'd179 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd179 && + nextAddrPred_updateEn$wget[138:131] == 8'd179 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_18 assign nextAddrPred_valid_18$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd18 && + nextAddrPred_updateEn$wget[138:131] == 8'd18 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_18$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd18 && + (nextAddrPred_updateEn$wget[138:131] == 8'd18 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd18 && + nextAddrPred_updateEn$wget[138:131] == 8'd18 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_180 assign nextAddrPred_valid_180$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd180 && + nextAddrPred_updateEn$wget[138:131] == 8'd180 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_180$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd180 && + (nextAddrPred_updateEn$wget[138:131] == 8'd180 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd180 && + nextAddrPred_updateEn$wget[138:131] == 8'd180 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_181 assign nextAddrPred_valid_181$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd181 && + nextAddrPred_updateEn$wget[138:131] == 8'd181 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_181$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd181 && + (nextAddrPred_updateEn$wget[138:131] == 8'd181 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd181 && + nextAddrPred_updateEn$wget[138:131] == 8'd181 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_182 assign nextAddrPred_valid_182$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd182 && + nextAddrPred_updateEn$wget[138:131] == 8'd182 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_182$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd182 && + (nextAddrPred_updateEn$wget[138:131] == 8'd182 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd182 && + nextAddrPred_updateEn$wget[138:131] == 8'd182 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_183 assign nextAddrPred_valid_183$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd183 && + nextAddrPred_updateEn$wget[138:131] == 8'd183 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_183$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd183 && + (nextAddrPred_updateEn$wget[138:131] == 8'd183 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd183 && + nextAddrPred_updateEn$wget[138:131] == 8'd183 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_184 assign nextAddrPred_valid_184$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd184 && + nextAddrPred_updateEn$wget[138:131] == 8'd184 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_184$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd184 && + (nextAddrPred_updateEn$wget[138:131] == 8'd184 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd184 && + nextAddrPred_updateEn$wget[138:131] == 8'd184 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_185 assign nextAddrPred_valid_185$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd185 && + nextAddrPred_updateEn$wget[138:131] == 8'd185 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_185$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd185 && + (nextAddrPred_updateEn$wget[138:131] == 8'd185 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd185 && + nextAddrPred_updateEn$wget[138:131] == 8'd185 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_186 assign nextAddrPred_valid_186$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd186 && + nextAddrPred_updateEn$wget[138:131] == 8'd186 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_186$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd186 && + (nextAddrPred_updateEn$wget[138:131] == 8'd186 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd186 && + nextAddrPred_updateEn$wget[138:131] == 8'd186 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_187 assign nextAddrPred_valid_187$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd187 && + nextAddrPred_updateEn$wget[138:131] == 8'd187 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_187$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd187 && + (nextAddrPred_updateEn$wget[138:131] == 8'd187 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd187 && + nextAddrPred_updateEn$wget[138:131] == 8'd187 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_188 assign nextAddrPred_valid_188$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd188 && + nextAddrPred_updateEn$wget[138:131] == 8'd188 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_188$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd188 && + (nextAddrPred_updateEn$wget[138:131] == 8'd188 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd188 && + nextAddrPred_updateEn$wget[138:131] == 8'd188 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_189 assign nextAddrPred_valid_189$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd189 && + nextAddrPred_updateEn$wget[138:131] == 8'd189 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_189$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd189 && + (nextAddrPred_updateEn$wget[138:131] == 8'd189 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd189 && + nextAddrPred_updateEn$wget[138:131] == 8'd189 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_19 assign nextAddrPred_valid_19$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd19 && + nextAddrPred_updateEn$wget[138:131] == 8'd19 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_19$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd19 && + (nextAddrPred_updateEn$wget[138:131] == 8'd19 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd19 && + nextAddrPred_updateEn$wget[138:131] == 8'd19 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_190 assign nextAddrPred_valid_190$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd190 && + nextAddrPred_updateEn$wget[138:131] == 8'd190 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_190$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd190 && + (nextAddrPred_updateEn$wget[138:131] == 8'd190 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd190 && + nextAddrPred_updateEn$wget[138:131] == 8'd190 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_191 assign nextAddrPred_valid_191$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd191 && + nextAddrPred_updateEn$wget[138:131] == 8'd191 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_191$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd191 && + (nextAddrPred_updateEn$wget[138:131] == 8'd191 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd191 && + nextAddrPred_updateEn$wget[138:131] == 8'd191 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_192 assign nextAddrPred_valid_192$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd192 && + nextAddrPred_updateEn$wget[138:131] == 8'd192 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_192$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd192 && + (nextAddrPred_updateEn$wget[138:131] == 8'd192 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd192 && + nextAddrPred_updateEn$wget[138:131] == 8'd192 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_193 assign nextAddrPred_valid_193$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd193 && + nextAddrPred_updateEn$wget[138:131] == 8'd193 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_193$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd193 && + (nextAddrPred_updateEn$wget[138:131] == 8'd193 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd193 && + nextAddrPred_updateEn$wget[138:131] == 8'd193 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_194 assign nextAddrPred_valid_194$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd194 && + nextAddrPred_updateEn$wget[138:131] == 8'd194 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_194$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd194 && + (nextAddrPred_updateEn$wget[138:131] == 8'd194 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd194 && + nextAddrPred_updateEn$wget[138:131] == 8'd194 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_195 assign nextAddrPred_valid_195$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd195 && + nextAddrPred_updateEn$wget[138:131] == 8'd195 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_195$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd195 && + (nextAddrPred_updateEn$wget[138:131] == 8'd195 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd195 && + nextAddrPred_updateEn$wget[138:131] == 8'd195 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_196 assign nextAddrPred_valid_196$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd196 && + nextAddrPred_updateEn$wget[138:131] == 8'd196 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_196$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd196 && + (nextAddrPred_updateEn$wget[138:131] == 8'd196 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd196 && + nextAddrPred_updateEn$wget[138:131] == 8'd196 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_197 assign nextAddrPred_valid_197$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd197 && + nextAddrPred_updateEn$wget[138:131] == 8'd197 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_197$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd197 && + (nextAddrPred_updateEn$wget[138:131] == 8'd197 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd197 && + nextAddrPred_updateEn$wget[138:131] == 8'd197 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_198 assign nextAddrPred_valid_198$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd198 && + nextAddrPred_updateEn$wget[138:131] == 8'd198 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_198$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd198 && + (nextAddrPred_updateEn$wget[138:131] == 8'd198 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd198 && + nextAddrPred_updateEn$wget[138:131] == 8'd198 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_199 assign nextAddrPred_valid_199$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd199 && + nextAddrPred_updateEn$wget[138:131] == 8'd199 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_199$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd199 && + (nextAddrPred_updateEn$wget[138:131] == 8'd199 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd199 && + nextAddrPred_updateEn$wget[138:131] == 8'd199 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_2 assign nextAddrPred_valid_2$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd2 && + nextAddrPred_updateEn$wget[138:131] == 8'd2 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_2$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd2 && + (nextAddrPred_updateEn$wget[138:131] == 8'd2 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd2 && + nextAddrPred_updateEn$wget[138:131] == 8'd2 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_20 assign nextAddrPred_valid_20$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd20 && + nextAddrPred_updateEn$wget[138:131] == 8'd20 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_20$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd20 && + (nextAddrPred_updateEn$wget[138:131] == 8'd20 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd20 && + nextAddrPred_updateEn$wget[138:131] == 8'd20 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_200 assign nextAddrPred_valid_200$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd200 && + nextAddrPred_updateEn$wget[138:131] == 8'd200 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_200$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd200 && + (nextAddrPred_updateEn$wget[138:131] == 8'd200 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd200 && + nextAddrPred_updateEn$wget[138:131] == 8'd200 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_201 assign nextAddrPred_valid_201$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd201 && + nextAddrPred_updateEn$wget[138:131] == 8'd201 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_201$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd201 && + (nextAddrPred_updateEn$wget[138:131] == 8'd201 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd201 && + nextAddrPred_updateEn$wget[138:131] == 8'd201 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_202 assign nextAddrPred_valid_202$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd202 && + nextAddrPred_updateEn$wget[138:131] == 8'd202 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_202$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd202 && + (nextAddrPred_updateEn$wget[138:131] == 8'd202 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd202 && + nextAddrPred_updateEn$wget[138:131] == 8'd202 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_203 assign nextAddrPred_valid_203$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd203 && + nextAddrPred_updateEn$wget[138:131] == 8'd203 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_203$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd203 && + (nextAddrPred_updateEn$wget[138:131] == 8'd203 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd203 && + nextAddrPred_updateEn$wget[138:131] == 8'd203 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_204 assign nextAddrPred_valid_204$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd204 && + nextAddrPred_updateEn$wget[138:131] == 8'd204 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_204$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd204 && + (nextAddrPred_updateEn$wget[138:131] == 8'd204 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd204 && + nextAddrPred_updateEn$wget[138:131] == 8'd204 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_205 assign nextAddrPred_valid_205$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd205 && + nextAddrPred_updateEn$wget[138:131] == 8'd205 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_205$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd205 && + (nextAddrPred_updateEn$wget[138:131] == 8'd205 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd205 && + nextAddrPred_updateEn$wget[138:131] == 8'd205 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_206 assign nextAddrPred_valid_206$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd206 && + nextAddrPred_updateEn$wget[138:131] == 8'd206 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_206$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd206 && + (nextAddrPred_updateEn$wget[138:131] == 8'd206 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd206 && + nextAddrPred_updateEn$wget[138:131] == 8'd206 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_207 assign nextAddrPred_valid_207$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd207 && + nextAddrPred_updateEn$wget[138:131] == 8'd207 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_207$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd207 && + (nextAddrPred_updateEn$wget[138:131] == 8'd207 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd207 && + nextAddrPred_updateEn$wget[138:131] == 8'd207 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_208 assign nextAddrPred_valid_208$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd208 && + nextAddrPred_updateEn$wget[138:131] == 8'd208 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_208$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd208 && + (nextAddrPred_updateEn$wget[138:131] == 8'd208 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd208 && + nextAddrPred_updateEn$wget[138:131] == 8'd208 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_209 assign nextAddrPred_valid_209$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd209 && + nextAddrPred_updateEn$wget[138:131] == 8'd209 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_209$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd209 && + (nextAddrPred_updateEn$wget[138:131] == 8'd209 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd209 && + nextAddrPred_updateEn$wget[138:131] == 8'd209 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_21 assign nextAddrPred_valid_21$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd21 && + nextAddrPred_updateEn$wget[138:131] == 8'd21 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_21$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd21 && + (nextAddrPred_updateEn$wget[138:131] == 8'd21 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd21 && + nextAddrPred_updateEn$wget[138:131] == 8'd21 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_210 assign nextAddrPred_valid_210$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd210 && + nextAddrPred_updateEn$wget[138:131] == 8'd210 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_210$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd210 && + (nextAddrPred_updateEn$wget[138:131] == 8'd210 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd210 && + nextAddrPred_updateEn$wget[138:131] == 8'd210 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_211 assign nextAddrPred_valid_211$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd211 && + nextAddrPred_updateEn$wget[138:131] == 8'd211 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_211$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd211 && + (nextAddrPred_updateEn$wget[138:131] == 8'd211 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd211 && + nextAddrPred_updateEn$wget[138:131] == 8'd211 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_212 assign nextAddrPred_valid_212$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd212 && + nextAddrPred_updateEn$wget[138:131] == 8'd212 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_212$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd212 && + (nextAddrPred_updateEn$wget[138:131] == 8'd212 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd212 && + nextAddrPred_updateEn$wget[138:131] == 8'd212 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_213 assign nextAddrPred_valid_213$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd213 && + nextAddrPred_updateEn$wget[138:131] == 8'd213 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_213$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd213 && + (nextAddrPred_updateEn$wget[138:131] == 8'd213 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd213 && + nextAddrPred_updateEn$wget[138:131] == 8'd213 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_214 assign nextAddrPred_valid_214$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd214 && + nextAddrPred_updateEn$wget[138:131] == 8'd214 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_214$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd214 && + (nextAddrPred_updateEn$wget[138:131] == 8'd214 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd214 && + nextAddrPred_updateEn$wget[138:131] == 8'd214 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_215 assign nextAddrPred_valid_215$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd215 && + nextAddrPred_updateEn$wget[138:131] == 8'd215 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_215$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd215 && + (nextAddrPred_updateEn$wget[138:131] == 8'd215 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd215 && + nextAddrPred_updateEn$wget[138:131] == 8'd215 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_216 assign nextAddrPred_valid_216$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd216 && + nextAddrPred_updateEn$wget[138:131] == 8'd216 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_216$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd216 && + (nextAddrPred_updateEn$wget[138:131] == 8'd216 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd216 && + nextAddrPred_updateEn$wget[138:131] == 8'd216 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_217 assign nextAddrPred_valid_217$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd217 && + nextAddrPred_updateEn$wget[138:131] == 8'd217 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_217$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd217 && + (nextAddrPred_updateEn$wget[138:131] == 8'd217 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd217 && + nextAddrPred_updateEn$wget[138:131] == 8'd217 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_218 assign nextAddrPred_valid_218$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd218 && + nextAddrPred_updateEn$wget[138:131] == 8'd218 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_218$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd218 && + (nextAddrPred_updateEn$wget[138:131] == 8'd218 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd218 && + nextAddrPred_updateEn$wget[138:131] == 8'd218 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_219 assign nextAddrPred_valid_219$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd219 && + nextAddrPred_updateEn$wget[138:131] == 8'd219 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_219$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd219 && + (nextAddrPred_updateEn$wget[138:131] == 8'd219 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd219 && + nextAddrPred_updateEn$wget[138:131] == 8'd219 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_22 assign nextAddrPred_valid_22$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd22 && + nextAddrPred_updateEn$wget[138:131] == 8'd22 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_22$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd22 && + (nextAddrPred_updateEn$wget[138:131] == 8'd22 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd22 && + nextAddrPred_updateEn$wget[138:131] == 8'd22 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_220 assign nextAddrPred_valid_220$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd220 && + nextAddrPred_updateEn$wget[138:131] == 8'd220 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_220$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd220 && + (nextAddrPred_updateEn$wget[138:131] == 8'd220 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd220 && + nextAddrPred_updateEn$wget[138:131] == 8'd220 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_221 assign nextAddrPred_valid_221$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd221 && + nextAddrPred_updateEn$wget[138:131] == 8'd221 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_221$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd221 && + (nextAddrPred_updateEn$wget[138:131] == 8'd221 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd221 && + nextAddrPred_updateEn$wget[138:131] == 8'd221 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_222 assign nextAddrPred_valid_222$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd222 && + nextAddrPred_updateEn$wget[138:131] == 8'd222 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_222$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd222 && + (nextAddrPred_updateEn$wget[138:131] == 8'd222 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd222 && + nextAddrPred_updateEn$wget[138:131] == 8'd222 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_223 assign nextAddrPred_valid_223$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd223 && + nextAddrPred_updateEn$wget[138:131] == 8'd223 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_223$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd223 && + (nextAddrPred_updateEn$wget[138:131] == 8'd223 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd223 && + nextAddrPred_updateEn$wget[138:131] == 8'd223 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_224 assign nextAddrPred_valid_224$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd224 && + nextAddrPred_updateEn$wget[138:131] == 8'd224 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_224$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd224 && + (nextAddrPred_updateEn$wget[138:131] == 8'd224 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd224 && + nextAddrPred_updateEn$wget[138:131] == 8'd224 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_225 assign nextAddrPred_valid_225$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd225 && + nextAddrPred_updateEn$wget[138:131] == 8'd225 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_225$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd225 && + (nextAddrPred_updateEn$wget[138:131] == 8'd225 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd225 && + nextAddrPred_updateEn$wget[138:131] == 8'd225 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_226 assign nextAddrPred_valid_226$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd226 && + nextAddrPred_updateEn$wget[138:131] == 8'd226 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_226$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd226 && + (nextAddrPred_updateEn$wget[138:131] == 8'd226 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd226 && + nextAddrPred_updateEn$wget[138:131] == 8'd226 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_227 assign nextAddrPred_valid_227$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd227 && + nextAddrPred_updateEn$wget[138:131] == 8'd227 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_227$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd227 && + (nextAddrPred_updateEn$wget[138:131] == 8'd227 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd227 && + nextAddrPred_updateEn$wget[138:131] == 8'd227 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_228 assign nextAddrPred_valid_228$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd228 && + nextAddrPred_updateEn$wget[138:131] == 8'd228 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_228$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd228 && + (nextAddrPred_updateEn$wget[138:131] == 8'd228 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd228 && + nextAddrPred_updateEn$wget[138:131] == 8'd228 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_229 assign nextAddrPred_valid_229$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd229 && + nextAddrPred_updateEn$wget[138:131] == 8'd229 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_229$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd229 && + (nextAddrPred_updateEn$wget[138:131] == 8'd229 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd229 && + nextAddrPred_updateEn$wget[138:131] == 8'd229 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_23 assign nextAddrPred_valid_23$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd23 && + nextAddrPred_updateEn$wget[138:131] == 8'd23 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_23$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd23 && + (nextAddrPred_updateEn$wget[138:131] == 8'd23 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd23 && + nextAddrPred_updateEn$wget[138:131] == 8'd23 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_230 assign nextAddrPred_valid_230$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd230 && + nextAddrPred_updateEn$wget[138:131] == 8'd230 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_230$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd230 && + (nextAddrPred_updateEn$wget[138:131] == 8'd230 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd230 && + nextAddrPred_updateEn$wget[138:131] == 8'd230 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_231 assign nextAddrPred_valid_231$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd231 && + nextAddrPred_updateEn$wget[138:131] == 8'd231 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_231$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd231 && + (nextAddrPred_updateEn$wget[138:131] == 8'd231 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd231 && + nextAddrPred_updateEn$wget[138:131] == 8'd231 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_232 assign nextAddrPred_valid_232$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd232 && + nextAddrPred_updateEn$wget[138:131] == 8'd232 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_232$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd232 && + (nextAddrPred_updateEn$wget[138:131] == 8'd232 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd232 && + nextAddrPred_updateEn$wget[138:131] == 8'd232 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_233 assign nextAddrPred_valid_233$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd233 && + nextAddrPred_updateEn$wget[138:131] == 8'd233 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_233$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd233 && + (nextAddrPred_updateEn$wget[138:131] == 8'd233 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd233 && + nextAddrPred_updateEn$wget[138:131] == 8'd233 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_234 assign nextAddrPred_valid_234$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd234 && + nextAddrPred_updateEn$wget[138:131] == 8'd234 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_234$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd234 && + (nextAddrPred_updateEn$wget[138:131] == 8'd234 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd234 && + nextAddrPred_updateEn$wget[138:131] == 8'd234 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_235 assign nextAddrPred_valid_235$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd235 && + nextAddrPred_updateEn$wget[138:131] == 8'd235 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_235$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd235 && + (nextAddrPred_updateEn$wget[138:131] == 8'd235 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd235 && + nextAddrPred_updateEn$wget[138:131] == 8'd235 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_236 assign nextAddrPred_valid_236$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd236 && + nextAddrPred_updateEn$wget[138:131] == 8'd236 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_236$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd236 && + (nextAddrPred_updateEn$wget[138:131] == 8'd236 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd236 && + nextAddrPred_updateEn$wget[138:131] == 8'd236 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_237 assign nextAddrPred_valid_237$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd237 && + nextAddrPred_updateEn$wget[138:131] == 8'd237 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_237$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd237 && + (nextAddrPred_updateEn$wget[138:131] == 8'd237 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd237 && + nextAddrPred_updateEn$wget[138:131] == 8'd237 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_238 assign nextAddrPred_valid_238$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd238 && + nextAddrPred_updateEn$wget[138:131] == 8'd238 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_238$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd238 && + (nextAddrPred_updateEn$wget[138:131] == 8'd238 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd238 && + nextAddrPred_updateEn$wget[138:131] == 8'd238 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_239 assign nextAddrPred_valid_239$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd239 && + nextAddrPred_updateEn$wget[138:131] == 8'd239 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_239$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd239 && + (nextAddrPred_updateEn$wget[138:131] == 8'd239 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd239 && + nextAddrPred_updateEn$wget[138:131] == 8'd239 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_24 assign nextAddrPred_valid_24$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd24 && + nextAddrPred_updateEn$wget[138:131] == 8'd24 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_24$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd24 && + (nextAddrPred_updateEn$wget[138:131] == 8'd24 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd24 && + nextAddrPred_updateEn$wget[138:131] == 8'd24 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_240 assign nextAddrPred_valid_240$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd240 && + nextAddrPred_updateEn$wget[138:131] == 8'd240 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_240$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd240 && + (nextAddrPred_updateEn$wget[138:131] == 8'd240 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd240 && + nextAddrPred_updateEn$wget[138:131] == 8'd240 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_241 assign nextAddrPred_valid_241$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd241 && + nextAddrPred_updateEn$wget[138:131] == 8'd241 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_241$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd241 && + (nextAddrPred_updateEn$wget[138:131] == 8'd241 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd241 && + nextAddrPred_updateEn$wget[138:131] == 8'd241 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_242 assign nextAddrPred_valid_242$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd242 && + nextAddrPred_updateEn$wget[138:131] == 8'd242 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_242$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd242 && + (nextAddrPred_updateEn$wget[138:131] == 8'd242 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd242 && + nextAddrPred_updateEn$wget[138:131] == 8'd242 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_243 assign nextAddrPred_valid_243$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd243 && + nextAddrPred_updateEn$wget[138:131] == 8'd243 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_243$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd243 && + (nextAddrPred_updateEn$wget[138:131] == 8'd243 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd243 && + nextAddrPred_updateEn$wget[138:131] == 8'd243 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_244 assign nextAddrPred_valid_244$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd244 && + nextAddrPred_updateEn$wget[138:131] == 8'd244 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_244$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd244 && + (nextAddrPred_updateEn$wget[138:131] == 8'd244 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd244 && + nextAddrPred_updateEn$wget[138:131] == 8'd244 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_245 assign nextAddrPred_valid_245$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd245 && + nextAddrPred_updateEn$wget[138:131] == 8'd245 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_245$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd245 && + (nextAddrPred_updateEn$wget[138:131] == 8'd245 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd245 && + nextAddrPred_updateEn$wget[138:131] == 8'd245 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_246 assign nextAddrPred_valid_246$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd246 && + nextAddrPred_updateEn$wget[138:131] == 8'd246 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_246$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd246 && + (nextAddrPred_updateEn$wget[138:131] == 8'd246 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd246 && + nextAddrPred_updateEn$wget[138:131] == 8'd246 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_247 assign nextAddrPred_valid_247$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd247 && + nextAddrPred_updateEn$wget[138:131] == 8'd247 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_247$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd247 && + (nextAddrPred_updateEn$wget[138:131] == 8'd247 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd247 && + nextAddrPred_updateEn$wget[138:131] == 8'd247 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_248 assign nextAddrPred_valid_248$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd248 && + nextAddrPred_updateEn$wget[138:131] == 8'd248 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_248$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd248 && + (nextAddrPred_updateEn$wget[138:131] == 8'd248 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd248 && + nextAddrPred_updateEn$wget[138:131] == 8'd248 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_249 assign nextAddrPred_valid_249$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd249 && + nextAddrPred_updateEn$wget[138:131] == 8'd249 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_249$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd249 && + (nextAddrPred_updateEn$wget[138:131] == 8'd249 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd249 && + nextAddrPred_updateEn$wget[138:131] == 8'd249 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_25 assign nextAddrPred_valid_25$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd25 && + nextAddrPred_updateEn$wget[138:131] == 8'd25 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_25$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd25 && + (nextAddrPred_updateEn$wget[138:131] == 8'd25 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd25 && + nextAddrPred_updateEn$wget[138:131] == 8'd25 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_250 assign nextAddrPred_valid_250$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd250 && + nextAddrPred_updateEn$wget[138:131] == 8'd250 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_250$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd250 && + (nextAddrPred_updateEn$wget[138:131] == 8'd250 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd250 && + nextAddrPred_updateEn$wget[138:131] == 8'd250 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_251 assign nextAddrPred_valid_251$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd251 && + nextAddrPred_updateEn$wget[138:131] == 8'd251 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_251$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd251 && + (nextAddrPred_updateEn$wget[138:131] == 8'd251 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd251 && + nextAddrPred_updateEn$wget[138:131] == 8'd251 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_252 assign nextAddrPred_valid_252$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd252 && + nextAddrPred_updateEn$wget[138:131] == 8'd252 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_252$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd252 && + (nextAddrPred_updateEn$wget[138:131] == 8'd252 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd252 && + nextAddrPred_updateEn$wget[138:131] == 8'd252 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_253 assign nextAddrPred_valid_253$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd253 && + nextAddrPred_updateEn$wget[138:131] == 8'd253 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_253$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd253 && + (nextAddrPred_updateEn$wget[138:131] == 8'd253 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd253 && + nextAddrPred_updateEn$wget[138:131] == 8'd253 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_254 assign nextAddrPred_valid_254$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd254 && + nextAddrPred_updateEn$wget[138:131] == 8'd254 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_254$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd254 && + (nextAddrPred_updateEn$wget[138:131] == 8'd254 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd254 && + nextAddrPred_updateEn$wget[138:131] == 8'd254 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_255 assign nextAddrPred_valid_255$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd255 && + nextAddrPred_updateEn$wget[138:131] == 8'd255 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_255$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd255 && + (nextAddrPred_updateEn$wget[138:131] == 8'd255 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd255 && + nextAddrPred_updateEn$wget[138:131] == 8'd255 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_26 assign nextAddrPred_valid_26$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd26 && + nextAddrPred_updateEn$wget[138:131] == 8'd26 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_26$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd26 && + (nextAddrPred_updateEn$wget[138:131] == 8'd26 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd26 && + nextAddrPred_updateEn$wget[138:131] == 8'd26 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_27 assign nextAddrPred_valid_27$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd27 && + nextAddrPred_updateEn$wget[138:131] == 8'd27 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_27$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd27 && + (nextAddrPred_updateEn$wget[138:131] == 8'd27 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd27 && + nextAddrPred_updateEn$wget[138:131] == 8'd27 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_28 assign nextAddrPred_valid_28$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd28 && + nextAddrPred_updateEn$wget[138:131] == 8'd28 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_28$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd28 && + (nextAddrPred_updateEn$wget[138:131] == 8'd28 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd28 && + nextAddrPred_updateEn$wget[138:131] == 8'd28 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_29 assign nextAddrPred_valid_29$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd29 && + nextAddrPred_updateEn$wget[138:131] == 8'd29 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_29$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd29 && + (nextAddrPred_updateEn$wget[138:131] == 8'd29 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd29 && + nextAddrPred_updateEn$wget[138:131] == 8'd29 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_3 assign nextAddrPred_valid_3$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd3 && + nextAddrPred_updateEn$wget[138:131] == 8'd3 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_3$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd3 && + (nextAddrPred_updateEn$wget[138:131] == 8'd3 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd3 && + nextAddrPred_updateEn$wget[138:131] == 8'd3 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_30 assign nextAddrPred_valid_30$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd30 && + nextAddrPred_updateEn$wget[138:131] == 8'd30 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_30$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd30 && + (nextAddrPred_updateEn$wget[138:131] == 8'd30 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd30 && + nextAddrPred_updateEn$wget[138:131] == 8'd30 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_31 assign nextAddrPred_valid_31$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd31 && + nextAddrPred_updateEn$wget[138:131] == 8'd31 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_31$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd31 && + (nextAddrPred_updateEn$wget[138:131] == 8'd31 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd31 && + nextAddrPred_updateEn$wget[138:131] == 8'd31 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_32 assign nextAddrPred_valid_32$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd32 && + nextAddrPred_updateEn$wget[138:131] == 8'd32 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_32$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd32 && + (nextAddrPred_updateEn$wget[138:131] == 8'd32 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd32 && + nextAddrPred_updateEn$wget[138:131] == 8'd32 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_33 assign nextAddrPred_valid_33$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd33 && + nextAddrPred_updateEn$wget[138:131] == 8'd33 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_33$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd33 && + (nextAddrPred_updateEn$wget[138:131] == 8'd33 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd33 && + nextAddrPred_updateEn$wget[138:131] == 8'd33 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_34 assign nextAddrPred_valid_34$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd34 && + nextAddrPred_updateEn$wget[138:131] == 8'd34 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_34$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd34 && + (nextAddrPred_updateEn$wget[138:131] == 8'd34 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd34 && + nextAddrPred_updateEn$wget[138:131] == 8'd34 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_35 assign nextAddrPred_valid_35$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd35 && + nextAddrPred_updateEn$wget[138:131] == 8'd35 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_35$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd35 && + (nextAddrPred_updateEn$wget[138:131] == 8'd35 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd35 && + nextAddrPred_updateEn$wget[138:131] == 8'd35 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_36 assign nextAddrPred_valid_36$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd36 && + nextAddrPred_updateEn$wget[138:131] == 8'd36 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_36$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd36 && + (nextAddrPred_updateEn$wget[138:131] == 8'd36 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd36 && + nextAddrPred_updateEn$wget[138:131] == 8'd36 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_37 assign nextAddrPred_valid_37$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd37 && + nextAddrPred_updateEn$wget[138:131] == 8'd37 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_37$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd37 && + (nextAddrPred_updateEn$wget[138:131] == 8'd37 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd37 && + nextAddrPred_updateEn$wget[138:131] == 8'd37 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_38 assign nextAddrPred_valid_38$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd38 && + nextAddrPred_updateEn$wget[138:131] == 8'd38 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_38$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd38 && + (nextAddrPred_updateEn$wget[138:131] == 8'd38 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd38 && + nextAddrPred_updateEn$wget[138:131] == 8'd38 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_39 assign nextAddrPred_valid_39$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd39 && + nextAddrPred_updateEn$wget[138:131] == 8'd39 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_39$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd39 && + (nextAddrPred_updateEn$wget[138:131] == 8'd39 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd39 && + nextAddrPred_updateEn$wget[138:131] == 8'd39 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_4 assign nextAddrPred_valid_4$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd4 && + nextAddrPred_updateEn$wget[138:131] == 8'd4 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_4$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd4 && + (nextAddrPred_updateEn$wget[138:131] == 8'd4 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd4 && + nextAddrPred_updateEn$wget[138:131] == 8'd4 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_40 assign nextAddrPred_valid_40$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd40 && + nextAddrPred_updateEn$wget[138:131] == 8'd40 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_40$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd40 && + (nextAddrPred_updateEn$wget[138:131] == 8'd40 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd40 && + nextAddrPred_updateEn$wget[138:131] == 8'd40 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_41 assign nextAddrPred_valid_41$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd41 && + nextAddrPred_updateEn$wget[138:131] == 8'd41 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_41$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd41 && + (nextAddrPred_updateEn$wget[138:131] == 8'd41 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd41 && + nextAddrPred_updateEn$wget[138:131] == 8'd41 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_42 assign nextAddrPred_valid_42$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd42 && + nextAddrPred_updateEn$wget[138:131] == 8'd42 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_42$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd42 && + (nextAddrPred_updateEn$wget[138:131] == 8'd42 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd42 && + nextAddrPred_updateEn$wget[138:131] == 8'd42 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_43 assign nextAddrPred_valid_43$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd43 && + nextAddrPred_updateEn$wget[138:131] == 8'd43 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_43$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd43 && + (nextAddrPred_updateEn$wget[138:131] == 8'd43 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd43 && + nextAddrPred_updateEn$wget[138:131] == 8'd43 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_44 assign nextAddrPred_valid_44$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd44 && + nextAddrPred_updateEn$wget[138:131] == 8'd44 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_44$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd44 && + (nextAddrPred_updateEn$wget[138:131] == 8'd44 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd44 && + nextAddrPred_updateEn$wget[138:131] == 8'd44 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_45 assign nextAddrPred_valid_45$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd45 && + nextAddrPred_updateEn$wget[138:131] == 8'd45 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_45$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd45 && + (nextAddrPred_updateEn$wget[138:131] == 8'd45 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd45 && + nextAddrPred_updateEn$wget[138:131] == 8'd45 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_46 assign nextAddrPred_valid_46$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd46 && + nextAddrPred_updateEn$wget[138:131] == 8'd46 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_46$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd46 && + (nextAddrPred_updateEn$wget[138:131] == 8'd46 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd46 && + nextAddrPred_updateEn$wget[138:131] == 8'd46 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_47 assign nextAddrPred_valid_47$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd47 && + nextAddrPred_updateEn$wget[138:131] == 8'd47 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_47$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd47 && + (nextAddrPred_updateEn$wget[138:131] == 8'd47 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd47 && + nextAddrPred_updateEn$wget[138:131] == 8'd47 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_48 assign nextAddrPred_valid_48$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd48 && + nextAddrPred_updateEn$wget[138:131] == 8'd48 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_48$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd48 && + (nextAddrPred_updateEn$wget[138:131] == 8'd48 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd48 && + nextAddrPred_updateEn$wget[138:131] == 8'd48 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_49 assign nextAddrPred_valid_49$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd49 && + nextAddrPred_updateEn$wget[138:131] == 8'd49 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_49$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd49 && + (nextAddrPred_updateEn$wget[138:131] == 8'd49 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd49 && + nextAddrPred_updateEn$wget[138:131] == 8'd49 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_5 assign nextAddrPred_valid_5$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd5 && + nextAddrPred_updateEn$wget[138:131] == 8'd5 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_5$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd5 && + (nextAddrPred_updateEn$wget[138:131] == 8'd5 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd5 && + nextAddrPred_updateEn$wget[138:131] == 8'd5 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_50 assign nextAddrPred_valid_50$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd50 && + nextAddrPred_updateEn$wget[138:131] == 8'd50 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_50$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd50 && + (nextAddrPred_updateEn$wget[138:131] == 8'd50 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd50 && + nextAddrPred_updateEn$wget[138:131] == 8'd50 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_51 assign nextAddrPred_valid_51$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd51 && + nextAddrPred_updateEn$wget[138:131] == 8'd51 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_51$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd51 && + (nextAddrPred_updateEn$wget[138:131] == 8'd51 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd51 && + nextAddrPred_updateEn$wget[138:131] == 8'd51 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_52 assign nextAddrPred_valid_52$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd52 && + nextAddrPred_updateEn$wget[138:131] == 8'd52 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_52$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd52 && + (nextAddrPred_updateEn$wget[138:131] == 8'd52 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd52 && + nextAddrPred_updateEn$wget[138:131] == 8'd52 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_53 assign nextAddrPred_valid_53$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd53 && + nextAddrPred_updateEn$wget[138:131] == 8'd53 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_53$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd53 && + (nextAddrPred_updateEn$wget[138:131] == 8'd53 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd53 && + nextAddrPred_updateEn$wget[138:131] == 8'd53 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_54 assign nextAddrPred_valid_54$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd54 && + nextAddrPred_updateEn$wget[138:131] == 8'd54 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_54$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd54 && + (nextAddrPred_updateEn$wget[138:131] == 8'd54 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd54 && + nextAddrPred_updateEn$wget[138:131] == 8'd54 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_55 assign nextAddrPred_valid_55$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd55 && + nextAddrPred_updateEn$wget[138:131] == 8'd55 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_55$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd55 && + (nextAddrPred_updateEn$wget[138:131] == 8'd55 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd55 && + nextAddrPred_updateEn$wget[138:131] == 8'd55 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_56 assign nextAddrPred_valid_56$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd56 && + nextAddrPred_updateEn$wget[138:131] == 8'd56 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_56$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd56 && + (nextAddrPred_updateEn$wget[138:131] == 8'd56 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd56 && + nextAddrPred_updateEn$wget[138:131] == 8'd56 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_57 assign nextAddrPred_valid_57$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd57 && + nextAddrPred_updateEn$wget[138:131] == 8'd57 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_57$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd57 && + (nextAddrPred_updateEn$wget[138:131] == 8'd57 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd57 && + nextAddrPred_updateEn$wget[138:131] == 8'd57 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_58 assign nextAddrPred_valid_58$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd58 && + nextAddrPred_updateEn$wget[138:131] == 8'd58 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_58$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd58 && + (nextAddrPred_updateEn$wget[138:131] == 8'd58 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd58 && + nextAddrPred_updateEn$wget[138:131] == 8'd58 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_59 assign nextAddrPred_valid_59$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd59 && + nextAddrPred_updateEn$wget[138:131] == 8'd59 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_59$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd59 && + (nextAddrPred_updateEn$wget[138:131] == 8'd59 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd59 && + nextAddrPred_updateEn$wget[138:131] == 8'd59 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_6 assign nextAddrPred_valid_6$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd6 && + nextAddrPred_updateEn$wget[138:131] == 8'd6 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_6$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd6 && + (nextAddrPred_updateEn$wget[138:131] == 8'd6 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd6 && + nextAddrPred_updateEn$wget[138:131] == 8'd6 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_60 assign nextAddrPred_valid_60$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd60 && + nextAddrPred_updateEn$wget[138:131] == 8'd60 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_60$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd60 && + (nextAddrPred_updateEn$wget[138:131] == 8'd60 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd60 && + nextAddrPred_updateEn$wget[138:131] == 8'd60 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_61 assign nextAddrPred_valid_61$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd61 && + nextAddrPred_updateEn$wget[138:131] == 8'd61 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_61$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd61 && + (nextAddrPred_updateEn$wget[138:131] == 8'd61 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd61 && + nextAddrPred_updateEn$wget[138:131] == 8'd61 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_62 assign nextAddrPred_valid_62$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd62 && + nextAddrPred_updateEn$wget[138:131] == 8'd62 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_62$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd62 && + (nextAddrPred_updateEn$wget[138:131] == 8'd62 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd62 && + nextAddrPred_updateEn$wget[138:131] == 8'd62 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_63 assign nextAddrPred_valid_63$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd63 && + nextAddrPred_updateEn$wget[138:131] == 8'd63 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_63$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd63 && + (nextAddrPred_updateEn$wget[138:131] == 8'd63 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd63 && + nextAddrPred_updateEn$wget[138:131] == 8'd63 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_64 assign nextAddrPred_valid_64$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd64 && + nextAddrPred_updateEn$wget[138:131] == 8'd64 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_64$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd64 && + (nextAddrPred_updateEn$wget[138:131] == 8'd64 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd64 && + nextAddrPred_updateEn$wget[138:131] == 8'd64 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_65 assign nextAddrPred_valid_65$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd65 && + nextAddrPred_updateEn$wget[138:131] == 8'd65 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_65$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd65 && + (nextAddrPred_updateEn$wget[138:131] == 8'd65 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd65 && + nextAddrPred_updateEn$wget[138:131] == 8'd65 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_66 assign nextAddrPred_valid_66$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd66 && + nextAddrPred_updateEn$wget[138:131] == 8'd66 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_66$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd66 && + (nextAddrPred_updateEn$wget[138:131] == 8'd66 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd66 && + nextAddrPred_updateEn$wget[138:131] == 8'd66 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_67 assign nextAddrPred_valid_67$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd67 && + nextAddrPred_updateEn$wget[138:131] == 8'd67 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_67$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd67 && + (nextAddrPred_updateEn$wget[138:131] == 8'd67 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd67 && + nextAddrPred_updateEn$wget[138:131] == 8'd67 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_68 assign nextAddrPred_valid_68$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd68 && + nextAddrPred_updateEn$wget[138:131] == 8'd68 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_68$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd68 && + (nextAddrPred_updateEn$wget[138:131] == 8'd68 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd68 && + nextAddrPred_updateEn$wget[138:131] == 8'd68 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_69 assign nextAddrPred_valid_69$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd69 && + nextAddrPred_updateEn$wget[138:131] == 8'd69 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_69$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd69 && + (nextAddrPred_updateEn$wget[138:131] == 8'd69 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd69 && + nextAddrPred_updateEn$wget[138:131] == 8'd69 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_7 assign nextAddrPred_valid_7$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd7 && + nextAddrPred_updateEn$wget[138:131] == 8'd7 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_7$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd7 && + (nextAddrPred_updateEn$wget[138:131] == 8'd7 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd7 && + nextAddrPred_updateEn$wget[138:131] == 8'd7 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_70 assign nextAddrPred_valid_70$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd70 && + nextAddrPred_updateEn$wget[138:131] == 8'd70 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_70$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd70 && + (nextAddrPred_updateEn$wget[138:131] == 8'd70 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd70 && + nextAddrPred_updateEn$wget[138:131] == 8'd70 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_71 assign nextAddrPred_valid_71$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd71 && + nextAddrPred_updateEn$wget[138:131] == 8'd71 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_71$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd71 && + (nextAddrPred_updateEn$wget[138:131] == 8'd71 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd71 && + nextAddrPred_updateEn$wget[138:131] == 8'd71 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_72 assign nextAddrPred_valid_72$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd72 && + nextAddrPred_updateEn$wget[138:131] == 8'd72 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_72$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd72 && + (nextAddrPred_updateEn$wget[138:131] == 8'd72 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd72 && + nextAddrPred_updateEn$wget[138:131] == 8'd72 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_73 assign nextAddrPred_valid_73$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd73 && + nextAddrPred_updateEn$wget[138:131] == 8'd73 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_73$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd73 && + (nextAddrPred_updateEn$wget[138:131] == 8'd73 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd73 && + nextAddrPred_updateEn$wget[138:131] == 8'd73 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_74 assign nextAddrPred_valid_74$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd74 && + nextAddrPred_updateEn$wget[138:131] == 8'd74 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_74$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd74 && + (nextAddrPred_updateEn$wget[138:131] == 8'd74 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd74 && + nextAddrPred_updateEn$wget[138:131] == 8'd74 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_75 assign nextAddrPred_valid_75$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd75 && + nextAddrPred_updateEn$wget[138:131] == 8'd75 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_75$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd75 && + (nextAddrPred_updateEn$wget[138:131] == 8'd75 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd75 && + nextAddrPred_updateEn$wget[138:131] == 8'd75 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_76 assign nextAddrPred_valid_76$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd76 && + nextAddrPred_updateEn$wget[138:131] == 8'd76 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_76$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd76 && + (nextAddrPred_updateEn$wget[138:131] == 8'd76 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd76 && + nextAddrPred_updateEn$wget[138:131] == 8'd76 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_77 assign nextAddrPred_valid_77$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd77 && + nextAddrPred_updateEn$wget[138:131] == 8'd77 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_77$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd77 && + (nextAddrPred_updateEn$wget[138:131] == 8'd77 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd77 && + nextAddrPred_updateEn$wget[138:131] == 8'd77 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_78 assign nextAddrPred_valid_78$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd78 && + nextAddrPred_updateEn$wget[138:131] == 8'd78 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_78$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd78 && + (nextAddrPred_updateEn$wget[138:131] == 8'd78 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd78 && + nextAddrPred_updateEn$wget[138:131] == 8'd78 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_79 assign nextAddrPred_valid_79$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd79 && + nextAddrPred_updateEn$wget[138:131] == 8'd79 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_79$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd79 && + (nextAddrPred_updateEn$wget[138:131] == 8'd79 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd79 && + nextAddrPred_updateEn$wget[138:131] == 8'd79 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_8 assign nextAddrPred_valid_8$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd8 && + nextAddrPred_updateEn$wget[138:131] == 8'd8 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_8$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd8 && + (nextAddrPred_updateEn$wget[138:131] == 8'd8 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd8 && + nextAddrPred_updateEn$wget[138:131] == 8'd8 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_80 assign nextAddrPred_valid_80$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd80 && + nextAddrPred_updateEn$wget[138:131] == 8'd80 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_80$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd80 && + (nextAddrPred_updateEn$wget[138:131] == 8'd80 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd80 && + nextAddrPred_updateEn$wget[138:131] == 8'd80 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_81 assign nextAddrPred_valid_81$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd81 && + nextAddrPred_updateEn$wget[138:131] == 8'd81 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_81$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd81 && + (nextAddrPred_updateEn$wget[138:131] == 8'd81 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd81 && + nextAddrPred_updateEn$wget[138:131] == 8'd81 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_82 assign nextAddrPred_valid_82$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd82 && + nextAddrPred_updateEn$wget[138:131] == 8'd82 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_82$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd82 && + (nextAddrPred_updateEn$wget[138:131] == 8'd82 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd82 && + nextAddrPred_updateEn$wget[138:131] == 8'd82 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_83 assign nextAddrPred_valid_83$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd83 && + nextAddrPred_updateEn$wget[138:131] == 8'd83 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_83$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd83 && + (nextAddrPred_updateEn$wget[138:131] == 8'd83 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd83 && + nextAddrPred_updateEn$wget[138:131] == 8'd83 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_84 assign nextAddrPred_valid_84$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd84 && + nextAddrPred_updateEn$wget[138:131] == 8'd84 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_84$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd84 && + (nextAddrPred_updateEn$wget[138:131] == 8'd84 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd84 && + nextAddrPred_updateEn$wget[138:131] == 8'd84 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_85 assign nextAddrPred_valid_85$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd85 && + nextAddrPred_updateEn$wget[138:131] == 8'd85 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_85$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd85 && + (nextAddrPred_updateEn$wget[138:131] == 8'd85 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd85 && + nextAddrPred_updateEn$wget[138:131] == 8'd85 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_86 assign nextAddrPred_valid_86$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd86 && + nextAddrPred_updateEn$wget[138:131] == 8'd86 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_86$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd86 && + (nextAddrPred_updateEn$wget[138:131] == 8'd86 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd86 && + nextAddrPred_updateEn$wget[138:131] == 8'd86 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_87 assign nextAddrPred_valid_87$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd87 && + nextAddrPred_updateEn$wget[138:131] == 8'd87 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_87$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd87 && + (nextAddrPred_updateEn$wget[138:131] == 8'd87 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd87 && + nextAddrPred_updateEn$wget[138:131] == 8'd87 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_88 assign nextAddrPred_valid_88$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd88 && + nextAddrPred_updateEn$wget[138:131] == 8'd88 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_88$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd88 && + (nextAddrPred_updateEn$wget[138:131] == 8'd88 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd88 && + nextAddrPred_updateEn$wget[138:131] == 8'd88 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_89 assign nextAddrPred_valid_89$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd89 && + nextAddrPred_updateEn$wget[138:131] == 8'd89 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_89$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd89 && + (nextAddrPred_updateEn$wget[138:131] == 8'd89 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd89 && + nextAddrPred_updateEn$wget[138:131] == 8'd89 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_9 assign nextAddrPred_valid_9$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd9 && + nextAddrPred_updateEn$wget[138:131] == 8'd9 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_9$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd9 && + (nextAddrPred_updateEn$wget[138:131] == 8'd9 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd9 && + nextAddrPred_updateEn$wget[138:131] == 8'd9 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_90 assign nextAddrPred_valid_90$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd90 && + nextAddrPred_updateEn$wget[138:131] == 8'd90 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_90$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd90 && + (nextAddrPred_updateEn$wget[138:131] == 8'd90 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd90 && + nextAddrPred_updateEn$wget[138:131] == 8'd90 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_91 assign nextAddrPred_valid_91$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd91 && + nextAddrPred_updateEn$wget[138:131] == 8'd91 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_91$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd91 && + (nextAddrPred_updateEn$wget[138:131] == 8'd91 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd91 && + nextAddrPred_updateEn$wget[138:131] == 8'd91 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_92 assign nextAddrPred_valid_92$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd92 && + nextAddrPred_updateEn$wget[138:131] == 8'd92 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_92$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd92 && + (nextAddrPred_updateEn$wget[138:131] == 8'd92 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd92 && + nextAddrPred_updateEn$wget[138:131] == 8'd92 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_93 assign nextAddrPred_valid_93$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd93 && + nextAddrPred_updateEn$wget[138:131] == 8'd93 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_93$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd93 && + (nextAddrPred_updateEn$wget[138:131] == 8'd93 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd93 && + nextAddrPred_updateEn$wget[138:131] == 8'd93 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_94 assign nextAddrPred_valid_94$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd94 && + nextAddrPred_updateEn$wget[138:131] == 8'd94 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_94$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd94 && + (nextAddrPred_updateEn$wget[138:131] == 8'd94 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd94 && + nextAddrPred_updateEn$wget[138:131] == 8'd94 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_95 assign nextAddrPred_valid_95$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd95 && + nextAddrPred_updateEn$wget[138:131] == 8'd95 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_95$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd95 && + (nextAddrPred_updateEn$wget[138:131] == 8'd95 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd95 && + nextAddrPred_updateEn$wget[138:131] == 8'd95 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_96 assign nextAddrPred_valid_96$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd96 && + nextAddrPred_updateEn$wget[138:131] == 8'd96 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_96$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd96 && + (nextAddrPred_updateEn$wget[138:131] == 8'd96 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd96 && + nextAddrPred_updateEn$wget[138:131] == 8'd96 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_97 assign nextAddrPred_valid_97$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd97 && + nextAddrPred_updateEn$wget[138:131] == 8'd97 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_97$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd97 && + (nextAddrPred_updateEn$wget[138:131] == 8'd97 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd97 && + nextAddrPred_updateEn$wget[138:131] == 8'd97 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_98 assign nextAddrPred_valid_98$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd98 && + nextAddrPred_updateEn$wget[138:131] == 8'd98 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_98$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd98 && + (nextAddrPred_updateEn$wget[138:131] == 8'd98 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd98 && + nextAddrPred_updateEn$wget[138:131] == 8'd98 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register nextAddrPred_valid_99 assign nextAddrPred_valid_99$D_IN = - nextAddrPred_updateEn$wget[74:67] == 8'd99 && + nextAddrPred_updateEn$wget[138:131] == 8'd99 && nextAddrPred_updateEn$wget[0] ; assign nextAddrPred_valid_99$EN = WILL_FIRE_RL_nextAddrPred_canonUpdate && - (nextAddrPred_updateEn$wget[74:67] == 8'd99 && + (nextAddrPred_updateEn$wget[138:131] == 8'd99 && nextAddrPred_updateEn$wget[0] || - nextAddrPred_updateEn$wget[74:67] == 8'd99 && + nextAddrPred_updateEn$wget[138:131] == 8'd99 && !nextAddrPred_updateEn$wget[0] && nextAddrPred_tags$D_OUT_1 == - nextAddrPred_updateEn$wget[128:75]) ; + nextAddrPred_updateEn$wget[193:139]) ; // register out_fifo_dequeueFifo_rl assign out_fifo_dequeueFifo_rl$D_IN = - IF_out_fifo_dequeueFifo_lat_1_whas__14_THEN_ou_ETC___d820 ; + IF_out_fifo_dequeueFifo_lat_1_whas__93_THEN_ou_ETC___d899 ; assign out_fifo_dequeueFifo_rl$EN = 1'd1 ; // register out_fifo_enqueueElement_0_rl assign out_fifo_enqueueElement_0_rl$D_IN = - 389'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAB1FEAAAAAAAAAAAAAAAAAAAAAAAFAAAAAAAAAAAAAAAA ; + 592'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA552AAAAAAAAAAA8FFAAAAAAAAAAAAAAAAAAAAAAAABCAAAAAAAAAAAAAAAA ; assign out_fifo_enqueueElement_0_rl$EN = 1'd1 ; // register out_fifo_enqueueElement_1_rl assign out_fifo_enqueueElement_1_rl$D_IN = - 389'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAB1FEAAAAAAAAAAAAAAAAAAAAAAAFAAAAAAAAAAAAAAAA ; + 592'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA552AAAAAAAAAAA8FFAAAAAAAAAAAAAAAAAAAAAAAABCAAAAAAAAAAAAAAAA ; assign out_fifo_enqueueElement_1_rl$EN = 1'd1 ; // register out_fifo_enqueueFifo_rl assign out_fifo_enqueueFifo_rl$D_IN = - IF_out_fifo_enqueueFifo_lat_1_whas__04_THEN_ou_ETC___d810 ; + IF_out_fifo_enqueueFifo_lat_1_whas__83_THEN_ou_ETC___d889 ; assign out_fifo_enqueueFifo_rl$EN = 1'd1 ; // register out_fifo_willDequeue_0_rl @@ -8575,7 +8712,9 @@ module mkFetchStage(CLK, assign pc_reg_rl$D_IN = EN_redirect ? redirect_pc : - IF_pc_reg_lat_1_whas_THEN_pc_reg_lat_1_wget_EL_ETC___d9 ; + (pc_reg_lat_2$whas ? + upd__h972 : + IF_pc_reg_lat_1_whas_THEN_pc_reg_lat_1_wget_EL_ETC___d11) ; assign pc_reg_rl$EN = 1'd1 ; // register perfReqQ_clearReq_rl @@ -8588,9 +8727,8 @@ module mkFetchStage(CLK, perfReqQ_enqReq_lat_0$wget[1:0] : perfReqQ_enqReq_rl[1:0] ; assign perfReqQ_data_0$EN = - NOT_perfReqQ_clearReq_dummy2_1_read__021_022_O_ETC___d3026 && - perfReqQ_enqReq_dummy2_2$Q_OUT && - IF_perfReqQ_enqReq_lat_1_whas__977_THEN_perfRe_ETC___d2986 ; + !perfReqQ_clearReq_rl && + IF_perfReqQ_enqReq_lat_1_whas__342_THEN_perfRe_ETC___d4351 ; // register perfReqQ_deqReq_rl assign perfReqQ_deqReq_rl$D_IN = 1'd0 ; @@ -8598,8 +8736,11 @@ module mkFetchStage(CLK, // register perfReqQ_empty assign perfReqQ_empty$D_IN = - perfReqQ_clearReq_dummy2_1$Q_OUT && perfReqQ_clearReq_rl || - NOT_perfReqQ_enqReq_dummy2_2_read__027_042_OR__ETC___d3047 ; + perfReqQ_clearReq_rl || + (EN_perf_req ? + !perfReqQ_enqReq_lat_0$wget[2] : + !perfReqQ_enqReq_rl[2]) && + (EN_perf_resp || perfReqQ_deqReq_rl || perfReqQ_empty) ; assign perfReqQ_empty$EN = 1'd1 ; // register perfReqQ_enqReq_rl @@ -8608,58 +8749,58 @@ module mkFetchStage(CLK, // register perfReqQ_full assign perfReqQ_full$D_IN = - NOT_perfReqQ_clearReq_dummy2_1_read__021_022_O_ETC___d3026 && - perfReqQ_enqReq_dummy2_2_read__027_AND_IF_perf_ETC___d3039 ; + !perfReqQ_clearReq_rl && + (IF_perfReqQ_enqReq_lat_1_whas__342_THEN_perfRe_ETC___d4351 || + !EN_perf_resp && !perfReqQ_deqReq_rl && perfReqQ_full) ; assign perfReqQ_full$EN = 1'd1 ; - // register rg_half_inst_lsbs - assign rg_half_inst_lsbs$D_IN = - (SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 == - 2'd3 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701) ? - SEL_ARR_instdata_data_0_686_BITS_63_TO_32_751__ETC___d4754[15:0] : - SEL_ARR_instdata_data_0_686_BITS_193_TO_162_16_ETC___d5171[15:0] ; - assign rg_half_inst_lsbs$EN = - WILL_FIRE_RL_doDecode && - (SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 == - 2'd3 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 || - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d5167) ; - - // register rg_half_inst_pc - assign rg_half_inst_pc$D_IN = - (SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 == - 2'd3 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701) ? - x__h143344 : - SEL_ARR_instdata_data_0_686_BITS_259_TO_196_99_ETC___d4994 ; - assign rg_half_inst_pc$EN = - WILL_FIRE_RL_doDecode && - (SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 == - 2'd3 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 || - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d5167) ; - - // register rg_pending_straddle - assign rg_pending_straddle$D_IN = MUX_rg_pending_straddle$write_1__SEL_1 ; - assign rg_pending_straddle$EN = - WILL_FIRE_RL_doDecode && _dfoo523 || + // register rg_pending_decode + assign rg_pending_decode$D_IN = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6307, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6314, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6322, + x__h159975, + x__h159980, + y_avValue_fst_pred_next_pc__h165564, + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_455_ETC___d6645, + x__h161103, + x__h161115 } ; + assign rg_pending_decode$EN = WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 ; + (pending_n_items__h113790 != 2'd0 || + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012) && + !_0_CONCAT_IF_rg_pending_n_items_951_EQ_0_952_TH_ETC___d5375 && + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5380 ; + + // register rg_pending_f32d + assign rg_pending_f32d$D_IN = + { y_avValue_fst_pred_next_pc__h165564, + x1_avValue_fst_pred_next_pc__h146091, + 71'h0A0000000000000000, + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6698 } ; + assign rg_pending_f32d$EN = + WILL_FIRE_RL_doFetch3 && + (pending_n_items__h113790 != 2'd0 || + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012) && + !_0_CONCAT_IF_rg_pending_n_items_951_EQ_0_952_TH_ETC___d5375 && + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5380 ; + + // register rg_pending_n_items + assign rg_pending_n_items$D_IN = + (pending_n_items__h113790 != 2'd0 || + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012) ? + y_avValue_snd__h168590 : + 2'd0 ; + assign rg_pending_n_items$EN = WILL_FIRE_RL_doFetch3 ; // register started assign started$D_IN = !EN_stop ; assign started$EN = EN_stop || EN_start ; // register waitForFlush - assign waitForFlush$D_IN = EN_redirect ; - assign waitForFlush$EN = EN_done_flushing || EN_start || EN_redirect ; + assign waitForFlush$D_IN = EN_redirect || EN_setWaitFlush ; + assign waitForFlush$EN = + EN_done_flushing || EN_start || EN_setWaitFlush || EN_redirect ; // register waitForRedirect always@(EN_redirect or EN_setWaitRedirect or EN_start) @@ -8672,146 +8813,44 @@ module mkFetchStage(CLK, assign waitForRedirect$EN = EN_redirect || EN_start || EN_setWaitRedirect ; // submodule dirPred - assign dirPred$pred_0_pred_pc = x__h143344 ; + assign dirPred$pred_0_pred_pc = x__h171664 ; assign dirPred$pred_1_pred_pc = - SEL_ARR_instdata_data_0_686_BITS_259_TO_196_99_ETC___d4994 ; + SEL_ARR_instdata_data_0_987_BITS_389_TO_261_42_ETC___d7425 ; assign dirPred$update_mispred = train_predictors_mispred ; assign dirPred$update_pc = train_predictors_pc ; assign dirPred$update_taken = train_predictors_taken ; assign dirPred$update_train = train_predictors_dpTrain ; assign dirPred$EN_pred_0_pred = WILL_FIRE_RL_doDecode && - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd3 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != + SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d6985 && + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 != 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 && - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d4768[0] && - decode___d4768[99:95] == 5'd10 ; + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998 && + SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7047[0] && + decode___d7047[171:167] == 5'd10 ; assign dirPred$EN_pred_1_pred = WILL_FIRE_RL_doDecode && - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 != - 2'd3 && - NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_19_ETC___d5188 ; + SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d6985 && + NOT_SEL_ARR_instdata_data_0_987_BITS_260_TO_25_ETC___d7566 ; assign dirPred$EN_update = EN_train_predictors && train_predictors_iType == 5'd10 ; assign dirPred$EN_flush = EN_flush_predictors ; - // submodule f12f2_clearReq_dummy2_0 - assign f12f2_clearReq_dummy2_0$D_IN = 1'b0 ; - assign f12f2_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule f12f2_clearReq_dummy2_1 - assign f12f2_clearReq_dummy2_1$D_IN = 1'd1 ; - assign f12f2_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule f12f2_deqReq_dummy2_0 - assign f12f2_deqReq_dummy2_0$D_IN = 1'd1 ; - assign f12f2_deqReq_dummy2_0$EN = WILL_FIRE_RL_doFetch2 ; - - // submodule f12f2_deqReq_dummy2_1 - assign f12f2_deqReq_dummy2_1$D_IN = 1'b0 ; - assign f12f2_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule f12f2_deqReq_dummy2_2 - assign f12f2_deqReq_dummy2_2$D_IN = 1'd1 ; - assign f12f2_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule f12f2_enqReq_dummy2_0 - assign f12f2_enqReq_dummy2_0$D_IN = 1'd1 ; - assign f12f2_enqReq_dummy2_0$EN = WILL_FIRE_RL_doFetch1 ; - - // submodule f12f2_enqReq_dummy2_1 - assign f12f2_enqReq_dummy2_1$D_IN = 1'b0 ; - assign f12f2_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule f12f2_enqReq_dummy2_2 - assign f12f2_enqReq_dummy2_2$D_IN = 1'd1 ; - assign f12f2_enqReq_dummy2_2$EN = 1'd1 ; - - // submodule f22f3_clearReq_dummy2_0 - assign f22f3_clearReq_dummy2_0$D_IN = 1'b0 ; - assign f22f3_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule f22f3_clearReq_dummy2_1 - assign f22f3_clearReq_dummy2_1$D_IN = 1'd1 ; - assign f22f3_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule f22f3_deqReq_dummy2_0 - assign f22f3_deqReq_dummy2_0$D_IN = 1'd1 ; - assign f22f3_deqReq_dummy2_0$EN = WILL_FIRE_RL_doFetch3 ; - - // submodule f22f3_deqReq_dummy2_1 - assign f22f3_deqReq_dummy2_1$D_IN = 1'b0 ; - assign f22f3_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule f22f3_deqReq_dummy2_2 - assign f22f3_deqReq_dummy2_2$D_IN = 1'd1 ; - assign f22f3_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule f22f3_enqReq_dummy2_0 - assign f22f3_enqReq_dummy2_0$D_IN = 1'd1 ; - assign f22f3_enqReq_dummy2_0$EN = WILL_FIRE_RL_doFetch2 ; - - // submodule f22f3_enqReq_dummy2_1 - assign f22f3_enqReq_dummy2_1$D_IN = 1'b0 ; - assign f22f3_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule f22f3_enqReq_dummy2_2 - assign f22f3_enqReq_dummy2_2$D_IN = 1'd1 ; - assign f22f3_enqReq_dummy2_2$EN = 1'd1 ; - - // submodule f32d_clearReq_dummy2_0 - assign f32d_clearReq_dummy2_0$D_IN = 1'b0 ; - assign f32d_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule f32d_clearReq_dummy2_1 - assign f32d_clearReq_dummy2_1$D_IN = 1'd1 ; - assign f32d_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule f32d_deqReq_dummy2_0 - assign f32d_deqReq_dummy2_0$D_IN = 1'd1 ; - assign f32d_deqReq_dummy2_0$EN = CAN_FIRE_RL_doDecode ; - - // submodule f32d_deqReq_dummy2_1 - assign f32d_deqReq_dummy2_1$D_IN = 1'b0 ; - assign f32d_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule f32d_deqReq_dummy2_2 - assign f32d_deqReq_dummy2_2$D_IN = 1'd1 ; - assign f32d_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule f32d_enqReq_dummy2_0 - assign f32d_enqReq_dummy2_0$D_IN = 1'd1 ; - assign f32d_enqReq_dummy2_0$EN = f32d_enqReq_lat_0$whas ; - - // submodule f32d_enqReq_dummy2_1 - assign f32d_enqReq_dummy2_1$D_IN = 1'b0 ; - assign f32d_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule f32d_enqReq_dummy2_2 - assign f32d_enqReq_dummy2_2$D_IN = 1'd1 ; - assign f32d_enqReq_dummy2_2$EN = 1'd1 ; - // submodule iMem assign iMem$perf_req_r = iMemIfc_perf_req_r ; assign iMem$perf_setStatus_doStats = iMemIfc_perf_setStatus_doStats ; assign iMem$to_parent_fromP_enq_x = iMemIfc_to_parent_fromP_enq_x ; assign iMem$to_proc_request_put = MUX_iMem$to_proc_request_put_1__SEL_1 ? - iTlb$to_proc_response_get[68:5] : + iTlb$to_proc_response_get[69:6] : iMemIfc_to_proc_request_put ; assign iMem$EN_to_proc_request_put = - WILL_FIRE_RL_doFetch2 && !iTlb$to_proc_response_get[4] && + WILL_FIRE_RL_doFetch2 && !iTlb$to_proc_response_get[5] && mmio$getFetchTarget == 2'd0 || EN_iMemIfc_to_proc_request_put ; assign iMem$EN_to_proc_response_get = - WILL_FIRE_RL_doFetch3 && - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - !SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491 || + _dand1iMem$EN_to_proc_response_get || EN_iMemIfc_to_proc_response_get ; assign iMem$EN_flush = EN_iMemIfc_flush ; assign iMem$EN_perf_setStatus = EN_iMemIfc_perf_setStatus ; @@ -8848,4544 +8887,8208 @@ module mkFetchStage(CLK, assign iTlb$EN_perf_req = EN_iTlbIfc_perf_req ; assign iTlb$EN_perf_resp = EN_iTlbIfc_perf_resp ; - // submodule instdata_deqP_dummy2_0 - assign instdata_deqP_dummy2_0$D_IN = 1'd1 ; - assign instdata_deqP_dummy2_0$EN = CAN_FIRE_RL_doDecode ; - - // submodule instdata_deqP_dummy2_1 - assign instdata_deqP_dummy2_1$D_IN = 1'b0 ; - assign instdata_deqP_dummy2_1$EN = 1'b0 ; - - // submodule instdata_empty_dummy2_0 - assign instdata_empty_dummy2_0$D_IN = 1'd1 ; - assign instdata_empty_dummy2_0$EN = instdata_empty_lat_0$whas ; - - // submodule instdata_empty_dummy2_1 - assign instdata_empty_dummy2_1$D_IN = 1'd1 ; - assign instdata_empty_dummy2_1$EN = f32d_enqReq_lat_0$whas ; - - // submodule instdata_empty_dummy2_2 - assign instdata_empty_dummy2_2$D_IN = 1'b0 ; - assign instdata_empty_dummy2_2$EN = 1'b0 ; - - // submodule instdata_enqP_dummy2_0 - assign instdata_enqP_dummy2_0$D_IN = 1'd1 ; - assign instdata_enqP_dummy2_0$EN = f32d_enqReq_lat_0$whas ; - - // submodule instdata_enqP_dummy2_1 - assign instdata_enqP_dummy2_1$D_IN = 1'b0 ; - assign instdata_enqP_dummy2_1$EN = 1'b0 ; - - // submodule instdata_full_dummy2_0 - assign instdata_full_dummy2_0$D_IN = 1'd1 ; - assign instdata_full_dummy2_0$EN = CAN_FIRE_RL_doDecode ; - - // submodule instdata_full_dummy2_1 - assign instdata_full_dummy2_1$D_IN = 1'd1 ; - assign instdata_full_dummy2_1$EN = instdata_full_lat_1$whas ; - - // submodule instdata_full_dummy2_2 - assign instdata_full_dummy2_2$D_IN = 1'b0 ; - assign instdata_full_dummy2_2$EN = 1'b0 ; - // submodule mmio - assign mmio$bootRomReq_maxWay = x__h116417 ; - assign mmio$bootRomReq_phyPc = iTlb$to_proc_response_get[68:5] ; - assign mmio$getFetchTarget_phyPc = iTlb$to_proc_response_get[68:5] ; + assign mmio$bootRomReq_maxWay = + SEL_ARR_f12f2_data_0_810_BITS_266_TO_265_811_f_ETC___d4815[1] ; + assign mmio$bootRomReq_phyPc = iTlb$to_proc_response_get[69:6] ; + assign mmio$getFetchTarget_phyPc = iTlb$to_proc_response_get[69:6] ; assign mmio$toCore_instResp_enq_x = mmioIfc_instResp_enq_x ; assign mmio$toCore_setHtifAddrs_fromHost = mmioIfc_setHtifAddrs_fromHost ; assign mmio$toCore_setHtifAddrs_toHost = mmioIfc_setHtifAddrs_toHost ; assign mmio$EN_bootRomReq = - WILL_FIRE_RL_doFetch2 && !iTlb$to_proc_response_get[4] && + WILL_FIRE_RL_doFetch2 && !iTlb$to_proc_response_get[5] && mmio$getFetchTarget == 2'd1 ; assign mmio$EN_bootRomResp = WILL_FIRE_RL_doFetch3 && - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491 ; + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5163) && + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 && + SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003 ; assign mmio$EN_toCore_instReq_deq = EN_mmioIfc_instReq_deq ; assign mmio$EN_toCore_instResp_enq = EN_mmioIfc_instResp_enq ; assign mmio$EN_toCore_setHtifAddrs = EN_mmioIfc_setHtifAddrs ; - // submodule napTrainByDecQ_deqP_dummy2_0 - assign napTrainByDecQ_deqP_dummy2_0$D_IN = 1'd1 ; - assign napTrainByDecQ_deqP_dummy2_0$EN = CAN_FIRE_RL_setTrainNAPByDec ; - - // submodule napTrainByDecQ_deqP_dummy2_1 - assign napTrainByDecQ_deqP_dummy2_1$D_IN = 1'b0 ; - assign napTrainByDecQ_deqP_dummy2_1$EN = 1'b0 ; - - // submodule napTrainByDecQ_empty_dummy2_0 - assign napTrainByDecQ_empty_dummy2_0$D_IN = 1'd1 ; - assign napTrainByDecQ_empty_dummy2_0$EN = CAN_FIRE_RL_setTrainNAPByDec ; - - // submodule napTrainByDecQ_empty_dummy2_1 - assign napTrainByDecQ_empty_dummy2_1$D_IN = 1'd1 ; - assign napTrainByDecQ_empty_dummy2_1$EN = napTrainByDecQ_enqP_lat_0$whas ; - - // submodule napTrainByDecQ_empty_dummy2_2 - assign napTrainByDecQ_empty_dummy2_2$D_IN = 1'b0 ; - assign napTrainByDecQ_empty_dummy2_2$EN = 1'b0 ; - - // submodule napTrainByDecQ_enqP_dummy2_0 - assign napTrainByDecQ_enqP_dummy2_0$D_IN = 1'd1 ; - assign napTrainByDecQ_enqP_dummy2_0$EN = napTrainByDecQ_enqP_lat_0$whas ; - - // submodule napTrainByDecQ_enqP_dummy2_1 - assign napTrainByDecQ_enqP_dummy2_1$D_IN = 1'b0 ; - assign napTrainByDecQ_enqP_dummy2_1$EN = 1'b0 ; - - // submodule napTrainByDecQ_full_dummy2_0 - assign napTrainByDecQ_full_dummy2_0$D_IN = 1'd1 ; - assign napTrainByDecQ_full_dummy2_0$EN = CAN_FIRE_RL_setTrainNAPByDec ; - - // submodule napTrainByDecQ_full_dummy2_1 - assign napTrainByDecQ_full_dummy2_1$D_IN = 1'd1 ; - assign napTrainByDecQ_full_dummy2_1$EN = napTrainByDecQ_enqP_lat_0$whas ; - - // submodule napTrainByDecQ_full_dummy2_2 - assign napTrainByDecQ_full_dummy2_2$D_IN = 1'b0 ; - assign napTrainByDecQ_full_dummy2_2$EN = 1'b0 ; - // submodule nextAddrPred_next_addrs - assign nextAddrPred_next_addrs$ADDR_1 = pred_next_pc__h114157[9:2] ; - assign nextAddrPred_next_addrs$ADDR_2 = x__h115849[9:2] ; - assign nextAddrPred_next_addrs$ADDR_3 = 8'h0 ; - assign nextAddrPred_next_addrs$ADDR_4 = 8'h0 ; + assign nextAddrPred_next_addrs$ADDR_1 = x__h111368[8:1] ; + assign nextAddrPred_next_addrs$ADDR_2 = address__h110316[8:1] ; + assign nextAddrPred_next_addrs$ADDR_3 = address__h109631[8:1] ; + assign nextAddrPred_next_addrs$ADDR_4 = pc_reg_rl[8:1] ; assign nextAddrPred_next_addrs$ADDR_5 = 8'h0 ; - assign nextAddrPred_next_addrs$ADDR_IN = nextAddrPred_updateEn$wget[74:67] ; - assign nextAddrPred_next_addrs$D_IN = nextAddrPred_updateEn$wget[64:1] ; + assign nextAddrPred_next_addrs$ADDR_IN = + nextAddrPred_updateEn$wget[138:131] ; + assign nextAddrPred_next_addrs$D_IN = nextAddrPred_updateEn$wget[129:1] ; assign nextAddrPred_next_addrs$WE = WILL_FIRE_RL_nextAddrPred_canonUpdate && nextAddrPred_updateEn$wget[0] ; // submodule nextAddrPred_tags - assign nextAddrPred_tags$ADDR_1 = nextAddrPred_updateEn$wget[74:67] ; - assign nextAddrPred_tags$ADDR_2 = pred_next_pc__h114157[9:2] ; - assign nextAddrPred_tags$ADDR_3 = x__h115849[9:2] ; - assign nextAddrPred_tags$ADDR_4 = 8'h0 ; - assign nextAddrPred_tags$ADDR_5 = 8'h0 ; - assign nextAddrPred_tags$ADDR_IN = nextAddrPred_updateEn$wget[74:67] ; - assign nextAddrPred_tags$D_IN = nextAddrPred_updateEn$wget[128:75] ; + assign nextAddrPred_tags$ADDR_1 = nextAddrPred_updateEn$wget[138:131] ; + assign nextAddrPred_tags$ADDR_2 = x__h111368[8:1] ; + assign nextAddrPred_tags$ADDR_3 = address__h110316[8:1] ; + assign nextAddrPred_tags$ADDR_4 = address__h109631[8:1] ; + assign nextAddrPred_tags$ADDR_5 = pc_reg_rl[8:1] ; + assign nextAddrPred_tags$ADDR_IN = nextAddrPred_updateEn$wget[138:131] ; + assign nextAddrPred_tags$D_IN = nextAddrPred_updateEn$wget[193:139] ; assign nextAddrPred_tags$WE = WILL_FIRE_RL_nextAddrPred_canonUpdate && nextAddrPred_updateEn$wget[0] ; - // submodule out_fifo_dequeueFifo_dummy2_0 - assign out_fifo_dequeueFifo_dummy2_0$D_IN = 1'd1 ; - assign out_fifo_dequeueFifo_dummy2_0$EN = out_fifo_dequeueFifo_lat_0$whas ; - - // submodule out_fifo_dequeueFifo_dummy2_1 - assign out_fifo_dequeueFifo_dummy2_1$D_IN = 1'd1 ; - assign out_fifo_dequeueFifo_dummy2_1$EN = out_fifo_dequeueFifo_lat_1$whas ; - - // submodule out_fifo_dequeueFifo_dummy2_2 - assign out_fifo_dequeueFifo_dummy2_2$D_IN = 1'b0 ; - assign out_fifo_dequeueFifo_dummy2_2$EN = 1'b0 ; - - // submodule out_fifo_enqueueElement_0_dummy2_0 - assign out_fifo_enqueueElement_0_dummy2_0$D_IN = 1'd1 ; - assign out_fifo_enqueueElement_0_dummy2_0$EN = - out_fifo_enqueueElement_0_lat_0$whas ; - - // submodule out_fifo_enqueueElement_0_dummy2_1 - assign out_fifo_enqueueElement_0_dummy2_1$D_IN = 1'd1 ; - assign out_fifo_enqueueElement_0_dummy2_1$EN = 1'd1 ; - - // submodule out_fifo_enqueueElement_1_dummy2_0 - assign out_fifo_enqueueElement_1_dummy2_0$D_IN = 1'd1 ; - assign out_fifo_enqueueElement_1_dummy2_0$EN = - out_fifo_enqueueElement_1_dummy_1_0$wget ; - - // submodule out_fifo_enqueueElement_1_dummy2_1 - assign out_fifo_enqueueElement_1_dummy2_1$D_IN = 1'd1 ; - assign out_fifo_enqueueElement_1_dummy2_1$EN = 1'd1 ; - - // submodule out_fifo_enqueueFifo_dummy2_0 - assign out_fifo_enqueueFifo_dummy2_0$D_IN = 1'd1 ; - assign out_fifo_enqueueFifo_dummy2_0$EN = out_fifo_enqueueFifo_lat_0$whas ; - - // submodule out_fifo_enqueueFifo_dummy2_1 - assign out_fifo_enqueueFifo_dummy2_1$D_IN = 1'd1 ; - assign out_fifo_enqueueFifo_dummy2_1$EN = out_fifo_enqueueFifo_lat_1$whas ; - - // submodule out_fifo_enqueueFifo_dummy2_2 - assign out_fifo_enqueueFifo_dummy2_2$D_IN = 1'b0 ; - assign out_fifo_enqueueFifo_dummy2_2$EN = 1'b0 ; - // submodule out_fifo_internalFifos_0 assign out_fifo_internalFifos_0$D_IN = - (x__h54856 == 1'd0 && out_fifo_enqueueElement_0_dummy2_1$Q_OUT && - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d830) ? - { IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d840, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d845, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d850, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d855, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d860, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d865, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1998, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d2037, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1217, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1222, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1232, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1238, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1248, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1255, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1265, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1271, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1281, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1289, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2058, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1381 } : - { IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1408, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1413, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1418, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1423, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1428, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1433, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2101, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d2140, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1784, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1789, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1799, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1805, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1815, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1822, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1832, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1838, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1848, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1856, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2161, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1948 } ; - assign out_fifo_internalFifos_0$ENQ = _dfoo5 ; - assign out_fifo_internalFifos_0$DEQ = _dfoo2 ; + (out_fifo_enqueueFifo_rl == 1'd0 && + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d909) ? + { IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d919, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d924, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d929, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d934, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d939, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d944, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3267, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3296, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1500, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d3358, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1890, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1895, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1905, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1911, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1921, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1928, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1938, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1944, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1954, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d3383 } : + { IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2087, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2092, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2097, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2102, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2107, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2112, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3414, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3443, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2665, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3505, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3055, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3060, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3070, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3076, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3086, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3093, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3103, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3109, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3119, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3530 } ; + assign out_fifo_internalFifos_0$ENQ = + out_fifo_enqueueFifo_rl == 1'd0 && + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d909 || + x__h60535 == 1'd0 && + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2077 ; + assign out_fifo_internalFifos_0$DEQ = + out_fifo_dequeueFifo_rl == 1'd0 && + IF_out_fifo_willDequeue_0_lat_0_whas__236_THEN_ETC___d3239 || + x__h74473 == 1'd0 && + IF_out_fifo_willDequeue_1_lat_0_whas__243_THEN_ETC___d3246 ; assign out_fifo_internalFifos_0$CLR = 1'b0 ; // submodule out_fifo_internalFifos_1 assign out_fifo_internalFifos_1$D_IN = - (x__h54856 == 1'd1 && out_fifo_enqueueElement_0_dummy2_1$Q_OUT && - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d830) ? - { IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d840, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d845, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d850, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d855, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d860, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d865, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1998, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d2037, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1217, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1222, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1232, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1238, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1248, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1255, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1265, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1271, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1281, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1289, - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2058, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1381 } : - { IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1408, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1413, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1418, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1423, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1428, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1433, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2101, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d2140, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1784, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1789, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1799, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1805, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1815, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1822, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1832, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1838, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1848, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1856, - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2161, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1948 } ; - assign out_fifo_internalFifos_1$ENQ = _dfoo3 ; - assign out_fifo_internalFifos_1$DEQ = _dfoo1 ; + (out_fifo_enqueueFifo_rl == 1'd1 && + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d909) ? + { IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d919, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d924, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d929, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d934, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d939, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d944, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3267, + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3296, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1500, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d3358, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1890, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1895, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1905, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1911, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1921, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1928, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1938, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1944, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1954, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d3383 } : + { IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2087, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2092, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2097, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2102, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2107, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2112, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3414, + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3443, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2665, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3505, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3055, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3060, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3070, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3076, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3086, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3093, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3103, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3109, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3119, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3530 } ; + assign out_fifo_internalFifos_1$ENQ = + out_fifo_enqueueFifo_rl == 1'd1 && + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d909 || + x__h60535 == 1'd1 && + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2077 ; + assign out_fifo_internalFifos_1$DEQ = + out_fifo_dequeueFifo_rl == 1'd1 && + IF_out_fifo_willDequeue_0_lat_0_whas__236_THEN_ETC___d3239 || + x__h74473 == 1'd1 && + IF_out_fifo_willDequeue_1_lat_0_whas__243_THEN_ETC___d3246 ; assign out_fifo_internalFifos_1$CLR = 1'b0 ; - // submodule out_fifo_willDequeue_0_dummy2_0 - assign out_fifo_willDequeue_0_dummy2_0$D_IN = 1'd1 ; - assign out_fifo_willDequeue_0_dummy2_0$EN = EN_pipelines_0_deq ; - - // submodule out_fifo_willDequeue_0_dummy2_1 - assign out_fifo_willDequeue_0_dummy2_1$D_IN = 1'd1 ; - assign out_fifo_willDequeue_0_dummy2_1$EN = 1'd1 ; - - // submodule out_fifo_willDequeue_1_dummy2_0 - assign out_fifo_willDequeue_1_dummy2_0$D_IN = 1'd1 ; - assign out_fifo_willDequeue_1_dummy2_0$EN = EN_pipelines_1_deq ; - - // submodule out_fifo_willDequeue_1_dummy2_1 - assign out_fifo_willDequeue_1_dummy2_1$D_IN = 1'd1 ; - assign out_fifo_willDequeue_1_dummy2_1$EN = 1'd1 ; - - // submodule pc_reg_dummy2_0 - assign pc_reg_dummy2_0$D_IN = 1'd1 ; - assign pc_reg_dummy2_0$EN = WILL_FIRE_RL_doFetch1 || EN_start ; - - // submodule pc_reg_dummy2_1 - assign pc_reg_dummy2_1$D_IN = 1'd1 ; - assign pc_reg_dummy2_1$EN = pc_reg_dummy_1_0$whas ; - - // submodule pc_reg_dummy2_2 - assign pc_reg_dummy2_2$D_IN = 1'd1 ; - assign pc_reg_dummy2_2$EN = EN_redirect ; - - // submodule perfReqQ_clearReq_dummy2_0 - assign perfReqQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign perfReqQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule perfReqQ_clearReq_dummy2_1 - assign perfReqQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign perfReqQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule perfReqQ_deqReq_dummy2_0 - assign perfReqQ_deqReq_dummy2_0$D_IN = 1'd1 ; - assign perfReqQ_deqReq_dummy2_0$EN = EN_perf_resp ; - - // submodule perfReqQ_deqReq_dummy2_1 - assign perfReqQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign perfReqQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule perfReqQ_deqReq_dummy2_2 - assign perfReqQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign perfReqQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule perfReqQ_enqReq_dummy2_0 - assign perfReqQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign perfReqQ_enqReq_dummy2_0$EN = EN_perf_req ; - - // submodule perfReqQ_enqReq_dummy2_1 - assign perfReqQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign perfReqQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule perfReqQ_enqReq_dummy2_2 - assign perfReqQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign perfReqQ_enqReq_dummy2_2$EN = 1'd1 ; - // submodule ras assign ras$ras_0_popPush_pop = - (decode___d4768[99:95] != 5'd8 || !decode___d4768[7] || - decode___d4768[6] || - decode___d4768[5:1] != 5'd1 && decode___d4768[5:1] != 5'd5) && - (NOT_decode_768_BIT_7_780_791_OR_decode_768_BIT_ETC___d4807 || - (decode___d4768[27] && !decode___d4768[26] && - (decode___d4768[25:21] == 5'd1 || - decode___d4768[25:21] == 5'd5) || - !decode___d4768[7] || - decode___d4768[6] || - decode___d4768[5:1] != 5'd1 && decode___d4768[5:1] != 5'd5) && - IF_NOT_decode_768_BIT_26_799_800_AND_NOT_decod_ETC___d4841) ; + (decode___d7047[171:167] != 5'd8 || !decode___d7047[7] || + decode___d7047[6] || + decode___d7047[5:1] != 5'd1 && decode___d7047[5:1] != 5'd5) && + (NOT_decode_047_BIT_7_058_071_OR_decode_047_BIT_ETC___d7087 || + (decode___d7047[27] && !decode___d7047[26] && + (decode___d7047[25:21] == 5'd1 || + decode___d7047[25:21] == 5'd5) || + !decode___d7047[7] || + decode___d7047[6] || + decode___d7047[5:1] != 5'd1 && decode___d7047[5:1] != 5'd5) && + IF_NOT_decode_047_BIT_26_079_080_AND_NOT_decod_ETC___d7120) ; assign ras$ras_0_popPush_pushAddr = - { decode___d4768[7] && !decode___d4768[6] && - (decode___d4768[5:1] == 5'd1 || decode___d4768[5:1] == 5'd5) || - !decode___d4768[27] || - decode___d4768[26] || - decode___d4768[25:21] != 5'd1 && decode___d4768[25:21] != 5'd5, - x__h143344 + - ((SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 == - 2'd2) ? - 64'd4 : - 64'd2) } ; + { decode___d7047[7] && !decode___d7047[6] && + (decode___d7047[5:1] == 5'd1 || decode___d7047[5:1] == 5'd5) || + !decode___d7047[27] || + decode___d7047[26] || + decode___d7047[25:21] != 5'd1 && decode___d7047[25:21] != 5'd5, + x__h171664[128:64], + address__h172257 } ; assign ras$ras_1_popPush_pop = - (decode___d5180[99:95] != 5'd8 || !decode___d5180[7] || - decode___d5180[6] || - decode___d5180[5:1] != 5'd1 && decode___d5180[5:1] != 5'd5) && - (NOT_decode_180_BIT_7_192_203_OR_decode_180_BIT_ETC___d5219 || - (decode___d5180[27] && !decode___d5180[26] && - (decode___d5180[25:21] == 5'd1 || - decode___d5180[25:21] == 5'd5) || - !decode___d5180[7] || - decode___d5180[6] || - decode___d5180[5:1] != 5'd1 && decode___d5180[5:1] != 5'd5) && - IF_NOT_decode_180_BIT_26_211_212_AND_NOT_decod_ETC___d5253) ; + (decode___d7558[171:167] != 5'd8 || !decode___d7558[7] || + decode___d7558[6] || + decode___d7558[5:1] != 5'd1 && decode___d7558[5:1] != 5'd5) && + (NOT_decode_558_BIT_7_569_582_OR_decode_558_BIT_ETC___d7598 || + (decode___d7558[27] && !decode___d7558[26] && + (decode___d7558[25:21] == 5'd1 || + decode___d7558[25:21] == 5'd5) || + !decode___d7558[7] || + decode___d7558[6] || + decode___d7558[5:1] != 5'd1 && decode___d7558[5:1] != 5'd5) && + IF_NOT_decode_558_BIT_26_590_591_AND_NOT_decod_ETC___d7631) ; assign ras$ras_1_popPush_pushAddr = - { decode___d5180[7] && !decode___d5180[6] && - (decode___d5180[5:1] == 5'd1 || decode___d5180[5:1] == 5'd5) || - !decode___d5180[27] || - decode___d5180[26] || - decode___d5180[25:21] != 5'd1 && decode___d5180[25:21] != 5'd5, - SEL_ARR_instdata_data_0_686_BITS_259_TO_196_99_ETC___d4994 + - ((SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 == - 2'd2) ? - 64'd4 : - 64'd2) } ; + { decode___d7558[7] && !decode___d7558[6] && + (decode___d7558[5:1] == 5'd1 || decode___d7558[5:1] == 5'd5) || + !decode___d7558[27] || + decode___d7558[26] || + decode___d7558[25:21] != 5'd1 && decode___d7558[25:21] != 5'd5, + SEL_ARR_instdata_data_0_987_BITS_389_TO_261_42_ETC___d7425[128:64], + address__h182904 } ; assign ras$EN_ras_0_popPush = WILL_FIRE_RL_doDecode && - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd3 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != + SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d6985 && + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 != 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 && - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d4768[0] && - decode_768_BITS_99_TO_95_772_EQ_8_779_AND_deco_ETC___d4820 ; + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998 && + SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7047[0] && + decode_047_BITS_171_TO_167_051_EQ_8_057_AND_de_ETC___d7100 ; assign ras$EN_ras_1_popPush = WILL_FIRE_RL_doDecode && - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d5237 ; + SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d7615 ; assign ras$EN_flush = EN_flush_predictors ; // remaining internal signals - module_decode instance_decode_3(.decode_inst(SEL_ARR_instdata_data_0_686_BITS_31_TO_0_764_i_ETC___d4767), - .decode(decode___d4768)); - module_decode instance_decode_2(.decode_inst(SEL_ARR_instdata_data_0_686_BITS_161_TO_130_17_ETC___d5179), - .decode(decode___d5180)); - module_decodeBrPred instance_decodeBrPred_1(.decodeBrPred_pc(SEL_ARR_instdata_data_0_686_BITS_259_TO_196_99_ETC___d4994), - .decodeBrPred_dInst(decode_180_BITS_99_TO_95_184_CONCAT_IF_decode__ETC___d5381), - .decodeBrPred_histTaken(decode___d5180[99:95] == + module_decode instance_decode_3(.decode_inst(SEL_ARR_instdata_data_0_987_BITS_31_TO_0_038_i_ETC___d7041), + .decode_cap_mode(x_BIT_109___h171706), + .decode(decode___d7047)); + module_decode instance_decode_2(.decode_inst(SEL_ARR_instdata_data_0_987_BITS_226_TO_195_55_ETC___d7556), + .decode_cap_mode(x_BIT_109___h182531), + .decode(decode___d7558)); + module_decodeBrPred instance_decodeBrPred_1(.decodeBrPred_pc(SEL_ARR_instdata_data_0_987_BITS_389_TO_261_42_ETC___d7425), + .decodeBrPred_dInst(decode_558_BITS_171_TO_167_562_CONCAT_IF_decod_ETC___d7911), + .decodeBrPred_histTaken(decode___d7558[171:167] == 5'd10 && dirPred$pred_1_pred[24]), - .decodeBrPred_is_32b_inst(SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 == + .decodeBrPred_is_32b_inst(SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 == 2'd2), - .decodeBrPred(decodeBrPred___d5385)); - module_decodeBrPred instance_decodeBrPred_0(.decodeBrPred_pc(x__h143344), - .decodeBrPred_dInst(decode_768_BITS_99_TO_95_772_CONCAT_IF_decode__ETC___d4969), - .decodeBrPred_histTaken(decode___d4768[99:95] == + .decodeBrPred(decodeBrPred___d7915)); + module_decodeBrPred instance_decodeBrPred_0(.decodeBrPred_pc(x__h171664), + .decodeBrPred_dInst(decode_047_BITS_171_TO_167_051_CONCAT_IF_decod_ETC___d7400), + .decodeBrPred_histTaken(decode___d7047[171:167] == 5'd10 && dirPred$pred_0_pred[24]), - .decodeBrPred_is_32b_inst(SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 == + .decodeBrPred_is_32b_inst(SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 == 2'd2), - .decodeBrPred(decodeBrPred___d4973)); - assign IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4042 = - IF_IF_rg_pending_straddle_514_THEN_IF_SEL_ARR__ETC___d4011 ? - y_avValue_fst__h122039 : - j__h119769 ; - assign IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4047 = - IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4042 + + .decodeBrPred(decodeBrPred___d7404)); + assign CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5108 = + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q361 && + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q362 ; + assign CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5110 = + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q363 && + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q364 && + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5108 ; + assign CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5112 = + CASE_pending_spaces_ext45988_0_1_1_NOT_SEL_ARR_ETC__q365 && + CASE_pending_spaces_ext45988_0_1_1_NOT_SEL_ARR_ETC__q366 && + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5110 ; + assign CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5144 = + CASE_pending_spaces_ext45988_0_1_1_1_2_NOT_f22_ETC__q368 && + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5140 && + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5142 ; + assign CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5145 = + CASE_pending_spaces_ext45988_0_1_1_1_2_NOT_f22_ETC__q369 && + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5144 ; + assign CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5147 = + CASE_pending_spaces_ext45988_0_1_1_1_2_1_3_NOT_ETC__q370 && + CASE_pending_spaces_ext45988_0_1_1_1_2_1_3_NOT_ETC__q371 && + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5145 ; + assign DONTCARE_CONCAT_SEL_ARR_out_fifo_internalFifos_ETC___d8377 = + { 4'hA, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q32 } ; + assign DONTCARE_CONCAT_SEL_ARR_out_fifo_internalFifos_ETC___d9326 = + { 4'hA, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q73 } ; + assign IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d5287 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5266 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b11) ? + !IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5271 || + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5284 : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5284) : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5284 ; + assign IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d5322 = + IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d5287 && + (IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5266 ? + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5320 : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5316) ; + assign IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d5403 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5266 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b11) ? + (IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5271 ? + 2'd2 : + 2'd0) : + 2'd1) : + 2'd0 ; + assign IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d6674 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5266 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b11) ? + !IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5271 || + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6671 : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6671) : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6671 ; + assign IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d6960 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5266 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b11) ? + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5271 && + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6957 : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6957) : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6957 ; + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5265 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 ? + y_avValue_fst__h134911 : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5254 ; + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5266 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5265 < + n_x16s__h114677 ; + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5270 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5265 + 3'd1 ; - assign IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4048 = - IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4047 < - n_x16s__h119766 ; - assign IF_IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AN_ETC___d5453 = - (IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5394 && - decode_pred_next_pc__h153837 != in_ppc__h150788) ? - decode_pred_next_pc__h153837 : - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5451 ; - assign IF_IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AN_ETC___d5465 = - (IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5394 && - decode_pred_next_pc__h153837 != in_ppc__h150788) ? - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5463 : - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5164 ; - assign IF_IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AN_ETC___d5480 = - (IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5394 && - decode_pred_next_pc__h153837 != in_ppc__h150788) ? - { SEL_ARR_instdata_data_0_686_BITS_259_TO_196_99_ETC___d4994, - decode_pred_next_pc__h153837 } : - { x__h143344, decode_pred_next_pc__h146966 } ; - assign IF_IF_decode_768_BITS_99_TO_95_772_EQ_8_779_AN_ETC___d5160 = - (IF_decode_768_BITS_99_TO_95_772_EQ_8_779_AND_d_ETC___d4982 && - decode_pred_next_pc__h146966 != in_ppc__h143612) ^ - decode_epoch ; - assign IF_IF_decode_768_BITS_99_TO_95_772_EQ_8_779_AN_ETC___d5459 = - !((IF_decode_768_BITS_99_TO_95_772_EQ_8_779_AND_d_ETC___d4982 && - decode_pred_next_pc__h146966 != in_ppc__h143612) ^ - decode_epoch) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1989 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[177:175] == 3'd2 : - out_fifo_enqueueElement_0_rl[177:175] == 3'd2) ? - 3'd2 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[177:175] == 3'd3 : - out_fifo_enqueueElement_0_rl[177:175] == 3'd3) ? + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5271 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5270 < + n_x16s__h114677 ; + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5284 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b11) ? + !IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260 || + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5281 : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5281) : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5281 ; + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5316 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 ? + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5315 : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5311 ; + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5319 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b11) ? + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260 && + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5314 : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5314) : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5314 ; + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5345 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 ? + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5344 : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5336 ; + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5351 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 ? + y_avValue_snd_snd_snd_snd_fst__h135219 : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5342 ; + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5369 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] != + 2'b11 || + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260) ? 3'd3 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[177:175] == 3'd4 : - out_fifo_enqueueElement_0_rl[177:175] == 3'd4) ? - 3'd4 : - 3'd7)) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1991 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[177:175] == 3'd0 : - out_fifo_enqueueElement_0_rl[177:175] == 3'd0) ? - 3'd0 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[177:175] == 3'd1 : - out_fifo_enqueueElement_0_rl[177:175] == 3'd1) ? + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5367) : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5367 ; + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5398 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b11) ? + (IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260 ? + 2'd2 : + 2'd0) : + 2'd1) : + 2'd0 ; + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6671 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b11) ? + !IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260 || + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6668 : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6668) : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6668 ; + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6957 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b11) ? + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260 && + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6954 : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6954) : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6954 ; + assign IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6969 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 ? + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d6968 : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6966 ; + assign IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5254 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 ? + y_avValue_fst__h126200 : + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5243 ; + assign IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5254 < + n_x16s__h114677 ; + assign IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260 = + y_avValue_fst__h134851 < n_x16s__h114677 ; + assign IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5281 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b11) ? + !IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249 || + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5278 : + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5278) : + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5278 ; + assign IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5311 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 ? + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5310 : + !SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 ; + assign IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5314 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b11) ? + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249 && + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5309 : + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5309) : + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5309 ; + assign IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5336 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 ? + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5335 : + pc_start__h114675 ; + assign IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5342 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 ? + y_avValue_snd_snd_snd_snd_fst__h126508 : + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5333 ; + assign IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5367 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] != + 2'b11 || + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249) ? + 3'd2 : + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5365) : + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5365 ; + assign IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5393 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b11) ? + (IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249 ? + 2'd2 : + 2'd0) : + 2'd1) : + 2'd0 ; + assign IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6668 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b11) ? + !IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249 || + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d6665 : + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d6665) : + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d6665 ; + assign IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6954 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b11) ? + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249 && + NOT_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_20_ETC___d6951 : + NOT_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_20_ETC___d6951) : + NOT_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_20_ETC___d6951 ; + assign IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6966 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 ? + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d6965 : + { pc_start__h114675, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234, + !SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 } ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6907 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd15 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6905) ? + 5'd15 : + 5'd28 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6908 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd13 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6895) ? + 5'd13 : + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6907 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6909 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd12 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6885) ? + 5'd12 : + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6908 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6910 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd11 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6875) ? + 5'd11 : + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6909 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6911 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd9 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6865) ? + 5'd9 : + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6910 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6912 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd8 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6855) ? + 5'd8 : + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6911 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6913 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd7 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6845) ? + 5'd7 : + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6912 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6914 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd6 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6835) ? + 5'd6 : + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6913 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6915 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd5 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6825) ? + 5'd5 : + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6914 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6916 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd4 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6815) ? + 5'd4 : + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6915 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6917 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd3 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6805) ? + 5'd3 : + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6916 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6918 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd2 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6795) ? + 5'd2 : + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6917 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6919 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd1 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6785) ? + 5'd1 : + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6918 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6920 = + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[73:69] == 5'd0 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6775) ? + 5'd0 : + IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6919 ; + assign IF_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f_ETC___d6975 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6962 ? + 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + ehr_pending_straddle_rl[145:0] : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6973) ; + assign IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5243 = + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196 ? + y_avValue_fst__h117264 : + j__h114680 ; + assign IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5243 < + n_x16s__h114677 ; + assign IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249 = + y_avValue_fst__h126140 < n_x16s__h114677 ; + assign IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5309 = + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196 ? + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d5308 : + !SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 ; + assign IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5333 = + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196 ? + y_avValue_snd_snd_snd_snd_fst__h117572 : + pc_start__h114675[63:0] ; + assign IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5365 = + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196 ? + ((IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 || + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] != + 2'b11 || + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5237) ? 3'd1 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1989) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1994 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[194:192] == 3'd4 : - out_fifo_enqueueElement_0_rl[194:192] == 3'd4) ? - { 12'd2218, - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[182:178] : - out_fifo_enqueueElement_0_rl[182:178], - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1991, - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[174] : - out_fifo_enqueueElement_0_rl[174] } : - 21'd1485482 ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1995 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[194:192] == 3'd3 : - out_fifo_enqueueElement_0_rl[194:192] == 3'd3) ? - { 16'd27306, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d878 } : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1994 ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1997 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[194:192] == 3'd1 : - out_fifo_enqueueElement_0_rl[194:192] == 3'd1) ? - { 18'd43690, - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[176:174] : - out_fifo_enqueueElement_0_rl[176:174] } : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[194:192] == 3'd2 : - out_fifo_enqueueElement_0_rl[194:192] == 3'd2) ? - { 3'd2, - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[191:174] : - out_fifo_enqueueElement_0_rl[191:174] } : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1995) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1998 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[194:192] == 3'd0 : - out_fifo_enqueueElement_0_rl[194:192] == 3'd0) ? - { 16'd2730, - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d878 } : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d1997 ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2001 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd3858 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd3858) ? - 12'd3858 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd3859 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd3859) ? - 12'd3859 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == - 12'd3860 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd3860) ? - 12'd3860 : - 12'd2303)) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2003 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd2818 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd2818) ? - 12'd2818 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd3857 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd3857) ? - 12'd3857 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2001) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2005 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd836 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd836) ? - 12'd836 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd2816 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd2816) ? - 12'd2816 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2003) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2007 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd834 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd834) ? - 12'd834 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd835 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd835) ? - 12'd835 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2005) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2009 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd832 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd832) ? - 12'd832 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd833 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd833) ? - 12'd833 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2007) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2011 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd773 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd773) ? - 12'd773 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd774 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd774) ? - 12'd774 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2009) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2013 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd771 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd771) ? - 12'd771 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd772 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd772) ? - 12'd772 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2011) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2015 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd769 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd769) ? - 12'd769 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd770 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd770) ? - 12'd770 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2013) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2017 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd384 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd384) ? - 12'd384 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd768 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd768) ? - 12'd768 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2015) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2019 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd323 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd323) ? - 12'd323 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd324 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd324) ? - 12'd324 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2017) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2021 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd321 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd321) ? - 12'd321 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd322 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd322) ? - 12'd322 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2019) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2023 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd262 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd262) ? - 12'd262 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd320 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd320) ? - 12'd320 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2021) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2025 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd260 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd260) ? - 12'd260 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd261 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd261) ? - 12'd261 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2023) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2027 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd2049 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd2049) ? - 12'd2049 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd256 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd256) ? - 12'd256 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2025) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2029 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd3074 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd3074) ? - 12'd3074 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd2048 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd2048) ? - 12'd2048 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2027) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2031 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd3072 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd3072) ? - 12'd3072 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd3073 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd3073) ? - 12'd3073 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2029) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2033 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd2 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd2) ? - 12'd2 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd3 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd3) ? - 12'd3 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2031) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2048 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[67:64] == 4'd11 : - out_fifo_enqueueElement_0_rl[67:64] == 4'd11) ? - 4'd11 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[67:64] == 4'd12 : - out_fifo_enqueueElement_0_rl[67:64] == 4'd12) ? - 4'd12 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[67:64] == 4'd13 : - out_fifo_enqueueElement_0_rl[67:64] == 4'd13) ? - 4'd13 : - 4'd15)) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2050 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[67:64] == 4'd8 : - out_fifo_enqueueElement_0_rl[67:64] == 4'd8) ? - 4'd8 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[67:64] == 4'd9 : - out_fifo_enqueueElement_0_rl[67:64] == 4'd9) ? - 4'd9 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2048) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2052 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[67:64] == 4'd6 : - out_fifo_enqueueElement_0_rl[67:64] == 4'd6) ? - 4'd6 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[67:64] == 4'd7 : - out_fifo_enqueueElement_0_rl[67:64] == 4'd7) ? - 4'd7 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2050) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2054 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[67:64] == 4'd4 : - out_fifo_enqueueElement_0_rl[67:64] == 4'd4) ? - 4'd4 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[67:64] == 4'd5 : - out_fifo_enqueueElement_0_rl[67:64] == 4'd5) ? - 4'd5 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2052) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2056 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[67:64] == 4'd2 : - out_fifo_enqueueElement_0_rl[67:64] == 4'd2) ? - 4'd2 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[67:64] == 4'd3 : - out_fifo_enqueueElement_0_rl[67:64] == 4'd3) ? - 4'd3 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2054) ; - assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2058 = - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[67:64] == 4'd0 : - out_fifo_enqueueElement_0_rl[67:64] == 4'd0) ? - 4'd0 : - ((out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[67:64] == 4'd1 : - out_fifo_enqueueElement_0_rl[67:64] == 4'd1) ? - 4'd1 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2056) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2092 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[177:175] == 3'd2 : - out_fifo_enqueueElement_1_rl[177:175] == 3'd2) ? - 3'd2 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[177:175] == 3'd3 : - out_fifo_enqueueElement_1_rl[177:175] == 3'd3) ? - 3'd3 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[177:175] == 3'd4 : - out_fifo_enqueueElement_1_rl[177:175] == 3'd4) ? - 3'd4 : - 3'd7)) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2094 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[177:175] == 3'd0 : - out_fifo_enqueueElement_1_rl[177:175] == 3'd0) ? - 3'd0 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[177:175] == 3'd1 : - out_fifo_enqueueElement_1_rl[177:175] == 3'd1) ? - 3'd1 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2092) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2097 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[194:192] == 3'd4 : - out_fifo_enqueueElement_1_rl[194:192] == 3'd4) ? - { 12'd2218, - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[182:178] : - out_fifo_enqueueElement_1_rl[182:178], - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2094, - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[174] : - out_fifo_enqueueElement_1_rl[174] } : - 21'd1485482 ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2098 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[194:192] == 3'd3 : - out_fifo_enqueueElement_1_rl[194:192] == 3'd3) ? - { 16'd27306, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1446 } : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2097 ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2100 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[194:192] == 3'd1 : - out_fifo_enqueueElement_1_rl[194:192] == 3'd1) ? - { 18'd43690, - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[176:174] : - out_fifo_enqueueElement_1_rl[176:174] } : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[194:192] == 3'd2 : - out_fifo_enqueueElement_1_rl[194:192] == 3'd2) ? - { 3'd2, - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[191:174] : - out_fifo_enqueueElement_1_rl[191:174] } : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2098) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2101 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[194:192] == 3'd0 : - out_fifo_enqueueElement_1_rl[194:192] == 3'd0) ? - { 16'd2730, - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1446 } : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2100 ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2104 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd3858 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd3858) ? - 12'd3858 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd3859 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd3859) ? - 12'd3859 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == - 12'd3860 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd3860) ? - 12'd3860 : - 12'd2303)) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2106 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd2818 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd2818) ? - 12'd2818 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd3857 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd3857) ? - 12'd3857 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2104) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2108 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd836 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd836) ? - 12'd836 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd2816 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd2816) ? - 12'd2816 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2106) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2110 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd834 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd834) ? - 12'd834 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd835 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd835) ? - 12'd835 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2108) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2112 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd832 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd832) ? - 12'd832 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd833 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd833) ? - 12'd833 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2110) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2114 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd773 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd773) ? - 12'd773 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd774 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd774) ? - 12'd774 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2112) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2116 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd771 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd771) ? - 12'd771 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd772 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd772) ? - 12'd772 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2114) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2118 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd769 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd769) ? - 12'd769 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd770 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd770) ? - 12'd770 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2116) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2120 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd384 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd384) ? - 12'd384 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd768 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd768) ? - 12'd768 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2118) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2122 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd323 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd323) ? - 12'd323 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd324 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd324) ? - 12'd324 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2120) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2124 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd321 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd321) ? - 12'd321 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd322 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd322) ? - 12'd322 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2122) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2126 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd262 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd262) ? - 12'd262 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd320 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd320) ? - 12'd320 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2124) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2128 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd260 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd260) ? - 12'd260 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd261 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd261) ? - 12'd261 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2126) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2130 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd2049 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd2049) ? - 12'd2049 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd256 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd256) ? - 12'd256 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2128) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2132 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd3074 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd3074) ? - 12'd3074 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd2048 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd2048) ? - 12'd2048 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2130) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2134 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd3072 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd3072) ? - 12'd3072 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd3073 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd3073) ? - 12'd3073 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2132) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2136 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd2 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd2) ? - 12'd2 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd3 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd3) ? - 12'd3 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2134) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2151 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[67:64] == 4'd11 : - out_fifo_enqueueElement_1_rl[67:64] == 4'd11) ? - 4'd11 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[67:64] == 4'd12 : - out_fifo_enqueueElement_1_rl[67:64] == 4'd12) ? - 4'd12 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[67:64] == 4'd13 : - out_fifo_enqueueElement_1_rl[67:64] == 4'd13) ? - 4'd13 : - 4'd15)) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2153 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[67:64] == 4'd8 : - out_fifo_enqueueElement_1_rl[67:64] == 4'd8) ? - 4'd8 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[67:64] == 4'd9 : - out_fifo_enqueueElement_1_rl[67:64] == 4'd9) ? - 4'd9 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2151) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2155 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[67:64] == 4'd6 : - out_fifo_enqueueElement_1_rl[67:64] == 4'd6) ? - 4'd6 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[67:64] == 4'd7 : - out_fifo_enqueueElement_1_rl[67:64] == 4'd7) ? - 4'd7 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2153) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2157 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[67:64] == 4'd4 : - out_fifo_enqueueElement_1_rl[67:64] == 4'd4) ? - 4'd4 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[67:64] == 4'd5 : - out_fifo_enqueueElement_1_rl[67:64] == 4'd5) ? - 4'd5 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2155) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2159 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[67:64] == 4'd2 : - out_fifo_enqueueElement_1_rl[67:64] == 4'd2) ? - 4'd2 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[67:64] == 4'd3 : - out_fifo_enqueueElement_1_rl[67:64] == 4'd3) ? - 4'd3 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2157) ; - assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2161 = - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[67:64] == 4'd0 : - out_fifo_enqueueElement_1_rl[67:64] == 4'd0) ? - 4'd0 : - ((out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[67:64] == 4'd1 : - out_fifo_enqueueElement_1_rl[67:64] == 4'd1) ? - 4'd1 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2159) ; - assign IF_IF_rg_pending_straddle_514_THEN_IF_SEL_ARR__ETC___d4011 = - j__h119769 < n_x16s__h119766 ; - assign IF_IF_rg_pending_straddle_514_THEN_IF_SEL_ARR__ETC___d4031 = - y_avValue_fst__h122004 < n_x16s__h119766 ; - assign IF_NOT_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758__ETC___d5144 = - (!SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q51) ? - 4'd1 : - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5143 ; - assign IF_NOT_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758__ETC___d5145 = - (!SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q52) ? - 4'd0 : - IF_NOT_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758__ETC___d5144 ; - assign IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5446 = - (SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719) ? - (SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165 ? - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5444 : - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5437) : - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5437 ; - assign IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5456 = - (SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719) ? - (SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165 ? - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5454 : - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5451) : - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5451 ; - assign IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5468 = - (SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719) ? - (SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165 ? - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5466 : - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5164) : - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5164 ; - assign IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5475 = - (SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719) ? - IF_SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_ETC___d5474 : - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd3 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 && - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d5434 ; - assign IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5483 = - (SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719) ? - IF_SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_ETC___d5482 : - { x__h143344, decode_pred_next_pc__h146966 } ; - assign IF_NOT_decode_180_BIT_26_211_212_AND_NOT_decod_ETC___d5253 = - (!decode___d5180[26] && !decode___d5180[6]) ? - NOT_decode_180_BITS_25_TO_21_213_EQ_decode_180_ETC___d5250 : - !decode___d5180[26] || !decode___d5180[6] || - NOT_decode_180_BITS_25_TO_21_213_EQ_decode_180_ETC___d5250 ; - assign IF_NOT_decode_180_BIT_7_192_203_OR_decode_180__ETC___d5400 = - NOT_decode_180_BIT_7_192_203_OR_decode_180_BIT_ETC___d5219 ? - ras$ras_1_first : - (NOT_decode_180_BIT_27_210_220_OR_decode_180_BI_ETC___d5227 ? - decodeBrPred___d5385[63:0] : - IF_decode_180_BIT_7_192_AND_NOT_decode_180_BIT_ETC___d5398) ; - assign IF_NOT_decode_768_BIT_26_799_800_AND_NOT_decod_ETC___d4841 = - (!decode___d4768[26] && !decode___d4768[6]) ? - NOT_decode_768_BITS_25_TO_21_801_EQ_decode_768_ETC___d4838 : - !decode___d4768[26] || !decode___d4768[6] || - NOT_decode_768_BITS_25_TO_21_801_EQ_decode_768_ETC___d4838 ; - assign IF_NOT_decode_768_BIT_7_780_791_OR_decode_768__ETC___d4988 = - NOT_decode_768_BIT_7_780_791_OR_decode_768_BIT_ETC___d4807 ? - ras$ras_0_first : - (NOT_decode_768_BIT_27_798_808_OR_decode_768_BI_ETC___d4815 ? - decodeBrPred___d4973[63:0] : - IF_decode_768_BIT_7_780_AND_NOT_decode_768_BIT_ETC___d4986) ; - assign IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4649 = - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3841 ? - 4'd11 : - (SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3862 ? - 4'd12 : - (SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3884 ? - 4'd13 : - 4'd15)) ; - assign IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4651 = - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3802 ? - 4'd8 : - (SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3821 ? - 4'd9 : - IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4649) ; - assign IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4653 = - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767 ? - 4'd6 : - (SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3784 ? - 4'd7 : - IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4651) ; - assign IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4655 = - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 ? - 4'd4 : - (SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 ? - 4'd5 : - IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4653) ; - assign IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4657 = - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 ? - 4'd2 : - (SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 ? - 4'd3 : - IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4655) ; - assign IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4659 = - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 ? - 4'd0 : - (SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 ? - 4'd1 : - IF_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_5_ETC___d4657) ; - assign IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5134 = - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q40 ? - 4'd12 : - (CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q41 ? - 4'd13 : - 4'd15) ; - assign IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5135 = - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q42 ? - 4'd11 : - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5134 ; - assign IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5136 = - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q43 ? - 4'd9 : - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5135 ; - assign IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5137 = - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q44 ? - 4'd8 : - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5136 ; - assign IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5138 = - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q45 ? - 4'd7 : - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5137 ; - assign IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5139 = - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q46 ? - 4'd6 : - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5138 ; - assign IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5140 = - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q47 ? - 4'd5 : - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5139 ; - assign IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5141 = - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q48 ? - 4'd4 : - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5140 ; - assign IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5142 = - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q49 ? - 4'd3 : - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5141 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d5704 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q13 ? - 3'd3 : - (CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q14 ? - 3'd4 : - 3'd7) ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d5705 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q15 ? - 3'd2 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d5704 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d5706 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q16 ? - 3'd1 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d5705 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d5707 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q17 ? - 3'd0 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d5706 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6112 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q141 ? - 4'd12 : - (CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q142 ? - 4'd13 : - 4'd15) ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6113 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q143 ? - 4'd11 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6112 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6114 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q144 ? - 4'd9 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6113 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6115 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q145 ? - 4'd8 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6114 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6116 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q146 ? - 4'd7 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6115 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6117 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q147 ? - 4'd6 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6116 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6118 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q148 ? - 4'd5 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6117 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6119 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q149 ? - 4'd4 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6118 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6120 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q150 ? - 4'd3 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6119 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6121 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q151 ? - 4'd2 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6120 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6122 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q152 ? - 4'd1 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6121 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6123 = - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q153 ? - 4'd0 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6122 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6184 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q34 ? - 3'd3 : - (CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q35 ? - 3'd4 : - 3'd7) ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6185 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q36 ? - 3'd2 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6184 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6186 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q37 ? - 3'd1 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6185 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6187 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q38 ? - 3'd0 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6186 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6321 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q154 ? - 4'd12 : - (CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q155 ? - 4'd13 : - 4'd15) ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6322 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q156 ? - 4'd11 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6321 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6323 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q157 ? - 4'd9 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6322 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6324 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q158 ? - 4'd8 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6323 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6325 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q159 ? - 4'd7 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6324 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6326 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q160 ? - 4'd6 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6325 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6327 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q161 ? - 4'd5 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6326 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6328 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q162 ? - 4'd4 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6327 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6329 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q163 ? - 4'd3 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6328 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6330 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q164 ? - 4'd2 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6329 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6331 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q165 ? - 4'd1 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6330 ; - assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6332 = - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q166 ? - 4'd0 : - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6331 ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4053 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b11) ? - (IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4048 ? - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4051 : - 16'd0) : - 16'd0 ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4304 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b001) ? - instr__h138587 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b101) ? - instr__h138740 : - 32'h0) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4306 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b001) ? - instr__h138231 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b101) ? - instr__h138386 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4304) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4308 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b011) ? - instr__h137033 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b111) ? - instr__h137186 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4306) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4310 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b011) ? - instr__h136677 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b111) ? - instr__h136832 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4308) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4312 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:10] == - 6'b100111 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:5] == - 2'b0) ? - instr__h136420 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:12] == - 4'b1001 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] == - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:2] == - 5'd0) ? - instr__h136580 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4310) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4314 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:10] == - 6'b100011 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:5] == - 2'b0) ? - instr__h136142 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:10] == - 6'b100111 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:5] == - 2'b01) ? - instr__h136281 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4312) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4316 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:10] == - 6'b100011 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:5] == - 2'b10) ? - instr__h135868 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:10] == - 6'b100011 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:5] == - 2'b01) ? - instr__h136005 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4314) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4319 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:12] == - 4'b1000 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:2] != - 5'd0) ? - instr__h135514 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:12] == - 4'b1001 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:2] != - 5'd0) ? - instr__h135635 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:10] == - 6'b100011 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:5] == - 2'b11) ? - instr__h135731 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4316)) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4322 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b100 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:10] == - 2'b0 && - imm6__h133600 != 6'd0) ? - instr__h135025 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b100 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:10] == - 2'b01 && - imm6__h133600 != 6'd0) ? - instr__h135215 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b100 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:10] == - 2'b10) ? - instr__h135333 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4319)) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4324 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b0 && - nzimm10__h134502 != 10'd0) ? - instr__h134664 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] != - 5'd0 && - imm6__h133600 != 6'd0) ? - instr__h134835 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4322) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4326 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b001 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] != - 5'd0) ? - instr__h134231 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b011 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] == - 5'd2 && - nzimm10__h134284 != 10'd0) ? - instr__h134491 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4324) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4327 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] != - 5'd0 && - imm6__h133600 != 6'd0 || - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] == - 5'd0 && - imm6__h133600 == 6'd0) ? - instr__h134000 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4326 ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4329 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b010 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] != - 5'd0) ? - instr__h133679 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b011 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] != - 5'd2 && - imm6__h133600 != 6'd0) ? - instr__h133868 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4327) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4331 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b110) ? - instr__h133019 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b111) ? - instr__h133338 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4329) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4333 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:12] == - 4'b1000 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:2] == - 5'd0) ? - instr__h132836 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:12] == - 4'b1001 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:2] == - 5'd0) ? - instr__h132954 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4331) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4335 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b110) ? - instr__h132152 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b101) ? - instr__h132382 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4333) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4337 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b110) ? - instr__h131761 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == - 3'b010) ? - instr__h131955 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4335) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4340 = - { (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b11) ? - (IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4048 ? - 2'd2 : - 2'd3) : - 2'd1, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4053, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044, - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == - 2'b11) ? - _theResult___snd_fst__h131373 : - y_avValue_snd_fst__h131336 } ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4346 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b11) ? - (IF_IF_rg_pending_straddle_514_THEN_IF_SEL_ARR__ETC___d4031 ? - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4344 : - 16'd0) : - 16'd0 ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4597 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b001) ? - instr__h130092 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b101) ? - instr__h130245 : - 32'h0) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4599 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b001) ? - instr__h129736 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b101) ? - instr__h129891 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4597) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4601 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b011) ? - instr__h128482 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b111) ? - instr__h128635 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4599) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4603 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b011) ? - instr__h128126 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b111) ? - instr__h128281 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4601) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4605 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:10] == - 6'b100111 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:5] == - 2'b0) ? - instr__h127869 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:12] == - 4'b1001 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] == - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:2] == - 5'd0) ? - instr__h128029 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4603) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4607 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:10] == - 6'b100011 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:5] == - 2'b0) ? - instr__h127591 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:10] == - 6'b100111 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:5] == - 2'b01) ? - instr__h127730 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4605) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4609 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:10] == - 6'b100011 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:5] == - 2'b10) ? - instr__h127317 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:10] == - 6'b100011 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:5] == - 2'b01) ? - instr__h127454 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4607) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4612 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:12] == - 4'b1000 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:2] != - 5'd0) ? - instr__h126963 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:12] == - 4'b1001 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:2] != - 5'd0) ? - instr__h127084 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:10] == - 6'b100011 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:5] == - 2'b11) ? - instr__h127180 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4609)) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4615 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b100 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:10] == - 2'b0 && - imm6__h125049 != 6'd0) ? - instr__h126474 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b100 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:10] == - 2'b01 && - imm6__h125049 != 6'd0) ? - instr__h126664 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b100 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:10] == - 2'b10) ? - instr__h126782 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4612)) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4617 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b0 && - nzimm10__h125951 != 10'd0) ? - instr__h126113 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] != - 5'd0 && - imm6__h125049 != 6'd0) ? - instr__h126284 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4615) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4619 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b001 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] != - 5'd0) ? - instr__h125680 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b011 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] == - 5'd2 && - nzimm10__h125733 != 10'd0) ? - instr__h125940 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4617) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4620 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] != - 5'd0 && - imm6__h125049 != 6'd0 || - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] == - 5'd0 && - imm6__h125049 == 6'd0) ? - instr__h125449 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4619 ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4622 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b010 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] != - 5'd0) ? - instr__h125128 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b011 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] != - 5'd2 && - imm6__h125049 != 6'd0) ? - instr__h125317 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4620) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4624 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b110) ? - instr__h124468 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b111) ? - instr__h124787 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4622) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4626 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:12] == - 4'b1000 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:2] == - 5'd0) ? - instr__h124285 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:12] == - 4'b1001 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] != - 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:2] == - 5'd0) ? - instr__h124403 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4624) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4628 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b110) ? - instr__h123598 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b01 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b101) ? - instr__h123829 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4626) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4630 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b110) ? - instr__h123207 : - ((SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == - 3'b010) ? - instr__h123401 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4628) ; - assign IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4633 = - { (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b11) ? - (IF_IF_rg_pending_straddle_514_THEN_IF_SEL_ARR__ETC___d4031 ? - 2'd2 : - 2'd3) : - 2'd1, - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4346, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028, - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == - 2'b11) ? - _theResult___snd_fst__h122365 : - y_avValue_snd_fst__h122334 } ; - assign IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4012 = - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3963 ? - 32'd0 : - value__h119455 ; - assign IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4020 = - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3981 ? - 32'd0 : - value__h119609 ; - assign IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5007 = - (SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d4768[0]) ? - ((decode___d4768[99:95] == 5'd10) ? - dirPred$pred_0_pred[23:0] : - 24'hAAAAAA) : - 24'hAAAAAA ; - assign IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5143 = - (SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 || - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q50) ? - 4'd2 : - IF_SEL_ARR_IF_f32d_data_0_678_BITS_73_TO_70_02_ETC___d5142 ; - assign IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5161 = - (SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d4768[0]) ? - IF_IF_decode_768_BITS_99_TO_95_772_EQ_8_779_AN_ETC___d5160 : - decode_epoch ; - assign IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5411 = - (SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d5180[0]) ? - ((decode___d5180[99:95] == 5'd10) ? - dirPred$pred_1_pred[23:0] : - 24'hAAAAAA) : - 24'hAAAAAA ; - assign IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5444 = - (SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d5180[0]) ? - IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5443 : - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5437 ; - assign IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5454 = - (SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d5180[0]) ? - IF_IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AN_ETC___d5453 : - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5451 ; - assign IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5460 = - (SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d4768[0]) ? - IF_IF_decode_768_BITS_99_TO_95_772_EQ_8_779_AN_ETC___d5459 : - !decode_epoch ; - assign IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5466 = - (SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d5180[0]) ? - IF_IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AN_ETC___d5465 : - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5164 ; - assign IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5473 = - (SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d5180[0]) ? - IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5472 : - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd3 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 && - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d5434 ; - assign IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5481 = - (SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d5180[0]) ? - IF_IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AN_ETC___d5480 : - { x__h143344, decode_pred_next_pc__h146966 } ; - assign IF_SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_ETC___d5474 = - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165 ? - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5473 : - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd3 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 && - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d5434 ; - assign IF_SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_ETC___d5482 = - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165 ? - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5481 : - { x__h143344, decode_pred_next_pc__h146966 } ; - assign IF_SEL_ARR_instdata_data_0_686_BITS_195_TO_194_ETC___d5447 = - (SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 == - 2'd3 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719) ? - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165 || - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5437 : - IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5446 ; - assign IF_SEL_ARR_instdata_data_0_686_BITS_195_TO_194_ETC___d5476 = - (SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 == - 2'd3 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719) ? - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd3 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 && - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d5434 : - IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5475 ; - assign IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5437 = - (SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 == - 2'd3) ? - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 : - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 && - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d5434 ; - assign IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5451 = - (SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 == - 2'd3) ? - next_PC__h143443 : - decode_pred_next_pc__h146966 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5710 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q167 ? - { 12'd2218, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5708 } : - 21'd1485482 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5711 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q168 ? - { 16'd27306, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5651 } : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5710 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5712 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q169 ? - { 3'd2, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q170, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5637 } : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5711 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5713 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q171 ? - { 18'd43690, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q172 } : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5712 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5714 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q173 ? - { 16'd2730, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q174 } : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5713 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5869 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q69 ? - 12'd3859 : - (CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q70 ? - 12'd3860 : - 12'd2303) ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5870 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q71 ? - 12'd3858 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5869 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5871 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q72 ? - 12'd3857 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5870 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5872 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q73 ? - 12'd2818 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5871 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5873 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q74 ? - 12'd2816 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5872 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5874 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q75 ? - 12'd836 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5873 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5875 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q76 ? - 12'd835 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5874 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5876 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q77 ? - 12'd834 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5875 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5877 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q78 ? - 12'd833 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5876 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5878 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q79 ? - 12'd832 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5877 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5879 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q80 ? - 12'd774 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5878 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5880 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q81 ? - 12'd773 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5879 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5881 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q82 ? - 12'd772 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5880 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5882 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q83 ? - 12'd771 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5881 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5883 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q84 ? - 12'd770 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5882 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5884 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q85 ? - 12'd769 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5883 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5885 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q86 ? - 12'd768 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5884 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5886 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q87 ? - 12'd384 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5885 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5887 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q88 ? - 12'd324 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5886 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5888 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q89 ? - 12'd323 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5887 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5889 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q90 ? - 12'd322 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5888 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5890 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q91 ? - 12'd321 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5889 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5891 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q92 ? - 12'd320 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5890 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5892 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q93 ? - 12'd262 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5891 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5893 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q94 ? - 12'd261 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5892 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5894 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q95 ? - 12'd260 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5893 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5895 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q96 ? - 12'd256 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5894 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5896 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q97 ? - 12'd2049 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5895 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5897 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q98 ? - 12'd2048 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5896 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5898 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q99 ? - 12'd3074 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5897 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5899 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q100 ? - 12'd3073 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5898 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5900 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q101 ? - 12'd3072 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5899 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5901 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q102 ? - 12'd3 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5900 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5902 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q103 ? - 12'd2 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5901 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5903 = - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q104 ? - 12'd1 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5902 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6190 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q178 ? - { 12'd2218, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6188 } : - 21'd1485482 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6191 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q179 ? - { 16'd27306, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6174 } : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6190 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6192 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q180 ? - { 3'd2, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q181, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6169 } : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6191 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6193 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q182 ? - { 18'd43690, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183 } : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6192 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6194 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q184 ? - { 16'd2730, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q185 } : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6193 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6234 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q105 ? - 12'd3859 : - (CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q106 ? - 12'd3860 : - 12'd2303) ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6235 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q107 ? - 12'd3858 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6234 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6236 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q108 ? - 12'd3857 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6235 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6237 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q109 ? - 12'd2818 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6236 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6238 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q110 ? - 12'd2816 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6237 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6239 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q111 ? - 12'd836 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6238 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6240 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q112 ? - 12'd835 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6239 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6241 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q113 ? - 12'd834 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6240 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6242 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q114 ? - 12'd833 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6241 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6243 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q115 ? - 12'd832 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6242 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6244 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q116 ? - 12'd774 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6243 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6245 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q117 ? - 12'd773 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6244 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6246 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q118 ? - 12'd772 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6245 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6247 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q119 ? - 12'd771 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6246 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6248 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q120 ? - 12'd770 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6247 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6249 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q121 ? - 12'd769 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6248 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6250 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q122 ? - 12'd768 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6249 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6251 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q123 ? - 12'd384 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6250 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6252 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q124 ? - 12'd324 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6251 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6253 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q125 ? - 12'd323 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6252 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6254 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q126 ? - 12'd322 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6253 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6255 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q127 ? - 12'd321 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6254 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6256 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q128 ? - 12'd320 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6255 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6257 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q129 ? - 12'd262 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6256 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6258 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q130 ? - 12'd261 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6257 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6259 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q131 ? - 12'd260 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6258 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6260 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q132 ? - 12'd256 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6259 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6261 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q133 ? - 12'd2049 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6260 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6262 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q134 ? - 12'd2048 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6261 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6263 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q135 ? - 12'd3074 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6262 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6264 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q136 ? - 12'd3073 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6263 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6265 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q137 ? - 12'd3072 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6264 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6266 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q138 ? - 12'd3 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6265 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6267 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q139 ? - 12'd2 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6266 ; - assign IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6268 = - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q140 ? - 12'd1 : - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6267 ; - assign IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5394 = - (decode___d5180[99:95] == 5'd8 && decode___d5180[7] && - !decode___d5180[6] && - (decode___d5180[5:1] == 5'd1 || decode___d5180[5:1] == 5'd5)) ? - decodeBrPred___d5385[64] : - ((decode___d5180[99:95] == 5'd9) ? - NOT_decode_180_BIT_7_192_203_OR_decode_180_BIT_ETC___d5392 : - decodeBrPred___d5385[64]) ; - assign IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5443 = - IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5394 && - decode_pred_next_pc__h153837 != in_ppc__h150788 || - ((SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 == - 2'd3) ? - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 : - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 && - NOT_decode_768_BIT_0_769_770_AND_IF_decode_768_ETC___d5439) ; - assign IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5472 = - IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5394 && - decode_pred_next_pc__h153837 != in_ppc__h150788 || - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd3 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 && - NOT_decode_768_BIT_0_769_770_AND_IF_decode_768_ETC___d5439 ; - assign IF_decode_180_BIT_7_192_AND_NOT_decode_180_BIT_ETC___d5398 = - decode_180_BIT_7_192_AND_NOT_decode_180_BIT_6__ETC___d5228 ? - (IF_NOT_decode_180_BIT_26_211_212_AND_NOT_decod_ETC___d5253 ? - ras$ras_1_first : - decodeBrPred___d5385[63:0]) : - decodeBrPred___d5385[63:0] ; - assign IF_decode_768_BITS_99_TO_95_772_EQ_8_779_AND_d_ETC___d4982 = - (decode___d4768[99:95] == 5'd8 && decode___d4768[7] && - !decode___d4768[6] && - (decode___d4768[5:1] == 5'd1 || decode___d4768[5:1] == 5'd5)) ? - decodeBrPred___d4973[64] : - ((decode___d4768[99:95] == 5'd9) ? - NOT_decode_768_BIT_7_780_791_OR_decode_768_BIT_ETC___d4980 : - decodeBrPred___d4973[64]) ; - assign IF_decode_768_BIT_7_780_AND_NOT_decode_768_BIT_ETC___d4986 = - decode_768_BIT_7_780_AND_NOT_decode_768_BIT_6__ETC___d4816 ? - (IF_NOT_decode_768_BIT_26_799_800_AND_NOT_decod_ETC___d4841 ? - ras$ras_0_first : - decodeBrPred___d4973[63:0]) : - decodeBrPred___d4973[63:0] ; - assign IF_f12f2_deqReq_dummy2_2_read__2_AND_IF_f12f2__ETC___d80 = - _theResult_____2__h7993 == v__h7269 ; - assign IF_f12f2_deqReq_lat_1_whas__3_THEN_f12f2_deqRe_ETC___d49 = - WILL_FIRE_RL_doFetch2 || f12f2_deqReq_rl ; - assign IF_f12f2_enqReq_lat_1_whas__4_THEN_f12f2_enqRe_ETC___d23 = - WILL_FIRE_RL_doFetch1 ? - f12f2_enqReq_lat_0$wget[134] : - f12f2_enqReq_rl[134] ; - assign IF_f22f3_deqReq_dummy2_2_read__19_AND_IF_f22f3_ETC___d332 = - _theResult_____2__h19260 == v__h15956 ; - assign IF_f22f3_deqReq_lat_1_whas__94_THEN_f22f3_deqR_ETC___d300 = - WILL_FIRE_RL_doFetch3 || f22f3_deqReq_rl ; - assign IF_f22f3_enqReq_lat_0_whas__14_THEN_IF_f22f3_e_ETC___d400 = - WILL_FIRE_RL_doFetch2 ? - CASE_f22f3_enqReq_lat_0wget_BITS_73_TO_70_0_f_ETC__q216 : - CASE_f22f3_enqReq_rl_BITS_73_TO_70_0_f22f3_enq_ETC__q217 ; - assign IF_f22f3_enqReq_lat_1_whas__11_THEN_NOT_f22f3__ETC___d127 = - WILL_FIRE_RL_doFetch2 ? - !f22f3_enqReq_lat_0$wget[268] : - !f22f3_enqReq_rl[268] ; - assign IF_f22f3_enqReq_lat_1_whas__11_THEN_f22f3_enqR_ETC___d120 = - WILL_FIRE_RL_doFetch2 ? - f22f3_enqReq_lat_0$wget[268] : - f22f3_enqReq_rl[268] ; - assign IF_f32d_deqReq_dummy2_2_read__55_AND_IF_f32d_d_ETC___d663 = - _theResult_____2__h28906 == v__h27080 ; - assign IF_f32d_deqReq_lat_1_whas__26_THEN_f32d_deqReq_ETC___d632 = - CAN_FIRE_RL_doDecode || f32d_deqReq_rl ; - assign IF_f32d_enqReq_lat_0_whas__46_THEN_IF_f32d_enq_ETC___d732 = - f32d_enqReq_lat_0$whas ? - CASE_f32d_enqReq_lat_0wget_BITS_73_TO_70_0_f3_ETC__q219 : - CASE_f32d_enqReq_rl_BITS_73_TO_70_0_f32d_enqRe_ETC__q220 ; - assign IF_f32d_enqReq_lat_1_whas__43_THEN_NOT_f32d_en_ETC___d459 = - f32d_enqReq_lat_0$whas ? - !f32d_enqReq_lat_0$wget[268] : - !f32d_enqReq_rl[268] ; - assign IF_f32d_enqReq_lat_1_whas__43_THEN_f32d_enqReq_ETC___d452 = - f32d_enqReq_lat_0$whas ? - f32d_enqReq_lat_0$wget[268] : - f32d_enqReq_rl[268] ; - assign IF_iTlb_to_proc_response_get_369_BIT_4_370_THE_ETC___d3465 = - { x__h116716, - !iTlb$to_proc_response_get[4] && mmio$getFetchTarget == 2'd1, - CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q203, - out_main_epoch__h116425 } ; - assign IF_instdata_deqP_lat_0_whas__77_THEN_instdata__ETC___d780 = - CAN_FIRE_RL_doDecode ? upd__h139977 : instdata_deqP_rl ; - assign IF_out_fifo_dequeueFifo_lat_1_whas__14_THEN_ou_ETC___d820 = - out_fifo_dequeueFifo_lat_1$whas ? - upd__h39683 : - (out_fifo_dequeueFifo_lat_0$whas ? - upd__h39710 : - out_fifo_dequeueFifo_rl) ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1217 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[127:96] : - out_fifo_enqueueElement_0_rl[127:96] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1222 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[95] : - out_fifo_enqueueElement_0_rl[95] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1232 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[94:89] : - out_fifo_enqueueElement_0_rl[94:89] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1238 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[88] : - out_fifo_enqueueElement_0_rl[88] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1248 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[87:82] : - out_fifo_enqueueElement_0_rl[87:82] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1255 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[81] : - out_fifo_enqueueElement_0_rl[81] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1265 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[80:76] : - out_fifo_enqueueElement_0_rl[80:76] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1271 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[75] : - out_fifo_enqueueElement_0_rl[75] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1281 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[74:69] : - out_fifo_enqueueElement_0_rl[74:69] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1289 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[68] : - out_fifo_enqueueElement_0_rl[68] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d1381 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[63:0] : - out_fifo_enqueueElement_0_rl[63:0] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d2037 = - { out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[173] : - out_fifo_enqueueElement_0_rl[173], - (out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[172:161] == 12'd1 : - out_fifo_enqueueElement_0_rl[172:161] == 12'd1) ? - 12'd1 : - IF_IF_out_fifo_enqueueElement_0_lat_0_whas__25_ETC___d2033, - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[160] : - out_fifo_enqueueElement_0_rl[160], - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[159:128] : - out_fifo_enqueueElement_0_rl[159:128] } ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d830 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[388] : - out_fifo_enqueueElement_0_rl[388] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d840 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[387:324] : - out_fifo_enqueueElement_0_rl[387:324] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d845 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[323:260] : - out_fifo_enqueueElement_0_rl[323:260] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d850 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[259:256] : - out_fifo_enqueueElement_0_rl[259:256] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d855 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[255:232] : - out_fifo_enqueueElement_0_rl[255:232] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d860 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[231:200] : - out_fifo_enqueueElement_0_rl[231:200] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d865 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[199:195] : - out_fifo_enqueueElement_0_rl[199:195] ; - assign IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d878 = - out_fifo_enqueueElement_0_lat_0$whas ? - out_fifo_enqueueElement_0_lat_0$wget[178:174] : - out_fifo_enqueueElement_0_rl[178:174] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1398 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[388] : - out_fifo_enqueueElement_1_rl[388] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1408 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[387:324] : - out_fifo_enqueueElement_1_rl[387:324] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1413 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[323:260] : - out_fifo_enqueueElement_1_rl[323:260] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1418 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[259:256] : - out_fifo_enqueueElement_1_rl[259:256] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1423 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[255:232] : - out_fifo_enqueueElement_1_rl[255:232] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1428 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[231:200] : - out_fifo_enqueueElement_1_rl[231:200] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1433 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[199:195] : - out_fifo_enqueueElement_1_rl[199:195] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1446 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[178:174] : - out_fifo_enqueueElement_1_rl[178:174] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1784 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[127:96] : - out_fifo_enqueueElement_1_rl[127:96] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1789 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[95] : - out_fifo_enqueueElement_1_rl[95] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1799 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[94:89] : - out_fifo_enqueueElement_1_rl[94:89] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1805 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[88] : - out_fifo_enqueueElement_1_rl[88] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1815 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[87:82] : - out_fifo_enqueueElement_1_rl[87:82] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1822 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[81] : - out_fifo_enqueueElement_1_rl[81] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1832 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[80:76] : - out_fifo_enqueueElement_1_rl[80:76] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1838 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[75] : - out_fifo_enqueueElement_1_rl[75] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1848 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[74:69] : - out_fifo_enqueueElement_1_rl[74:69] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1856 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[68] : - out_fifo_enqueueElement_1_rl[68] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1948 = - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[63:0] : - out_fifo_enqueueElement_1_rl[63:0] ; - assign IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d2140 = - { out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[173] : - out_fifo_enqueueElement_1_rl[173], - (out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[172:161] == 12'd1 : - out_fifo_enqueueElement_1_rl[172:161] == 12'd1) ? - 12'd1 : - IF_IF_out_fifo_enqueueElement_1_lat_0_whas__39_ETC___d2136, - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[160] : - out_fifo_enqueueElement_1_rl[160], - out_fifo_enqueueElement_1_dummy_1_0$wget ? - out_fifo_enqueueElement_1_lat_0$wget[159:128] : - out_fifo_enqueueElement_1_rl[159:128] } ; - assign IF_out_fifo_enqueueFifo_lat_1_whas__04_THEN_ou_ETC___d810 = - out_fifo_enqueueFifo_lat_1$whas ? - upd__h38127 : - (out_fifo_enqueueFifo_lat_0$whas ? - upd__h38154 : - out_fifo_enqueueFifo_rl) ; - assign IF_out_fifo_willDequeue_0_lat_0_whas__959_THEN_ETC___d1962 = - EN_pipelines_0_deq || out_fifo_willDequeue_0_rl ; - assign IF_out_fifo_willDequeue_1_lat_0_whas__966_THEN_ETC___d1969 = - EN_pipelines_1_deq || out_fifo_willDequeue_1_rl ; - assign IF_pc_reg_dummy2_0_read__063_AND_pc_reg_dummy2_ETC___d3337 = - x__h115849 + 64'd4 ; - assign IF_pc_reg_lat_1_whas_THEN_pc_reg_lat_1_wget_EL_ETC___d9 = - pc_reg_dummy_1_0$whas ? - upd__h1659 : - (pc_reg_lat_0$whas ? upd__h1686 : pc_reg_rl) ; - assign IF_perfReqQ_enqReq_lat_1_whas__977_THEN_perfRe_ETC___d2986 = - EN_perf_req ? - perfReqQ_enqReq_lat_0$wget[2] : - perfReqQ_enqReq_rl[2] ; - assign IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4015 = - rg_pending_straddle ? - (SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 ? - 16'd0 : - IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4012[15:0]) : - IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4012[15:0] ; - assign IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4019 = - rg_pending_straddle ? - (SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 ? - rg_half_inst_lsbs : - IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4012[31:16]) : - IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4012[31:16] ; - assign IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4023 = - rg_pending_straddle ? - (SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 ? - IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4012[15:0] : - IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4020[15:0]) : - IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4020[15:0] ; - assign IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4026 = - rg_pending_straddle ? - (SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 ? - IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4012[31:16] : - IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4020[31:16]) : - IF_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_ETC___d4020[31:16] ; - assign NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3773 = - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 && - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767 ; - assign NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3790 = - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767 && - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3784 ; - assign NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3808 = - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3784 && - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3802 ; - assign NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3827 = - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3784 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3802 && - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3821 ; - assign NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3847 = - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3784 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3802 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3821 && - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3841 ; - assign NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3868 = - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3784 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3802 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3821 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3841 && - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3862 ; - assign NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3890 = - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3784 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3802 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3821 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3841 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3862 && - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3884 ; - assign NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3896 = - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 && - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3890 ; - assign NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3907 = - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3784 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3802 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3821 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3841 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3862 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3884 ; - assign NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3913 = - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 && - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3907 ; - assign NOT_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_47_ETC___d3757 = - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 && - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 ; - assign NOT_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_47_ETC___d3874 = - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 && - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3868 ; - assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d5917 = - { !CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q175, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5903, - !CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q176, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q177 } ; - assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d5996 = - { !CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q59, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q60, - !CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q61, - !CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q62, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q63 } ; - assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d5997 = - { !CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q189, - !CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q190, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q191, - !CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q192, - !CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q193, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q194, - NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d5996 } ; - assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6129 = - { !CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q195, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6123, - x__h167949 } ; - assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6274 = - { !CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q186, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6268, - !CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q187, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q188 } ; - assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6303 = - { !CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q64, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q65, - !CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q66, - !CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q67, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q68 } ; - assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6304 = - { !CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q196, - !CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q197, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q198, - !CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q199, - !CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q200, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q201, - NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6303 } ; - assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6335 = - { !CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q202, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6332, - x__h174427 } ; - assign NOT_SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_5_ETC___d3742 = - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 && - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 ; - assign NOT_SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_5_ETC___d3853 = - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 && - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3847 ; - assign NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_19_ETC___d5188 = - SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165 && - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d5180[0] && - decode___d5180[99:95] == 5'd10 ; - assign NOT_decode_180_BITS_25_TO_21_213_EQ_decode_180_ETC___d5250 = - decode___d5180[25:21] != decode___d5180[5:1] ; - assign NOT_decode_180_BIT_27_210_220_OR_decode_180_BI_ETC___d5227 = - (!decode___d5180[27] || - (decode___d5180[26] || decode___d5180[25:21] != 5'd1) && - (decode___d5180[26] || decode___d5180[25:21] != 5'd5)) && - decode___d5180[7] && - !decode___d5180[6] && - (decode___d5180[5:1] == 5'd1 || decode___d5180[5:1] == 5'd5) ; - assign NOT_decode_180_BIT_7_192_203_OR_decode_180_BIT_ETC___d5219 = - (!decode___d5180[7] || - (decode___d5180[6] || decode___d5180[5:1] != 5'd1) && - (decode___d5180[6] || decode___d5180[5:1] != 5'd5)) && - decode___d5180[27] && - !decode___d5180[26] && - (decode___d5180[25:21] == 5'd1 || - decode___d5180[25:21] == 5'd5) ; - assign NOT_decode_180_BIT_7_192_203_OR_decode_180_BIT_ETC___d5392 = - (!decode___d5180[7] || - (decode___d5180[6] || decode___d5180[5:1] != 5'd1) && - (decode___d5180[6] || decode___d5180[5:1] != 5'd5)) && - decode___d5180[27] && - !decode___d5180[26] && - (decode___d5180[25:21] == 5'd1 || - decode___d5180[25:21] == 5'd5) || - (NOT_decode_180_BIT_27_210_220_OR_decode_180_BI_ETC___d5227 ? - decodeBrPred___d5385[64] : - (decode_180_BIT_7_192_AND_NOT_decode_180_BIT_6__ETC___d5228 ? - IF_NOT_decode_180_BIT_26_211_212_AND_NOT_decod_ETC___d5253 || - decodeBrPred___d5385[64] : - decodeBrPred___d5385[64])) ; - assign NOT_decode_768_BITS_25_TO_21_801_EQ_decode_768_ETC___d4838 = - decode___d4768[25:21] != decode___d4768[5:1] ; - assign NOT_decode_768_BIT_0_769_770_AND_IF_decode_768_ETC___d5439 = - !decode___d4768[0] && - IF_decode_768_BITS_99_TO_95_772_EQ_8_779_AND_d_ETC___d4982 && - decode_pred_next_pc__h146966 != in_ppc__h143612 ; - assign NOT_decode_768_BIT_27_798_808_OR_decode_768_BI_ETC___d4815 = - (!decode___d4768[27] || - (decode___d4768[26] || decode___d4768[25:21] != 5'd1) && - (decode___d4768[26] || decode___d4768[25:21] != 5'd5)) && - decode___d4768[7] && - !decode___d4768[6] && - (decode___d4768[5:1] == 5'd1 || decode___d4768[5:1] == 5'd5) ; - assign NOT_decode_768_BIT_7_780_791_OR_decode_768_BIT_ETC___d4807 = - (!decode___d4768[7] || - (decode___d4768[6] || decode___d4768[5:1] != 5'd1) && - (decode___d4768[6] || decode___d4768[5:1] != 5'd5)) && - decode___d4768[27] && - !decode___d4768[26] && - (decode___d4768[25:21] == 5'd1 || - decode___d4768[25:21] == 5'd5) ; - assign NOT_decode_768_BIT_7_780_791_OR_decode_768_BIT_ETC___d4980 = - (!decode___d4768[7] || - (decode___d4768[6] || decode___d4768[5:1] != 5'd1) && - (decode___d4768[6] || decode___d4768[5:1] != 5'd5)) && - decode___d4768[27] && - !decode___d4768[26] && - (decode___d4768[25:21] == 5'd1 || - decode___d4768[25:21] == 5'd5) || - (NOT_decode_768_BIT_27_798_808_OR_decode_768_BI_ETC___d4815 ? - decodeBrPred___d4973[64] : - (decode_768_BIT_7_780_AND_NOT_decode_768_BIT_6__ETC___d4816 ? - IF_NOT_decode_768_BIT_26_799_800_AND_NOT_decod_ETC___d4841 || - decodeBrPred___d4973[64] : - decodeBrPred___d4973[64])) ; - assign NOT_f12f2_clearReq_dummy2_1_read__8_9_OR_IF_f1_ETC___d63 = - !f12f2_clearReq_dummy2_1$Q_OUT || !f12f2_clearReq_rl ; - assign NOT_f12f2_enqReq_dummy2_2_read__4_4_OR_IF_f12f_ETC___d98 = - (!f12f2_enqReq_dummy2_2$Q_OUT || - (WILL_FIRE_RL_doFetch1 ? - !f12f2_enqReq_lat_0$wget[134] : - !f12f2_enqReq_rl[134])) && - (f12f2_deqReq_dummy2_2$Q_OUT && - IF_f12f2_deqReq_lat_1_whas__3_THEN_f12f2_deqRe_ETC___d49 || - f12f2_empty) ; - assign NOT_f22f3_clearReq_dummy2_1_read__09_27_OR_IF__ETC___d331 = - !f22f3_clearReq_dummy2_1$Q_OUT || !f22f3_clearReq_rl ; - assign NOT_f22f3_enqReq_dummy2_2_read__11_45_OR_IF_f2_ETC___d349 = - (!f22f3_enqReq_dummy2_2$Q_OUT || - IF_f22f3_enqReq_lat_1_whas__11_THEN_NOT_f22f3__ETC___d127) && - (f22f3_deqReq_dummy2_2$Q_OUT && - IF_f22f3_deqReq_lat_1_whas__94_THEN_f22f3_deqR_ETC___d300 || - f22f3_empty) ; - assign NOT_f22f3_enqReq_dummy2_2_read__11_45_OR_IF_f2_ETC___d431 = - { !f22f3_enqReq_dummy2_2$Q_OUT || - IF_f22f3_enqReq_lat_1_whas__11_THEN_NOT_f22f3__ETC___d127 || - (WILL_FIRE_RL_doFetch2 ? - f22f3_enqReq_lat_0$wget[74] : - f22f3_enqReq_rl[74]), - CASE_IF_f22f3_enqReq_lat_0_whas__14_THEN_IF_f2_ETC__q218, - WILL_FIRE_RL_doFetch2 ? - f22f3_enqReq_lat_0$wget[69:0] : - f22f3_enqReq_rl[69:0] } ; - assign NOT_f32d_clearReq_dummy2_1_read__41_42_OR_IF_f_ETC___d646 = - !f32d_clearReq_dummy2_1$Q_OUT || !f32d_clearReq_rl ; - assign NOT_f32d_enqReq_dummy2_2_read__47_77_OR_IF_f32_ETC___d681 = - (!f32d_enqReq_dummy2_2$Q_OUT || - IF_f32d_enqReq_lat_1_whas__43_THEN_NOT_f32d_en_ETC___d459) && - (f32d_deqReq_dummy2_2$Q_OUT && - IF_f32d_deqReq_lat_1_whas__26_THEN_f32d_deqReq_ETC___d632 || - f32d_empty) ; - assign NOT_f32d_enqReq_dummy2_2_read__47_77_OR_IF_f32_ETC___d763 = - { !f32d_enqReq_dummy2_2$Q_OUT || - IF_f32d_enqReq_lat_1_whas__43_THEN_NOT_f32d_en_ETC___d459 || + 3'd0) : + 3'd0 ; + assign IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d6665 = + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196 ? + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d6664 : + SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 ; + assign IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d7548 = + (IF_decode_047_BITS_171_TO_167_051_EQ_8_057_AND_ETC___d7413 && + decode_pred_next_pc__h177047 != in_ppc__h171466) ^ + decode_epoch_rl ; + assign IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d7983 = + !((IF_decode_047_BITS_171_TO_167_051_EQ_8_057_AND_ETC___d7413 && + decode_pred_next_pc__h177047 != in_ppc__h171466) ^ + decode_epoch_rl) ; + assign IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d8000 = + (IF_decode_047_BITS_171_TO_167_051_EQ_8_057_AND_ETC___d7413 && + decode_pred_next_pc__h177047 != in_ppc__h171466) ? + SEL_ARR_NOT_f32d_data_0_979_BIT_75_991_992_NOT_ETC___d7996 || + SEL_ARR_f32d_data_0_979_BIT_75_991_f32d_data_1_ETC___d7998 : + SEL_ARR_f32d_data_0_979_BIT_75_991_f32d_data_1_ETC___d7998 ; + assign IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d8028 = + (IF_decode_047_BITS_171_TO_167_051_EQ_8_057_AND_ETC___d7413 && + decode_pred_next_pc__h177047 != in_ppc__h171466) ? + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_75_991_992__ETC___d8027 : + { x__h171664, nextPc__h193173 } ; + assign IF_IF_decode_558_BITS_171_TO_167_562_EQ_8_568__ETC___d7979 = + (IF_decode_558_BITS_171_TO_167_562_EQ_8_568_AND_ETC___d7924 && + decode_pred_next_pc__h187627 != in_ppc__h182302) ? + decode_pred_next_pc__h187627 : + decode_pred_next_pc__h177047 ; + assign IF_IF_decode_558_BITS_171_TO_167_562_EQ_8_568__ETC___d7987 = + (IF_decode_558_BITS_171_TO_167_562_EQ_8_568_AND_ETC___d7924 && + decode_pred_next_pc__h187627 != in_ppc__h182302) ? + ((SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 == + 2'd0) ? + !decode_epoch_rl : + IF_SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_ETC___d7985) : + IF_SEL_ARR_instdata_data_0_987_BITS_65_TO_64_9_ETC___d7551 ; + assign IF_IF_decode_558_BITS_171_TO_167_562_EQ_8_568__ETC___d8005 = + (IF_decode_558_BITS_171_TO_167_562_EQ_8_568_AND_ETC___d7924 && + decode_pred_next_pc__h187627 != in_ppc__h182302) ? + SEL_ARR_NOT_f32d_data_0_979_BIT_75_991_992_NOT_ETC___d7996 || + NOT_SEL_ARR_instdata_data_0_987_BITS_65_TO_64__ETC___d8003 : + NOT_SEL_ARR_instdata_data_0_987_BITS_65_TO_64__ETC___d8003 ; + assign IF_IF_decode_558_BITS_171_TO_167_562_EQ_8_568__ETC___d8029 = + (IF_decode_558_BITS_171_TO_167_562_EQ_8_568_AND_ETC___d7924 && + decode_pred_next_pc__h187627 != in_ppc__h182302) ? + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_75_991_992__ETC___d8021 : + IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d8028 ; + assign IF_IF_f12f2_deqReq_lat_1_whas__13_THEN_f12f2_d_ETC___d143 = + _theResult_____2__h6605 == v__h5669 ; + assign IF_IF_f12f2_deqReq_lat_1_whas__13_THEN_f12f2_d_ETC___d152 = + IF_IF_f12f2_deqReq_lat_1_whas__13_THEN_f12f2_d_ETC___d143 && + (IF_f12f2_enqReq_lat_1_whas__6_THEN_f12f2_enqRe_ETC___d55 || + !WILL_FIRE_RL_doFetch2 && !f12f2_deqReq_rl && f12f2_full) ; + assign IF_IF_f22f3_deqReq_lat_1_whas__76_THEN_f22f3_d_ETC___d406 = + _theResult_____2__h14823 == v__h10967 ; + assign IF_IF_f22f3_deqReq_lat_1_whas__76_THEN_f22f3_d_ETC___d415 = + IF_IF_f22f3_deqReq_lat_1_whas__76_THEN_f22f3_d_ETC___d406 && + (IF_f22f3_enqReq_lat_1_whas__77_THEN_f22f3_enqR_ETC___d186 || + !f22f3_deqReq_lat_0$whas && !f22f3_deqReq_rl && f22f3_full) ; + assign IF_IF_f32d_deqReq_lat_1_whas__11_THEN_f32d_deq_ETC___d741 = + _theResult_____2__h20522 == v__h18830 ; + assign IF_IF_f32d_deqReq_lat_1_whas__11_THEN_f32d_deq_ETC___d750 = + IF_IF_f32d_deqReq_lat_1_whas__11_THEN_f32d_deq_ETC___d741 && + (IF_f32d_enqReq_lat_1_whas__20_THEN_f32d_enqReq_ETC___d529 || + !CAN_FIRE_RL_doDecode && !f32d_deqReq_rl && f32d_full) ; + assign IF_IF_f32d_enqReq_lat_1_whas__20_THEN_NOT_f32d_ETC___d842 = + { x__h19215, + f32d_enqReq_lat_0$whas ? + f32d_enqReq_lat_0$wget[75] : + f32d_enqReq_rl[75], + IF_f32d_enqReq_lat_1_whas__20_THEN_NOT_f32d_en_ETC___d536 || (f32d_enqReq_lat_0$whas ? f32d_enqReq_lat_0$wget[74] : f32d_enqReq_rl[74]), - CASE_IF_f32d_enqReq_lat_0_whas__46_THEN_IF_f32_ETC__q221, + CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388, f32d_enqReq_lat_0$whas ? - f32d_enqReq_lat_0$wget[69:0] : - f32d_enqReq_rl[69:0] } ; - assign NOT_instdata_full_dummy2_1_read__505_506_OR_NO_ETC___d3536 = - (!instdata_full_dummy2_1$Q_OUT || - !instdata_full_dummy2_2$Q_OUT || - CAN_FIRE_RL_doDecode || - !instdata_full_rl) && - (rg_pending_straddle ? - SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 || - f22f3_empty_47_OR_NOT_SEL_ARR_NOT_f22f3_data_0_ETC___d3495 : - f22f3_empty_47_OR_NOT_SEL_ARR_NOT_f22f3_data_0_ETC___d3495) ; - assign NOT_perfReqQ_clearReq_dummy2_1_read__021_022_O_ETC___d3026 = - !perfReqQ_clearReq_dummy2_1$Q_OUT || !perfReqQ_clearReq_rl ; - assign NOT_perfReqQ_enqReq_dummy2_2_read__027_042_OR__ETC___d3047 = - (!perfReqQ_enqReq_dummy2_2$Q_OUT || - (EN_perf_req ? - !perfReqQ_enqReq_lat_0$wget[2] : - !perfReqQ_enqReq_rl[2])) && - (perfReqQ_deqReq_dummy2_2$Q_OUT && - (EN_perf_resp || perfReqQ_deqReq_rl) || - perfReqQ_empty) ; - assign SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3963 = - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - (SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491 ? + f32d_enqReq_lat_0$wget[68:0] : + f32d_enqReq_rl[68:0] } ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3258 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[241:239] == 3'd2 : + out_fifo_enqueueElement_0_rl[241:239] == 3'd2) ? + 3'd2 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[241:239] == 3'd3 : + out_fifo_enqueueElement_0_rl[241:239] == 3'd3) ? + 3'd3 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[241:239] == 3'd4 : + out_fifo_enqueueElement_0_rl[241:239] == 3'd4) ? + 3'd4 : + 3'd7)) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3260 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[241:239] == 3'd0 : + out_fifo_enqueueElement_0_rl[241:239] == 3'd0) ? + 3'd0 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[241:239] == 3'd1 : + out_fifo_enqueueElement_0_rl[241:239] == 3'd1) ? + 3'd1 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3258) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3263 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[267:265] == 3'd4 : + out_fifo_enqueueElement_0_rl[267:265] == 3'd4) ? + { 21'd1223338, + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[246:242] : + out_fifo_enqueueElement_0_rl[246:242], + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3260, + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[238] : + out_fifo_enqueueElement_0_rl[238] } : + 30'd715827882 ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3264 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[267:265] == 3'd3 : + out_fifo_enqueueElement_0_rl[267:265] == 3'd3) ? + { 25'd15379114, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d957 } : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3263 ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3266 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[267:265] == 3'd1 : + out_fifo_enqueueElement_0_rl[267:265] == 3'd1) ? + { 27'd27962026, + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[240:238] : + out_fifo_enqueueElement_0_rl[240:238] } : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[267:265] == 3'd2 : + out_fifo_enqueueElement_0_rl[267:265] == 3'd2) ? + { 3'd2, + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[264:238] : + out_fifo_enqueueElement_0_rl[264:238] } : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3264) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3267 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[267:265] == 3'd0 : + out_fifo_enqueueElement_0_rl[267:265] == 3'd0) ? + { 25'd2796202, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d957 } : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3266 ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3277 = + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1263 ? + { 3'd1, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1189 } : + { IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1275 ? + 3'd2 : + (IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1286 ? + 3'd3 : + 3'd4), + 2'h2 } ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3284 = + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1433 ? + 4'd8 : + (IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1456 ? + 4'd9 : + (IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1479 ? + 4'd10 : + 4'd11)) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3286 = + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1387 ? + 4'd6 : + (IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1410 ? + 4'd7 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3284) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3290 = + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1315 ? + { 8'd58, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1156 } : + (IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1339 ? + 9'd138 : + (IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1363 ? + { 8'd90, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1156 } : + { IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3286, + 5'h0A })) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3292 = + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1184 ? + { 7'd10, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1189 } : + (IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1213 ? + _2_CONCAT_IF_IF_out_fifo_enqueueElement_0_lat_0_ETC___d3279 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3290) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3296 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[237:236] == 2'd0 : + out_fifo_enqueueElement_0_rl[237:236] == 2'd0) ? + { 7'd10, + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[230:227] : + out_fifo_enqueueElement_0_rl[230:227] } : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[237:236] == 2'd1 : + out_fifo_enqueueElement_0_rl[237:236] == 2'd1) ? + { 2'd1, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1151 ? + { 8'd10, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1156 } : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3292 } : + 11'd1194) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3299 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd1969 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd1969) ? + 12'd1969 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd1970 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd1970) ? + 12'd1970 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == + 12'd1971 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd1971) ? + 12'd1971 : + 12'd2303)) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3301 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd1955 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd1955) ? + 12'd1955 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd1968 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd1968) ? + 12'd1968 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3299) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3303 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd1953 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd1953) ? + 12'd1953 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd1954 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd1954) ? + 12'd1954 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3301) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3305 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd3008 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd3008) ? + 12'd3008 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd1952 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd1952) ? + 12'd1952 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3303) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3307 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd3859 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd3859) ? + 12'd3859 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd3860 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd3860) ? + 12'd3860 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3305) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3309 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd3857 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd3857) ? + 12'd3857 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd3858 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd3858) ? + 12'd3858 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3307) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3311 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd2816 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd2816) ? + 12'd2816 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd2818 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd2818) ? + 12'd2818 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3309) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3313 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd835 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd835) ? + 12'd835 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd836 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd836) ? + 12'd836 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3311) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3315 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd833 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd833) ? + 12'd833 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd834 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd834) ? + 12'd834 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3313) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3317 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd774 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd774) ? + 12'd774 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd832 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd832) ? + 12'd832 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3315) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3319 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd772 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd772) ? + 12'd772 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd773 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd773) ? + 12'd773 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3317) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3321 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd770 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd770) ? + 12'd770 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd771 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd771) ? + 12'd771 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3319) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3323 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd768 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd768) ? + 12'd768 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd769 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd769) ? + 12'd769 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3321) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3325 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd384 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd384) ? + 12'd384 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd2496 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd2496) ? + 12'd2496 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3323) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3327 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd323 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd323) ? + 12'd323 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd324 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd324) ? + 12'd324 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3325) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3329 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd321 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd321) ? + 12'd321 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd322 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd322) ? + 12'd322 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3327) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3331 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd262 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd262) ? + 12'd262 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd320 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd320) ? + 12'd320 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3329) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3333 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd260 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd260) ? + 12'd260 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd261 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd261) ? + 12'd261 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3331) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3335 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd2049 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd2049) ? + 12'd2049 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd256 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd256) ? + 12'd256 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3333) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3337 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd3074 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd3074) ? + 12'd3074 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd2048 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd2048) ? + 12'd2048 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3335) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3339 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd3072 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd3072) ? + 12'd3072 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd3073 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd3073) ? + 12'd3073 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3337) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3341 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd2 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd2) ? + 12'd2 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd3 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd3) ? + 12'd3 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3339) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3346 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[166:162] == 5'd29 : + out_fifo_enqueueElement_0_rl[166:162] == 5'd29) ? + 5'd29 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[166:162] == 5'd30 : + out_fifo_enqueueElement_0_rl[166:162] == 5'd30) ? + 5'd30 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[166:162] == 5'd31 : + out_fifo_enqueueElement_0_rl[166:162] == 5'd31) ? + 5'd31 : + 5'd10)) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3348 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[166:162] == 5'd15 : + out_fifo_enqueueElement_0_rl[166:162] == 5'd15) ? + 5'd15 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[166:162] == 5'd28 : + out_fifo_enqueueElement_0_rl[166:162] == 5'd28) ? + 5'd28 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3346) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3350 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[166:162] == 5'd13 : + out_fifo_enqueueElement_0_rl[166:162] == 5'd13) ? + 5'd13 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[166:162] == 5'd14 : + out_fifo_enqueueElement_0_rl[166:162] == 5'd14) ? + 5'd14 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3348) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3352 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[166:162] == 5'd1 : + out_fifo_enqueueElement_0_rl[166:162] == 5'd1) ? + 5'd1 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[166:162] == 5'd12 : + out_fifo_enqueueElement_0_rl[166:162] == 5'd12) ? + 5'd12 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3350) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3370 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd12 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd12) ? + 5'd12 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd13 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd13) ? + 5'd13 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd15 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd15) ? + 5'd15 : + 5'd28)) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3372 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd9 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd9) ? + 5'd9 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd11 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd11) ? + 5'd11 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3370) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3374 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd7 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd7) ? + 5'd7 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd8 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd8) ? + 5'd8 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3372) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3376 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd5 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd5) ? + 5'd5 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd6 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd6) ? + 5'd6 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3374) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3378 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd3 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd3) ? + 5'd3 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd4 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd4) ? + 5'd4 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3376) ; + assign IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3380 = + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd1 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd1) ? + 5'd1 : + ((out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd2 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd2) ? + 5'd2 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3378) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3405 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[241:239] == 3'd2 : + out_fifo_enqueueElement_1_rl[241:239] == 3'd2) ? + 3'd2 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[241:239] == 3'd3 : + out_fifo_enqueueElement_1_rl[241:239] == 3'd3) ? + 3'd3 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[241:239] == 3'd4 : + out_fifo_enqueueElement_1_rl[241:239] == 3'd4) ? + 3'd4 : + 3'd7)) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3407 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[241:239] == 3'd0 : + out_fifo_enqueueElement_1_rl[241:239] == 3'd0) ? + 3'd0 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[241:239] == 3'd1 : + out_fifo_enqueueElement_1_rl[241:239] == 3'd1) ? + 3'd1 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3405) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3410 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[267:265] == 3'd4 : + out_fifo_enqueueElement_1_rl[267:265] == 3'd4) ? + { 21'd1223338, + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[246:242] : + out_fifo_enqueueElement_1_rl[246:242], + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3407, + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[238] : + out_fifo_enqueueElement_1_rl[238] } : + 30'd715827882 ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3411 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[267:265] == 3'd3 : + out_fifo_enqueueElement_1_rl[267:265] == 3'd3) ? + { 25'd15379114, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2125 } : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3410 ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3413 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[267:265] == 3'd1 : + out_fifo_enqueueElement_1_rl[267:265] == 3'd1) ? + { 27'd27962026, + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[240:238] : + out_fifo_enqueueElement_1_rl[240:238] } : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[267:265] == 3'd2 : + out_fifo_enqueueElement_1_rl[267:265] == 3'd2) ? + { 3'd2, + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[264:238] : + out_fifo_enqueueElement_1_rl[264:238] } : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3411) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3414 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[267:265] == 3'd0 : + out_fifo_enqueueElement_1_rl[267:265] == 3'd0) ? + { 25'd2796202, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2125 } : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3413 ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3424 = + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2430 ? + { 3'd1, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2356 } : + { IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2442 ? + 3'd2 : + (IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2453 ? + 3'd3 : + 3'd4), + 2'h2 } ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3431 = + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2599 ? + 4'd8 : + (IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2622 ? + 4'd9 : + (IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2645 ? + 4'd10 : + 4'd11)) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3433 = + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2553 ? + 4'd6 : + (IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2576 ? + 4'd7 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3431) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3437 = + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2482 ? + { 8'd58, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2323 } : + (IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2506 ? + 9'd138 : + (IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2529 ? + { 8'd90, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2323 } : + { IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3433, + 5'h0A })) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3439 = + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2351 ? + { 7'd10, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2356 } : + (IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2380 ? + _2_CONCAT_IF_IF_out_fifo_enqueueElement_1_lat_0_ETC___d3426 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3437) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3443 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[237:236] == 2'd0 : + out_fifo_enqueueElement_1_rl[237:236] == 2'd0) ? + { 7'd10, + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[230:227] : + out_fifo_enqueueElement_1_rl[230:227] } : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[237:236] == 2'd1 : + out_fifo_enqueueElement_1_rl[237:236] == 2'd1) ? + { 2'd1, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2318 ? + { 8'd10, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2323 } : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3439 } : + 11'd1194) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3446 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd1969 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd1969) ? + 12'd1969 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd1970 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd1970) ? + 12'd1970 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == + 12'd1971 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd1971) ? + 12'd1971 : + 12'd2303)) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3448 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd1955 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd1955) ? + 12'd1955 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd1968 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd1968) ? + 12'd1968 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3446) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3450 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd1953 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd1953) ? + 12'd1953 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd1954 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd1954) ? + 12'd1954 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3448) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3452 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd3008 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd3008) ? + 12'd3008 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd1952 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd1952) ? + 12'd1952 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3450) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3454 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd3859 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd3859) ? + 12'd3859 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd3860 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd3860) ? + 12'd3860 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3452) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3456 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd3857 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd3857) ? + 12'd3857 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd3858 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd3858) ? + 12'd3858 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3454) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3458 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd2816 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd2816) ? + 12'd2816 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd2818 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd2818) ? + 12'd2818 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3456) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3460 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd835 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd835) ? + 12'd835 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd836 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd836) ? + 12'd836 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3458) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3462 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd833 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd833) ? + 12'd833 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd834 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd834) ? + 12'd834 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3460) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3464 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd774 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd774) ? + 12'd774 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd832 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd832) ? + 12'd832 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3462) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3466 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd772 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd772) ? + 12'd772 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd773 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd773) ? + 12'd773 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3464) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3468 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd770 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd770) ? + 12'd770 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd771 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd771) ? + 12'd771 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3466) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3470 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd768 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd768) ? + 12'd768 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd769 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd769) ? + 12'd769 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3468) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3472 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd384 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd384) ? + 12'd384 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd2496 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd2496) ? + 12'd2496 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3470) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3474 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd323 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd323) ? + 12'd323 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd324 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd324) ? + 12'd324 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3472) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3476 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd321 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd321) ? + 12'd321 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd322 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd322) ? + 12'd322 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3474) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3478 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd262 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd262) ? + 12'd262 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd320 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd320) ? + 12'd320 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3476) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3480 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd260 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd260) ? + 12'd260 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd261 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd261) ? + 12'd261 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3478) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3482 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd2049 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd2049) ? + 12'd2049 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd256 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd256) ? + 12'd256 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3480) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3484 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd3074 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd3074) ? + 12'd3074 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd2048 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd2048) ? + 12'd2048 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3482) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3486 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd3072 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd3072) ? + 12'd3072 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd3073 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd3073) ? + 12'd3073 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3484) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3488 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd2 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd2) ? + 12'd2 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd3 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd3) ? + 12'd3 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3486) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3493 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[166:162] == 5'd29 : + out_fifo_enqueueElement_1_rl[166:162] == 5'd29) ? + 5'd29 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[166:162] == 5'd30 : + out_fifo_enqueueElement_1_rl[166:162] == 5'd30) ? + 5'd30 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[166:162] == 5'd31 : + out_fifo_enqueueElement_1_rl[166:162] == 5'd31) ? + 5'd31 : + 5'd10)) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3495 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[166:162] == 5'd15 : + out_fifo_enqueueElement_1_rl[166:162] == 5'd15) ? + 5'd15 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[166:162] == 5'd28 : + out_fifo_enqueueElement_1_rl[166:162] == 5'd28) ? + 5'd28 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3493) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3497 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[166:162] == 5'd13 : + out_fifo_enqueueElement_1_rl[166:162] == 5'd13) ? + 5'd13 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[166:162] == 5'd14 : + out_fifo_enqueueElement_1_rl[166:162] == 5'd14) ? + 5'd14 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3495) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3499 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[166:162] == 5'd1 : + out_fifo_enqueueElement_1_rl[166:162] == 5'd1) ? + 5'd1 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[166:162] == 5'd12 : + out_fifo_enqueueElement_1_rl[166:162] == 5'd12) ? + 5'd12 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3497) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3517 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd12 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd12) ? + 5'd12 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd13 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd13) ? + 5'd13 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd15 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd15) ? + 5'd15 : + 5'd28)) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3519 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd9 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd9) ? + 5'd9 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd11 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd11) ? + 5'd11 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3517) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3521 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd7 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd7) ? + 5'd7 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd8 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd8) ? + 5'd8 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3519) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3523 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd5 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd5) ? + 5'd5 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd6 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd6) ? + 5'd6 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3521) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3525 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd3 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd3) ? + 5'd3 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd4 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd4) ? + 5'd4 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3523) ; + assign IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3527 = + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd1 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd1) ? + 5'd1 : + ((out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd2 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd2) ? + 5'd2 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3525) ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d5044 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 ? + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5019 : + !f22f3_empty && + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5023 && + CASE_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_2_ETC___d5040 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d5308 = + (IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 || + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] != + 2'b11) ? + !SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 : + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5237 && + !SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d6317 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 ? + 2'd2 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b11) ? + (IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5237 ? + 2'd2 : + 2'd0) : + 2'd1) ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d6664 = + (IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 || + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] != + 2'b11) ? + SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 : + !IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5237 || + SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d5083 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + !SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 : + rg_pending_f32d[74]) : + rg_pending_f32d[74] ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d5379 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 : + !rg_pending_f32d[74]) : + !rg_pending_f32d[74] ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6319 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + (IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196 ? + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d6317 : + 2'd0) : + 2'd0 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6694 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4937 : + rg_pending_f32d[4]) : + rg_pending_f32d[4] ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6759 = + (pending_n_items__h113790 == 2'd0) ? + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 && + ehr_pending_straddle_rl[0] : + rg_pending_f32d[75] ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6775 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6773 : + rg_pending_f32d[73:69] == 5'd0) : + rg_pending_f32d[73:69] == 5'd0 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6785 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6783 : + rg_pending_f32d[73:69] == 5'd1) : + rg_pending_f32d[73:69] == 5'd1 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6795 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6793 : + rg_pending_f32d[73:69] == 5'd2) : + rg_pending_f32d[73:69] == 5'd2 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6805 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6803 : + rg_pending_f32d[73:69] == 5'd3) : + rg_pending_f32d[73:69] == 5'd3 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6815 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6813 : + rg_pending_f32d[73:69] == 5'd4) : + rg_pending_f32d[73:69] == 5'd4 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6825 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6823 : + rg_pending_f32d[73:69] == 5'd5) : + rg_pending_f32d[73:69] == 5'd5 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6835 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6833 : + rg_pending_f32d[73:69] == 5'd6) : + rg_pending_f32d[73:69] == 5'd6 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6845 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6843 : + rg_pending_f32d[73:69] == 5'd7) : + rg_pending_f32d[73:69] == 5'd7 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6855 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6853 : + rg_pending_f32d[73:69] == 5'd8) : + rg_pending_f32d[73:69] == 5'd8 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6865 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6863 : + rg_pending_f32d[73:69] == 5'd9) : + rg_pending_f32d[73:69] == 5'd9 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6875 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6873 : + rg_pending_f32d[73:69] == 5'd11) : + rg_pending_f32d[73:69] == 5'd11 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6885 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6883 : + rg_pending_f32d[73:69] == 5'd12) : + rg_pending_f32d[73:69] == 5'd12 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6895 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6893 : + rg_pending_f32d[73:69] == 5'd13) : + rg_pending_f32d[73:69] == 5'd13 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6905 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + ((pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6903 : + rg_pending_f32d[73:69] == 5'd15) : + rg_pending_f32d[73:69] == 5'd15 ; + assign IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6973 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + (IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5266 ? + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d6971 : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6969) : + ehr_pending_straddle_rl[145:0] ; + assign IF_NOT_IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15__ETC___d4732 = + ((cap__h109578[5:2] != 4'd15 || cap__h109578[1:0] == 2'b0) && + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4709) ? + !SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 || + !IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4729 : + !SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 || + !pc_reg_rl_BITS_63_TO_0_689_PLUS_2_690_BITS_63__ETC___d4704 ; + assign IF_NOT_IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15__ETC___d4765 = + ((cap__h109578[5:2] != 4'd15 || cap__h109578[1:0] == 2'b0) && + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4709) ? + nextAddrPred_next_addrs$D_OUT_2 : + nextAddrPred_next_addrs$D_OUT_3 ; + assign IF_NOT_IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15__ETC___d4781 = + ((cap__h109578[5:2] != 4'd15 || cap__h109578[1:0] == 2'b0) && + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4709) ? + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 && + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4729 : + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 && + pc_reg_rl_BITS_63_TO_0_689_PLUS_2_690_BITS_63__ETC___d4704 ; + assign IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5310 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] != + 2'b11 || + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249) ? + !SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 : + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5309 ; + assign IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5315 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] != + 2'b11 || + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260) ? + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5311 : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5314 ; + assign IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5320 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] != + 2'b11 || + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5271) ? + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5316 : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5319 ; + assign IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5335 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] != + 2'b11 || + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249) ? + pc_start__h114675 : + value__h127057 ; + assign IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5344 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] != + 2'b11 || + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260) ? + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5336 : + value__h135811 ; + assign IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5353 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] != + 2'b11 || + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5271) ? + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5345 : + a__h144061 ; + assign IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d6965 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] != + 2'b11 || + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249) ? + { pc_start__h114675, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234, + !SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 } : + { value__h127057, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245, + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5309 } ; + assign IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d6968 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] != + 2'b11 || + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260) ? + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d6966 : + { value__h135811, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256, + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5314 } ; + assign IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d6971 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] != + 2'b11 || + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5271) ? + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d6969 : + { a__h144061, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267, + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5319 } ; + assign IF_NOT_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032__ETC___d7532 = + (!SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q89) ? + 5'd1 : + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7531 ; + assign IF_NOT_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032__ETC___d7533 = + (!SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q90) ? + 5'd0 : + IF_NOT_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032__ETC___d7532 ; + assign IF_NOT_SEL_ARR_instdata_data_0_987_BITS_260_TO_ETC___d7977 = + (SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_334_011_f32d_data__ETC___d7014) ? + IF_SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_ETC___d7976 : + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998 && + SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7972 ; + assign IF_NOT_SEL_ARR_instdata_data_0_987_BITS_260_TO_ETC___d8011 = + (SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_334_011_f32d_data__ETC___d7014) ? + IF_SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_ETC___d8010 : + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d8007 ; + assign IF_NOT_decode_047_BIT_26_079_080_AND_NOT_decod_ETC___d7120 = + (!decode___d7047[26] && !decode___d7047[6]) ? + NOT_decode_047_BITS_25_TO_21_081_EQ_decode_047_ETC___d7117 : + !decode___d7047[26] || !decode___d7047[6] || + NOT_decode_047_BITS_25_TO_21_081_EQ_decode_047_ETC___d7117 ; + assign IF_NOT_decode_047_BIT_7_058_071_OR_decode_047__ETC___d7419 = + NOT_decode_047_BIT_7_058_071_OR_decode_047_BIT_ETC___d7087 ? + ras$ras_0_first : + (NOT_decode_047_BIT_27_078_088_OR_decode_047_BI_ETC___d7095 ? + decodeBrPred___d7404[128:0] : + IF_decode_047_BIT_7_058_AND_NOT_decode_047_BIT_ETC___d7417) ; + assign IF_NOT_decode_558_BIT_26_590_591_AND_NOT_decod_ETC___d7631 = + (!decode___d7558[26] && !decode___d7558[6]) ? + NOT_decode_558_BITS_25_TO_21_592_EQ_decode_558_ETC___d7628 : + !decode___d7558[26] || !decode___d7558[6] || + NOT_decode_558_BITS_25_TO_21_592_EQ_decode_558_ETC___d7628 ; + assign IF_NOT_decode_558_BIT_7_569_582_OR_decode_558__ETC___d7930 = + NOT_decode_558_BIT_7_569_582_OR_decode_558_BIT_ETC___d7598 ? + ras$ras_1_first : + (NOT_decode_558_BIT_27_589_599_OR_decode_558_BI_ETC___d7606 ? + decodeBrPred___d7915[128:0] : + IF_decode_558_BIT_7_569_AND_NOT_decode_558_BIT_ETC___d7928) ; + assign IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5084 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[74] : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d5083 ; + assign IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217 = + ((NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5163) && + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d5210) ? + 32'd0 : + ((NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + IF_SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_ETC___d5215 : + 32'd0) ; + assign IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230 = + ((NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5163) && + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d5223) ? + 32'd0 : + ((NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + IF_SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_ETC___d5228 : + 32'd0) ; + assign IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5380 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + !rg_pending_f32d[74] : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d5379 ; + assign IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5395 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + 2'd0 : + (IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5393 : + 2'd0) ; + assign IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5400 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + 2'd0 : + (IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5398 : + 2'd0) ; + assign IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5405 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + 2'd0 : + (IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d5403 : + 2'd0) ; + assign IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6320 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + 2'd0 : + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6319 ; + assign IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6698 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[4:0] : + { IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6694, + x1_avValue_fst_main_epoch__h146089 } ; + assign IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6761 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[75] : + (IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6759 : + rg_pending_f32d[75]) ; + assign IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6934 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[68:0] : + { x1_avValue_fst_tval__h146087, + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg__ETC___d6694, + x1_avValue_fst_main_epoch__h146089 } ; + assign IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6945 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4930 && + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4938 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 : + (IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d5287 : + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988) ; + assign IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6962 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + !SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4930 || + !SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4938 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_NOT_eh_ETC___d5077 : + (IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 ? + IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d6960 : + IF_rg_pending_n_items_951_EQ_0_952_THEN_NOT_eh_ETC___d5077) ; + assign IF_NOT_f22f3_empty_17_919_AND_SEL_ARR_f22f3_da_ETC___d5007 = + (!f22f3_empty && + SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003) ? + mmio$RDY_bootRomResp : + iMem$RDY_to_proc_response_get ; + assign IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4709 = + ((pc_reg_rl[5:2] != 4'd15 || pc_reg_rl[1:0] == 2'b0) && + (!SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 || + !pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684)) ? + !SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 || + !pc_reg_rl_BITS_63_TO_0_689_PLUS_2_690_BITS_63__ETC___d4704 : + !SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 || + !pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684 ; + assign IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4729 = + address__h110316[63:9] == nextAddrPred_tags$D_OUT_3 ; + assign IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4741 = + x__h111368[63:9] == nextAddrPred_tags$D_OUT_2 ; + assign IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4746 = + ((pc_reg_rl[5:2] != 4'd15 || pc_reg_rl[1:0] == 2'b0) && + (!SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 || + !pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684)) ? + IF_NOT_IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15__ETC___d4732 : + !SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 || + !pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684 ; + assign IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4751 = + ((pc_reg_rl[5:2] != 4'd15 || pc_reg_rl[1:0] == 2'b0) && + (!SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 || + !pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684)) ? + 12'd1 : + 12'd0 ; + assign IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4767 = + ((pc_reg_rl[5:2] != 4'd15 || pc_reg_rl[1:0] == 2'b0) && + (!SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 || + !pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684)) ? + IF_NOT_IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15__ETC___d4765 : + nextAddrPred_next_addrs$D_OUT_4 ; + assign IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4768 = + NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_OR_ETC___d4708 ? + IF_pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NO_ETC___d4764 : + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4767 ; + assign IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4772 = + ((pc_reg_rl[5:2] != 4'd15 || pc_reg_rl[1:0] == 2'b0) && + (!SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 || + !pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684)) ? + 2'd1 : + 2'd0 ; + assign IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4783 = + ((pc_reg_rl[5:2] != 4'd15 || pc_reg_rl[1:0] == 2'b0) && + (!SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 || + !pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684)) ? + IF_NOT_IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15__ETC___d4781 : + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 && + pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684 ; + assign IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4786 = + { NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_OR_ETC___d4708 ? + IF_pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NO_ETC___d4779 : + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4783, + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4768 } ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5686 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b001) ? + instr__h134406 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b101) ? + instr__h134559 : + 32'h0) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5688 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b001) ? + instr__h134029 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b101) ? + instr__h134205 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5686) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5690 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b111) ? + instr__h133011 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b011) ? + instr__h133215 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5688) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5692 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b111) ? + instr__h132657 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b011) ? + instr__h132858 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5690) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5695 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:10] == + 6'b100111 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:5] == + 2'b0) ? + instr__h132245 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:12] == + 4'b1001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] == + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:2] == + 5'd0) ? + instr__h132405 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b011) ? + instr__h132502 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5692)) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5697 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:5] == + 2'b0) ? + instr__h131967 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:10] == + 6'b100111 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:5] == + 2'b01) ? + instr__h132106 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5695) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5699 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:5] == + 2'b10) ? + instr__h131693 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:5] == + 2'b01) ? + instr__h131830 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5697) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5702 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:12] == + 4'b1000 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:2] != + 5'd0) ? + instr__h131339 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:12] == + 4'b1001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:2] != + 5'd0) ? + instr__h131460 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:5] == + 2'b11) ? + instr__h131556 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5699)) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5705 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b100 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:10] == + 2'b0 && + imm6__h129425 != 6'd0) ? + instr__h130850 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b100 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:10] == + 2'b01 && + imm6__h129425 != 6'd0) ? + instr__h131040 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b100 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:10] == + 2'b10) ? + instr__h131158 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5702)) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5707 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b0 && + nzimm10__h130327 != 10'd0) ? + instr__h130489 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] != + 5'd0 && + imm6__h129425 != 6'd0) ? + instr__h130660 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5705) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5709 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] != + 5'd0) ? + instr__h130056 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] == + 5'd2 && + nzimm10__h130109 != 10'd0) ? + instr__h130316 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5707) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5710 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] != + 5'd0 && + imm6__h129425 != 6'd0 || + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] == + 5'd0 && + imm6__h129425 == 6'd0) ? + instr__h129825 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5709 ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5712 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b010 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] != + 5'd0) ? + instr__h129504 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] != + 5'd2 && + imm6__h129425 != 6'd0) ? + instr__h129693 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5710) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5714 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b110) ? + instr__h128844 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b111) ? + instr__h129163 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5712) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5716 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:12] == + 4'b1000 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:2] == + 5'd0) ? + instr__h128661 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:12] == + 4'b1001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:2] == + 5'd0) ? + instr__h128779 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5714) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5718 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b110) ? + instr__h127977 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b101) ? + instr__h128207 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5716) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5720 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b110) ? + instr__h127586 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == + 3'b010) ? + instr__h127780 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5718) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5975 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b001) ? + instr__h143160 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b101) ? + instr__h143313 : + 32'h0) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5977 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b001) ? + instr__h142783 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b101) ? + instr__h142959 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5975) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5979 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b111) ? + instr__h141765 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b011) ? + instr__h141969 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5977) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5981 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b111) ? + instr__h141411 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b011) ? + instr__h141612 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5979) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5984 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:10] == + 6'b100111 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:5] == + 2'b0) ? + instr__h140999 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:12] == + 4'b1001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] == + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:2] == + 5'd0) ? + instr__h141159 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b011) ? + instr__h141256 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5981)) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5986 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:5] == + 2'b0) ? + instr__h140721 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:10] == + 6'b100111 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:5] == + 2'b01) ? + instr__h140860 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5984) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5988 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:5] == + 2'b10) ? + instr__h140447 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:5] == + 2'b01) ? + instr__h140584 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5986) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5991 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:12] == + 4'b1000 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:2] != + 5'd0) ? + instr__h140093 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:12] == + 4'b1001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:2] != + 5'd0) ? + instr__h140214 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:5] == + 2'b11) ? + instr__h140310 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5988)) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5994 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b100 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:10] == + 2'b0 && + imm6__h138179 != 6'd0) ? + instr__h139604 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b100 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:10] == + 2'b01 && + imm6__h138179 != 6'd0) ? + instr__h139794 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b100 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:10] == + 2'b10) ? + instr__h139912 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5991)) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5996 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b0 && + nzimm10__h139081 != 10'd0) ? + instr__h139243 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] != + 5'd0 && + imm6__h138179 != 6'd0) ? + instr__h139414 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5994) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5998 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] != + 5'd0) ? + instr__h138810 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] == + 5'd2 && + nzimm10__h138863 != 10'd0) ? + instr__h139070 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5996) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5999 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] != + 5'd0 && + imm6__h138179 != 6'd0 || + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] == + 5'd0 && + imm6__h138179 == 6'd0) ? + instr__h138579 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5998 ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6001 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b010 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] != + 5'd0) ? + instr__h138258 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] != + 5'd2 && + imm6__h138179 != 6'd0) ? + instr__h138447 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5999) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6003 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b110) ? + instr__h137598 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b111) ? + instr__h137917 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6001) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6005 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:12] == + 4'b1000 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:2] == + 5'd0) ? + instr__h137415 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:12] == + 4'b1001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:2] == + 5'd0) ? + instr__h137533 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6003) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6007 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b110) ? + instr__h136731 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b101) ? + instr__h136961 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6005) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6009 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b110) ? + instr__h136340 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b010) ? + instr__h136534 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6007) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6264 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b001) ? + instr__h159432 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b101) ? + instr__h159585 : + 32'h0) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6266 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b001) ? + instr__h159055 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b101) ? + instr__h159231 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6264) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6268 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b111) ? + instr__h158037 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b011) ? + instr__h158241 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6266) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6270 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b111) ? + instr__h157683 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b011) ? + instr__h157884 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6268) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6273 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:10] == + 6'b100111 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:5] == + 2'b0) ? + instr__h157271 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:12] == + 4'b1001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] == + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:2] == + 5'd0) ? + instr__h157431 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b011) ? + instr__h157528 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6270)) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6275 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:5] == + 2'b0) ? + instr__h156993 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:10] == + 6'b100111 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:5] == + 2'b01) ? + instr__h157132 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6273) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6277 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:5] == + 2'b10) ? + instr__h156719 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:5] == + 2'b01) ? + instr__h156856 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6275) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6280 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:12] == + 4'b1000 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:2] != + 5'd0) ? + instr__h156365 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:12] == + 4'b1001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:2] != + 5'd0) ? + instr__h156486 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:5] == + 2'b11) ? + instr__h156582 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6277)) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6283 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b100 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:10] == + 2'b0 && + imm6__h154451 != 6'd0) ? + instr__h155876 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b100 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:10] == + 2'b01 && + imm6__h154451 != 6'd0) ? + instr__h156066 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b100 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:10] == + 2'b10) ? + instr__h156184 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6280)) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6285 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b0 && + nzimm10__h155353 != 10'd0) ? + instr__h155515 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] != + 5'd0 && + imm6__h154451 != 6'd0) ? + instr__h155686 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6283) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6287 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] != + 5'd0) ? + instr__h155082 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] == + 5'd2 && + nzimm10__h155135 != 10'd0) ? + instr__h155342 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6285) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6288 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] != + 5'd0 && + imm6__h154451 != 6'd0 || + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] == + 5'd0 && + imm6__h154451 == 6'd0) ? + instr__h154851 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6287 ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6290 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b010 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] != + 5'd0) ? + instr__h154530 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] != + 5'd2 && + imm6__h154451 != 6'd0) ? + instr__h154719 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6288) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6292 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b110) ? + instr__h153870 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b111) ? + instr__h154189 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6290) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6294 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:12] == + 4'b1000 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:2] == + 5'd0) ? + instr__h153687 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:12] == + 4'b1001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:2] == + 5'd0) ? + instr__h153805 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6292) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6296 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b110) ? + instr__h153003 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b101) ? + instr__h153233 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6294) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6298 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b110) ? + instr__h152612 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b010) ? + instr__h152806 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6296) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6586 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b001) ? + instr__h125665 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b101) ? + instr__h125818 : + 32'h0) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6588 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b001) ? + instr__h125288 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b101) ? + instr__h125464 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6586) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6590 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b111) ? + instr__h124214 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b011) ? + instr__h124473 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6588) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6592 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b111) ? + instr__h123860 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b011) ? + instr__h124061 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6590) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6595 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:10] == + 6'b100111 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:5] == + 2'b0) ? + instr__h123448 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:12] == + 4'b1001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] == + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:2] == + 5'd0) ? + instr__h123608 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b011) ? + instr__h123705 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6592)) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6597 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:5] == + 2'b0) ? + instr__h123170 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:10] == + 6'b100111 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:5] == + 2'b01) ? + instr__h123309 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6595) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6599 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:5] == + 2'b10) ? + instr__h122896 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:5] == + 2'b01) ? + instr__h123033 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6597) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6602 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:12] == + 4'b1000 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:2] != + 5'd0) ? + instr__h122542 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:12] == + 4'b1001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:2] != + 5'd0) ? + instr__h122663 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:10] == + 6'b100011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:5] == + 2'b11) ? + instr__h122759 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6599)) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6605 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b100 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:10] == + 2'b0 && + imm6__h120628 != 6'd0) ? + instr__h122053 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b100 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:10] == + 2'b01 && + imm6__h120628 != 6'd0) ? + instr__h122243 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b100 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:10] == + 2'b10) ? + instr__h122361 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6602)) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6607 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b0 && + nzimm10__h121530 != 10'd0) ? + instr__h121692 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] != + 5'd0 && + imm6__h120628 != 6'd0) ? + instr__h121863 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6605) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6609 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] != + 5'd0) ? + instr__h121259 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] == + 5'd2 && + nzimm10__h121312 != 10'd0) ? + instr__h121519 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6607) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6610 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] != + 5'd0 && + imm6__h120628 != 6'd0 || + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] == + 5'd0 && + imm6__h120628 == 6'd0) ? + instr__h121028 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6609 ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6612 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b010 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] != + 5'd0) ? + instr__h120707 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b011 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] != + 5'd2 && + imm6__h120628 != 6'd0) ? + instr__h120896 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6610) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6614 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b110) ? + instr__h120047 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b111) ? + instr__h120366 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6612) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6616 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:12] == + 4'b1000 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:2] == + 5'd0) ? + instr__h119864 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:12] == + 4'b1001 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:2] == + 5'd0) ? + instr__h119982 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6614) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6618 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b110) ? + instr__h119177 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b01 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b101) ? + instr__h119408 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6616) ; + assign IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6620 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b110) ? + instr__h118786 : + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == + 3'b010) ? + instr__h118980 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6618) ; + assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d8287 = + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q26 ? + 3'd3 : + (CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q27 ? + 3'd4 : + 3'd7) ; + assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d8288 = + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q28 ? + 3'd2 : + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d8287 ; + assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d8289 = + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q29 ? + 3'd1 : + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d8288 ; + assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d8290 = + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q30 ? + 3'd0 : + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d8289 ; + assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d9309 = + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q67 ? + 3'd3 : + (CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q68 ? + 3'd4 : + 3'd7) ; + assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d9310 = + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q69 ? + 3'd2 : + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d9309 ; + assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d9311 = + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q70 ? + 3'd1 : + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d9310 ; + assign IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d9312 = + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q71 ? + 3'd0 : + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d9311 ; + assign IF_SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_ETC___d5215 = + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 ? + (SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003 ? + mmio$bootRomResp[31:0] : + iMem$to_proc_response_get[31:0]) : + 32'd0 ; + assign IF_SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_ETC___d5228 = + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 ? + (SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003 ? + mmio$bootRomResp[64:33] : + iMem$to_proc_response_get[64:33]) : + 32'd0 ; + assign IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7438 = + (SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7047[0]) ? + ((decode___d7047[171:167] == 5'd10) ? + dirPred$pred_0_pred[23:0] : + 24'hAAAAAA) : + 24'hAAAAAA ; + assign IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7531 = + (SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 || + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q88) ? + 5'd2 : + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7530 ; + assign IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7549 = + (SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7047[0]) ? + IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d7548 : + decode_epoch_rl ; + assign IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7941 = + (SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7558[0]) ? + ((decode___d7558[171:167] == 5'd10) ? + dirPred$pred_1_pred[23:0] : + 24'hAAAAAA) : + 24'hAAAAAA ; + assign IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7975 = + (SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7558[0]) ? + IF_decode_558_BITS_171_TO_167_562_EQ_8_568_AND_ETC___d7971 : + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998 && + SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7972 ; + assign IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7980 = + (SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7558[0]) ? + IF_IF_decode_558_BITS_171_TO_167_562_EQ_8_568__ETC___d7979 : + decode_pred_next_pc__h177047 ; + assign IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7988 = + (SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7558[0]) ? + IF_IF_decode_558_BITS_171_TO_167_562_EQ_8_568__ETC___d7987 : + IF_SEL_ARR_instdata_data_0_987_BITS_65_TO_64_9_ETC___d7551 ; + assign IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d8009 = + (SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7558[0]) ? + IF_IF_decode_558_BITS_171_TO_167_562_EQ_8_568__ETC___d8005 : + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d8007 ; + assign IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d8030 = + (SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7558[0]) ? + IF_IF_decode_558_BITS_171_TO_167_562_EQ_8_568__ETC___d8029 : + IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d8028 ; + assign IF_SEL_ARR_NOT_f32d_data_0_979_BIT_75_991_992__ETC___d8021 = + SEL_ARR_NOT_f32d_data_0_979_BIT_75_991_992_NOT_ETC___d7996 ? + { last_x16_pc__h187660, decode_pred_next_pc__h187627 } : + { x__h171664, nextPc__h193173 } ; + assign IF_SEL_ARR_NOT_f32d_data_0_979_BIT_75_991_992__ETC___d8027 = + SEL_ARR_NOT_f32d_data_0_979_BIT_75_991_992_NOT_ETC___d7996 ? + { last_x16_pc__h177080, decode_pred_next_pc__h177047 } : + { x__h171664, nextPc__h193173 } ; + assign IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8473 = + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8452 ? + { 3'd1, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8400 } : + { SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8461 ? + 3'd2 : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8469 ? + 3'd3 : + 3'd4), + 2'h2 } ; + assign IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8608 = + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8573 ? + 4'd8 : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8589 ? + 4'd9 : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8605 ? + 4'd10 : + 4'd11)) ; + assign IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8610 = + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8541 ? + 4'd6 : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8557 ? + 4'd7 : + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8608) ; + assign IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8613 = + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8508 ? + 9'd138 : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8524 ? + { 4'd5, + DONTCARE_CONCAT_SEL_ARR_out_fifo_internalFifos_ETC___d8377 } : + { IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8610, + 5'h0A }) ; + assign IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8615 = + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8417 ? + _2_CONCAT_IF_SEL_ARR_out_fifo_internalFifos_0_f_ETC___d8475 : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8491 ? + { 4'd3, + DONTCARE_CONCAT_SEL_ARR_out_fifo_internalFifos_ETC___d8377 } : + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8613) ; + assign IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9341 = + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9334 ? + { 3'd1, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9329 } : + { SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9336 ? + 3'd2 : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9337 ? + 3'd3 : + 3'd4), + 2'h2 } ; + assign IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9356 = + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9351 ? + 4'd8 : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9352 ? + 4'd9 : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9353 ? + 4'd10 : + 4'd11)) ; + assign IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9358 = + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9349 ? + 4'd6 : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9350 ? + 4'd7 : + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9356) ; + assign IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9361 = + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9346 ? + 9'd138 : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9347 ? + { 4'd5, + DONTCARE_CONCAT_SEL_ARR_out_fifo_internalFifos_ETC___d9326 } : + { IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9358, + 5'h0A }) ; + assign IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9363 = + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9331 ? + _2_CONCAT_IF_SEL_ARR_out_fifo_internalFifos_0_f_ETC___d9343 : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9344 ? + { 4'd3, + DONTCARE_CONCAT_SEL_ARR_out_fifo_internalFifos_ETC___d9326 } : + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9361) ; + assign IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196 = + j__h114680 < n_x16s__h114677 ; + assign IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5203 = + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 && + pc_start__h114675[63:0] != + ehr_pending_straddle_rl[80:17] + 64'd2 ; + assign IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5237 = + y_avValue_fst__h117191 < n_x16s__h114677 ; + assign IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5278 = + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_NOT_eh_ETC___d5077 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b11 && + !IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5237 ; + assign IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7521 = + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q77 ? + 5'd13 : + (CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q78 ? + 5'd15 : + 5'd28) ; + assign IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7522 = + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q79 ? + 5'd12 : + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7521 ; + assign IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7523 = + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q80 ? + 5'd11 : + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7522 ; + assign IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7524 = + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q81 ? + 5'd9 : + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7523 ; + assign IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7525 = + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q82 ? + 5'd8 : + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7524 ; + assign IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7526 = + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q83 ? + 5'd7 : + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7525 ; + assign IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7527 = + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q84 ? + 5'd6 : + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7526 ; + assign IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7528 = + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q85 ? + 5'd5 : + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7527 ; + assign IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7529 = + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q86 ? + 5'd4 : + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7528 ; + assign IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7530 = + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q87 ? + 5'd3 : + IF_SEL_ARR_f32d_data_0_979_BITS_73_TO_69_459_E_ETC___d7529 ; + assign IF_SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_ETC___d7976 = + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d7552 ? + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7975 : + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998 && + SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7972 ; + assign IF_SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_ETC___d7985 = + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998 ? + (decode___d7047[0] ? + !decode_epoch_rl : + IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d7983) : + !decode_epoch_rl ; + assign IF_SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_ETC___d8010 = + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d7552 ? + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d8009 : + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d8007 ; + assign IF_SEL_ARR_instdata_data_0_987_BITS_65_TO_64_9_ETC___d7551 = + (SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 == + 2'd0) ? + decode_epoch_rl : + (SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998 ? + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7549 : + decode_epoch_rl) ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8293 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q333 ? + { 21'd1223338, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8291 } : + 30'd715827882 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8294 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q334 ? + { 25'd15379114, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8234 } : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8293 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8295 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q335 ? + { 3'd2, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q336, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8220 } : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8294 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8296 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q337 ? + { 27'd27962026, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q338 } : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8295 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8297 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q339 ? + { 25'd2796202, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q340 } : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8296 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8617 = + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8372 ? + { 4'd0, + DONTCARE_CONCAT_SEL_ARR_out_fifo_internalFifos_ETC___d8377 } : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8396 ? + { 7'd10, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8400 } : + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8615) ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8619 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q33 ? + { 2'd1, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8617 } : + 11'd1194 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8620 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q34 ? + { 7'd10, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q35 } : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8619 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8954 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q183 ? + 12'd1970 : + (CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q184 ? + 12'd1971 : + 12'd2303) ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8955 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q185 ? + 12'd1969 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8954 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8956 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q186 ? + 12'd1968 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8955 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8957 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q187 ? + 12'd1955 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8956 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8958 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q188 ? + 12'd1954 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8957 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8959 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q189 ? + 12'd1953 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8958 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8960 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q190 ? + 12'd1952 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8959 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8961 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q191 ? + 12'd3008 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8960 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8962 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q192 ? + 12'd3860 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8961 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8963 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q193 ? + 12'd3859 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8962 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8964 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q194 ? + 12'd3858 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8963 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8965 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q195 ? + 12'd3857 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8964 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8966 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q196 ? + 12'd2818 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8965 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8967 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q197 ? + 12'd2816 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8966 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8968 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q198 ? + 12'd836 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8967 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8969 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q199 ? + 12'd835 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8968 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8970 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q200 ? + 12'd834 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8969 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8971 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q201 ? + 12'd833 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8970 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8972 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q202 ? + 12'd832 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8971 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8973 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q203 ? + 12'd774 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8972 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8974 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q204 ? + 12'd773 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8973 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8975 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q205 ? + 12'd772 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8974 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8976 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q206 ? + 12'd771 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8975 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8977 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q207 ? + 12'd770 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8976 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8978 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q208 ? + 12'd769 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8977 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8979 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q209 ? + 12'd768 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8978 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8980 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q210 ? + 12'd2496 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8979 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8981 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q211 ? + 12'd384 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8980 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8982 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q212 ? + 12'd324 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8981 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8983 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q213 ? + 12'd323 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8982 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8984 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q214 ? + 12'd322 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8983 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8985 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q215 ? + 12'd321 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8984 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8986 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q216 ? + 12'd320 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8985 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8987 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q217 ? + 12'd262 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8986 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8988 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q218 ? + 12'd261 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8987 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8989 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q219 ? + 12'd260 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8988 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8990 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q220 ? + 12'd256 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8989 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8991 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q221 ? + 12'd2049 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8990 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8992 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q222 ? + 12'd2048 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8991 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8993 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q223 ? + 12'd3074 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8992 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8994 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q224 ? + 12'd3073 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8993 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8995 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q225 ? + 12'd3072 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8994 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8996 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q226 ? + 12'd3 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8995 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8997 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q227 ? + 12'd2 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8996 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8998 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q228 ? + 12'd1 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8997 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9050 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q91 ? + 5'd30 : + (CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q92 ? + 5'd31 : + 5'd10) ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9051 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q93 ? + 5'd29 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9050 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9052 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q94 ? + 5'd28 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9051 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9053 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q95 ? + 5'd15 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9052 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9054 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q96 ? + 5'd14 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9053 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9055 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q97 ? + 5'd13 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9054 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9056 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q98 ? + 5'd12 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9055 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9057 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q99 ? + 5'd1 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9056 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9058 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q100 ? + 5'd0 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9057 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9222 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q275 ? + 5'd13 : + (CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q276 ? + 5'd15 : + 5'd28) ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9223 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q277 ? + 5'd12 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9222 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9224 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q278 ? + 5'd11 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9223 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9225 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q279 ? + 5'd9 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9224 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9226 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q280 ? + 5'd8 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9225 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9227 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q281 ? + 5'd7 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9226 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9228 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q282 ? + 5'd6 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9227 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9229 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q283 ? + 5'd5 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9228 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9230 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q284 ? + 5'd4 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9229 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9231 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q285 ? + 5'd3 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9230 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9232 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q286 ? + 5'd2 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9231 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9233 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q287 ? + 5'd1 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9232 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9234 = + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q288 ? + 5'd0 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9233 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9315 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q341 ? + { 21'd1223338, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9313 } : + 30'd715827882 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9316 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q342 ? + { 25'd15379114, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9299 } : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9315 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9317 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q343 ? + { 3'd2, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q344, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9294 } : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9316 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9318 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q345 ? + { 27'd27962026, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q346 } : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9317 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9319 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q347 ? + { 25'd2796202, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q348 } : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9318 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9365 = + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9324 ? + { 4'd0, + DONTCARE_CONCAT_SEL_ARR_out_fifo_internalFifos_ETC___d9326 } : + (SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9328 ? + { 7'd10, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9329 } : + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9363) ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9367 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q74 ? + { 2'd1, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9365 } : + 11'd1194 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9368 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q75 ? + { 7'd10, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q76 } : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9367 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9464 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q229 ? + 12'd1970 : + (CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q230 ? + 12'd1971 : + 12'd2303) ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9465 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q231 ? + 12'd1969 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9464 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9466 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q232 ? + 12'd1968 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9465 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9467 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q233 ? + 12'd1955 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9466 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9468 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q234 ? + 12'd1954 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9467 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9469 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q235 ? + 12'd1953 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9468 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9470 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q236 ? + 12'd1952 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9469 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9471 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q237 ? + 12'd3008 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9470 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9472 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q238 ? + 12'd3860 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9471 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9473 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q239 ? + 12'd3859 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9472 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9474 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q240 ? + 12'd3858 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9473 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9475 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q241 ? + 12'd3857 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9474 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9476 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q242 ? + 12'd2818 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9475 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9477 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q243 ? + 12'd2816 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9476 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9478 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q244 ? + 12'd836 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9477 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9479 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q245 ? + 12'd835 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9478 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9480 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q246 ? + 12'd834 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9479 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9481 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q247 ? + 12'd833 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9480 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9482 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q248 ? + 12'd832 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9481 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9483 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q249 ? + 12'd774 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9482 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9484 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q250 ? + 12'd773 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9483 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9485 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q251 ? + 12'd772 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9484 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9486 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q252 ? + 12'd771 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9485 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9487 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q253 ? + 12'd770 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9486 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9488 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q254 ? + 12'd769 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9487 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9489 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q255 ? + 12'd768 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9488 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9490 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q256 ? + 12'd2496 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9489 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9491 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q257 ? + 12'd384 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9490 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9492 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q258 ? + 12'd324 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9491 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9493 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q259 ? + 12'd323 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9492 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9494 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q260 ? + 12'd322 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9493 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9495 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q261 ? + 12'd321 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9494 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9496 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q262 ? + 12'd320 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9495 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9497 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q263 ? + 12'd262 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9496 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9498 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q264 ? + 12'd261 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9497 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9499 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q265 ? + 12'd260 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9498 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9500 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q266 ? + 12'd256 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9499 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9501 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q267 ? + 12'd2049 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9500 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9502 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q268 ? + 12'd2048 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9501 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9503 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q269 ? + 12'd3074 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9502 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9504 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q270 ? + 12'd3073 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9503 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9505 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q271 ? + 12'd3072 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9504 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9506 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q272 ? + 12'd3 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9505 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9507 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q273 ? + 12'd2 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9506 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9508 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q274 ? + 12'd1 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9507 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9523 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q101 ? + 5'd30 : + (CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q102 ? + 5'd31 : + 5'd10) ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9524 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q103 ? + 5'd29 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9523 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9525 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q104 ? + 5'd28 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9524 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9526 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q105 ? + 5'd15 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9525 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9527 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q106 ? + 5'd14 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9526 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9528 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q107 ? + 5'd13 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9527 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9529 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q108 ? + 5'd12 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9528 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9530 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q109 ? + 5'd1 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9529 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9531 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q110 ? + 5'd0 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9530 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9588 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q289 ? + 5'd13 : + (CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q290 ? + 5'd15 : + 5'd28) ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9589 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q291 ? + 5'd12 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9588 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9590 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q292 ? + 5'd11 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9589 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9591 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q293 ? + 5'd9 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9590 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9592 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q294 ? + 5'd8 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9591 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9593 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q295 ? + 5'd7 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9592 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9594 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q296 ? + 5'd6 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9593 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9595 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q297 ? + 5'd5 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9594 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9596 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q298 ? + 5'd4 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9595 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9597 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q299 ? + 5'd3 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9596 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9598 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q300 ? + 5'd2 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9597 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9599 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q301 ? + 5'd1 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9598 ; + assign IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9600 = + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q302 ? + 5'd0 : + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9599 ; + assign IF_decode_047_BITS_134_TO_131_176_EQ_0_177_OR__ETC___d7270 = + (decode___d7047[134:131] == 4'd0 || + decode___d7047[134:131] != 4'd1 && + decode___d7047[134:131] != 4'd2 && + decode___d7047[134:131] != 4'd3 && + decode___d7047[134:131] != 4'd4 && + decode___d7047[134:131] != 4'd5 && + IF_decode_047_BITS_134_TO_131_176_EQ_6_188_OR__ETC___d7197 == + 4'd0) ? + { 4'd0, decode___d7047[130:126] } : + IF_decode_047_BITS_134_TO_131_176_EQ_1_178_OR__ETC___d7269 ; + assign IF_decode_047_BITS_134_TO_131_176_EQ_1_178_OR__ETC___d7269 = + (decode___d7047[134:131] == 4'd1 || + decode___d7047[134:131] != 4'd2 && + decode___d7047[134:131] != 4'd3 && + decode___d7047[134:131] != 4'd4 && + decode___d7047[134:131] != 4'd5 && + IF_decode_047_BITS_134_TO_131_176_EQ_6_188_OR__ETC___d7197 == + 4'd1) ? + { 4'd1, decode___d7047[130:126] } : + IF_decode_047_BITS_134_TO_131_176_EQ_2_180_OR__ETC___d7268 ; + assign IF_decode_047_BITS_134_TO_131_176_EQ_2_180_OR__ETC___d7268 = + (decode___d7047[134:131] == 4'd2 || + decode___d7047[134:131] != 4'd3 && + decode___d7047[134:131] != 4'd4 && + decode___d7047[134:131] != 4'd5 && + IF_decode_047_BITS_134_TO_131_176_EQ_6_188_OR__ETC___d7197 == + 4'd2) ? + { 4'd2, + (decode___d7047[130:128] == 3'd0 || + decode___d7047[130:128] != 3'd1 && + IF_decode_047_BITS_130_TO_128_219_EQ_2_223_OR__ETC___d7226 == + 3'd0) ? + { 3'd0, decode___d7047[127:126] } : + ((decode___d7047[130:128] == 3'd1 || + IF_decode_047_BITS_130_TO_128_219_EQ_2_223_OR__ETC___d7226 == + 3'd1) ? + { 3'd1, decode___d7047[127:126] } : + { CASE_IF_decode_047_BITS_130_TO_128_219_EQ_2_22_ETC__q5, + 2'h2 }) } : + ((decode___d7047[134:131] == 4'd3 || + decode___d7047[134:131] != 4'd4 && + decode___d7047[134:131] != 4'd5 && + IF_decode_047_BITS_134_TO_131_176_EQ_6_188_OR__ETC___d7197 == + 4'd3) ? + { 4'd3, decode___d7047[130:126] } : + ((decode___d7047[134:131] == 4'd4 || + decode___d7047[134:131] != 4'd5 && + IF_decode_047_BITS_134_TO_131_176_EQ_6_188_OR__ETC___d7197 == + 4'd4) ? + 9'd138 : + ((decode___d7047[134:131] == 4'd5 || + IF_decode_047_BITS_134_TO_131_176_EQ_6_188_OR__ETC___d7197 == + 4'd5) ? + { 4'd5, decode___d7047[130:126] } : + { CASE_IF_decode_047_BITS_134_TO_131_176_EQ_6_18_ETC__q6, + 5'h0A }))) ; + assign IF_decode_047_BITS_171_TO_167_051_EQ_8_057_AND_ETC___d7413 = + (decode___d7047[171:167] == 5'd8 && decode___d7047[7] && + !decode___d7047[6] && + (decode___d7047[5:1] == 5'd1 || decode___d7047[5:1] == 5'd5)) ? + decodeBrPred___d7404[129] : + CASE_decode_047_BITS_171_TO_167_9_NOT_decode_0_ETC__q22 ; + assign IF_decode_047_BIT_7_058_AND_NOT_decode_047_BIT_ETC___d7417 = + decode_047_BIT_7_058_AND_NOT_decode_047_BIT_6__ETC___d7096 ? + (IF_NOT_decode_047_BIT_26_079_080_AND_NOT_decod_ETC___d7120 ? + ras$ras_0_first : + decodeBrPred___d7404[128:0]) : + decodeBrPred___d7404[128:0] ; + assign IF_decode_558_BITS_134_TO_131_687_EQ_0_688_OR__ETC___d7781 = + (decode___d7558[134:131] == 4'd0 || + decode___d7558[134:131] != 4'd1 && + decode___d7558[134:131] != 4'd2 && + decode___d7558[134:131] != 4'd3 && + decode___d7558[134:131] != 4'd4 && + decode___d7558[134:131] != 4'd5 && + IF_decode_558_BITS_134_TO_131_687_EQ_6_699_OR__ETC___d7708 == + 4'd0) ? + { 4'd0, decode___d7558[130:126] } : + IF_decode_558_BITS_134_TO_131_687_EQ_1_689_OR__ETC___d7780 ; + assign IF_decode_558_BITS_134_TO_131_687_EQ_1_689_OR__ETC___d7780 = + (decode___d7558[134:131] == 4'd1 || + decode___d7558[134:131] != 4'd2 && + decode___d7558[134:131] != 4'd3 && + decode___d7558[134:131] != 4'd4 && + decode___d7558[134:131] != 4'd5 && + IF_decode_558_BITS_134_TO_131_687_EQ_6_699_OR__ETC___d7708 == + 4'd1) ? + { 4'd1, decode___d7558[130:126] } : + IF_decode_558_BITS_134_TO_131_687_EQ_2_691_OR__ETC___d7779 ; + assign IF_decode_558_BITS_134_TO_131_687_EQ_2_691_OR__ETC___d7779 = + (decode___d7558[134:131] == 4'd2 || + decode___d7558[134:131] != 4'd3 && + decode___d7558[134:131] != 4'd4 && + decode___d7558[134:131] != 4'd5 && + IF_decode_558_BITS_134_TO_131_687_EQ_6_699_OR__ETC___d7708 == + 4'd2) ? + { 4'd2, + (decode___d7558[130:128] == 3'd0 || + decode___d7558[130:128] != 3'd1 && + IF_decode_558_BITS_130_TO_128_730_EQ_2_734_OR__ETC___d7737 == + 3'd0) ? + { 3'd0, decode___d7558[127:126] } : + ((decode___d7558[130:128] == 3'd1 || + IF_decode_558_BITS_130_TO_128_730_EQ_2_734_OR__ETC___d7737 == + 3'd1) ? + { 3'd1, decode___d7558[127:126] } : + { CASE_IF_decode_558_BITS_130_TO_128_730_EQ_2_73_ETC__q7, + 2'h2 }) } : + ((decode___d7558[134:131] == 4'd3 || + decode___d7558[134:131] != 4'd4 && + decode___d7558[134:131] != 4'd5 && + IF_decode_558_BITS_134_TO_131_687_EQ_6_699_OR__ETC___d7708 == + 4'd3) ? + { 4'd3, decode___d7558[130:126] } : + ((decode___d7558[134:131] == 4'd4 || + decode___d7558[134:131] != 4'd5 && + IF_decode_558_BITS_134_TO_131_687_EQ_6_699_OR__ETC___d7708 == + 4'd4) ? + 9'd138 : + ((decode___d7558[134:131] == 4'd5 || + IF_decode_558_BITS_134_TO_131_687_EQ_6_699_OR__ETC___d7708 == + 4'd5) ? + { 4'd5, decode___d7558[130:126] } : + { CASE_IF_decode_558_BITS_134_TO_131_687_EQ_6_69_ETC__q8, + 5'h0A }))) ; + assign IF_decode_558_BITS_171_TO_167_562_EQ_8_568_AND_ETC___d7924 = + (decode___d7558[171:167] == 5'd8 && decode___d7558[7] && + !decode___d7558[6] && + (decode___d7558[5:1] == 5'd1 || decode___d7558[5:1] == 5'd5)) ? + decodeBrPred___d7915[129] : + CASE_decode_558_BITS_171_TO_167_9_NOT_decode_5_ETC__q15 ; + assign IF_decode_558_BITS_171_TO_167_562_EQ_8_568_AND_ETC___d7971 = + IF_decode_558_BITS_171_TO_167_562_EQ_8_568_AND_ETC___d7924 && + decode_pred_next_pc__h187627 != in_ppc__h182302 || + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998 && + !decode___d7047[0] && + IF_decode_047_BITS_171_TO_167_051_EQ_8_057_AND_ETC___d7413 && + decode_pred_next_pc__h177047 != in_ppc__h171466 ; + assign IF_decode_558_BIT_7_569_AND_NOT_decode_558_BIT_ETC___d7928 = + decode_558_BIT_7_569_AND_NOT_decode_558_BIT_6__ETC___d7607 ? + (IF_NOT_decode_558_BIT_26_590_591_AND_NOT_decod_ETC___d7631 ? + ras$ras_1_first : + decodeBrPred___d7915[128:0]) : + decodeBrPred___d7915[128:0] ; + assign IF_decode_epoch_lat_0_whas__6_THEN_decode_epoc_ETC___d19 = + decode_epoch_lat_0$whas ? + decode_epoch_lat_0$wget : + decode_epoch_rl ; + assign IF_ehr_pending_straddle_lat_1_whas__1_THEN_ehr_ETC___d30 = + !EN_redirect && + (WILL_FIRE_RL_doFetch3 ? + ehr_pending_straddle_lat_0$wget[146] : + ehr_pending_straddle_rl[146]) ; + assign IF_ehr_pending_straddle_lat_1_whas__1_THEN_ehr_ETC___d40 = + EN_redirect ? + 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : + (WILL_FIRE_RL_doFetch3 ? + ehr_pending_straddle_lat_0$wget[145:0] : + ehr_pending_straddle_rl[145:0]) ; + assign IF_f12f2_deqReq_lat_1_whas__13_THEN_f12f2_deqR_ETC___d119 = + WILL_FIRE_RL_doFetch2 || f12f2_deqReq_rl ; + assign IF_f12f2_enqReq_lat_1_whas__6_THEN_NOT_f12f2_e_ETC___d62 = + WILL_FIRE_RL_doFetch1 ? + !f12f2_enqReq_lat_0$wget[267] : + !f12f2_enqReq_rl[267] ; + assign IF_f12f2_enqReq_lat_1_whas__6_THEN_f12f2_enqRe_ETC___d55 = + WILL_FIRE_RL_doFetch1 ? + f12f2_enqReq_lat_0$wget[267] : + f12f2_enqReq_rl[267] ; + assign IF_f22f3_deqReq_lat_1_whas__76_THEN_f22f3_deqR_ETC___d382 = + f22f3_deqReq_lat_0$whas || f22f3_deqReq_rl ; + assign IF_f22f3_enqReq_lat_1_whas__77_THEN_NOT_f22f3__ETC___d193 = + WILL_FIRE_RL_doFetch2 ? + !f22f3_enqReq_lat_0$wget[338] : + !f22f3_enqReq_rl[338] ; + assign IF_f22f3_enqReq_lat_1_whas__77_THEN_NOT_f22f3__ETC___d509 = + { IF_f22f3_enqReq_lat_1_whas__77_THEN_NOT_f22f3__ETC___d193 || + (WILL_FIRE_RL_doFetch2 ? + f22f3_enqReq_lat_0$wget[206] : + f22f3_enqReq_rl[206]), + WILL_FIRE_RL_doFetch2 ? + f22f3_enqReq_lat_0$wget[205:77] : + f22f3_enqReq_rl[205:77], + IF_f22f3_enqReq_lat_1_whas__77_THEN_NOT_f22f3__ETC___d193 || + (WILL_FIRE_RL_doFetch2 ? + f22f3_enqReq_lat_0$wget[76] : + f22f3_enqReq_rl[76]), + CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385, + WILL_FIRE_RL_doFetch2 ? + f22f3_enqReq_lat_0$wget[70:0] : + f22f3_enqReq_rl[70:0] } ; + assign IF_f22f3_enqReq_lat_1_whas__77_THEN_f22f3_enqR_ETC___d186 = + WILL_FIRE_RL_doFetch2 ? + f22f3_enqReq_lat_0$wget[338] : + f22f3_enqReq_rl[338] ; + assign IF_f32d_deqReq_lat_1_whas__11_THEN_f32d_deqReq_ETC___d717 = + CAN_FIRE_RL_doDecode || f32d_deqReq_rl ; + assign IF_f32d_enqReq_lat_1_whas__20_THEN_NOT_f32d_en_ETC___d536 = + f32d_enqReq_lat_0$whas ? + !f32d_enqReq_lat_0$wget[335] : + !f32d_enqReq_rl[335] ; + assign IF_f32d_enqReq_lat_1_whas__20_THEN_f32d_enqReq_ETC___d529 = + f32d_enqReq_lat_0$whas ? + f32d_enqReq_lat_0$wget[335] : + f32d_enqReq_rl[335] ; + assign IF_instdata_full_lat_0_whas__75_THEN_NOT_instd_ETC___d5149 = + (CAN_FIRE_RL_doDecode || !instdata_full_rl) && + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992 || + !f22f3_empty && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5085) && + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5127 && + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5147 ; + assign IF_out_fifo_dequeueFifo_lat_1_whas__93_THEN_ou_ETC___d899 = + IF_out_fifo_willDequeue_1_lat_0_whas__243_THEN_ETC___d3246 ? + out_fifo_dequeueFifo_rl : + (IF_out_fifo_willDequeue_0_lat_0_whas__236_THEN_ETC___d3239 ? + upd__h25105 : + out_fifo_dequeueFifo_rl) ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1151 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[235:232] == 4'd0 || + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114 == + 4'd0 : + out_fifo_enqueueElement_0_rl[235:232] == 4'd0 || + out_fifo_enqueueElement_0_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143 == + 4'd0 ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1156 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[227] : + out_fifo_enqueueElement_0_rl[227] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1184 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd0 && + (out_fifo_enqueueElement_0_lat_0$wget[235:232] == 4'd1 || + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114 == + 4'd1) : + out_fifo_enqueueElement_0_rl[235:232] != 4'd0 && + (out_fifo_enqueueElement_0_rl[235:232] == 4'd1 || + out_fifo_enqueueElement_0_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143 == + 4'd1) ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1189 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[228:227] : + out_fifo_enqueueElement_0_rl[228:227] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1213 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd1 && + (out_fifo_enqueueElement_0_lat_0$wget[235:232] == 4'd2 || + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114 == + 4'd2) : + out_fifo_enqueueElement_0_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd1 && + (out_fifo_enqueueElement_0_rl[235:232] == 4'd2 || + out_fifo_enqueueElement_0_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143 == + 4'd2) ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1248 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[231:229] == 3'd0 || + out_fifo_enqueueElement_0_lat_0$wget[231:229] != 3'd1 && + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1233 == + 3'd0 : + out_fifo_enqueueElement_0_rl[231:229] == 3'd0 || + out_fifo_enqueueElement_0_rl[231:229] != 3'd1 && + IF_out_fifo_enqueueElement_0_rl_07_BITS_231_TO_ETC___d1244 == + 3'd0 ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1263 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[231:229] != 3'd0 && + (out_fifo_enqueueElement_0_lat_0$wget[231:229] == 3'd1 || + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1233 == + 3'd1) : + out_fifo_enqueueElement_0_rl[231:229] != 3'd0 && + (out_fifo_enqueueElement_0_rl[231:229] == 3'd1 || + IF_out_fifo_enqueueElement_0_rl_07_BITS_231_TO_ETC___d1244 == + 3'd1) ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1275 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[231:229] != 3'd0 && + out_fifo_enqueueElement_0_lat_0$wget[231:229] != 3'd1 && + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1233 == + 3'd2 : + out_fifo_enqueueElement_0_rl[231:229] != 3'd0 && + out_fifo_enqueueElement_0_rl[231:229] != 3'd1 && + IF_out_fifo_enqueueElement_0_rl_07_BITS_231_TO_ETC___d1244 == + 3'd2 ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1286 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[231:229] != 3'd0 && + out_fifo_enqueueElement_0_lat_0$wget[231:229] != 3'd1 && + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1233 == + 3'd3 : + out_fifo_enqueueElement_0_rl[231:229] != 3'd0 && + out_fifo_enqueueElement_0_rl[231:229] != 3'd1 && + IF_out_fifo_enqueueElement_0_rl_07_BITS_231_TO_ETC___d1244 == + 3'd3 ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1315 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd2 && + (out_fifo_enqueueElement_0_lat_0$wget[235:232] == 4'd3 || + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114 == + 4'd3) : + out_fifo_enqueueElement_0_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd2 && + (out_fifo_enqueueElement_0_rl[235:232] == 4'd3 || + out_fifo_enqueueElement_0_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143 == + 4'd3) ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1339 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd3 && + (out_fifo_enqueueElement_0_lat_0$wget[235:232] == 4'd4 || + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114 == + 4'd4) : + out_fifo_enqueueElement_0_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd3 && + (out_fifo_enqueueElement_0_rl[235:232] == 4'd4 || + out_fifo_enqueueElement_0_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143 == + 4'd4) ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1363 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd4 && + (out_fifo_enqueueElement_0_lat_0$wget[235:232] == 4'd5 || + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114 == + 4'd5) : + out_fifo_enqueueElement_0_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd4 && + (out_fifo_enqueueElement_0_rl[235:232] == 4'd5 || + IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143 == + 4'd5) ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1387 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114 == + 4'd6 : + out_fifo_enqueueElement_0_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143 == + 4'd6 ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1410 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114 == + 4'd7 : + out_fifo_enqueueElement_0_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143 == + 4'd7 ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1433 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114 == + 4'd8 : + out_fifo_enqueueElement_0_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143 == + 4'd8 ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1456 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114 == + 4'd9 : + out_fifo_enqueueElement_0_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143 == + 4'd9 ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1479 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_0_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114 == + 4'd10 : + out_fifo_enqueueElement_0_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_0_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143 == + 4'd10 ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1500 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[226:181] : + out_fifo_enqueueElement_0_rl[226:181] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1890 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[128:97] : + out_fifo_enqueueElement_0_rl[128:97] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1895 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[96] : + out_fifo_enqueueElement_0_rl[96] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1905 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[95:90] : + out_fifo_enqueueElement_0_rl[95:90] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1911 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[89] : + out_fifo_enqueueElement_0_rl[89] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1921 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[88:83] : + out_fifo_enqueueElement_0_rl[88:83] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1928 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[82] : + out_fifo_enqueueElement_0_rl[82] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1938 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[81:77] : + out_fifo_enqueueElement_0_rl[81:77] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1944 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[76] : + out_fifo_enqueueElement_0_rl[76] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1954 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[75:70] : + out_fifo_enqueueElement_0_rl[75:70] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d3358 = + { out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[180] : + out_fifo_enqueueElement_0_rl[180], + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[179:168] == 12'd1 : + out_fifo_enqueueElement_0_rl[179:168] == 12'd1) ? + 12'd1 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3341, + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[167] : + out_fifo_enqueueElement_0_rl[167], + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[166:162] == 5'd0 : + out_fifo_enqueueElement_0_rl[166:162] == 5'd0) ? + 5'd0 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3352, + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[161] : + out_fifo_enqueueElement_0_rl[161], + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[160:129] : + out_fifo_enqueueElement_0_rl[160:129] } ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d3383 = + { out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[69] : + out_fifo_enqueueElement_0_rl[69], + (out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[68:64] == 5'd0 : + out_fifo_enqueueElement_0_rl[68:64] == 5'd0) ? + 5'd0 : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3380, + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[63:0] : + out_fifo_enqueueElement_0_rl[63:0] } ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d909 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[591] : + out_fifo_enqueueElement_0_rl[591] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d919 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[590:462] : + out_fifo_enqueueElement_0_rl[590:462] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d924 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[461:333] : + out_fifo_enqueueElement_0_rl[461:333] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d929 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[332:329] : + out_fifo_enqueueElement_0_rl[332:329] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d934 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[328:305] : + out_fifo_enqueueElement_0_rl[328:305] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d939 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[304:273] : + out_fifo_enqueueElement_0_rl[304:273] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d944 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[272:268] : + out_fifo_enqueueElement_0_rl[272:268] ; + assign IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d957 = + out_fifo_enqueueElement_0_lat_0$whas ? + out_fifo_enqueueElement_0_lat_0$wget[242:238] : + out_fifo_enqueueElement_0_rl[242:238] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2077 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[591] : + out_fifo_enqueueElement_1_rl[591] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2087 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[590:462] : + out_fifo_enqueueElement_1_rl[590:462] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2092 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[461:333] : + out_fifo_enqueueElement_1_rl[461:333] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2097 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[332:329] : + out_fifo_enqueueElement_1_rl[332:329] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2102 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[328:305] : + out_fifo_enqueueElement_1_rl[328:305] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2107 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[304:273] : + out_fifo_enqueueElement_1_rl[304:273] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2112 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[272:268] : + out_fifo_enqueueElement_1_rl[272:268] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2125 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[242:238] : + out_fifo_enqueueElement_1_rl[242:238] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2318 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[235:232] == 4'd0 || + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281 == + 4'd0 : + out_fifo_enqueueElement_1_rl[235:232] == 4'd0 || + out_fifo_enqueueElement_1_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310 == + 4'd0 ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2323 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[227] : + out_fifo_enqueueElement_1_rl[227] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2351 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd0 && + (out_fifo_enqueueElement_1_lat_0$wget[235:232] == 4'd1 || + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281 == + 4'd1) : + out_fifo_enqueueElement_1_rl[235:232] != 4'd0 && + (out_fifo_enqueueElement_1_rl[235:232] == 4'd1 || + out_fifo_enqueueElement_1_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310 == + 4'd1) ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2356 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[228:227] : + out_fifo_enqueueElement_1_rl[228:227] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2380 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd1 && + (out_fifo_enqueueElement_1_lat_0$wget[235:232] == 4'd2 || + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281 == + 4'd2) : + out_fifo_enqueueElement_1_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd1 && + (out_fifo_enqueueElement_1_rl[235:232] == 4'd2 || + out_fifo_enqueueElement_1_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310 == + 4'd2) ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2415 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[231:229] == 3'd0 || + out_fifo_enqueueElement_1_lat_0$wget[231:229] != 3'd1 && + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2400 == + 3'd0 : + out_fifo_enqueueElement_1_rl[231:229] == 3'd0 || + out_fifo_enqueueElement_1_rl[231:229] != 3'd1 && + IF_out_fifo_enqueueElement_1_rl_075_BITS_231_T_ETC___d2411 == + 3'd0 ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2430 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[231:229] != 3'd0 && + (out_fifo_enqueueElement_1_lat_0$wget[231:229] == 3'd1 || + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2400 == + 3'd1) : + out_fifo_enqueueElement_1_rl[231:229] != 3'd0 && + (out_fifo_enqueueElement_1_rl[231:229] == 3'd1 || + IF_out_fifo_enqueueElement_1_rl_075_BITS_231_T_ETC___d2411 == + 3'd1) ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2442 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[231:229] != 3'd0 && + out_fifo_enqueueElement_1_lat_0$wget[231:229] != 3'd1 && + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2400 == + 3'd2 : + out_fifo_enqueueElement_1_rl[231:229] != 3'd0 && + out_fifo_enqueueElement_1_rl[231:229] != 3'd1 && + IF_out_fifo_enqueueElement_1_rl_075_BITS_231_T_ETC___d2411 == + 3'd2 ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2453 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[231:229] != 3'd0 && + out_fifo_enqueueElement_1_lat_0$wget[231:229] != 3'd1 && + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2400 == + 3'd3 : + out_fifo_enqueueElement_1_rl[231:229] != 3'd0 && + out_fifo_enqueueElement_1_rl[231:229] != 3'd1 && + IF_out_fifo_enqueueElement_1_rl_075_BITS_231_T_ETC___d2411 == + 3'd3 ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2482 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd2 && + (out_fifo_enqueueElement_1_lat_0$wget[235:232] == 4'd3 || + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281 == + 4'd3) : + out_fifo_enqueueElement_1_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd2 && + (out_fifo_enqueueElement_1_rl[235:232] == 4'd3 || + out_fifo_enqueueElement_1_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310 == + 4'd3) ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2506 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd3 && + (out_fifo_enqueueElement_1_lat_0$wget[235:232] == 4'd4 || + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281 == + 4'd4) : + out_fifo_enqueueElement_1_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd3 && + (out_fifo_enqueueElement_1_rl[235:232] == 4'd4 || + out_fifo_enqueueElement_1_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310 == + 4'd4) ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2529 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd4 && + (out_fifo_enqueueElement_1_lat_0$wget[235:232] == 4'd5 || + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281 == + 4'd5) : + out_fifo_enqueueElement_1_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd4 && + (out_fifo_enqueueElement_1_rl[235:232] == 4'd5 || + IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310 == + 4'd5) ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2553 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281 == + 4'd6 : + out_fifo_enqueueElement_1_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310 == + 4'd6 ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2576 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281 == + 4'd7 : + out_fifo_enqueueElement_1_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310 == + 4'd7 ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2599 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281 == + 4'd8 : + out_fifo_enqueueElement_1_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310 == + 4'd8 ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2622 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281 == + 4'd9 : + out_fifo_enqueueElement_1_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310 == + 4'd9 ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2645 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd0 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd1 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd2 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd3 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd4 && + out_fifo_enqueueElement_1_lat_0$wget[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281 == + 4'd10 : + out_fifo_enqueueElement_1_rl[235:232] != 4'd0 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd1 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd2 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd3 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd4 && + out_fifo_enqueueElement_1_rl[235:232] != 4'd5 && + IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310 == + 4'd10 ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2665 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[226:181] : + out_fifo_enqueueElement_1_rl[226:181] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3055 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[128:97] : + out_fifo_enqueueElement_1_rl[128:97] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3060 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[96] : + out_fifo_enqueueElement_1_rl[96] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3070 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[95:90] : + out_fifo_enqueueElement_1_rl[95:90] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3076 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[89] : + out_fifo_enqueueElement_1_rl[89] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3086 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[88:83] : + out_fifo_enqueueElement_1_rl[88:83] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3093 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[82] : + out_fifo_enqueueElement_1_rl[82] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3103 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[81:77] : + out_fifo_enqueueElement_1_rl[81:77] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3109 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[76] : + out_fifo_enqueueElement_1_rl[76] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3119 = + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[75:70] : + out_fifo_enqueueElement_1_rl[75:70] ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3505 = + { out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[180] : + out_fifo_enqueueElement_1_rl[180], + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[179:168] == 12'd1 : + out_fifo_enqueueElement_1_rl[179:168] == 12'd1) ? + 12'd1 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3488, + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[167] : + out_fifo_enqueueElement_1_rl[167], + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[166:162] == 5'd0 : + out_fifo_enqueueElement_1_rl[166:162] == 5'd0) ? + 5'd0 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3499, + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[161] : + out_fifo_enqueueElement_1_rl[161], + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[160:129] : + out_fifo_enqueueElement_1_rl[160:129] } ; + assign IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d3530 = + { out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[69] : + out_fifo_enqueueElement_1_rl[69], + (out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[68:64] == 5'd0 : + out_fifo_enqueueElement_1_rl[68:64] == 5'd0) ? + 5'd0 : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3527, + out_fifo_enqueueElement_1_lat_0$whas ? + out_fifo_enqueueElement_1_lat_0$wget[63:0] : + out_fifo_enqueueElement_1_rl[63:0] } ; + assign IF_out_fifo_enqueueFifo_lat_1_whas__83_THEN_ou_ETC___d889 = + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2077 ? + out_fifo_enqueueFifo_rl : + (IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d909 ? + upd__h24504 : + out_fifo_enqueueFifo_rl) ; + assign IF_out_fifo_willDequeue_0_lat_0_whas__236_THEN_ETC___d3239 = + EN_pipelines_0_deq || out_fifo_willDequeue_0_rl ; + assign IF_out_fifo_willDequeue_1_lat_0_whas__243_THEN_ETC___d3246 = + EN_pipelines_1_deq || out_fifo_willDequeue_1_rl ; + assign IF_pc_reg_lat_1_whas_THEN_pc_reg_lat_1_wget_EL_ETC___d11 = + pc_reg_lat_1$whas ? + upd__h999 : + (pc_reg_lat_0$whas ? upd__h1026 : pc_reg_rl) ; + assign IF_pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NO_ETC___d4745 = + pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NOT_I_ETC___d4733 ? + !SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 || + !IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4741 : + !SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 || + !IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4729 ; + assign IF_pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NO_ETC___d4764 = + pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NOT_I_ETC___d4733 ? + nextAddrPred_next_addrs$D_OUT_1 : + (IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4709 ? + nextAddrPred_next_addrs$D_OUT_2 : + nextAddrPred_next_addrs$D_OUT_3) ; + assign IF_pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NO_ETC___d4779 = + pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NOT_I_ETC___d4733 ? + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 && + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4741 : + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 && + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4729 ; + assign IF_perfReqQ_enqReq_lat_1_whas__342_THEN_perfRe_ETC___d4351 = + EN_perf_req ? + perfReqQ_enqReq_lat_0$wget[2] : + perfReqQ_enqReq_rl[2] ; + assign IF_rg_pending_n_items_951_EQ_0_952_THEN_NOT_eh_ETC___d5077 = + (rg_pending_n_items == 2'd0) ? + !ehr_pending_straddle_rl[146] : + !rg_pending_f32d_953_BITS_3_TO_0_954_EQ_f_main__ETC___d4955 || + !rg_pending_f32d_953_BIT_4_957_EQ_IF_decode_epo_ETC___d4958 || + !ehr_pending_straddle_rl[146] ; + assign IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 = + (rg_pending_n_items == 2'd0) ? + ehr_pending_straddle_rl[146] : + rg_pending_f32d_953_BITS_3_TO_0_954_EQ_f_main__ETC___d4955 && + rg_pending_f32d_953_BIT_4_957_EQ_IF_decode_epo_ETC___d4958 && + ehr_pending_straddle_rl[146] ; + assign IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d4965 = + pending_n_items__h113790 < 2'd2 ; + assign IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 = + pending_n_items__h113790 == 2'd0 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d4965 && + !f22f3_empty && + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 && + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4980 && + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4983 && + (IF_rg_pending_n_items_951_EQ_0_952_THEN_NOT_eh_ETC___d5077 || + !ehr_pending_straddle_rl[0]) ; + assign IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5156 = + (pending_n_items__h113790 == 2'd0 && + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d5069 && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5151) && + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5154) ; + assign IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5163 = + pending_n_items__h113790 == 2'd0 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d4965 && + !f22f3_empty && + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4980 && + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4983 && + (IF_rg_pending_n_items_951_EQ_0_952_THEN_NOT_eh_ETC___d5077 || + !ehr_pending_straddle_rl[0]) ; + assign NOT_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_20_ETC___d6951 = + !IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 || + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] != + 2'b11 || + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5237 ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992 = + pending_n_items__h113790 != 2'd0 && + (!IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d4965 || + f22f3_empty || + !SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 || + !SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4980 || + !SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4983 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 && + ehr_pending_straddle_rl[0]) ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4994 = + !IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d4965 || + f22f3_empty || + !SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4980 || + !SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4983 ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4996 = + pending_n_items__h113790 != 2'd0 && + (NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4994 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 && + ehr_pending_straddle_rl[0]) ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5009 = + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4996 || + f22f3_empty || + !SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 || + IF_NOT_f22f3_empty_17_919_AND_SEL_ARR_f22f3_da_ETC___d5007 ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5037 = + pending_n_items__h113790 != 2'd0 && + (NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4994 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 && + ehr_pending_straddle_rl[0]) ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5046 = + pending_n_items__h113790 != 2'd0 && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4994 || + f22f3_empty || + !SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 || + IF_NOT_f22f3_empty_17_919_AND_SEL_ARR_f22f3_da_ETC___d5007 ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5052 = + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992 || + !f22f3_empty && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5009 && + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d5044 && + CASE_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_2_ETC___d5040 && + (IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5046) ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5055 = + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5009 && + (IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5046 && + CASE_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_2_ETC___d5040) ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5058 = + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5052 && + (NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992 || + !f22f3_empty && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5055) ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5085 = + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5009 && + CASE_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_2_ETC___d5040 && + (IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5046) ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5090 = + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5037 || + f22f3_empty || + !SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 || + IF_NOT_f22f3_empty_17_919_AND_SEL_ARR_f22f3_da_ETC___d5007 ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5094 = + pending_n_items__h113790 != 2'd0 && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4994 || + f22f3_empty || + !SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 || + IF_NOT_f22f3_empty_17_919_AND_SEL_ARR_f22f3_da_ETC___d5007 ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5097 = + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5090 && + (IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5094 && + CASE_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_2_ETC___d5040) ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5130 = + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992 || + !f22f3_empty && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5090 && + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d5044 ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5151 = + (pending_n_items__h113790 != 2'd0 || !f22f3_empty) && + (IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5084 || + !f22f3_empty && + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5087 && + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5112) && + !f32d_full && + IF_instdata_full_lat_0_whas__75_THEN_NOT_instd_ETC___d5149 ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5154 = + (NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992 || + !f22f3_empty && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5085) && + (NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992 || + !f22f3_empty && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5055) ; + assign NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d6749 = + (pending_n_items__h113790 != 2'd0 || + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012) && + n_items__h145984 != 3'd0 && + next_enqP__h165312 == n__read__h165419 ; + assign NOT_SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_96_ETC___d5175 = + !SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 || + (SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003 ? + mmio$bootRomResp[65] : + iMem$to_proc_response_get[65]) ; + assign NOT_SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_96_ETC___d5181 = + !SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 || + (SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003 ? + mmio$bootRomResp[32] : + iMem$to_proc_response_get[32]) ; + assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9074 = + { !CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q309, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8998, + !CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q310, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9058, + !CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q311, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q312 } ; + assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9154 = + { !CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q129, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q130, + !CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q131, + !CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q132, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q133 } ; + assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9155 = + { !CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q317, + !CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q318, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q319, + !CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q320, + !CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q321, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q322, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9154 } ; + assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9240 = + { !CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q323, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9234, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q324 } ; + assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9539 = + { !CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q313, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9508, + !CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q314, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9531, + !CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q315, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q316 } ; + assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9569 = + { !CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q134, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q135, + !CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q136, + !CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q137, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q138 } ; + assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9570 = + { !CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q325, + !CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q326, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q327, + !CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q328, + !CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q329, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q330, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9569 } ; + assign NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9603 = + { !CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q331, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9600, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q332 } ; + assign NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5087 = + !SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4930 || + !SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4938 || + !SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4947 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5085 ; + assign NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5093 = + !SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4930 || + !SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4938 || + !SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4947 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5090 && + IF_IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_ETC___d5044 ; + assign NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099 = + !SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4930 || + !SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4938 || + !SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4947 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5097 ; + assign NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5106 = + !SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4930 || + !SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4938 || + !SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4947 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5090 ; + assign NOT_SEL_ARR_instdata_data_0_987_BITS_260_TO_25_ETC___d7566 = + SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_334_011_f32d_data__ETC___d7014 && + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d7552 && + SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7558[0] && + decode___d7558[171:167] == 5'd10 ; + assign NOT_SEL_ARR_instdata_data_0_987_BITS_65_TO_64__ETC___d8003 = + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998 && + !decode___d7047[0] && + IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d8000 ; + assign NOT_SEL_ARR_nextAddrPred_valid_0_read__422_nex_ETC___d4748 = + (!SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 || + !pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684) && + (cap__h109578[5:2] != 4'd15 || cap__h109578[1:0] == 2'b0) && + (!SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 || + !pc_reg_rl_BITS_63_TO_0_689_PLUS_2_690_BITS_63__ETC___d4704) ; + assign NOT_decode_047_BITS_25_TO_21_081_EQ_decode_047_ETC___d7117 = + decode___d7047[25:21] != decode___d7047[5:1] ; + assign NOT_decode_047_BIT_27_078_088_OR_decode_047_BI_ETC___d7095 = + (!decode___d7047[27] || + (decode___d7047[26] || decode___d7047[25:21] != 5'd1) && + (decode___d7047[26] || decode___d7047[25:21] != 5'd5)) && + decode___d7047[7] && + !decode___d7047[6] && + (decode___d7047[5:1] == 5'd1 || decode___d7047[5:1] == 5'd5) ; + assign NOT_decode_047_BIT_7_058_071_OR_decode_047_BIT_ETC___d7087 = + (!decode___d7047[7] || + (decode___d7047[6] || decode___d7047[5:1] != 5'd1) && + (decode___d7047[6] || decode___d7047[5:1] != 5'd5)) && + decode___d7047[27] && + !decode___d7047[26] && + (decode___d7047[25:21] == 5'd1 || + decode___d7047[25:21] == 5'd5) ; + assign NOT_decode_047_BIT_7_058_071_OR_decode_047_BIT_ETC___d7411 = + (!decode___d7047[7] || + (decode___d7047[6] || decode___d7047[5:1] != 5'd1) && + (decode___d7047[6] || decode___d7047[5:1] != 5'd5)) && + decode___d7047[27] && + !decode___d7047[26] && + (decode___d7047[25:21] == 5'd1 || + decode___d7047[25:21] == 5'd5) || + (NOT_decode_047_BIT_27_078_088_OR_decode_047_BI_ETC___d7095 ? + decodeBrPred___d7404[129] : + (decode_047_BIT_7_058_AND_NOT_decode_047_BIT_6__ETC___d7096 ? + IF_NOT_decode_047_BIT_26_079_080_AND_NOT_decod_ETC___d7120 || + decodeBrPred___d7404[129] : + decodeBrPred___d7404[129])) ; + assign NOT_decode_558_BITS_25_TO_21_592_EQ_decode_558_ETC___d7628 = + decode___d7558[25:21] != decode___d7558[5:1] ; + assign NOT_decode_558_BIT_27_589_599_OR_decode_558_BI_ETC___d7606 = + (!decode___d7558[27] || + (decode___d7558[26] || decode___d7558[25:21] != 5'd1) && + (decode___d7558[26] || decode___d7558[25:21] != 5'd5)) && + decode___d7558[7] && + !decode___d7558[6] && + (decode___d7558[5:1] == 5'd1 || decode___d7558[5:1] == 5'd5) ; + assign NOT_decode_558_BIT_7_569_582_OR_decode_558_BIT_ETC___d7598 = + (!decode___d7558[7] || + (decode___d7558[6] || decode___d7558[5:1] != 5'd1) && + (decode___d7558[6] || decode___d7558[5:1] != 5'd5)) && + decode___d7558[27] && + !decode___d7558[26] && + (decode___d7558[25:21] == 5'd1 || + decode___d7558[25:21] == 5'd5) ; + assign NOT_decode_558_BIT_7_569_582_OR_decode_558_BIT_ETC___d7922 = + (!decode___d7558[7] || + (decode___d7558[6] || decode___d7558[5:1] != 5'd1) && + (decode___d7558[6] || decode___d7558[5:1] != 5'd5)) && + decode___d7558[27] && + !decode___d7558[26] && + (decode___d7558[25:21] == 5'd1 || + decode___d7558[25:21] == 5'd5) || + (NOT_decode_558_BIT_27_589_599_OR_decode_558_BI_ETC___d7606 ? + decodeBrPred___d7915[129] : + (decode_558_BIT_7_569_AND_NOT_decode_558_BIT_6__ETC___d7607 ? + IF_NOT_decode_558_BIT_26_590_591_AND_NOT_decod_ETC___d7631 || + decodeBrPred___d7915[129] : + decodeBrPred___d7915[129])) ; + assign NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 = + !f22f3_empty && + (!SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4930 || + !SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4938 || + !SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4947) ; + assign NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d5069 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992 || + !f22f3_empty && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5009 && + (IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5046) && + CASE_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_2_ETC___d5040 ; + assign NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d5134 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992 || + !f22f3_empty && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5097 ; + assign NOT_iTlb_to_proc_response_get_801_BIT_5_802_80_ETC___d4915 = + { !iTlb$to_proc_response_get[5] && mmio$getFetchTarget == 2'd1, + CASE_f12f2_deqP_0_f12f2_data_0_BIT_5_1_f12f2_d_ETC__q303, + CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q304, + out_main_epoch__h112357 } ; + assign NOT_instdata_empty_rl_67_978_AND_NOT_SEL_ARR_f_ETC___d7025 = + !instdata_empty_rl && + (!SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d6985 || + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d7005 && + SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7018 && + (!napTrainByDecQ_empty_rl || !napTrainByDecQ_full_rl)) ; + assign NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_OR_ETC___d4708 = + (pc_reg_rl[5:2] != 4'd15 || pc_reg_rl[1:0] == 2'b0) && + (!SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 || + !pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684) && + (cap__h109578[5:2] != 4'd15 || cap__h109578[1:0] == 2'b0) && + (!SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 || + !pc_reg_rl_BITS_63_TO_0_689_PLUS_2_690_BITS_63__ETC___d4704) ; + assign SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6307 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5390, + CASE_pending_spaces_ext45988_0_IF_NOT_f22f3_em_ETC__q380, + x__h152277, + x__h152323 } ; + assign SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d5210 = + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 && + (SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003 ? !mmio$bootRomResp[32] : !iMem$to_proc_response_get[32]) ; - assign SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3981 = - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - (SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491 ? + assign SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d5223 = + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 && + (SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003 ? !mmio$bootRomResp[65] : !iMem$to_proc_response_get[65]) ; - assign SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d5434 = - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d4768[0] && - IF_decode_768_BITS_99_TO_95_772_EQ_8_779_AND_d_ETC___d4982 && - decode_pred_next_pc__h146966 != in_ppc__h143612 ; - assign SEL_ARR_f12f2_data_0_378_BITS_68_TO_5_388_f12f_ETC___d3466 = - { x__h116447, - iTlb$to_proc_response_get[4] || + assign SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7972 = + SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7047[0] && + IF_decode_047_BITS_171_TO_167_051_EQ_8_057_AND_ETC___d7413 && + decode_pred_next_pc__h177047 != in_ppc__h171466 ; + assign SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4930 = + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4929 == + f_main_epoch ; + assign SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4980 = + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4929 == + rg_pending_f32d[3:0] ; + assign SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4938 = + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4937 == + IF_decode_epoch_lat_0_whas__6_THEN_decode_epoc_ETC___d19 ; + assign SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4983 = + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4937 == + rg_pending_f32d[4] ; + assign SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4947 = + SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4946 == + fetch3_epoch ; + assign SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d6985 = + out_main_epoch__h177345 == f_main_epoch ; + assign SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d7615 = + SEL_ARR_f32d_data_0_979_BITS_3_TO_0_980_f32d_d_ETC___d6985 && + SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_334_011_f32d_data__ETC___d7014 && + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d7552 && + SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7558[0] && + decode_558_BITS_171_TO_167_562_EQ_8_568_AND_de_ETC___d7611 ; + assign SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998 = + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6997 == + decode_epoch_rl ; + assign SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d7552 = + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6997 == + IF_SEL_ARR_instdata_data_0_987_BITS_65_TO_64_9_ETC___d7551 ; + assign SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d8007 = + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998 && + SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7047[0] && + IF_IF_decode_047_BITS_171_TO_167_051_EQ_8_057__ETC___d8000 ; + assign SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7018 = + SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 == + 2'd0 || + !SEL_ARR_f32d_data_0_979_BIT_334_011_f32d_data__ETC___d7014 || + CASE_x0535_0_out_fifo_internalFifos_0FULL_N_1_ETC__q3 ; + assign SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d7005 = + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 == + 2'd0 || + !SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6998 || + CASE_out_fifo_enqueueFifo_rl_0_out_fifo_intern_ETC__q4 ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8090 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q351, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q352, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q353, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q354 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8147 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q23, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q24, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q25 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8156 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8147, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q41, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q42 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8165 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8156, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q45, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q46 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8174 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8165, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q49, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q50 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8183 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8174, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q53, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q54 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8192 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8183, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q57, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q58 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8201 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8192, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q61, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q62 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8219 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8201, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q123, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8209, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q124, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8217 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8220 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q149, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q150, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8219 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8234 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q65, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8209, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q66 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8291 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q31, + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d8290, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8217 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8745 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q112, + x__h200265, + x__h200270 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8746 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q115, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q116, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8745 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8747 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q119, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q120, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8746 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8748 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q127, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q128, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8747 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8749 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q141, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q142, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8748 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8750 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q145, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q146, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8749 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8751 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q151, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q152, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8750 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8752 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q157, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q158, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8751 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8753 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q161, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q162, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8752 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8754 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q165, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q166, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8753 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8755 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q169, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q170, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8754 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8756 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q173, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q174, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8755 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8757 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q177, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q178, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8756 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8758 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q181, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q182, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8757 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8759 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q305, + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q306, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8758 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9076 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q349, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8297, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d8620, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8759, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9074 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9243 = + { CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q359, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8090, + x__h195484, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9076, + x__h206149, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9155, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9240 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9253 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q355, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q356, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q357, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q358 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9269 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q36, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q37, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q38 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9272 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9269, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q39, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q40 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9275 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9272, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q43, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q44 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9278 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9275, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q47, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q48 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9281 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9278, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q51, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q52 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9284 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9281, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q55, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q56 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9287 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9284, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q59, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q60 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9293 = + { SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9287, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q121, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9289, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q122, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9291 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9294 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q147, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q148, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9293 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9299 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q63, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9289, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q64 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9313 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q72, + IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d9312, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9291 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9400 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q111, + x__h211978, + x__h211979 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9401 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q113, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q114, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9400 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9402 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q117, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q118, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9401 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9403 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q125, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q126, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9402 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9404 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q139, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q140, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9403 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9405 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q143, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q144, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9404 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9406 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q153, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q154, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9405 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9407 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q155, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q156, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9406 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9408 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q159, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q160, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9407 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9409 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q163, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q164, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9408 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9410 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q167, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q168, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9409 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9411 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q171, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q172, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9410 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9412 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q175, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q176, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9411 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9413 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q179, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q180, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9412 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9414 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q307, + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q308, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9413 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9541 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q350, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9319, + IF_SEL_ARR_out_fifo_internalFifos_0_first__059_ETC___d9368, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9414, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9539 } ; + assign SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9606 = + { CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q360, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9253, + x__h207737, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9541, + x__h217664, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9570, + NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d9603 } ; + assign SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5497 = + { {9{offset__h128155[11]}}, offset__h128155 } ; + assign SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5522 = + { {4{offset__h128788[8]}}, offset__h128788 } ; + assign SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5786 = + { {9{offset__h136909[11]}}, offset__h136909 } ; + assign SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5811 = + { {4{offset__h137542[8]}}, offset__h137542 } ; + assign SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6075 = + { {9{offset__h153181[11]}}, offset__h153181 } ; + assign SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6100 = + { {4{offset__h153814[8]}}, offset__h153814 } ; + assign SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6397 = + { {9{offset__h119355[11]}}, offset__h119355 } ; + assign SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6422 = + { {4{offset__h119991[8]}}, offset__h119991 } ; + assign _0_CONCAT_IF_rg_pending_n_items_951_EQ_0_952_TH_ETC___d5375 = + n_items__h145984 <= 3'd2 ; + assign _0_CONCAT_SEL_ARR_f22f3_data_0_920_BITS_337_TO__ETC___d5193 = + { 1'd0, nbSupX2In__h113561 } + 3'd1 ; + assign _2_CONCAT_IF_IF_out_fifo_enqueueElement_0_lat_0_ETC___d3279 = + { 4'd2, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1248 ? + { 3'd0, + IF_out_fifo_enqueueElement_0_lat_0_whas__04_TH_ETC___d1189 } : + IF_IF_out_fifo_enqueueElement_0_lat_0_whas__04_ETC___d3277 } ; + assign _2_CONCAT_IF_IF_out_fifo_enqueueElement_1_lat_0_ETC___d3426 = + { 4'd2, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2415 ? + { 3'd0, + IF_out_fifo_enqueueElement_1_lat_0_whas__072_T_ETC___d2356 } : + IF_IF_out_fifo_enqueueElement_1_lat_0_whas__07_ETC___d3424 } ; + assign _2_CONCAT_IF_SEL_ARR_out_fifo_internalFifos_0_f_ETC___d8475 = + { 4'd2, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8441 ? + { 3'd0, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8400 } : + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d8473 } ; + assign _2_CONCAT_IF_SEL_ARR_out_fifo_internalFifos_0_f_ETC___d9343 = + { 4'd2, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9332 ? + { 3'd0, + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9329 } : + IF_SEL_ARR_NOT_out_fifo_internalFifos_0_first__ETC___d9341 } ; + assign _dand1iMem$EN_to_proc_response_get = + WILL_FIRE_RL_doFetch3 && + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5163) && + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 && + !SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003 ; + assign _theResult_____2__h14823 = + IF_f22f3_deqReq_lat_1_whas__76_THEN_f22f3_deqR_ETC___d382 ? + next_deqP___1__h15012 : + f22f3_deqP ; + assign _theResult_____2__h20522 = + IF_f32d_deqReq_lat_1_whas__11_THEN_f32d_deqReq_ETC___d717 ? + next_deqP___1__h20711 : + f32d_deqP ; + assign _theResult_____2__h6605 = + IF_f12f2_deqReq_lat_1_whas__13_THEN_f12f2_deqR_ETC___d119 ? + next_deqP___1__h6794 : + f12f2_deqP ; + assign _theResult___fst__h117329 = + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5237 ? + j__h117346 : + y_avValue_fst__h117191 ; + assign _theResult___fst__h126265 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249 ? + j__h126282 : + y_avValue_fst__h126140 ; + assign _theResult___fst__h134976 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260 ? + j__h134993 : + y_avValue_fst__h134851 ; + assign _theResult___snd_fst__h117672 = + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5237 ? + orig_inst___1__h117345 : + 32'd0 ; + assign _theResult___snd_fst__h126562 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249 ? + orig_inst___1__h126281 : + 32'd0 ; + assign _theResult___snd_fst__h135273 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260 ? + orig_inst___1__h134992 : + 32'd0 ; + assign _theResult___snd_fst__h144006 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5271 ? + orig_inst___1__h146034 : + 32'd0 ; + assign _theResult___snd_snd_fst__h110304 = + ((cap__h109578[5:2] != 4'd15 || cap__h109578[1:0] == 2'b0) && + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4709) ? + prev_PC__h110311 : + cap__h109578 ; + assign _theResult___snd_snd_snd_fst__h117676 = + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5237 ? + next_pc___1__h117347 : + pc_start__h114675[63:0] ; + assign _theResult___snd_snd_snd_fst__h126566 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5249 ? + next_pc___1__h126283 : + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5333 ; + assign _theResult___snd_snd_snd_fst__h135277 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5260 ? + next_pc___1__h134994 : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5342 ; + assign _theResult___snd_snd_snd_fst__h144010 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5271 ? + next_pc___1__h146036 : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5351 ; + assign a__h144061 = + { pc_start__h114675[128:64], + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5351 } ; + assign address__h109631 = pc_reg_rl[63:0] + 64'd2 ; + assign address__h110316 = cap__h109578[63:0] + 64'd2 ; + assign address__h111404 = + pc_reg_rl[63:0] + { {52{inc__h111403[11]}}, inc__h111403 } ; + assign address__h118137 = + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196 ? + y_avValue_snd_fst__h117557 : + pc_start__h114675[63:0] ; + assign address__h145071 = cap__h145069[63:0] + 64'd2 ; + assign address__h161170 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5266 ? + y_avValue_snd_snd_snd_snd_fst__h143793 : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5351 ; + assign address__h172257 = + x__h171664[63:0] + { {52{inc__h172256[11]}}, inc__h172256 } ; + assign address__h182904 = + SEL_ARR_instdata_data_0_987_BITS_389_TO_261_42_ETC___d7425[63:0] + + { {52{inc__h182903[11]}}, inc__h182903 } ; + assign address__h193189 = + SEL_ARR_instdata_data_0_987_BITS_389_TO_261_42_ETC___d7425[63:0] + + { {52{inc__h193188[11]}}, inc__h193188 } ; + assign address__h193365 = + x__h171664[63:0] + { {52{inc__h193364[11]}}, inc__h193364 } ; + assign address__h193564 = x__h171664[63:0] + 64'd2 ; + assign address__h194902 = x__h194838[63:0] + 64'd2 ; + assign address__h225906 = + train_predictors_pc[63:0] + + { {52{inc__h225905[11]}}, inc__h225905 } ; + assign b__h114808 = + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5037 || + NOT_SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_96_ETC___d5181 ; + assign b__h114820 = + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5037 || + NOT_SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_96_ETC___d5175 ; + assign cap__h109578 = + ((pc_reg_rl[5:2] != 4'd15 || pc_reg_rl[1:0] == 2'b0) && + (!SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 || + !pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684)) ? + prev_PC__h109626 : + pc_reg_rl ; + assign cap__h110263 = + ((pc_reg_rl[5:2] != 4'd15 || pc_reg_rl[1:0] == 2'b0) && + (!SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 || + !pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684)) ? + _theResult___snd_snd_fst__h110304 : + cap__h109578 ; + assign cap__h145069 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5266 ? + IF_NOT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_N_ETC___d5353 : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5345 ; + assign decode_047_BITS_171_TO_167_051_CONCAT_IF_decod_ETC___d7400 = + { decode___d7047[171:167], + CASE_decode_047_BITS_166_TO_164_0_decode_047_B_ETC__q17, + CASE_decode_047_BITS_136_TO_135_0_decode_047_B_ETC__q18, + decode___d7047[125:79], + CASE_decode_047_BITS_78_TO_67_1_decode_047_BIT_ETC__q19, + decode___d7047[66], + CASE_decode_047_BITS_65_TO_61_0_decode_047_BIT_ETC__q20, + decode___d7047[60:28] } ; + assign decode_047_BITS_171_TO_167_051_EQ_8_057_AND_de_ETC___d7100 = + decode___d7047[171:167] == 5'd8 && decode___d7047[7] && + !decode___d7047[6] && + (decode___d7047[5:1] == 5'd1 || decode___d7047[5:1] == 5'd5) || + (decode___d7047[171:167] == 5'd9 || + decode___d7047[171:167] == 5'd12) && + (NOT_decode_047_BIT_7_058_071_OR_decode_047_BIT_ETC___d7087 || + NOT_decode_047_BIT_27_078_088_OR_decode_047_BI_ETC___d7095 || + decode_047_BIT_7_058_AND_NOT_decode_047_BIT_6__ETC___d7096) ; + assign decode_047_BIT_7_058_AND_NOT_decode_047_BIT_6__ETC___d7096 = + decode___d7047[7] && !decode___d7047[6] && + (decode___d7047[5:1] == 5'd1 || decode___d7047[5:1] == 5'd5) && + decode___d7047[27] && + !decode___d7047[26] && + (decode___d7047[25:21] == 5'd1 || + decode___d7047[25:21] == 5'd5) ; + assign decode_558_BITS_171_TO_167_562_CONCAT_IF_decod_ETC___d7911 = + { decode___d7558[171:167], + CASE_decode_558_BITS_166_TO_164_0_decode_558_B_ETC__q10, + CASE_decode_558_BITS_136_TO_135_0_decode_558_B_ETC__q11, + decode___d7558[125:79], + CASE_decode_558_BITS_78_TO_67_1_decode_558_BIT_ETC__q12, + decode___d7558[66], + CASE_decode_558_BITS_65_TO_61_0_decode_558_BIT_ETC__q13, + decode___d7558[60:28] } ; + assign decode_558_BITS_171_TO_167_562_EQ_8_568_AND_de_ETC___d7611 = + decode___d7558[171:167] == 5'd8 && decode___d7558[7] && + !decode___d7558[6] && + (decode___d7558[5:1] == 5'd1 || decode___d7558[5:1] == 5'd5) || + (decode___d7558[171:167] == 5'd9 || + decode___d7558[171:167] == 5'd12) && + (NOT_decode_558_BIT_7_569_582_OR_decode_558_BIT_ETC___d7598 || + NOT_decode_558_BIT_27_589_599_OR_decode_558_BI_ETC___d7606 || + decode_558_BIT_7_569_AND_NOT_decode_558_BIT_6__ETC___d7607) ; + assign decode_558_BIT_7_569_AND_NOT_decode_558_BIT_6__ETC___d7607 = + decode___d7558[7] && !decode___d7558[6] && + (decode___d7558[5:1] == 5'd1 || decode___d7558[5:1] == 5'd5) && + decode___d7558[27] && + !decode___d7558[26] && + (decode___d7558[25:21] == 5'd1 || + decode___d7558[25:21] == 5'd5) ; + assign decode_pred_next_pc__h177047 = + (decode___d7047[171:167] == 5'd8 && decode___d7047[7] && + !decode___d7047[6] && + (decode___d7047[5:1] == 5'd1 || decode___d7047[5:1] == 5'd5)) ? + decodeBrPred___d7404[128:0] : + CASE_decode_047_BITS_171_TO_167_9_IF_NOT_decod_ETC__q21 ; + assign decode_pred_next_pc__h187627 = + (decode___d7558[171:167] == 5'd8 && decode___d7558[7] && + !decode___d7558[6] && + (decode___d7558[5:1] == 5'd1 || decode___d7558[5:1] == 5'd5)) ? + decodeBrPred___d7915[128:0] : + CASE_decode_558_BITS_171_TO_167_9_IF_NOT_decod_ETC__q14 ; + assign def__h108385 = { pc_reg_rl[128:64], address__h111404 } ; + assign def__h161167 = { pc_start__h114675[128:64], address__h161170 } ; + assign f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 = + f22f3_empty || + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4930 && + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4938 && + SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4947 ; + assign f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5019 = + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + pending_n_items__h113790 != 2'd0 && + (NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4994 || + ehr_pending_straddle_rl[0]) || + f22f3_empty || + !SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 || + IF_NOT_f22f3_empty_17_919_AND_SEL_ARR_f22f3_da_ETC___d5007 ; + assign f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5023 = + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + pending_n_items__h113790 != 2'd0 && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4994 || + f22f3_empty || + !SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 || + IF_NOT_f22f3_empty_17_919_AND_SEL_ARR_f22f3_da_ETC___d5007 ; + assign f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5039 = + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5037 || + f22f3_empty || + !SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 || + IF_NOT_f22f3_empty_17_919_AND_SEL_ARR_f22f3_da_ETC___d5007 ; + assign f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5063 = + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d4992 || + !f22f3_empty && + (!SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 || + IF_NOT_f22f3_empty_17_919_AND_SEL_ARR_f22f3_da_ETC___d5007) ; + assign iTlb_to_proc_response_get_801_BIT_5_802_OR_NOT_ETC___d4916 = + { iTlb$to_proc_response_get[5] || mmio$getFetchTarget != 2'd0 && mmio$getFetchTarget != 2'd1, - (!iTlb$to_proc_response_get[4] && + (!iTlb$to_proc_response_get[5] && (mmio$getFetchTarget == 2'd0 || mmio$getFetchTarget == 2'd1)) ? - 4'hA : - ((iTlb$to_proc_response_get[4] ? - iTlb$to_proc_response_get[3:0] == 4'd0 : + 5'h0A : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == 5'd0 : (mmio$getFetchTarget == 2'd0 || mmio$getFetchTarget == 2'd1) && - iTlb$to_proc_response_get[3:0] == 4'd0) ? - 4'd0 : - ((iTlb$to_proc_response_get[4] ? - iTlb$to_proc_response_get[3:0] == 4'd1 : + iTlb$to_proc_response_get[4:0] == 5'd0) ? + 5'd0 : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == 5'd1 : mmio$getFetchTarget != 2'd0 && mmio$getFetchTarget != 2'd1 || - iTlb$to_proc_response_get[3:0] == 4'd1) ? - 4'd1 : - ((iTlb$to_proc_response_get[4] ? - iTlb$to_proc_response_get[3:0] == 4'd2 : + iTlb$to_proc_response_get[4:0] == 5'd1) ? + 5'd1 : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == 5'd2 : (mmio$getFetchTarget == 2'd0 || mmio$getFetchTarget == 2'd1) && - iTlb$to_proc_response_get[3:0] == 4'd2) ? - 4'd2 : - ((iTlb$to_proc_response_get[4] ? - iTlb$to_proc_response_get[3:0] == 4'd3 : + iTlb$to_proc_response_get[4:0] == 5'd2) ? + 5'd2 : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == 5'd3 : (mmio$getFetchTarget == 2'd0 || mmio$getFetchTarget == 2'd1) && - iTlb$to_proc_response_get[3:0] == 4'd3) ? - 4'd3 : - ((iTlb$to_proc_response_get[4] ? - iTlb$to_proc_response_get[3:0] == 4'd4 : + iTlb$to_proc_response_get[4:0] == 5'd3) ? + 5'd3 : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == 5'd4 : (mmio$getFetchTarget == 2'd0 || mmio$getFetchTarget == 2'd1) && - iTlb$to_proc_response_get[3:0] == 4'd4) ? - 4'd4 : - ((iTlb$to_proc_response_get[4] ? - iTlb$to_proc_response_get[3:0] == 4'd5 : + iTlb$to_proc_response_get[4:0] == 5'd4) ? + 5'd4 : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == 5'd5 : (mmio$getFetchTarget == 2'd0 || mmio$getFetchTarget == 2'd1) && - iTlb$to_proc_response_get[3:0] == 4'd5) ? - 4'd5 : - ((iTlb$to_proc_response_get[4] ? - iTlb$to_proc_response_get[3:0] == - 4'd6 : + iTlb$to_proc_response_get[4:0] == 5'd5) ? + 5'd5 : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == + 5'd6 : (mmio$getFetchTarget == 2'd0 || mmio$getFetchTarget == 2'd1) && - iTlb$to_proc_response_get[3:0] == - 4'd6) ? - 4'd6 : - ((iTlb$to_proc_response_get[4] ? - iTlb$to_proc_response_get[3:0] == - 4'd7 : + iTlb$to_proc_response_get[4:0] == + 5'd6) ? + 5'd6 : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == + 5'd7 : (mmio$getFetchTarget == 2'd0 || mmio$getFetchTarget == 2'd1) && - iTlb$to_proc_response_get[3:0] == - 4'd7) ? - 4'd7 : - ((iTlb$to_proc_response_get[4] ? - iTlb$to_proc_response_get[3:0] == - 4'd8 : + iTlb$to_proc_response_get[4:0] == + 5'd7) ? + 5'd7 : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == + 5'd8 : (mmio$getFetchTarget == 2'd0 || mmio$getFetchTarget == 2'd1) && - iTlb$to_proc_response_get[3:0] == - 4'd8) ? - 4'd8 : - ((iTlb$to_proc_response_get[4] ? - iTlb$to_proc_response_get[3:0] == - 4'd9 : + iTlb$to_proc_response_get[4:0] == + 5'd8) ? + 5'd8 : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == + 5'd9 : (mmio$getFetchTarget == 2'd0 || mmio$getFetchTarget == 2'd1) && - iTlb$to_proc_response_get[3:0] == - 4'd9) ? - 4'd9 : - ((iTlb$to_proc_response_get[4] ? - iTlb$to_proc_response_get[3:0] == - 4'd11 : + iTlb$to_proc_response_get[4:0] == + 5'd9) ? + 5'd9 : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == + 5'd11 : (mmio$getFetchTarget == 2'd0 || mmio$getFetchTarget == 2'd1) && - iTlb$to_proc_response_get[3:0] == - 4'd11) ? - 4'd11 : - ((iTlb$to_proc_response_get[4] ? - iTlb$to_proc_response_get[3:0] == - 4'd12 : + iTlb$to_proc_response_get[4:0] == + 5'd11) ? + 5'd11 : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == + 5'd12 : (mmio$getFetchTarget == 2'd0 || mmio$getFetchTarget == 2'd1) && - iTlb$to_proc_response_get[3:0] == - 4'd12) ? - 4'd12 : - ((iTlb$to_proc_response_get[4] ? - iTlb$to_proc_response_get[3:0] == - 4'd13 : + iTlb$to_proc_response_get[4:0] == + 5'd12) ? + 5'd12 : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == + 5'd13 : (mmio$getFetchTarget == 2'd0 || mmio$getFetchTarget == 2'd1) && - iTlb$to_proc_response_get[3:0] == - 4'd13) ? - 4'd13 : - 4'd15))))))))))))), - IF_iTlb_to_proc_response_get_369_BIT_4_370_THE_ETC___d3465 } ; - assign SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 = - start_PC__h117515 == y__h117541 ; - assign SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 = - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3501 == - decode_epoch ; - assign SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3569 = - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 ; - assign SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3715 = - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 && - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 ; - assign SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3814 = - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 && - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3808 ; - assign SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d4646 = - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - next_enqP__h139674 == - (instdata_deqP_dummy2_1$Q_OUT && - IF_instdata_deqP_lat_0_whas__77_THEN_instdata__ETC___d780) ; - assign SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 = - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4683 == - f_main_epoch ; - assign SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d5167 = - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 == - 2'd3 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165 ; - assign SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d5237 = - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 != - 2'd3 && - SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 != - 2'd0 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165 && - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d5180[0] && - decode_180_BITS_99_TO_95_184_EQ_8_191_AND_deco_ETC___d5232 ; - assign SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 = - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4700 == - decode_epoch ; - assign SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165 = - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4700 == - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5164 ; - assign SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4723 = - SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 == - 2'd0 || - !SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719 || - CASE_x4600_0_out_fifo_internalFifos_0FULL_N_1_ETC__q2 ; - assign SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4708 = - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 == - 2'd0 || - !SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 || - CASE_x4856_0_out_fifo_internalFifos_0FULL_N_1_ETC__q3 ; - assign SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4735 = - (SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 == - 2'd3 || - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4708) && - (SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 == - 2'd3 || - SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4723) && - (!napTrainByDecQ_full_dummy2_1$Q_OUT || - !napTrainByDecQ_full_dummy2_2$Q_OUT || - CAN_FIRE_RL_setTrainNAPByDec || - !napTrainByDecQ_full_rl) ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5548 = - { CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q208, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q209 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5605 = - { CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q10, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q11, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q12 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5614 = - { SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5605, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q24, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q25 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5623 = - { SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5614, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q28, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q29 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5636 = - { SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5623, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5627, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q54, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5635 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5637 = - { CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q57, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q58, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5636 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5651 = - { CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q32, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5627, - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q33 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5708 = - { CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d5707, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5635 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5918 = - { CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d5714, - NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d5917 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6132 = - { CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q214, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5548, - x__h161061, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5918, - x__h166575, - NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d5997, - NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6129 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6142 = - { CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q210, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q211, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q212, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q213 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6158 = - { CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6161 = - { SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6158, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q23 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6164 = - { SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6161, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q26, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q27 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6168 = - { SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6164, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6165, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q53, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6167 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6169 = - { CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q55, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q56, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6168 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6174 = - { CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q30, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6165, - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q31 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6188 = - { CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q39, - IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6187, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6167 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6275 = - { CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204, - IF_SEL_ARR_out_fifo_internalFifos_0_first__517_ETC___d6194, - NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6274 } ; - assign SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6338 = - { CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q215, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6142, - x__h168161, - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6275, - x__h173399, - NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6304, - NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6335 } ; - assign SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4117 = - { {9{offset__h132330[11]}}, offset__h132330 } ; - assign SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4142 = - { {4{offset__h132963[8]}}, offset__h132963 } ; - assign SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4410 = - { {9{offset__h123776[11]}}, offset__h123776 } ; - assign SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4435 = - { {4{offset__h124412[8]}}, offset__h124412 } ; - assign _dfoo1 = - x__h63120 == 1'd1 && out_fifo_willDequeue_0_dummy2_1$Q_OUT && - IF_out_fifo_willDequeue_0_lat_0_whas__959_THEN_ETC___d1962 || - x__h72803 == 1'd1 && out_fifo_willDequeue_1_dummy2_1$Q_OUT && - IF_out_fifo_willDequeue_1_lat_0_whas__966_THEN_ETC___d1969 ; - assign _dfoo2 = - x__h63120 == 1'd0 && out_fifo_willDequeue_0_dummy2_1$Q_OUT && - IF_out_fifo_willDequeue_0_lat_0_whas__959_THEN_ETC___d1962 || - x__h72803 == 1'd0 && out_fifo_willDequeue_1_dummy2_1$Q_OUT && - IF_out_fifo_willDequeue_1_lat_0_whas__966_THEN_ETC___d1969 ; - assign _dfoo3 = - x__h54856 == 1'd1 && out_fifo_enqueueElement_0_dummy2_1$Q_OUT && - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d830 || - x__h64600 == 1'd1 && out_fifo_enqueueElement_1_dummy2_1$Q_OUT && - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1398 ; - assign _dfoo5 = - x__h54856 == 1'd0 && out_fifo_enqueueElement_0_dummy2_1$Q_OUT && - IF_out_fifo_enqueueElement_0_lat_0_whas__25_TH_ETC___d830 || - x__h64600 == 1'd0 && out_fifo_enqueueElement_1_dummy2_1$Q_OUT && - IF_out_fifo_enqueueElement_1_lat_0_whas__393_T_ETC___d1398 ; - assign _dfoo523 = - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 == - 2'd3 && - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 || - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d5167 ; - assign _theResult_____2__h19260 = - (f22f3_deqReq_dummy2_2$Q_OUT && - IF_f22f3_deqReq_lat_1_whas__94_THEN_f22f3_deqR_ETC___d300) ? - next_deqP___1__h19579 : - f22f3_deqP ; - assign _theResult_____2__h28906 = - (f32d_deqReq_dummy2_2$Q_OUT && - IF_f32d_deqReq_lat_1_whas__26_THEN_f32d_deqReq_ETC___d632) ? - next_deqP___1__h29225 : - f32d_deqP ; - assign _theResult_____2__h7993 = - (f12f2_deqReq_dummy2_2$Q_OUT && - IF_f12f2_deqReq_lat_1_whas__3_THEN_f12f2_deqRe_ETC___d49) ? - next_deqP___1__h8312 : - f12f2_deqP ; - assign _theResult___fst__h122094 = - IF_IF_rg_pending_straddle_514_THEN_IF_SEL_ARR__ETC___d4031 ? - j__h122111 : - y_avValue_fst__h122004 ; - assign _theResult___snd_fst__h122365 = - IF_IF_rg_pending_straddle_514_THEN_IF_SEL_ARR__ETC___d4031 ? - orig_inst___1__h122110 : + iTlb$to_proc_response_get[4:0] == + 5'd13) ? + 5'd13 : + ((iTlb$to_proc_response_get[5] ? + iTlb$to_proc_response_get[4:0] == + 5'd15 : + (mmio$getFetchTarget == + 2'd0 || + mmio$getFetchTarget == + 2'd1) && + iTlb$to_proc_response_get[4:0] == + 5'd15) ? + 5'd15 : + 5'd28)))))))))))))), + out_tval__h112353, + NOT_iTlb_to_proc_response_get_801_BIT_5_802_80_ETC___d4915 } ; + assign imm12__h118640 = { 4'd0, offset__h118483 } ; + assign imm12__h118981 = { 5'd0, offset__h118923 } ; + assign imm12__h120630 = { {6{imm6__h120628[5]}}, imm6__h120628 } ; + assign imm12__h121314 = { {2{nzimm10__h121312[9]}}, nzimm10__h121312 } ; + assign imm12__h121532 = { 2'd0, nzimm10__h121530 } ; + assign imm12__h121729 = { 6'b0, imm6__h120628 } ; + assign imm12__h122069 = { 6'b010000, imm6__h120628 } ; + assign imm12__h123706 = { 3'd0, offset__h123619 } ; + assign imm12__h124062 = { 4'd0, offset__h123996 } ; + assign imm12__h127440 = { 4'd0, offset__h127348 } ; + assign imm12__h127781 = { 5'd0, offset__h127723 } ; + assign imm12__h129427 = { {6{imm6__h129425[5]}}, imm6__h129425 } ; + assign imm12__h130111 = { {2{nzimm10__h130109[9]}}, nzimm10__h130109 } ; + assign imm12__h130329 = { 2'd0, nzimm10__h130327 } ; + assign imm12__h130526 = { 6'b0, imm6__h129425 } ; + assign imm12__h130866 = { 6'b010000, imm6__h129425 } ; + assign imm12__h132503 = { 3'd0, offset__h132416 } ; + assign imm12__h132859 = { 4'd0, offset__h132793 } ; + assign imm12__h136194 = { 4'd0, offset__h136102 } ; + assign imm12__h136535 = { 5'd0, offset__h136477 } ; + assign imm12__h138181 = { {6{imm6__h138179[5]}}, imm6__h138179 } ; + assign imm12__h138865 = { {2{nzimm10__h138863[9]}}, nzimm10__h138863 } ; + assign imm12__h139083 = { 2'd0, nzimm10__h139081 } ; + assign imm12__h139280 = { 6'b0, imm6__h138179 } ; + assign imm12__h139620 = { 6'b010000, imm6__h138179 } ; + assign imm12__h141257 = { 3'd0, offset__h141170 } ; + assign imm12__h141613 = { 4'd0, offset__h141547 } ; + assign imm12__h152466 = { 4'd0, offset__h152374 } ; + assign imm12__h152807 = { 5'd0, offset__h152749 } ; + assign imm12__h154453 = { {6{imm6__h154451[5]}}, imm6__h154451 } ; + assign imm12__h155137 = { {2{nzimm10__h155135[9]}}, nzimm10__h155135 } ; + assign imm12__h155355 = { 2'd0, nzimm10__h155353 } ; + assign imm12__h155552 = { 6'b0, imm6__h154451 } ; + assign imm12__h155892 = { 6'b010000, imm6__h154451 } ; + assign imm12__h157529 = { 3'd0, offset__h157442 } ; + assign imm12__h157885 = { 4'd0, offset__h157819 } ; + assign imm20__h120761 = { {14{imm6__h120628[5]}}, imm6__h120628 } ; + assign imm20__h129558 = { {14{imm6__h129425[5]}}, imm6__h129425 } ; + assign imm20__h138312 = { {14{imm6__h138179[5]}}, imm6__h138179 } ; + assign imm20__h154584 = { {14{imm6__h154451[5]}}, imm6__h154451 } ; + assign imm6__h120628 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:2] } ; + assign imm6__h129425 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:2] } ; + assign imm6__h138179 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:2] } ; + assign imm6__h154451 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:2] } ; + assign in_ppc__h171466 = + SEL_ARR_f32d_data_0_979_BIT_334_011_f32d_data__ETC___d7014 ? + SEL_ARR_instdata_data_0_987_BITS_389_TO_261_42_ETC___d7425 : + in_ppc__h182302 ; + assign inc__h111403 = { x11563_PLUS_1__q2[10:0], 1'd0 } ; + assign inc__h172256 = + (SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 == + 2'd2) ? + 12'd4 : + 12'd2 ; + assign inc__h182903 = + (SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 == + 2'd2) ? + 12'd4 : + 12'd2 ; + assign inc__h193188 = + (SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 == + 2'd2) ? + 12'd2 : + 12'd0 ; + assign inc__h193364 = + (SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 == + 2'd2) ? + 12'd2 : + 12'd0 ; + assign inc__h225905 = train_predictors_isCompressed ? 12'd0 : 12'd2 ; + assign inst__h149818 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + n_inst__h127069 : 32'd0 ; - assign _theResult___snd_fst__h131373 = - IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4048 ? - orig_inst___1__h131399 : + assign inst__h149822 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + 32'd0 : + inst__h149818 ; + assign inst__h150160 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + n_inst__h135823 : 32'd0 ; - assign _theResult___snd_snd_snd_fst__h122369 = - IF_IF_rg_pending_straddle_514_THEN_IF_SEL_ARR__ETC___d4031 ? - next_pc___1__h122112 : - next_pc___1__h122117 ; - assign b__h119858 = - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 || - (SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491 ? - mmio$bootRomResp[32] : - iMem$to_proc_response_get[32]) ; - assign b__h119870 = - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 || - (SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491 ? - mmio$bootRomResp[65] : - iMem$to_proc_response_get[65]) ; - assign decode_180_BITS_99_TO_95_184_CONCAT_IF_decode__ETC___d5381 = - { decode___d5180[99:95], - CASE_decode_180_BITS_94_TO_92_0_decode_180_BIT_ETC__q5, - decode___d5180[73], - CASE_decode_180_BITS_72_TO_61_1_decode_180_BIT_ETC__q6, - decode___d5180[60:28] } ; - assign decode_180_BITS_99_TO_95_184_EQ_8_191_AND_deco_ETC___d5232 = - decode___d5180[99:95] == 5'd8 && decode___d5180[7] && - !decode___d5180[6] && - (decode___d5180[5:1] == 5'd1 || decode___d5180[5:1] == 5'd5) || - decode___d5180[99:95] == 5'd9 && - (NOT_decode_180_BIT_7_192_203_OR_decode_180_BIT_ETC___d5219 || - NOT_decode_180_BIT_27_210_220_OR_decode_180_BI_ETC___d5227 || - decode_180_BIT_7_192_AND_NOT_decode_180_BIT_6__ETC___d5228) ; - assign decode_180_BIT_7_192_AND_NOT_decode_180_BIT_6__ETC___d5228 = - decode___d5180[7] && !decode___d5180[6] && - (decode___d5180[5:1] == 5'd1 || decode___d5180[5:1] == 5'd5) && - decode___d5180[27] && - !decode___d5180[26] && - (decode___d5180[25:21] == 5'd1 || - decode___d5180[25:21] == 5'd5) ; - assign decode_768_BITS_99_TO_95_772_CONCAT_IF_decode__ETC___d4969 = - { decode___d4768[99:95], - CASE_decode_768_BITS_94_TO_92_0_decode_768_BIT_ETC__q8, - decode___d4768[73], - CASE_decode_768_BITS_72_TO_61_1_decode_768_BIT_ETC__q9, - decode___d4768[60:28] } ; - assign decode_768_BITS_99_TO_95_772_EQ_8_779_AND_deco_ETC___d4820 = - decode___d4768[99:95] == 5'd8 && decode___d4768[7] && - !decode___d4768[6] && - (decode___d4768[5:1] == 5'd1 || decode___d4768[5:1] == 5'd5) || - decode___d4768[99:95] == 5'd9 && - (NOT_decode_768_BIT_7_780_791_OR_decode_768_BIT_ETC___d4807 || - NOT_decode_768_BIT_27_798_808_OR_decode_768_BI_ETC___d4815 || - decode_768_BIT_7_780_AND_NOT_decode_768_BIT_6__ETC___d4816) ; - assign decode_768_BIT_7_780_AND_NOT_decode_768_BIT_6__ETC___d4816 = - decode___d4768[7] && !decode___d4768[6] && - (decode___d4768[5:1] == 5'd1 || decode___d4768[5:1] == 5'd5) && - decode___d4768[27] && - !decode___d4768[26] && - (decode___d4768[25:21] == 5'd1 || - decode___d4768[25:21] == 5'd5) ; - assign decode_pred_next_pc__h146966 = - (decode___d4768[99:95] == 5'd8 && decode___d4768[7] && - !decode___d4768[6] && - (decode___d4768[5:1] == 5'd1 || decode___d4768[5:1] == 5'd5)) ? - decodeBrPred___d4973[63:0] : - ((decode___d4768[99:95] == 5'd9) ? - IF_NOT_decode_768_BIT_7_780_791_OR_decode_768__ETC___d4988 : - decodeBrPred___d4973[63:0]) ; - assign decode_pred_next_pc__h153837 = - (decode___d5180[99:95] == 5'd8 && decode___d5180[7] && - !decode___d5180[6] && - (decode___d5180[5:1] == 5'd1 || decode___d5180[5:1] == 5'd5)) ? - decodeBrPred___d5385[63:0] : - ((decode___d5180[99:95] == 5'd9) ? - IF_NOT_decode_180_BIT_7_192_203_OR_decode_180__ETC___d5400 : - decodeBrPred___d5385[63:0]) ; - assign f12f2_enqReq_dummy2_2_read__4_AND_IF_f12f2_enq_ETC___d90 = - f12f2_enqReq_dummy2_2$Q_OUT && - IF_f12f2_enqReq_lat_1_whas__4_THEN_f12f2_enqRe_ETC___d23 || - (!f12f2_deqReq_dummy2_2$Q_OUT || - !WILL_FIRE_RL_doFetch2 && !f12f2_deqReq_rl) && - f12f2_full ; - assign f22f3_empty_47_OR_NOT_SEL_ARR_NOT_f22f3_data_0_ETC___d3495 = - f22f3_empty || - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 || - (SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491 ? - mmio$RDY_bootRomResp : - iMem$RDY_to_proc_response_get) ; - assign f22f3_empty_47_OR_NOT_SEL_ARR_NOT_f22f3_data_0_ETC___d3539 = - f22f3_empty_47_OR_NOT_SEL_ARR_NOT_f22f3_data_0_ETC___d3495 && - (!SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 || - !f32d_full && - NOT_instdata_full_dummy2_1_read__505_506_OR_NO_ETC___d3536) ; - assign f22f3_enqReq_dummy2_2_read__11_AND_IF_f22f3_en_ETC___d342 = - f22f3_enqReq_dummy2_2$Q_OUT && - IF_f22f3_enqReq_lat_1_whas__11_THEN_f22f3_enqR_ETC___d120 || - (!f22f3_deqReq_dummy2_2$Q_OUT || - !WILL_FIRE_RL_doFetch3 && !f22f3_deqReq_rl) && - f22f3_full ; - assign f32d_enqReq_dummy2_2_read__47_AND_IF_f32d_enqR_ETC___d673 = - f32d_enqReq_dummy2_2$Q_OUT && - IF_f32d_enqReq_lat_1_whas__43_THEN_f32d_enqReq_ETC___d452 || - (!f32d_deqReq_dummy2_2$Q_OUT || - !CAN_FIRE_RL_doDecode && !f32d_deqReq_rl) && - f32d_full ; - assign imm12__h123061 = { 4'd0, offset__h122904 } ; - assign imm12__h123402 = { 5'd0, offset__h123344 } ; - assign imm12__h125051 = { {6{imm6__h125049[5]}}, imm6__h125049 } ; - assign imm12__h125735 = { {2{nzimm10__h125733[9]}}, nzimm10__h125733 } ; - assign imm12__h125953 = { 2'd0, nzimm10__h125951 } ; - assign imm12__h126150 = { 6'b0, imm6__h125049 } ; - assign imm12__h126490 = { 6'b010000, imm6__h125049 } ; - assign imm12__h128127 = { 3'd0, offset__h128040 } ; - assign imm12__h128483 = { 4'd0, offset__h128417 } ; - assign imm12__h131615 = { 4'd0, offset__h131523 } ; - assign imm12__h131956 = { 5'd0, offset__h131898 } ; - assign imm12__h133602 = { {6{imm6__h133600[5]}}, imm6__h133600 } ; - assign imm12__h134286 = { {2{nzimm10__h134284[9]}}, nzimm10__h134284 } ; - assign imm12__h134504 = { 2'd0, nzimm10__h134502 } ; - assign imm12__h134701 = { 6'b0, imm6__h133600 } ; - assign imm12__h135041 = { 6'b010000, imm6__h133600 } ; - assign imm12__h136678 = { 3'd0, offset__h136591 } ; - assign imm12__h137034 = { 4'd0, offset__h136968 } ; - assign imm20__h125182 = { {14{imm6__h125049[5]}}, imm6__h125049 } ; - assign imm20__h133733 = { {14{imm6__h133600[5]}}, imm6__h133600 } ; - assign imm6__h125049 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:2] } ; - assign imm6__h133600 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:2] } ; - assign in_ppc__h143612 = - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719 ? - SEL_ARR_instdata_data_0_686_BITS_259_TO_196_99_ETC___d4994 : - in_ppc__h150788 ; - assign instr__h123060 = - { imm12__h123061, + assign inst__h150164 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + 32'd0 : + inst__h150160 ; + assign inst__h150506 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + n_inst__h150502 : + 32'd0 ; + assign inst__h150510 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + 32'd0 : + inst__h150506 ; + assign inst__h159849 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + n_inst__h118136 : + 32'd0 ; + assign inst__h159853 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + 32'd0 : + inst__h159849 ; + assign instr__h118639 = + { imm12__h118640, 8'd18, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 7'b0000011 } ; - assign instr__h123207 = + assign instr__h118786 = { 4'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[8:7], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[8:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:2], 8'd18, - offset_BITS_4_TO_0___h123333, + offset_BITS_4_TO_0___h118912, 7'b0100011 } ; - assign instr__h123401 = - { imm12__h123402, - rs1__h123403, + assign instr__h118980 = + { imm12__h118981, + rs1__h118982, 3'b010, - rd__h123404, + rd__h118983, 7'b0000011 } ; - assign instr__h123598 = + assign instr__h119177 = { 5'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12], - rd__h123404, - rs1__h123403, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12], + rd__h118983, + rs1__h118982, 3'b010, - offset_BITS_4_TO_0___h123768, + offset_BITS_4_TO_0___h119347, 7'b0100011 } ; - assign instr__h123829 = - { SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4410[20], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4410[10:1], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4410[11], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4410[19:12], + assign instr__h119408 = + { SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6397[20], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6397[10:1], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6397[11], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6397[19:12], 12'd111 } ; - assign instr__h124285 = + assign instr__h119864 = { 12'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 15'd103 } ; - assign instr__h124403 = + assign instr__h119982 = { 12'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 15'd231 } ; - assign instr__h124468 = - { SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4435[12], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4435[10:5], + assign instr__h120047 = + { SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6422[12], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6422[10:5], 5'd0, - rs1__h123403, + rs1__h118982, 3'b0, - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4435[4:1], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4435[11], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6422[4:1], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6422[11], 7'b1100011 } ; - assign instr__h124787 = - { SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4435[12], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4435[10:5], + assign instr__h120366 = + { SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6422[12], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6422[10:5], 5'd0, - rs1__h123403, + rs1__h118982, 3'b001, - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4435[4:1], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4435[11], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6422[4:1], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6422[11], 7'b1100011 } ; - assign instr__h125128 = - { imm12__h125051, + assign instr__h120707 = + { imm12__h120630, 8'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 7'b0010011 } ; - assign instr__h125317 = - { imm20__h125182, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + assign instr__h120896 = + { imm20__h120761, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 7'b0110111 } ; - assign instr__h125449 = - { imm12__h125051, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + assign instr__h121028 = + { imm12__h120630, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 3'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 7'b0010011 } ; - assign instr__h125680 = - { imm12__h125051, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + assign instr__h121259 = + { imm12__h120630, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 3'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 7'b0011011 } ; - assign instr__h125940 = - { imm12__h125735, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + assign instr__h121519 = + { imm12__h121314, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 3'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 7'b0010011 } ; - assign instr__h126113 = { imm12__h125953, 8'd16, rd__h123404, 7'b0010011 } ; - assign instr__h126284 = - { imm12__h126150, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + assign instr__h121692 = { imm12__h121532, 8'd16, rd__h118983, 7'b0010011 } ; + assign instr__h121863 = + { imm12__h121729, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 3'b001, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 7'b0010011 } ; - assign instr__h126474 = - { imm12__h126150, - rs1__h123403, + assign instr__h122053 = + { imm12__h121729, + rs1__h118982, 3'b101, - rs1__h123403, + rs1__h118982, 7'b0010011 } ; - assign instr__h126664 = - { imm12__h126490, - rs1__h123403, + assign instr__h122243 = + { imm12__h122069, + rs1__h118982, 3'b101, - rs1__h123403, + rs1__h118982, 7'b0010011 } ; - assign instr__h126782 = - { imm12__h125051, - rs1__h123403, + assign instr__h122361 = + { imm12__h120630, + rs1__h118982, 3'b111, - rs1__h123403, + rs1__h118982, 7'b0010011 } ; - assign instr__h126963 = + assign instr__h122542 = { 7'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:2], 8'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 7'b0110011 } ; - assign instr__h127084 = + assign instr__h122663 = { 7'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:2], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 3'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 7'b0110011 } ; - assign instr__h127180 = + assign instr__h122759 = { 7'b0, - rd__h123404, - rs1__h123403, + rd__h118983, + rs1__h118982, 3'b111, - rs1__h123403, + rs1__h118982, 7'b0110011 } ; - assign instr__h127317 = + assign instr__h122896 = { 7'b0, - rd__h123404, - rs1__h123403, + rd__h118983, + rs1__h118982, 3'b110, - rs1__h123403, + rs1__h118982, 7'b0110011 } ; - assign instr__h127454 = + assign instr__h123033 = { 7'b0, - rd__h123404, - rs1__h123403, + rd__h118983, + rs1__h118982, 3'b100, - rs1__h123403, + rs1__h118982, 7'b0110011 } ; - assign instr__h127591 = + assign instr__h123170 = { 7'b0100000, - rd__h123404, - rs1__h123403, + rd__h118983, + rs1__h118982, 3'b0, - rs1__h123403, + rs1__h118982, 7'b0110011 } ; - assign instr__h127730 = + assign instr__h123309 = { 7'b0, - rd__h123404, - rs1__h123403, + rd__h118983, + rs1__h118982, 3'b0, - rs1__h123403, + rs1__h118982, 7'b0111011 } ; - assign instr__h127869 = + assign instr__h123448 = { 7'b0100000, - rd__h123404, - rs1__h123403, + rd__h118983, + rs1__h118982, 3'b0, - rs1__h123403, + rs1__h118982, 7'b0111011 } ; - assign instr__h128029 = + assign instr__h123608 = { 12'b000000000001, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 3'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 7'b1110011 } ; - assign instr__h128126 = - { imm12__h128127, + assign instr__h123705 = + { imm12__h123706, 8'd19, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 7'b0000011 } ; - assign instr__h128281 = + assign instr__h123860 = { 3'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[9:7], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[9:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:2], 8'd19, - offset_BITS_4_TO_0___h128762, + offset_BITS_4_TO_0___h124341, 7'b0100011 } ; - assign instr__h128482 = - { imm12__h128483, - rs1__h123403, + assign instr__h124061 = + { imm12__h124062, + rs1__h118982, 3'b011, - rd__h123404, + rd__h118983, 7'b0000011 } ; - assign instr__h128635 = + assign instr__h124214 = { 4'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12], - rd__h123404, - rs1__h123403, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12], + rd__h118983, + rs1__h118982, 3'b011, - offset_BITS_4_TO_0___h128762, + offset_BITS_4_TO_0___h124341, 7'b0100011 } ; - assign instr__h129736 = - { imm12__h128127, - 8'd19, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7], + assign instr__h124473 = + { imm12__h118640, + 8'd18, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], 7'b0000111 } ; - assign instr__h129891 = + assign instr__h125288 = + { imm12__h123706, + 8'd19, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7], + 7'b0000111 } ; + assign instr__h125464 = { 3'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[9:7], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[9:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:2], 8'd19, - offset_BITS_4_TO_0___h128762, + offset_BITS_4_TO_0___h124341, 7'b0100111 } ; - assign instr__h130092 = - { imm12__h128483, - rs1__h123403, + assign instr__h125665 = + { imm12__h124062, + rs1__h118982, 3'b011, - rd__h123404, + rd__h118983, 7'b0000111 } ; - assign instr__h130245 = + assign instr__h125818 = { 4'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12], - rd__h123404, - rs1__h123403, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12], + rd__h118983, + rs1__h118982, 3'b011, - offset_BITS_4_TO_0___h128762, + offset_BITS_4_TO_0___h124341, 7'b0100111 } ; - assign instr__h131614 = - { imm12__h131615, + assign instr__h127439 = + { imm12__h127440, 8'd18, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 7'b0000011 } ; - assign instr__h131761 = + assign instr__h127586 = { 4'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[8:7], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[8:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:2], 8'd18, - offset_BITS_4_TO_0___h131887, + offset_BITS_4_TO_0___h127712, 7'b0100011 } ; - assign instr__h131955 = - { imm12__h131956, - rs1__h131957, + assign instr__h127780 = + { imm12__h127781, + rs1__h127782, 3'b010, - rd__h131958, + rd__h127783, 7'b0000011 } ; - assign instr__h132152 = + assign instr__h127977 = { 5'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12], - rd__h131958, - rs1__h131957, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12], + rd__h127783, + rs1__h127782, 3'b010, - offset_BITS_4_TO_0___h132322, + offset_BITS_4_TO_0___h128147, 7'b0100011 } ; - assign instr__h132382 = - { SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4117[20], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4117[10:1], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4117[11], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4117[19:12], + assign instr__h128207 = + { SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5497[20], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5497[10:1], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5497[11], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5497[19:12], 12'd111 } ; - assign instr__h132836 = + assign instr__h128661 = { 12'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 15'd103 } ; - assign instr__h132954 = + assign instr__h128779 = { 12'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 15'd231 } ; - assign instr__h133019 = - { SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4142[12], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4142[10:5], + assign instr__h128844 = + { SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5522[12], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5522[10:5], 5'd0, - rs1__h131957, + rs1__h127782, 3'b0, - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4142[4:1], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4142[11], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5522[4:1], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5522[11], 7'b1100011 } ; - assign instr__h133338 = - { SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4142[12], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4142[10:5], + assign instr__h129163 = + { SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5522[12], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5522[10:5], 5'd0, - rs1__h131957, + rs1__h127782, 3'b001, - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4142[4:1], - SEXT_SEL_ARR_IF_rg_pending_straddle_514_THEN_I_ETC___d4142[11], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5522[4:1], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5522[11], 7'b1100011 } ; - assign instr__h133679 = - { imm12__h133602, + assign instr__h129504 = + { imm12__h129427, 8'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 7'b0010011 } ; - assign instr__h133868 = - { imm20__h133733, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + assign instr__h129693 = + { imm20__h129558, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 7'b0110111 } ; - assign instr__h134000 = - { imm12__h133602, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + assign instr__h129825 = + { imm12__h129427, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 3'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 7'b0010011 } ; - assign instr__h134231 = - { imm12__h133602, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + assign instr__h130056 = + { imm12__h129427, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 3'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 7'b0011011 } ; - assign instr__h134491 = - { imm12__h134286, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + assign instr__h130316 = + { imm12__h130111, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 3'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 7'b0010011 } ; - assign instr__h134664 = { imm12__h134504, 8'd16, rd__h131958, 7'b0010011 } ; - assign instr__h134835 = - { imm12__h134701, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + assign instr__h130489 = { imm12__h130329, 8'd16, rd__h127783, 7'b0010011 } ; + assign instr__h130660 = + { imm12__h130526, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 3'b001, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 7'b0010011 } ; - assign instr__h135025 = - { imm12__h134701, - rs1__h131957, + assign instr__h130850 = + { imm12__h130526, + rs1__h127782, 3'b101, - rs1__h131957, + rs1__h127782, 7'b0010011 } ; - assign instr__h135215 = - { imm12__h135041, - rs1__h131957, + assign instr__h131040 = + { imm12__h130866, + rs1__h127782, 3'b101, - rs1__h131957, + rs1__h127782, 7'b0010011 } ; - assign instr__h135333 = - { imm12__h133602, - rs1__h131957, + assign instr__h131158 = + { imm12__h129427, + rs1__h127782, 3'b111, - rs1__h131957, + rs1__h127782, 7'b0010011 } ; - assign instr__h135514 = + assign instr__h131339 = { 7'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:2], 8'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 7'b0110011 } ; - assign instr__h135635 = + assign instr__h131460 = { 7'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:2], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 3'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 7'b0110011 } ; - assign instr__h135731 = + assign instr__h131556 = { 7'b0, - rd__h131958, - rs1__h131957, + rd__h127783, + rs1__h127782, 3'b111, - rs1__h131957, + rs1__h127782, 7'b0110011 } ; - assign instr__h135868 = + assign instr__h131693 = { 7'b0, - rd__h131958, - rs1__h131957, + rd__h127783, + rs1__h127782, 3'b110, - rs1__h131957, + rs1__h127782, 7'b0110011 } ; - assign instr__h136005 = + assign instr__h131830 = { 7'b0, - rd__h131958, - rs1__h131957, + rd__h127783, + rs1__h127782, 3'b100, - rs1__h131957, + rs1__h127782, 7'b0110011 } ; - assign instr__h136142 = + assign instr__h131967 = { 7'b0100000, - rd__h131958, - rs1__h131957, + rd__h127783, + rs1__h127782, 3'b0, - rs1__h131957, + rs1__h127782, 7'b0110011 } ; - assign instr__h136281 = + assign instr__h132106 = { 7'b0, - rd__h131958, - rs1__h131957, + rd__h127783, + rs1__h127782, 3'b0, - rs1__h131957, + rs1__h127782, 7'b0111011 } ; - assign instr__h136420 = + assign instr__h132245 = { 7'b0100000, - rd__h131958, - rs1__h131957, + rd__h127783, + rs1__h127782, 3'b0, - rs1__h131957, + rs1__h127782, 7'b0111011 } ; - assign instr__h136580 = + assign instr__h132405 = { 12'b000000000001, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 3'b0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 7'b1110011 } ; - assign instr__h136677 = - { imm12__h136678, + assign instr__h132502 = + { imm12__h132503, 8'd19, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 7'b0000011 } ; - assign instr__h136832 = + assign instr__h132657 = { 3'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[9:7], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[9:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:2], 8'd19, - offset_BITS_4_TO_0___h137313, + offset_BITS_4_TO_0___h133138, 7'b0100011 } ; - assign instr__h137033 = - { imm12__h137034, - rs1__h131957, + assign instr__h132858 = + { imm12__h132859, + rs1__h127782, 3'b011, - rd__h131958, + rd__h127783, 7'b0000011 } ; - assign instr__h137186 = + assign instr__h133011 = { 4'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12], - rd__h131958, - rs1__h131957, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12], + rd__h127783, + rs1__h127782, 3'b011, - offset_BITS_4_TO_0___h137313, + offset_BITS_4_TO_0___h133138, 7'b0100011 } ; - assign instr__h138231 = - { imm12__h136678, - 8'd19, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7], + assign instr__h133215 = + { imm12__h127440, + 8'd18, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], 7'b0000111 } ; - assign instr__h138386 = + assign instr__h134029 = + { imm12__h132503, + 8'd19, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7], + 7'b0000111 } ; + assign instr__h134205 = { 3'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[9:7], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[9:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:2], 8'd19, - offset_BITS_4_TO_0___h137313, + offset_BITS_4_TO_0___h133138, 7'b0100111 } ; - assign instr__h138587 = - { imm12__h137034, - rs1__h131957, + assign instr__h134406 = + { imm12__h132859, + rs1__h127782, 3'b011, - rd__h131958, + rd__h127783, 7'b0000111 } ; - assign instr__h138740 = + assign instr__h134559 = { 4'd0, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12], - rd__h131958, - rs1__h131957, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12], + rd__h127783, + rs1__h127782, 3'b011, - offset_BITS_4_TO_0___h137313, + offset_BITS_4_TO_0___h133138, 7'b0100111 } ; - assign j__h119769 = (pc_start__h119765[1:0] == 2'b0) ? 3'd0 : 3'd1 ; - assign j__h122111 = j__h119769 + 3'd2 ; - assign n__read__h142595 = - instdata_deqP_dummy2_0$Q_OUT && instdata_deqP_dummy2_1$Q_OUT && - instdata_deqP_rl ; - assign n_x16s__h117514 = { x__h119846, 1'd0 } ; - assign n_x16s__h119766 = - rg_pending_straddle ? - y_avValue_snd_fst__h119828 : - n_x16s__h117514 ; - assign next_PC__h143443 = x__h143344 + 64'd4 ; - assign next_PC__h150615 = - SEL_ARR_instdata_data_0_686_BITS_259_TO_196_99_ETC___d4994 + - 64'd4 ; - assign next_deqP___1__h19579 = + assign instr__h136193 = + { imm12__h136194, + 8'd18, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 7'b0000011 } ; + assign instr__h136340 = + { 4'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[8:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:2], + 8'd18, + offset_BITS_4_TO_0___h136466, + 7'b0100011 } ; + assign instr__h136534 = + { imm12__h136535, + rs1__h136536, + 3'b010, + rd__h136537, + 7'b0000011 } ; + assign instr__h136731 = + { 5'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12], + rd__h136537, + rs1__h136536, + 3'b010, + offset_BITS_4_TO_0___h136901, + 7'b0100011 } ; + assign instr__h136961 = + { SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5786[20], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5786[10:1], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5786[11], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5786[19:12], + 12'd111 } ; + assign instr__h137415 = + { 12'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 15'd103 } ; + assign instr__h137533 = + { 12'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 15'd231 } ; + assign instr__h137598 = + { SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5811[12], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5811[10:5], + 5'd0, + rs1__h136536, + 3'b0, + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5811[4:1], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5811[11], + 7'b1100011 } ; + assign instr__h137917 = + { SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5811[12], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5811[10:5], + 5'd0, + rs1__h136536, + 3'b001, + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5811[4:1], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d5811[11], + 7'b1100011 } ; + assign instr__h138258 = + { imm12__h138181, + 8'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 7'b0010011 } ; + assign instr__h138447 = + { imm20__h138312, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 7'b0110111 } ; + assign instr__h138579 = + { imm12__h138181, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 3'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 7'b0010011 } ; + assign instr__h138810 = + { imm12__h138181, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 3'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 7'b0011011 } ; + assign instr__h139070 = + { imm12__h138865, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 3'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 7'b0010011 } ; + assign instr__h139243 = { imm12__h139083, 8'd16, rd__h136537, 7'b0010011 } ; + assign instr__h139414 = + { imm12__h139280, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 3'b001, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 7'b0010011 } ; + assign instr__h139604 = + { imm12__h139280, + rs1__h136536, + 3'b101, + rs1__h136536, + 7'b0010011 } ; + assign instr__h139794 = + { imm12__h139620, + rs1__h136536, + 3'b101, + rs1__h136536, + 7'b0010011 } ; + assign instr__h139912 = + { imm12__h138181, + rs1__h136536, + 3'b111, + rs1__h136536, + 7'b0010011 } ; + assign instr__h140093 = + { 7'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:2], + 8'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 7'b0110011 } ; + assign instr__h140214 = + { 7'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 3'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 7'b0110011 } ; + assign instr__h140310 = + { 7'b0, + rd__h136537, + rs1__h136536, + 3'b111, + rs1__h136536, + 7'b0110011 } ; + assign instr__h140447 = + { 7'b0, + rd__h136537, + rs1__h136536, + 3'b110, + rs1__h136536, + 7'b0110011 } ; + assign instr__h140584 = + { 7'b0, + rd__h136537, + rs1__h136536, + 3'b100, + rs1__h136536, + 7'b0110011 } ; + assign instr__h140721 = + { 7'b0100000, + rd__h136537, + rs1__h136536, + 3'b0, + rs1__h136536, + 7'b0110011 } ; + assign instr__h140860 = + { 7'b0, + rd__h136537, + rs1__h136536, + 3'b0, + rs1__h136536, + 7'b0111011 } ; + assign instr__h140999 = + { 7'b0100000, + rd__h136537, + rs1__h136536, + 3'b0, + rs1__h136536, + 7'b0111011 } ; + assign instr__h141159 = + { 12'b000000000001, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 3'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 7'b1110011 } ; + assign instr__h141256 = + { imm12__h141257, + 8'd19, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 7'b0000011 } ; + assign instr__h141411 = + { 3'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[9:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:2], + 8'd19, + offset_BITS_4_TO_0___h141892, + 7'b0100011 } ; + assign instr__h141612 = + { imm12__h141613, + rs1__h136536, + 3'b011, + rd__h136537, + 7'b0000011 } ; + assign instr__h141765 = + { 4'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12], + rd__h136537, + rs1__h136536, + 3'b011, + offset_BITS_4_TO_0___h141892, + 7'b0100011 } ; + assign instr__h141969 = + { imm12__h136194, + 8'd18, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 7'b0000111 } ; + assign instr__h142783 = + { imm12__h141257, + 8'd19, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7], + 7'b0000111 } ; + assign instr__h142959 = + { 3'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[9:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:2], + 8'd19, + offset_BITS_4_TO_0___h141892, + 7'b0100111 } ; + assign instr__h143160 = + { imm12__h141613, + rs1__h136536, + 3'b011, + rd__h136537, + 7'b0000111 } ; + assign instr__h143313 = + { 4'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12], + rd__h136537, + rs1__h136536, + 3'b011, + offset_BITS_4_TO_0___h141892, + 7'b0100111 } ; + assign instr__h152465 = + { imm12__h152466, + 8'd18, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 7'b0000011 } ; + assign instr__h152612 = + { 4'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[8:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:2], + 8'd18, + offset_BITS_4_TO_0___h152738, + 7'b0100011 } ; + assign instr__h152806 = + { imm12__h152807, + rs1__h152808, + 3'b010, + rd__h152809, + 7'b0000011 } ; + assign instr__h153003 = + { 5'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12], + rd__h152809, + rs1__h152808, + 3'b010, + offset_BITS_4_TO_0___h153173, + 7'b0100011 } ; + assign instr__h153233 = + { SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6075[20], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6075[10:1], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6075[11], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6075[19:12], + 12'd111 } ; + assign instr__h153687 = + { 12'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 15'd103 } ; + assign instr__h153805 = + { 12'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 15'd231 } ; + assign instr__h153870 = + { SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6100[12], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6100[10:5], + 5'd0, + rs1__h152808, + 3'b0, + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6100[4:1], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6100[11], + 7'b1100011 } ; + assign instr__h154189 = + { SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6100[12], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6100[10:5], + 5'd0, + rs1__h152808, + 3'b001, + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6100[4:1], + SEXT_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_ETC___d6100[11], + 7'b1100011 } ; + assign instr__h154530 = + { imm12__h154453, + 8'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 7'b0010011 } ; + assign instr__h154719 = + { imm20__h154584, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 7'b0110111 } ; + assign instr__h154851 = + { imm12__h154453, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 3'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 7'b0010011 } ; + assign instr__h155082 = + { imm12__h154453, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 3'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 7'b0011011 } ; + assign instr__h155342 = + { imm12__h155137, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 3'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 7'b0010011 } ; + assign instr__h155515 = { imm12__h155355, 8'd16, rd__h152809, 7'b0010011 } ; + assign instr__h155686 = + { imm12__h155552, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 3'b001, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 7'b0010011 } ; + assign instr__h155876 = + { imm12__h155552, + rs1__h152808, + 3'b101, + rs1__h152808, + 7'b0010011 } ; + assign instr__h156066 = + { imm12__h155892, + rs1__h152808, + 3'b101, + rs1__h152808, + 7'b0010011 } ; + assign instr__h156184 = + { imm12__h154453, + rs1__h152808, + 3'b111, + rs1__h152808, + 7'b0010011 } ; + assign instr__h156365 = + { 7'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:2], + 8'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 7'b0110011 } ; + assign instr__h156486 = + { 7'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 3'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 7'b0110011 } ; + assign instr__h156582 = + { 7'b0, + rd__h152809, + rs1__h152808, + 3'b111, + rs1__h152808, + 7'b0110011 } ; + assign instr__h156719 = + { 7'b0, + rd__h152809, + rs1__h152808, + 3'b110, + rs1__h152808, + 7'b0110011 } ; + assign instr__h156856 = + { 7'b0, + rd__h152809, + rs1__h152808, + 3'b100, + rs1__h152808, + 7'b0110011 } ; + assign instr__h156993 = + { 7'b0100000, + rd__h152809, + rs1__h152808, + 3'b0, + rs1__h152808, + 7'b0110011 } ; + assign instr__h157132 = + { 7'b0, + rd__h152809, + rs1__h152808, + 3'b0, + rs1__h152808, + 7'b0111011 } ; + assign instr__h157271 = + { 7'b0100000, + rd__h152809, + rs1__h152808, + 3'b0, + rs1__h152808, + 7'b0111011 } ; + assign instr__h157431 = + { 12'b000000000001, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 3'b0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 7'b1110011 } ; + assign instr__h157528 = + { imm12__h157529, + 8'd19, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 7'b0000011 } ; + assign instr__h157683 = + { 3'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[9:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:2], + 8'd19, + offset_BITS_4_TO_0___h158164, + 7'b0100011 } ; + assign instr__h157884 = + { imm12__h157885, + rs1__h152808, + 3'b011, + rd__h152809, + 7'b0000011 } ; + assign instr__h158037 = + { 4'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12], + rd__h152809, + rs1__h152808, + 3'b011, + offset_BITS_4_TO_0___h158164, + 7'b0100011 } ; + assign instr__h158241 = + { imm12__h152466, + 8'd18, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 7'b0000111 } ; + assign instr__h159055 = + { imm12__h157529, + 8'd19, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7], + 7'b0000111 } ; + assign instr__h159231 = + { 3'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[9:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:2], + 8'd19, + offset_BITS_4_TO_0___h158164, + 7'b0100111 } ; + assign instr__h159432 = + { imm12__h157885, + rs1__h152808, + 3'b011, + rd__h152809, + 7'b0000111 } ; + assign instr__h159585 = + { 4'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12], + rd__h152809, + rs1__h152808, + 3'b011, + offset_BITS_4_TO_0___h158164, + 7'b0100111 } ; + assign j__h114680 = + (pc_start__h114675[1:0] == 2'b0 || + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988) ? + 3'd0 : + 3'd1 ; + assign j__h117346 = j__h114680 + 3'd2 ; + assign j__h126282 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5243 + + 3'd2 ; + assign j__h134993 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5254 + + 3'd2 ; + assign last_x16_pc__h177080 = { x__h171664[128:64], address__h193365 } ; + assign last_x16_pc__h187660 = + { SEL_ARR_instdata_data_0_987_BITS_389_TO_261_42_ETC___d7425[128:64], + address__h193189 } ; + assign n__read__h165419 = + CAN_FIRE_RL_doDecode ? upd__h165446 : instdata_deqP_rl ; + assign n_inst__h118136 = + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196 ? + y_avValue_snd_snd_fst__h117562 : + 32'd0 ; + assign n_inst__h127069 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 ? + y_avValue_snd_snd_fst__h126498 : + 32'd0 ; + assign n_inst__h135823 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 ? + y_avValue_snd_snd_fst__h135209 : + 32'd0 ; + assign n_inst__h150502 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5266 ? + y_avValue_snd_snd_fst__h143783 : + 32'd0 ; + assign n_items__h145984 = + { 1'd0, pending_n_items__h113790 } + + (NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + 3'd0 : + y_avValue_snd_snd_fst__h146015) ; + assign n_orig_inst__h118135 = + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5196 ? + y_avValue_snd_snd_snd_fst__h117567 : + 32'd0 ; + assign n_orig_inst__h127068 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5244 ? + y_avValue_snd_snd_snd_fst__h126503 : + 32'd0 ; + assign n_orig_inst__h135822 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5255 ? + y_avValue_snd_snd_snd_fst__h135214 : + 32'd0 ; + assign n_orig_inst__h150501 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5266 ? + y_avValue_snd_snd_snd_fst__h143788 : + 32'd0 ; + assign n_x16s__h114667 = { x__h114796, 1'd0 } ; + assign n_x16s__h114677 = + (n_x16s__h114667 <= + _0_CONCAT_SEL_ARR_f22f3_data_0_920_BITS_337_TO__ETC___d5193) ? + n_x16s__h114667 : + _0_CONCAT_SEL_ARR_f22f3_data_0_920_BITS_337_TO__ETC___d5193 ; + assign nextPc__h193173 = { x__h171664[128:64], address__h193564 } ; + assign next_deqP___1__h15012 = (f22f3_deqP == 2'd3) ? 2'd0 : f22f3_deqP + 2'd1 ; - assign next_deqP___1__h29225 = f32d_deqP + 1'd1 ; - assign next_deqP___1__h8312 = f12f2_deqP + 1'd1 ; - assign next_deqP__h142575 = - !instdata_deqP_dummy2_0$Q_OUT || !instdata_deqP_dummy2_1$Q_OUT || - !instdata_deqP_rl ; - assign next_enqP__h139674 = - !instdata_enqP_dummy2_0$Q_OUT || !instdata_enqP_dummy2_1$Q_OUT || - !instdata_enqP_rl ; - assign next_pc___1__h122112 = pc_start__h119765 + 64'd4 ; - assign next_pc___1__h122117 = pc_start__h119765 + 64'd2 ; - assign nzimm10__h125733 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[4:3], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[2], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6], + assign next_deqP___1__h20711 = f32d_deqP + 1'd1 ; + assign next_deqP___1__h6794 = f12f2_deqP + 1'd1 ; + assign next_deqP__h170905 = instdata_deqP_rl + 1'd1 ; + assign next_enqP__h165312 = instdata_enqP_rl + 1'd1 ; + assign next_pc___1__h117347 = pc_start__h114675[63:0] + 64'd4 ; + assign next_pc___1__h126283 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5333 + + 64'd4 ; + assign next_pc___1__h134994 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5342 + + 64'd4 ; + assign next_pc___1__h146036 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5351 + + 64'd4 ; + assign nzimm10__h121312 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[4:3], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6], 4'b0 } ; - assign nzimm10__h125951 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[10:7], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12:11], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6], + assign nzimm10__h121530 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[10:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12:11], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6], 2'b0 } ; - assign nzimm10__h134284 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[4:3], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[2], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6], + assign nzimm10__h130109 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[4:3], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6], 4'b0 } ; - assign nzimm10__h134502 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[10:7], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12:11], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6], + assign nzimm10__h130327 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[10:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12:11], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6], 2'b0 } ; - assign offset_BITS_4_TO_0___h123333 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:9], + assign nzimm10__h138863 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[4:3], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6], + 4'b0 } ; + assign nzimm10__h139081 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[10:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12:11], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6], 2'b0 } ; - assign offset_BITS_4_TO_0___h123768 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:10], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6], + assign nzimm10__h155135 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[4:3], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6], + 4'b0 } ; + assign nzimm10__h155353 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[10:7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12:11], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6], 2'b0 } ; - assign offset_BITS_4_TO_0___h128762 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:10], + assign offset_BITS_4_TO_0___h118912 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:9], + 2'b0 } ; + assign offset_BITS_4_TO_0___h119347 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:10], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6], + 2'b0 } ; + assign offset_BITS_4_TO_0___h124341 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:10], 3'b0 } ; - assign offset_BITS_4_TO_0___h131887 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:9], + assign offset_BITS_4_TO_0___h127712 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:9], 2'b0 } ; - assign offset_BITS_4_TO_0___h132322 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:10], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6], + assign offset_BITS_4_TO_0___h128147 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:10], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6], 2'b0 } ; - assign offset_BITS_4_TO_0___h137313 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:10], + assign offset_BITS_4_TO_0___h133138 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:10], 3'b0 } ; - assign offset__h122904 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[3:2], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:4], + assign offset_BITS_4_TO_0___h136466 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:9], 2'b0 } ; - assign offset__h123344 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12:10], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6], + assign offset_BITS_4_TO_0___h136901 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:10], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6], 2'b0 } ; - assign offset__h123776 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[8], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[10:9], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[7], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[2], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[5:3], + assign offset_BITS_4_TO_0___h141892 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:10], + 3'b0 } ; + assign offset_BITS_4_TO_0___h152738 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:9], + 2'b0 } ; + assign offset_BITS_4_TO_0___h153173 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:10], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6], + 2'b0 } ; + assign offset_BITS_4_TO_0___h158164 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:10], + 3'b0 } ; + assign offset__h118483 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[3:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:4], + 2'b0 } ; + assign offset__h118923 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12:10], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6], + 2'b0 } ; + assign offset__h119355 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[8], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[10:9], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[5:3], 1'b0 } ; - assign offset__h124412 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[2], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:10], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[4:3], + assign offset__h119991 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:10], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[4:3], 1'b0 } ; - assign offset__h128040 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[4:2], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:5], + assign offset__h123619 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[4:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:5], 3'b0 } ; - assign offset__h128417 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[6:5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[12:10], + assign offset__h123996 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[12:10], 3'b0 } ; - assign offset__h131523 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[3:2], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:4], + assign offset__h127348 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[3:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:4], 2'b0 } ; - assign offset__h131898 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12:10], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6], + assign offset__h127723 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12:10], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6], 2'b0 } ; - assign offset__h132330 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[8], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[10:9], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[7], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[2], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[5:3], + assign offset__h128155 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[8], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[10:9], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[5:3], 1'b0 } ; - assign offset__h132963 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[2], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:10], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[4:3], + assign offset__h128788 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:10], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[4:3], 1'b0 } ; - assign offset__h136591 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[4:2], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:5], + assign offset__h132416 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[4:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:5], 3'b0 } ; - assign offset__h136968 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[6:5], - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[12:10], + assign offset__h132793 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[12:10], 3'b0 } ; - assign orig_inst___1__h122110 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4344, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028 } ; - assign orig_inst___1__h131399 = - { SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4051, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044 } ; - assign pc_start__h119765 = - rg_pending_straddle ? - y_avValue_snd_snd__h119829 : - start_PC__h117515 ; - assign perfReqQ_enqReq_dummy2_2_read__027_AND_IF_perf_ETC___d3039 = - perfReqQ_enqReq_dummy2_2$Q_OUT && - IF_perfReqQ_enqReq_lat_1_whas__977_THEN_perfRe_ETC___d2986 || - (!perfReqQ_deqReq_dummy2_2$Q_OUT || - !EN_perf_resp && !perfReqQ_deqReq_rl) && - perfReqQ_full ; - assign pred_next_pc__h114157 = - (SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 && - x__h115849[63:10] == nextAddrPred_tags$D_OUT_3) ? - nextAddrPred_next_addrs$D_OUT_2 : - IF_pc_reg_dummy2_0_read__063_AND_pc_reg_dummy2_ETC___d3337 ; - assign pred_next_pc__h114166 = - x__h115826 ? pred_next_pc__h115374 : pred_next_pc__h114157 ; - assign pred_next_pc__h115374 = - (SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 && - pred_next_pc__h114157[63:10] == nextAddrPred_tags$D_OUT_2) ? - nextAddrPred_next_addrs$D_OUT_1 : - pred_next_pc__h114157 + 64'd4 ; - assign rd__h123404 = + assign offset__h136102 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[3:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:4], + 2'b0 } ; + assign offset__h136477 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12:10], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6], + 2'b0 } ; + assign offset__h136909 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[8], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[10:9], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[5:3], + 1'b0 } ; + assign offset__h137542 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:10], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[4:3], + 1'b0 } ; + assign offset__h141170 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[4:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:5], + 3'b0 } ; + assign offset__h141547 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[12:10], + 3'b0 } ; + assign offset__h152374 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[3:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:4], + 2'b0 } ; + assign offset__h152749 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12:10], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6], + 2'b0 } ; + assign offset__h153181 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[8], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[10:9], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[7], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[5:3], + 1'b0 } ; + assign offset__h153814 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:10], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[4:3], + 1'b0 } ; + assign offset__h157442 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[4:2], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:5], + 3'b0 } ; + assign offset__h157819 = + { SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[6:5], + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[12:10], + 3'b0 } ; + assign orig_inst___1__h117345 = + { CASE_y_avValue_fst17191_0_IF_NOT_f22f3_empty_1_ETC__q372, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234 } ; + assign orig_inst___1__h126281 = + { CASE_y_avValue_fst26140_0_IF_NOT_f22f3_empty_1_ETC__q373, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245 } ; + assign orig_inst___1__h134992 = + { CASE_y_avValue_fst34851_0_IF_NOT_f22f3_empty_1_ETC__q374, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256 } ; + assign orig_inst___1__h146034 = + { CASE_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_ETC__q375, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267 } ; + assign orig_inst__h149817 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + n_orig_inst__h127068 : + 32'd0 ; + assign orig_inst__h149821 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + 32'd0 : + orig_inst__h149817 ; + assign orig_inst__h150159 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + n_orig_inst__h135822 : + 32'd0 ; + assign orig_inst__h150163 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + 32'd0 : + orig_inst__h150159 ; + assign orig_inst__h150505 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + n_orig_inst__h150501 : + 32'd0 ; + assign orig_inst__h150509 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + 32'd0 : + orig_inst__h150505 ; + assign orig_inst__h159848 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + n_orig_inst__h118135 : + 32'd0 ; + assign orig_inst__h159852 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + 32'd0 : + orig_inst__h159848 ; + assign out_tval__h112353 = + iTlb$to_proc_response_get[5] ? + tval__h112495 : + y_avValue_snd_fst__h113417 ; + assign pc__h149815 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + value__h127057 : + pc_start__h114675 ; + assign pc__h149819 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + pc_start__h114675 : + pc__h149815 ; + assign pc__h150157 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + value__h135811 : + pc_start__h114675 ; + assign pc__h150161 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + pc_start__h114675 : + pc__h150157 ; + assign pc__h150503 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + a__h144061 : + pc_start__h114675 ; + assign pc__h150507 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + pc_start__h114675 : + pc__h150503 ; + assign pc__h159846 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + value__h118124 : + pc_start__h114675 ; + assign pc__h159850 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + pc_start__h114675 : + pc__h159846 ; + assign pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NOT_I_ETC___d4733 = + pc_reg_rl[1:0] == 2'b0 && + (cap__h110263[5:2] != 4'd15 || cap__h110263[1:0] == 2'b0) && + IF_NOT_IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15__ETC___d4732 ; + assign pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NOT_I_ETC___d4749 = + pc_reg_rl[1:0] == 2'b0 && + (cap__h110263[5:2] != 4'd15 || cap__h110263[1:0] == 2'b0) && + (!SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 || + !IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4729) ; + assign pc_reg_rl_BITS_63_TO_0_689_PLUS_2_690_BITS_63__ETC___d4704 = + address__h109631[63:9] == nextAddrPred_tags$D_OUT_4 ; + assign pc_reg_rl_BITS_63_TO_9_682_EQ_nextAddrPred_tag_ETC___d4684 = + pc_reg_rl[63:9] == nextAddrPred_tags$D_OUT_5 ; + assign pending_n_items__h113790 = + (rg_pending_n_items == 2'd0) ? + rg_pending_n_items : + y_avValue_snd__h113781 ; + assign pending_spaces__h145986 = 2'd3 - pending_n_items__h113790 ; + assign pending_spaces_ext__h145988 = { 1'd0, pending_spaces__h145986 } ; + assign pred_next_pc__h143735 = + IF_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_3_ETC___d6674 ? + def__h161167 : + SEL_ARR_f22f3_data_0_920_BITS_205_TO_77_682_f2_ETC___d6687 ; + assign prev_PC__h109626 = { pc_reg_rl[128:64], address__h109631 } ; + assign prev_PC__h110311 = { cap__h109578[128:64], address__h110316 } ; + assign rd__h118983 = { 2'b01, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[4:2] } ; - assign rd__h131958 = + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[4:2] } ; + assign rd__h127783 = { 2'b01, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[4:2] } ; - assign rg_pending_straddle_514_AND_NOT_SEL_ARR_f22f3__ETC___d3728 = - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 && - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 ; - assign rg_pending_straddle_514_AND_NOT_SEL_ARR_f22f3__ETC___d3833 = - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 && - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3827 ; - assign rs1__h123403 = + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[4:2] } ; + assign rd__h136537 = { 2'b01, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[9:7] } ; - assign rs1__h131957 = + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[4:2] } ; + assign rd__h152809 = { 2'b01, - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[9:7] } ; - assign tval__h116722 = { x__h116419[63:2], 2'd0 } ; - assign upd__h139977 = next_deqP__h142575 ; - assign upd__h1659 = - (SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 == - 2'd3 && - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719) ? - (SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d5165 ? - next_PC__h150615 : - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5451) : - IF_NOT_SEL_ARR_instdata_data_0_686_BITS_195_TO_ETC___d5456 ; - assign upd__h1686 = EN_start ? start_pc : pred_next_pc__h114166 ; - assign upd__h32146 = next_enqP__h139674 ; - assign upd__h38127 = x__h54856 ; - assign upd__h38154 = x__h54856 + 1'd1 ; - assign upd__h39683 = x__h63120 ; - assign upd__h39710 = x__h63120 + 1'd1 ; - assign v__h15956 = - (f22f3_enqReq_dummy2_2$Q_OUT && - IF_f22f3_enqReq_lat_1_whas__11_THEN_f22f3_enqR_ETC___d120) ? - v__h16239 : + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[4:2] } ; + assign rg_pending_f32d_953_BITS_3_TO_0_954_EQ_f_main__ETC___d4955 = + rg_pending_f32d[3:0] == f_main_epoch ; + assign rg_pending_f32d_953_BIT_4_957_EQ_IF_decode_epo_ETC___d4958 = + rg_pending_f32d[4] == + IF_decode_epoch_lat_0_whas__6_THEN_decode_epoc_ETC___d19 ; + assign rs1__h118982 = + { 2'b01, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[9:7] } ; + assign rs1__h127782 = + { 2'b01, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[9:7] } ; + assign rs1__h136536 = + { 2'b01, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[9:7] } ; + assign rs1__h152808 = + { 2'b01, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[9:7] } ; + assign train_nextPc__h194872 = + napTrainByExe$whas ? + napTrainByExe$wget[128:0] : + napTrainByDecQ_data_0[128:0] ; + assign tval__h112495 = { out_pc__h112351[63:1], 1'd0 } ; + assign upd__h1026 = EN_start ? start_pc : MUX_pc_reg_lat_0$wset_1__VAL_2 ; + assign upd__h165446 = next_deqP__h170905 ; + assign upd__h21945 = next_enqP__h165312 ; + assign upd__h24504 = out_fifo_enqueueFifo_rl + 1'd1 ; + assign upd__h25105 = out_fifo_dequeueFifo_rl + 1'd1 ; + assign upd__h972 = { cap__h145069[128:64], address__h145071 } ; + assign upd__h999 = + (SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 != + 2'd0 && + SEL_ARR_f32d_data_0_979_BIT_334_011_f32d_data__ETC___d7014) ? + (SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d7552 ? + IF_SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033__ETC___d7980 : + decode_pred_next_pc__h177047) : + decode_pred_next_pc__h177047 ; + assign v__h10967 = + IF_f22f3_enqReq_lat_1_whas__77_THEN_f22f3_enqR_ETC___d186 ? + v__h11118 : f22f3_enqP ; - assign v__h16239 = (f22f3_enqP == 2'd3) ? 2'd0 : f22f3_enqP + 2'd1 ; - assign v__h27080 = - (f32d_enqReq_dummy2_2$Q_OUT && - IF_f32d_enqReq_lat_1_whas__43_THEN_f32d_enqReq_ETC___d452) ? - v__h27363 : + assign v__h11118 = (f22f3_enqP == 2'd3) ? 2'd0 : f22f3_enqP + 2'd1 ; + assign v__h18830 = + IF_f32d_enqReq_lat_1_whas__20_THEN_f32d_enqReq_ETC___d529 ? + v__h18981 : f32d_enqP ; - assign v__h27363 = f32d_enqP + 1'd1 ; - assign v__h7269 = - (f12f2_enqReq_dummy2_2$Q_OUT && - IF_f12f2_enqReq_lat_1_whas__4_THEN_f12f2_enqRe_ETC___d23) ? - v__h7552 : + assign v__h18981 = f32d_enqP + 1'd1 ; + assign v__h5669 = + IF_f12f2_enqReq_lat_1_whas__6_THEN_f12f2_enqRe_ETC___d55 ? + v__h5820 : f12f2_enqP ; - assign v__h7552 = f12f2_enqP + 1'd1 ; - assign value__h119455 = - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 ? - (SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491 ? - mmio$bootRomResp[31:0] : - iMem$to_proc_response_get[31:0]) : - 32'd0 ; - assign value__h119609 = - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 ? - (SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491 ? - mmio$bootRomResp[64:33] : - iMem$to_proc_response_get[64:33]) : - 32'd0 ; - assign x1_avValue_fst_ppc__h147284 = - (IF_decode_768_BITS_99_TO_95_772_EQ_8_779_AND_d_ETC___d4982 && - decode_pred_next_pc__h146966 != in_ppc__h143612) ? - decode_pred_next_pc__h146966 : - in_ppc__h143612 ; - assign x1_avValue_fst_ppc__h154042 = - (IF_decode_180_BITS_99_TO_95_184_EQ_8_191_AND_d_ETC___d5394 && - decode_pred_next_pc__h153837 != in_ppc__h150788) ? - decode_pred_next_pc__h153837 : - in_ppc__h150788 ; - assign x__h115826 = - x__h115849[5:2] != 4'd15 && - (x__h115849 + 64'd2 == pred_next_pc__h114157 || - IF_pc_reg_dummy2_0_read__063_AND_pc_reg_dummy2_ETC___d3337 == - pred_next_pc__h114157) ; - assign x__h115849 = - (pc_reg_dummy2_0$Q_OUT && pc_reg_dummy2_1$Q_OUT && - pc_reg_dummy2_2$Q_OUT) ? - pc_reg_rl : - 64'd0 ; - assign x__h116716 = iTlb$to_proc_response_get[4] ? tval__h116722 : 64'd0 ; - assign x__h119846 = x__h119862 + y__h119863 ; - assign x__h119862 = { 1'd0, b__h119870 } ; - assign x__h147295 = - (SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d4768[0]) ? - x1_avValue_fst_ppc__h147284 : - in_ppc__h143612 ; - assign x__h154053 = - (SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 && - !decode___d5180[0]) ? - x1_avValue_fst_ppc__h154042 : - in_ppc__h150788 ; - assign x__h160492 = + assign v__h5820 = f12f2_enqP + 1'd1 ; + assign value__h118124 = { pc_start__h114675[128:64], address__h118137 } ; + assign value__h127057 = + { pc_start__h114675[128:64], + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5333 } ; + assign value__h135811 = + { pc_start__h114675[128:64], + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5342 } ; + assign x11563_PLUS_1__q2 = x__h111563 + 12'd1 ; + assign x1_avValue_fst_main_epoch__h146089 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + y_avValue_fst_main_epoch__h146082 : + rg_pending_f32d[3:0] ; + assign x1_avValue_fst_pc__h146083 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + y_avValue_fst_pc__h146077 : + rg_pending_f32d[333:205] ; + assign x1_avValue_fst_ppc__h177356 = + (IF_decode_047_BITS_171_TO_167_051_EQ_8_057_AND_ETC___d7413 && + decode_pred_next_pc__h177047 != in_ppc__h171466) ? + decode_pred_next_pc__h177047 : + in_ppc__h171466 ; + assign x1_avValue_fst_ppc__h187823 = + (IF_decode_558_BITS_171_TO_167_562_EQ_8_568_AND_ETC___d7924 && + decode_pred_next_pc__h187627 != in_ppc__h182302) ? + decode_pred_next_pc__h187627 : + in_ppc__h182302 ; + assign x1_avValue_fst_pred_next_pc__h146084 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + pred_next_pc__h143735 : + rg_pending_f32d[204:76] ; + assign x1_avValue_fst_pred_next_pc__h146091 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[204:76] : + x1_avValue_fst_pred_next_pc__h146084 ; + assign x1_avValue_fst_tval__h146087 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + y_avValue_fst_tval__h146080 : + rg_pending_f32d[68:5] ; + assign x_BIT_109___h171706 = x__h171664[109] ; + assign x_BIT_109___h182531 = + SEL_ARR_instdata_data_0_987_BITS_389_TO_261_42_ETC___d7425[109] ; + assign x__h111368 = cap__h110263[63:0] + 64'd2 ; + assign x__h111563 = + (NOT_SEL_ARR_nextAddrPred_valid_0_read__422_nex_ETC___d4748 && + pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NOT_I_ETC___d4749) ? + 12'd3 : + (NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_OR_ETC___d4708 ? + 12'd2 : + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4751) ; + assign x__h111739 = x__h111757 + y__h111758 ; + assign x__h111757 = + (NOT_SEL_ARR_nextAddrPred_valid_0_read__422_nex_ETC___d4748 && + pc_reg_rl_BITS_1_TO_0_419_EQ_0b0_420_AND_NOT_I_ETC___d4749) ? + 2'd3 : + (NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_OR_ETC___d4708 ? + 2'd2 : + IF_NOT_pc_reg_rl_BITS_5_TO_2_416_EQ_15_417_418_ETC___d4772) ; + assign x__h11317 = + WILL_FIRE_RL_doFetch2 ? + f22f3_enqReq_lat_0$wget[337:336] : + f22f3_enqReq_rl[337:336] ; + assign x__h114796 = x__h114812 + y__h114813 ; + assign x__h114812 = { 1'd0, b__h114820 } ; + assign x__h163892 = n_items__h145984 - 3'd2 ; + assign x__h165551 = + !_0_CONCAT_IF_rg_pending_n_items_951_EQ_0_952_TH_ETC___d5375 || + x__h165559[0] ; + assign x__h165559 = n_items__h145984 - 3'd1 ; + assign x__h165562 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 ? + rg_pending_f32d[333:205] : + x1_avValue_fst_pc__h146083 ; + assign x__h165577 = + _0_CONCAT_IF_rg_pending_n_items_951_EQ_0_952_TH_ETC___d5375 ? + x1_avValue_fst_pred_next_pc__h146091 : + y_avValue_fst_pred_next_pc__h165564 ; + assign x__h177367 = + (SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7047[0]) ? + x1_avValue_fst_ppc__h177356 : + in_ppc__h171466 ; + assign x__h187834 = + (SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 && + !decode___d7558[0]) ? + x1_avValue_fst_ppc__h187823 : + in_ppc__h182302 ; + assign x__h19100 = + f32d_enqReq_lat_0$whas ? + f32d_enqReq_lat_0$wget[334] : + f32d_enqReq_rl[334] ; + assign x__h19157 = + f32d_enqReq_lat_0$whas ? + f32d_enqReq_lat_0$wget[333:205] : + f32d_enqReq_rl[333:205] ; + assign x__h19215 = + f32d_enqReq_lat_0$whas ? + f32d_enqReq_lat_0$wget[204:76] : + f32d_enqReq_rl[204:76] ; + assign x__h194838 = napTrainByExe$whas ? - napTrainByExe$wget[127:64] : - napTrainByDecQ_data_0[127:64] ; - assign x__h160545 = - napTrainByExe$whas ? - napTrainByExe$wget[63:0] : - napTrainByDecQ_data_0[63:0] ; - assign x__h16438 = + napTrainByExe$wget[257:129] : + napTrainByDecQ_data_0[257:129] ; + assign x__h225902 = { train_predictors_pc[128:64], address__h225906 } ; + assign x__h5939 = + WILL_FIRE_RL_doFetch1 ? + f12f2_enqReq_lat_0$wget[266:265] : + f12f2_enqReq_rl[266:265] ; + assign x__h60535 = upd__h24504 ; + assign x__h74473 = upd__h25105 ; + assign x_snd_pc__h11415 = WILL_FIRE_RL_doFetch2 ? - f22f3_enqReq_lat_0$wget[267] : - f22f3_enqReq_rl[267] ; - assign x__h16495 = - WILL_FIRE_RL_doFetch2 ? - f22f3_enqReq_lat_0$wget[266:203] : - f22f3_enqReq_rl[266:203] ; - assign x__h16558 = - WILL_FIRE_RL_doFetch2 ? - f22f3_enqReq_lat_0$wget[202:139] : - f22f3_enqReq_rl[202:139] ; - assign x__h16572 = - WILL_FIRE_RL_doFetch2 ? - f22f3_enqReq_lat_0$wget[138:75] : - f22f3_enqReq_rl[138:75] ; - assign x__h27482 = - f32d_enqReq_lat_0$whas ? - f32d_enqReq_lat_0$wget[267] : - f32d_enqReq_rl[267] ; - assign x__h27539 = - f32d_enqReq_lat_0$whas ? - f32d_enqReq_lat_0$wget[266:203] : - f32d_enqReq_rl[266:203] ; - assign x__h27602 = - f32d_enqReq_lat_0$whas ? - f32d_enqReq_lat_0$wget[202:139] : - f32d_enqReq_rl[202:139] ; - assign x__h27616 = - f32d_enqReq_lat_0$whas ? - f32d_enqReq_lat_0$wget[138:75] : - f32d_enqReq_rl[138:75] ; - assign x__h54856 = - out_fifo_enqueueFifo_dummy2_0$Q_OUT && - out_fifo_enqueueFifo_dummy2_1$Q_OUT && - out_fifo_enqueueFifo_dummy2_2$Q_OUT && - out_fifo_enqueueFifo_rl ; - assign x__h63120 = - out_fifo_dequeueFifo_dummy2_0$Q_OUT && - out_fifo_dequeueFifo_dummy2_1$Q_OUT && - out_fifo_dequeueFifo_dummy2_2$Q_OUT && - out_fifo_dequeueFifo_rl ; - assign x__h64600 = upd__h38154 ; - assign x__h72803 = upd__h39710 ; - assign y__h117541 = rg_half_inst_pc + 64'd4 ; - assign y__h119863 = { 1'd0, b__h119858 } ; - assign y__h160555 = x__h160492 + 64'd4 ; - assign y_avValue_fst__h122004 = j__h119769 + 3'd1 ; - assign y_avValue_fst__h122012 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == + f22f3_enqReq_lat_0$wget[335:207] : + f22f3_enqReq_rl[335:207] ; + assign x_snd_pc__h6025 = + WILL_FIRE_RL_doFetch1 ? + f12f2_enqReq_lat_0$wget[264:136] : + f12f2_enqReq_rl[264:136] ; + assign y__h111758 = (pc_reg_rl[1:0] == 2'b0) ? pc_reg_rl[1:0] : 2'd1 ; + assign y__h114813 = { 1'd0, b__h114808 } ; + assign y_avValue_fst__h117191 = j__h114680 + 3'd1 ; + assign y_avValue_fst__h117202 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == 2'b11) ? - _theResult___fst__h122094 : - j__h119769 ; - assign y_avValue_fst__h122039 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == + _theResult___fst__h117329 : + j__h114680 ; + assign y_avValue_fst__h117230 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == 2'b11) ? - y_avValue_fst__h122012 : - y_avValue_fst__h122004 ; - assign y_avValue_snd_fst__h119828 = - SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 ? - y_avValue_snd_fst__h119835 : - n_x16s__h117514 ; - assign y_avValue_snd_fst__h119835 = - (n_x16s__h117514 < 3'd2) ? - n_x16s__h117514 + 3'd2 : - { x__h119846, n_x16s__h117514 < 3'd3 } ; - assign y_avValue_snd_fst__h122334 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == + y_avValue_fst__h117202 : + y_avValue_fst__h117191 ; + assign y_avValue_fst__h117264 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 ? + 3'd1 : + y_avValue_fst__h117230 ; + assign y_avValue_fst__h126140 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5243 + + 3'd1 ; + assign y_avValue_fst__h126151 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b11) ? + _theResult___fst__h126265 : + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5243 ; + assign y_avValue_fst__h126200 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b11) ? + y_avValue_fst__h126151 : + y_avValue_fst__h126140 ; + assign y_avValue_fst__h134851 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5254 + + 3'd1 ; + assign y_avValue_fst__h134862 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b11) ? + _theResult___fst__h134976 : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5254 ; + assign y_avValue_fst__h134911 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b11) ? + y_avValue_fst__h134862 : + y_avValue_fst__h134851 ; + assign y_avValue_fst_main_epoch__h146082 = + (pending_n_items__h113790 == 2'd0) ? + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4929 : + rg_pending_f32d[3:0] ; + assign y_avValue_fst_pc__h146077 = + (pending_n_items__h113790 == 2'd0) ? + pc_start__h114675 : + rg_pending_f32d[333:205] ; + assign y_avValue_fst_tval__h146080 = + (pending_n_items__h113790 == 2'd0) ? + out___1_tval__h146073 : + rg_pending_f32d[68:5] ; + assign y_avValue_snd__h113781 = + (!rg_pending_f32d_953_BITS_3_TO_0_954_EQ_f_main__ETC___d4955 || + !rg_pending_f32d_953_BIT_4_957_EQ_IF_decode_epo_ETC___d4958) ? + 2'd0 : + rg_pending_n_items ; + assign y_avValue_snd__h168590 = + _0_CONCAT_IF_rg_pending_n_items_951_EQ_0_952_TH_ETC___d5375 ? + 2'd0 : + y_avValue_snd_fst__h165552 ; + assign y_avValue_snd_fst__h117557 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 ? + ehr_pending_straddle_rl[80:17] : + pc_start__h114675[63:0] ; + assign y_avValue_snd_fst__h117639 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[11:7] != + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[11:7] != 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[15:13] == + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[15:13] == 3'b010) ? - instr__h123060 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4630 ; - assign y_avValue_snd_fst__h131336 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[1:0] == + instr__h118639 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6620 ; + assign y_avValue_snd_fst__h117641 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b11) ? + _theResult___snd_fst__h117672 : + 32'd0 ; + assign y_avValue_snd_fst__h126529 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == 2'b10 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[11:7] != + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[11:7] != 5'd0 && - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044[15:13] == + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[15:13] == 3'b010) ? - instr__h131614 : - IF_SEL_ARR_IF_rg_pending_straddle_514_THEN_IF__ETC___d4337 ; - assign y_avValue_snd_snd__h119829 = - SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 ? - rg_half_inst_pc : - start_PC__h117515 ; - assign y_avValue_snd_snd_snd_fst__h122323 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == + instr__h127439 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d5720 ; + assign y_avValue_snd_fst__h126531 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == 2'b11) ? - y_avValue_snd_snd_snd_fst__h122348 : - next_pc___1__h122117 ; - assign y_avValue_snd_snd_snd_fst__h122348 = - (SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028[1:0] == + _theResult___snd_fst__h126562 : + 32'd0 ; + assign y_avValue_snd_fst__h135240 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[15:13] == + 3'b010) ? + instr__h136193 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6009 ; + assign y_avValue_snd_fst__h135242 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == 2'b11) ? - _theResult___snd_snd_snd_fst__h122369 : - pc_start__h119765 ; + _theResult___snd_fst__h135273 : + 32'd0 ; + assign y_avValue_snd_fst__h143841 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b10 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[11:7] != + 5'd0 && + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[15:13] == + 3'b010) ? + instr__h152465 : + IF_SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_S_ETC___d6298 ; + assign y_avValue_snd_fst__h143843 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b11) ? + _theResult___snd_fst__h144006 : + 32'd0 ; + assign y_avValue_snd_fst__h165552 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5380 ? + x__h163892[1:0] : + 2'd0 ; + assign y_avValue_snd_snd_fst__h117562 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 ? + y_avValue_snd_snd_fst__h117591 : + y_avValue_snd_snd_fst__h117593 ; + assign y_avValue_snd_snd_fst__h117591 = + { IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[15:0], + ehr_pending_straddle_rl[16:1] } ; + assign y_avValue_snd_snd_fst__h117593 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b11) ? + y_avValue_snd_fst__h117641 : + y_avValue_snd_fst__h117639 ; + assign y_avValue_snd_snd_fst__h117645 = + { 16'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234 } ; + assign y_avValue_snd_snd_fst__h126498 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b11) ? + y_avValue_snd_fst__h126531 : + y_avValue_snd_fst__h126529 ; + assign y_avValue_snd_snd_fst__h126535 = + { 16'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245 } ; + assign y_avValue_snd_snd_fst__h135209 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b11) ? + y_avValue_snd_fst__h135242 : + y_avValue_snd_fst__h135240 ; + assign y_avValue_snd_snd_fst__h135246 = + { 16'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256 } ; + assign y_avValue_snd_snd_fst__h143783 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b11) ? + y_avValue_snd_fst__h143843 : + y_avValue_snd_fst__h143841 ; + assign y_avValue_snd_snd_fst__h143847 = + { 16'd0, + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267 } ; + assign y_avValue_snd_snd_fst__h146015 = + (f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081) ? + y_avValue_snd_snd_fst__h146024 : + 3'd0 ; + assign y_avValue_snd_snd_fst__h146024 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5266 ? + ((SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] != + 2'b11 || + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5271) ? + 3'd4 : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5369) : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5369 ; + assign y_avValue_snd_snd_snd_fst__h117567 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 ? + y_avValue_snd_snd_fst__h117591 : + y_avValue_snd_snd_snd_fst__h117599 ; + assign y_avValue_snd_snd_snd_fst__h117599 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b11) ? + y_avValue_snd_fst__h117641 : + y_avValue_snd_snd_fst__h117645 ; + assign y_avValue_snd_snd_snd_fst__h117651 = + pc_start__h114675[63:0] + 64'd2 ; + assign y_avValue_snd_snd_snd_fst__h117653 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b11) ? + _theResult___snd_snd_snd_fst__h117676 : + pc_start__h114675[63:0] ; + assign y_avValue_snd_snd_snd_fst__h126503 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b11) ? + y_avValue_snd_fst__h126531 : + y_avValue_snd_snd_fst__h126535 ; + assign y_avValue_snd_snd_snd_fst__h126541 = + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5333 + + 64'd2 ; + assign y_avValue_snd_snd_snd_fst__h126543 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b11) ? + _theResult___snd_snd_snd_fst__h126566 : + IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5333 ; + assign y_avValue_snd_snd_snd_fst__h135214 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b11) ? + y_avValue_snd_fst__h135242 : + y_avValue_snd_snd_fst__h135246 ; + assign y_avValue_snd_snd_snd_fst__h135252 = + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5342 + + 64'd2 ; + assign y_avValue_snd_snd_snd_fst__h135254 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b11) ? + _theResult___snd_snd_snd_fst__h135277 : + IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5342 ; + assign y_avValue_snd_snd_snd_fst__h143788 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b11) ? + y_avValue_snd_fst__h143843 : + y_avValue_snd_snd_fst__h143847 ; + assign y_avValue_snd_snd_snd_fst__h143853 = + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5351 + + 64'd2 ; + assign y_avValue_snd_snd_snd_fst__h143855 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b11) ? + _theResult___snd_snd_snd_fst__h144010 : + IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5351 ; + assign y_avValue_snd_snd_snd_snd_fst__h117572 = + IF_rg_pending_n_items_951_EQ_0_952_THEN_ehr_pe_ETC___d4988 ? + y_avValue_snd_snd_snd_snd_fst__h117603 : + y_avValue_snd_snd_snd_snd_fst__h117605 ; + assign y_avValue_snd_snd_snd_snd_fst__h117603 = + ehr_pending_straddle_rl[80:17] + 64'd4 ; + assign y_avValue_snd_snd_snd_snd_fst__h117605 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234[1:0] == + 2'b11) ? + y_avValue_snd_snd_snd_fst__h117653 : + y_avValue_snd_snd_snd_fst__h117651 ; + assign y_avValue_snd_snd_snd_snd_fst__h126508 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245[1:0] == + 2'b11) ? + y_avValue_snd_snd_snd_fst__h126543 : + y_avValue_snd_snd_snd_fst__h126541 ; + assign y_avValue_snd_snd_snd_snd_fst__h135219 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256[1:0] == + 2'b11) ? + y_avValue_snd_snd_snd_fst__h135254 : + y_avValue_snd_snd_snd_fst__h135252 ; + assign y_avValue_snd_snd_snd_snd_fst__h143793 = + (SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267[1:0] == + 2'b11) ? + y_avValue_snd_snd_snd_fst__h143855 : + y_avValue_snd_snd_snd_fst__h143853 ; always@(iTlb$to_proc_response_get) begin - case (iTlb$to_proc_response_get[3:0]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_iTlbto_proc_response_get_BITS_3_TO_0_0_i_ETC__q1 = - iTlb$to_proc_response_get[3:0]; - default: CASE_iTlbto_proc_response_get_BITS_3_TO_0_0_i_ETC__q1 = 4'd15; + case (iTlb$to_proc_response_get[4:0]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd11, + 5'd12, + 5'd13, + 5'd15: + CASE_iTlbto_proc_response_get_BITS_4_TO_0_0_i_ETC__q1 = + iTlb$to_proc_response_get[4:0]; + default: CASE_iTlbto_proc_response_get_BITS_4_TO_0_0_i_ETC__q1 = 5'd28; + endcase + end + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: nbSupX2In__h113561 = f22f3_data_0[337:336]; + 2'd1: nbSupX2In__h113561 = f22f3_data_1[337:336]; + 2'd2: nbSupX2In__h113561 = f22f3_data_2[337:336]; + 2'd3: nbSupX2In__h113561 = f22f3_data_3[337:336]; endcase end always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) begin case (f12f2_deqP) - 1'd0: x__h116417 = f12f2_data_0[133]; - 1'd1: x__h116417 = f12f2_data_1[133]; + 1'd0: out_pc__h112351 = f12f2_data_0[264:136]; + 1'd1: out_pc__h112351 = f12f2_data_1[264:136]; endcase end always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) begin case (f12f2_deqP) - 1'd0: x__h116419 = f12f2_data_0[132:69]; - 1'd1: x__h116419 = f12f2_data_1[132:69]; + 1'd0: out_main_epoch__h112357 = f12f2_data_0[3:0]; + 1'd1: out_main_epoch__h112357 = f12f2_data_1[3:0]; endcase end - always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) + always@(instdata_deqP_rl or instdata_data_0 or instdata_data_1) begin - case (f12f2_deqP) - 1'd0: x__h116447 = f12f2_data_0[68:5]; - 1'd1: x__h116447 = f12f2_data_1[68:5]; - endcase - end - always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) - begin - case (f12f2_deqP) - 1'd0: out_main_epoch__h116425 = f12f2_data_0[3:0]; - 1'd1: out_main_epoch__h116425 = f12f2_data_1[3:0]; - endcase - end - always@(f22f3_deqP or - f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) - begin - case (f22f3_deqP) - 2'd0: value__h117642 = f22f3_data_0[267]; - 2'd1: value__h117642 = f22f3_data_1[267]; - 2'd2: value__h117642 = f22f3_data_2[267]; - 2'd3: value__h117642 = f22f3_data_3[267]; - endcase - end - always@(f22f3_deqP or - f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) - begin - case (f22f3_deqP) - 2'd0: start_PC__h117515 = f22f3_data_0[266:203]; - 2'd1: start_PC__h117515 = f22f3_data_1[266:203]; - 2'd2: start_PC__h117515 = f22f3_data_2[266:203]; - 2'd3: start_PC__h117515 = f22f3_data_3[266:203]; - endcase - end - always@(f22f3_deqP or - f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) - begin - case (f22f3_deqP) - 2'd0: value__h117654 = f22f3_data_0[202:139]; - 2'd1: value__h117654 = f22f3_data_1[202:139]; - 2'd2: value__h117654 = f22f3_data_2[202:139]; - 2'd3: value__h117654 = f22f3_data_3[202:139]; - endcase - end - always@(f22f3_deqP or - f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) - begin - case (f22f3_deqP) - 2'd0: value__h117656 = f22f3_data_0[138:75]; - 2'd1: value__h117656 = f22f3_data_1[138:75]; - 2'd2: value__h117656 = f22f3_data_2[138:75]; - 2'd3: value__h117656 = f22f3_data_3[138:75]; - endcase - end - always@(f22f3_deqP or - f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) - begin - case (f22f3_deqP) - 2'd0: value__h118910 = f22f3_data_0[69:6]; - 2'd1: value__h118910 = f22f3_data_1[69:6]; - 2'd2: value__h118910 = f22f3_data_2[69:6]; - 2'd3: value__h118910 = f22f3_data_3[69:6]; + case (instdata_deqP_rl) + 1'd0: x__h171664 = instdata_data_0[194:66]; + 1'd1: x__h171664 = instdata_data_1[194:66]; endcase end always@(f32d_deqP or f32d_data_0 or f32d_data_1) begin case (f32d_deqP) - 1'd0: x__h149997 = f32d_data_0[69:6]; - 1'd1: x__h149997 = f32d_data_1[69:6]; + 1'd0: out_main_epoch__h177345 = f32d_data_0[3:0]; + 1'd1: out_main_epoch__h177345 = f32d_data_1[3:0]; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(instdata_deqP_rl or instdata_data_0 or instdata_data_1) begin - case (x__h63120) - 1'd0: x__h161003 = out_fifo_internalFifos_0$D_OUT[323:260]; - 1'd1: x__h161003 = out_fifo_internalFifos_1$D_OUT[323:260]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: x__h161061 = out_fifo_internalFifos_0$D_OUT[231:200]; - 1'd1: x__h161061 = out_fifo_internalFifos_1$D_OUT[231:200]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: x__h166575 = out_fifo_internalFifos_0$D_OUT[127:96]; - 1'd1: x__h166575 = out_fifo_internalFifos_1$D_OUT[127:96]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: x__h167949 = out_fifo_internalFifos_0$D_OUT[63:0]; - 1'd1: x__h167949 = out_fifo_internalFifos_1$D_OUT[63:0]; - endcase - end - always@(n__read__h142595 or instdata_data_0 or instdata_data_1) - begin - case (n__read__h142595) - 1'd0: x__h143344 = instdata_data_0[129:66]; - 1'd1: x__h143344 = instdata_data_1[129:66]; + case (instdata_deqP_rl) + 1'd0: x__h180841 = instdata_data_0[63:32]; + 1'd1: x__h180841 = instdata_data_1[63:32]; endcase end always@(f32d_deqP or f32d_data_0 or f32d_data_1) begin case (f32d_deqP) - 1'd0: in_ppc__h150788 = f32d_data_0[138:75]; - 1'd1: in_ppc__h150788 = f32d_data_1[138:75]; + 1'd0: tval___2__h171521 = f32d_data_0[68:5]; + 1'd1: tval___2__h171521 = f32d_data_1[68:5]; endcase end - always@(x__h72803 or + always@(instdata_deqP_rl or instdata_data_0 or instdata_data_1) + begin + case (instdata_deqP_rl) + 1'd0: x__h191306 = instdata_data_0[258:227]; + 1'd1: x__h191306 = instdata_data_1[258:227]; + endcase + end + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) - 1'd0: x__h168147 = out_fifo_internalFifos_0$D_OUT[323:260]; - 1'd1: x__h168147 = out_fifo_internalFifos_1$D_OUT[323:260]; + case (out_fifo_dequeueFifo_rl) + 1'd0: x__h195426 = out_fifo_internalFifos_0$D_OUT[461:333]; + 1'd1: x__h195426 = out_fifo_internalFifos_1$D_OUT[461:333]; endcase end - always@(x__h72803 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) - 1'd0: x__h168161 = out_fifo_internalFifos_0$D_OUT[231:200]; - 1'd1: x__h168161 = out_fifo_internalFifos_1$D_OUT[231:200]; + case (out_fifo_dequeueFifo_rl) + 1'd0: x__h195484 = out_fifo_internalFifos_0$D_OUT[304:273]; + 1'd1: x__h195484 = out_fifo_internalFifos_1$D_OUT[304:273]; endcase end - always@(x__h72803 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) - 1'd0: x__h173399 = out_fifo_internalFifos_0$D_OUT[127:96]; - 1'd1: x__h173399 = out_fifo_internalFifos_1$D_OUT[127:96]; + case (out_fifo_dequeueFifo_rl) + 1'd0: x__h200265 = out_fifo_internalFifos_0$D_OUT[192:187]; + 1'd1: x__h200265 = out_fifo_internalFifos_1$D_OUT[192:187]; endcase end - always@(x__h72803 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) - 1'd0: x__h174427 = out_fifo_internalFifos_0$D_OUT[63:0]; - 1'd1: x__h174427 = out_fifo_internalFifos_1$D_OUT[63:0]; + case (out_fifo_dequeueFifo_rl) + 1'd0: x__h200270 = out_fifo_internalFifos_0$D_OUT[186:181]; + 1'd1: x__h200270 = out_fifo_internalFifos_1$D_OUT[186:181]; endcase end - always@(x__h63120 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) - 1'd0: x__h160939 = out_fifo_internalFifos_0$D_OUT[387:324]; - 1'd1: x__h160939 = out_fifo_internalFifos_1$D_OUT[387:324]; + case (out_fifo_dequeueFifo_rl) + 1'd0: x__h206149 = out_fifo_internalFifos_0$D_OUT[128:97]; + 1'd1: x__h206149 = out_fifo_internalFifos_1$D_OUT[128:97]; endcase end - always@(x__h72803 or + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: pc_start__h114675 = f22f3_data_0[335:207]; + 2'd1: pc_start__h114675 = f22f3_data_1[335:207]; + 2'd2: pc_start__h114675 = f22f3_data_2[335:207]; + 2'd3: pc_start__h114675 = f22f3_data_3[335:207]; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: in_ppc__h182302 = f32d_data_0[204:76]; + 1'd1: in_ppc__h182302 = f32d_data_1[204:76]; + endcase + end + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: out___1_tval__h146073 = f22f3_data_0[70:7]; + 2'd1: out___1_tval__h146073 = f22f3_data_1[70:7]; + 2'd2: out___1_tval__h146073 = f22f3_data_2[70:7]; + 2'd3: out___1_tval__h146073 = f22f3_data_3[70:7]; + endcase + end + always@(mmio$getFetchTarget or tval__h112495) + begin + case (mmio$getFetchTarget) + 2'd0, 2'd1: y_avValue_snd_fst__h113417 = 64'd0; + default: y_avValue_snd_fst__h113417 = tval__h112495; + endcase + end + always@(x__h74473 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) - 1'd0: x__h168127 = out_fifo_internalFifos_0$D_OUT[387:324]; - 1'd1: x__h168127 = out_fifo_internalFifos_1$D_OUT[387:324]; + case (x__h74473) + 1'd0: x__h207723 = out_fifo_internalFifos_0$D_OUT[461:333]; + 1'd1: x__h207723 = out_fifo_internalFifos_1$D_OUT[461:333]; endcase end - always@(x__h115849 or + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: x__h207737 = out_fifo_internalFifos_0$D_OUT[304:273]; + 1'd1: x__h207737 = out_fifo_internalFifos_1$D_OUT[304:273]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: x__h211978 = out_fifo_internalFifos_0$D_OUT[192:187]; + 1'd1: x__h211978 = out_fifo_internalFifos_1$D_OUT[192:187]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: x__h211979 = out_fifo_internalFifos_0$D_OUT[186:181]; + 1'd1: x__h211979 = out_fifo_internalFifos_1$D_OUT[186:181]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: x__h217664 = out_fifo_internalFifos_0$D_OUT[128:97]; + 1'd1: x__h217664 = out_fifo_internalFifos_1$D_OUT[128:97]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: x__h195362 = out_fifo_internalFifos_0$D_OUT[590:462]; + 1'd1: x__h195362 = out_fifo_internalFifos_1$D_OUT[590:462]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: x__h207703 = out_fifo_internalFifos_0$D_OUT[590:462]; + 1'd1: x__h207703 = out_fifo_internalFifos_1$D_OUT[590:462]; + endcase + end + always@(out_fifo_enqueueElement_0_rl) + begin + case (out_fifo_enqueueElement_0_rl[235:232]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143 = + out_fifo_enqueueElement_0_rl[235:232]; + default: IF_out_fifo_enqueueElement_0_rl_07_BITS_235_TO_ETC___d1143 = + 4'd11; + endcase + end + always@(out_fifo_enqueueElement_0_rl) + begin + case (out_fifo_enqueueElement_0_rl[231:229]) + 3'd2, 3'd3: + IF_out_fifo_enqueueElement_0_rl_07_BITS_231_TO_ETC___d1244 = + out_fifo_enqueueElement_0_rl[231:229]; + default: IF_out_fifo_enqueueElement_0_rl_07_BITS_231_TO_ETC___d1244 = + 3'd4; + endcase + end + always@(out_fifo_enqueueElement_1_rl) + begin + case (out_fifo_enqueueElement_1_rl[235:232]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310 = + out_fifo_enqueueElement_1_rl[235:232]; + default: IF_out_fifo_enqueueElement_1_rl_075_BITS_235_T_ETC___d2310 = + 4'd11; + endcase + end + always@(out_fifo_enqueueElement_1_rl) + begin + case (out_fifo_enqueueElement_1_rl[231:229]) + 3'd2, 3'd3: + IF_out_fifo_enqueueElement_1_rl_075_BITS_231_T_ETC___d2411 = + out_fifo_enqueueElement_1_rl[231:229]; + default: IF_out_fifo_enqueueElement_1_rl_075_BITS_231_T_ETC___d2411 = + 3'd4; + endcase + end + always@(pc_reg_rl or nextAddrPred_valid_0 or nextAddrPred_valid_1 or nextAddrPred_valid_2 or @@ -13642,778 +17345,778 @@ module mkFetchStage(CLK, nextAddrPred_valid_253 or nextAddrPred_valid_254 or nextAddrPred_valid_255) begin - case (x__h115849[9:2]) + case (pc_reg_rl[8:1]) 8'd0: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_0; 8'd1: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_1; 8'd2: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_2; 8'd3: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_3; 8'd4: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_4; 8'd5: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_5; 8'd6: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_6; 8'd7: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_7; 8'd8: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_8; 8'd9: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_9; 8'd10: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_10; 8'd11: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_11; 8'd12: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_12; 8'd13: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_13; 8'd14: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_14; 8'd15: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_15; 8'd16: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_16; 8'd17: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_17; 8'd18: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_18; 8'd19: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_19; 8'd20: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_20; 8'd21: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_21; 8'd22: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_22; 8'd23: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_23; 8'd24: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_24; 8'd25: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_25; 8'd26: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_26; 8'd27: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_27; 8'd28: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_28; 8'd29: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_29; 8'd30: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_30; 8'd31: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_31; 8'd32: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_32; 8'd33: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_33; 8'd34: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_34; 8'd35: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_35; 8'd36: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_36; 8'd37: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_37; 8'd38: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_38; 8'd39: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_39; 8'd40: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_40; 8'd41: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_41; 8'd42: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_42; 8'd43: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_43; 8'd44: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_44; 8'd45: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_45; 8'd46: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_46; 8'd47: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_47; 8'd48: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_48; 8'd49: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_49; 8'd50: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_50; 8'd51: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_51; 8'd52: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_52; 8'd53: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_53; 8'd54: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_54; 8'd55: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_55; 8'd56: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_56; 8'd57: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_57; 8'd58: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_58; 8'd59: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_59; 8'd60: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_60; 8'd61: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_61; 8'd62: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_62; 8'd63: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_63; 8'd64: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_64; 8'd65: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_65; 8'd66: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_66; 8'd67: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_67; 8'd68: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_68; 8'd69: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_69; 8'd70: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_70; 8'd71: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_71; 8'd72: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_72; 8'd73: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_73; 8'd74: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_74; 8'd75: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_75; 8'd76: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_76; 8'd77: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_77; 8'd78: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_78; 8'd79: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_79; 8'd80: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_80; 8'd81: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_81; 8'd82: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_82; 8'd83: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_83; 8'd84: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_84; 8'd85: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_85; 8'd86: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_86; 8'd87: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_87; 8'd88: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_88; 8'd89: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_89; 8'd90: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_90; 8'd91: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_91; 8'd92: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_92; 8'd93: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_93; 8'd94: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_94; 8'd95: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_95; 8'd96: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_96; 8'd97: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_97; 8'd98: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_98; 8'd99: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_99; 8'd100: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_100; 8'd101: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_101; 8'd102: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_102; 8'd103: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_103; 8'd104: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_104; 8'd105: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_105; 8'd106: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_106; 8'd107: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_107; 8'd108: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_108; 8'd109: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_109; 8'd110: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_110; 8'd111: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_111; 8'd112: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_112; 8'd113: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_113; 8'd114: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_114; 8'd115: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_115; 8'd116: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_116; 8'd117: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_117; 8'd118: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_118; 8'd119: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_119; 8'd120: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_120; 8'd121: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_121; 8'd122: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_122; 8'd123: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_123; 8'd124: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_124; 8'd125: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_125; 8'd126: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_126; 8'd127: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_127; 8'd128: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_128; 8'd129: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_129; 8'd130: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_130; 8'd131: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_131; 8'd132: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_132; 8'd133: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_133; 8'd134: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_134; 8'd135: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_135; 8'd136: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_136; 8'd137: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_137; 8'd138: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_138; 8'd139: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_139; 8'd140: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_140; 8'd141: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_141; 8'd142: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_142; 8'd143: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_143; 8'd144: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_144; 8'd145: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_145; 8'd146: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_146; 8'd147: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_147; 8'd148: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_148; 8'd149: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_149; 8'd150: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_150; 8'd151: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_151; 8'd152: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_152; 8'd153: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_153; 8'd154: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_154; 8'd155: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_155; 8'd156: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_156; 8'd157: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_157; 8'd158: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_158; 8'd159: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_159; 8'd160: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_160; 8'd161: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_161; 8'd162: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_162; 8'd163: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_163; 8'd164: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_164; 8'd165: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_165; 8'd166: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_166; 8'd167: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_167; 8'd168: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_168; 8'd169: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_169; 8'd170: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_170; 8'd171: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_171; 8'd172: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_172; 8'd173: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_173; 8'd174: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_174; 8'd175: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_175; 8'd176: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_176; 8'd177: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_177; 8'd178: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_178; 8'd179: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_179; 8'd180: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_180; 8'd181: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_181; 8'd182: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_182; 8'd183: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_183; 8'd184: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_184; 8'd185: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_185; 8'd186: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_186; 8'd187: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_187; 8'd188: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_188; 8'd189: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_189; 8'd190: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_190; 8'd191: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_191; 8'd192: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_192; 8'd193: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_193; 8'd194: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_194; 8'd195: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_195; 8'd196: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_196; 8'd197: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_197; 8'd198: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_198; 8'd199: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_199; 8'd200: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_200; 8'd201: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_201; 8'd202: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_202; 8'd203: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_203; 8'd204: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_204; 8'd205: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_205; 8'd206: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_206; 8'd207: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_207; 8'd208: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_208; 8'd209: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_209; 8'd210: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_210; 8'd211: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_211; 8'd212: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_212; 8'd213: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_213; 8'd214: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_214; 8'd215: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_215; 8'd216: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_216; 8'd217: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_217; 8'd218: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_218; 8'd219: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_219; 8'd220: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_220; 8'd221: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_221; 8'd222: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_222; 8'd223: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_223; 8'd224: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_224; 8'd225: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_225; 8'd226: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_226; 8'd227: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_227; 8'd228: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_228; 8'd229: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_229; 8'd230: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_230; 8'd231: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_231; 8'd232: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_232; 8'd233: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_233; 8'd234: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_234; 8'd235: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_235; 8'd236: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_236; 8'd237: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_237; 8'd238: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_238; 8'd239: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_239; 8'd240: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_240; 8'd241: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_241; 8'd242: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_242; 8'd243: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_243; 8'd244: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_244; 8'd245: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_245; 8'd246: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_246; 8'd247: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_247; 8'd248: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_248; 8'd249: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_249; 8'd250: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_250; 8'd251: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_251; 8'd252: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_252; 8'd253: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_253; 8'd254: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_254; 8'd255: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3331 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4680 = nextAddrPred_valid_255; endcase end - always@(pred_next_pc__h114157 or + always@(address__h109631 or nextAddrPred_valid_0 or nextAddrPred_valid_1 or nextAddrPred_valid_2 or @@ -14670,774 +18373,2830 @@ module mkFetchStage(CLK, nextAddrPred_valid_253 or nextAddrPred_valid_254 or nextAddrPred_valid_255) begin - case (pred_next_pc__h114157[9:2]) + case (address__h109631[8:1]) 8'd0: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_0; 8'd1: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_1; 8'd2: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_2; 8'd3: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_3; 8'd4: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_4; 8'd5: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_5; 8'd6: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_6; 8'd7: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_7; 8'd8: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_8; 8'd9: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_9; 8'd10: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_10; 8'd11: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_11; 8'd12: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_12; 8'd13: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_13; 8'd14: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_14; 8'd15: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_15; 8'd16: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_16; 8'd17: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_17; 8'd18: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_18; 8'd19: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_19; 8'd20: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_20; 8'd21: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_21; 8'd22: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_22; 8'd23: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_23; 8'd24: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_24; 8'd25: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_25; 8'd26: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_26; 8'd27: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_27; 8'd28: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_28; 8'd29: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_29; 8'd30: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_30; 8'd31: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_31; 8'd32: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_32; 8'd33: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_33; 8'd34: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_34; 8'd35: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_35; 8'd36: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_36; 8'd37: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_37; 8'd38: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_38; 8'd39: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_39; 8'd40: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_40; 8'd41: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_41; 8'd42: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_42; 8'd43: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_43; 8'd44: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_44; 8'd45: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_45; 8'd46: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_46; 8'd47: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_47; 8'd48: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_48; 8'd49: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_49; 8'd50: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_50; 8'd51: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_51; 8'd52: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_52; 8'd53: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_53; 8'd54: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_54; 8'd55: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_55; 8'd56: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_56; 8'd57: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_57; 8'd58: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_58; 8'd59: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_59; 8'd60: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_60; 8'd61: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_61; 8'd62: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_62; 8'd63: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_63; 8'd64: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_64; 8'd65: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_65; 8'd66: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_66; 8'd67: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_67; 8'd68: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_68; 8'd69: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_69; 8'd70: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_70; 8'd71: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_71; 8'd72: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_72; 8'd73: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_73; 8'd74: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_74; 8'd75: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_75; 8'd76: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_76; 8'd77: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_77; 8'd78: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_78; 8'd79: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_79; 8'd80: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_80; 8'd81: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_81; 8'd82: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_82; 8'd83: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_83; 8'd84: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_84; 8'd85: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_85; 8'd86: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_86; 8'd87: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_87; 8'd88: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_88; 8'd89: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_89; 8'd90: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_90; 8'd91: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_91; 8'd92: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_92; 8'd93: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_93; 8'd94: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_94; 8'd95: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_95; 8'd96: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_96; 8'd97: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_97; 8'd98: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_98; 8'd99: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_99; 8'd100: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_100; 8'd101: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_101; 8'd102: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_102; 8'd103: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_103; 8'd104: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_104; 8'd105: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_105; 8'd106: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_106; 8'd107: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_107; 8'd108: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_108; 8'd109: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_109; 8'd110: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_110; 8'd111: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_111; 8'd112: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_112; 8'd113: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_113; 8'd114: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_114; 8'd115: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_115; 8'd116: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_116; 8'd117: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_117; 8'd118: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_118; 8'd119: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_119; 8'd120: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_120; 8'd121: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_121; 8'd122: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_122; 8'd123: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_123; 8'd124: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_124; 8'd125: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_125; 8'd126: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_126; 8'd127: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_127; 8'd128: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_128; 8'd129: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_129; 8'd130: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_130; 8'd131: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_131; 8'd132: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_132; 8'd133: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_133; 8'd134: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_134; 8'd135: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_135; 8'd136: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_136; 8'd137: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_137; 8'd138: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_138; 8'd139: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_139; 8'd140: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_140; 8'd141: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_141; 8'd142: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_142; 8'd143: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_143; 8'd144: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_144; 8'd145: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_145; 8'd146: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_146; 8'd147: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_147; 8'd148: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_148; 8'd149: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_149; 8'd150: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_150; 8'd151: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_151; 8'd152: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_152; 8'd153: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_153; 8'd154: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_154; 8'd155: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_155; 8'd156: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_156; 8'd157: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_157; 8'd158: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_158; 8'd159: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_159; 8'd160: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_160; 8'd161: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_161; 8'd162: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_162; 8'd163: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_163; 8'd164: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_164; 8'd165: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_165; 8'd166: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_166; 8'd167: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_167; 8'd168: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_168; 8'd169: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_169; 8'd170: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_170; 8'd171: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_171; 8'd172: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_172; 8'd173: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_173; 8'd174: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_174; 8'd175: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_175; 8'd176: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_176; 8'd177: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_177; 8'd178: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_178; 8'd179: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_179; 8'd180: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_180; 8'd181: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_181; 8'd182: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_182; 8'd183: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_183; 8'd184: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_184; 8'd185: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_185; 8'd186: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_186; 8'd187: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_187; 8'd188: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_188; 8'd189: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_189; 8'd190: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_190; 8'd191: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_191; 8'd192: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_192; 8'd193: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_193; 8'd194: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_194; 8'd195: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_195; 8'd196: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_196; 8'd197: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_197; 8'd198: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_198; 8'd199: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_199; 8'd200: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_200; 8'd201: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_201; 8'd202: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_202; 8'd203: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_203; 8'd204: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_204; 8'd205: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_205; 8'd206: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_206; 8'd207: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_207; 8'd208: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_208; 8'd209: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_209; 8'd210: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_210; 8'd211: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_211; 8'd212: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_212; 8'd213: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_213; 8'd214: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_214; 8'd215: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_215; 8'd216: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_216; 8'd217: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_217; 8'd218: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_218; 8'd219: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_219; 8'd220: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_220; 8'd221: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_221; 8'd222: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_222; 8'd223: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_223; 8'd224: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_224; 8'd225: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_225; 8'd226: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_226; 8'd227: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_227; 8'd228: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_228; 8'd229: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_229; 8'd230: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_230; 8'd231: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_231; 8'd232: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_232; 8'd233: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_233; 8'd234: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_234; 8'd235: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_235; 8'd236: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_236; 8'd237: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_237; 8'd238: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_238; 8'd239: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_239; 8'd240: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_240; 8'd241: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_241; 8'd242: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_242; 8'd243: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_243; 8'd244: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_244; 8'd245: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_245; 8'd246: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_246; 8'd247: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_247; 8'd248: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_248; 8'd249: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_249; 8'd250: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_250; 8'd251: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_251; 8'd252: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_252; 8'd253: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_253; 8'd254: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = nextAddrPred_valid_254; 8'd255: - SEL_ARR_nextAddrPred_valid_0_read__073_nextAdd_ETC___d3344 = + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4700 = + nextAddrPred_valid_255; + endcase + end + always@(address__h110316 or + nextAddrPred_valid_0 or + nextAddrPred_valid_1 or + nextAddrPred_valid_2 or + nextAddrPred_valid_3 or + nextAddrPred_valid_4 or + nextAddrPred_valid_5 or + nextAddrPred_valid_6 or + nextAddrPred_valid_7 or + nextAddrPred_valid_8 or + nextAddrPred_valid_9 or + nextAddrPred_valid_10 or + nextAddrPred_valid_11 or + nextAddrPred_valid_12 or + nextAddrPred_valid_13 or + nextAddrPred_valid_14 or + nextAddrPred_valid_15 or + nextAddrPred_valid_16 or + nextAddrPred_valid_17 or + nextAddrPred_valid_18 or + nextAddrPred_valid_19 or + nextAddrPred_valid_20 or + nextAddrPred_valid_21 or + nextAddrPred_valid_22 or + nextAddrPred_valid_23 or + nextAddrPred_valid_24 or + nextAddrPred_valid_25 or + nextAddrPred_valid_26 or + nextAddrPred_valid_27 or + nextAddrPred_valid_28 or + nextAddrPred_valid_29 or + nextAddrPred_valid_30 or + nextAddrPred_valid_31 or + nextAddrPred_valid_32 or + nextAddrPred_valid_33 or + nextAddrPred_valid_34 or + nextAddrPred_valid_35 or + nextAddrPred_valid_36 or + nextAddrPred_valid_37 or + nextAddrPred_valid_38 or + nextAddrPred_valid_39 or + nextAddrPred_valid_40 or + nextAddrPred_valid_41 or + nextAddrPred_valid_42 or + nextAddrPred_valid_43 or + nextAddrPred_valid_44 or + nextAddrPred_valid_45 or + nextAddrPred_valid_46 or + nextAddrPred_valid_47 or + nextAddrPred_valid_48 or + nextAddrPred_valid_49 or + nextAddrPred_valid_50 or + nextAddrPred_valid_51 or + nextAddrPred_valid_52 or + nextAddrPred_valid_53 or + nextAddrPred_valid_54 or + nextAddrPred_valid_55 or + nextAddrPred_valid_56 or + nextAddrPred_valid_57 or + nextAddrPred_valid_58 or + nextAddrPred_valid_59 or + nextAddrPred_valid_60 or + nextAddrPred_valid_61 or + nextAddrPred_valid_62 or + nextAddrPred_valid_63 or + nextAddrPred_valid_64 or + nextAddrPred_valid_65 or + nextAddrPred_valid_66 or + nextAddrPred_valid_67 or + nextAddrPred_valid_68 or + nextAddrPred_valid_69 or + nextAddrPred_valid_70 or + nextAddrPred_valid_71 or + nextAddrPred_valid_72 or + nextAddrPred_valid_73 or + nextAddrPred_valid_74 or + nextAddrPred_valid_75 or + nextAddrPred_valid_76 or + nextAddrPred_valid_77 or + nextAddrPred_valid_78 or + nextAddrPred_valid_79 or + nextAddrPred_valid_80 or + nextAddrPred_valid_81 or + nextAddrPred_valid_82 or + nextAddrPred_valid_83 or + nextAddrPred_valid_84 or + nextAddrPred_valid_85 or + nextAddrPred_valid_86 or + nextAddrPred_valid_87 or + nextAddrPred_valid_88 or + nextAddrPred_valid_89 or + nextAddrPred_valid_90 or + nextAddrPred_valid_91 or + nextAddrPred_valid_92 or + nextAddrPred_valid_93 or + nextAddrPred_valid_94 or + nextAddrPred_valid_95 or + nextAddrPred_valid_96 or + nextAddrPred_valid_97 or + nextAddrPred_valid_98 or + nextAddrPred_valid_99 or + nextAddrPred_valid_100 or + nextAddrPred_valid_101 or + nextAddrPred_valid_102 or + nextAddrPred_valid_103 or + nextAddrPred_valid_104 or + nextAddrPred_valid_105 or + nextAddrPred_valid_106 or + nextAddrPred_valid_107 or + nextAddrPred_valid_108 or + nextAddrPred_valid_109 or + nextAddrPred_valid_110 or + nextAddrPred_valid_111 or + nextAddrPred_valid_112 or + nextAddrPred_valid_113 or + nextAddrPred_valid_114 or + nextAddrPred_valid_115 or + nextAddrPred_valid_116 or + nextAddrPred_valid_117 or + nextAddrPred_valid_118 or + nextAddrPred_valid_119 or + nextAddrPred_valid_120 or + nextAddrPred_valid_121 or + nextAddrPred_valid_122 or + nextAddrPred_valid_123 or + nextAddrPred_valid_124 or + nextAddrPred_valid_125 or + nextAddrPred_valid_126 or + nextAddrPred_valid_127 or + nextAddrPred_valid_128 or + nextAddrPred_valid_129 or + nextAddrPred_valid_130 or + nextAddrPred_valid_131 or + nextAddrPred_valid_132 or + nextAddrPred_valid_133 or + nextAddrPred_valid_134 or + nextAddrPred_valid_135 or + nextAddrPred_valid_136 or + nextAddrPred_valid_137 or + nextAddrPred_valid_138 or + nextAddrPred_valid_139 or + nextAddrPred_valid_140 or + nextAddrPred_valid_141 or + nextAddrPred_valid_142 or + nextAddrPred_valid_143 or + nextAddrPred_valid_144 or + nextAddrPred_valid_145 or + nextAddrPred_valid_146 or + nextAddrPred_valid_147 or + nextAddrPred_valid_148 or + nextAddrPred_valid_149 or + nextAddrPred_valid_150 or + nextAddrPred_valid_151 or + nextAddrPred_valid_152 or + nextAddrPred_valid_153 or + nextAddrPred_valid_154 or + nextAddrPred_valid_155 or + nextAddrPred_valid_156 or + nextAddrPred_valid_157 or + nextAddrPred_valid_158 or + nextAddrPred_valid_159 or + nextAddrPred_valid_160 or + nextAddrPred_valid_161 or + nextAddrPred_valid_162 or + nextAddrPred_valid_163 or + nextAddrPred_valid_164 or + nextAddrPred_valid_165 or + nextAddrPred_valid_166 or + nextAddrPred_valid_167 or + nextAddrPred_valid_168 or + nextAddrPred_valid_169 or + nextAddrPred_valid_170 or + nextAddrPred_valid_171 or + nextAddrPred_valid_172 or + nextAddrPred_valid_173 or + nextAddrPred_valid_174 or + nextAddrPred_valid_175 or + nextAddrPred_valid_176 or + nextAddrPred_valid_177 or + nextAddrPred_valid_178 or + nextAddrPred_valid_179 or + nextAddrPred_valid_180 or + nextAddrPred_valid_181 or + nextAddrPred_valid_182 or + nextAddrPred_valid_183 or + nextAddrPred_valid_184 or + nextAddrPred_valid_185 or + nextAddrPred_valid_186 or + nextAddrPred_valid_187 or + nextAddrPred_valid_188 or + nextAddrPred_valid_189 or + nextAddrPred_valid_190 or + nextAddrPred_valid_191 or + nextAddrPred_valid_192 or + nextAddrPred_valid_193 or + nextAddrPred_valid_194 or + nextAddrPred_valid_195 or + nextAddrPred_valid_196 or + nextAddrPred_valid_197 or + nextAddrPred_valid_198 or + nextAddrPred_valid_199 or + nextAddrPred_valid_200 or + nextAddrPred_valid_201 or + nextAddrPred_valid_202 or + nextAddrPred_valid_203 or + nextAddrPred_valid_204 or + nextAddrPred_valid_205 or + nextAddrPred_valid_206 or + nextAddrPred_valid_207 or + nextAddrPred_valid_208 or + nextAddrPred_valid_209 or + nextAddrPred_valid_210 or + nextAddrPred_valid_211 or + nextAddrPred_valid_212 or + nextAddrPred_valid_213 or + nextAddrPred_valid_214 or + nextAddrPred_valid_215 or + nextAddrPred_valid_216 or + nextAddrPred_valid_217 or + nextAddrPred_valid_218 or + nextAddrPred_valid_219 or + nextAddrPred_valid_220 or + nextAddrPred_valid_221 or + nextAddrPred_valid_222 or + nextAddrPred_valid_223 or + nextAddrPred_valid_224 or + nextAddrPred_valid_225 or + nextAddrPred_valid_226 or + nextAddrPred_valid_227 or + nextAddrPred_valid_228 or + nextAddrPred_valid_229 or + nextAddrPred_valid_230 or + nextAddrPred_valid_231 or + nextAddrPred_valid_232 or + nextAddrPred_valid_233 or + nextAddrPred_valid_234 or + nextAddrPred_valid_235 or + nextAddrPred_valid_236 or + nextAddrPred_valid_237 or + nextAddrPred_valid_238 or + nextAddrPred_valid_239 or + nextAddrPred_valid_240 or + nextAddrPred_valid_241 or + nextAddrPred_valid_242 or + nextAddrPred_valid_243 or + nextAddrPred_valid_244 or + nextAddrPred_valid_245 or + nextAddrPred_valid_246 or + nextAddrPred_valid_247 or + nextAddrPred_valid_248 or + nextAddrPred_valid_249 or + nextAddrPred_valid_250 or + nextAddrPred_valid_251 or + nextAddrPred_valid_252 or + nextAddrPred_valid_253 or + nextAddrPred_valid_254 or nextAddrPred_valid_255) + begin + case (address__h110316[8:1]) + 8'd0: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_0; + 8'd1: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_1; + 8'd2: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_2; + 8'd3: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_3; + 8'd4: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_4; + 8'd5: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_5; + 8'd6: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_6; + 8'd7: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_7; + 8'd8: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_8; + 8'd9: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_9; + 8'd10: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_10; + 8'd11: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_11; + 8'd12: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_12; + 8'd13: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_13; + 8'd14: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_14; + 8'd15: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_15; + 8'd16: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_16; + 8'd17: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_17; + 8'd18: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_18; + 8'd19: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_19; + 8'd20: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_20; + 8'd21: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_21; + 8'd22: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_22; + 8'd23: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_23; + 8'd24: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_24; + 8'd25: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_25; + 8'd26: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_26; + 8'd27: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_27; + 8'd28: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_28; + 8'd29: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_29; + 8'd30: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_30; + 8'd31: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_31; + 8'd32: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_32; + 8'd33: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_33; + 8'd34: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_34; + 8'd35: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_35; + 8'd36: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_36; + 8'd37: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_37; + 8'd38: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_38; + 8'd39: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_39; + 8'd40: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_40; + 8'd41: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_41; + 8'd42: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_42; + 8'd43: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_43; + 8'd44: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_44; + 8'd45: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_45; + 8'd46: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_46; + 8'd47: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_47; + 8'd48: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_48; + 8'd49: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_49; + 8'd50: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_50; + 8'd51: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_51; + 8'd52: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_52; + 8'd53: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_53; + 8'd54: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_54; + 8'd55: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_55; + 8'd56: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_56; + 8'd57: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_57; + 8'd58: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_58; + 8'd59: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_59; + 8'd60: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_60; + 8'd61: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_61; + 8'd62: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_62; + 8'd63: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_63; + 8'd64: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_64; + 8'd65: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_65; + 8'd66: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_66; + 8'd67: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_67; + 8'd68: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_68; + 8'd69: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_69; + 8'd70: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_70; + 8'd71: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_71; + 8'd72: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_72; + 8'd73: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_73; + 8'd74: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_74; + 8'd75: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_75; + 8'd76: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_76; + 8'd77: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_77; + 8'd78: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_78; + 8'd79: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_79; + 8'd80: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_80; + 8'd81: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_81; + 8'd82: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_82; + 8'd83: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_83; + 8'd84: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_84; + 8'd85: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_85; + 8'd86: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_86; + 8'd87: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_87; + 8'd88: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_88; + 8'd89: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_89; + 8'd90: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_90; + 8'd91: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_91; + 8'd92: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_92; + 8'd93: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_93; + 8'd94: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_94; + 8'd95: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_95; + 8'd96: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_96; + 8'd97: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_97; + 8'd98: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_98; + 8'd99: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_99; + 8'd100: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_100; + 8'd101: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_101; + 8'd102: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_102; + 8'd103: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_103; + 8'd104: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_104; + 8'd105: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_105; + 8'd106: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_106; + 8'd107: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_107; + 8'd108: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_108; + 8'd109: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_109; + 8'd110: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_110; + 8'd111: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_111; + 8'd112: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_112; + 8'd113: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_113; + 8'd114: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_114; + 8'd115: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_115; + 8'd116: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_116; + 8'd117: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_117; + 8'd118: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_118; + 8'd119: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_119; + 8'd120: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_120; + 8'd121: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_121; + 8'd122: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_122; + 8'd123: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_123; + 8'd124: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_124; + 8'd125: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_125; + 8'd126: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_126; + 8'd127: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_127; + 8'd128: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_128; + 8'd129: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_129; + 8'd130: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_130; + 8'd131: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_131; + 8'd132: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_132; + 8'd133: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_133; + 8'd134: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_134; + 8'd135: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_135; + 8'd136: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_136; + 8'd137: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_137; + 8'd138: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_138; + 8'd139: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_139; + 8'd140: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_140; + 8'd141: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_141; + 8'd142: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_142; + 8'd143: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_143; + 8'd144: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_144; + 8'd145: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_145; + 8'd146: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_146; + 8'd147: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_147; + 8'd148: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_148; + 8'd149: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_149; + 8'd150: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_150; + 8'd151: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_151; + 8'd152: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_152; + 8'd153: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_153; + 8'd154: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_154; + 8'd155: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_155; + 8'd156: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_156; + 8'd157: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_157; + 8'd158: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_158; + 8'd159: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_159; + 8'd160: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_160; + 8'd161: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_161; + 8'd162: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_162; + 8'd163: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_163; + 8'd164: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_164; + 8'd165: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_165; + 8'd166: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_166; + 8'd167: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_167; + 8'd168: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_168; + 8'd169: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_169; + 8'd170: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_170; + 8'd171: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_171; + 8'd172: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_172; + 8'd173: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_173; + 8'd174: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_174; + 8'd175: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_175; + 8'd176: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_176; + 8'd177: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_177; + 8'd178: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_178; + 8'd179: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_179; + 8'd180: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_180; + 8'd181: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_181; + 8'd182: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_182; + 8'd183: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_183; + 8'd184: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_184; + 8'd185: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_185; + 8'd186: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_186; + 8'd187: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_187; + 8'd188: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_188; + 8'd189: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_189; + 8'd190: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_190; + 8'd191: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_191; + 8'd192: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_192; + 8'd193: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_193; + 8'd194: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_194; + 8'd195: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_195; + 8'd196: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_196; + 8'd197: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_197; + 8'd198: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_198; + 8'd199: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_199; + 8'd200: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_200; + 8'd201: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_201; + 8'd202: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_202; + 8'd203: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_203; + 8'd204: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_204; + 8'd205: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_205; + 8'd206: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_206; + 8'd207: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_207; + 8'd208: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_208; + 8'd209: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_209; + 8'd210: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_210; + 8'd211: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_211; + 8'd212: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_212; + 8'd213: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_213; + 8'd214: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_214; + 8'd215: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_215; + 8'd216: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_216; + 8'd217: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_217; + 8'd218: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_218; + 8'd219: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_219; + 8'd220: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_220; + 8'd221: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_221; + 8'd222: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_222; + 8'd223: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_223; + 8'd224: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_224; + 8'd225: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_225; + 8'd226: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_226; + 8'd227: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_227; + 8'd228: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_228; + 8'd229: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_229; + 8'd230: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_230; + 8'd231: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_231; + 8'd232: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_232; + 8'd233: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_233; + 8'd234: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_234; + 8'd235: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_235; + 8'd236: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_236; + 8'd237: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_237; + 8'd238: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_238; + 8'd239: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_239; + 8'd240: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_240; + 8'd241: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_241; + 8'd242: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_242; + 8'd243: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_243; + 8'd244: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_244; + 8'd245: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_245; + 8'd246: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_246; + 8'd247: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_247; + 8'd248: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_248; + 8'd249: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_249; + 8'd250: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_250; + 8'd251: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_251; + 8'd252: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_252; + 8'd253: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_253; + 8'd254: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_254; + 8'd255: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4725 = + nextAddrPred_valid_255; + endcase + end + always@(x__h111368 or + nextAddrPred_valid_0 or + nextAddrPred_valid_1 or + nextAddrPred_valid_2 or + nextAddrPred_valid_3 or + nextAddrPred_valid_4 or + nextAddrPred_valid_5 or + nextAddrPred_valid_6 or + nextAddrPred_valid_7 or + nextAddrPred_valid_8 or + nextAddrPred_valid_9 or + nextAddrPred_valid_10 or + nextAddrPred_valid_11 or + nextAddrPred_valid_12 or + nextAddrPred_valid_13 or + nextAddrPred_valid_14 or + nextAddrPred_valid_15 or + nextAddrPred_valid_16 or + nextAddrPred_valid_17 or + nextAddrPred_valid_18 or + nextAddrPred_valid_19 or + nextAddrPred_valid_20 or + nextAddrPred_valid_21 or + nextAddrPred_valid_22 or + nextAddrPred_valid_23 or + nextAddrPred_valid_24 or + nextAddrPred_valid_25 or + nextAddrPred_valid_26 or + nextAddrPred_valid_27 or + nextAddrPred_valid_28 or + nextAddrPred_valid_29 or + nextAddrPred_valid_30 or + nextAddrPred_valid_31 or + nextAddrPred_valid_32 or + nextAddrPred_valid_33 or + nextAddrPred_valid_34 or + nextAddrPred_valid_35 or + nextAddrPred_valid_36 or + nextAddrPred_valid_37 or + nextAddrPred_valid_38 or + nextAddrPred_valid_39 or + nextAddrPred_valid_40 or + nextAddrPred_valid_41 or + nextAddrPred_valid_42 or + nextAddrPred_valid_43 or + nextAddrPred_valid_44 or + nextAddrPred_valid_45 or + nextAddrPred_valid_46 or + nextAddrPred_valid_47 or + nextAddrPred_valid_48 or + nextAddrPred_valid_49 or + nextAddrPred_valid_50 or + nextAddrPred_valid_51 or + nextAddrPred_valid_52 or + nextAddrPred_valid_53 or + nextAddrPred_valid_54 or + nextAddrPred_valid_55 or + nextAddrPred_valid_56 or + nextAddrPred_valid_57 or + nextAddrPred_valid_58 or + nextAddrPred_valid_59 or + nextAddrPred_valid_60 or + nextAddrPred_valid_61 or + nextAddrPred_valid_62 or + nextAddrPred_valid_63 or + nextAddrPred_valid_64 or + nextAddrPred_valid_65 or + nextAddrPred_valid_66 or + nextAddrPred_valid_67 or + nextAddrPred_valid_68 or + nextAddrPred_valid_69 or + nextAddrPred_valid_70 or + nextAddrPred_valid_71 or + nextAddrPred_valid_72 or + nextAddrPred_valid_73 or + nextAddrPred_valid_74 or + nextAddrPred_valid_75 or + nextAddrPred_valid_76 or + nextAddrPred_valid_77 or + nextAddrPred_valid_78 or + nextAddrPred_valid_79 or + nextAddrPred_valid_80 or + nextAddrPred_valid_81 or + nextAddrPred_valid_82 or + nextAddrPred_valid_83 or + nextAddrPred_valid_84 or + nextAddrPred_valid_85 or + nextAddrPred_valid_86 or + nextAddrPred_valid_87 or + nextAddrPred_valid_88 or + nextAddrPred_valid_89 or + nextAddrPred_valid_90 or + nextAddrPred_valid_91 or + nextAddrPred_valid_92 or + nextAddrPred_valid_93 or + nextAddrPred_valid_94 or + nextAddrPred_valid_95 or + nextAddrPred_valid_96 or + nextAddrPred_valid_97 or + nextAddrPred_valid_98 or + nextAddrPred_valid_99 or + nextAddrPred_valid_100 or + nextAddrPred_valid_101 or + nextAddrPred_valid_102 or + nextAddrPred_valid_103 or + nextAddrPred_valid_104 or + nextAddrPred_valid_105 or + nextAddrPred_valid_106 or + nextAddrPred_valid_107 or + nextAddrPred_valid_108 or + nextAddrPred_valid_109 or + nextAddrPred_valid_110 or + nextAddrPred_valid_111 or + nextAddrPred_valid_112 or + nextAddrPred_valid_113 or + nextAddrPred_valid_114 or + nextAddrPred_valid_115 or + nextAddrPred_valid_116 or + nextAddrPred_valid_117 or + nextAddrPred_valid_118 or + nextAddrPred_valid_119 or + nextAddrPred_valid_120 or + nextAddrPred_valid_121 or + nextAddrPred_valid_122 or + nextAddrPred_valid_123 or + nextAddrPred_valid_124 or + nextAddrPred_valid_125 or + nextAddrPred_valid_126 or + nextAddrPred_valid_127 or + nextAddrPred_valid_128 or + nextAddrPred_valid_129 or + nextAddrPred_valid_130 or + nextAddrPred_valid_131 or + nextAddrPred_valid_132 or + nextAddrPred_valid_133 or + nextAddrPred_valid_134 or + nextAddrPred_valid_135 or + nextAddrPred_valid_136 or + nextAddrPred_valid_137 or + nextAddrPred_valid_138 or + nextAddrPred_valid_139 or + nextAddrPred_valid_140 or + nextAddrPred_valid_141 or + nextAddrPred_valid_142 or + nextAddrPred_valid_143 or + nextAddrPred_valid_144 or + nextAddrPred_valid_145 or + nextAddrPred_valid_146 or + nextAddrPred_valid_147 or + nextAddrPred_valid_148 or + nextAddrPred_valid_149 or + nextAddrPred_valid_150 or + nextAddrPred_valid_151 or + nextAddrPred_valid_152 or + nextAddrPred_valid_153 or + nextAddrPred_valid_154 or + nextAddrPred_valid_155 or + nextAddrPred_valid_156 or + nextAddrPred_valid_157 or + nextAddrPred_valid_158 or + nextAddrPred_valid_159 or + nextAddrPred_valid_160 or + nextAddrPred_valid_161 or + nextAddrPred_valid_162 or + nextAddrPred_valid_163 or + nextAddrPred_valid_164 or + nextAddrPred_valid_165 or + nextAddrPred_valid_166 or + nextAddrPred_valid_167 or + nextAddrPred_valid_168 or + nextAddrPred_valid_169 or + nextAddrPred_valid_170 or + nextAddrPred_valid_171 or + nextAddrPred_valid_172 or + nextAddrPred_valid_173 or + nextAddrPred_valid_174 or + nextAddrPred_valid_175 or + nextAddrPred_valid_176 or + nextAddrPred_valid_177 or + nextAddrPred_valid_178 or + nextAddrPred_valid_179 or + nextAddrPred_valid_180 or + nextAddrPred_valid_181 or + nextAddrPred_valid_182 or + nextAddrPred_valid_183 or + nextAddrPred_valid_184 or + nextAddrPred_valid_185 or + nextAddrPred_valid_186 or + nextAddrPred_valid_187 or + nextAddrPred_valid_188 or + nextAddrPred_valid_189 or + nextAddrPred_valid_190 or + nextAddrPred_valid_191 or + nextAddrPred_valid_192 or + nextAddrPred_valid_193 or + nextAddrPred_valid_194 or + nextAddrPred_valid_195 or + nextAddrPred_valid_196 or + nextAddrPred_valid_197 or + nextAddrPred_valid_198 or + nextAddrPred_valid_199 or + nextAddrPred_valid_200 or + nextAddrPred_valid_201 or + nextAddrPred_valid_202 or + nextAddrPred_valid_203 or + nextAddrPred_valid_204 or + nextAddrPred_valid_205 or + nextAddrPred_valid_206 or + nextAddrPred_valid_207 or + nextAddrPred_valid_208 or + nextAddrPred_valid_209 or + nextAddrPred_valid_210 or + nextAddrPred_valid_211 or + nextAddrPred_valid_212 or + nextAddrPred_valid_213 or + nextAddrPred_valid_214 or + nextAddrPred_valid_215 or + nextAddrPred_valid_216 or + nextAddrPred_valid_217 or + nextAddrPred_valid_218 or + nextAddrPred_valid_219 or + nextAddrPred_valid_220 or + nextAddrPred_valid_221 or + nextAddrPred_valid_222 or + nextAddrPred_valid_223 or + nextAddrPred_valid_224 or + nextAddrPred_valid_225 or + nextAddrPred_valid_226 or + nextAddrPred_valid_227 or + nextAddrPred_valid_228 or + nextAddrPred_valid_229 or + nextAddrPred_valid_230 or + nextAddrPred_valid_231 or + nextAddrPred_valid_232 or + nextAddrPred_valid_233 or + nextAddrPred_valid_234 or + nextAddrPred_valid_235 or + nextAddrPred_valid_236 or + nextAddrPred_valid_237 or + nextAddrPred_valid_238 or + nextAddrPred_valid_239 or + nextAddrPred_valid_240 or + nextAddrPred_valid_241 or + nextAddrPred_valid_242 or + nextAddrPred_valid_243 or + nextAddrPred_valid_244 or + nextAddrPred_valid_245 or + nextAddrPred_valid_246 or + nextAddrPred_valid_247 or + nextAddrPred_valid_248 or + nextAddrPred_valid_249 or + nextAddrPred_valid_250 or + nextAddrPred_valid_251 or + nextAddrPred_valid_252 or + nextAddrPred_valid_253 or + nextAddrPred_valid_254 or nextAddrPred_valid_255) + begin + case (x__h111368[8:1]) + 8'd0: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_0; + 8'd1: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_1; + 8'd2: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_2; + 8'd3: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_3; + 8'd4: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_4; + 8'd5: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_5; + 8'd6: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_6; + 8'd7: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_7; + 8'd8: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_8; + 8'd9: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_9; + 8'd10: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_10; + 8'd11: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_11; + 8'd12: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_12; + 8'd13: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_13; + 8'd14: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_14; + 8'd15: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_15; + 8'd16: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_16; + 8'd17: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_17; + 8'd18: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_18; + 8'd19: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_19; + 8'd20: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_20; + 8'd21: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_21; + 8'd22: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_22; + 8'd23: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_23; + 8'd24: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_24; + 8'd25: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_25; + 8'd26: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_26; + 8'd27: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_27; + 8'd28: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_28; + 8'd29: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_29; + 8'd30: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_30; + 8'd31: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_31; + 8'd32: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_32; + 8'd33: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_33; + 8'd34: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_34; + 8'd35: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_35; + 8'd36: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_36; + 8'd37: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_37; + 8'd38: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_38; + 8'd39: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_39; + 8'd40: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_40; + 8'd41: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_41; + 8'd42: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_42; + 8'd43: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_43; + 8'd44: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_44; + 8'd45: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_45; + 8'd46: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_46; + 8'd47: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_47; + 8'd48: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_48; + 8'd49: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_49; + 8'd50: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_50; + 8'd51: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_51; + 8'd52: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_52; + 8'd53: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_53; + 8'd54: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_54; + 8'd55: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_55; + 8'd56: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_56; + 8'd57: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_57; + 8'd58: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_58; + 8'd59: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_59; + 8'd60: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_60; + 8'd61: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_61; + 8'd62: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_62; + 8'd63: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_63; + 8'd64: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_64; + 8'd65: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_65; + 8'd66: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_66; + 8'd67: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_67; + 8'd68: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_68; + 8'd69: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_69; + 8'd70: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_70; + 8'd71: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_71; + 8'd72: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_72; + 8'd73: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_73; + 8'd74: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_74; + 8'd75: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_75; + 8'd76: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_76; + 8'd77: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_77; + 8'd78: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_78; + 8'd79: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_79; + 8'd80: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_80; + 8'd81: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_81; + 8'd82: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_82; + 8'd83: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_83; + 8'd84: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_84; + 8'd85: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_85; + 8'd86: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_86; + 8'd87: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_87; + 8'd88: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_88; + 8'd89: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_89; + 8'd90: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_90; + 8'd91: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_91; + 8'd92: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_92; + 8'd93: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_93; + 8'd94: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_94; + 8'd95: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_95; + 8'd96: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_96; + 8'd97: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_97; + 8'd98: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_98; + 8'd99: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_99; + 8'd100: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_100; + 8'd101: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_101; + 8'd102: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_102; + 8'd103: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_103; + 8'd104: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_104; + 8'd105: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_105; + 8'd106: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_106; + 8'd107: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_107; + 8'd108: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_108; + 8'd109: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_109; + 8'd110: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_110; + 8'd111: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_111; + 8'd112: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_112; + 8'd113: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_113; + 8'd114: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_114; + 8'd115: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_115; + 8'd116: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_116; + 8'd117: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_117; + 8'd118: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_118; + 8'd119: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_119; + 8'd120: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_120; + 8'd121: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_121; + 8'd122: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_122; + 8'd123: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_123; + 8'd124: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_124; + 8'd125: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_125; + 8'd126: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_126; + 8'd127: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_127; + 8'd128: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_128; + 8'd129: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_129; + 8'd130: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_130; + 8'd131: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_131; + 8'd132: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_132; + 8'd133: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_133; + 8'd134: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_134; + 8'd135: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_135; + 8'd136: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_136; + 8'd137: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_137; + 8'd138: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_138; + 8'd139: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_139; + 8'd140: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_140; + 8'd141: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_141; + 8'd142: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_142; + 8'd143: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_143; + 8'd144: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_144; + 8'd145: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_145; + 8'd146: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_146; + 8'd147: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_147; + 8'd148: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_148; + 8'd149: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_149; + 8'd150: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_150; + 8'd151: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_151; + 8'd152: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_152; + 8'd153: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_153; + 8'd154: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_154; + 8'd155: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_155; + 8'd156: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_156; + 8'd157: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_157; + 8'd158: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_158; + 8'd159: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_159; + 8'd160: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_160; + 8'd161: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_161; + 8'd162: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_162; + 8'd163: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_163; + 8'd164: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_164; + 8'd165: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_165; + 8'd166: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_166; + 8'd167: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_167; + 8'd168: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_168; + 8'd169: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_169; + 8'd170: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_170; + 8'd171: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_171; + 8'd172: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_172; + 8'd173: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_173; + 8'd174: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_174; + 8'd175: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_175; + 8'd176: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_176; + 8'd177: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_177; + 8'd178: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_178; + 8'd179: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_179; + 8'd180: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_180; + 8'd181: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_181; + 8'd182: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_182; + 8'd183: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_183; + 8'd184: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_184; + 8'd185: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_185; + 8'd186: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_186; + 8'd187: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_187; + 8'd188: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_188; + 8'd189: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_189; + 8'd190: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_190; + 8'd191: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_191; + 8'd192: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_192; + 8'd193: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_193; + 8'd194: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_194; + 8'd195: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_195; + 8'd196: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_196; + 8'd197: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_197; + 8'd198: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_198; + 8'd199: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_199; + 8'd200: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_200; + 8'd201: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_201; + 8'd202: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_202; + 8'd203: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_203; + 8'd204: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_204; + 8'd205: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_205; + 8'd206: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_206; + 8'd207: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_207; + 8'd208: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_208; + 8'd209: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_209; + 8'd210: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_210; + 8'd211: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_211; + 8'd212: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_212; + 8'd213: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_213; + 8'd214: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_214; + 8'd215: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_215; + 8'd216: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_216; + 8'd217: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_217; + 8'd218: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_218; + 8'd219: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_219; + 8'd220: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_220; + 8'd221: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_221; + 8'd222: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_222; + 8'd223: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_223; + 8'd224: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_224; + 8'd225: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_225; + 8'd226: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_226; + 8'd227: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_227; + 8'd228: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_228; + 8'd229: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_229; + 8'd230: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_230; + 8'd231: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_231; + 8'd232: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_232; + 8'd233: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_233; + 8'd234: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_234; + 8'd235: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_235; + 8'd236: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_236; + 8'd237: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_237; + 8'd238: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_238; + 8'd239: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_239; + 8'd240: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_240; + 8'd241: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_241; + 8'd242: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_242; + 8'd243: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_243; + 8'd244: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_244; + 8'd245: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_245; + 8'd246: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_246; + 8'd247: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_247; + 8'd248: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_248; + 8'd249: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_249; + 8'd250: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_250; + 8'd251: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_251; + 8'd252: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_252; + 8'd253: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_253; + 8'd254: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = + nextAddrPred_valid_254; + 8'd255: + SEL_ARR_nextAddrPred_valid_0_read__422_nextAdd_ETC___d4737 = nextAddrPred_valid_255; endcase end @@ -15446,17 +21205,17 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 = - !f22f3_data_0[74]; + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4929 = + f22f3_data_0[3:0]; 2'd1: - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 = - !f22f3_data_1[74]; + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4929 = + f22f3_data_1[3:0]; 2'd2: - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 = - !f22f3_data_2[74]; + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4929 = + f22f3_data_2[3:0]; 2'd3: - SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 = - !f22f3_data_3[74]; + SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f22f3_ETC___d4929 = + f22f3_data_3[3:0]; endcase end always@(f22f3_deqP or @@ -15464,16 +21223,34 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491 = + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4937 = + f22f3_data_0[4]; + 2'd1: + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4937 = + f22f3_data_1[4]; + 2'd2: + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4937 = + f22f3_data_2[4]; + 2'd3: + SEL_ARR_f22f3_data_0_920_BIT_4_932_f22f3_data__ETC___d4937 = + f22f3_data_3[4]; + endcase + end + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4946 = f22f3_data_0[5]; 2'd1: - SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491 = + SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4946 = f22f3_data_1[5]; 2'd2: - SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491 = + SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4946 = f22f3_data_2[5]; 2'd3: - SEL_ARR_f22f3_data_0_470_BIT_5_486_f22f3_data__ETC___d3491 = + SEL_ARR_f22f3_data_0_920_BIT_5_941_f22f3_data__ETC___d4946 = f22f3_data_3[5]; endcase end @@ -15482,406 +21259,17 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3501 = - f22f3_data_0[4]; + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 = + !f22f3_data_0[76]; 2'd1: - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3501 = - f22f3_data_1[4]; + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 = + !f22f3_data_1[76]; 2'd2: - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3501 = - f22f3_data_2[4]; + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 = + !f22f3_data_2[76]; 2'd3: - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3501 = - f22f3_data_3[4]; - endcase - end - always@(f22f3_data_0) - begin - case (f22f3_data_0[73:70]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 = - f22f3_data_0[73:70]; - 4'd11: - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 = 4'd10; - 4'd12: - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 = 4'd11; - 4'd13: - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 = 4'd12; - default: IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 = - 4'd13; - endcase - end - always@(f22f3_data_1) - begin - case (f22f3_data_1[73:70]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 = - f22f3_data_1[73:70]; - 4'd11: - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 = 4'd10; - 4'd12: - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 = 4'd11; - 4'd13: - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 = 4'd12; - default: IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 = - 4'd13; - endcase - end - always@(f22f3_data_2) - begin - case (f22f3_data_2[73:70]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 = - f22f3_data_2[73:70]; - 4'd11: - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 = 4'd10; - 4'd12: - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 = 4'd11; - 4'd13: - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 = 4'd12; - default: IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 = - 4'd13; - endcase - end - always@(f22f3_data_3) - begin - case (f22f3_data_3[73:70]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 = - f22f3_data_3[73:70]; - 4'd11: - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 = 4'd10; - 4'd12: - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 = 4'd11; - 4'd13: - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 = 4'd12; - default: IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 = - 4'd13; - endcase - end - always@(f22f3_deqP or - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 or - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 or - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 or - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 = - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 == - 4'd0; - 2'd1: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 = - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 == - 4'd0; - 2'd2: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 = - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 == - 4'd0; - 2'd3: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 = - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 == - 4'd0; - endcase - end - always@(f22f3_deqP or - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 or - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 or - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 or - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 = - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 == - 4'd1; - 2'd1: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 = - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 == - 4'd1; - 2'd2: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 = - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 == - 4'd1; - 2'd3: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697 = - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 == - 4'd1; - endcase - end - always@(f22f3_deqP or - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 or - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 or - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 or - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 = - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 == - 4'd2; - 2'd1: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 = - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 == - 4'd2; - 2'd2: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 = - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 == - 4'd2; - 2'd3: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3709 = - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 == - 4'd2; - endcase - end - always@(f22f3_deqP or - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 or - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 or - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 or - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 = - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 == - 4'd3; - 2'd1: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 = - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 == - 4'd3; - 2'd2: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 = - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 == - 4'd3; - 2'd3: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3722 = - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 == - 4'd3; - endcase - end - always@(f22f3_deqP or - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 or - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 or - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 or - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 = - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 == - 4'd4; - 2'd1: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 = - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 == - 4'd4; - 2'd2: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 = - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 == - 4'd4; - 2'd3: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3736 = - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 == - 4'd4; - endcase - end - always@(f22f3_deqP or - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 or - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 or - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 or - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 = - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 == - 4'd5; - 2'd1: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 = - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 == - 4'd5; - 2'd2: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 = - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 == - 4'd5; - 2'd3: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3751 = - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 == - 4'd5; - endcase - end - always@(f22f3_deqP or - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 or - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 or - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 or - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767 = - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 == - 4'd6; - 2'd1: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767 = - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 == - 4'd6; - 2'd2: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767 = - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 == - 4'd6; - 2'd3: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3767 = - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 == - 4'd6; - endcase - end - always@(f22f3_deqP or - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 or - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 or - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 or - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3784 = - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 == - 4'd7; - 2'd1: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3784 = - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 == - 4'd7; - 2'd2: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3784 = - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 == - 4'd7; - 2'd3: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3784 = - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 == - 4'd7; - endcase - end - always@(f22f3_deqP or - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 or - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 or - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 or - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3802 = - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 == - 4'd8; - 2'd1: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3802 = - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 == - 4'd8; - 2'd2: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3802 = - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 == - 4'd8; - 2'd3: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3802 = - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 == - 4'd8; - endcase - end - always@(f22f3_deqP or - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 or - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 or - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 or - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3821 = - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 == - 4'd9; - 2'd1: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3821 = - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 == - 4'd9; - 2'd2: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3821 = - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 == - 4'd9; - 2'd3: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3821 = - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 == - 4'd9; - endcase - end - always@(f22f3_deqP or - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 or - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 or - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 or - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3841 = - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 == - 4'd10; - 2'd1: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3841 = - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 == - 4'd10; - 2'd2: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3841 = - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 == - 4'd10; - 2'd3: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3841 = - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 == - 4'd10; - endcase - end - always@(f22f3_deqP or - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 or - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 or - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 or - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3862 = - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 == - 4'd11; - 2'd1: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3862 = - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 == - 4'd11; - 2'd2: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3862 = - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 == - 4'd11; - 2'd3: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3862 = - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 == - 4'd11; - endcase - end - always@(f22f3_deqP or - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 or - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 or - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 or - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3884 = - IF_f22f3_data_0_470_BITS_73_TO_70_573_EQ_0_574_ETC___d3599 == - 4'd12; - 2'd1: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3884 = - IF_f22f3_data_1_473_BITS_73_TO_70_601_EQ_0_602_ETC___d3627 == - 4'd12; - 2'd2: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3884 = - IF_f22f3_data_2_476_BITS_73_TO_70_629_EQ_0_630_ETC___d3655 == - 4'd12; - 2'd3: - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3884 = - IF_f22f3_data_3_479_BITS_73_TO_70_657_EQ_0_658_ETC___d3683 == - 4'd12; + SEL_ARR_NOT_f22f3_data_0_920_BIT_76_968_969_NO_ETC___d4977 = + !f22f3_data_3[76]; endcase end always@(f22f3_deqP or @@ -15889,17 +21277,17 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_NOT_f22f3_data_0_470_BIT_5_486_924_NOT_ETC___d3929 = - !f22f3_data_0[5]; + SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003 = + f22f3_data_0[6]; 2'd1: - SEL_ARR_NOT_f22f3_data_0_470_BIT_5_486_924_NOT_ETC___d3929 = - !f22f3_data_1[5]; + SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003 = + f22f3_data_1[6]; 2'd2: - SEL_ARR_NOT_f22f3_data_0_470_BIT_5_486_924_NOT_ETC___d3929 = - !f22f3_data_2[5]; + SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003 = + f22f3_data_2[6]; 2'd3: - SEL_ARR_NOT_f22f3_data_0_470_BIT_5_486_924_NOT_ETC___d3929 = - !f22f3_data_3[5]; + SEL_ARR_f22f3_data_0_920_BIT_6_998_f22f3_data__ETC___d5003 = + f22f3_data_3[6]; endcase end always@(f22f3_deqP or @@ -15907,130 +21295,297 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_NOT_f22f3_data_0_470_BIT_4_496_937_NOT_ETC___d3942 = - !f22f3_data_0[4]; + SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 = + !f22f3_data_0[206]; 2'd1: - SEL_ARR_NOT_f22f3_data_0_470_BIT_4_496_937_NOT_ETC___d3942 = - !f22f3_data_1[4]; + SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 = + !f22f3_data_1[206]; 2'd2: - SEL_ARR_NOT_f22f3_data_0_470_BIT_4_496_937_NOT_ETC___d3942 = - !f22f3_data_2[4]; + SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 = + !f22f3_data_2[206]; 2'd3: - SEL_ARR_NOT_f22f3_data_0_470_BIT_4_496_937_NOT_ETC___d3942 = - !f22f3_data_3[4]; + SEL_ARR_NOT_f22f3_data_0_920_BIT_206_294_295_N_ETC___d5303 = + !f22f3_data_3[206]; endcase end - always@(j__h119769 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4015 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4019 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4023 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4026) + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin - case (j__h119769) - 3'd0: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4015; - 3'd1: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4019; - 3'd2: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4023; - 3'd3: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4026; - default: SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4028 = - 16'b1010101010101010 /* unspecified value */ ; + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_205_TO_77_682_f2_ETC___d6687 = + f22f3_data_0[205:77]; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_205_TO_77_682_f2_ETC___d6687 = + f22f3_data_1[205:77]; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_205_TO_77_682_f2_ETC___d6687 = + f22f3_data_2[205:77]; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_205_TO_77_682_f2_ETC___d6687 = + f22f3_data_3[205:77]; endcase end - always@(IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4042 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4015 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4019 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4023 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4026) + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin - case (IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4042) - 3'd0: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4015; - 3'd1: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4019; - 3'd2: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4023; - 3'd3: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4026; - default: SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4044 = - 16'b1010101010101010 /* unspecified value */ ; + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6773 = + f22f3_data_0[75:71] == 5'd0; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6773 = + f22f3_data_1[75:71] == 5'd0; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6773 = + f22f3_data_2[75:71] == 5'd0; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6773 = + f22f3_data_3[75:71] == 5'd0; endcase end - always@(IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4047 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4015 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4019 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4023 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4026) + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin - case (IF_IF_IF_rg_pending_straddle_514_THEN_IF_SEL_A_ETC___d4047) - 3'd0: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4051 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4015; - 3'd1: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4051 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4019; - 3'd2: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4051 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4023; - 3'd3: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4051 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4026; - default: SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4051 = - 16'b1010101010101010 /* unspecified value */ ; + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6783 = + f22f3_data_0[75:71] == 5'd1; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6783 = + f22f3_data_1[75:71] == 5'd1; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6783 = + f22f3_data_2[75:71] == 5'd1; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6783 = + f22f3_data_3[75:71] == 5'd1; endcase end - always@(y_avValue_fst__h122004 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4015 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4019 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4023 or - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4026) + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin - case (y_avValue_fst__h122004) - 3'd0: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4344 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4015; - 3'd1: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4344 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4019; - 3'd2: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4344 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4023; - 3'd3: - SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4344 = - IF_rg_pending_straddle_514_THEN_IF_SEL_ARR_f22_ETC___d4026; - default: SEL_ARR_IF_rg_pending_straddle_514_THEN_IF_SEL_ETC___d4344 = - 16'b1010101010101010 /* unspecified value */ ; + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6793 = + f22f3_data_0[75:71] == 5'd2; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6793 = + f22f3_data_1[75:71] == 5'd2; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6793 = + f22f3_data_2[75:71] == 5'd2; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6793 = + f22f3_data_3[75:71] == 5'd2; endcase end - always@(f32d_deqP or f32d_data_0 or f32d_data_1) + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin - case (f32d_deqP) + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6803 = + f22f3_data_0[75:71] == 5'd3; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6803 = + f22f3_data_1[75:71] == 5'd3; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6803 = + f22f3_data_2[75:71] == 5'd3; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6803 = + f22f3_data_3[75:71] == 5'd3; + endcase + end + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6813 = + f22f3_data_0[75:71] == 5'd4; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6813 = + f22f3_data_1[75:71] == 5'd4; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6813 = + f22f3_data_2[75:71] == 5'd4; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6813 = + f22f3_data_3[75:71] == 5'd4; + endcase + end + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6823 = + f22f3_data_0[75:71] == 5'd5; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6823 = + f22f3_data_1[75:71] == 5'd5; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6823 = + f22f3_data_2[75:71] == 5'd5; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6823 = + f22f3_data_3[75:71] == 5'd5; + endcase + end + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6843 = + f22f3_data_0[75:71] == 5'd7; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6843 = + f22f3_data_1[75:71] == 5'd7; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6843 = + f22f3_data_2[75:71] == 5'd7; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6843 = + f22f3_data_3[75:71] == 5'd7; + endcase + end + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6833 = + f22f3_data_0[75:71] == 5'd6; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6833 = + f22f3_data_1[75:71] == 5'd6; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6833 = + f22f3_data_2[75:71] == 5'd6; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6833 = + f22f3_data_3[75:71] == 5'd6; + endcase + end + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6853 = + f22f3_data_0[75:71] == 5'd8; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6853 = + f22f3_data_1[75:71] == 5'd8; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6853 = + f22f3_data_2[75:71] == 5'd8; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6853 = + f22f3_data_3[75:71] == 5'd8; + endcase + end + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6863 = + f22f3_data_0[75:71] == 5'd9; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6863 = + f22f3_data_1[75:71] == 5'd9; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6863 = + f22f3_data_2[75:71] == 5'd9; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6863 = + f22f3_data_3[75:71] == 5'd9; + endcase + end + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6883 = + f22f3_data_0[75:71] == 5'd12; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6883 = + f22f3_data_1[75:71] == 5'd12; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6883 = + f22f3_data_2[75:71] == 5'd12; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6883 = + f22f3_data_3[75:71] == 5'd12; + endcase + end + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6873 = + f22f3_data_0[75:71] == 5'd11; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6873 = + f22f3_data_1[75:71] == 5'd11; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6873 = + f22f3_data_2[75:71] == 5'd11; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6873 = + f22f3_data_3[75:71] == 5'd11; + endcase + end + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6893 = + f22f3_data_0[75:71] == 5'd13; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6893 = + f22f3_data_1[75:71] == 5'd13; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6893 = + f22f3_data_2[75:71] == 5'd13; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6893 = + f22f3_data_3[75:71] == 5'd13; + endcase + end + always@(f22f3_deqP or + f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) + begin + case (f22f3_deqP) + 2'd0: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6903 = + f22f3_data_0[75:71] == 5'd15; + 2'd1: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6903 = + f22f3_data_1[75:71] == 5'd15; + 2'd2: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6903 = + f22f3_data_2[75:71] == 5'd15; + 2'd3: + SEL_ARR_f22f3_data_0_920_BITS_75_TO_71_764_EQ__ETC___d6903 = + f22f3_data_3[75:71] == 5'd15; + endcase + end + always@(instdata_deqP_rl or instdata_data_0 or instdata_data_1) + begin + case (instdata_deqP_rl) 1'd0: - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4683 = - f32d_data_0[3:0]; - 1'd1: - SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4683 = - f32d_data_1[3:0]; - endcase - end - always@(n__read__h142595 or instdata_data_0 or instdata_data_1) - begin - case (n__read__h142595) - 1'd0: - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 = + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 = instdata_data_0[65:64]; 1'd1: - SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 = + SEL_ARR_instdata_data_0_987_BITS_65_TO_64_988__ETC___d6992 = instdata_data_1[65:64]; endcase end @@ -16038,56 +21593,56 @@ module mkFetchStage(CLK, begin case (f32d_deqP) 1'd0: - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4700 = + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6997 = f32d_data_0[4]; 1'd1: - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4700 = + SEL_ARR_f32d_data_0_979_BIT_4_994_f32d_data_1__ETC___d6997 = f32d_data_1[4]; endcase end - always@(n__read__h142595 or instdata_data_0 or instdata_data_1) + always@(instdata_deqP_rl or instdata_data_0 or instdata_data_1) begin - case (n__read__h142595) + case (instdata_deqP_rl) 1'd0: - SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 = - instdata_data_0[195:194]; + SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 = + instdata_data_0[260:259]; 1'd1: - SEL_ARR_instdata_data_0_686_BITS_195_TO_194_71_ETC___d4713 = - instdata_data_1[195:194]; + SEL_ARR_instdata_data_0_987_BITS_260_TO_259_00_ETC___d7009 = + instdata_data_1[260:259]; endcase end always@(f32d_deqP or f32d_data_0 or f32d_data_1) begin case (f32d_deqP) 1'd0: - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719 = - f32d_data_0[267]; + SEL_ARR_f32d_data_0_979_BIT_334_011_f32d_data__ETC___d7014 = + f32d_data_0[334]; 1'd1: - SEL_ARR_f32d_data_0_678_BIT_267_716_f32d_data__ETC___d4719 = - f32d_data_1[267]; + SEL_ARR_f32d_data_0_979_BIT_334_011_f32d_data__ETC___d7014 = + f32d_data_1[334]; endcase end - always@(x__h64600 or + always@(x__h60535 or out_fifo_internalFifos_0$FULL_N or out_fifo_internalFifos_1$FULL_N) begin - case (x__h64600) + case (x__h60535) 1'd0: - CASE_x4600_0_out_fifo_internalFifos_0FULL_N_1_ETC__q2 = + CASE_x0535_0_out_fifo_internalFifos_0FULL_N_1_ETC__q3 = out_fifo_internalFifos_0$FULL_N; 1'd1: - CASE_x4600_0_out_fifo_internalFifos_0FULL_N_1_ETC__q2 = + CASE_x0535_0_out_fifo_internalFifos_0FULL_N_1_ETC__q3 = out_fifo_internalFifos_1$FULL_N; endcase end - always@(x__h54856 or + always@(out_fifo_enqueueFifo_rl or out_fifo_internalFifos_0$FULL_N or out_fifo_internalFifos_1$FULL_N) begin - case (x__h54856) + case (out_fifo_enqueueFifo_rl) 1'd0: - CASE_x4856_0_out_fifo_internalFifos_0FULL_N_1_ETC__q3 = + CASE_out_fifo_enqueueFifo_rl_0_out_fifo_intern_ETC__q4 = out_fifo_internalFifos_0$FULL_N; 1'd1: - CASE_x4856_0_out_fifo_internalFifos_0FULL_N_1_ETC__q3 = + CASE_out_fifo_enqueueFifo_rl_0_out_fifo_intern_ETC__q4 = out_fifo_internalFifos_1$FULL_N; endcase end @@ -16095,3096 +21650,6615 @@ module mkFetchStage(CLK, begin case (f32d_deqP) 1'd0: - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 = + SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 = !f32d_data_0[74]; 1'd1: - SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759_NOT_ETC___d4763 = + SEL_ARR_NOT_f32d_data_0_979_BIT_74_032_033_NOT_ETC___d7037 = !f32d_data_1[74]; endcase end - always@(n__read__h142595 or instdata_data_0 or instdata_data_1) + always@(instdata_deqP_rl or instdata_data_0 or instdata_data_1) begin - case (n__read__h142595) + case (instdata_deqP_rl) 1'd0: - SEL_ARR_instdata_data_0_686_BITS_63_TO_32_751__ETC___d4754 = - instdata_data_0[63:32]; + SEL_ARR_instdata_data_0_987_BITS_389_TO_261_42_ETC___d7425 = + instdata_data_0[389:261]; 1'd1: - SEL_ARR_instdata_data_0_686_BITS_63_TO_32_751__ETC___d4754 = - instdata_data_1[63:32]; + SEL_ARR_instdata_data_0_987_BITS_389_TO_261_42_ETC___d7425 = + instdata_data_1[389:261]; endcase end - always@(n__read__h142595 or instdata_data_0 or instdata_data_1) + always@(instdata_deqP_rl or instdata_data_0 or instdata_data_1) begin - case (n__read__h142595) + case (instdata_deqP_rl) 1'd0: - SEL_ARR_instdata_data_0_686_BITS_259_TO_196_99_ETC___d4994 = - instdata_data_0[259:196]; + SEL_ARR_instdata_data_0_987_BITS_226_TO_195_55_ETC___d7556 = + instdata_data_0[226:195]; 1'd1: - SEL_ARR_instdata_data_0_686_BITS_259_TO_196_99_ETC___d4994 = - instdata_data_1[259:196]; + SEL_ARR_instdata_data_0_987_BITS_226_TO_195_55_ETC___d7556 = + instdata_data_1[226:195]; endcase end - always@(f32d_data_0) + always@(instdata_deqP_rl or instdata_data_0 or instdata_data_1) begin - case (f32d_data_0[73:70]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 = - f32d_data_0[73:70]; - 4'd11: - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 = 4'd10; - 4'd12: - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 = 4'd11; - 4'd13: - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 = 4'd12; - default: IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 = - 4'd13; - endcase - end - always@(f32d_data_1) - begin - case (f32d_data_1[73:70]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 = - f32d_data_1[73:70]; - 4'd11: - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 = 4'd10; - 4'd12: - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 = 4'd11; - 4'd13: - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 = 4'd12; - default: IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 = - 4'd13; - endcase - end - always@(n__read__h142595 or instdata_data_0 or instdata_data_1) - begin - case (n__read__h142595) + case (instdata_deqP_rl) 1'd0: - SEL_ARR_instdata_data_0_686_BITS_193_TO_162_16_ETC___d5171 = - instdata_data_0[193:162]; - 1'd1: - SEL_ARR_instdata_data_0_686_BITS_193_TO_162_16_ETC___d5171 = - instdata_data_1[193:162]; - endcase - end - always@(n__read__h142595 or instdata_data_0 or instdata_data_1) - begin - case (n__read__h142595) - 1'd0: - SEL_ARR_instdata_data_0_686_BITS_161_TO_130_17_ETC___d5179 = - instdata_data_0[161:130]; - 1'd1: - SEL_ARR_instdata_data_0_686_BITS_161_TO_130_17_ETC___d5179 = - instdata_data_1[161:130]; - endcase - end - always@(n__read__h142595 or instdata_data_0 or instdata_data_1) - begin - case (n__read__h142595) - 1'd0: - SEL_ARR_instdata_data_0_686_BITS_31_TO_0_764_i_ETC___d4767 = + SEL_ARR_instdata_data_0_987_BITS_31_TO_0_038_i_ETC___d7041 = instdata_data_0[31:0]; 1'd1: - SEL_ARR_instdata_data_0_686_BITS_31_TO_0_764_i_ETC___d4767 = + SEL_ARR_instdata_data_0_987_BITS_31_TO_0_038_i_ETC___d7041 = instdata_data_1[31:0]; endcase end - always@(decode___d5180) + always@(decode___d7047) begin - case (decode___d5180[77:75]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_decode_180_BITS_77_TO_75_0_decode_180_BIT_ETC__q4 = - decode___d5180[77:75]; - default: CASE_decode_180_BITS_77_TO_75_0_decode_180_BIT_ETC__q4 = 3'd7; + case (decode___d7047[134:131]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_decode_047_BITS_134_TO_131_176_EQ_6_188_OR__ETC___d7197 = + decode___d7047[134:131]; + default: IF_decode_047_BITS_134_TO_131_176_EQ_6_188_OR__ETC___d7197 = + 4'd11; endcase end - always@(decode___d5180 or - CASE_decode_180_BITS_77_TO_75_0_decode_180_BIT_ETC__q4) + always@(decode___d7047) begin - case (decode___d5180[94:92]) + case (decode___d7047[130:128]) + 3'd2, 3'd3: + IF_decode_047_BITS_130_TO_128_219_EQ_2_223_OR__ETC___d7226 = + decode___d7047[130:128]; + default: IF_decode_047_BITS_130_TO_128_219_EQ_2_223_OR__ETC___d7226 = + 3'd4; + endcase + end + always@(IF_decode_047_BITS_130_TO_128_219_EQ_2_223_OR__ETC___d7226) + begin + case (IF_decode_047_BITS_130_TO_128_219_EQ_2_223_OR__ETC___d7226) + 3'd2, 3'd3: + CASE_IF_decode_047_BITS_130_TO_128_219_EQ_2_22_ETC__q5 = + IF_decode_047_BITS_130_TO_128_219_EQ_2_223_OR__ETC___d7226; + default: CASE_IF_decode_047_BITS_130_TO_128_219_EQ_2_22_ETC__q5 = 3'd4; + endcase + end + always@(IF_decode_047_BITS_134_TO_131_176_EQ_6_188_OR__ETC___d7197) + begin + case (IF_decode_047_BITS_134_TO_131_176_EQ_6_188_OR__ETC___d7197) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + CASE_IF_decode_047_BITS_134_TO_131_176_EQ_6_18_ETC__q6 = + IF_decode_047_BITS_134_TO_131_176_EQ_6_188_OR__ETC___d7197; + default: CASE_IF_decode_047_BITS_134_TO_131_176_EQ_6_18_ETC__q6 = 4'd11; + endcase + end + always@(decode___d7558) + begin + case (decode___d7558[134:131]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_decode_558_BITS_134_TO_131_687_EQ_6_699_OR__ETC___d7708 = + decode___d7558[134:131]; + default: IF_decode_558_BITS_134_TO_131_687_EQ_6_699_OR__ETC___d7708 = + 4'd11; + endcase + end + always@(decode___d7558) + begin + case (decode___d7558[130:128]) + 3'd2, 3'd3: + IF_decode_558_BITS_130_TO_128_730_EQ_2_734_OR__ETC___d7737 = + decode___d7558[130:128]; + default: IF_decode_558_BITS_130_TO_128_730_EQ_2_734_OR__ETC___d7737 = + 3'd4; + endcase + end + always@(IF_decode_558_BITS_130_TO_128_730_EQ_2_734_OR__ETC___d7737) + begin + case (IF_decode_558_BITS_130_TO_128_730_EQ_2_734_OR__ETC___d7737) + 3'd2, 3'd3: + CASE_IF_decode_558_BITS_130_TO_128_730_EQ_2_73_ETC__q7 = + IF_decode_558_BITS_130_TO_128_730_EQ_2_734_OR__ETC___d7737; + default: CASE_IF_decode_558_BITS_130_TO_128_730_EQ_2_73_ETC__q7 = 3'd4; + endcase + end + always@(IF_decode_558_BITS_134_TO_131_687_EQ_6_699_OR__ETC___d7708) + begin + case (IF_decode_558_BITS_134_TO_131_687_EQ_6_699_OR__ETC___d7708) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + CASE_IF_decode_558_BITS_134_TO_131_687_EQ_6_69_ETC__q8 = + IF_decode_558_BITS_134_TO_131_687_EQ_6_699_OR__ETC___d7708; + default: CASE_IF_decode_558_BITS_134_TO_131_687_EQ_6_69_ETC__q8 = 4'd11; + endcase + end + always@(decode___d7558) + begin + case (decode___d7558[140:138]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_decode_558_BITS_140_TO_138_0_decode_558_B_ETC__q9 = + decode___d7558[140:138]; + default: CASE_decode_558_BITS_140_TO_138_0_decode_558_B_ETC__q9 = 3'd7; + endcase + end + always@(decode___d7558 or + CASE_decode_558_BITS_140_TO_138_0_decode_558_B_ETC__q9) + begin + case (decode___d7558[166:164]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_decode_180_BITS_94_TO_92_0_decode_180_BIT_ETC__q5 = - decode___d5180[94:74]; + CASE_decode_558_BITS_166_TO_164_0_decode_558_B_ETC__q10 = + decode___d7558[166:137]; 3'd4: - CASE_decode_180_BITS_94_TO_92_0_decode_180_BIT_ETC__q5 = - { decode___d5180[94:92], - 9'h0AA, - decode___d5180[82:78], - CASE_decode_180_BITS_77_TO_75_0_decode_180_BIT_ETC__q4, - decode___d5180[74] }; - default: CASE_decode_180_BITS_94_TO_92_0_decode_180_BIT_ETC__q5 = - 21'd1485482; + CASE_decode_558_BITS_166_TO_164_0_decode_558_B_ETC__q10 = + { decode___d7558[166:164], + 18'h2AAAA, + decode___d7558[145:141], + CASE_decode_558_BITS_140_TO_138_0_decode_558_B_ETC__q9, + decode___d7558[137] }; + default: CASE_decode_558_BITS_166_TO_164_0_decode_558_B_ETC__q10 = + 30'd715827882; endcase end - always@(decode___d5180) + always@(decode___d7558 or + IF_decode_558_BITS_134_TO_131_687_EQ_0_688_OR__ETC___d7781) begin - case (decode___d5180[72:61]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_decode_180_BITS_72_TO_61_1_decode_180_BIT_ETC__q6 = - decode___d5180[72:61]; - default: CASE_decode_180_BITS_72_TO_61_1_decode_180_BIT_ETC__q6 = - 12'd2303; - endcase - end - always@(decode___d4768) - begin - case (decode___d4768[77:75]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_decode_768_BITS_77_TO_75_0_decode_768_BIT_ETC__q7 = - decode___d4768[77:75]; - default: CASE_decode_768_BITS_77_TO_75_0_decode_768_BIT_ETC__q7 = 3'd7; - endcase - end - always@(decode___d4768 or - CASE_decode_768_BITS_77_TO_75_0_decode_768_BIT_ETC__q7) - begin - case (decode___d4768[94:92]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_decode_768_BITS_94_TO_92_0_decode_768_BIT_ETC__q8 = - decode___d4768[94:74]; - 3'd4: - CASE_decode_768_BITS_94_TO_92_0_decode_768_BIT_ETC__q8 = - { decode___d4768[94:92], - 9'h0AA, - decode___d4768[82:78], - CASE_decode_768_BITS_77_TO_75_0_decode_768_BIT_ETC__q7, - decode___d4768[74] }; - default: CASE_decode_768_BITS_94_TO_92_0_decode_768_BIT_ETC__q8 = - 21'd1485482; - endcase - end - always@(decode___d4768) - begin - case (decode___d4768[72:61]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_decode_768_BITS_72_TO_61_1_decode_768_BIT_ETC__q9 = - decode___d4768[72:61]; - default: CASE_decode_768_BITS_72_TO_61_1_decode_768_BIT_ETC__q9 = - 12'd2303; - endcase - end - always@(SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 or - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 or - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5161 or - decode_epoch) - begin - case (SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694) + case (decode___d7558[136:135]) 2'd0: - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5164 = - decode_epoch; - 2'd3: - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5164 = - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 ^ - decode_epoch; - default: IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5164 = - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 ? - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5161 : - decode_epoch; - endcase - end - always@(SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694 or - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 or - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5460 or - decode_epoch or - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4700) - begin - case (SEL_ARR_instdata_data_0_686_BITS_65_TO_64_687__ETC___d4694) - 2'd0: - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5463 = - !decode_epoch; - 2'd3: - IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5463 = - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 ? - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4700 : - !decode_epoch; - default: IF_SEL_ARR_instdata_data_0_686_BITS_65_TO_64_6_ETC___d5463 = - SEL_ARR_f32d_data_0_678_BIT_4_697_f32d_data_1__ETC___d4701 ? - IF_SEL_ARR_NOT_f32d_data_0_678_BIT_74_758_759__ETC___d5460 : - !decode_epoch; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q10 = - out_fifo_internalFifos_0$D_OUT[183]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q10 = - out_fifo_internalFifos_1$D_OUT[183]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q11 = - out_fifo_internalFifos_0$D_OUT[182]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q11 = - out_fifo_internalFifos_1$D_OUT[182]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q12 = - out_fifo_internalFifos_0$D_OUT[181]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q12 = - out_fifo_internalFifos_1$D_OUT[181]; - endcase - end - always@(out_fifo_internalFifos_0$D_OUT) - begin - case (out_fifo_internalFifos_0$D_OUT[177:175]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 = - out_fifo_internalFifos_0$D_OUT[177:175]; - default: IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 = - 3'd5; - endcase - end - always@(out_fifo_internalFifos_1$D_OUT) - begin - case (out_fifo_internalFifos_1$D_OUT[177:175]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683 = - out_fifo_internalFifos_1$D_OUT[177:175]; - default: IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683 = - 3'd5; - endcase - end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 or - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q13 = - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 == - 3'd3; - 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q13 = - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683 == - 3'd3; - endcase - end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 or - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q14 = - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 == - 3'd4; - 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q14 = - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683 == - 3'd4; - endcase - end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 or - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q15 = - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 == - 3'd2; - 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q15 = - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683 == - 3'd2; - endcase - end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 or - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q16 = - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 == - 3'd1; - 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q16 = - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683 == - 3'd1; - endcase - end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 or - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q17 = - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 == - 3'd0; - 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q17 = - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683 == - 3'd0; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5635 = - out_fifo_internalFifos_0$D_OUT[174]; - 1'd1: - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5635 = - out_fifo_internalFifos_1$D_OUT[174]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = - out_fifo_internalFifos_0$D_OUT[182:178]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = - out_fifo_internalFifos_1$D_OUT[182:178]; - endcase - end - always@(out_fifo_internalFifos_0$D_OUT) - begin - case (out_fifo_internalFifos_0$D_OUT[67:64]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 = - out_fifo_internalFifos_0$D_OUT[67:64]; - 4'd11: - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 = 4'd10; - 4'd12: - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 = 4'd11; - 4'd13: - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 = 4'd12; - default: IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 = - 4'd13; - endcase - end - always@(out_fifo_internalFifos_1$D_OUT) - begin - case (out_fifo_internalFifos_1$D_OUT[67:64]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 = - out_fifo_internalFifos_1$D_OUT[67:64]; - 4'd11: - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 = 4'd10; - 4'd12: - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 = 4'd11; - 4'd13: - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 = 4'd12; - default: IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 = - 4'd13; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = - out_fifo_internalFifos_0$D_OUT[183]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = - out_fifo_internalFifos_1$D_OUT[183]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = - out_fifo_internalFifos_0$D_OUT[182]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = - out_fifo_internalFifos_1$D_OUT[182]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21 = - out_fifo_internalFifos_0$D_OUT[181]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21 = - out_fifo_internalFifos_1$D_OUT[181]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 = - out_fifo_internalFifos_0$D_OUT[180]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 = - out_fifo_internalFifos_1$D_OUT[180]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q23 = - out_fifo_internalFifos_0$D_OUT[179]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q23 = - out_fifo_internalFifos_1$D_OUT[179]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q24 = - out_fifo_internalFifos_0$D_OUT[180]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q24 = - out_fifo_internalFifos_1$D_OUT[180]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q25 = - out_fifo_internalFifos_0$D_OUT[179]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q25 = - out_fifo_internalFifos_1$D_OUT[179]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q26 = - out_fifo_internalFifos_0$D_OUT[178]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q26 = - out_fifo_internalFifos_1$D_OUT[178]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q27 = - out_fifo_internalFifos_0$D_OUT[177]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q27 = - out_fifo_internalFifos_1$D_OUT[177]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q28 = - out_fifo_internalFifos_0$D_OUT[178]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q28 = - out_fifo_internalFifos_1$D_OUT[178]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q29 = - out_fifo_internalFifos_0$D_OUT[177]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q29 = - out_fifo_internalFifos_1$D_OUT[177]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6165 = - out_fifo_internalFifos_0$D_OUT[176]; - 1'd1: - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6165 = - out_fifo_internalFifos_1$D_OUT[176]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q30 = - out_fifo_internalFifos_0$D_OUT[178:177]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q30 = - out_fifo_internalFifos_1$D_OUT[178:177]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q31 = - out_fifo_internalFifos_0$D_OUT[175:174]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q31 = - out_fifo_internalFifos_1$D_OUT[175:174]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5627 = - out_fifo_internalFifos_0$D_OUT[176]; - 1'd1: - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d5627 = - out_fifo_internalFifos_1$D_OUT[176]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q32 = - out_fifo_internalFifos_0$D_OUT[178:177]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q32 = - out_fifo_internalFifos_1$D_OUT[178:177]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q33 = - out_fifo_internalFifos_0$D_OUT[175:174]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q33 = - out_fifo_internalFifos_1$D_OUT[175:174]; - endcase - end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 or - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q34 = - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 == - 3'd3; - 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q34 = - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683 == - 3'd3; - endcase - end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 or - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q35 = - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 == - 3'd4; - 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q35 = - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683 == - 3'd4; - endcase - end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 or - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q36 = - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 == - 3'd2; - 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q36 = - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683 == - 3'd2; - endcase - end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 or - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q37 = - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 == - 3'd1; - 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q37 = - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683 == - 3'd1; - endcase - end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 or - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q38 = - IF_out_fifo_internalFifos_0_first__517_BITS_17_ETC___d5671 == - 3'd0; - 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q38 = - IF_out_fifo_internalFifos_1_first__519_BITS_17_ETC___d5683 == - 3'd0; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6167 = - out_fifo_internalFifos_0$D_OUT[174]; - 1'd1: - SEL_ARR_out_fifo_internalFifos_0_first__517_BI_ETC___d6167 = - out_fifo_internalFifos_1$D_OUT[174]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q39 = - out_fifo_internalFifos_0$D_OUT[182:178]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q39 = - out_fifo_internalFifos_1$D_OUT[182:178]; - endcase - end - always@(f32d_deqP or - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 or - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078) - begin - case (f32d_deqP) - 1'd0: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q40 = - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 == - 4'd11; - 1'd1: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q40 = - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 == - 4'd11; - endcase - end - always@(f32d_deqP or - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 or - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078) - begin - case (f32d_deqP) - 1'd0: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q41 = - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 == - 4'd12; - 1'd1: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q41 = - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 == - 4'd12; - endcase - end - always@(f32d_deqP or - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 or - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078) - begin - case (f32d_deqP) - 1'd0: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q42 = - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 == - 4'd10; - 1'd1: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q42 = - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 == - 4'd10; - endcase - end - always@(f32d_deqP or - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 or - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078) - begin - case (f32d_deqP) - 1'd0: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q43 = - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 == - 4'd9; - 1'd1: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q43 = - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 == - 4'd9; - endcase - end - always@(f32d_deqP or - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 or - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078) - begin - case (f32d_deqP) - 1'd0: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q44 = - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 == - 4'd8; - 1'd1: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q44 = - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 == - 4'd8; - endcase - end - always@(f32d_deqP or - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 or - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078) - begin - case (f32d_deqP) - 1'd0: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q45 = - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 == - 4'd7; - 1'd1: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q45 = - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 == - 4'd7; - endcase - end - always@(f32d_deqP or - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 or - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078) - begin - case (f32d_deqP) - 1'd0: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q46 = - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 == - 4'd6; - 1'd1: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q46 = - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 == - 4'd6; - endcase - end - always@(f32d_deqP or - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 or - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078) - begin - case (f32d_deqP) - 1'd0: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q47 = - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 == - 4'd5; - 1'd1: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q47 = - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 == - 4'd5; - endcase - end - always@(f32d_deqP or - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 or - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078) - begin - case (f32d_deqP) - 1'd0: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q48 = - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 == - 4'd4; - 1'd1: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q48 = - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 == - 4'd4; - endcase - end - always@(f32d_deqP or - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 or - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078) - begin - case (f32d_deqP) - 1'd0: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q49 = - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 == - 4'd3; - 1'd1: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q49 = - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 == - 4'd3; - endcase - end - always@(f32d_deqP or - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 or - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078) - begin - case (f32d_deqP) - 1'd0: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q50 = - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 == - 4'd2; - 1'd1: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q50 = - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 == - 4'd2; - endcase - end - always@(f32d_deqP or - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 or - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078) - begin - case (f32d_deqP) - 1'd0: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q51 = - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 == - 4'd1; - 1'd1: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q51 = - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 == - 4'd1; - endcase - end - always@(f32d_deqP or - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 or - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078) - begin - case (f32d_deqP) - 1'd0: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q52 = - IF_f32d_data_0_678_BITS_73_TO_70_024_EQ_0_025__ETC___d5050 == - 4'd0; - 1'd1: - CASE_f32d_deqP_0_IF_f32d_data_0_678_BITS_73_TO_ETC__q52 = - IF_f32d_data_1_680_BITS_73_TO_70_052_EQ_0_053__ETC___d5078 == - 4'd0; - endcase - end - always@(f22f3_deqP or - f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_f22f3_data_0_470_BITS_3_TO_0_950_f22f3_ETC___d3955 = - f22f3_data_0[3:0]; + CASE_decode_558_BITS_136_TO_135_0_decode_558_B_ETC__q11 = + decode___d7558[136:126]; 2'd1: - SEL_ARR_f22f3_data_0_470_BITS_3_TO_0_950_f22f3_ETC___d3955 = - f22f3_data_1[3:0]; - 2'd2: - SEL_ARR_f22f3_data_0_470_BITS_3_TO_0_950_f22f3_ETC___d3955 = - f22f3_data_2[3:0]; - 2'd3: - SEL_ARR_f22f3_data_0_470_BITS_3_TO_0_950_f22f3_ETC___d3955 = - f22f3_data_3[3:0]; + CASE_decode_558_BITS_136_TO_135_0_decode_558_B_ETC__q11 = + { decode___d7558[136:135], + IF_decode_558_BITS_134_TO_131_687_EQ_0_688_OR__ETC___d7781 }; + default: CASE_decode_558_BITS_136_TO_135_0_decode_558_B_ETC__q11 = + 11'd1194; + endcase + end + always@(decode___d7558) + begin + case (decode___d7558[78:67]) + 12'd1, + 12'd2, + 12'd3, + 12'd256, + 12'd260, + 12'd261, + 12'd262, + 12'd320, + 12'd321, + 12'd322, + 12'd323, + 12'd324, + 12'd384, + 12'd768, + 12'd769, + 12'd770, + 12'd771, + 12'd772, + 12'd773, + 12'd774, + 12'd832, + 12'd833, + 12'd834, + 12'd835, + 12'd836, + 12'd1952, + 12'd1953, + 12'd1954, + 12'd1955, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, + 12'd2048, + 12'd2049, + 12'd2496, + 12'd2816, + 12'd2818, + 12'd3008, + 12'd3072, + 12'd3073, + 12'd3074, + 12'd3857, + 12'd3858, + 12'd3859, + 12'd3860: + CASE_decode_558_BITS_78_TO_67_1_decode_558_BIT_ETC__q12 = + decode___d7558[78:67]; + default: CASE_decode_558_BITS_78_TO_67_1_decode_558_BIT_ETC__q12 = + 12'd2303; + endcase + end + always@(decode___d7558) + begin + case (decode___d7558[65:61]) + 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: + CASE_decode_558_BITS_65_TO_61_0_decode_558_BIT_ETC__q13 = + decode___d7558[65:61]; + default: CASE_decode_558_BITS_65_TO_61_0_decode_558_BIT_ETC__q13 = + 5'd10; + endcase + end + always@(decode___d7558 or + decodeBrPred___d7915 or + IF_NOT_decode_558_BIT_7_569_582_OR_decode_558__ETC___d7930) + begin + case (decode___d7558[171:167]) + 5'd9, 5'd12: + CASE_decode_558_BITS_171_TO_167_9_IF_NOT_decod_ETC__q14 = + IF_NOT_decode_558_BIT_7_569_582_OR_decode_558__ETC___d7930; + default: CASE_decode_558_BITS_171_TO_167_9_IF_NOT_decod_ETC__q14 = + decodeBrPred___d7915[128:0]; + endcase + end + always@(decode___d7558 or + decodeBrPred___d7915 or + NOT_decode_558_BIT_7_569_582_OR_decode_558_BIT_ETC___d7922) + begin + case (decode___d7558[171:167]) + 5'd9, 5'd12: + CASE_decode_558_BITS_171_TO_167_9_NOT_decode_5_ETC__q15 = + NOT_decode_558_BIT_7_569_582_OR_decode_558_BIT_ETC___d7922; + default: CASE_decode_558_BITS_171_TO_167_9_NOT_decode_5_ETC__q15 = + decodeBrPred___d7915[129]; + endcase + end + always@(decode___d7047) + begin + case (decode___d7047[140:138]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_decode_047_BITS_140_TO_138_0_decode_047_B_ETC__q16 = + decode___d7047[140:138]; + default: CASE_decode_047_BITS_140_TO_138_0_decode_047_B_ETC__q16 = 3'd7; + endcase + end + always@(decode___d7047 or + CASE_decode_047_BITS_140_TO_138_0_decode_047_B_ETC__q16) + begin + case (decode___d7047[166:164]) + 3'd0, 3'd1, 3'd2, 3'd3: + CASE_decode_047_BITS_166_TO_164_0_decode_047_B_ETC__q17 = + decode___d7047[166:137]; + 3'd4: + CASE_decode_047_BITS_166_TO_164_0_decode_047_B_ETC__q17 = + { decode___d7047[166:164], + 18'h2AAAA, + decode___d7047[145:141], + CASE_decode_047_BITS_140_TO_138_0_decode_047_B_ETC__q16, + decode___d7047[137] }; + default: CASE_decode_047_BITS_166_TO_164_0_decode_047_B_ETC__q17 = + 30'd715827882; + endcase + end + always@(decode___d7047 or + IF_decode_047_BITS_134_TO_131_176_EQ_0_177_OR__ETC___d7270) + begin + case (decode___d7047[136:135]) + 2'd0: + CASE_decode_047_BITS_136_TO_135_0_decode_047_B_ETC__q18 = + decode___d7047[136:126]; + 2'd1: + CASE_decode_047_BITS_136_TO_135_0_decode_047_B_ETC__q18 = + { decode___d7047[136:135], + IF_decode_047_BITS_134_TO_131_176_EQ_0_177_OR__ETC___d7270 }; + default: CASE_decode_047_BITS_136_TO_135_0_decode_047_B_ETC__q18 = + 11'd1194; + endcase + end + always@(decode___d7047) + begin + case (decode___d7047[78:67]) + 12'd1, + 12'd2, + 12'd3, + 12'd256, + 12'd260, + 12'd261, + 12'd262, + 12'd320, + 12'd321, + 12'd322, + 12'd323, + 12'd324, + 12'd384, + 12'd768, + 12'd769, + 12'd770, + 12'd771, + 12'd772, + 12'd773, + 12'd774, + 12'd832, + 12'd833, + 12'd834, + 12'd835, + 12'd836, + 12'd1952, + 12'd1953, + 12'd1954, + 12'd1955, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, + 12'd2048, + 12'd2049, + 12'd2496, + 12'd2816, + 12'd2818, + 12'd3008, + 12'd3072, + 12'd3073, + 12'd3074, + 12'd3857, + 12'd3858, + 12'd3859, + 12'd3860: + CASE_decode_047_BITS_78_TO_67_1_decode_047_BIT_ETC__q19 = + decode___d7047[78:67]; + default: CASE_decode_047_BITS_78_TO_67_1_decode_047_BIT_ETC__q19 = + 12'd2303; endcase end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q53 = - out_fifo_internalFifos_0$D_OUT[175]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q53 = - out_fifo_internalFifos_1$D_OUT[175]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q54 = - out_fifo_internalFifos_0$D_OUT[175]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q54 = - out_fifo_internalFifos_1$D_OUT[175]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q55 = - out_fifo_internalFifos_0$D_OUT[188:185]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q55 = - out_fifo_internalFifos_1$D_OUT[188:185]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q56 = - out_fifo_internalFifos_0$D_OUT[184]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q56 = - out_fifo_internalFifos_1$D_OUT[184]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q57 = - out_fifo_internalFifos_0$D_OUT[188:185]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q57 = - out_fifo_internalFifos_1$D_OUT[188:185]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q58 = - out_fifo_internalFifos_0$D_OUT[184]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q58 = - out_fifo_internalFifos_1$D_OUT[184]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q59 = - !out_fifo_internalFifos_0$D_OUT[81]; - 1'd1: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q59 = - !out_fifo_internalFifos_1$D_OUT[81]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q60 = - out_fifo_internalFifos_0$D_OUT[80:76]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q60 = - out_fifo_internalFifos_1$D_OUT[80:76]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q61 = - !out_fifo_internalFifos_0$D_OUT[75]; - 1'd1: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q61 = - !out_fifo_internalFifos_1$D_OUT[75]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q62 = - !out_fifo_internalFifos_0$D_OUT[74]; - 1'd1: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q62 = - !out_fifo_internalFifos_1$D_OUT[74]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q63 = - out_fifo_internalFifos_0$D_OUT[73:69]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q63 = - out_fifo_internalFifos_1$D_OUT[73:69]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q64 = - !out_fifo_internalFifos_0$D_OUT[81]; - 1'd1: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q64 = - !out_fifo_internalFifos_1$D_OUT[81]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q65 = - out_fifo_internalFifos_0$D_OUT[80:76]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q65 = - out_fifo_internalFifos_1$D_OUT[80:76]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q66 = - !out_fifo_internalFifos_0$D_OUT[75]; - 1'd1: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q66 = - !out_fifo_internalFifos_1$D_OUT[75]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q67 = - !out_fifo_internalFifos_0$D_OUT[74]; - 1'd1: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q67 = - !out_fifo_internalFifos_1$D_OUT[74]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q68 = - out_fifo_internalFifos_0$D_OUT[73:69]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q68 = - out_fifo_internalFifos_1$D_OUT[73:69]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q69 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3859; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q69 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3859; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q70 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3860; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q70 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3860; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(decode___d7047) begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q71 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3858; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q71 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3858; + case (decode___d7047[65:61]) + 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: + CASE_decode_047_BITS_65_TO_61_0_decode_047_BIT_ETC__q20 = + decode___d7047[65:61]; + default: CASE_decode_047_BITS_65_TO_61_0_decode_047_BIT_ETC__q20 = + 5'd10; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(decode___d7047 or + decodeBrPred___d7404 or + IF_NOT_decode_047_BIT_7_058_071_OR_decode_047__ETC___d7419) begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q72 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3857; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q72 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3857; + case (decode___d7047[171:167]) + 5'd9, 5'd12: + CASE_decode_047_BITS_171_TO_167_9_IF_NOT_decod_ETC__q21 = + IF_NOT_decode_047_BIT_7_058_071_OR_decode_047__ETC___d7419; + default: CASE_decode_047_BITS_171_TO_167_9_IF_NOT_decod_ETC__q21 = + decodeBrPred___d7404[128:0]; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(decode___d7047 or + decodeBrPred___d7404 or + NOT_decode_047_BIT_7_058_071_OR_decode_047_BIT_ETC___d7411) begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q73 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd2818; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q73 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd2818; + case (decode___d7047[171:167]) + 5'd9, 5'd12: + CASE_decode_047_BITS_171_TO_167_9_NOT_decode_0_ETC__q22 = + NOT_decode_047_BIT_7_058_071_OR_decode_047_BIT_ETC___d7411; + default: CASE_decode_047_BITS_171_TO_167_9_NOT_decode_0_ETC__q22 = + decodeBrPred___d7404[129]; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(f32d_deqP or f32d_data_0 or f32d_data_1) begin - case (x__h63120) + case (f32d_deqP) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q74 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd2816; + SEL_ARR_NOT_f32d_data_0_979_BIT_75_991_992_NOT_ETC___d7996 = + !f32d_data_0[75]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q74 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd2816; + SEL_ARR_NOT_f32d_data_0_979_BIT_75_991_992_NOT_ETC___d7996 = + !f32d_data_1[75]; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(f32d_deqP or f32d_data_0 or f32d_data_1) begin - case (x__h63120) + case (f32d_deqP) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q75 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd836; + SEL_ARR_f32d_data_0_979_BIT_75_991_f32d_data_1_ETC___d7998 = + f32d_data_0[75]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q75 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd836; + SEL_ARR_f32d_data_0_979_BIT_75_991_f32d_data_1_ETC___d7998 = + f32d_data_1[75]; endcase end - always@(x__h63120 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q76 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd835; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q23 = + out_fifo_internalFifos_0$D_OUT[256]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q76 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd835; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q23 = + out_fifo_internalFifos_1$D_OUT[256]; endcase end - always@(x__h63120 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q77 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd834; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q24 = + out_fifo_internalFifos_0$D_OUT[255]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q77 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd834; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q24 = + out_fifo_internalFifos_1$D_OUT[255]; endcase end - always@(x__h63120 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q78 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd833; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q25 = + out_fifo_internalFifos_0$D_OUT[254]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q78 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd833; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q25 = + out_fifo_internalFifos_1$D_OUT[254]; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(out_fifo_internalFifos_0$D_OUT) begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q79 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd832; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q79 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd832; + case (out_fifo_internalFifos_0$D_OUT[241:239]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 = + out_fifo_internalFifos_0$D_OUT[241:239]; + default: IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 = + 3'd5; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q80 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd774; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q80 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd774; + case (out_fifo_internalFifos_1$D_OUT[241:239]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266 = + out_fifo_internalFifos_1$D_OUT[241:239]; + default: IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266 = + 3'd5; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(out_fifo_dequeueFifo_rl or + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 or + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q81 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd773; + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q26 = + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 == + 3'd3; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q81 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd773; + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q26 = + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266 == + 3'd3; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(out_fifo_dequeueFifo_rl or + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 or + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q82 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd772; + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q27 = + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 == + 3'd4; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q82 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd772; + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q27 = + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266 == + 3'd4; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(out_fifo_dequeueFifo_rl or + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 or + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q83 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd771; + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q28 = + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 == + 3'd2; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q83 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd771; + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q28 = + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266 == + 3'd2; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(out_fifo_dequeueFifo_rl or + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 or + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q84 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd770; + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q29 = + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 == + 3'd1; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q84 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd770; + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q29 = + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266 == + 3'd1; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(out_fifo_dequeueFifo_rl or + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 or + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q85 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd769; + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q30 = + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 == + 3'd0; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q85 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd769; + CASE_out_fifo_dequeueFifo_rl_0_IF_out_fifo_int_ETC__q30 = + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266 == + 3'd0; endcase end - always@(x__h63120 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q86 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd768; + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8217 = + out_fifo_internalFifos_0$D_OUT[238]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q86 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd768; + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8217 = + out_fifo_internalFifos_1$D_OUT[238]; endcase end - always@(x__h63120 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q87 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd384; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q31 = + out_fifo_internalFifos_0$D_OUT[246:242]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q87 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd384; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q31 = + out_fifo_internalFifos_1$D_OUT[246:242]; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(out_fifo_internalFifos_0$D_OUT) begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q88 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd324; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q88 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd324; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q89 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd323; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q89 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd323; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q90 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd322; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q90 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd322; + case (out_fifo_internalFifos_0$D_OUT[235:232]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 = + out_fifo_internalFifos_0$D_OUT[235:232]; + default: IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 = + 4'd11; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q91 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd321; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q91 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd321; + case (out_fifo_internalFifos_1$D_OUT[235:232]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 = + out_fifo_internalFifos_1$D_OUT[235:232]; + default: IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 = + 4'd11; endcase end - always@(x__h63120 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q92 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd320; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q32 = + out_fifo_internalFifos_0$D_OUT[227]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q92 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd320; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q32 = + out_fifo_internalFifos_1$D_OUT[227]; endcase end - always@(x__h63120 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q93 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd262; + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8400 = + out_fifo_internalFifos_0$D_OUT[228:227]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q93 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd262; + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8400 = + out_fifo_internalFifos_1$D_OUT[228:227]; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(out_fifo_internalFifos_0$D_OUT) begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q94 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd261; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q94 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd261; + case (out_fifo_internalFifos_0$D_OUT[231:229]) + 3'd2, 3'd3: + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 = + out_fifo_internalFifos_0$D_OUT[231:229]; + default: IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 = + 3'd4; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q95 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd260; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q95 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd260; + case (out_fifo_internalFifos_1$D_OUT[231:229]) + 3'd2, 3'd3: + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436 = + out_fifo_internalFifos_1$D_OUT[231:229]; + default: IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436 = + 3'd4; endcase end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q96 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd256; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q96 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd256; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q97 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd2049; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q97 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd2049; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q98 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd2048; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q98 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd2048; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q99 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3074; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q99 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3074; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q100 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3073; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q100 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3073; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q101 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3072; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q101 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3072; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q102 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q102 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q103 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd2; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q103 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd2; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q104 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd1; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q104 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd1; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q105 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3859; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q105 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3859; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q106 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3860; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q106 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3860; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q107 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3858; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q107 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3858; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q108 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3857; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q108 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3857; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q109 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd2818; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q109 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd2818; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q110 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd2816; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q110 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd2816; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q111 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd836; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q111 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd836; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q112 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd835; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q112 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd835; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q113 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd834; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q113 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd834; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q114 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd833; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q114 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd833; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q115 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd832; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q115 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd832; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q116 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd774; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q116 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd774; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q117 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd773; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q117 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd773; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q118 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd772; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q118 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd772; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q119 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd771; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q119 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd771; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q120 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd770; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q120 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd770; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q121 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd769; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q121 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd769; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q122 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd768; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q122 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd768; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q123 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd384; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q123 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd384; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q124 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd324; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q124 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd324; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q125 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd323; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q125 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd323; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q126 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd322; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q126 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd322; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q127 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd321; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q127 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd321; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q128 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd320; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q128 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd320; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q129 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd262; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q129 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd262; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q130 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd261; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q130 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd261; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q131 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd260; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q131 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd260; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q132 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd256; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q132 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd256; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q133 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd2049; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q133 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd2049; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q134 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd2048; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q134 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd2048; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q135 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3074; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q135 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3074; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q136 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3073; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q136 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3073; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q137 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3072; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q137 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3072; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q138 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd3; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q138 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd3; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q139 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd2; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q139 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd2; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436) begin - case (x__h72803) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q140 = - out_fifo_internalFifos_0$D_OUT[172:161] == 12'd1; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8469 = + out_fifo_internalFifos_0$D_OUT[231:229] != 3'd0 && + out_fifo_internalFifos_0$D_OUT[231:229] != 3'd1 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 == + 3'd3; 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q140 = - out_fifo_internalFifos_1$D_OUT[172:161] == 12'd1; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8469 = + out_fifo_internalFifos_1$D_OUT[231:229] != 3'd0 && + out_fifo_internalFifos_1$D_OUT[231:229] != 3'd1 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436 == + 3'd3; endcase end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q141 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd11; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8461 = + out_fifo_internalFifos_0$D_OUT[231:229] != 3'd0 && + out_fifo_internalFifos_0$D_OUT[231:229] != 3'd1 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 == + 3'd2; 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q141 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd11; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8461 = + out_fifo_internalFifos_1$D_OUT[231:229] != 3'd0 && + out_fifo_internalFifos_1$D_OUT[231:229] != 3'd1 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436 == + 3'd2; endcase end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q142 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd12; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8452 = + out_fifo_internalFifos_0$D_OUT[231:229] != 3'd0 && + (out_fifo_internalFifos_0$D_OUT[231:229] == 3'd1 || + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 == + 3'd1); 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q142 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd12; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8452 = + out_fifo_internalFifos_1$D_OUT[231:229] != 3'd0 && + (out_fifo_internalFifos_1$D_OUT[231:229] == 3'd1 || + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436 == + 3'd1); endcase end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q143 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8441 = + out_fifo_internalFifos_0$D_OUT[231:229] == 3'd0 || + out_fifo_internalFifos_0$D_OUT[231:229] != 3'd1 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 == + 3'd0; + 1'd1: + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8441 = + out_fifo_internalFifos_1$D_OUT[231:229] == 3'd0 || + out_fifo_internalFifos_1$D_OUT[231:229] != 3'd1 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436 == + 3'd0; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8605 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == 4'd10; 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q143 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8605 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == 4'd10; endcase end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q144 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8589 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == 4'd9; 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q144 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8589 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == 4'd9; endcase end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q145 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8573 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == 4'd8; 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q145 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8573 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == 4'd8; endcase end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q146 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8557 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == 4'd7; 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q146 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8557 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == 4'd7; endcase end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q147 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8541 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == 4'd6; 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q147 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8541 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == 4'd6; endcase end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q148 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd5; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8524 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + (out_fifo_internalFifos_0$D_OUT[235:232] == 4'd5 || + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == + 4'd5); 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q148 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd5; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8524 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + (out_fifo_internalFifos_1$D_OUT[235:232] == 4'd5 || + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == + 4'd5); endcase end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q149 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd4; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8508 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + (out_fifo_internalFifos_0$D_OUT[235:232] == 4'd4 || + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == + 4'd4); 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q149 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd4; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8508 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + (out_fifo_internalFifos_1$D_OUT[235:232] == 4'd4 || + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == + 4'd4); endcase end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q150 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd3; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8491 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + (out_fifo_internalFifos_0$D_OUT[235:232] == 4'd3 || + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == + 4'd3); 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q150 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd3; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8491 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + (out_fifo_internalFifos_1$D_OUT[235:232] == 4'd3 || + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == + 4'd3); endcase end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q151 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd2; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8417 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + (out_fifo_internalFifos_0$D_OUT[235:232] == 4'd2 || + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == + 4'd2); 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q151 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd2; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8417 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + (out_fifo_internalFifos_1$D_OUT[235:232] == 4'd2 || + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == + 4'd2); endcase end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q152 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd1; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8396 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + (out_fifo_internalFifos_0$D_OUT[235:232] == 4'd1 || + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == + 4'd1); 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q152 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd1; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d8396 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + (out_fifo_internalFifos_1$D_OUT[235:232] == 4'd1 || + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == + 4'd1); endcase end - always@(x__h63120 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q153 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8372 = + out_fifo_internalFifos_0$D_OUT[235:232] == 4'd0 || + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == 4'd0; 1'd1: - CASE_x3120_0_IF_out_fifo_internalFifos_0_first_ETC__q153 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8372 = + out_fifo_internalFifos_1$D_OUT[235:232] == 4'd0 || + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == 4'd0; endcase end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q154 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd11; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q33 = + out_fifo_internalFifos_0$D_OUT[237:236] == 2'd1; 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q154 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd11; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q33 = + out_fifo_internalFifos_1$D_OUT[237:236] == 2'd1; endcase end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q155 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd12; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q34 = + out_fifo_internalFifos_0$D_OUT[237:236] == 2'd0; 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q155 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd12; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q34 = + out_fifo_internalFifos_1$D_OUT[237:236] == 2'd0; endcase end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q156 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q35 = + out_fifo_internalFifos_0$D_OUT[230:227]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q35 = + out_fifo_internalFifos_1$D_OUT[230:227]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9289 = + out_fifo_internalFifos_0$D_OUT[240]; + 1'd1: + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9289 = + out_fifo_internalFifos_1$D_OUT[240]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q36 = + out_fifo_internalFifos_0$D_OUT[256]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q36 = + out_fifo_internalFifos_1$D_OUT[256]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q37 = + out_fifo_internalFifos_0$D_OUT[255]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q37 = + out_fifo_internalFifos_1$D_OUT[255]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q38 = + out_fifo_internalFifos_0$D_OUT[254]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q38 = + out_fifo_internalFifos_1$D_OUT[254]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q39 = + out_fifo_internalFifos_0$D_OUT[253]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q39 = + out_fifo_internalFifos_1$D_OUT[253]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q40 = + out_fifo_internalFifos_0$D_OUT[252]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q40 = + out_fifo_internalFifos_1$D_OUT[252]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q41 = + out_fifo_internalFifos_0$D_OUT[253]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q41 = + out_fifo_internalFifos_1$D_OUT[253]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q42 = + out_fifo_internalFifos_0$D_OUT[252]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q42 = + out_fifo_internalFifos_1$D_OUT[252]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q43 = + out_fifo_internalFifos_0$D_OUT[251]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q43 = + out_fifo_internalFifos_1$D_OUT[251]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q44 = + out_fifo_internalFifos_0$D_OUT[250]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q44 = + out_fifo_internalFifos_1$D_OUT[250]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q45 = + out_fifo_internalFifos_0$D_OUT[251]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q45 = + out_fifo_internalFifos_1$D_OUT[251]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q46 = + out_fifo_internalFifos_0$D_OUT[250]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q46 = + out_fifo_internalFifos_1$D_OUT[250]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q47 = + out_fifo_internalFifos_0$D_OUT[249]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q47 = + out_fifo_internalFifos_1$D_OUT[249]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q48 = + out_fifo_internalFifos_0$D_OUT[248]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q48 = + out_fifo_internalFifos_1$D_OUT[248]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q49 = + out_fifo_internalFifos_0$D_OUT[249]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q49 = + out_fifo_internalFifos_1$D_OUT[249]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q50 = + out_fifo_internalFifos_0$D_OUT[248]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q50 = + out_fifo_internalFifos_1$D_OUT[248]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q51 = + out_fifo_internalFifos_0$D_OUT[247]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q51 = + out_fifo_internalFifos_1$D_OUT[247]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q52 = + out_fifo_internalFifos_0$D_OUT[246]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q52 = + out_fifo_internalFifos_1$D_OUT[246]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q53 = + out_fifo_internalFifos_0$D_OUT[247]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q53 = + out_fifo_internalFifos_1$D_OUT[247]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q54 = + out_fifo_internalFifos_0$D_OUT[246]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q54 = + out_fifo_internalFifos_1$D_OUT[246]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q55 = + out_fifo_internalFifos_0$D_OUT[245]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q55 = + out_fifo_internalFifos_1$D_OUT[245]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q56 = + out_fifo_internalFifos_0$D_OUT[244]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q56 = + out_fifo_internalFifos_1$D_OUT[244]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q57 = + out_fifo_internalFifos_0$D_OUT[245]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q57 = + out_fifo_internalFifos_1$D_OUT[245]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q58 = + out_fifo_internalFifos_0$D_OUT[244]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q58 = + out_fifo_internalFifos_1$D_OUT[244]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q59 = + out_fifo_internalFifos_0$D_OUT[243]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q59 = + out_fifo_internalFifos_1$D_OUT[243]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q60 = + out_fifo_internalFifos_0$D_OUT[242]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q60 = + out_fifo_internalFifos_1$D_OUT[242]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q61 = + out_fifo_internalFifos_0$D_OUT[243]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q61 = + out_fifo_internalFifos_1$D_OUT[243]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q62 = + out_fifo_internalFifos_0$D_OUT[242]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q62 = + out_fifo_internalFifos_1$D_OUT[242]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q63 = + out_fifo_internalFifos_0$D_OUT[242:241]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q63 = + out_fifo_internalFifos_1$D_OUT[242:241]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q64 = + out_fifo_internalFifos_0$D_OUT[239:238]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q64 = + out_fifo_internalFifos_1$D_OUT[239:238]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8209 = + out_fifo_internalFifos_0$D_OUT[240]; + 1'd1: + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d8209 = + out_fifo_internalFifos_1$D_OUT[240]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q65 = + out_fifo_internalFifos_0$D_OUT[242:241]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q65 = + out_fifo_internalFifos_1$D_OUT[242:241]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q66 = + out_fifo_internalFifos_0$D_OUT[239:238]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q66 = + out_fifo_internalFifos_1$D_OUT[239:238]; + endcase + end + always@(x__h74473 or + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 or + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q67 = + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 == + 3'd3; + 1'd1: + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q67 = + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266 == + 3'd3; + endcase + end + always@(x__h74473 or + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 or + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q68 = + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 == + 3'd4; + 1'd1: + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q68 = + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266 == + 3'd4; + endcase + end + always@(x__h74473 or + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 or + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q69 = + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 == + 3'd2; + 1'd1: + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q69 = + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266 == + 3'd2; + endcase + end + always@(x__h74473 or + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 or + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q70 = + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 == + 3'd1; + 1'd1: + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q70 = + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266 == + 3'd1; + endcase + end + always@(x__h74473 or + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 or + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q71 = + IF_out_fifo_internalFifos_0_first__059_BITS_24_ETC___d8254 == + 3'd0; + 1'd1: + CASE_x4473_0_IF_out_fifo_internalFifos_0_first_ETC__q71 = + IF_out_fifo_internalFifos_1_first__061_BITS_24_ETC___d8266 == + 3'd0; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9291 = + out_fifo_internalFifos_0$D_OUT[238]; + 1'd1: + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9291 = + out_fifo_internalFifos_1$D_OUT[238]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q72 = + out_fifo_internalFifos_0$D_OUT[246:242]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q72 = + out_fifo_internalFifos_1$D_OUT[246:242]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q73 = + out_fifo_internalFifos_0$D_OUT[227]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q73 = + out_fifo_internalFifos_1$D_OUT[227]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9329 = + out_fifo_internalFifos_0$D_OUT[228:227]; + 1'd1: + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9329 = + out_fifo_internalFifos_1$D_OUT[228:227]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436) + begin + case (x__h74473) + 1'd0: + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9337 = + out_fifo_internalFifos_0$D_OUT[231:229] != 3'd0 && + out_fifo_internalFifos_0$D_OUT[231:229] != 3'd1 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 == + 3'd3; + 1'd1: + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9337 = + out_fifo_internalFifos_1$D_OUT[231:229] != 3'd0 && + out_fifo_internalFifos_1$D_OUT[231:229] != 3'd1 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436 == + 3'd3; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436) + begin + case (x__h74473) + 1'd0: + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9336 = + out_fifo_internalFifos_0$D_OUT[231:229] != 3'd0 && + out_fifo_internalFifos_0$D_OUT[231:229] != 3'd1 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 == + 3'd2; + 1'd1: + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9336 = + out_fifo_internalFifos_1$D_OUT[231:229] != 3'd0 && + out_fifo_internalFifos_1$D_OUT[231:229] != 3'd1 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436 == + 3'd2; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436) + begin + case (x__h74473) + 1'd0: + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9334 = + out_fifo_internalFifos_0$D_OUT[231:229] != 3'd0 && + (out_fifo_internalFifos_0$D_OUT[231:229] == 3'd1 || + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 == + 3'd1); + 1'd1: + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9334 = + out_fifo_internalFifos_1$D_OUT[231:229] != 3'd0 && + (out_fifo_internalFifos_1$D_OUT[231:229] == 3'd1 || + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436 == + 3'd1); + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436) + begin + case (x__h74473) + 1'd0: + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9332 = + out_fifo_internalFifos_0$D_OUT[231:229] == 3'd0 || + out_fifo_internalFifos_0$D_OUT[231:229] != 3'd1 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8425 == + 3'd0; + 1'd1: + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9332 = + out_fifo_internalFifos_1$D_OUT[231:229] == 3'd0 || + out_fifo_internalFifos_1$D_OUT[231:229] != 3'd1 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8436 == + 3'd0; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) + begin + case (x__h74473) + 1'd0: + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9353 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == 4'd10; 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q156 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9353 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == 4'd10; endcase end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h72803) + case (x__h74473) 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q157 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9352 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == 4'd9; 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q157 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9352 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == 4'd9; endcase end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h72803) + case (x__h74473) 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q158 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9351 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == 4'd8; 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q158 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9351 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == 4'd8; endcase end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h72803) + case (x__h74473) 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q159 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9350 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == 4'd7; 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q159 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9350 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == 4'd7; endcase end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h72803) + case (x__h74473) 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q160 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9349 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == 4'd6; 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q160 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9349 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == 4'd6; endcase end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h72803) + case (x__h74473) 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q161 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd5; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9347 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + (out_fifo_internalFifos_0$D_OUT[235:232] == 4'd5 || + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == + 4'd5); 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q161 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd5; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9347 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + (out_fifo_internalFifos_1$D_OUT[235:232] == 4'd5 || + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == + 4'd5); endcase end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h72803) + case (x__h74473) 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q162 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd4; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9346 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + (out_fifo_internalFifos_0$D_OUT[235:232] == 4'd4 || + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == + 4'd4); 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q162 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd4; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9346 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + (out_fifo_internalFifos_1$D_OUT[235:232] == 4'd4 || + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == + 4'd4); endcase end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h72803) + case (x__h74473) 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q163 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd3; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9344 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + (out_fifo_internalFifos_0$D_OUT[235:232] == 4'd3 || + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == + 4'd3); 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q163 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd3; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9344 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + (out_fifo_internalFifos_1$D_OUT[235:232] == 4'd3 || + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == + 4'd3); endcase end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h72803) + case (x__h74473) 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q164 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd2; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9331 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + (out_fifo_internalFifos_0$D_OUT[235:232] == 4'd2 || + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == + 4'd2); 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q164 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd2; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9331 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + (out_fifo_internalFifos_1$D_OUT[235:232] == 4'd2 || + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == + 4'd2); endcase end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h72803) + case (x__h74473) 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q165 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == - 4'd1; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9328 = + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd0 && + (out_fifo_internalFifos_0$D_OUT[235:232] == 4'd1 || + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == + 4'd1); 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q165 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == - 4'd1; + SEL_ARR_NOT_out_fifo_internalFifos_0_first__05_ETC___d9328 = + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd0 && + (out_fifo_internalFifos_1$D_OUT[235:232] == 4'd1 || + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == + 4'd1); endcase end - always@(x__h72803 or - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 or - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059) + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 or + out_fifo_internalFifos_1$D_OUT or + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363) begin - case (x__h72803) + case (x__h74473) 1'd0: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q166 = - IF_out_fifo_internalFifos_0_first__517_BITS_67_ETC___d6031 == + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9324 = + out_fifo_internalFifos_0$D_OUT[235:232] == 4'd0 || + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_0$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_0_first__059_BITS_23_ETC___d8334 == 4'd0; 1'd1: - CASE_x2803_0_IF_out_fifo_internalFifos_0_first_ETC__q166 = - IF_out_fifo_internalFifos_1_first__519_BITS_67_ETC___d6059 == + SEL_ARR_out_fifo_internalFifos_0_first__059_BI_ETC___d9324 = + out_fifo_internalFifos_1$D_OUT[235:232] == 4'd0 || + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd1 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd2 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd3 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd4 && + out_fifo_internalFifos_1$D_OUT[235:232] != 4'd5 && + IF_out_fifo_internalFifos_1_first__061_BITS_23_ETC___d8363 == 4'd0; endcase end - always@(x__h63120 or + always@(x__h74473 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (x__h74473) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q167 = - out_fifo_internalFifos_0$D_OUT[194:192] == 3'd4; + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q74 = + out_fifo_internalFifos_0$D_OUT[237:236] == 2'd1; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q167 = - out_fifo_internalFifos_1$D_OUT[194:192] == 3'd4; + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q74 = + out_fifo_internalFifos_1$D_OUT[237:236] == 2'd1; endcase end - always@(x__h63120 or + always@(x__h74473 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (x__h74473) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q168 = - out_fifo_internalFifos_0$D_OUT[194:192] == 3'd3; + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q75 = + out_fifo_internalFifos_0$D_OUT[237:236] == 2'd0; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q168 = - out_fifo_internalFifos_1$D_OUT[194:192] == 3'd3; + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q75 = + out_fifo_internalFifos_1$D_OUT[237:236] == 2'd0; endcase end - always@(x__h63120 or + always@(x__h74473 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (x__h74473) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q169 = - out_fifo_internalFifos_0$D_OUT[194:192] == 3'd2; + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q76 = + out_fifo_internalFifos_0$D_OUT[230:227]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q169 = - out_fifo_internalFifos_1$D_OUT[194:192] == 3'd2; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q170 = - out_fifo_internalFifos_0$D_OUT[191:189]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q170 = - out_fifo_internalFifos_1$D_OUT[191:189]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q171 = - out_fifo_internalFifos_0$D_OUT[194:192] == 3'd1; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q171 = - out_fifo_internalFifos_1$D_OUT[194:192] == 3'd1; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q172 = - out_fifo_internalFifos_0$D_OUT[176:174]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q172 = - out_fifo_internalFifos_1$D_OUT[176:174]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q173 = - out_fifo_internalFifos_0$D_OUT[194:192] == 3'd0; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q173 = - out_fifo_internalFifos_1$D_OUT[194:192] == 3'd0; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q174 = - out_fifo_internalFifos_0$D_OUT[178:174]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q174 = - out_fifo_internalFifos_1$D_OUT[178:174]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q175 = - !out_fifo_internalFifos_0$D_OUT[173]; - 1'd1: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q175 = - !out_fifo_internalFifos_1$D_OUT[173]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q176 = - !out_fifo_internalFifos_0$D_OUT[160]; - 1'd1: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q176 = - !out_fifo_internalFifos_1$D_OUT[160]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q177 = - out_fifo_internalFifos_0$D_OUT[159:128]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q177 = - out_fifo_internalFifos_1$D_OUT[159:128]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q178 = - out_fifo_internalFifos_0$D_OUT[194:192] == 3'd4; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q178 = - out_fifo_internalFifos_1$D_OUT[194:192] == 3'd4; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q179 = - out_fifo_internalFifos_0$D_OUT[194:192] == 3'd3; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q179 = - out_fifo_internalFifos_1$D_OUT[194:192] == 3'd3; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q180 = - out_fifo_internalFifos_0$D_OUT[194:192] == 3'd2; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q180 = - out_fifo_internalFifos_1$D_OUT[194:192] == 3'd2; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q181 = - out_fifo_internalFifos_0$D_OUT[191:189]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q181 = - out_fifo_internalFifos_1$D_OUT[191:189]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q182 = - out_fifo_internalFifos_0$D_OUT[194:192] == 3'd1; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q182 = - out_fifo_internalFifos_1$D_OUT[194:192] == 3'd1; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183 = - out_fifo_internalFifos_0$D_OUT[176:174]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183 = - out_fifo_internalFifos_1$D_OUT[176:174]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q184 = - out_fifo_internalFifos_0$D_OUT[194:192] == 3'd0; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q184 = - out_fifo_internalFifos_1$D_OUT[194:192] == 3'd0; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q185 = - out_fifo_internalFifos_0$D_OUT[178:174]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q185 = - out_fifo_internalFifos_1$D_OUT[178:174]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q186 = - !out_fifo_internalFifos_0$D_OUT[173]; - 1'd1: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q186 = - !out_fifo_internalFifos_1$D_OUT[173]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q187 = - !out_fifo_internalFifos_0$D_OUT[160]; - 1'd1: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q187 = - !out_fifo_internalFifos_1$D_OUT[160]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q188 = - out_fifo_internalFifos_0$D_OUT[159:128]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q188 = - out_fifo_internalFifos_1$D_OUT[159:128]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q189 = - !out_fifo_internalFifos_0$D_OUT[95]; - 1'd1: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q189 = - !out_fifo_internalFifos_1$D_OUT[95]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q190 = - !out_fifo_internalFifos_0$D_OUT[94]; - 1'd1: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q190 = - !out_fifo_internalFifos_1$D_OUT[94]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q191 = - out_fifo_internalFifos_0$D_OUT[93:89]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q191 = - out_fifo_internalFifos_1$D_OUT[93:89]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q192 = - !out_fifo_internalFifos_0$D_OUT[88]; - 1'd1: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q192 = - !out_fifo_internalFifos_1$D_OUT[88]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q193 = - !out_fifo_internalFifos_0$D_OUT[87]; - 1'd1: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q193 = - !out_fifo_internalFifos_1$D_OUT[87]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q194 = - out_fifo_internalFifos_0$D_OUT[86:82]; - 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q194 = - out_fifo_internalFifos_1$D_OUT[86:82]; - endcase - end - always@(x__h63120 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h63120) - 1'd0: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q195 = - !out_fifo_internalFifos_0$D_OUT[68]; - 1'd1: - CASE_x3120_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q195 = - !out_fifo_internalFifos_1$D_OUT[68]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q196 = - !out_fifo_internalFifos_0$D_OUT[95]; - 1'd1: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q196 = - !out_fifo_internalFifos_1$D_OUT[95]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q197 = - !out_fifo_internalFifos_0$D_OUT[94]; - 1'd1: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q197 = - !out_fifo_internalFifos_1$D_OUT[94]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q198 = - out_fifo_internalFifos_0$D_OUT[93:89]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q198 = - out_fifo_internalFifos_1$D_OUT[93:89]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q199 = - !out_fifo_internalFifos_0$D_OUT[88]; - 1'd1: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q199 = - !out_fifo_internalFifos_1$D_OUT[88]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q200 = - !out_fifo_internalFifos_0$D_OUT[87]; - 1'd1: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q200 = - !out_fifo_internalFifos_1$D_OUT[87]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q201 = - out_fifo_internalFifos_0$D_OUT[86:82]; - 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q201 = - out_fifo_internalFifos_1$D_OUT[86:82]; - endcase - end - always@(x__h72803 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h72803) - 1'd0: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q202 = - !out_fifo_internalFifos_0$D_OUT[68]; - 1'd1: - CASE_x2803_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q202 = - !out_fifo_internalFifos_1$D_OUT[68]; + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q76 = + out_fifo_internalFifos_1$D_OUT[230:227]; endcase end always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) begin case (f12f2_deqP) 1'd0: - CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q203 = + SEL_ARR_f12f2_data_0_810_BITS_266_TO_265_811_f_ETC___d4815 = + f12f2_data_0[266:265]; + 1'd1: + SEL_ARR_f12f2_data_0_810_BITS_266_TO_265_811_f_ETC___d4815 = + f12f2_data_1[266:265]; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q77 = + f32d_data_0[73:69] == 5'd13; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q77 = + f32d_data_1[73:69] == 5'd13; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q78 = + f32d_data_0[73:69] == 5'd15; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q78 = + f32d_data_1[73:69] == 5'd15; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q79 = + f32d_data_0[73:69] == 5'd12; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q79 = + f32d_data_1[73:69] == 5'd12; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q80 = + f32d_data_0[73:69] == 5'd11; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q80 = + f32d_data_1[73:69] == 5'd11; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q81 = + f32d_data_0[73:69] == 5'd9; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q81 = + f32d_data_1[73:69] == 5'd9; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q82 = + f32d_data_0[73:69] == 5'd8; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q82 = + f32d_data_1[73:69] == 5'd8; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q83 = + f32d_data_0[73:69] == 5'd7; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q83 = + f32d_data_1[73:69] == 5'd7; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q84 = + f32d_data_0[73:69] == 5'd6; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q84 = + f32d_data_1[73:69] == 5'd6; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q85 = + f32d_data_0[73:69] == 5'd5; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q85 = + f32d_data_1[73:69] == 5'd5; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q86 = + f32d_data_0[73:69] == 5'd4; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q86 = + f32d_data_1[73:69] == 5'd4; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q87 = + f32d_data_0[73:69] == 5'd3; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q87 = + f32d_data_1[73:69] == 5'd3; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q88 = + f32d_data_0[73:69] == 5'd2; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q88 = + f32d_data_1[73:69] == 5'd2; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q89 = + f32d_data_0[73:69] == 5'd1; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q89 = + f32d_data_1[73:69] == 5'd1; + endcase + end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q90 = + f32d_data_0[73:69] == 5'd0; + 1'd1: + CASE_f32d_deqP_0_f32d_data_0_BITS_73_TO_69_EQ__ETC__q90 = + f32d_data_1[73:69] == 5'd0; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q91 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd30; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q91 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd30; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q92 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd31; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q92 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd31; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q93 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd29; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q93 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd29; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q94 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd28; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q94 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd28; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q95 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd15; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q95 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd15; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q96 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd14; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q96 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd14; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q97 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd13; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q97 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd13; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q98 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd12; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q98 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd12; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q99 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd1; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q99 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd1; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q100 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd0; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q100 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd0; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q101 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd30; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q101 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd30; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q102 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd31; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q102 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd31; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q103 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd29; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q103 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd29; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q104 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd28; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q104 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd28; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q105 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd15; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q105 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd15; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q106 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd14; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q106 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd14; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q107 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd13; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q107 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd13; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q108 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd12; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q108 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd12; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q109 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd1; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q109 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd1; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q110 = + out_fifo_internalFifos_0$D_OUT[166:162] == 5'd0; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q110 = + out_fifo_internalFifos_1$D_OUT[166:162] == 5'd0; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q111 = + out_fifo_internalFifos_0$D_OUT[193]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q111 = + out_fifo_internalFifos_1$D_OUT[193]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q112 = + out_fifo_internalFifos_0$D_OUT[193]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q112 = + out_fifo_internalFifos_1$D_OUT[193]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q113 = + out_fifo_internalFifos_0$D_OUT[199:197]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q113 = + out_fifo_internalFifos_1$D_OUT[199:197]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q114 = + out_fifo_internalFifos_0$D_OUT[196:194]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q114 = + out_fifo_internalFifos_1$D_OUT[196:194]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q115 = + out_fifo_internalFifos_0$D_OUT[199:197]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q115 = + out_fifo_internalFifos_1$D_OUT[199:197]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q116 = + out_fifo_internalFifos_0$D_OUT[196:194]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q116 = + out_fifo_internalFifos_1$D_OUT[196:194]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q117 = + out_fifo_internalFifos_0$D_OUT[202]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q117 = + out_fifo_internalFifos_1$D_OUT[202]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q118 = + out_fifo_internalFifos_0$D_OUT[201:200]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q118 = + out_fifo_internalFifos_1$D_OUT[201:200]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q119 = + out_fifo_internalFifos_0$D_OUT[202]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q119 = + out_fifo_internalFifos_1$D_OUT[202]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q120 = + out_fifo_internalFifos_0$D_OUT[201:200]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q120 = + out_fifo_internalFifos_1$D_OUT[201:200]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q121 = + out_fifo_internalFifos_0$D_OUT[241]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q121 = + out_fifo_internalFifos_1$D_OUT[241]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q122 = + out_fifo_internalFifos_0$D_OUT[239]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q122 = + out_fifo_internalFifos_1$D_OUT[239]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q123 = + out_fifo_internalFifos_0$D_OUT[241]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q123 = + out_fifo_internalFifos_1$D_OUT[241]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q124 = + out_fifo_internalFifos_0$D_OUT[239]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q124 = + out_fifo_internalFifos_1$D_OUT[239]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q125 = + out_fifo_internalFifos_0$D_OUT[204]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q125 = + out_fifo_internalFifos_1$D_OUT[204]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q126 = + out_fifo_internalFifos_0$D_OUT[203]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q126 = + out_fifo_internalFifos_1$D_OUT[203]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q127 = + out_fifo_internalFifos_0$D_OUT[204]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q127 = + out_fifo_internalFifos_1$D_OUT[204]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q128 = + out_fifo_internalFifos_0$D_OUT[203]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q128 = + out_fifo_internalFifos_1$D_OUT[203]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q129 = + !out_fifo_internalFifos_0$D_OUT[82]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q129 = + !out_fifo_internalFifos_1$D_OUT[82]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q130 = + out_fifo_internalFifos_0$D_OUT[81:77]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q130 = + out_fifo_internalFifos_1$D_OUT[81:77]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q131 = + !out_fifo_internalFifos_0$D_OUT[76]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q131 = + !out_fifo_internalFifos_1$D_OUT[76]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q132 = + !out_fifo_internalFifos_0$D_OUT[75]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q132 = + !out_fifo_internalFifos_1$D_OUT[75]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q133 = + out_fifo_internalFifos_0$D_OUT[74:70]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q133 = + out_fifo_internalFifos_1$D_OUT[74:70]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q134 = + !out_fifo_internalFifos_0$D_OUT[82]; + 1'd1: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q134 = + !out_fifo_internalFifos_1$D_OUT[82]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q135 = + out_fifo_internalFifos_0$D_OUT[81:77]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q135 = + out_fifo_internalFifos_1$D_OUT[81:77]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q136 = + !out_fifo_internalFifos_0$D_OUT[76]; + 1'd1: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q136 = + !out_fifo_internalFifos_1$D_OUT[76]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q137 = + !out_fifo_internalFifos_0$D_OUT[75]; + 1'd1: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q137 = + !out_fifo_internalFifos_1$D_OUT[75]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q138 = + out_fifo_internalFifos_0$D_OUT[74:70]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q138 = + out_fifo_internalFifos_1$D_OUT[74:70]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q139 = + out_fifo_internalFifos_0$D_OUT[206]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q139 = + out_fifo_internalFifos_1$D_OUT[206]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q140 = + out_fifo_internalFifos_0$D_OUT[205]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q140 = + out_fifo_internalFifos_1$D_OUT[205]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q141 = + out_fifo_internalFifos_0$D_OUT[206]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q141 = + out_fifo_internalFifos_1$D_OUT[206]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q142 = + out_fifo_internalFifos_0$D_OUT[205]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q142 = + out_fifo_internalFifos_1$D_OUT[205]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q143 = + out_fifo_internalFifos_0$D_OUT[208]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q143 = + out_fifo_internalFifos_1$D_OUT[208]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q144 = + out_fifo_internalFifos_0$D_OUT[207]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q144 = + out_fifo_internalFifos_1$D_OUT[207]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q145 = + out_fifo_internalFifos_0$D_OUT[208]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q145 = + out_fifo_internalFifos_1$D_OUT[208]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q146 = + out_fifo_internalFifos_0$D_OUT[207]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q146 = + out_fifo_internalFifos_1$D_OUT[207]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q147 = + out_fifo_internalFifos_0$D_OUT[261:258]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q147 = + out_fifo_internalFifos_1$D_OUT[261:258]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q148 = + out_fifo_internalFifos_0$D_OUT[257]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q148 = + out_fifo_internalFifos_1$D_OUT[257]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q149 = + out_fifo_internalFifos_0$D_OUT[261:258]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q149 = + out_fifo_internalFifos_1$D_OUT[261:258]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q150 = + out_fifo_internalFifos_0$D_OUT[257]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q150 = + out_fifo_internalFifos_1$D_OUT[257]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q151 = + out_fifo_internalFifos_0$D_OUT[210]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q151 = + out_fifo_internalFifos_1$D_OUT[210]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q152 = + out_fifo_internalFifos_0$D_OUT[209]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q152 = + out_fifo_internalFifos_1$D_OUT[209]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q153 = + out_fifo_internalFifos_0$D_OUT[210]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q153 = + out_fifo_internalFifos_1$D_OUT[210]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q154 = + out_fifo_internalFifos_0$D_OUT[209]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q154 = + out_fifo_internalFifos_1$D_OUT[209]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q155 = + out_fifo_internalFifos_0$D_OUT[212]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q155 = + out_fifo_internalFifos_1$D_OUT[212]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q156 = + out_fifo_internalFifos_0$D_OUT[211]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q156 = + out_fifo_internalFifos_1$D_OUT[211]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q157 = + out_fifo_internalFifos_0$D_OUT[212]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q157 = + out_fifo_internalFifos_1$D_OUT[212]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q158 = + out_fifo_internalFifos_0$D_OUT[211]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q158 = + out_fifo_internalFifos_1$D_OUT[211]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q159 = + out_fifo_internalFifos_0$D_OUT[214]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q159 = + out_fifo_internalFifos_1$D_OUT[214]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q160 = + out_fifo_internalFifos_0$D_OUT[213]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q160 = + out_fifo_internalFifos_1$D_OUT[213]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q161 = + out_fifo_internalFifos_0$D_OUT[214]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q161 = + out_fifo_internalFifos_1$D_OUT[214]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q162 = + out_fifo_internalFifos_0$D_OUT[213]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q162 = + out_fifo_internalFifos_1$D_OUT[213]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q163 = + out_fifo_internalFifos_0$D_OUT[216]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q163 = + out_fifo_internalFifos_1$D_OUT[216]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q164 = + out_fifo_internalFifos_0$D_OUT[215]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q164 = + out_fifo_internalFifos_1$D_OUT[215]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q165 = + out_fifo_internalFifos_0$D_OUT[216]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q165 = + out_fifo_internalFifos_1$D_OUT[216]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q166 = + out_fifo_internalFifos_0$D_OUT[215]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q166 = + out_fifo_internalFifos_1$D_OUT[215]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q167 = + out_fifo_internalFifos_0$D_OUT[218]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q167 = + out_fifo_internalFifos_1$D_OUT[218]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q168 = + out_fifo_internalFifos_0$D_OUT[217]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q168 = + out_fifo_internalFifos_1$D_OUT[217]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q169 = + out_fifo_internalFifos_0$D_OUT[218]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q169 = + out_fifo_internalFifos_1$D_OUT[218]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q170 = + out_fifo_internalFifos_0$D_OUT[217]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q170 = + out_fifo_internalFifos_1$D_OUT[217]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q171 = + out_fifo_internalFifos_0$D_OUT[220]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q171 = + out_fifo_internalFifos_1$D_OUT[220]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q172 = + out_fifo_internalFifos_0$D_OUT[219]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q172 = + out_fifo_internalFifos_1$D_OUT[219]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q173 = + out_fifo_internalFifos_0$D_OUT[220]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q173 = + out_fifo_internalFifos_1$D_OUT[220]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q174 = + out_fifo_internalFifos_0$D_OUT[219]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q174 = + out_fifo_internalFifos_1$D_OUT[219]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q175 = + out_fifo_internalFifos_0$D_OUT[222]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q175 = + out_fifo_internalFifos_1$D_OUT[222]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q176 = + out_fifo_internalFifos_0$D_OUT[221]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q176 = + out_fifo_internalFifos_1$D_OUT[221]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q177 = + out_fifo_internalFifos_0$D_OUT[222]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q177 = + out_fifo_internalFifos_1$D_OUT[222]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q178 = + out_fifo_internalFifos_0$D_OUT[221]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q178 = + out_fifo_internalFifos_1$D_OUT[221]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q179 = + out_fifo_internalFifos_0$D_OUT[224]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q179 = + out_fifo_internalFifos_1$D_OUT[224]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q180 = + out_fifo_internalFifos_0$D_OUT[223]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q180 = + out_fifo_internalFifos_1$D_OUT[223]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q181 = + out_fifo_internalFifos_0$D_OUT[224]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q181 = + out_fifo_internalFifos_1$D_OUT[224]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q182 = + out_fifo_internalFifos_0$D_OUT[223]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q182 = + out_fifo_internalFifos_1$D_OUT[223]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q183 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1970; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q183 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1970; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q184 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1971; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q184 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1971; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q185 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1969; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q185 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1969; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q186 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1968; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q186 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1968; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q187 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1955; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q187 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1955; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q188 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1954; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q188 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1954; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q189 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1953; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q189 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1953; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q190 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1952; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q190 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1952; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q191 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3008; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q191 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3008; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q192 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3860; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q192 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3860; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q193 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3859; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q193 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3859; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q194 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3858; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q194 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3858; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q195 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3857; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q195 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3857; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q196 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd2818; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q196 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd2818; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q197 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd2816; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q197 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd2816; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q198 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd836; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q198 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd836; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q199 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd835; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q199 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd835; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q200 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd834; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q200 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd834; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q201 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd833; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q201 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd833; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q202 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd832; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q202 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd832; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q203 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd774; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q203 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd774; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q204 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd773; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q204 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd773; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q205 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd772; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q205 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd772; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q206 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd771; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q206 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd771; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q207 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd770; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q207 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd770; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q208 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd769; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q208 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd769; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q209 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd768; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q209 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd768; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q210 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd2496; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q210 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd2496; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q211 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd384; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q211 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd384; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q212 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd324; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q212 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd324; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q213 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd323; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q213 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd323; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q214 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd322; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q214 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd322; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q215 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd321; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q215 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd321; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q216 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd320; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q216 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd320; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q217 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd262; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q217 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd262; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q218 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd261; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q218 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd261; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q219 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd260; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q219 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd260; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q220 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd256; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q220 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd256; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q221 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd2049; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q221 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd2049; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q222 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd2048; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q222 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd2048; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q223 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3074; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q223 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3074; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q224 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3073; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q224 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3073; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q225 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3072; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q225 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3072; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q226 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q226 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q227 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd2; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q227 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd2; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q228 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q228 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q229 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1970; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q229 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1970; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q230 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1971; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q230 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1971; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q231 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1969; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q231 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1969; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q232 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1968; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q232 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1968; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q233 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1955; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q233 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1955; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q234 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1954; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q234 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1954; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q235 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1953; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q235 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1953; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q236 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1952; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q236 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1952; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q237 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3008; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q237 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3008; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q238 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3860; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q238 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3860; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q239 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3859; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q239 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3859; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q240 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3858; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q240 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3858; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q241 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3857; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q241 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3857; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q242 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd2818; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q242 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd2818; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q243 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd2816; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q243 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd2816; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q244 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd836; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q244 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd836; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q245 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd835; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q245 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd835; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q246 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd834; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q246 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd834; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q247 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd833; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q247 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd833; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q248 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd832; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q248 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd832; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q249 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd774; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q249 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd774; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q250 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd773; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q250 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd773; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q251 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd772; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q251 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd772; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q252 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd771; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q252 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd771; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q253 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd770; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q253 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd770; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q254 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd769; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q254 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd769; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q255 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd768; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q255 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd768; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q256 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd2496; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q256 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd2496; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q257 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd384; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q257 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd384; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q258 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd324; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q258 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd324; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q259 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd323; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q259 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd323; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q260 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd322; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q260 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd322; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q261 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd321; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q261 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd321; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q262 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd320; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q262 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd320; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q263 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd262; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q263 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd262; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q264 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd261; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q264 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd261; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q265 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd260; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q265 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd260; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q266 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd256; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q266 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd256; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q267 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd2049; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q267 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd2049; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q268 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd2048; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q268 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd2048; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q269 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3074; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q269 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3074; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q270 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3073; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q270 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3073; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q271 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3072; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q271 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3072; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q272 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd3; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q272 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd3; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q273 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd2; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q273 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd2; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q274 = + out_fifo_internalFifos_0$D_OUT[179:168] == 12'd1; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q274 = + out_fifo_internalFifos_1$D_OUT[179:168] == 12'd1; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q275 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd13; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q275 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd13; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q276 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd15; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q276 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd15; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q277 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd12; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q277 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd12; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q278 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd11; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q278 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd11; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q279 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd9; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q279 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd9; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q280 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd8; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q280 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd8; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q281 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd7; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q281 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd7; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q282 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd6; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q282 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd6; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q283 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd5; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q283 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd5; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q284 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd4; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q284 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd4; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q285 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd3; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q285 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd3; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q286 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd2; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q286 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd2; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q287 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd1; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q287 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd1; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q288 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd0; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q288 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd0; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q289 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd13; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q289 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd13; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q290 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd15; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q290 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd15; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q291 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd12; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q291 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd12; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q292 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd11; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q292 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd11; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q293 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd9; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q293 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd9; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q294 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd8; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q294 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd8; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q295 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd7; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q295 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd7; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q296 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd6; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q296 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd6; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q297 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd5; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q297 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd5; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q298 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd4; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q298 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd4; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q299 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd3; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q299 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd3; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q300 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd2; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q300 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd2; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q301 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd1; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q301 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd1; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q302 = + out_fifo_internalFifos_0$D_OUT[68:64] == 5'd0; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q302 = + out_fifo_internalFifos_1$D_OUT[68:64] == 5'd0; + endcase + end + always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) + begin + case (f12f2_deqP) + 1'd0: + CASE_f12f2_deqP_0_f12f2_data_0_BIT_5_1_f12f2_d_ETC__q303 = + f12f2_data_0[5]; + 1'd1: + CASE_f12f2_deqP_0_f12f2_data_0_BIT_5_1_f12f2_d_ETC__q303 = + f12f2_data_1[5]; + endcase + end + always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) + begin + case (f12f2_deqP) + 1'd0: + CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q304 = f12f2_data_0[4]; 1'd1: - CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q203 = + CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q304 = f12f2_data_1[4]; endcase end - always@(x__h72803 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204 = - out_fifo_internalFifos_0$D_OUT[199:195]; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q305 = + out_fifo_internalFifos_0$D_OUT[226]; 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204 = - out_fifo_internalFifos_1$D_OUT[199:195]; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q305 = + out_fifo_internalFifos_1$D_OUT[226]; endcase end - always@(x__h63120 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205 = - out_fifo_internalFifos_0$D_OUT[199:195]; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q306 = + out_fifo_internalFifos_0$D_OUT[225]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205 = - out_fifo_internalFifos_1$D_OUT[199:195]; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q306 = + out_fifo_internalFifos_1$D_OUT[225]; endcase end - always@(x__h63120 or + always@(x__h74473 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (x__h74473) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206 = - out_fifo_internalFifos_0$D_OUT[255:244]; + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q307 = + out_fifo_internalFifos_0$D_OUT[226]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206 = - out_fifo_internalFifos_1$D_OUT[255:244]; + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q307 = + out_fifo_internalFifos_1$D_OUT[226]; endcase end - always@(x__h63120 or + always@(x__h74473 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (x__h74473) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207 = - out_fifo_internalFifos_0$D_OUT[243:234]; + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q308 = + out_fifo_internalFifos_0$D_OUT[225]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207 = - out_fifo_internalFifos_1$D_OUT[243:234]; + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q308 = + out_fifo_internalFifos_1$D_OUT[225]; endcase end - always@(x__h63120 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q208 = - out_fifo_internalFifos_0$D_OUT[233]; + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q309 = + !out_fifo_internalFifos_0$D_OUT[180]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q208 = - out_fifo_internalFifos_1$D_OUT[233]; + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q309 = + !out_fifo_internalFifos_1$D_OUT[180]; endcase end - always@(x__h63120 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q209 = - out_fifo_internalFifos_0$D_OUT[232]; + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q310 = + !out_fifo_internalFifos_0$D_OUT[167]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q209 = - out_fifo_internalFifos_1$D_OUT[232]; + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q310 = + !out_fifo_internalFifos_1$D_OUT[167]; endcase end - always@(x__h72803 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q210 = - out_fifo_internalFifos_0$D_OUT[255:244]; + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q311 = + !out_fifo_internalFifos_0$D_OUT[161]; 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q210 = - out_fifo_internalFifos_1$D_OUT[255:244]; + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q311 = + !out_fifo_internalFifos_1$D_OUT[161]; endcase end - always@(x__h72803 or + always@(out_fifo_dequeueFifo_rl or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) + case (out_fifo_dequeueFifo_rl) 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q211 = - out_fifo_internalFifos_0$D_OUT[243:234]; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q312 = + out_fifo_internalFifos_0$D_OUT[160:129]; 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q211 = - out_fifo_internalFifos_1$D_OUT[243:234]; + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q312 = + out_fifo_internalFifos_1$D_OUT[160:129]; endcase end - always@(x__h72803 or + always@(x__h74473 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) + case (x__h74473) 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q212 = - out_fifo_internalFifos_0$D_OUT[233]; + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q313 = + !out_fifo_internalFifos_0$D_OUT[180]; 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q212 = - out_fifo_internalFifos_1$D_OUT[233]; + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q313 = + !out_fifo_internalFifos_1$D_OUT[180]; endcase end - always@(x__h72803 or + always@(x__h74473 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) + case (x__h74473) 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q213 = - out_fifo_internalFifos_0$D_OUT[232]; + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q314 = + !out_fifo_internalFifos_0$D_OUT[167]; 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q213 = - out_fifo_internalFifos_1$D_OUT[232]; + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q314 = + !out_fifo_internalFifos_1$D_OUT[167]; endcase end - always@(x__h63120 or + always@(x__h74473 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h63120) + case (x__h74473) 1'd0: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q214 = - out_fifo_internalFifos_0$D_OUT[259:256]; + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q315 = + !out_fifo_internalFifos_0$D_OUT[161]; 1'd1: - CASE_x3120_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q214 = - out_fifo_internalFifos_1$D_OUT[259:256]; + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q315 = + !out_fifo_internalFifos_1$D_OUT[161]; endcase end - always@(x__h72803 or + always@(x__h74473 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72803) + case (x__h74473) 1'd0: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q215 = - out_fifo_internalFifos_0$D_OUT[259:256]; + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q316 = + out_fifo_internalFifos_0$D_OUT[160:129]; 1'd1: - CASE_x2803_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q215 = - out_fifo_internalFifos_1$D_OUT[259:256]; + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q316 = + out_fifo_internalFifos_1$D_OUT[160:129]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q317 = + !out_fifo_internalFifos_0$D_OUT[96]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q317 = + !out_fifo_internalFifos_1$D_OUT[96]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q318 = + !out_fifo_internalFifos_0$D_OUT[95]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q318 = + !out_fifo_internalFifos_1$D_OUT[95]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q319 = + out_fifo_internalFifos_0$D_OUT[94:90]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q319 = + out_fifo_internalFifos_1$D_OUT[94:90]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q320 = + !out_fifo_internalFifos_0$D_OUT[89]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q320 = + !out_fifo_internalFifos_1$D_OUT[89]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q321 = + !out_fifo_internalFifos_0$D_OUT[88]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q321 = + !out_fifo_internalFifos_1$D_OUT[88]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q322 = + out_fifo_internalFifos_0$D_OUT[87:83]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q322 = + out_fifo_internalFifos_1$D_OUT[87:83]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q323 = + !out_fifo_internalFifos_0$D_OUT[69]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_NOT_out_fifo_in_ETC__q323 = + !out_fifo_internalFifos_1$D_OUT[69]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q324 = + out_fifo_internalFifos_0$D_OUT[63:0]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q324 = + out_fifo_internalFifos_1$D_OUT[63:0]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q325 = + !out_fifo_internalFifos_0$D_OUT[96]; + 1'd1: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q325 = + !out_fifo_internalFifos_1$D_OUT[96]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q326 = + !out_fifo_internalFifos_0$D_OUT[95]; + 1'd1: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q326 = + !out_fifo_internalFifos_1$D_OUT[95]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q327 = + out_fifo_internalFifos_0$D_OUT[94:90]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q327 = + out_fifo_internalFifos_1$D_OUT[94:90]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q328 = + !out_fifo_internalFifos_0$D_OUT[89]; + 1'd1: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q328 = + !out_fifo_internalFifos_1$D_OUT[89]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q329 = + !out_fifo_internalFifos_0$D_OUT[88]; + 1'd1: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q329 = + !out_fifo_internalFifos_1$D_OUT[88]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q330 = + out_fifo_internalFifos_0$D_OUT[87:83]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q330 = + out_fifo_internalFifos_1$D_OUT[87:83]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q331 = + !out_fifo_internalFifos_0$D_OUT[69]; + 1'd1: + CASE_x4473_0_NOT_out_fifo_internalFifos_0D_OU_ETC__q331 = + !out_fifo_internalFifos_1$D_OUT[69]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q332 = + out_fifo_internalFifos_0$D_OUT[63:0]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q332 = + out_fifo_internalFifos_1$D_OUT[63:0]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q333 = + out_fifo_internalFifos_0$D_OUT[267:265] == 3'd4; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q333 = + out_fifo_internalFifos_1$D_OUT[267:265] == 3'd4; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q334 = + out_fifo_internalFifos_0$D_OUT[267:265] == 3'd3; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q334 = + out_fifo_internalFifos_1$D_OUT[267:265] == 3'd3; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q335 = + out_fifo_internalFifos_0$D_OUT[267:265] == 3'd2; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q335 = + out_fifo_internalFifos_1$D_OUT[267:265] == 3'd2; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q336 = + out_fifo_internalFifos_0$D_OUT[264:262]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q336 = + out_fifo_internalFifos_1$D_OUT[264:262]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q337 = + out_fifo_internalFifos_0$D_OUT[267:265] == 3'd1; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q337 = + out_fifo_internalFifos_1$D_OUT[267:265] == 3'd1; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q338 = + out_fifo_internalFifos_0$D_OUT[240:238]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q338 = + out_fifo_internalFifos_1$D_OUT[240:238]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q339 = + out_fifo_internalFifos_0$D_OUT[267:265] == 3'd0; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q339 = + out_fifo_internalFifos_1$D_OUT[267:265] == 3'd0; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q340 = + out_fifo_internalFifos_0$D_OUT[242:238]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q340 = + out_fifo_internalFifos_1$D_OUT[242:238]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q341 = + out_fifo_internalFifos_0$D_OUT[267:265] == 3'd4; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q341 = + out_fifo_internalFifos_1$D_OUT[267:265] == 3'd4; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q342 = + out_fifo_internalFifos_0$D_OUT[267:265] == 3'd3; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q342 = + out_fifo_internalFifos_1$D_OUT[267:265] == 3'd3; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q343 = + out_fifo_internalFifos_0$D_OUT[267:265] == 3'd2; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q343 = + out_fifo_internalFifos_1$D_OUT[267:265] == 3'd2; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q344 = + out_fifo_internalFifos_0$D_OUT[264:262]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q344 = + out_fifo_internalFifos_1$D_OUT[264:262]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q345 = + out_fifo_internalFifos_0$D_OUT[267:265] == 3'd1; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q345 = + out_fifo_internalFifos_1$D_OUT[267:265] == 3'd1; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q346 = + out_fifo_internalFifos_0$D_OUT[240:238]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q346 = + out_fifo_internalFifos_1$D_OUT[240:238]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q347 = + out_fifo_internalFifos_0$D_OUT[267:265] == 3'd0; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q347 = + out_fifo_internalFifos_1$D_OUT[267:265] == 3'd0; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q348 = + out_fifo_internalFifos_0$D_OUT[242:238]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q348 = + out_fifo_internalFifos_1$D_OUT[242:238]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q349 = + out_fifo_internalFifos_0$D_OUT[272:268]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q349 = + out_fifo_internalFifos_1$D_OUT[272:268]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q350 = + out_fifo_internalFifos_0$D_OUT[272:268]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q350 = + out_fifo_internalFifos_1$D_OUT[272:268]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q351 = + out_fifo_internalFifos_0$D_OUT[328:317]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q351 = + out_fifo_internalFifos_1$D_OUT[328:317]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q352 = + out_fifo_internalFifos_0$D_OUT[316:307]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q352 = + out_fifo_internalFifos_1$D_OUT[316:307]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q353 = + out_fifo_internalFifos_0$D_OUT[306]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q353 = + out_fifo_internalFifos_1$D_OUT[306]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q354 = + out_fifo_internalFifos_0$D_OUT[305]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q354 = + out_fifo_internalFifos_1$D_OUT[305]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q355 = + out_fifo_internalFifos_0$D_OUT[328:317]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q355 = + out_fifo_internalFifos_1$D_OUT[328:317]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q356 = + out_fifo_internalFifos_0$D_OUT[316:307]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q356 = + out_fifo_internalFifos_1$D_OUT[316:307]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q357 = + out_fifo_internalFifos_0$D_OUT[306]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q357 = + out_fifo_internalFifos_1$D_OUT[306]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q358 = + out_fifo_internalFifos_0$D_OUT[305]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q358 = + out_fifo_internalFifos_1$D_OUT[305]; + endcase + end + always@(out_fifo_dequeueFifo_rl or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (out_fifo_dequeueFifo_rl) + 1'd0: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q359 = + out_fifo_internalFifos_0$D_OUT[332:329]; + 1'd1: + CASE_out_fifo_dequeueFifo_rl_0_out_fifo_intern_ETC__q359 = + out_fifo_internalFifos_1$D_OUT[332:329]; + endcase + end + always@(x__h74473 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h74473) + 1'd0: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q360 = + out_fifo_internalFifos_0$D_OUT[332:329]; + 1'd1: + CASE_x4473_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q360 = + out_fifo_internalFifos_1$D_OUT[332:329]; + endcase + end + always@(j__h114680 or + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5039) + begin + case (j__h114680) + 3'd0, 3'd1, 3'd2, 3'd3: + CASE_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_2_ETC___d5040 = + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5039; + default: CASE_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_2_ETC___d5040 = + 1'd1; + endcase + end + always@(pending_spaces_ext__h145988 or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099) + begin + case (pending_spaces_ext__h145988) + 3'd0, 3'd1, 3'd2: + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q361 = + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099; + 3'd3, 3'd4, 3'd5, 3'd6, 3'd7: + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q361 = 1'd1; + endcase + end + always@(pending_spaces_ext__h145988 or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5106 or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099) + begin + case (pending_spaces_ext__h145988) + 3'd0: + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q362 = + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5106; + 3'd1, 3'd2, 3'd3: + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q362 = + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099; + 3'd4, 3'd5, 3'd6, 3'd7: + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q362 = 1'd1; + endcase + end + always@(pending_spaces_ext__h145988 or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5093 or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099) + begin + case (pending_spaces_ext__h145988) + 3'd0: + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q363 = + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5093; + 3'd1, 3'd2, 3'd3: + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q363 = + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099; + 3'd4, 3'd5, 3'd6, 3'd7: + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q363 = 1'd1; + endcase + end + always@(pending_spaces_ext__h145988 or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099) + begin + case (pending_spaces_ext__h145988) + 3'd0, 3'd1, 3'd2, 3'd3: + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q364 = + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099; + 3'd4, 3'd5, 3'd6, 3'd7: + CASE_pending_spaces_ext45988_0_NOT_SEL_ARR_f22_ETC__q364 = 1'd1; + endcase + end + always@(pending_spaces_ext__h145988 or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5093 or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099) + begin + case (pending_spaces_ext__h145988) + 3'd0, 3'd5, 3'd6, 3'd7: + CASE_pending_spaces_ext45988_0_1_1_NOT_SEL_ARR_ETC__q365 = 1'd1; + 3'd1: + CASE_pending_spaces_ext45988_0_1_1_NOT_SEL_ARR_ETC__q365 = + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5093; + 3'd2, 3'd3, 3'd4: + CASE_pending_spaces_ext45988_0_1_1_NOT_SEL_ARR_ETC__q365 = + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099; + endcase + end + always@(pending_spaces_ext__h145988 or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099) + begin + case (pending_spaces_ext__h145988) + 3'd0, 3'd5, 3'd6, 3'd7: + CASE_pending_spaces_ext45988_0_1_1_NOT_SEL_ARR_ETC__q366 = 1'd1; + 3'd1, 3'd2, 3'd3, 3'd4: + CASE_pending_spaces_ext45988_0_1_1_NOT_SEL_ARR_ETC__q366 = + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099; + endcase + end + always@(pending_spaces__h145986 or f22f3_empty) + begin + case (pending_spaces__h145986) + 2'd0, 2'd1, 2'd2: + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5124 = 1'd1; + 2'd3: + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5124 = + !f22f3_empty; + endcase + end + always@(pending_spaces__h145986 or f22f3_empty) + begin + case (pending_spaces__h145986) + 2'd0, 2'd1: + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5139 = 1'd1; + 2'd2, 2'd3: + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5139 = + !f22f3_empty; + endcase + end + always@(pending_spaces_ext__h145988 or + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5139 or + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5124 or + f22f3_empty or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5106 or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099) + begin + case (pending_spaces_ext__h145988) + 3'd0: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5140 = + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5139; + 3'd1: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5140 = + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5124; + 3'd2: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5140 = + !f22f3_empty && + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5106; + 3'd3, 3'd4, 3'd5: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5140 = + !f22f3_empty && + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099; + 3'd6, 3'd7: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5140 = + !f22f3_empty; + endcase + end + always@(pending_spaces_ext__h145988 or + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5124 or + f22f3_empty or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5106 or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099) + begin + case (pending_spaces_ext__h145988) + 3'd0: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5127 = + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5124; + 3'd1: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5127 = + !f22f3_empty && + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5106; + 3'd2, 3'd3, 3'd4: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5127 = + !f22f3_empty && + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099; + 3'd5, 3'd6, 3'd7: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5127 = + !f22f3_empty; + endcase + end + always@(pending_spaces__h145986 or f22f3_empty) + begin + case (pending_spaces__h145986) + 2'd0: CASE_pending_spaces45986_0_1_1_NOT_f22f3_empty_ETC__q367 = 1'd1; + 2'd1, 2'd2, 2'd3: + CASE_pending_spaces45986_0_1_1_NOT_f22f3_empty_ETC__q367 = + !f22f3_empty; + endcase + end + always@(pending_spaces_ext__h145988 or + CASE_pending_spaces45986_0_1_1_NOT_f22f3_empty_ETC__q367 or + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5139 or + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5124 or + f22f3_empty or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5106 or + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099) + begin + case (pending_spaces_ext__h145988) + 3'd0: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5142 = + CASE_pending_spaces45986_0_1_1_NOT_f22f3_empty_ETC__q367; + 3'd1: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5142 = + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5139; + 3'd2: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5142 = + CASE_3_MINUS_IF_rg_pending_n_items_951_EQ_0_95_ETC___d5124; + 3'd3: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5142 = + !f22f3_empty && + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5106; + 3'd4, 3'd5, 3'd6: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5142 = + !f22f3_empty && + NOT_SEL_ARR_f22f3_data_0_920_BITS_3_TO_0_921_f_ETC___d5099; + 3'd7: + CASE_0_CONCAT_3_MINUS_IF_rg_pending_n_items_95_ETC___d5142 = + !f22f3_empty; + endcase + end + always@(pending_spaces_ext__h145988 or + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d5134) + begin + case (pending_spaces_ext__h145988) + 3'd0, 3'd1, 3'd6, 3'd7: + CASE_pending_spaces_ext45988_0_1_1_1_2_NOT_f22_ETC__q368 = 1'd1; + 3'd2, 3'd3, 3'd4, 3'd5: + CASE_pending_spaces_ext45988_0_1_1_1_2_NOT_f22_ETC__q368 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d5134; + endcase + end + always@(pending_spaces_ext__h145988 or + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 or + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5130 or + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d5134) + begin + case (pending_spaces_ext__h145988) + 3'd0, 3'd1, 3'd6, 3'd7: + CASE_pending_spaces_ext45988_0_1_1_1_2_NOT_f22_ETC__q369 = 1'd1; + 3'd2: + CASE_pending_spaces_ext45988_0_1_1_1_2_NOT_f22_ETC__q369 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5130; + 3'd3, 3'd4, 3'd5: + CASE_pending_spaces_ext45988_0_1_1_1_2_NOT_f22_ETC__q369 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d5134; + endcase + end + always@(pending_spaces_ext__h145988 or + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 or + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5130 or + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d5134) + begin + case (pending_spaces_ext__h145988) + 3'd0, 3'd1, 3'd2, 3'd7: + CASE_pending_spaces_ext45988_0_1_1_1_2_1_3_NOT_ETC__q370 = 1'd1; + 3'd3: + CASE_pending_spaces_ext45988_0_1_1_1_2_1_3_NOT_ETC__q370 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d4950 || + NOT_IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_ETC___d5130; + 3'd4, 3'd5, 3'd6: + CASE_pending_spaces_ext45988_0_1_1_1_2_1_3_NOT_ETC__q370 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d5134; + endcase + end + always@(pending_spaces_ext__h145988 or + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d5134) + begin + case (pending_spaces_ext__h145988) + 3'd0, 3'd1, 3'd2, 3'd7: + CASE_pending_spaces_ext45988_0_1_1_1_2_1_3_NOT_ETC__q371 = 1'd1; + 3'd3, 3'd4, 3'd5, 3'd6: + CASE_pending_spaces_ext45988_0_1_1_1_2_1_3_NOT_ETC__q371 = + NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f3_d_ETC___d5134; + endcase + end + always@(j__h114680 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230) + begin + case (j__h114680) + 3'd0: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[15:0]; + 3'd1: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[31:16]; + 3'd2: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[15:0]; + 3'd3: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[31:16]; + default: SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5234 = + 16'b1010101010101010 /* unspecified value */ ; + endcase + end + always@(y_avValue_fst__h117191 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230) + begin + case (y_avValue_fst__h117191) + 3'd0: + CASE_y_avValue_fst17191_0_IF_NOT_f22f3_empty_1_ETC__q372 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[15:0]; + 3'd1: + CASE_y_avValue_fst17191_0_IF_NOT_f22f3_empty_1_ETC__q372 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[31:16]; + 3'd2: + CASE_y_avValue_fst17191_0_IF_NOT_f22f3_empty_1_ETC__q372 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[15:0]; + 3'd3: + CASE_y_avValue_fst17191_0_IF_NOT_f22f3_empty_1_ETC__q372 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[31:16]; + default: CASE_y_avValue_fst17191_0_IF_NOT_f22f3_empty_1_ETC__q372 = + 16'b1010101010101010 /* unspecified value */ ; + endcase + end + always@(IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5243 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230) + begin + case (IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_ETC___d5243) + 3'd0: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[15:0]; + 3'd1: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[31:16]; + 3'd2: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[15:0]; + 3'd3: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[31:16]; + default: SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5245 = + 16'b1010101010101010 /* unspecified value */ ; + endcase + end + always@(y_avValue_fst__h126140 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230) + begin + case (y_avValue_fst__h126140) + 3'd0: + CASE_y_avValue_fst26140_0_IF_NOT_f22f3_empty_1_ETC__q373 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[15:0]; + 3'd1: + CASE_y_avValue_fst26140_0_IF_NOT_f22f3_empty_1_ETC__q373 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[31:16]; + 3'd2: + CASE_y_avValue_fst26140_0_IF_NOT_f22f3_empty_1_ETC__q373 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[15:0]; + 3'd3: + CASE_y_avValue_fst26140_0_IF_NOT_f22f3_empty_1_ETC__q373 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[31:16]; + default: CASE_y_avValue_fst26140_0_IF_NOT_f22f3_empty_1_ETC__q373 = + 16'b1010101010101010 /* unspecified value */ ; + endcase + end + always@(IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5254 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230) + begin + case (IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO__ETC___d5254) + 3'd0: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[15:0]; + 3'd1: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[31:16]; + 3'd2: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[15:0]; + 3'd3: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[31:16]; + default: SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5256 = + 16'b1010101010101010 /* unspecified value */ ; + endcase + end + always@(y_avValue_fst__h134851 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230) + begin + case (y_avValue_fst__h134851) + 3'd0: + CASE_y_avValue_fst34851_0_IF_NOT_f22f3_empty_1_ETC__q374 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[15:0]; + 3'd1: + CASE_y_avValue_fst34851_0_IF_NOT_f22f3_empty_1_ETC__q374 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[31:16]; + 3'd2: + CASE_y_avValue_fst34851_0_IF_NOT_f22f3_empty_1_ETC__q374 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[15:0]; + 3'd3: + CASE_y_avValue_fst34851_0_IF_NOT_f22f3_empty_1_ETC__q374 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[31:16]; + default: CASE_y_avValue_fst34851_0_IF_NOT_f22f3_empty_1_ETC__q374 = + 16'b1010101010101010 /* unspecified value */ ; + endcase + end + always@(IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5265 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230) + begin + case (IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5265) + 3'd0: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[15:0]; + 3'd1: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[31:16]; + 3'd2: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[15:0]; + 3'd3: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[31:16]; + default: SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5267 = + 16'b1010101010101010 /* unspecified value */ ; + endcase + end + always@(IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5270 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230) + begin + case (IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_335__ETC___d5270) + 3'd0: + CASE_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_ETC__q375 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[15:0]; + 3'd1: + CASE_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_ETC__q375 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5217[31:16]; + 3'd2: + CASE_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_ETC__q375 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[15:0]; + 3'd3: + CASE_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_ETC__q375 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5230[31:16]; + default: CASE_IF_IF_IF_IF_SEL_ARR_f22f3_data_0_920_BITS_ETC__q375 = + 16'b1010101010101010 /* unspecified value */ ; + endcase + end + always@(pending_spaces_ext__h145988 or + orig_inst__h149821 or orig_inst__h150163 or orig_inst__h150509) + begin + case (pending_spaces_ext__h145988) + 3'd0: x__h152277 = orig_inst__h149821; + 3'd1: x__h152277 = orig_inst__h150163; + 3'd2: x__h152277 = orig_inst__h150509; + 3'd3, 3'd4, 3'd5, 3'd6, 3'd7: x__h152277 = 32'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + orig_inst__h159852 or + orig_inst__h149821 or orig_inst__h150163 or orig_inst__h150509) + begin + case (pending_spaces_ext__h145988) + 3'd0: x__h159975 = orig_inst__h159852; + 3'd1: x__h159975 = orig_inst__h149821; + 3'd2: x__h159975 = orig_inst__h150163; + 3'd3: x__h159975 = orig_inst__h150509; + 3'd4, 3'd5, 3'd6, 3'd7: x__h159975 = 32'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + inst__h149822 or inst__h150164 or inst__h150510) + begin + case (pending_spaces_ext__h145988) + 3'd0: x__h152323 = inst__h149822; + 3'd1: x__h152323 = inst__h150164; + 3'd2: x__h152323 = inst__h150510; + 3'd3, 3'd4, 3'd5, 3'd6, 3'd7: x__h152323 = 32'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + inst__h159853 or inst__h149822 or inst__h150164 or inst__h150510) + begin + case (pending_spaces_ext__h145988) + 3'd0: x__h159980 = inst__h159853; + 3'd1: x__h159980 = inst__h149822; + 3'd2: x__h159980 = inst__h150164; + 3'd3: x__h159980 = inst__h150510; + 3'd4, 3'd5, 3'd6, 3'd7: x__h159980 = 32'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + pc__h159850 or + pc__h149819 or pc__h150161 or pc__h150507 or pc_start__h114675) + begin + case (pending_spaces_ext__h145988) + 3'd0: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6314 = + pc__h159850; + 3'd1: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6314 = + pc__h149819; + 3'd2: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6314 = + pc__h150161; + 3'd3: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6314 = + pc__h150507; + 3'd4, 3'd5, 3'd6, 3'd7: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6314 = + pc_start__h114675; + endcase + end + always@(pending_spaces_ext__h145988 or + pc__h149819 or pc__h150161 or pc__h150507 or pc_start__h114675) + begin + case (pending_spaces_ext__h145988) + 3'd0: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5390 = + pc__h149819; + 3'd1: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5390 = + pc__h150161; + 3'd2: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5390 = + pc__h150507; + 3'd3, 3'd4, 3'd5, 3'd6, 3'd7: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d5390 = + pc_start__h114675; + endcase + end + always@(pending_spaces__h145986 or rg_pending_decode or pc_start__h114675) + begin + case (pending_spaces__h145986) + 2'd0: + SEL_ARR_rg_pending_decode_631_BITS_584_TO_456__ETC___d6636 = + rg_pending_decode[584:456]; + 2'd1: + SEL_ARR_rg_pending_decode_631_BITS_584_TO_456__ETC___d6636 = + rg_pending_decode[389:261]; + 2'd2: + SEL_ARR_rg_pending_decode_631_BITS_584_TO_456__ETC___d6636 = + rg_pending_decode[194:66]; + 2'd3: + SEL_ARR_rg_pending_decode_631_BITS_584_TO_456__ETC___d6636 = + pc_start__h114675; + endcase + end + always@(pending_spaces_ext__h145988 or + SEL_ARR_rg_pending_decode_631_BITS_584_TO_456__ETC___d6636 or + pc__h159850 or + pc__h149819 or pc__h150161 or pc__h150507 or pc_start__h114675) + begin + case (pending_spaces_ext__h145988) + 3'd0: + y_avValue_fst_pred_next_pc__h165564 = + SEL_ARR_rg_pending_decode_631_BITS_584_TO_456__ETC___d6636; + 3'd1: y_avValue_fst_pred_next_pc__h165564 = pc__h159850; + 3'd2: y_avValue_fst_pred_next_pc__h165564 = pc__h149819; + 3'd3: y_avValue_fst_pred_next_pc__h165564 = pc__h150161; + 3'd4: y_avValue_fst_pred_next_pc__h165564 = pc__h150507; + 3'd5, 3'd6, 3'd7: + y_avValue_fst_pred_next_pc__h165564 = pc_start__h114675; + endcase + end + always@(pending_spaces__h145986 or rg_pending_decode) + begin + case (pending_spaces__h145986) + 2'd0: + SEL_ARR_rg_pending_decode_631_BITS_453_TO_422__ETC___d6650 = + rg_pending_decode[453:422]; + 2'd1: + SEL_ARR_rg_pending_decode_631_BITS_453_TO_422__ETC___d6650 = + rg_pending_decode[258:227]; + 2'd2: + SEL_ARR_rg_pending_decode_631_BITS_453_TO_422__ETC___d6650 = + rg_pending_decode[63:32]; + 2'd3: + SEL_ARR_rg_pending_decode_631_BITS_453_TO_422__ETC___d6650 = 32'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + SEL_ARR_rg_pending_decode_631_BITS_453_TO_422__ETC___d6650 or + orig_inst__h159852 or + orig_inst__h149821 or orig_inst__h150163 or orig_inst__h150509) + begin + case (pending_spaces_ext__h145988) + 3'd0: + x__h161103 = + SEL_ARR_rg_pending_decode_631_BITS_453_TO_422__ETC___d6650; + 3'd1: x__h161103 = orig_inst__h159852; + 3'd2: x__h161103 = orig_inst__h149821; + 3'd3: x__h161103 = orig_inst__h150163; + 3'd4: x__h161103 = orig_inst__h150509; + 3'd5, 3'd6, 3'd7: x__h161103 = 32'd0; + endcase + end + always@(pending_spaces__h145986 or rg_pending_decode) + begin + case (pending_spaces__h145986) + 2'd0: + SEL_ARR_rg_pending_decode_631_BITS_455_TO_454__ETC___d6643 = + rg_pending_decode[455:454]; + 2'd1: + SEL_ARR_rg_pending_decode_631_BITS_455_TO_454__ETC___d6643 = + rg_pending_decode[260:259]; + 2'd2: + SEL_ARR_rg_pending_decode_631_BITS_455_TO_454__ETC___d6643 = + rg_pending_decode[65:64]; + 2'd3: SEL_ARR_rg_pending_decode_631_BITS_455_TO_454__ETC___d6643 = 2'd0; + endcase + end + always@(pending_spaces__h145986 or rg_pending_decode) + begin + case (pending_spaces__h145986) + 2'd0: + SEL_ARR_rg_pending_decode_631_BITS_421_TO_390__ETC___d6657 = + rg_pending_decode[421:390]; + 2'd1: + SEL_ARR_rg_pending_decode_631_BITS_421_TO_390__ETC___d6657 = + rg_pending_decode[226:195]; + 2'd2: + SEL_ARR_rg_pending_decode_631_BITS_421_TO_390__ETC___d6657 = + rg_pending_decode[31:0]; + 2'd3: + SEL_ARR_rg_pending_decode_631_BITS_421_TO_390__ETC___d6657 = 32'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + SEL_ARR_rg_pending_decode_631_BITS_421_TO_390__ETC___d6657 or + inst__h159853 or inst__h149822 or inst__h150164 or inst__h150510) + begin + case (pending_spaces_ext__h145988) + 3'd0: + x__h161115 = + SEL_ARR_rg_pending_decode_631_BITS_421_TO_390__ETC___d6657; + 3'd1: x__h161115 = inst__h159853; + 3'd2: x__h161115 = inst__h149822; + 3'd3: x__h161115 = inst__h150164; + 3'd4: x__h161115 = inst__h150510; + 3'd5, 3'd6, 3'd7: x__h161115 = 32'd0; + endcase + end + always@(pending_spaces__h145986 or rg_pending_decode or pc_start__h114675) + begin + case (pending_spaces__h145986) + 2'd0: + SEL_ARR_rg_pending_decode_631_BITS_389_TO_261__ETC___d6708 = + rg_pending_decode[389:261]; + 2'd1: + SEL_ARR_rg_pending_decode_631_BITS_389_TO_261__ETC___d6708 = + rg_pending_decode[194:66]; + 2'd2, 2'd3: + SEL_ARR_rg_pending_decode_631_BITS_389_TO_261__ETC___d6708 = + pc_start__h114675; + endcase + end + always@(pending_spaces__h145986 or rg_pending_decode) + begin + case (pending_spaces__h145986) + 2'd0: + SEL_ARR_rg_pending_decode_631_BITS_260_TO_259__ETC___d6712 = + rg_pending_decode[260:259]; + 2'd1: + SEL_ARR_rg_pending_decode_631_BITS_260_TO_259__ETC___d6712 = + rg_pending_decode[65:64]; + 2'd2, 2'd3: + SEL_ARR_rg_pending_decode_631_BITS_260_TO_259__ETC___d6712 = 2'd0; + endcase + end + always@(pending_spaces__h145986 or rg_pending_decode) + begin + case (pending_spaces__h145986) + 2'd0: + SEL_ARR_rg_pending_decode_631_BITS_258_TO_227__ETC___d6716 = + rg_pending_decode[258:227]; + 2'd1: + SEL_ARR_rg_pending_decode_631_BITS_258_TO_227__ETC___d6716 = + rg_pending_decode[63:32]; + 2'd2, 2'd3: + SEL_ARR_rg_pending_decode_631_BITS_258_TO_227__ETC___d6716 = 32'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + SEL_ARR_rg_pending_decode_631_BITS_258_TO_227__ETC___d6716 or + SEL_ARR_rg_pending_decode_631_BITS_453_TO_422__ETC___d6650 or + orig_inst__h159852 or + orig_inst__h149821 or orig_inst__h150163 or orig_inst__h150509) + begin + case (pending_spaces_ext__h145988) + 3'd0: + x__h165114 = + SEL_ARR_rg_pending_decode_631_BITS_258_TO_227__ETC___d6716; + 3'd1: + x__h165114 = + SEL_ARR_rg_pending_decode_631_BITS_453_TO_422__ETC___d6650; + 3'd2: x__h165114 = orig_inst__h159852; + 3'd3: x__h165114 = orig_inst__h149821; + 3'd4: x__h165114 = orig_inst__h150163; + 3'd5: x__h165114 = orig_inst__h150509; + 3'd6, 3'd7: x__h165114 = 32'd0; + endcase + end + always@(pending_spaces__h145986 or rg_pending_decode) + begin + case (pending_spaces__h145986) + 2'd0: + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q376 = + rg_pending_decode[63:32]; + 2'd1, 2'd2, 2'd3: + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q376 = 32'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q376 or + SEL_ARR_rg_pending_decode_631_BITS_258_TO_227__ETC___d6716 or + SEL_ARR_rg_pending_decode_631_BITS_453_TO_422__ETC___d6650 or + orig_inst__h159852 or + orig_inst__h149821 or orig_inst__h150163 or orig_inst__h150509) + begin + case (pending_spaces_ext__h145988) + 3'd0: + x__h165191 = + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q376; + 3'd1: + x__h165191 = + SEL_ARR_rg_pending_decode_631_BITS_258_TO_227__ETC___d6716; + 3'd2: + x__h165191 = + SEL_ARR_rg_pending_decode_631_BITS_453_TO_422__ETC___d6650; + 3'd3: x__h165191 = orig_inst__h159852; + 3'd4: x__h165191 = orig_inst__h149821; + 3'd5: x__h165191 = orig_inst__h150163; + 3'd6: x__h165191 = orig_inst__h150509; + 3'd7: x__h165191 = 32'd0; + endcase + end + always@(pending_spaces__h145986 or rg_pending_decode) + begin + case (pending_spaces__h145986) + 2'd0: + SEL_ARR_rg_pending_decode_631_BITS_226_TO_195__ETC___d6720 = + rg_pending_decode[226:195]; + 2'd1: + SEL_ARR_rg_pending_decode_631_BITS_226_TO_195__ETC___d6720 = + rg_pending_decode[31:0]; + 2'd2, 2'd3: + SEL_ARR_rg_pending_decode_631_BITS_226_TO_195__ETC___d6720 = 32'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + SEL_ARR_rg_pending_decode_631_BITS_226_TO_195__ETC___d6720 or + SEL_ARR_rg_pending_decode_631_BITS_421_TO_390__ETC___d6657 or + inst__h159853 or inst__h149822 or inst__h150164 or inst__h150510) + begin + case (pending_spaces_ext__h145988) + 3'd0: + x__h165122 = + SEL_ARR_rg_pending_decode_631_BITS_226_TO_195__ETC___d6720; + 3'd1: + x__h165122 = + SEL_ARR_rg_pending_decode_631_BITS_421_TO_390__ETC___d6657; + 3'd2: x__h165122 = inst__h159853; + 3'd3: x__h165122 = inst__h149822; + 3'd4: x__h165122 = inst__h150164; + 3'd5: x__h165122 = inst__h150510; + 3'd6, 3'd7: x__h165122 = 32'd0; + endcase + end + always@(pending_spaces__h145986 or rg_pending_decode) + begin + case (pending_spaces__h145986) + 2'd0: + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q377 = + rg_pending_decode[31:0]; + 2'd1, 2'd2, 2'd3: + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q377 = 32'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q377 or + SEL_ARR_rg_pending_decode_631_BITS_226_TO_195__ETC___d6720 or + SEL_ARR_rg_pending_decode_631_BITS_421_TO_390__ETC___d6657 or + inst__h159853 or inst__h149822 or inst__h150164 or inst__h150510) + begin + case (pending_spaces_ext__h145988) + 3'd0: + x__h165202 = + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q377; + 3'd1: + x__h165202 = + SEL_ARR_rg_pending_decode_631_BITS_226_TO_195__ETC___d6720; + 3'd2: + x__h165202 = + SEL_ARR_rg_pending_decode_631_BITS_421_TO_390__ETC___d6657; + 3'd3: x__h165202 = inst__h159853; + 3'd4: x__h165202 = inst__h149822; + 3'd5: x__h165202 = inst__h150164; + 3'd6: x__h165202 = inst__h150510; + 3'd7: x__h165202 = 32'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + SEL_ARR_rg_pending_decode_631_BITS_260_TO_259__ETC___d6712 or + SEL_ARR_rg_pending_decode_631_BITS_455_TO_454__ETC___d6643 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6320 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5395 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5400 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5405) + begin + case (pending_spaces_ext__h145988) + 3'd0: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_260_ETC___d6714 = + SEL_ARR_rg_pending_decode_631_BITS_260_TO_259__ETC___d6712; + 3'd1: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_260_ETC___d6714 = + SEL_ARR_rg_pending_decode_631_BITS_455_TO_454__ETC___d6643; + 3'd2: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_260_ETC___d6714 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6320; + 3'd3: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_260_ETC___d6714 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5395; + 3'd4: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_260_ETC___d6714 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5400; + 3'd5: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_260_ETC___d6714 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5405; + 3'd6, 3'd7: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_260_ETC___d6714 = 2'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + SEL_ARR_rg_pending_decode_631_BITS_455_TO_454__ETC___d6643 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6320 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5395 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5400 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5405) + begin + case (pending_spaces_ext__h145988) + 3'd0: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_455_ETC___d6645 = + SEL_ARR_rg_pending_decode_631_BITS_455_TO_454__ETC___d6643; + 3'd1: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_455_ETC___d6645 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6320; + 3'd2: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_455_ETC___d6645 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5395; + 3'd3: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_455_ETC___d6645 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5400; + 3'd4: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_455_ETC___d6645 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5405; + 3'd5, 3'd6, 3'd7: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_455_ETC___d6645 = 2'd0; + endcase + end + always@(pending_spaces__h145986 or rg_pending_decode) + begin + case (pending_spaces__h145986) + 2'd0: + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q378 = + rg_pending_decode[65:64]; + 2'd1, 2'd2, 2'd3: + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q378 = 2'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q378 or + SEL_ARR_rg_pending_decode_631_BITS_260_TO_259__ETC___d6712 or + SEL_ARR_rg_pending_decode_631_BITS_455_TO_454__ETC___d6643 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6320 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5395 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5400 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5405) + begin + case (pending_spaces_ext__h145988) + 3'd0: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_65__ETC___d6731 = + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q378; + 3'd1: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_65__ETC___d6731 = + SEL_ARR_rg_pending_decode_631_BITS_260_TO_259__ETC___d6712; + 3'd2: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_65__ETC___d6731 = + SEL_ARR_rg_pending_decode_631_BITS_455_TO_454__ETC___d6643; + 3'd3: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_65__ETC___d6731 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6320; + 3'd4: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_65__ETC___d6731 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5395; + 3'd5: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_65__ETC___d6731 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5400; + 3'd6: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_65__ETC___d6731 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5405; + 3'd7: SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_65__ETC___d6731 = 2'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + SEL_ARR_rg_pending_decode_631_BITS_389_TO_261__ETC___d6708 or + SEL_ARR_rg_pending_decode_631_BITS_584_TO_456__ETC___d6636 or + pc__h159850 or + pc__h149819 or pc__h150161 or pc__h150507 or pc_start__h114675) + begin + case (pending_spaces_ext__h145988) + 3'd0: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_389_ETC___d6710 = + SEL_ARR_rg_pending_decode_631_BITS_389_TO_261__ETC___d6708; + 3'd1: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_389_ETC___d6710 = + SEL_ARR_rg_pending_decode_631_BITS_584_TO_456__ETC___d6636; + 3'd2: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_389_ETC___d6710 = + pc__h159850; + 3'd3: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_389_ETC___d6710 = + pc__h149819; + 3'd4: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_389_ETC___d6710 = + pc__h150161; + 3'd5: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_389_ETC___d6710 = + pc__h150507; + 3'd6, 3'd7: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_389_ETC___d6710 = + pc_start__h114675; + endcase + end + always@(pending_spaces__h145986 or rg_pending_decode or pc_start__h114675) + begin + case (pending_spaces__h145986) + 2'd0: + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q379 = + rg_pending_decode[194:66]; + 2'd1, 2'd2, 2'd3: + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q379 = + pc_start__h114675; + endcase + end + always@(pending_spaces_ext__h145988 or + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q379 or + SEL_ARR_rg_pending_decode_631_BITS_389_TO_261__ETC___d6708 or + SEL_ARR_rg_pending_decode_631_BITS_584_TO_456__ETC___d6636 or + pc__h159850 or + pc__h149819 or pc__h150161 or pc__h150507 or pc_start__h114675) + begin + case (pending_spaces_ext__h145988) + 3'd0: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_194_ETC___d6727 = + CASE_pending_spaces45986_0_rg_pending_decode_B_ETC__q379; + 3'd1: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_194_ETC___d6727 = + SEL_ARR_rg_pending_decode_631_BITS_389_TO_261__ETC___d6708; + 3'd2: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_194_ETC___d6727 = + SEL_ARR_rg_pending_decode_631_BITS_584_TO_456__ETC___d6636; + 3'd3: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_194_ETC___d6727 = + pc__h159850; + 3'd4: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_194_ETC___d6727 = + pc__h149819; + 3'd5: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_194_ETC___d6727 = + pc__h150161; + 3'd6: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_194_ETC___d6727 = + pc__h150507; + 3'd7: + SEL_ARR_SEL_ARR_rg_pending_decode_631_BITS_194_ETC___d6727 = + pc_start__h114675; + endcase + end + always@(pending_spaces_ext__h145988 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6320 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5395 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5400 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5405) + begin + case (pending_spaces_ext__h145988) + 3'd0: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6322 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d6320; + 3'd1: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6322 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5395; + 3'd2: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6322 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5400; + 3'd3: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6322 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5405; + 3'd4, 3'd5, 3'd6, 3'd7: + SEL_ARR_IF_NOT_f22f3_empty_17_919_AND_NOT_SEL__ETC___d6322 = 2'd0; + endcase + end + always@(pending_spaces_ext__h145988 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5395 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5400 or + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5405) + begin + case (pending_spaces_ext__h145988) + 3'd0: + CASE_pending_spaces_ext45988_0_IF_NOT_f22f3_em_ETC__q380 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5395; + 3'd1: + CASE_pending_spaces_ext45988_0_IF_NOT_f22f3_em_ETC__q380 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5400; + 3'd2: + CASE_pending_spaces_ext45988_0_IF_NOT_f22f3_em_ETC__q380 = + IF_NOT_f22f3_empty_17_919_AND_NOT_SEL_ARR_f22f_ETC___d5405; + 3'd3, 3'd4, 3'd5, 3'd6, 3'd7: + CASE_pending_spaces_ext45988_0_IF_NOT_f22f3_em_ETC__q380 = 2'd0; + endcase + end + always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) + begin + case (f12f2_deqP) + 1'd0: + CASE_f12f2_deqP_0_NOT_f12f2_data_0_BIT_135_1_N_ETC__q381 = + !f12f2_data_0[135]; + 1'd1: + CASE_f12f2_deqP_0_NOT_f12f2_data_0_BIT_135_1_N_ETC__q381 = + !f12f2_data_1[135]; + endcase + end + always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) + begin + case (f12f2_deqP) + 1'd0: + CASE_f12f2_deqP_0_f12f2_data_0_BITS_134_TO_6_1_ETC__q382 = + f12f2_data_0[134:6]; + 1'd1: + CASE_f12f2_deqP_0_f12f2_data_0_BITS_134_TO_6_1_ETC__q382 = + f12f2_data_1[134:6]; endcase end always@(f22f3_enqReq_lat_0$wget) begin - case (f22f3_enqReq_lat_0$wget[73:70]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - CASE_f22f3_enqReq_lat_0wget_BITS_73_TO_70_0_f_ETC__q216 = - f22f3_enqReq_lat_0$wget[73:70]; - 4'd11: CASE_f22f3_enqReq_lat_0wget_BITS_73_TO_70_0_f_ETC__q216 = 4'd10; - 4'd12: CASE_f22f3_enqReq_lat_0wget_BITS_73_TO_70_0_f_ETC__q216 = 4'd11; - 4'd13: CASE_f22f3_enqReq_lat_0wget_BITS_73_TO_70_0_f_ETC__q216 = 4'd12; - default: CASE_f22f3_enqReq_lat_0wget_BITS_73_TO_70_0_f_ETC__q216 = - 4'd13; + case (f22f3_enqReq_lat_0$wget[75:71]) + 5'd0: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd0; + 5'd1: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd1; + 5'd2: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd2; + 5'd3: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd3; + 5'd4: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd4; + 5'd5: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd5; + 5'd6: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd6; + 5'd7: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd7; + 5'd8: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd8; + 5'd9: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd9; + 5'd11: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd10; + 5'd12: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd11; + 5'd13: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd12; + 5'd15: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = 4'd13; + default: CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 = + 4'd14; endcase end always@(f22f3_enqReq_rl) begin - case (f22f3_enqReq_rl[73:70]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - CASE_f22f3_enqReq_rl_BITS_73_TO_70_0_f22f3_enq_ETC__q217 = - f22f3_enqReq_rl[73:70]; - 4'd11: CASE_f22f3_enqReq_rl_BITS_73_TO_70_0_f22f3_enq_ETC__q217 = 4'd10; - 4'd12: CASE_f22f3_enqReq_rl_BITS_73_TO_70_0_f22f3_enq_ETC__q217 = 4'd11; - 4'd13: CASE_f22f3_enqReq_rl_BITS_73_TO_70_0_f22f3_enq_ETC__q217 = 4'd12; - default: CASE_f22f3_enqReq_rl_BITS_73_TO_70_0_f22f3_enq_ETC__q217 = - 4'd13; + case (f22f3_enqReq_rl[75:71]) + 5'd0: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd0; + 5'd1: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd1; + 5'd2: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd2; + 5'd3: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd3; + 5'd4: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd4; + 5'd5: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd5; + 5'd6: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd6; + 5'd7: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd7; + 5'd8: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd8; + 5'd9: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd9; + 5'd11: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd10; + 5'd12: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd11; + 5'd13: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd12; + 5'd15: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = 4'd13; + default: CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384 = + 4'd14; endcase end - always@(IF_f22f3_enqReq_lat_0_whas__14_THEN_IF_f22f3_e_ETC___d400) + always@(WILL_FIRE_RL_doFetch2 or + CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 or + CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384) begin - case (IF_f22f3_enqReq_lat_0_whas__14_THEN_IF_f22f3_e_ETC___d400) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - CASE_IF_f22f3_enqReq_lat_0_whas__14_THEN_IF_f2_ETC__q218 = - IF_f22f3_enqReq_lat_0_whas__14_THEN_IF_f22f3_e_ETC___d400; - 4'd10: CASE_IF_f22f3_enqReq_lat_0_whas__14_THEN_IF_f2_ETC__q218 = 4'd11; - 4'd11: CASE_IF_f22f3_enqReq_lat_0_whas__14_THEN_IF_f2_ETC__q218 = 4'd12; - 4'd12: CASE_IF_f22f3_enqReq_lat_0_whas__14_THEN_IF_f2_ETC__q218 = 4'd13; - default: CASE_IF_f22f3_enqReq_lat_0_whas__14_THEN_IF_f2_ETC__q218 = - 4'd15; + case (WILL_FIRE_RL_doFetch2 ? + CASE_f22f3_enqReq_lat_0wget_BITS_75_TO_71_0_0_ETC__q383 : + CASE_f22f3_enqReq_rl_BITS_75_TO_71_0_0_1_1_2_2_ETC__q384) + 4'd0: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd0; + 4'd1: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd1; + 4'd2: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd2; + 4'd3: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd3; + 4'd4: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd4; + 4'd5: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd5; + 4'd6: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd6; + 4'd7: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd7; + 4'd8: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd8; + 4'd9: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd9; + 4'd10: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd11; + 4'd11: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd12; + 4'd12: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd13; + 4'd13: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = 5'd15; + default: CASE_IF_WILL_FIRE_RL_doFetch2_THEN_CASE_f22f3__ETC__q385 = + 5'd28; endcase end always@(f32d_enqReq_lat_0$wget) begin - case (f32d_enqReq_lat_0$wget[73:70]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - CASE_f32d_enqReq_lat_0wget_BITS_73_TO_70_0_f3_ETC__q219 = - f32d_enqReq_lat_0$wget[73:70]; - 4'd11: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_70_0_f3_ETC__q219 = 4'd10; - 4'd12: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_70_0_f3_ETC__q219 = 4'd11; - 4'd13: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_70_0_f3_ETC__q219 = 4'd12; - default: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_70_0_f3_ETC__q219 = - 4'd13; + case (f32d_enqReq_lat_0$wget[73:69]) + 5'd0: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd0; + 5'd1: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd1; + 5'd2: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd2; + 5'd3: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd3; + 5'd4: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd4; + 5'd5: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd5; + 5'd6: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd6; + 5'd7: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd7; + 5'd8: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd8; + 5'd9: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd9; + 5'd11: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd10; + 5'd12: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd11; + 5'd13: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd12; + 5'd15: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = 4'd13; + default: CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 = + 4'd14; endcase end always@(f32d_enqReq_rl) begin - case (f32d_enqReq_rl[73:70]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - CASE_f32d_enqReq_rl_BITS_73_TO_70_0_f32d_enqRe_ETC__q220 = - f32d_enqReq_rl[73:70]; - 4'd11: CASE_f32d_enqReq_rl_BITS_73_TO_70_0_f32d_enqRe_ETC__q220 = 4'd10; - 4'd12: CASE_f32d_enqReq_rl_BITS_73_TO_70_0_f32d_enqRe_ETC__q220 = 4'd11; - 4'd13: CASE_f32d_enqReq_rl_BITS_73_TO_70_0_f32d_enqRe_ETC__q220 = 4'd12; - default: CASE_f32d_enqReq_rl_BITS_73_TO_70_0_f32d_enqRe_ETC__q220 = - 4'd13; + case (f32d_enqReq_rl[73:69]) + 5'd0: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd0; + 5'd1: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd1; + 5'd2: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd2; + 5'd3: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd3; + 5'd4: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd4; + 5'd5: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd5; + 5'd6: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd6; + 5'd7: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd7; + 5'd8: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd8; + 5'd9: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd9; + 5'd11: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd10; + 5'd12: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd11; + 5'd13: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd12; + 5'd15: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = 4'd13; + default: CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387 = + 4'd14; endcase end - always@(IF_f32d_enqReq_lat_0_whas__46_THEN_IF_f32d_enq_ETC___d732) + always@(f32d_enqReq_lat_0$whas or + CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 or + CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387) begin - case (IF_f32d_enqReq_lat_0_whas__46_THEN_IF_f32d_enq_ETC___d732) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - CASE_IF_f32d_enqReq_lat_0_whas__46_THEN_IF_f32_ETC__q221 = - IF_f32d_enqReq_lat_0_whas__46_THEN_IF_f32d_enq_ETC___d732; - 4'd10: CASE_IF_f32d_enqReq_lat_0_whas__46_THEN_IF_f32_ETC__q221 = 4'd11; - 4'd11: CASE_IF_f32d_enqReq_lat_0_whas__46_THEN_IF_f32_ETC__q221 = 4'd12; - 4'd12: CASE_IF_f32d_enqReq_lat_0_whas__46_THEN_IF_f32_ETC__q221 = 4'd13; - default: CASE_IF_f32d_enqReq_lat_0_whas__46_THEN_IF_f32_ETC__q221 = - 4'd15; + case (f32d_enqReq_lat_0$whas ? + CASE_f32d_enqReq_lat_0wget_BITS_73_TO_69_0_0__ETC__q386 : + CASE_f32d_enqReq_rl_BITS_73_TO_69_0_0_1_1_2_2__ETC__q387) + 4'd0: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd0; + 4'd1: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd1; + 4'd2: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd2; + 4'd3: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd3; + 4'd4: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd4; + 4'd5: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd5; + 4'd6: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd6; + 4'd7: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd7; + 4'd8: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd8; + 4'd9: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd9; + 4'd10: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd11; + 4'd11: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd12; + 4'd12: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd13; + 4'd13: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = 5'd15; + default: CASE_IF_f32d_enqReq_lat_0whas_THEN_CASE_f32d__ETC__q388 = + 5'd28; + endcase + end + always@(out_fifo_enqueueElement_0_lat_0$wget) + begin + case (out_fifo_enqueueElement_0_lat_0$wget[235:232]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114 = + out_fifo_enqueueElement_0_lat_0$wget[235:232]; + default: IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1114 = + 4'd11; + endcase + end + always@(out_fifo_enqueueElement_0_lat_0$wget) + begin + case (out_fifo_enqueueElement_0_lat_0$wget[231:229]) + 3'd2, 3'd3: + IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1233 = + out_fifo_enqueueElement_0_lat_0$wget[231:229]; + default: IF_out_fifo_enqueueElement_0_lat_0_wget__05_BI_ETC___d1233 = + 3'd4; + endcase + end + always@(out_fifo_enqueueElement_1_lat_0$wget) + begin + case (out_fifo_enqueueElement_1_lat_0$wget[235:232]) + 4'd6, 4'd7, 4'd8, 4'd9, 4'd10: + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281 = + out_fifo_enqueueElement_1_lat_0$wget[235:232]; + default: IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2281 = + 4'd11; + endcase + end + always@(out_fifo_enqueueElement_1_lat_0$wget) + begin + case (out_fifo_enqueueElement_1_lat_0$wget[231:229]) + 3'd2, 3'd3: + IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2400 = + out_fifo_enqueueElement_1_lat_0$wget[231:229]; + default: IF_out_fifo_enqueueElement_1_lat_0_wget__073_B_ETC___d2400 = + 3'd4; endcase end @@ -19194,53 +28268,58 @@ module mkFetchStage(CLK, begin if (RST_N == `BSV_RESET_VALUE) begin - decode_epoch <= `BSV_ASSIGNMENT_DELAY 1'd0; + decode_epoch_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; + ehr_pending_straddle_rl <= `BSV_ASSIGNMENT_DELAY + 147'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f12f2_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - f12f2_data_0 <= `BSV_ASSIGNMENT_DELAY 134'd0; - f12f2_data_1 <= `BSV_ASSIGNMENT_DELAY 134'd0; + f12f2_data_0 <= `BSV_ASSIGNMENT_DELAY + 267'h0000000000000000000000000000000002AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80; + f12f2_data_1 <= `BSV_ASSIGNMENT_DELAY + 267'h0000000000000000000000000000000002AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80; f12f2_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0; f12f2_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; f12f2_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; f12f2_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0; f12f2_enqReq_rl <= `BSV_ASSIGNMENT_DELAY - 135'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 268'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f12f2_full <= `BSV_ASSIGNMENT_DELAY 1'd0; f22f3_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; f22f3_data_0 <= `BSV_ASSIGNMENT_DELAY - 268'h0000000000000000000000000000000000000000000000002800000000000000000; + 338'h0000000000000000000000000000000001555555555555555555555555555555545000000000000000000; f22f3_data_1 <= `BSV_ASSIGNMENT_DELAY - 268'h0000000000000000000000000000000000000000000000002800000000000000000; + 338'h0000000000000000000000000000000001555555555555555555555555555555545000000000000000000; f22f3_data_2 <= `BSV_ASSIGNMENT_DELAY - 268'h0000000000000000000000000000000000000000000000002800000000000000000; + 338'h0000000000000000000000000000000001555555555555555555555555555555545000000000000000000; f22f3_data_3 <= `BSV_ASSIGNMENT_DELAY - 268'h0000000000000000000000000000000000000000000000002800000000000000000; + 338'h0000000000000000000000000000000001555555555555555555555555555555545000000000000000000; f22f3_deqP <= `BSV_ASSIGNMENT_DELAY 2'd0; f22f3_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; f22f3_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; f22f3_enqP <= `BSV_ASSIGNMENT_DELAY 2'd0; f22f3_enqReq_rl <= `BSV_ASSIGNMENT_DELAY - 269'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 339'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f22f3_full <= `BSV_ASSIGNMENT_DELAY 1'd0; f32d_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; f32d_data_0 <= `BSV_ASSIGNMENT_DELAY - 268'h0000000000000000000000000000000000000000000000002800000000000000000; + 335'h000000000000000000000000000000000000000000000000000000000000000001400000000000000000; f32d_data_1 <= `BSV_ASSIGNMENT_DELAY - 268'h0000000000000000000000000000000000000000000000002800000000000000000; + 335'h000000000000000000000000000000000000000000000000000000000000000001400000000000000000; f32d_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0; f32d_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; f32d_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; f32d_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0; f32d_enqReq_rl <= `BSV_ASSIGNMENT_DELAY - 269'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 336'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f32d_full <= `BSV_ASSIGNMENT_DELAY 1'd0; f_main_epoch <= `BSV_ASSIGNMENT_DELAY 4'd0; - instdata_data_0 <= `BSV_ASSIGNMENT_DELAY 260'd0; - instdata_data_1 <= `BSV_ASSIGNMENT_DELAY 260'd0; + fetch3_epoch <= `BSV_ASSIGNMENT_DELAY 1'd0; + instdata_data_0 <= `BSV_ASSIGNMENT_DELAY 390'd0; + instdata_data_1 <= `BSV_ASSIGNMENT_DELAY 390'd0; instdata_deqP_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; instdata_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1; instdata_enqP_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; instdata_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - napTrainByDecQ_data_0 <= `BSV_ASSIGNMENT_DELAY 128'd0; + napTrainByDecQ_data_0 <= `BSV_ASSIGNMENT_DELAY 258'd0; napTrainByDecQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1; napTrainByDecQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; nextAddrPred_valid_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -19501,28 +28580,33 @@ module mkFetchStage(CLK, nextAddrPred_valid_99 <= `BSV_ASSIGNMENT_DELAY 1'd0; out_fifo_dequeueFifo_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; out_fifo_enqueueElement_0_rl <= `BSV_ASSIGNMENT_DELAY - 389'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 592'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; out_fifo_enqueueElement_1_rl <= `BSV_ASSIGNMENT_DELAY - 389'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 592'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; out_fifo_enqueueFifo_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; out_fifo_willDequeue_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; out_fifo_willDequeue_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - pc_reg_rl <= `BSV_ASSIGNMENT_DELAY 64'd0; + pc_reg_rl <= `BSV_ASSIGNMENT_DELAY + 129'h000001FFFFC0180040000000000000000; perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 2'd0; perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 3'd2; perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_pending_straddle <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_pending_decode <= `BSV_ASSIGNMENT_DELAY + 585'h000001FFFFC01800400000000000000000000000000000000000003FFFF803000800000000000000000000000000000000000007FFFF006001000000000000000000000000000000000; started <= `BSV_ASSIGNMENT_DELAY 1'd0; waitForFlush <= `BSV_ASSIGNMENT_DELAY 1'd0; waitForRedirect <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin - if (decode_epoch$EN) - decode_epoch <= `BSV_ASSIGNMENT_DELAY decode_epoch$D_IN; + if (decode_epoch_rl$EN) + decode_epoch_rl <= `BSV_ASSIGNMENT_DELAY decode_epoch_rl$D_IN; + if (ehr_pending_straddle_rl$EN) + ehr_pending_straddle_rl <= `BSV_ASSIGNMENT_DELAY + ehr_pending_straddle_rl$D_IN; if (f12f2_clearReq_rl$EN) f12f2_clearReq_rl <= `BSV_ASSIGNMENT_DELAY f12f2_clearReq_rl$D_IN; if (f12f2_data_0$EN) @@ -19580,6 +28664,8 @@ module mkFetchStage(CLK, if (f32d_full$EN) f32d_full <= `BSV_ASSIGNMENT_DELAY f32d_full$D_IN; if (f_main_epoch$EN) f_main_epoch <= `BSV_ASSIGNMENT_DELAY f_main_epoch$D_IN; + if (fetch3_epoch$EN) + fetch3_epoch <= `BSV_ASSIGNMENT_DELAY fetch3_epoch$D_IN; if (instdata_data_0$EN) instdata_data_0 <= `BSV_ASSIGNMENT_DELAY instdata_data_0$D_IN; if (instdata_data_1$EN) @@ -20401,19 +29487,18 @@ module mkFetchStage(CLK, perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_enqReq_rl$D_IN; if (perfReqQ_full$EN) perfReqQ_full <= `BSV_ASSIGNMENT_DELAY perfReqQ_full$D_IN; - if (rg_pending_straddle$EN) - rg_pending_straddle <= `BSV_ASSIGNMENT_DELAY - rg_pending_straddle$D_IN; + if (rg_pending_decode$EN) + rg_pending_decode <= `BSV_ASSIGNMENT_DELAY rg_pending_decode$D_IN; if (started$EN) started <= `BSV_ASSIGNMENT_DELAY started$D_IN; if (waitForFlush$EN) waitForFlush <= `BSV_ASSIGNMENT_DELAY waitForFlush$D_IN; if (waitForRedirect$EN) waitForRedirect <= `BSV_ASSIGNMENT_DELAY waitForRedirect$D_IN; end - if (rg_half_inst_lsbs$EN) - rg_half_inst_lsbs <= `BSV_ASSIGNMENT_DELAY rg_half_inst_lsbs$D_IN; - if (rg_half_inst_pc$EN) - rg_half_inst_pc <= `BSV_ASSIGNMENT_DELAY rg_half_inst_pc$D_IN; + if (rg_pending_f32d$EN) + rg_pending_f32d <= `BSV_ASSIGNMENT_DELAY rg_pending_f32d$D_IN; + if (rg_pending_n_items$EN) + rg_pending_n_items <= `BSV_ASSIGNMENT_DELAY rg_pending_n_items$D_IN; end // synopsys translate_off @@ -20421,54 +29506,60 @@ module mkFetchStage(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - decode_epoch = 1'h0; + decode_epoch_rl = 1'h0; + ehr_pending_straddle_rl = 147'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f12f2_clearReq_rl = 1'h0; - f12f2_data_0 = 134'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f12f2_data_1 = 134'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + f12f2_data_0 = + 267'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + f12f2_data_1 = + 267'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f12f2_deqP = 1'h0; f12f2_deqReq_rl = 1'h0; f12f2_empty = 1'h0; f12f2_enqP = 1'h0; - f12f2_enqReq_rl = 135'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + f12f2_enqReq_rl = + 268'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f12f2_full = 1'h0; f22f3_clearReq_rl = 1'h0; f22f3_data_0 = - 268'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 338'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f22f3_data_1 = - 268'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 338'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f22f3_data_2 = - 268'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 338'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f22f3_data_3 = - 268'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 338'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f22f3_deqP = 2'h2; f22f3_deqReq_rl = 1'h0; f22f3_empty = 1'h0; f22f3_enqP = 2'h2; f22f3_enqReq_rl = - 269'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 339'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f22f3_full = 1'h0; f32d_clearReq_rl = 1'h0; f32d_data_0 = - 268'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 335'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f32d_data_1 = - 268'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 335'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f32d_deqP = 1'h0; f32d_deqReq_rl = 1'h0; f32d_empty = 1'h0; f32d_enqP = 1'h0; f32d_enqReq_rl = - 269'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 336'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; f32d_full = 1'h0; f_main_epoch = 4'hA; + fetch3_epoch = 1'h0; instdata_data_0 = - 260'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 390'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; instdata_data_1 = - 260'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 390'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; instdata_deqP_rl = 1'h0; instdata_empty_rl = 1'h0; instdata_enqP_rl = 1'h0; instdata_full_rl = 1'h0; - napTrainByDecQ_data_0 = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + napTrainByDecQ_data_0 = + 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; napTrainByDecQ_empty_rl = 1'h0; napTrainByDecQ_full_rl = 1'h0; nextAddrPred_valid_0 = 1'h0; @@ -20729,22 +29820,24 @@ module mkFetchStage(CLK, nextAddrPred_valid_99 = 1'h0; out_fifo_dequeueFifo_rl = 1'h0; out_fifo_enqueueElement_0_rl = - 389'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 592'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; out_fifo_enqueueElement_1_rl = - 389'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 592'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; out_fifo_enqueueFifo_rl = 1'h0; out_fifo_willDequeue_0_rl = 1'h0; out_fifo_willDequeue_1_rl = 1'h0; - pc_reg_rl = 64'hAAAAAAAAAAAAAAAA; + pc_reg_rl = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; perfReqQ_clearReq_rl = 1'h0; perfReqQ_data_0 = 2'h2; perfReqQ_deqReq_rl = 1'h0; perfReqQ_empty = 1'h0; perfReqQ_enqReq_rl = 3'h2; perfReqQ_full = 1'h0; - rg_half_inst_lsbs = 16'hAAAA; - rg_half_inst_pc = 64'hAAAAAAAAAAAAAAAA; - rg_pending_straddle = 1'h0; + rg_pending_decode = + 585'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + rg_pending_f32d = + 334'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + rg_pending_n_items = 2'h2; started = 1'h0; waitForFlush = 1'h0; waitForRedirect = 1'h0; @@ -20760,339 +29853,12 @@ module mkFetchStage(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $display("Fetch3: straddle: pc mismatch"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write("Fetch3: f22f3.first: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write("<"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write("'h%h", value__h117642); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write(","); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write("Fetch2ToFetch3 { ", "pc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write("'h%h", start_PC__h117515); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write(", ", "phys_pc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write("'h%h", value__h117654); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write(", ", "pred_next_pc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write("'h%h", value__h117656); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write(", ", "cause: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3569) - $write("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483) - $write("tagged Valid "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3569) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686) - $write("InstAddrMisaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 && - SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3697) - $write("InstAccessFault"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3715) - $write("IllegalInst"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle_514_AND_NOT_SEL_ARR_f22f3__ETC___d3728) - $write("Breakpoint"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - NOT_SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_5_ETC___d3742) - $write("LoadAddrMisaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - NOT_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_47_ETC___d3757) - $write("LoadAccessFault"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3773) - $write("StoreAddrMisaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - !SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70_573__ETC___d3686 && - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3790) - $write("StoreAccessFault"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3814) - $write("EnvCallU"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle_514_AND_NOT_SEL_ARR_f22f3__ETC___d3833) - $write("EnvCallS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - NOT_SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_5_ETC___d3853) - $write("EnvCallM"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - NOT_SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_47_ETC___d3874) - $write("InstPageFault"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3896) - $write("LoadPageFault"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_74_471_472_NO_ETC___d3483 && - NOT_SEL_ARR_IF_f22f3_data_0_470_BITS_73_TO_70__ETC___d3913) - $write("StorePageFault"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write("'h%h", value__h118910); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write(", ", "access_mmio: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - SEL_ARR_NOT_f22f3_data_0_470_BIT_5_486_924_NOT_ETC___d3929) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_5_486_924_NOT_ETC___d3929) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write(", ", "decode_epoch: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - SEL_ARR_NOT_f22f3_data_0_470_BIT_4_496_937_NOT_ETC___d3942) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523 && - !SEL_ARR_NOT_f22f3_data_0_470_BIT_4_496_937_NOT_ETC___d3942) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write(", ", "main_epoch: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write("'h%h", - SEL_ARR_f22f3_data_0_470_BITS_3_TO_0_950_f22f3_ETC___d3955, - " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write(">"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write("Fetch3: inst_d: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_470_BIT_4_496_f22f3_data__ETC___d3502 && - rg_pending_straddle && - !SEL_ARR_f22f3_data_0_470_BITS_266_TO_203_515_f_ETC___d3523) - $write("\n"); + f22f3_empty_17_OR_SEL_ARR_f22f3_data_0_920_BIT_ETC___d5012 && + IF_rg_pending_n_items_951_EQ_0_952_THEN_rg_pen_ETC___d5081 && + IF_SEL_ARR_f22f3_data_0_920_BITS_335_TO_207_02_ETC___d5203) + $display("FetchStage.fav_parse_insts: straddle: pc mismatch: pc = 0x%0h but s_pc = 0x%0h", + pc_start__h114675[63:0], + ehr_pending_straddle_rl[145:17]); end // synopsys translate_on endmodule // mkFetchStage diff --git a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v index 382f1e2..1bc00b3 100644 --- a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v @@ -1,74 +1,67 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// +// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // +// On Fri Jun 5 17:49:03 BST 2020 // // // Ports: // Name I/O size props +// master0_awid O 6 +// master0_awaddr O 64 +// master0_awlen O 8 +// master0_awsize O 3 +// master0_awburst O 2 +// master0_awlock O 1 +// master0_awcache O 4 +// master0_awprot O 3 +// master0_awqos O 4 +// master0_awregion O 4 // master0_awvalid O 1 -// master0_awid O 4 reg -// master0_awaddr O 64 reg -// master0_awlen O 8 reg -// master0_awsize O 3 reg -// master0_awburst O 2 reg -// master0_awlock O 1 reg -// master0_awcache O 4 reg -// master0_awprot O 3 reg -// master0_awqos O 4 reg -// master0_awregion O 4 reg +// master0_wdata O 64 +// master0_wstrb O 8 +// master0_wlast O 1 // master0_wvalid O 1 -// master0_wid O 4 reg -// master0_wdata O 64 reg -// master0_wstrb O 8 reg -// master0_wlast O 1 reg // master0_bready O 1 +// master0_arid O 6 +// master0_araddr O 64 +// master0_arlen O 8 +// master0_arsize O 3 +// master0_arburst O 2 +// master0_arlock O 1 +// master0_arcache O 4 +// master0_arprot O 3 +// master0_arqos O 4 +// master0_arregion O 4 // master0_arvalid O 1 -// master0_arid O 4 reg -// master0_araddr O 64 reg -// master0_arlen O 8 reg -// master0_arsize O 3 reg -// master0_arburst O 2 reg -// master0_arlock O 1 reg -// master0_arcache O 4 reg -// master0_arprot O 3 reg -// master0_arqos O 4 reg -// master0_arregion O 4 reg // master0_rready O 1 +// master1_awid O 6 +// master1_awaddr O 64 +// master1_awlen O 8 +// master1_awsize O 3 +// master1_awburst O 2 +// master1_awlock O 1 +// master1_awcache O 4 +// master1_awprot O 3 +// master1_awqos O 4 +// master1_awregion O 4 // master1_awvalid O 1 reg -// master1_awid O 4 reg -// master1_awaddr O 64 reg -// master1_awlen O 8 reg -// master1_awsize O 3 reg -// master1_awburst O 2 reg -// master1_awlock O 1 reg -// master1_awcache O 4 reg -// master1_awprot O 3 reg -// master1_awqos O 4 reg -// master1_awregion O 4 reg -// master1_wvalid O 1 reg -// master1_wid O 4 reg // master1_wdata O 64 reg // master1_wstrb O 8 reg // master1_wlast O 1 reg +// master1_wvalid O 1 reg // master1_bready O 1 reg +// master1_arid O 6 +// master1_araddr O 64 +// master1_arlen O 8 +// master1_arsize O 3 +// master1_arburst O 2 +// master1_arlock O 1 +// master1_arcache O 4 +// master1_arprot O 3 +// master1_arqos O 4 +// master1_arregion O 4 // master1_arvalid O 1 reg -// master1_arid O 4 reg -// master1_araddr O 64 reg -// master1_arlen O 8 reg -// master1_arsize O 3 reg -// master1_arburst O 2 reg -// master1_arlock O 1 reg -// master1_arcache O 4 reg -// master1_arprot O 3 reg -// master1_arqos O 4 reg -// master1_arregion O 4 reg // master1_rready O 1 reg -// tv_verifier_info_tx_tvalid O 1 reg -// tv_verifier_info_tx_tdata O 608 reg -// tv_verifier_info_tx_tstrb O 76 reg -// tv_verifier_info_tx_tkeep O 76 reg -// tv_verifier_info_tx_tlast O 1 reg // jtag_tdo O 1 // CLK_jtag_tclk_out O 1 clock // CLK_GATE_jtag_tclk_out O 1 const @@ -76,35 +69,33 @@ // RST_N I 1 reset // master0_awready I 1 // master0_wready I 1 -// master0_bvalid I 1 -// master0_bid I 4 reg -// master0_bresp I 2 reg +// master0_bid I 6 +// master0_bresp I 2 // master0_arready I 1 -// master0_rvalid I 1 -// master0_rid I 4 reg -// master0_rdata I 64 reg -// master0_rresp I 2 reg -// master0_rlast I 1 reg +// master0_rid I 6 +// master0_rdata I 64 +// master0_rresp I 2 +// master0_rlast I 1 // master1_awready I 1 // master1_wready I 1 -// master1_bvalid I 1 -// master1_bid I 4 reg +// master1_bid I 6 reg // master1_bresp I 2 reg // master1_arready I 1 -// master1_rvalid I 1 -// master1_rid I 4 reg +// master1_rid I 6 reg // master1_rdata I 64 reg // master1_rresp I 2 reg // master1_rlast I 1 reg // cpu_external_interrupt_req I 16 -// debug_external_interrupt_req_set_not_clear I 1 -// tv_verifier_info_tx_tready I 1 +// debug_external_interrupt_req_set_not_clear I 1 unused // jtag_tdi I 1 // jtag_tms I 1 // jtag_tclk I 1 +// master0_bvalid I 1 +// master0_rvalid I 1 +// master1_bvalid I 1 +// master1_rvalid I 1 // -// Combinational paths from inputs to outputs: -// (master0_awready, master0_wready) -> master0_bready +// No combinational paths from inputs to outputs // // @@ -124,8 +115,6 @@ module mkP3_Core(CLK, RST_N, - master0_awvalid, - master0_awid, master0_awaddr, @@ -146,28 +135,26 @@ module mkP3_Core(CLK, master0_awregion, + master0_awvalid, + master0_awready, - master0_wvalid, - - master0_wid, - master0_wdata, master0_wstrb, master0_wlast, + master0_wvalid, + master0_wready, - master0_bvalid, master0_bid, master0_bresp, + master0_bvalid, master0_bready, - master0_arvalid, - master0_arid, master0_araddr, @@ -188,18 +175,18 @@ module mkP3_Core(CLK, master0_arregion, + master0_arvalid, + master0_arready, - master0_rvalid, master0_rid, master0_rdata, master0_rresp, master0_rlast, + master0_rvalid, master0_rready, - master1_awvalid, - master1_awid, master1_awaddr, @@ -220,28 +207,26 @@ module mkP3_Core(CLK, master1_awregion, + master1_awvalid, + master1_awready, - master1_wvalid, - - master1_wid, - master1_wdata, master1_wstrb, master1_wlast, + master1_wvalid, + master1_wready, - master1_bvalid, master1_bid, master1_bresp, + master1_bvalid, master1_bready, - master1_arvalid, - master1_arid, master1_araddr, @@ -262,13 +247,15 @@ module mkP3_Core(CLK, master1_arregion, + master1_arvalid, + master1_arready, - master1_rvalid, master1_rid, master1_rdata, master1_rresp, master1_rlast, + master1_rvalid, master1_rready, @@ -276,18 +263,6 @@ module mkP3_Core(CLK, debug_external_interrupt_req_set_not_clear, - tv_verifier_info_tx_tvalid, - - tv_verifier_info_tx_tdata, - - tv_verifier_info_tx_tstrb, - - tv_verifier_info_tx_tkeep, - - tv_verifier_info_tx_tlast, - - tv_verifier_info_tx_tready, - jtag_tdi, jtag_tms, @@ -301,232 +276,226 @@ module mkP3_Core(CLK, input CLK; input RST_N; - // value method master0_m_awvalid - output master0_awvalid; + // value method master0_aw_awid + output [5 : 0] master0_awid; - // value method master0_m_awid - output [3 : 0] master0_awid; - - // value method master0_m_awaddr + // value method master0_aw_awaddr output [63 : 0] master0_awaddr; - // value method master0_m_awlen + // value method master0_aw_awlen output [7 : 0] master0_awlen; - // value method master0_m_awsize + // value method master0_aw_awsize output [2 : 0] master0_awsize; - // value method master0_m_awburst + // value method master0_aw_awburst output [1 : 0] master0_awburst; - // value method master0_m_awlock + // value method master0_aw_awlock output master0_awlock; - // value method master0_m_awcache + // value method master0_aw_awcache output [3 : 0] master0_awcache; - // value method master0_m_awprot + // value method master0_aw_awprot output [2 : 0] master0_awprot; - // value method master0_m_awqos + // value method master0_aw_awqos output [3 : 0] master0_awqos; - // value method master0_m_awregion + // value method master0_aw_awregion output [3 : 0] master0_awregion; - // value method master0_m_awuser + // value method master0_aw_awuser - // action method master0_m_awready + // value method master0_aw_awvalid + output master0_awvalid; + + // action method master0_aw_awready input master0_awready; - // value method master0_m_wvalid - output master0_wvalid; - - // value method master0_m_wid - output [3 : 0] master0_wid; - - // value method master0_m_wdata + // value method master0_w_wdata output [63 : 0] master0_wdata; - // value method master0_m_wstrb + // value method master0_w_wstrb output [7 : 0] master0_wstrb; - // value method master0_m_wlast + // value method master0_w_wlast output master0_wlast; - // value method master0_m_wuser + // value method master0_w_wuser - // action method master0_m_wready + // value method master0_w_wvalid + output master0_wvalid; + + // action method master0_w_wready input master0_wready; - // action method master0_m_bvalid - input master0_bvalid; - input [3 : 0] master0_bid; + // action method master0_b_bflit + input [5 : 0] master0_bid; input [1 : 0] master0_bresp; + input master0_bvalid; - // value method master0_m_bready + // value method master0_b_bready output master0_bready; - // value method master0_m_arvalid - output master0_arvalid; + // value method master0_ar_arid + output [5 : 0] master0_arid; - // value method master0_m_arid - output [3 : 0] master0_arid; - - // value method master0_m_araddr + // value method master0_ar_araddr output [63 : 0] master0_araddr; - // value method master0_m_arlen + // value method master0_ar_arlen output [7 : 0] master0_arlen; - // value method master0_m_arsize + // value method master0_ar_arsize output [2 : 0] master0_arsize; - // value method master0_m_arburst + // value method master0_ar_arburst output [1 : 0] master0_arburst; - // value method master0_m_arlock + // value method master0_ar_arlock output master0_arlock; - // value method master0_m_arcache + // value method master0_ar_arcache output [3 : 0] master0_arcache; - // value method master0_m_arprot + // value method master0_ar_arprot output [2 : 0] master0_arprot; - // value method master0_m_arqos + // value method master0_ar_arqos output [3 : 0] master0_arqos; - // value method master0_m_arregion + // value method master0_ar_arregion output [3 : 0] master0_arregion; - // value method master0_m_aruser + // value method master0_ar_aruser - // action method master0_m_arready + // value method master0_ar_arvalid + output master0_arvalid; + + // action method master0_ar_arready input master0_arready; - // action method master0_m_rvalid - input master0_rvalid; - input [3 : 0] master0_rid; + // action method master0_r_rflit + input [5 : 0] master0_rid; input [63 : 0] master0_rdata; input [1 : 0] master0_rresp; input master0_rlast; + input master0_rvalid; - // value method master0_m_rready + // value method master0_r_rready output master0_rready; - // value method master1_m_awvalid - output master1_awvalid; + // value method master1_aw_awid + output [5 : 0] master1_awid; - // value method master1_m_awid - output [3 : 0] master1_awid; - - // value method master1_m_awaddr + // value method master1_aw_awaddr output [63 : 0] master1_awaddr; - // value method master1_m_awlen + // value method master1_aw_awlen output [7 : 0] master1_awlen; - // value method master1_m_awsize + // value method master1_aw_awsize output [2 : 0] master1_awsize; - // value method master1_m_awburst + // value method master1_aw_awburst output [1 : 0] master1_awburst; - // value method master1_m_awlock + // value method master1_aw_awlock output master1_awlock; - // value method master1_m_awcache + // value method master1_aw_awcache output [3 : 0] master1_awcache; - // value method master1_m_awprot + // value method master1_aw_awprot output [2 : 0] master1_awprot; - // value method master1_m_awqos + // value method master1_aw_awqos output [3 : 0] master1_awqos; - // value method master1_m_awregion + // value method master1_aw_awregion output [3 : 0] master1_awregion; - // value method master1_m_awuser + // value method master1_aw_awuser - // action method master1_m_awready + // value method master1_aw_awvalid + output master1_awvalid; + + // action method master1_aw_awready input master1_awready; - // value method master1_m_wvalid - output master1_wvalid; - - // value method master1_m_wid - output [3 : 0] master1_wid; - - // value method master1_m_wdata + // value method master1_w_wdata output [63 : 0] master1_wdata; - // value method master1_m_wstrb + // value method master1_w_wstrb output [7 : 0] master1_wstrb; - // value method master1_m_wlast + // value method master1_w_wlast output master1_wlast; - // value method master1_m_wuser + // value method master1_w_wuser - // action method master1_m_wready + // value method master1_w_wvalid + output master1_wvalid; + + // action method master1_w_wready input master1_wready; - // action method master1_m_bvalid - input master1_bvalid; - input [3 : 0] master1_bid; + // action method master1_b_bflit + input [5 : 0] master1_bid; input [1 : 0] master1_bresp; + input master1_bvalid; - // value method master1_m_bready + // value method master1_b_bready output master1_bready; - // value method master1_m_arvalid - output master1_arvalid; + // value method master1_ar_arid + output [5 : 0] master1_arid; - // value method master1_m_arid - output [3 : 0] master1_arid; - - // value method master1_m_araddr + // value method master1_ar_araddr output [63 : 0] master1_araddr; - // value method master1_m_arlen + // value method master1_ar_arlen output [7 : 0] master1_arlen; - // value method master1_m_arsize + // value method master1_ar_arsize output [2 : 0] master1_arsize; - // value method master1_m_arburst + // value method master1_ar_arburst output [1 : 0] master1_arburst; - // value method master1_m_arlock + // value method master1_ar_arlock output master1_arlock; - // value method master1_m_arcache + // value method master1_ar_arcache output [3 : 0] master1_arcache; - // value method master1_m_arprot + // value method master1_ar_arprot output [2 : 0] master1_arprot; - // value method master1_m_arqos + // value method master1_ar_arqos output [3 : 0] master1_arqos; - // value method master1_m_arregion + // value method master1_ar_arregion output [3 : 0] master1_arregion; - // value method master1_m_aruser + // value method master1_ar_aruser - // action method master1_m_arready + // value method master1_ar_arvalid + output master1_arvalid; + + // action method master1_ar_arready input master1_arready; - // action method master1_m_rvalid - input master1_rvalid; - input [3 : 0] master1_rid; + // action method master1_r_rflit + input [5 : 0] master1_rid; input [63 : 0] master1_rdata; input [1 : 0] master1_rresp; input master1_rlast; + input master1_rvalid; - // value method master1_m_rready + // value method master1_r_rready output master1_rready; // action method interrupt_reqs @@ -535,30 +504,6 @@ module mkP3_Core(CLK, // action method debug_external_interrupt_req input debug_external_interrupt_req_set_not_clear; - // value method tv_verifier_info_tx_m_tvalid - output tv_verifier_info_tx_tvalid; - - // value method tv_verifier_info_tx_m_tid - - // value method tv_verifier_info_tx_m_tdata - output [607 : 0] tv_verifier_info_tx_tdata; - - // value method tv_verifier_info_tx_m_tstrb - output [75 : 0] tv_verifier_info_tx_tstrb; - - // value method tv_verifier_info_tx_m_tkeep - output [75 : 0] tv_verifier_info_tx_tkeep; - - // value method tv_verifier_info_tx_m_tlast - output tv_verifier_info_tx_tlast; - - // value method tv_verifier_info_tx_m_tdest - - // value method tv_verifier_info_tx_m_tuser - - // action method tv_verifier_info_tx_m_tready - input tv_verifier_info_tx_tready; - // action method jtag_tdi input jtag_tdi; @@ -576,8 +521,6 @@ module mkP3_Core(CLK, output CLK_GATE_jtag_tclk_out; // signals for module outputs - wire [607 : 0] tv_verifier_info_tx_tdata; - wire [75 : 0] tv_verifier_info_tx_tkeep, tv_verifier_info_tx_tstrb; wire [63 : 0] master0_araddr, master0_awaddr, master0_wdata, @@ -590,24 +533,19 @@ module mkP3_Core(CLK, master1_arlen, master1_awlen, master1_wstrb; + wire [5 : 0] master0_arid, master0_awid, master1_arid, master1_awid; wire [3 : 0] master0_arcache, - master0_arid, master0_arqos, master0_arregion, master0_awcache, - master0_awid, master0_awqos, master0_awregion, - master0_wid, master1_arcache, - master1_arid, master1_arqos, master1_arregion, master1_awcache, - master1_awid, master1_awqos, - master1_awregion, - master1_wid; + master1_awregion; wire [2 : 0] master0_arprot, master0_arsize, master0_awprot, @@ -638,9 +576,7 @@ module mkP3_Core(CLK, master1_bready, master1_rready, master1_wlast, - master1_wvalid, - tv_verifier_info_tx_tlast, - tv_verifier_info_tx_tvalid; + master1_wvalid; // inlined wires wire [40 : 0] bus_dmi_req_data_wire$wget; @@ -661,9 +597,14 @@ module mkP3_Core(CLK, reg [33 : 0] bus_dmi_rsp_fifof_q_1$D_IN; wire bus_dmi_rsp_fifof_q_1$EN; - // register rg_once - reg rg_once; - wire rg_once$D_IN, rg_once$EN; + // register rg_corew_start_after_por + reg rg_corew_start_after_por; + wire rg_corew_start_after_por$D_IN, rg_corew_start_after_por$EN; + + // register rg_ndm_reset_delay + reg [7 : 0] rg_ndm_reset_delay; + wire [7 : 0] rg_ndm_reset_delay$D_IN; + wire rg_ndm_reset_delay$EN; // ports of submodule bus_dmi_req_fifof wire [40 : 0] bus_dmi_req_fifof$D_IN, bus_dmi_req_fifof$D_OUT; @@ -674,7 +615,6 @@ module mkP3_Core(CLK, bus_dmi_req_fifof$FULL_N; // ports of submodule corew - wire [607 : 0] corew$tv_verifier_info_get_get; wire [63 : 0] corew$cpu_dmem_master_araddr, corew$cpu_dmem_master_awaddr, corew$cpu_dmem_master_rdata, @@ -683,39 +623,37 @@ module mkP3_Core(CLK, corew$cpu_imem_master_awaddr, corew$cpu_imem_master_rdata, corew$cpu_imem_master_wdata, - corew$set_htif_addrs_fromhost_addr, - corew$set_htif_addrs_tohost_addr, - corew$set_verbosity_logdelay; - wire [31 : 0] corew$dm_dmi_read_data, corew$dm_dmi_write_dm_word; + corew$set_verbosity_logdelay, + corew$start_fromhost_addr, + corew$start_tohost_addr; + wire [31 : 0] corew$dmi_read_data, corew$dmi_write_dm_word; wire [7 : 0] corew$cpu_dmem_master_arlen, corew$cpu_dmem_master_awlen, corew$cpu_dmem_master_wstrb, corew$cpu_imem_master_arlen, corew$cpu_imem_master_awlen, corew$cpu_imem_master_wstrb; - wire [6 : 0] corew$dm_dmi_read_addr_dm_addr, corew$dm_dmi_write_dm_addr; + wire [6 : 0] corew$dmi_read_addr_dm_addr, corew$dmi_write_dm_addr; + wire [5 : 0] corew$cpu_dmem_master_arid, + corew$cpu_dmem_master_awid, + corew$cpu_dmem_master_bid, + corew$cpu_dmem_master_rid, + corew$cpu_imem_master_arid, + corew$cpu_imem_master_awid, + corew$cpu_imem_master_bid, + corew$cpu_imem_master_rid; wire [3 : 0] corew$cpu_dmem_master_arcache, - corew$cpu_dmem_master_arid, corew$cpu_dmem_master_arqos, corew$cpu_dmem_master_arregion, corew$cpu_dmem_master_awcache, - corew$cpu_dmem_master_awid, corew$cpu_dmem_master_awqos, corew$cpu_dmem_master_awregion, - corew$cpu_dmem_master_bid, - corew$cpu_dmem_master_rid, - corew$cpu_dmem_master_wid, corew$cpu_imem_master_arcache, - corew$cpu_imem_master_arid, corew$cpu_imem_master_arqos, corew$cpu_imem_master_arregion, corew$cpu_imem_master_awcache, - corew$cpu_imem_master_awid, corew$cpu_imem_master_awqos, corew$cpu_imem_master_awregion, - corew$cpu_imem_master_bid, - corew$cpu_imem_master_rid, - corew$cpu_imem_master_wid, corew$set_verbosity_verbosity; wire [2 : 0] corew$cpu_dmem_master_arprot, corew$cpu_dmem_master_arsize, @@ -733,22 +671,19 @@ module mkP3_Core(CLK, corew$cpu_imem_master_awburst, corew$cpu_imem_master_bresp, corew$cpu_imem_master_rresp; - wire corew$EN_cpu_reset_server_request_put, - corew$EN_cpu_reset_server_response_get, - corew$EN_dm_dmi_read_addr, - corew$EN_dm_dmi_read_data, - corew$EN_dm_dmi_write, - corew$EN_dm_ndm_reset_req_get_get, - corew$EN_set_htif_addrs, + wire corew$EN_dmi_read_addr, + corew$EN_dmi_read_data, + corew$EN_dmi_write, + corew$EN_ndm_reset_client_request_get, + corew$EN_ndm_reset_client_response_put, corew$EN_set_verbosity, - corew$EN_tv_verifier_info_get_get, - corew$RDY_cpu_reset_server_request_put, - corew$RDY_cpu_reset_server_response_get, - corew$RDY_dm_dmi_read_addr, - corew$RDY_dm_dmi_read_data, - corew$RDY_dm_dmi_write, - corew$RDY_dm_ndm_reset_req_get_get, - corew$RDY_tv_verifier_info_get_get, + corew$EN_start, + corew$RDY_dmi_read_addr, + corew$RDY_dmi_read_data, + corew$RDY_dmi_write, + corew$RDY_ndm_reset_client_request_get, + corew$RDY_ndm_reset_client_response_put, + corew$RDY_start, corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, corew$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, corew$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, @@ -793,7 +728,8 @@ module mkP3_Core(CLK, corew$cpu_imem_master_wlast, corew$cpu_imem_master_wready, corew$cpu_imem_master_wvalid, - corew$debug_external_interrupt_req_set_not_clear; + corew$ndm_reset_client_response_put, + corew$nmi_req_set_not_clear; // ports of submodule jtagtap wire [31 : 0] jtagtap$dmi_req_data, jtagtap$dmi_rsp_data; @@ -809,14 +745,11 @@ module mkP3_Core(CLK, jtagtap$jtag_tdo, jtagtap$jtag_tms; - // ports of submodule tv_xactor - wire [607 : 0] tv_xactor$axi_out_tdata, tv_xactor$tv_in_put; - wire [75 : 0] tv_xactor$axi_out_tkeep, tv_xactor$axi_out_tstrb; - wire tv_xactor$EN_tv_in_put, - tv_xactor$RDY_tv_in_put, - tv_xactor$axi_out_tlast, - tv_xactor$axi_out_tready, - tv_xactor$axi_out_tvalid; + // ports of submodule ndm_reset + wire ndm_reset$RST_OUT; + + // ports of submodule ndm_reset_controller + wire ndm_reset_controller$ASSERT_IN, ndm_reset_controller$OUT_RST; // rule scheduling signals wire CAN_FIRE_RL_bus_dmi_req_do_enq, @@ -824,7 +757,6 @@ module mkP3_Core(CLK, CAN_FIRE_RL_bus_dmi_rsp_fifof_both, CAN_FIRE_RL_bus_dmi_rsp_fifof_decCtr, CAN_FIRE_RL_bus_dmi_rsp_fifof_incCtr, - CAN_FIRE_RL_mkConnectionGetPut, CAN_FIRE_RL_mkConnectionVtoAf, CAN_FIRE_RL_mkConnectionVtoAf_1, CAN_FIRE_RL_mkConnectionVtoAf_2, @@ -834,35 +766,34 @@ module mkP3_Core(CLK, CAN_FIRE_RL_mkConnectionVtoAf_6, CAN_FIRE_RL_mkConnectionVtoAf_7, CAN_FIRE_RL_mkConnectionVtoAf_8, + CAN_FIRE_RL_rl_always, CAN_FIRE_RL_rl_dmi_req, CAN_FIRE_RL_rl_dmi_req_cpu, CAN_FIRE_RL_rl_dmi_rsp, CAN_FIRE_RL_rl_dmi_rsp_cpu, - CAN_FIRE_RL_rl_ndmreset, - CAN_FIRE_RL_rl_once, - CAN_FIRE_RL_rl_reset_response, + CAN_FIRE_RL_rl_ndm_reset, + CAN_FIRE_RL_rl_ndm_reset_wait, + CAN_FIRE_RL_rl_step_0, CAN_FIRE_debug_external_interrupt_req, CAN_FIRE_interrupt_reqs, CAN_FIRE_jtag_tclk, CAN_FIRE_jtag_tdi, CAN_FIRE_jtag_tms, - CAN_FIRE_master0_m_arready, - CAN_FIRE_master0_m_awready, - CAN_FIRE_master0_m_bvalid, - CAN_FIRE_master0_m_rvalid, - CAN_FIRE_master0_m_wready, - CAN_FIRE_master1_m_arready, - CAN_FIRE_master1_m_awready, - CAN_FIRE_master1_m_bvalid, - CAN_FIRE_master1_m_rvalid, - CAN_FIRE_master1_m_wready, - CAN_FIRE_tv_verifier_info_tx_m_tready, + CAN_FIRE_master0_ar_arready, + CAN_FIRE_master0_aw_awready, + CAN_FIRE_master0_b_bflit, + CAN_FIRE_master0_r_rflit, + CAN_FIRE_master0_w_wready, + CAN_FIRE_master1_ar_arready, + CAN_FIRE_master1_aw_awready, + CAN_FIRE_master1_b_bflit, + CAN_FIRE_master1_r_rflit, + CAN_FIRE_master1_w_wready, WILL_FIRE_RL_bus_dmi_req_do_enq, WILL_FIRE_RL_bus_dmi_rsp_do_deq, WILL_FIRE_RL_bus_dmi_rsp_fifof_both, WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr, WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr, - WILL_FIRE_RL_mkConnectionGetPut, WILL_FIRE_RL_mkConnectionVtoAf, WILL_FIRE_RL_mkConnectionVtoAf_1, WILL_FIRE_RL_mkConnectionVtoAf_2, @@ -872,29 +803,29 @@ module mkP3_Core(CLK, WILL_FIRE_RL_mkConnectionVtoAf_6, WILL_FIRE_RL_mkConnectionVtoAf_7, WILL_FIRE_RL_mkConnectionVtoAf_8, + WILL_FIRE_RL_rl_always, WILL_FIRE_RL_rl_dmi_req, WILL_FIRE_RL_rl_dmi_req_cpu, WILL_FIRE_RL_rl_dmi_rsp, WILL_FIRE_RL_rl_dmi_rsp_cpu, - WILL_FIRE_RL_rl_ndmreset, - WILL_FIRE_RL_rl_once, - WILL_FIRE_RL_rl_reset_response, + WILL_FIRE_RL_rl_ndm_reset, + WILL_FIRE_RL_rl_ndm_reset_wait, + WILL_FIRE_RL_rl_step_0, WILL_FIRE_debug_external_interrupt_req, WILL_FIRE_interrupt_reqs, WILL_FIRE_jtag_tclk, WILL_FIRE_jtag_tdi, WILL_FIRE_jtag_tms, - WILL_FIRE_master0_m_arready, - WILL_FIRE_master0_m_awready, - WILL_FIRE_master0_m_bvalid, - WILL_FIRE_master0_m_rvalid, - WILL_FIRE_master0_m_wready, - WILL_FIRE_master1_m_arready, - WILL_FIRE_master1_m_awready, - WILL_FIRE_master1_m_bvalid, - WILL_FIRE_master1_m_rvalid, - WILL_FIRE_master1_m_wready, - WILL_FIRE_tv_verifier_info_tx_m_tready; + WILL_FIRE_master0_ar_arready, + WILL_FIRE_master0_aw_awready, + WILL_FIRE_master0_b_bflit, + WILL_FIRE_master0_r_rflit, + WILL_FIRE_master0_w_wready, + WILL_FIRE_master1_ar_arready, + WILL_FIRE_master1_aw_awready, + WILL_FIRE_master1_b_bflit, + WILL_FIRE_master1_r_rflit, + WILL_FIRE_master1_w_wready; // inputs to muxes for submodule ports wire [33 : 0] MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1, @@ -902,16 +833,26 @@ module mkP3_Core(CLK, MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2; + wire [7 : 0] MUX_rg_ndm_reset_delay$write_1__VAL_1; wire [1 : 0] MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2; wire MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1, MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2, MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1, MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2, - MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1; + MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1, + MUX_corew$start_1__SEL_1; + + // declarations used by system tasks + // synopsys translate_off + reg [31 : 0] v__h1238; + reg [31 : 0] v__h1383; + reg [31 : 0] v__h1232; + reg [31 : 0] v__h1377; + // synopsys translate_on // remaining internal signals - wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28; - wire IF_bus_dmi_req_fifof_first__7_BITS_1_TO_0_8_EQ_ETC___d78, + wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42; + wire IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92, _dfoo1, _dfoo3; @@ -919,218 +860,212 @@ module mkP3_Core(CLK, assign CLK_jtag_tclk_out = jtagtap$CLK_jtag_tclk_out ; assign CLK_GATE_jtag_tclk_out = 1'b1 ; - // value method master0_m_awvalid - assign master0_awvalid = corew$cpu_imem_master_awvalid ; - - // value method master0_m_awid + // value method master0_aw_awid assign master0_awid = corew$cpu_imem_master_awid ; - // value method master0_m_awaddr + // value method master0_aw_awaddr assign master0_awaddr = corew$cpu_imem_master_awaddr ; - // value method master0_m_awlen + // value method master0_aw_awlen assign master0_awlen = corew$cpu_imem_master_awlen ; - // value method master0_m_awsize + // value method master0_aw_awsize assign master0_awsize = corew$cpu_imem_master_awsize ; - // value method master0_m_awburst + // value method master0_aw_awburst assign master0_awburst = corew$cpu_imem_master_awburst ; - // value method master0_m_awlock + // value method master0_aw_awlock assign master0_awlock = corew$cpu_imem_master_awlock ; - // value method master0_m_awcache + // value method master0_aw_awcache assign master0_awcache = corew$cpu_imem_master_awcache ; - // value method master0_m_awprot + // value method master0_aw_awprot assign master0_awprot = corew$cpu_imem_master_awprot ; - // value method master0_m_awqos + // value method master0_aw_awqos assign master0_awqos = corew$cpu_imem_master_awqos ; - // value method master0_m_awregion + // value method master0_aw_awregion assign master0_awregion = corew$cpu_imem_master_awregion ; - // action method master0_m_awready - assign CAN_FIRE_master0_m_awready = 1'd1 ; - assign WILL_FIRE_master0_m_awready = 1'd1 ; + // value method master0_aw_awvalid + assign master0_awvalid = corew$cpu_imem_master_awvalid ; - // value method master0_m_wvalid - assign master0_wvalid = corew$cpu_imem_master_wvalid ; + // action method master0_aw_awready + assign CAN_FIRE_master0_aw_awready = 1'd1 ; + assign WILL_FIRE_master0_aw_awready = 1'd1 ; - // value method master0_m_wid - assign master0_wid = corew$cpu_imem_master_wid ; - - // value method master0_m_wdata + // value method master0_w_wdata assign master0_wdata = corew$cpu_imem_master_wdata ; - // value method master0_m_wstrb + // value method master0_w_wstrb assign master0_wstrb = corew$cpu_imem_master_wstrb ; - // value method master0_m_wlast + // value method master0_w_wlast assign master0_wlast = corew$cpu_imem_master_wlast ; - // action method master0_m_wready - assign CAN_FIRE_master0_m_wready = 1'd1 ; - assign WILL_FIRE_master0_m_wready = 1'd1 ; + // value method master0_w_wvalid + assign master0_wvalid = corew$cpu_imem_master_wvalid ; - // action method master0_m_bvalid - assign CAN_FIRE_master0_m_bvalid = 1'd1 ; - assign WILL_FIRE_master0_m_bvalid = 1'd1 ; + // action method master0_w_wready + assign CAN_FIRE_master0_w_wready = 1'd1 ; + assign WILL_FIRE_master0_w_wready = 1'd1 ; - // value method master0_m_bready + // action method master0_b_bflit + assign CAN_FIRE_master0_b_bflit = 1'd1 ; + assign WILL_FIRE_master0_b_bflit = master0_bvalid ; + + // value method master0_b_bready assign master0_bready = corew$cpu_imem_master_bready ; - // value method master0_m_arvalid - assign master0_arvalid = corew$cpu_imem_master_arvalid ; - - // value method master0_m_arid + // value method master0_ar_arid assign master0_arid = corew$cpu_imem_master_arid ; - // value method master0_m_araddr + // value method master0_ar_araddr assign master0_araddr = corew$cpu_imem_master_araddr ; - // value method master0_m_arlen + // value method master0_ar_arlen assign master0_arlen = corew$cpu_imem_master_arlen ; - // value method master0_m_arsize + // value method master0_ar_arsize assign master0_arsize = corew$cpu_imem_master_arsize ; - // value method master0_m_arburst + // value method master0_ar_arburst assign master0_arburst = corew$cpu_imem_master_arburst ; - // value method master0_m_arlock + // value method master0_ar_arlock assign master0_arlock = corew$cpu_imem_master_arlock ; - // value method master0_m_arcache + // value method master0_ar_arcache assign master0_arcache = corew$cpu_imem_master_arcache ; - // value method master0_m_arprot + // value method master0_ar_arprot assign master0_arprot = corew$cpu_imem_master_arprot ; - // value method master0_m_arqos + // value method master0_ar_arqos assign master0_arqos = corew$cpu_imem_master_arqos ; - // value method master0_m_arregion + // value method master0_ar_arregion assign master0_arregion = corew$cpu_imem_master_arregion ; - // action method master0_m_arready - assign CAN_FIRE_master0_m_arready = 1'd1 ; - assign WILL_FIRE_master0_m_arready = 1'd1 ; + // value method master0_ar_arvalid + assign master0_arvalid = corew$cpu_imem_master_arvalid ; - // action method master0_m_rvalid - assign CAN_FIRE_master0_m_rvalid = 1'd1 ; - assign WILL_FIRE_master0_m_rvalid = 1'd1 ; + // action method master0_ar_arready + assign CAN_FIRE_master0_ar_arready = 1'd1 ; + assign WILL_FIRE_master0_ar_arready = 1'd1 ; - // value method master0_m_rready + // action method master0_r_rflit + assign CAN_FIRE_master0_r_rflit = 1'd1 ; + assign WILL_FIRE_master0_r_rflit = master0_rvalid ; + + // value method master0_r_rready assign master0_rready = corew$cpu_imem_master_rready ; - // value method master1_m_awvalid - assign master1_awvalid = corew$cpu_dmem_master_awvalid ; - - // value method master1_m_awid + // value method master1_aw_awid assign master1_awid = corew$cpu_dmem_master_awid ; - // value method master1_m_awaddr + // value method master1_aw_awaddr assign master1_awaddr = corew$cpu_dmem_master_awaddr ; - // value method master1_m_awlen + // value method master1_aw_awlen assign master1_awlen = corew$cpu_dmem_master_awlen ; - // value method master1_m_awsize + // value method master1_aw_awsize assign master1_awsize = corew$cpu_dmem_master_awsize ; - // value method master1_m_awburst + // value method master1_aw_awburst assign master1_awburst = corew$cpu_dmem_master_awburst ; - // value method master1_m_awlock + // value method master1_aw_awlock assign master1_awlock = corew$cpu_dmem_master_awlock ; - // value method master1_m_awcache + // value method master1_aw_awcache assign master1_awcache = corew$cpu_dmem_master_awcache ; - // value method master1_m_awprot + // value method master1_aw_awprot assign master1_awprot = corew$cpu_dmem_master_awprot ; - // value method master1_m_awqos + // value method master1_aw_awqos assign master1_awqos = corew$cpu_dmem_master_awqos ; - // value method master1_m_awregion + // value method master1_aw_awregion assign master1_awregion = corew$cpu_dmem_master_awregion ; - // action method master1_m_awready - assign CAN_FIRE_master1_m_awready = 1'd1 ; - assign WILL_FIRE_master1_m_awready = 1'd1 ; + // value method master1_aw_awvalid + assign master1_awvalid = corew$cpu_dmem_master_awvalid ; - // value method master1_m_wvalid - assign master1_wvalid = corew$cpu_dmem_master_wvalid ; + // action method master1_aw_awready + assign CAN_FIRE_master1_aw_awready = 1'd1 ; + assign WILL_FIRE_master1_aw_awready = 1'd1 ; - // value method master1_m_wid - assign master1_wid = corew$cpu_dmem_master_wid ; - - // value method master1_m_wdata + // value method master1_w_wdata assign master1_wdata = corew$cpu_dmem_master_wdata ; - // value method master1_m_wstrb + // value method master1_w_wstrb assign master1_wstrb = corew$cpu_dmem_master_wstrb ; - // value method master1_m_wlast + // value method master1_w_wlast assign master1_wlast = corew$cpu_dmem_master_wlast ; - // action method master1_m_wready - assign CAN_FIRE_master1_m_wready = 1'd1 ; - assign WILL_FIRE_master1_m_wready = 1'd1 ; + // value method master1_w_wvalid + assign master1_wvalid = corew$cpu_dmem_master_wvalid ; - // action method master1_m_bvalid - assign CAN_FIRE_master1_m_bvalid = 1'd1 ; - assign WILL_FIRE_master1_m_bvalid = 1'd1 ; + // action method master1_w_wready + assign CAN_FIRE_master1_w_wready = 1'd1 ; + assign WILL_FIRE_master1_w_wready = 1'd1 ; - // value method master1_m_bready + // action method master1_b_bflit + assign CAN_FIRE_master1_b_bflit = 1'd1 ; + assign WILL_FIRE_master1_b_bflit = master1_bvalid ; + + // value method master1_b_bready assign master1_bready = corew$cpu_dmem_master_bready ; - // value method master1_m_arvalid - assign master1_arvalid = corew$cpu_dmem_master_arvalid ; - - // value method master1_m_arid + // value method master1_ar_arid assign master1_arid = corew$cpu_dmem_master_arid ; - // value method master1_m_araddr + // value method master1_ar_araddr assign master1_araddr = corew$cpu_dmem_master_araddr ; - // value method master1_m_arlen + // value method master1_ar_arlen assign master1_arlen = corew$cpu_dmem_master_arlen ; - // value method master1_m_arsize + // value method master1_ar_arsize assign master1_arsize = corew$cpu_dmem_master_arsize ; - // value method master1_m_arburst + // value method master1_ar_arburst assign master1_arburst = corew$cpu_dmem_master_arburst ; - // value method master1_m_arlock + // value method master1_ar_arlock assign master1_arlock = corew$cpu_dmem_master_arlock ; - // value method master1_m_arcache + // value method master1_ar_arcache assign master1_arcache = corew$cpu_dmem_master_arcache ; - // value method master1_m_arprot + // value method master1_ar_arprot assign master1_arprot = corew$cpu_dmem_master_arprot ; - // value method master1_m_arqos + // value method master1_ar_arqos assign master1_arqos = corew$cpu_dmem_master_arqos ; - // value method master1_m_arregion + // value method master1_ar_arregion assign master1_arregion = corew$cpu_dmem_master_arregion ; - // action method master1_m_arready - assign CAN_FIRE_master1_m_arready = 1'd1 ; - assign WILL_FIRE_master1_m_arready = 1'd1 ; + // value method master1_ar_arvalid + assign master1_arvalid = corew$cpu_dmem_master_arvalid ; - // action method master1_m_rvalid - assign CAN_FIRE_master1_m_rvalid = 1'd1 ; - assign WILL_FIRE_master1_m_rvalid = 1'd1 ; + // action method master1_ar_arready + assign CAN_FIRE_master1_ar_arready = 1'd1 ; + assign WILL_FIRE_master1_ar_arready = 1'd1 ; - // value method master1_m_rready + // action method master1_r_rflit + assign CAN_FIRE_master1_r_rflit = 1'd1 ; + assign WILL_FIRE_master1_r_rflit = master1_rvalid ; + + // value method master1_r_rready assign master1_rready = corew$cpu_dmem_master_rready ; // action method interrupt_reqs @@ -1141,25 +1076,6 @@ module mkP3_Core(CLK, assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ; assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ; - // value method tv_verifier_info_tx_m_tvalid - assign tv_verifier_info_tx_tvalid = tv_xactor$axi_out_tvalid ; - - // value method tv_verifier_info_tx_m_tdata - assign tv_verifier_info_tx_tdata = tv_xactor$axi_out_tdata ; - - // value method tv_verifier_info_tx_m_tstrb - assign tv_verifier_info_tx_tstrb = tv_xactor$axi_out_tstrb ; - - // value method tv_verifier_info_tx_m_tkeep - assign tv_verifier_info_tx_tkeep = tv_xactor$axi_out_tkeep ; - - // value method tv_verifier_info_tx_m_tlast - assign tv_verifier_info_tx_tlast = tv_xactor$axi_out_tlast ; - - // action method tv_verifier_info_tx_m_tready - assign CAN_FIRE_tv_verifier_info_tx_m_tready = 1'd1 ; - assign WILL_FIRE_tv_verifier_info_tx_m_tready = 1'd1 ; - // action method jtag_tdi assign CAN_FIRE_jtag_tdi = 1'd1 ; assign WILL_FIRE_jtag_tdi = 1'd1 ; @@ -1187,8 +1103,9 @@ module mkP3_Core(CLK, .EMPTY_N(bus_dmi_req_fifof$EMPTY_N)); // submodule corew - mkCoreW corew(.CLK(CLK), - .RST_N(RST_N), + mkCoreW corew(.RST_N_dm_power_on_reset(RST_N), + .CLK(CLK), + .RST_N(ndm_reset$RST_OUT), .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear), .core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear), @@ -1209,46 +1126,42 @@ module mkP3_Core(CLK, .cpu_dmem_master_awready(corew$cpu_dmem_master_awready), .cpu_dmem_master_bid(corew$cpu_dmem_master_bid), .cpu_dmem_master_bresp(corew$cpu_dmem_master_bresp), - .cpu_dmem_master_bvalid(corew$cpu_dmem_master_bvalid), .cpu_dmem_master_rdata(corew$cpu_dmem_master_rdata), .cpu_dmem_master_rid(corew$cpu_dmem_master_rid), .cpu_dmem_master_rlast(corew$cpu_dmem_master_rlast), .cpu_dmem_master_rresp(corew$cpu_dmem_master_rresp), - .cpu_dmem_master_rvalid(corew$cpu_dmem_master_rvalid), .cpu_dmem_master_wready(corew$cpu_dmem_master_wready), .cpu_imem_master_arready(corew$cpu_imem_master_arready), .cpu_imem_master_awready(corew$cpu_imem_master_awready), .cpu_imem_master_bid(corew$cpu_imem_master_bid), .cpu_imem_master_bresp(corew$cpu_imem_master_bresp), - .cpu_imem_master_bvalid(corew$cpu_imem_master_bvalid), .cpu_imem_master_rdata(corew$cpu_imem_master_rdata), .cpu_imem_master_rid(corew$cpu_imem_master_rid), .cpu_imem_master_rlast(corew$cpu_imem_master_rlast), .cpu_imem_master_rresp(corew$cpu_imem_master_rresp), - .cpu_imem_master_rvalid(corew$cpu_imem_master_rvalid), .cpu_imem_master_wready(corew$cpu_imem_master_wready), - .debug_external_interrupt_req_set_not_clear(corew$debug_external_interrupt_req_set_not_clear), - .dm_dmi_read_addr_dm_addr(corew$dm_dmi_read_addr_dm_addr), - .dm_dmi_write_dm_addr(corew$dm_dmi_write_dm_addr), - .dm_dmi_write_dm_word(corew$dm_dmi_write_dm_word), - .set_htif_addrs_fromhost_addr(corew$set_htif_addrs_fromhost_addr), - .set_htif_addrs_tohost_addr(corew$set_htif_addrs_tohost_addr), + .dmi_read_addr_dm_addr(corew$dmi_read_addr_dm_addr), + .dmi_write_dm_addr(corew$dmi_write_dm_addr), + .dmi_write_dm_word(corew$dmi_write_dm_word), + .ndm_reset_client_response_put(corew$ndm_reset_client_response_put), + .nmi_req_set_not_clear(corew$nmi_req_set_not_clear), .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), + .start_fromhost_addr(corew$start_fromhost_addr), + .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), - .EN_set_htif_addrs(corew$EN_set_htif_addrs), - .EN_cpu_reset_server_request_put(corew$EN_cpu_reset_server_request_put), - .EN_cpu_reset_server_response_get(corew$EN_cpu_reset_server_response_get), - .EN_tv_verifier_info_get_get(corew$EN_tv_verifier_info_get_get), - .EN_dm_dmi_read_addr(corew$EN_dm_dmi_read_addr), - .EN_dm_dmi_read_data(corew$EN_dm_dmi_read_data), - .EN_dm_dmi_write(corew$EN_dm_dmi_write), - .EN_dm_ndm_reset_req_get_get(corew$EN_dm_ndm_reset_req_get_get), + .EN_start(corew$EN_start), + .cpu_imem_master_bvalid(corew$cpu_imem_master_bvalid), + .cpu_imem_master_rvalid(corew$cpu_imem_master_rvalid), + .cpu_dmem_master_bvalid(corew$cpu_dmem_master_bvalid), + .cpu_dmem_master_rvalid(corew$cpu_dmem_master_rvalid), + .EN_dmi_read_addr(corew$EN_dmi_read_addr), + .EN_dmi_read_data(corew$EN_dmi_read_data), + .EN_dmi_write(corew$EN_dmi_write), + .EN_ndm_reset_client_request_get(corew$EN_ndm_reset_client_request_get), + .EN_ndm_reset_client_response_put(corew$EN_ndm_reset_client_response_put), .RDY_set_verbosity(), - .RDY_set_htif_addrs(), - .RDY_cpu_reset_server_request_put(corew$RDY_cpu_reset_server_request_put), - .RDY_cpu_reset_server_response_get(corew$RDY_cpu_reset_server_response_get), - .cpu_imem_master_awvalid(corew$cpu_imem_master_awvalid), + .RDY_start(corew$RDY_start), .cpu_imem_master_awid(corew$cpu_imem_master_awid), .cpu_imem_master_awaddr(corew$cpu_imem_master_awaddr), .cpu_imem_master_awlen(corew$cpu_imem_master_awlen), @@ -1259,13 +1172,12 @@ module mkP3_Core(CLK, .cpu_imem_master_awprot(corew$cpu_imem_master_awprot), .cpu_imem_master_awqos(corew$cpu_imem_master_awqos), .cpu_imem_master_awregion(corew$cpu_imem_master_awregion), - .cpu_imem_master_wvalid(corew$cpu_imem_master_wvalid), - .cpu_imem_master_wid(corew$cpu_imem_master_wid), + .cpu_imem_master_awvalid(corew$cpu_imem_master_awvalid), .cpu_imem_master_wdata(corew$cpu_imem_master_wdata), .cpu_imem_master_wstrb(corew$cpu_imem_master_wstrb), .cpu_imem_master_wlast(corew$cpu_imem_master_wlast), + .cpu_imem_master_wvalid(corew$cpu_imem_master_wvalid), .cpu_imem_master_bready(corew$cpu_imem_master_bready), - .cpu_imem_master_arvalid(corew$cpu_imem_master_arvalid), .cpu_imem_master_arid(corew$cpu_imem_master_arid), .cpu_imem_master_araddr(corew$cpu_imem_master_araddr), .cpu_imem_master_arlen(corew$cpu_imem_master_arlen), @@ -1276,8 +1188,8 @@ module mkP3_Core(CLK, .cpu_imem_master_arprot(corew$cpu_imem_master_arprot), .cpu_imem_master_arqos(corew$cpu_imem_master_arqos), .cpu_imem_master_arregion(corew$cpu_imem_master_arregion), + .cpu_imem_master_arvalid(corew$cpu_imem_master_arvalid), .cpu_imem_master_rready(corew$cpu_imem_master_rready), - .cpu_dmem_master_awvalid(corew$cpu_dmem_master_awvalid), .cpu_dmem_master_awid(corew$cpu_dmem_master_awid), .cpu_dmem_master_awaddr(corew$cpu_dmem_master_awaddr), .cpu_dmem_master_awlen(corew$cpu_dmem_master_awlen), @@ -1288,13 +1200,12 @@ module mkP3_Core(CLK, .cpu_dmem_master_awprot(corew$cpu_dmem_master_awprot), .cpu_dmem_master_awqos(corew$cpu_dmem_master_awqos), .cpu_dmem_master_awregion(corew$cpu_dmem_master_awregion), - .cpu_dmem_master_wvalid(corew$cpu_dmem_master_wvalid), - .cpu_dmem_master_wid(corew$cpu_dmem_master_wid), + .cpu_dmem_master_awvalid(corew$cpu_dmem_master_awvalid), .cpu_dmem_master_wdata(corew$cpu_dmem_master_wdata), .cpu_dmem_master_wstrb(corew$cpu_dmem_master_wstrb), .cpu_dmem_master_wlast(corew$cpu_dmem_master_wlast), + .cpu_dmem_master_wvalid(corew$cpu_dmem_master_wvalid), .cpu_dmem_master_bready(corew$cpu_dmem_master_bready), - .cpu_dmem_master_arvalid(corew$cpu_dmem_master_arvalid), .cpu_dmem_master_arid(corew$cpu_dmem_master_arid), .cpu_dmem_master_araddr(corew$cpu_dmem_master_araddr), .cpu_dmem_master_arlen(corew$cpu_dmem_master_arlen), @@ -1305,14 +1216,15 @@ module mkP3_Core(CLK, .cpu_dmem_master_arprot(corew$cpu_dmem_master_arprot), .cpu_dmem_master_arqos(corew$cpu_dmem_master_arqos), .cpu_dmem_master_arregion(corew$cpu_dmem_master_arregion), + .cpu_dmem_master_arvalid(corew$cpu_dmem_master_arvalid), .cpu_dmem_master_rready(corew$cpu_dmem_master_rready), - .tv_verifier_info_get_get(corew$tv_verifier_info_get_get), - .RDY_tv_verifier_info_get_get(corew$RDY_tv_verifier_info_get_get), - .RDY_dm_dmi_read_addr(corew$RDY_dm_dmi_read_addr), - .dm_dmi_read_data(corew$dm_dmi_read_data), - .RDY_dm_dmi_read_data(corew$RDY_dm_dmi_read_data), - .RDY_dm_dmi_write(corew$RDY_dm_dmi_write), - .RDY_dm_ndm_reset_req_get_get(corew$RDY_dm_ndm_reset_req_get_get)); + .RDY_dmi_read_addr(corew$RDY_dmi_read_addr), + .dmi_read_data(corew$dmi_read_data), + .RDY_dmi_read_data(corew$RDY_dmi_read_data), + .RDY_dmi_write(corew$RDY_dmi_write), + .ndm_reset_client_request_get(), + .RDY_ndm_reset_client_request_get(corew$RDY_ndm_reset_client_request_get), + .RDY_ndm_reset_client_response_put(corew$RDY_ndm_reset_client_response_put)); // submodule jtagtap mkJtagTap jtagtap(.CLK(CLK), @@ -1333,34 +1245,34 @@ module mkP3_Core(CLK, .CLK_jtag_tclk_out(jtagtap$CLK_jtag_tclk_out), .CLK_GATE_jtag_tclk_out()); - // submodule tv_xactor - mkTV_Xactor tv_xactor(.CLK(CLK), - .RST_N(RST_N), - .axi_out_tready(tv_xactor$axi_out_tready), - .tv_in_put(tv_xactor$tv_in_put), - .EN_tv_in_put(tv_xactor$EN_tv_in_put), - .RDY_tv_in_put(tv_xactor$RDY_tv_in_put), - .axi_out_tvalid(tv_xactor$axi_out_tvalid), - .axi_out_tdata(tv_xactor$axi_out_tdata), - .axi_out_tstrb(tv_xactor$axi_out_tstrb), - .axi_out_tkeep(tv_xactor$axi_out_tkeep), - .axi_out_tlast(tv_xactor$axi_out_tlast)); + // submodule ndm_reset + ResetEither ndm_reset(.A_RST(RST_N), + .B_RST(ndm_reset_controller$OUT_RST), + .RST_OUT(ndm_reset$RST_OUT)); - // rule RL_rl_once - assign CAN_FIRE_RL_rl_once = WILL_FIRE_RL_rl_once ; - assign WILL_FIRE_RL_rl_once = - corew$RDY_cpu_reset_server_request_put && !rg_once ; + // submodule ndm_reset_controller + MakeResetA #(.RSTDELAY(32'd10), .init(1'd1)) ndm_reset_controller(.CLK(CLK), + .RST(RST_N), + .DST_CLK(CLK), + .ASSERT_IN(ndm_reset_controller$ASSERT_IN), + .ASSERT_OUT(), + .OUT_RST(ndm_reset_controller$OUT_RST)); - // rule RL_rl_reset_response - assign CAN_FIRE_RL_rl_reset_response = - corew$RDY_cpu_reset_server_response_get ; - assign WILL_FIRE_RL_rl_reset_response = - corew$RDY_cpu_reset_server_response_get ; + // rule RL_rl_always + assign CAN_FIRE_RL_rl_always = 1'd1 ; + assign WILL_FIRE_RL_rl_always = 1'd1 ; - // rule RL_rl_ndmreset - assign CAN_FIRE_RL_rl_ndmreset = - corew$RDY_dm_ndm_reset_req_get_get && rg_once ; - assign WILL_FIRE_RL_rl_ndmreset = CAN_FIRE_RL_rl_ndmreset ; + // rule RL_rl_ndm_reset + assign CAN_FIRE_RL_rl_ndm_reset = + corew$RDY_ndm_reset_client_request_get && + rg_ndm_reset_delay == 8'd0 ; + assign WILL_FIRE_RL_rl_ndm_reset = CAN_FIRE_RL_rl_ndm_reset ; + + // rule RL_rl_step_0 + assign CAN_FIRE_RL_rl_step_0 = + corew$RDY_start && !rg_corew_start_after_por ; + assign WILL_FIRE_RL_rl_step_0 = + CAN_FIRE_RL_rl_step_0 && !WILL_FIRE_RL_rl_ndm_reset_wait ; // rule RL_mkConnectionVtoAf assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ; @@ -1406,22 +1318,24 @@ module mkP3_Core(CLK, assign CAN_FIRE_RL_mkConnectionVtoAf_8 = 1'd1 ; assign WILL_FIRE_RL_mkConnectionVtoAf_8 = 1'd1 ; - // rule RL_rl_dmi_req_cpu - assign CAN_FIRE_RL_rl_dmi_req_cpu = - bus_dmi_req_fifof$EMPTY_N && - IF_bus_dmi_req_fifof_first__7_BITS_1_TO_0_8_EQ_ETC___d78 ; - assign WILL_FIRE_RL_rl_dmi_req_cpu = CAN_FIRE_RL_rl_dmi_req_cpu ; - // rule RL_rl_dmi_rsp_cpu assign CAN_FIRE_RL_rl_dmi_rsp_cpu = - bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dm_dmi_read_data ; + bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_read_data ; assign WILL_FIRE_RL_rl_dmi_rsp_cpu = CAN_FIRE_RL_rl_dmi_rsp_cpu && !WILL_FIRE_RL_rl_dmi_req_cpu ; - // rule RL_mkConnectionGetPut - assign CAN_FIRE_RL_mkConnectionGetPut = - corew$RDY_tv_verifier_info_get_get && tv_xactor$RDY_tv_in_put ; - assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ; + // rule RL_rl_dmi_req_cpu + assign CAN_FIRE_RL_rl_dmi_req_cpu = + bus_dmi_req_fifof$EMPTY_N && + IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 ; + assign WILL_FIRE_RL_rl_dmi_req_cpu = CAN_FIRE_RL_rl_dmi_req_cpu ; + + // rule RL_rl_ndm_reset_wait + assign CAN_FIRE_RL_rl_ndm_reset_wait = + (rg_ndm_reset_delay != 8'd1 || + corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && + rg_ndm_reset_delay != 8'd0 ; + assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; // rule RL_bus_dmi_req_do_enq assign CAN_FIRE_RL_bus_dmi_req_do_enq = @@ -1470,6 +1384,8 @@ module mkP3_Core(CLK, assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] != 2'd1 ; + assign MUX_corew$start_1__SEL_1 = + WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 ; assign MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 = bus_dmi_rsp_fifof_cntr_r + 2'd1 ; assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 = @@ -1488,7 +1404,8 @@ module mkP3_Core(CLK, { 32'hAAAAAAAA, (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2) ? 2'd0 : 2'd2 } ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2 = - { corew$dm_dmi_read_data, 2'd0 } ; + { corew$dmi_read_data, 2'd0 } ; + assign MUX_rg_ndm_reset_delay$write_1__VAL_1 = rg_ndm_reset_delay - 8'd1 ; // inlined wires assign bus_dmi_rsp_fifof_enqueueing$whas = @@ -1503,7 +1420,7 @@ module mkP3_Core(CLK, // register bus_dmi_rsp_fifof_cntr_r assign bus_dmi_rsp_fifof_cntr_r$D_IN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ? - bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 : + bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 : MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 ; assign bus_dmi_rsp_fifof_cntr_r$EN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr || @@ -1561,9 +1478,17 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r == 2'd1 || WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; - // register rg_once - assign rg_once$D_IN = !WILL_FIRE_RL_rl_ndmreset ; - assign rg_once$EN = WILL_FIRE_RL_rl_ndmreset || WILL_FIRE_RL_rl_once ; + // register rg_corew_start_after_por + assign rg_corew_start_after_por$D_IN = 1'd1 ; + assign rg_corew_start_after_por$EN = WILL_FIRE_RL_rl_step_0 ; + + // register rg_ndm_reset_delay + assign rg_ndm_reset_delay$D_IN = + WILL_FIRE_RL_rl_ndm_reset_wait ? + MUX_rg_ndm_reset_delay$write_1__VAL_1 : + 8'd110 ; + assign rg_ndm_reset_delay$EN = + WILL_FIRE_RL_rl_ndm_reset_wait || WILL_FIRE_RL_rl_ndm_reset ; // submodule bus_dmi_req_fifof assign bus_dmi_req_fifof$D_IN = bus_dmi_req_data_wire$wget ; @@ -1608,47 +1533,46 @@ module mkP3_Core(CLK, assign corew$cpu_dmem_master_awready = master1_awready ; assign corew$cpu_dmem_master_bid = master1_bid ; assign corew$cpu_dmem_master_bresp = master1_bresp ; - assign corew$cpu_dmem_master_bvalid = master1_bvalid ; assign corew$cpu_dmem_master_rdata = master1_rdata ; assign corew$cpu_dmem_master_rid = master1_rid ; assign corew$cpu_dmem_master_rlast = master1_rlast ; assign corew$cpu_dmem_master_rresp = master1_rresp ; - assign corew$cpu_dmem_master_rvalid = master1_rvalid ; assign corew$cpu_dmem_master_wready = master1_wready ; assign corew$cpu_imem_master_arready = master0_arready ; assign corew$cpu_imem_master_awready = master0_awready ; assign corew$cpu_imem_master_bid = master0_bid ; assign corew$cpu_imem_master_bresp = master0_bresp ; - assign corew$cpu_imem_master_bvalid = master0_bvalid ; assign corew$cpu_imem_master_rdata = master0_rdata ; assign corew$cpu_imem_master_rid = master0_rid ; assign corew$cpu_imem_master_rlast = master0_rlast ; assign corew$cpu_imem_master_rresp = master0_rresp ; - assign corew$cpu_imem_master_rvalid = master0_rvalid ; assign corew$cpu_imem_master_wready = master0_wready ; - assign corew$debug_external_interrupt_req_set_not_clear = - debug_external_interrupt_req_set_not_clear ; - assign corew$dm_dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; - assign corew$dm_dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; - assign corew$dm_dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; - assign corew$set_htif_addrs_fromhost_addr = 64'h0 ; - assign corew$set_htif_addrs_tohost_addr = 64'h0 ; + assign corew$dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; + assign corew$dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; + assign corew$dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; + assign corew$ndm_reset_client_response_put = 1'd1 ; + assign corew$nmi_req_set_not_clear = 1'd0 ; assign corew$set_verbosity_logdelay = 64'h0 ; assign corew$set_verbosity_verbosity = 4'h0 ; + assign corew$start_fromhost_addr = 64'd0 ; + assign corew$start_tohost_addr = 64'd0 ; assign corew$EN_set_verbosity = 1'b0 ; - assign corew$EN_set_htif_addrs = 1'b0 ; - assign corew$EN_cpu_reset_server_request_put = WILL_FIRE_RL_rl_once ; - assign corew$EN_cpu_reset_server_response_get = - corew$RDY_cpu_reset_server_response_get ; - assign corew$EN_tv_verifier_info_get_get = CAN_FIRE_RL_mkConnectionGetPut ; - assign corew$EN_dm_dmi_read_addr = + assign corew$EN_start = + WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 || + WILL_FIRE_RL_rl_step_0 ; + assign corew$cpu_imem_master_bvalid = master0_bvalid ; + assign corew$cpu_imem_master_rvalid = master0_rvalid ; + assign corew$cpu_dmem_master_bvalid = master1_bvalid ; + assign corew$cpu_dmem_master_rvalid = master1_rvalid ; + assign corew$EN_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ; - assign corew$EN_dm_dmi_read_data = WILL_FIRE_RL_rl_dmi_rsp_cpu ; - assign corew$EN_dm_dmi_write = + assign corew$EN_dmi_read_data = WILL_FIRE_RL_rl_dmi_rsp_cpu ; + assign corew$EN_dmi_write = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 ; - assign corew$EN_dm_ndm_reset_req_get_get = CAN_FIRE_RL_rl_ndmreset ; + assign corew$EN_ndm_reset_client_request_get = CAN_FIRE_RL_rl_ndm_reset ; + assign corew$EN_ndm_reset_client_response_put = MUX_corew$start_1__SEL_1 ; // submodule jtagtap assign jtagtap$dmi_req_ready = bus_dmi_req_fifof$FULL_N ; @@ -1659,26 +1583,24 @@ module mkP3_Core(CLK, assign jtagtap$jtag_tdi = jtag_tdi ; assign jtagtap$jtag_tms = jtag_tms ; - // submodule tv_xactor - assign tv_xactor$axi_out_tready = tv_verifier_info_tx_tready ; - assign tv_xactor$tv_in_put = corew$tv_verifier_info_get_get ; - assign tv_xactor$EN_tv_in_put = CAN_FIRE_RL_mkConnectionGetPut ; + // submodule ndm_reset_controller + assign ndm_reset_controller$ASSERT_IN = CAN_FIRE_RL_rl_ndm_reset ; // remaining internal signals - assign IF_bus_dmi_req_fifof_first__7_BITS_1_TO_0_8_EQ_ETC___d78 = + assign IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 = (bus_dmi_req_fifof$D_OUT[1:0] == 2'd1) ? - corew$RDY_dm_dmi_read_addr : + corew$RDY_dmi_read_addr : (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 || bus_dmi_rsp_fifof_cntr_r != 2'd2) && (bus_dmi_req_fifof$D_OUT[1:0] != 2'd2 || - bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dm_dmi_write) ; + bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_write) ; assign _dfoo1 = bus_dmi_rsp_fifof_cntr_r != 2'd2 || - bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 == 2'd1 ; + bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd1 ; assign _dfoo3 = bus_dmi_rsp_fifof_cntr_r != 2'd1 || - bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 == 2'd0 ; - assign bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 = + bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd0 ; + assign bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 = bus_dmi_rsp_fifof_cntr_r - 2'd1 ; // handling of inlined registers @@ -1690,7 +1612,8 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; bus_dmi_rsp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 34'd0; bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 34'd0; - rg_once <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; end else begin @@ -1703,7 +1626,11 @@ module mkP3_Core(CLK, if (bus_dmi_rsp_fifof_q_1$EN) bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY bus_dmi_rsp_fifof_q_1$D_IN; - if (rg_once$EN) rg_once <= `BSV_ASSIGNMENT_DELAY rg_once$D_IN; + if (rg_corew_start_after_por$EN) + rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY + rg_corew_start_after_por$D_IN; + if (rg_ndm_reset_delay$EN) + rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY rg_ndm_reset_delay$D_IN; end end @@ -1715,9 +1642,44 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r = 2'h2; bus_dmi_rsp_fifof_q_0 = 34'h2AAAAAAAA; bus_dmi_rsp_fifof_q_1 = 34'h2AAAAAAAA; - rg_once = 1'h0; + rg_corew_start_after_por = 1'h0; + rg_ndm_reset_delay = 8'hAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + begin + v__h1238 = $stime; + #0; + end + v__h1232 = v__h1238 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", + v__h1232, + $signed(32'd10)); + if (RST_N != `BSV_RESET_VALUE) + if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + begin + v__h1383 = $stime; + #0; + end + v__h1377 = v__h1383 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", + v__h1377); + end + // synopsys translate_on endmodule // mkP3_Core diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index 969e53c..dc727f7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -1,88 +1,96 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// +// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // +// On Fri Jun 5 17:48:42 BST 2020 // // // Ports: // Name I/O size props -// RDY_hart0_server_reset_request_put O 1 reg -// RDY_hart0_server_reset_response_get O 1 reg // RDY_start O 1 +// master0_awid O 5 +// master0_awaddr O 64 +// master0_awlen O 8 +// master0_awsize O 3 +// master0_awburst O 2 +// master0_awlock O 1 +// master0_awcache O 4 +// master0_awprot O 3 +// master0_awqos O 4 +// master0_awregion O 4 // master0_awvalid O 1 -// master0_awid O 4 reg -// master0_awaddr O 64 reg -// master0_awlen O 8 reg -// master0_awsize O 3 reg -// master0_awburst O 2 reg -// master0_awlock O 1 reg -// master0_awcache O 4 reg -// master0_awprot O 3 reg -// master0_awqos O 4 reg -// master0_awregion O 4 reg +// master0_wdata O 64 +// master0_wstrb O 8 +// master0_wlast O 1 +// master0_wuser O 1 // master0_wvalid O 1 -// master0_wid O 4 reg -// master0_wdata O 64 reg -// master0_wstrb O 8 reg -// master0_wlast O 1 reg // master0_bready O 1 +// master0_arid O 5 +// master0_araddr O 64 +// master0_arlen O 8 +// master0_arsize O 3 +// master0_arburst O 2 +// master0_arlock O 1 +// master0_arcache O 4 +// master0_arprot O 3 +// master0_arqos O 4 +// master0_arregion O 4 // master0_arvalid O 1 -// master0_arid O 4 reg -// master0_araddr O 64 reg -// master0_arlen O 8 reg -// master0_arsize O 3 reg -// master0_arburst O 2 reg -// master0_arlock O 1 reg -// master0_arcache O 4 reg -// master0_arprot O 3 reg -// master0_arqos O 4 reg -// master0_arregion O 4 reg // master0_rready O 1 +// master1_awid O 4 +// master1_awaddr O 64 +// master1_awlen O 8 +// master1_awsize O 3 +// master1_awburst O 2 +// master1_awlock O 1 +// master1_awcache O 4 +// master1_awprot O 3 +// master1_awqos O 4 +// master1_awregion O 4 // master1_awvalid O 1 -// master1_awid O 4 reg -// master1_awaddr O 64 reg -// master1_awlen O 8 reg -// master1_awsize O 3 reg -// master1_awburst O 2 reg -// master1_awlock O 1 reg -// master1_awcache O 4 reg -// master1_awprot O 3 reg -// master1_awqos O 4 reg -// master1_awregion O 4 reg +// master1_wdata O 64 +// master1_wstrb O 8 +// master1_wlast O 1 +// master1_wuser O 1 // master1_wvalid O 1 -// master1_wid O 4 reg -// master1_wdata O 64 reg -// master1_wstrb O 8 reg -// master1_wlast O 1 reg // master1_bready O 1 +// master1_arid O 4 +// master1_araddr O 64 +// master1_arlen O 8 +// master1_arsize O 3 +// master1_arburst O 2 +// master1_arlock O 1 +// master1_arcache O 4 +// master1_arprot O 3 +// master1_arqos O 4 +// master1_arregion O 4 // master1_arvalid O 1 -// master1_arid O 4 reg -// master1_araddr O 64 reg -// master1_arlen O 8 reg -// master1_arsize O 3 reg -// master1_arburst O 2 reg -// master1_arlock O 1 reg -// master1_arcache O 4 reg -// master1_arprot O 3 reg -// master1_arqos O 4 reg -// master1_arregion O 4 reg // master1_rready O 1 // RDY_set_verbosity O 1 const -// trace_data_out_get O 362 reg -// RDY_trace_data_out_get O 1 reg -// RDY_hart0_server_run_halt_request_put O 1 const -// hart0_server_run_halt_response_get O 1 const -// RDY_hart0_server_run_halt_response_get O 1 const +// debug_module_mem_server_awready O 1 +// debug_module_mem_server_wready O 1 +// debug_module_mem_server_bid O 5 +// debug_module_mem_server_bresp O 2 +// debug_module_mem_server_bvalid O 1 +// debug_module_mem_server_arready O 1 +// debug_module_mem_server_rid O 5 +// debug_module_mem_server_rdata O 64 +// debug_module_mem_server_rresp O 2 +// debug_module_mem_server_rlast O 1 +// debug_module_mem_server_ruser O 1 +// debug_module_mem_server_rvalid O 1 +// RDY_hart0_run_halt_server_request_put O 1 reg +// hart0_run_halt_server_response_get O 1 reg +// RDY_hart0_run_halt_server_response_get O 1 reg +// RDY_hart0_gpr_mem_server_request_put O 1 reg +// hart0_gpr_mem_server_response_get O 65 reg +// RDY_hart0_gpr_mem_server_response_get O 1 reg +// RDY_hart0_fpr_mem_server_request_put O 1 reg +// hart0_fpr_mem_server_response_get O 65 reg +// RDY_hart0_fpr_mem_server_response_get O 1 reg +// RDY_hart0_csr_mem_server_request_put O 1 reg +// hart0_csr_mem_server_response_get O 65 reg +// RDY_hart0_csr_mem_server_response_get O 1 reg // RDY_hart0_put_other_req_put O 1 const -// RDY_hart0_gpr_mem_server_request_put O 1 const -// hart0_gpr_mem_server_response_get O 65 const -// RDY_hart0_gpr_mem_server_response_get O 1 const -// RDY_hart0_fpr_mem_server_request_put O 1 const -// hart0_fpr_mem_server_response_get O 65 const -// RDY_hart0_fpr_mem_server_response_get O 1 const -// RDY_hart0_csr_mem_server_request_put O 1 const -// hart0_csr_mem_server_response_get O 65 const -// RDY_hart0_csr_mem_server_response_get O 1 const // CLK I 1 clock // RST_N I 1 reset // start_startpc I 64 @@ -90,54 +98,209 @@ // start_fromhostAddr I 64 reg // master0_awready I 1 // master0_wready I 1 -// master0_bvalid I 1 -// master0_bid I 4 reg -// master0_bresp I 2 reg +// master0_bid I 5 +// master0_bresp I 2 // master0_arready I 1 -// master0_rvalid I 1 -// master0_rid I 4 reg -// master0_rdata I 64 reg -// master0_rresp I 2 reg -// master0_rlast I 1 reg +// master0_rid I 5 +// master0_rdata I 64 +// master0_rresp I 2 +// master0_rlast I 1 +// master0_ruser I 1 // master1_awready I 1 // master1_wready I 1 -// master1_bvalid I 1 -// master1_bid I 4 reg -// master1_bresp I 2 reg +// master1_bid I 4 +// master1_bresp I 2 // master1_arready I 1 -// master1_rvalid I 1 -// master1_rid I 4 reg -// master1_rdata I 64 reg -// master1_rresp I 2 reg -// master1_rlast I 1 reg -// m_external_interrupt_req_set_not_clear I 1 +// master1_rid I 4 +// master1_rdata I 64 +// master1_rresp I 2 +// master1_rlast I 1 +// master1_ruser I 1 +// m_external_interrupt_req_set_not_clear I 1 reg // s_external_interrupt_req_set_not_clear I 1 -// debug_external_interrupt_req_set_not_clear I 1 // non_maskable_interrupt_req_set_not_clear I 1 unused -// set_verbosity_verbosity I 4 reg -// hart0_server_run_halt_request_put I 1 unused -// hart0_put_other_req_put I 4 unused -// hart0_gpr_mem_server_request_put I 70 unused -// hart0_fpr_mem_server_request_put I 70 unused -// hart0_csr_mem_server_request_put I 77 unused -// EN_hart0_server_reset_request_put I 1 -// EN_hart0_server_reset_response_get I 1 +// set_verbosity_verbosity I 4 +// debug_module_mem_server_awid I 5 +// debug_module_mem_server_awaddr I 64 +// debug_module_mem_server_awlen I 8 +// debug_module_mem_server_awsize I 3 +// debug_module_mem_server_awburst I 2 +// debug_module_mem_server_awlock I 1 +// debug_module_mem_server_awcache I 4 +// debug_module_mem_server_awprot I 3 +// debug_module_mem_server_awqos I 4 +// debug_module_mem_server_awregion I 4 +// debug_module_mem_server_wdata I 64 +// debug_module_mem_server_wstrb I 8 +// debug_module_mem_server_wlast I 1 +// debug_module_mem_server_wuser I 1 +// debug_module_mem_server_bready I 1 +// debug_module_mem_server_arid I 5 +// debug_module_mem_server_araddr I 64 +// debug_module_mem_server_arlen I 8 +// debug_module_mem_server_arsize I 3 +// debug_module_mem_server_arburst I 2 +// debug_module_mem_server_arlock I 1 +// debug_module_mem_server_arcache I 4 +// debug_module_mem_server_arprot I 3 +// debug_module_mem_server_arqos I 4 +// debug_module_mem_server_arregion I 4 +// debug_module_mem_server_rready I 1 +// hart0_run_halt_server_request_put I 1 reg +// hart0_gpr_mem_server_request_put I 70 reg +// hart0_fpr_mem_server_request_put I 70 reg +// hart0_csr_mem_server_request_put I 77 reg +// hart0_put_other_req_put I 4 // EN_start I 1 +// master0_bvalid I 1 +// master0_rvalid I 1 +// master1_bvalid I 1 +// master1_rvalid I 1 // EN_set_verbosity I 1 -// EN_hart0_server_run_halt_request_put I 1 unused -// EN_hart0_put_other_req_put I 1 unused -// EN_hart0_gpr_mem_server_request_put I 1 unused -// EN_hart0_fpr_mem_server_request_put I 1 unused -// EN_hart0_csr_mem_server_request_put I 1 unused -// EN_trace_data_out_get I 1 -// EN_hart0_server_run_halt_response_get I 1 unused -// EN_hart0_gpr_mem_server_response_get I 1 unused -// EN_hart0_fpr_mem_server_response_get I 1 unused -// EN_hart0_csr_mem_server_response_get I 1 unused +// debug_module_mem_server_awvalid I 1 +// debug_module_mem_server_wvalid I 1 +// debug_module_mem_server_arvalid I 1 +// EN_hart0_run_halt_server_request_put I 1 +// EN_hart0_gpr_mem_server_request_put I 1 +// EN_hart0_fpr_mem_server_request_put I 1 +// EN_hart0_csr_mem_server_request_put I 1 +// EN_hart0_put_other_req_put I 1 +// EN_hart0_run_halt_server_response_get I 1 +// EN_hart0_gpr_mem_server_response_get I 1 +// EN_hart0_fpr_mem_server_response_get I 1 +// EN_hart0_csr_mem_server_response_get I 1 // // Combinational paths from inputs to outputs: -// (master0_awready, master0_wready) -> master0_bready -// (master1_awready, master1_wready) -> master1_bready +// (debug_module_mem_server_awid, +// debug_module_mem_server_awaddr, +// debug_module_mem_server_awlen, +// debug_module_mem_server_awsize, +// debug_module_mem_server_awburst, +// debug_module_mem_server_awlock, +// debug_module_mem_server_awcache, +// debug_module_mem_server_awprot, +// debug_module_mem_server_awqos, +// debug_module_mem_server_awregion, +// debug_module_mem_server_wdata, +// debug_module_mem_server_wstrb, +// debug_module_mem_server_wlast, +// debug_module_mem_server_wuser, +// debug_module_mem_server_awvalid, +// debug_module_mem_server_wvalid) -> debug_module_mem_server_bid +// (debug_module_mem_server_awid, +// debug_module_mem_server_awaddr, +// debug_module_mem_server_awlen, +// debug_module_mem_server_awsize, +// debug_module_mem_server_awburst, +// debug_module_mem_server_awlock, +// debug_module_mem_server_awcache, +// debug_module_mem_server_awprot, +// debug_module_mem_server_awqos, +// debug_module_mem_server_awregion, +// debug_module_mem_server_wdata, +// debug_module_mem_server_wstrb, +// debug_module_mem_server_wlast, +// debug_module_mem_server_wuser, +// debug_module_mem_server_awvalid, +// debug_module_mem_server_wvalid) -> debug_module_mem_server_bresp +// (debug_module_mem_server_awid, +// debug_module_mem_server_awaddr, +// debug_module_mem_server_awlen, +// debug_module_mem_server_awsize, +// debug_module_mem_server_awburst, +// debug_module_mem_server_awlock, +// debug_module_mem_server_awcache, +// debug_module_mem_server_awprot, +// debug_module_mem_server_awqos, +// debug_module_mem_server_awregion, +// debug_module_mem_server_wdata, +// debug_module_mem_server_wstrb, +// debug_module_mem_server_wlast, +// debug_module_mem_server_wuser, +// debug_module_mem_server_awvalid, +// debug_module_mem_server_wvalid) -> debug_module_mem_server_buser +// (debug_module_mem_server_awid, +// debug_module_mem_server_awaddr, +// debug_module_mem_server_awlen, +// debug_module_mem_server_awsize, +// debug_module_mem_server_awburst, +// debug_module_mem_server_awlock, +// debug_module_mem_server_awcache, +// debug_module_mem_server_awprot, +// debug_module_mem_server_awqos, +// debug_module_mem_server_awregion, +// debug_module_mem_server_wdata, +// debug_module_mem_server_wstrb, +// debug_module_mem_server_wlast, +// debug_module_mem_server_wuser, +// debug_module_mem_server_awvalid, +// debug_module_mem_server_wvalid) -> debug_module_mem_server_bvalid +// (debug_module_mem_server_arid, +// debug_module_mem_server_araddr, +// debug_module_mem_server_arlen, +// debug_module_mem_server_arsize, +// debug_module_mem_server_arburst, +// debug_module_mem_server_arlock, +// debug_module_mem_server_arcache, +// debug_module_mem_server_arprot, +// debug_module_mem_server_arqos, +// debug_module_mem_server_arregion, +// debug_module_mem_server_arvalid) -> debug_module_mem_server_rid +// (debug_module_mem_server_arid, +// debug_module_mem_server_araddr, +// debug_module_mem_server_arlen, +// debug_module_mem_server_arsize, +// debug_module_mem_server_arburst, +// debug_module_mem_server_arlock, +// debug_module_mem_server_arcache, +// debug_module_mem_server_arprot, +// debug_module_mem_server_arqos, +// debug_module_mem_server_arregion, +// debug_module_mem_server_arvalid) -> debug_module_mem_server_rdata +// (debug_module_mem_server_arid, +// debug_module_mem_server_araddr, +// debug_module_mem_server_arlen, +// debug_module_mem_server_arsize, +// debug_module_mem_server_arburst, +// debug_module_mem_server_arlock, +// debug_module_mem_server_arcache, +// debug_module_mem_server_arprot, +// debug_module_mem_server_arqos, +// debug_module_mem_server_arregion, +// debug_module_mem_server_arvalid) -> debug_module_mem_server_rresp +// (debug_module_mem_server_arid, +// debug_module_mem_server_araddr, +// debug_module_mem_server_arlen, +// debug_module_mem_server_arsize, +// debug_module_mem_server_arburst, +// debug_module_mem_server_arlock, +// debug_module_mem_server_arcache, +// debug_module_mem_server_arprot, +// debug_module_mem_server_arqos, +// debug_module_mem_server_arregion, +// debug_module_mem_server_arvalid) -> debug_module_mem_server_rlast +// (debug_module_mem_server_arid, +// debug_module_mem_server_araddr, +// debug_module_mem_server_arlen, +// debug_module_mem_server_arsize, +// debug_module_mem_server_arburst, +// debug_module_mem_server_arlock, +// debug_module_mem_server_arcache, +// debug_module_mem_server_arprot, +// debug_module_mem_server_arqos, +// debug_module_mem_server_arregion, +// debug_module_mem_server_arvalid) -> debug_module_mem_server_ruser +// (debug_module_mem_server_arid, +// debug_module_mem_server_araddr, +// debug_module_mem_server_arlen, +// debug_module_mem_server_arsize, +// debug_module_mem_server_arburst, +// debug_module_mem_server_arlock, +// debug_module_mem_server_arcache, +// debug_module_mem_server_arprot, +// debug_module_mem_server_arqos, +// debug_module_mem_server_arregion, +// debug_module_mem_server_arvalid) -> debug_module_mem_server_rvalid // // @@ -157,20 +320,12 @@ module mkProc(CLK, RST_N, - EN_hart0_server_reset_request_put, - RDY_hart0_server_reset_request_put, - - EN_hart0_server_reset_response_get, - RDY_hart0_server_reset_response_get, - start_startpc, start_tohostAddr, start_fromhostAddr, EN_start, RDY_start, - master0_awvalid, - master0_awid, master0_awaddr, @@ -191,28 +346,28 @@ module mkProc(CLK, master0_awregion, + master0_awvalid, + master0_awready, - master0_wvalid, - - master0_wid, - master0_wdata, master0_wstrb, master0_wlast, + master0_wuser, + + master0_wvalid, + master0_wready, - master0_bvalid, master0_bid, master0_bresp, + master0_bvalid, master0_bready, - master0_arvalid, - master0_arid, master0_araddr, @@ -233,18 +388,19 @@ module mkProc(CLK, master0_arregion, + master0_arvalid, + master0_arready, - master0_rvalid, master0_rid, master0_rdata, master0_rresp, master0_rlast, + master0_ruser, + master0_rvalid, master0_rready, - master1_awvalid, - master1_awid, master1_awaddr, @@ -265,28 +421,28 @@ module mkProc(CLK, master1_awregion, + master1_awvalid, + master1_awready, - master1_wvalid, - - master1_wid, - master1_wdata, master1_wstrb, master1_wlast, + master1_wuser, + + master1_wvalid, + master1_wready, - master1_bvalid, master1_bid, master1_bresp, + master1_bvalid, master1_bready, - master1_arvalid, - master1_arid, master1_araddr, @@ -307,13 +463,16 @@ module mkProc(CLK, master1_arregion, + master1_arvalid, + master1_arready, - master1_rvalid, master1_rid, master1_rdata, master1_rresp, master1_rlast, + master1_ruser, + master1_rvalid, master1_rready, @@ -321,29 +480,77 @@ module mkProc(CLK, s_external_interrupt_req_set_not_clear, - debug_external_interrupt_req_set_not_clear, - non_maskable_interrupt_req_set_not_clear, set_verbosity_verbosity, EN_set_verbosity, RDY_set_verbosity, - EN_trace_data_out_get, - trace_data_out_get, - RDY_trace_data_out_get, + debug_module_mem_server_awid, + debug_module_mem_server_awaddr, + debug_module_mem_server_awlen, + debug_module_mem_server_awsize, + debug_module_mem_server_awburst, + debug_module_mem_server_awlock, + debug_module_mem_server_awcache, + debug_module_mem_server_awprot, + debug_module_mem_server_awqos, + debug_module_mem_server_awregion, + debug_module_mem_server_awvalid, - hart0_server_run_halt_request_put, - EN_hart0_server_run_halt_request_put, - RDY_hart0_server_run_halt_request_put, + debug_module_mem_server_awready, - EN_hart0_server_run_halt_response_get, - hart0_server_run_halt_response_get, - RDY_hart0_server_run_halt_response_get, + debug_module_mem_server_wdata, + debug_module_mem_server_wstrb, + debug_module_mem_server_wlast, + debug_module_mem_server_wuser, + debug_module_mem_server_wvalid, - hart0_put_other_req_put, - EN_hart0_put_other_req_put, - RDY_hart0_put_other_req_put, + debug_module_mem_server_wready, + + debug_module_mem_server_bid, + + debug_module_mem_server_bresp, + + debug_module_mem_server_bvalid, + + debug_module_mem_server_bready, + + debug_module_mem_server_arid, + debug_module_mem_server_araddr, + debug_module_mem_server_arlen, + debug_module_mem_server_arsize, + debug_module_mem_server_arburst, + debug_module_mem_server_arlock, + debug_module_mem_server_arcache, + debug_module_mem_server_arprot, + debug_module_mem_server_arqos, + debug_module_mem_server_arregion, + debug_module_mem_server_arvalid, + + debug_module_mem_server_arready, + + debug_module_mem_server_rid, + + debug_module_mem_server_rdata, + + debug_module_mem_server_rresp, + + debug_module_mem_server_rlast, + + debug_module_mem_server_ruser, + + debug_module_mem_server_rvalid, + + debug_module_mem_server_rready, + + hart0_run_halt_server_request_put, + EN_hart0_run_halt_server_request_put, + RDY_hart0_run_halt_server_request_put, + + EN_hart0_run_halt_server_response_get, + hart0_run_halt_server_response_get, + RDY_hart0_run_halt_server_response_get, hart0_gpr_mem_server_request_put, EN_hart0_gpr_mem_server_request_put, @@ -367,18 +574,14 @@ module mkProc(CLK, EN_hart0_csr_mem_server_response_get, hart0_csr_mem_server_response_get, - RDY_hart0_csr_mem_server_response_get); + RDY_hart0_csr_mem_server_response_get, + + hart0_put_other_req_put, + EN_hart0_put_other_req_put, + RDY_hart0_put_other_req_put); input CLK; input RST_N; - // action method hart0_server_reset_request_put - input EN_hart0_server_reset_request_put; - output RDY_hart0_server_reset_request_put; - - // action method hart0_server_reset_response_get - input EN_hart0_server_reset_response_get; - output RDY_hart0_server_reset_response_get; - // action method start input [63 : 0] start_startpc; input [63 : 0] start_tohostAddr; @@ -386,232 +589,230 @@ module mkProc(CLK, input EN_start; output RDY_start; - // value method master0_m_awvalid - output master0_awvalid; + // value method master0_aw_awid + output [4 : 0] master0_awid; - // value method master0_m_awid - output [3 : 0] master0_awid; - - // value method master0_m_awaddr + // value method master0_aw_awaddr output [63 : 0] master0_awaddr; - // value method master0_m_awlen + // value method master0_aw_awlen output [7 : 0] master0_awlen; - // value method master0_m_awsize + // value method master0_aw_awsize output [2 : 0] master0_awsize; - // value method master0_m_awburst + // value method master0_aw_awburst output [1 : 0] master0_awburst; - // value method master0_m_awlock + // value method master0_aw_awlock output master0_awlock; - // value method master0_m_awcache + // value method master0_aw_awcache output [3 : 0] master0_awcache; - // value method master0_m_awprot + // value method master0_aw_awprot output [2 : 0] master0_awprot; - // value method master0_m_awqos + // value method master0_aw_awqos output [3 : 0] master0_awqos; - // value method master0_m_awregion + // value method master0_aw_awregion output [3 : 0] master0_awregion; - // value method master0_m_awuser + // value method master0_aw_awuser - // action method master0_m_awready + // value method master0_aw_awvalid + output master0_awvalid; + + // action method master0_aw_awready input master0_awready; - // value method master0_m_wvalid - output master0_wvalid; - - // value method master0_m_wid - output [3 : 0] master0_wid; - - // value method master0_m_wdata + // value method master0_w_wdata output [63 : 0] master0_wdata; - // value method master0_m_wstrb + // value method master0_w_wstrb output [7 : 0] master0_wstrb; - // value method master0_m_wlast + // value method master0_w_wlast output master0_wlast; - // value method master0_m_wuser + // value method master0_w_wuser + output master0_wuser; - // action method master0_m_wready + // value method master0_w_wvalid + output master0_wvalid; + + // action method master0_w_wready input master0_wready; - // action method master0_m_bvalid - input master0_bvalid; - input [3 : 0] master0_bid; + // action method master0_b_bflit + input [4 : 0] master0_bid; input [1 : 0] master0_bresp; + input master0_bvalid; - // value method master0_m_bready + // value method master0_b_bready output master0_bready; - // value method master0_m_arvalid - output master0_arvalid; + // value method master0_ar_arid + output [4 : 0] master0_arid; - // value method master0_m_arid - output [3 : 0] master0_arid; - - // value method master0_m_araddr + // value method master0_ar_araddr output [63 : 0] master0_araddr; - // value method master0_m_arlen + // value method master0_ar_arlen output [7 : 0] master0_arlen; - // value method master0_m_arsize + // value method master0_ar_arsize output [2 : 0] master0_arsize; - // value method master0_m_arburst + // value method master0_ar_arburst output [1 : 0] master0_arburst; - // value method master0_m_arlock + // value method master0_ar_arlock output master0_arlock; - // value method master0_m_arcache + // value method master0_ar_arcache output [3 : 0] master0_arcache; - // value method master0_m_arprot + // value method master0_ar_arprot output [2 : 0] master0_arprot; - // value method master0_m_arqos + // value method master0_ar_arqos output [3 : 0] master0_arqos; - // value method master0_m_arregion + // value method master0_ar_arregion output [3 : 0] master0_arregion; - // value method master0_m_aruser + // value method master0_ar_aruser - // action method master0_m_arready + // value method master0_ar_arvalid + output master0_arvalid; + + // action method master0_ar_arready input master0_arready; - // action method master0_m_rvalid - input master0_rvalid; - input [3 : 0] master0_rid; + // action method master0_r_rflit + input [4 : 0] master0_rid; input [63 : 0] master0_rdata; input [1 : 0] master0_rresp; input master0_rlast; + input master0_ruser; + input master0_rvalid; - // value method master0_m_rready + // value method master0_r_rready output master0_rready; - // value method master1_m_awvalid - output master1_awvalid; - - // value method master1_m_awid + // value method master1_aw_awid output [3 : 0] master1_awid; - // value method master1_m_awaddr + // value method master1_aw_awaddr output [63 : 0] master1_awaddr; - // value method master1_m_awlen + // value method master1_aw_awlen output [7 : 0] master1_awlen; - // value method master1_m_awsize + // value method master1_aw_awsize output [2 : 0] master1_awsize; - // value method master1_m_awburst + // value method master1_aw_awburst output [1 : 0] master1_awburst; - // value method master1_m_awlock + // value method master1_aw_awlock output master1_awlock; - // value method master1_m_awcache + // value method master1_aw_awcache output [3 : 0] master1_awcache; - // value method master1_m_awprot + // value method master1_aw_awprot output [2 : 0] master1_awprot; - // value method master1_m_awqos + // value method master1_aw_awqos output [3 : 0] master1_awqos; - // value method master1_m_awregion + // value method master1_aw_awregion output [3 : 0] master1_awregion; - // value method master1_m_awuser + // value method master1_aw_awuser - // action method master1_m_awready + // value method master1_aw_awvalid + output master1_awvalid; + + // action method master1_aw_awready input master1_awready; - // value method master1_m_wvalid - output master1_wvalid; - - // value method master1_m_wid - output [3 : 0] master1_wid; - - // value method master1_m_wdata + // value method master1_w_wdata output [63 : 0] master1_wdata; - // value method master1_m_wstrb + // value method master1_w_wstrb output [7 : 0] master1_wstrb; - // value method master1_m_wlast + // value method master1_w_wlast output master1_wlast; - // value method master1_m_wuser + // value method master1_w_wuser + output master1_wuser; - // action method master1_m_wready + // value method master1_w_wvalid + output master1_wvalid; + + // action method master1_w_wready input master1_wready; - // action method master1_m_bvalid - input master1_bvalid; + // action method master1_b_bflit input [3 : 0] master1_bid; input [1 : 0] master1_bresp; + input master1_bvalid; - // value method master1_m_bready + // value method master1_b_bready output master1_bready; - // value method master1_m_arvalid - output master1_arvalid; - - // value method master1_m_arid + // value method master1_ar_arid output [3 : 0] master1_arid; - // value method master1_m_araddr + // value method master1_ar_araddr output [63 : 0] master1_araddr; - // value method master1_m_arlen + // value method master1_ar_arlen output [7 : 0] master1_arlen; - // value method master1_m_arsize + // value method master1_ar_arsize output [2 : 0] master1_arsize; - // value method master1_m_arburst + // value method master1_ar_arburst output [1 : 0] master1_arburst; - // value method master1_m_arlock + // value method master1_ar_arlock output master1_arlock; - // value method master1_m_arcache + // value method master1_ar_arcache output [3 : 0] master1_arcache; - // value method master1_m_arprot + // value method master1_ar_arprot output [2 : 0] master1_arprot; - // value method master1_m_arqos + // value method master1_ar_arqos output [3 : 0] master1_arqos; - // value method master1_m_arregion + // value method master1_ar_arregion output [3 : 0] master1_arregion; - // value method master1_m_aruser + // value method master1_ar_aruser - // action method master1_m_arready + // value method master1_ar_arvalid + output master1_arvalid; + + // action method master1_ar_arready input master1_arready; - // action method master1_m_rvalid - input master1_rvalid; + // action method master1_r_rflit input [3 : 0] master1_rid; input [63 : 0] master1_rdata; input [1 : 0] master1_rresp; input master1_rlast; + input master1_ruser; + input master1_rvalid; - // value method master1_m_rready + // value method master1_r_rready output master1_rready; // action method m_external_interrupt_req @@ -620,9 +821,6 @@ module mkProc(CLK, // action method s_external_interrupt_req input s_external_interrupt_req_set_not_clear; - // action method debug_external_interrupt_req - input debug_external_interrupt_req_set_not_clear; - // action method non_maskable_interrupt_req input non_maskable_interrupt_req_set_not_clear; @@ -631,25 +829,92 @@ module mkProc(CLK, input EN_set_verbosity; output RDY_set_verbosity; - // actionvalue method trace_data_out_get - input EN_trace_data_out_get; - output [361 : 0] trace_data_out_get; - output RDY_trace_data_out_get; + // action method debug_module_mem_server_aw_awflit + input [4 : 0] debug_module_mem_server_awid; + input [63 : 0] debug_module_mem_server_awaddr; + input [7 : 0] debug_module_mem_server_awlen; + input [2 : 0] debug_module_mem_server_awsize; + input [1 : 0] debug_module_mem_server_awburst; + input debug_module_mem_server_awlock; + input [3 : 0] debug_module_mem_server_awcache; + input [2 : 0] debug_module_mem_server_awprot; + input [3 : 0] debug_module_mem_server_awqos; + input [3 : 0] debug_module_mem_server_awregion; + input debug_module_mem_server_awvalid; - // action method hart0_server_run_halt_request_put - input hart0_server_run_halt_request_put; - input EN_hart0_server_run_halt_request_put; - output RDY_hart0_server_run_halt_request_put; + // value method debug_module_mem_server_aw_awready + output debug_module_mem_server_awready; - // actionvalue method hart0_server_run_halt_response_get - input EN_hart0_server_run_halt_response_get; - output hart0_server_run_halt_response_get; - output RDY_hart0_server_run_halt_response_get; + // action method debug_module_mem_server_w_wflit + input [63 : 0] debug_module_mem_server_wdata; + input [7 : 0] debug_module_mem_server_wstrb; + input debug_module_mem_server_wlast; + input debug_module_mem_server_wuser; + input debug_module_mem_server_wvalid; - // action method hart0_put_other_req_put - input [3 : 0] hart0_put_other_req_put; - input EN_hart0_put_other_req_put; - output RDY_hart0_put_other_req_put; + // value method debug_module_mem_server_w_wready + output debug_module_mem_server_wready; + + // value method debug_module_mem_server_b_bid + output [4 : 0] debug_module_mem_server_bid; + + // value method debug_module_mem_server_b_bresp + output [1 : 0] debug_module_mem_server_bresp; + + // value method debug_module_mem_server_b_buser + + // value method debug_module_mem_server_b_bvalid + output debug_module_mem_server_bvalid; + + // action method debug_module_mem_server_b_bready + input debug_module_mem_server_bready; + + // action method debug_module_mem_server_ar_arflit + input [4 : 0] debug_module_mem_server_arid; + input [63 : 0] debug_module_mem_server_araddr; + input [7 : 0] debug_module_mem_server_arlen; + input [2 : 0] debug_module_mem_server_arsize; + input [1 : 0] debug_module_mem_server_arburst; + input debug_module_mem_server_arlock; + input [3 : 0] debug_module_mem_server_arcache; + input [2 : 0] debug_module_mem_server_arprot; + input [3 : 0] debug_module_mem_server_arqos; + input [3 : 0] debug_module_mem_server_arregion; + input debug_module_mem_server_arvalid; + + // value method debug_module_mem_server_ar_arready + output debug_module_mem_server_arready; + + // value method debug_module_mem_server_r_rid + output [4 : 0] debug_module_mem_server_rid; + + // value method debug_module_mem_server_r_rdata + output [63 : 0] debug_module_mem_server_rdata; + + // value method debug_module_mem_server_r_rresp + output [1 : 0] debug_module_mem_server_rresp; + + // value method debug_module_mem_server_r_rlast + output debug_module_mem_server_rlast; + + // value method debug_module_mem_server_r_ruser + output debug_module_mem_server_ruser; + + // value method debug_module_mem_server_r_rvalid + output debug_module_mem_server_rvalid; + + // action method debug_module_mem_server_r_rready + input debug_module_mem_server_rready; + + // action method hart0_run_halt_server_request_put + input hart0_run_halt_server_request_put; + input EN_hart0_run_halt_server_request_put; + output RDY_hart0_run_halt_server_request_put; + + // actionvalue method hart0_run_halt_server_response_get + input EN_hart0_run_halt_server_response_get; + output hart0_run_halt_server_response_get; + output RDY_hart0_run_halt_server_response_get; // action method hart0_gpr_mem_server_request_put input [69 : 0] hart0_gpr_mem_server_request_put; @@ -681,12 +946,17 @@ module mkProc(CLK, output [64 : 0] hart0_csr_mem_server_response_get; output RDY_hart0_csr_mem_server_response_get; + // action method hart0_put_other_req_put + input [3 : 0] hart0_put_other_req_put; + input EN_hart0_put_other_req_put; + output RDY_hart0_put_other_req_put; + // signals for module outputs - wire [361 : 0] trace_data_out_get; wire [64 : 0] hart0_csr_mem_server_response_get, hart0_fpr_mem_server_response_get, hart0_gpr_mem_server_response_get; - wire [63 : 0] master0_araddr, + wire [63 : 0] debug_module_mem_server_rdata, + master0_araddr, master0_awaddr, master0_wdata, master1_araddr, @@ -698,15 +968,16 @@ module mkProc(CLK, master1_arlen, master1_awlen, master1_wstrb; - wire [3 : 0] master0_arcache, + wire [4 : 0] debug_module_mem_server_bid, + debug_module_mem_server_rid, master0_arid, + master0_awid; + wire [3 : 0] master0_arcache, master0_arqos, master0_arregion, master0_awcache, - master0_awid, master0_awqos, master0_awregion, - master0_wid, master1_arcache, master1_arid, master1_arqos, @@ -714,8 +985,7 @@ module mkProc(CLK, master1_awcache, master1_awid, master1_awqos, - master1_awregion, - master1_wid; + master1_awregion; wire [2 : 0] master0_arprot, master0_arsize, master0_awprot, @@ -724,7 +994,9 @@ module mkProc(CLK, master1_arsize, master1_awprot, master1_awsize; - wire [1 : 0] master0_arburst, + wire [1 : 0] debug_module_mem_server_bresp, + debug_module_mem_server_rresp, + master0_arburst, master0_awburst, master1_arburst, master1_awburst; @@ -735,14 +1007,18 @@ module mkProc(CLK, RDY_hart0_gpr_mem_server_request_put, RDY_hart0_gpr_mem_server_response_get, RDY_hart0_put_other_req_put, - RDY_hart0_server_reset_request_put, - RDY_hart0_server_reset_response_get, - RDY_hart0_server_run_halt_request_put, - RDY_hart0_server_run_halt_response_get, + RDY_hart0_run_halt_server_request_put, + RDY_hart0_run_halt_server_response_get, RDY_set_verbosity, RDY_start, - RDY_trace_data_out_get, - hart0_server_run_halt_response_get, + debug_module_mem_server_arready, + debug_module_mem_server_awready, + debug_module_mem_server_bvalid, + debug_module_mem_server_rlast, + debug_module_mem_server_ruser, + debug_module_mem_server_rvalid, + debug_module_mem_server_wready, + hart0_run_halt_server_response_get, master0_arlock, master0_arvalid, master0_awlock, @@ -750,6 +1026,7 @@ module mkProc(CLK, master0_bready, master0_rready, master0_wlast, + master0_wuser, master0_wvalid, master1_arlock, master1_arvalid, @@ -758,57 +1035,115 @@ module mkProc(CLK, master1_bready, master1_rready, master1_wlast, + master1_wuser, master1_wvalid; // inlined wires - wire [580 : 0] enqDst_1_0_lat_0$wget; - wire [579 : 0] propDstData_1_0_lat_0$wget, propDstData_1_1_lat_0$wget; - wire [73 : 0] enqDst_0_lat_0$wget; - wire [72 : 0] propDstData_0_lat_0$wget, propDstData_1_lat_0$wget; - wire [65 : 0] enqDst_0_lat_0_1$wget; + wire [584 : 0] enqDst_1_0_lat_0$wget; + wire [583 : 0] propDstData_1_0_lat_0$wget, propDstData_1_1_lat_0$wget; + wire [98 : 0] llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1, + llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read, + llc_axi4_adapter_master_xactor_shim_arff_rv$port2__read, + llc_axi4_adapter_master_xactor_shim_arff_rv$port3__read, + llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1, + llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read, + llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read, + llc_axi4_adapter_master_xactor_shim_awff_rv$port3__read, + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port0__write_1, + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read, + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port2__read, + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port3__read, + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port0__write_1, + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read, + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read, + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port3__read; + wire [97 : 0] llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget, + llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget, + mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1, + mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read, + mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read, + mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read, + mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1, + mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read, + mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read, + mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read; + wire [74 : 0] llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1, + llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read, + llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read, + llc_axi4_adapter_master_xactor_shim_wff_rv$port3__read, + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1, + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read, + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read, + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port3__read, + mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1, + mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read, + mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read, + mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read; + wire [73 : 0] enqDst_0_lat_0$wget, + llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1, + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read, + llc_axi4_adapter_master_xactor_shim_rff_rv$port2__read, + llc_axi4_adapter_master_xactor_shim_rff_rv$port3__read, + llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1, + llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read, + llc_mem_server_axi4_slave_xactor_shim_rff_rv$port2__read, + llc_mem_server_axi4_slave_xactor_shim_rff_rv$port3__read, + llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget; + wire [72 : 0] llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget, + mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1, + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read, + mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read, + mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read, + propDstData_0_lat_0$wget, + propDstData_1_lat_0$wget; + wire [71 : 0] mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget; + wire [65 : 0] llc_mem_server_enqDst_0_lat_0$wget; wire [64 : 0] mmioPlatform_toHostQ_enqReq_lat_0$wget; + wire [7 : 0] llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1, + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read, + llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read, + llc_axi4_adapter_master_xactor_shim_bff_rv$port3__read, + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read, + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read, + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port3__read; + wire [6 : 0] llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget, + mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1, + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read, + mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read, + mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read; + wire [5 : 0] mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget; wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read, - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1, - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read, - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read; - wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write, - llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read, - llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read, - llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write, - llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read, - llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read, - llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write, - llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read, - llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read, - llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write, - llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read, - llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read, - llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write, - llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read, - llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read, + mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read; + wire enqDst_0_lat_0$whas, + enqDst_1_0_lat_0$whas, + llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write, + llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write, + llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas, + llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas, + llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas, + llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas, + llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas, + llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas, + llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas, + llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas, + llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas, + llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas, + llc_mem_server_propDstIdx_0_lat_1$whas, mmioPlatform_fromHostQ_deqReq_lat_0$whas, mmioPlatform_toHostQ_enqReq_lat_0$whas, - mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write, - mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read, - mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read, - mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write, - mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read, - mmio_axi4_adapter_master_xactor_crg_rd_data_full$port3__read, - mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write, - mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read, - mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read, - mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write, - mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read, - mmio_axi4_adapter_master_xactor_crg_wr_data_full$port3__read, - mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write, - mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read, - mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read, - propDstIdx_0_lat_1$whas, - propDstIdx_1_0_lat_1$whas, + mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write, + mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write, + mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write, + mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write, + mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas, + mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas, + mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas, + mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas, + mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas, propDstIdx_1_1_lat_1$whas, propDstIdx_1_lat_1$whas; @@ -822,14 +1157,9 @@ module mkProc(CLK, wire [73 : 0] enqDst_0_rl$D_IN; wire enqDst_0_rl$EN; - // register enqDst_0_rl_1 - reg [65 : 0] enqDst_0_rl_1; - wire [65 : 0] enqDst_0_rl_1$D_IN; - wire enqDst_0_rl_1$EN; - // register enqDst_1_0_rl - reg [580 : 0] enqDst_1_0_rl; - wire [580 : 0] enqDst_1_0_rl$D_IN; + reg [584 : 0] enqDst_1_0_rl; + wire [584 : 0] enqDst_1_0_rl$D_IN; wire enqDst_1_0_rl$EN; // register llc_axi4_adapter_cfg_verbosity @@ -842,59 +1172,39 @@ module mkProc(CLK, wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN; wire llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN; - // register llc_axi4_adapter_master_xactor_crg_rd_addr_full - reg llc_axi4_adapter_master_xactor_crg_rd_addr_full; - wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN, - llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN; + // register llc_axi4_adapter_master_xactor_clearing + reg llc_axi4_adapter_master_xactor_clearing; + wire llc_axi4_adapter_master_xactor_clearing$D_IN, + llc_axi4_adapter_master_xactor_clearing$EN; - // register llc_axi4_adapter_master_xactor_crg_rd_data_full - reg llc_axi4_adapter_master_xactor_crg_rd_data_full; - wire llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN, - llc_axi4_adapter_master_xactor_crg_rd_data_full$EN; + // register llc_axi4_adapter_master_xactor_shim_arff_rv + reg [98 : 0] llc_axi4_adapter_master_xactor_shim_arff_rv; + wire [98 : 0] llc_axi4_adapter_master_xactor_shim_arff_rv$D_IN; + wire llc_axi4_adapter_master_xactor_shim_arff_rv$EN; - // register llc_axi4_adapter_master_xactor_crg_wr_addr_full - reg llc_axi4_adapter_master_xactor_crg_wr_addr_full; - wire llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN, - llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN; + // register llc_axi4_adapter_master_xactor_shim_awff_rv + reg [98 : 0] llc_axi4_adapter_master_xactor_shim_awff_rv; + wire [98 : 0] llc_axi4_adapter_master_xactor_shim_awff_rv$D_IN; + wire llc_axi4_adapter_master_xactor_shim_awff_rv$EN; - // register llc_axi4_adapter_master_xactor_crg_wr_data_full - reg llc_axi4_adapter_master_xactor_crg_wr_data_full; - wire llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN, - llc_axi4_adapter_master_xactor_crg_wr_data_full$EN; + // register llc_axi4_adapter_master_xactor_shim_bff_rv + reg [7 : 0] llc_axi4_adapter_master_xactor_shim_bff_rv; + wire [7 : 0] llc_axi4_adapter_master_xactor_shim_bff_rv$D_IN; + wire llc_axi4_adapter_master_xactor_shim_bff_rv$EN; - // register llc_axi4_adapter_master_xactor_crg_wr_resp_full - reg llc_axi4_adapter_master_xactor_crg_wr_resp_full; - wire llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN, - llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN; + // register llc_axi4_adapter_master_xactor_shim_rff_rv + reg [73 : 0] llc_axi4_adapter_master_xactor_shim_rff_rv; + wire [73 : 0] llc_axi4_adapter_master_xactor_shim_rff_rv$D_IN; + wire llc_axi4_adapter_master_xactor_shim_rff_rv$EN; - // register llc_axi4_adapter_master_xactor_rg_rd_addr - reg [96 : 0] llc_axi4_adapter_master_xactor_rg_rd_addr; - wire [96 : 0] llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN; - wire llc_axi4_adapter_master_xactor_rg_rd_addr$EN; - - // register llc_axi4_adapter_master_xactor_rg_rd_data - reg [70 : 0] llc_axi4_adapter_master_xactor_rg_rd_data; - wire [70 : 0] llc_axi4_adapter_master_xactor_rg_rd_data$D_IN; - wire llc_axi4_adapter_master_xactor_rg_rd_data$EN; - - // register llc_axi4_adapter_master_xactor_rg_wr_addr - reg [96 : 0] llc_axi4_adapter_master_xactor_rg_wr_addr; - wire [96 : 0] llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN; - wire llc_axi4_adapter_master_xactor_rg_wr_addr$EN; - - // register llc_axi4_adapter_master_xactor_rg_wr_data - reg [76 : 0] llc_axi4_adapter_master_xactor_rg_wr_data; - wire [76 : 0] llc_axi4_adapter_master_xactor_rg_wr_data$D_IN; - wire llc_axi4_adapter_master_xactor_rg_wr_data$EN; - - // register llc_axi4_adapter_master_xactor_rg_wr_resp - reg [5 : 0] llc_axi4_adapter_master_xactor_rg_wr_resp; - wire [5 : 0] llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN; - wire llc_axi4_adapter_master_xactor_rg_wr_resp$EN; + // register llc_axi4_adapter_master_xactor_shim_wff_rv + reg [74 : 0] llc_axi4_adapter_master_xactor_shim_wff_rv; + wire [74 : 0] llc_axi4_adapter_master_xactor_shim_wff_rv$D_IN; + wire llc_axi4_adapter_master_xactor_shim_wff_rv$EN; // register llc_axi4_adapter_rg_cline - reg [511 : 0] llc_axi4_adapter_rg_cline; - wire [511 : 0] llc_axi4_adapter_rg_cline$D_IN; + reg [515 : 0] llc_axi4_adapter_rg_cline; + wire [515 : 0] llc_axi4_adapter_rg_cline$D_IN; wire llc_axi4_adapter_rg_cline$EN; // register llc_axi4_adapter_rg_rd_req_beat @@ -912,14 +1222,73 @@ module mkProc(CLK, wire [2 : 0] llc_axi4_adapter_rg_wr_req_beat$D_IN; wire llc_axi4_adapter_rg_wr_req_beat$EN; - // register llc_axi4_adapter_rg_wr_rsp_beat - reg [2 : 0] llc_axi4_adapter_rg_wr_rsp_beat; - wire [2 : 0] llc_axi4_adapter_rg_wr_rsp_beat$D_IN; - wire llc_axi4_adapter_rg_wr_rsp_beat$EN; + // register llc_mem_server_axi4_slave_xactor_clearing + reg llc_mem_server_axi4_slave_xactor_clearing; + wire llc_mem_server_axi4_slave_xactor_clearing$D_IN, + llc_mem_server_axi4_slave_xactor_clearing$EN; + + // register llc_mem_server_axi4_slave_xactor_shim_arff_rv + reg [98 : 0] llc_mem_server_axi4_slave_xactor_shim_arff_rv; + wire [98 : 0] llc_mem_server_axi4_slave_xactor_shim_arff_rv$D_IN; + wire llc_mem_server_axi4_slave_xactor_shim_arff_rv$EN; + + // register llc_mem_server_axi4_slave_xactor_shim_awff_rv + reg [98 : 0] llc_mem_server_axi4_slave_xactor_shim_awff_rv; + wire [98 : 0] llc_mem_server_axi4_slave_xactor_shim_awff_rv$D_IN; + wire llc_mem_server_axi4_slave_xactor_shim_awff_rv$EN; + + // register llc_mem_server_axi4_slave_xactor_shim_bff_rv + reg [7 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rv; + wire [7 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rv$D_IN; + wire llc_mem_server_axi4_slave_xactor_shim_bff_rv$EN; + + // register llc_mem_server_axi4_slave_xactor_shim_rff_rv + reg [73 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rv; + wire [73 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rv$D_IN; + wire llc_mem_server_axi4_slave_xactor_shim_rff_rv$EN; + + // register llc_mem_server_axi4_slave_xactor_shim_wff_rv + reg [74 : 0] llc_mem_server_axi4_slave_xactor_shim_wff_rv; + wire [74 : 0] llc_mem_server_axi4_slave_xactor_shim_wff_rv$D_IN; + wire llc_mem_server_axi4_slave_xactor_shim_wff_rv$EN; + + // register llc_mem_server_enqDst_0_rl + reg [65 : 0] llc_mem_server_enqDst_0_rl; + wire [65 : 0] llc_mem_server_enqDst_0_rl$D_IN; + wire llc_mem_server_enqDst_0_rl$EN; + + // register llc_mem_server_propDstData_0_rl + reg [64 : 0] llc_mem_server_propDstData_0_rl; + wire [64 : 0] llc_mem_server_propDstData_0_rl$D_IN; + wire llc_mem_server_propDstData_0_rl$EN; + + // register llc_mem_server_propDstIdx_0_rl + reg llc_mem_server_propDstIdx_0_rl; + wire llc_mem_server_propDstIdx_0_rl$D_IN, llc_mem_server_propDstIdx_0_rl$EN; + + // register llc_mem_server_rg_cacheline_cache_addr + reg [63 : 0] llc_mem_server_rg_cacheline_cache_addr; + wire [63 : 0] llc_mem_server_rg_cacheline_cache_addr$D_IN; + wire llc_mem_server_rg_cacheline_cache_addr$EN; + + // register llc_mem_server_rg_cacheline_cache_data + reg [515 : 0] llc_mem_server_rg_cacheline_cache_data; + wire [515 : 0] llc_mem_server_rg_cacheline_cache_data$D_IN; + wire llc_mem_server_rg_cacheline_cache_data$EN; + + // register llc_mem_server_rg_cacheline_cache_dirty_delay + reg [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay; + wire [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN; + wire llc_mem_server_rg_cacheline_cache_dirty_delay$EN; + + // register llc_mem_server_rg_cacheline_cache_state + reg [2 : 0] llc_mem_server_rg_cacheline_cache_state; + reg [2 : 0] llc_mem_server_rg_cacheline_cache_state$D_IN; + wire llc_mem_server_rg_cacheline_cache_state$EN; // register mmioPlatform_amoResp - reg [63 : 0] mmioPlatform_amoResp; - wire [63 : 0] mmioPlatform_amoResp$D_IN; + reg [128 : 0] mmioPlatform_amoResp; + wire [128 : 0] mmioPlatform_amoResp$D_IN; wire mmioPlatform_amoResp$EN; // register mmioPlatform_curReq @@ -975,8 +1344,9 @@ module mkProc(CLK, wire mmioPlatform_fromHostQ_full$D_IN, mmioPlatform_fromHostQ_full$EN; // register mmioPlatform_instSel - reg mmioPlatform_instSel; - wire mmioPlatform_instSel$D_IN, mmioPlatform_instSel$EN; + reg [1 : 0] mmioPlatform_instSel; + wire [1 : 0] mmioPlatform_instSel$D_IN; + wire mmioPlatform_instSel$EN; // register mmioPlatform_mtime reg [63 : 0] mmioPlatform_mtime; @@ -998,13 +1368,13 @@ module mkProc(CLK, wire mmioPlatform_reqAmofunc$EN; // register mmioPlatform_reqBE - reg [7 : 0] mmioPlatform_reqBE; - wire [7 : 0] mmioPlatform_reqBE$D_IN; + reg [15 : 0] mmioPlatform_reqBE; + wire [15 : 0] mmioPlatform_reqBE$D_IN; wire mmioPlatform_reqBE$EN; // register mmioPlatform_reqData - reg [63 : 0] mmioPlatform_reqData; - wire [63 : 0] mmioPlatform_reqData$D_IN; + reg [128 : 0] mmioPlatform_reqData; + wire [128 : 0] mmioPlatform_reqData$D_IN; wire mmioPlatform_reqData$EN; // register mmioPlatform_reqFunc @@ -1076,74 +1446,54 @@ module mkProc(CLK, wire [3 : 0] mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN; wire mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN; - // register mmio_axi4_adapter_master_xactor_crg_rd_addr_full - reg mmio_axi4_adapter_master_xactor_crg_rd_addr_full; - wire mmio_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN, - mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN; + // register mmio_axi4_adapter_master_xactor_clearing + reg mmio_axi4_adapter_master_xactor_clearing; + wire mmio_axi4_adapter_master_xactor_clearing$D_IN, + mmio_axi4_adapter_master_xactor_clearing$EN; - // register mmio_axi4_adapter_master_xactor_crg_rd_data_full - reg mmio_axi4_adapter_master_xactor_crg_rd_data_full; - wire mmio_axi4_adapter_master_xactor_crg_rd_data_full$D_IN, - mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN; + // register mmio_axi4_adapter_master_xactor_shim_arff_rv + reg [97 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rv; + wire [97 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN; + wire mmio_axi4_adapter_master_xactor_shim_arff_rv$EN; - // register mmio_axi4_adapter_master_xactor_crg_wr_addr_full - reg mmio_axi4_adapter_master_xactor_crg_wr_addr_full; - wire mmio_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN, - mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN; + // register mmio_axi4_adapter_master_xactor_shim_awff_rv + reg [97 : 0] mmio_axi4_adapter_master_xactor_shim_awff_rv; + wire [97 : 0] mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN; + wire mmio_axi4_adapter_master_xactor_shim_awff_rv$EN; - // register mmio_axi4_adapter_master_xactor_crg_wr_data_full - reg mmio_axi4_adapter_master_xactor_crg_wr_data_full; - wire mmio_axi4_adapter_master_xactor_crg_wr_data_full$D_IN, - mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN; + // register mmio_axi4_adapter_master_xactor_shim_bff_rv + reg [6 : 0] mmio_axi4_adapter_master_xactor_shim_bff_rv; + wire [6 : 0] mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN; + wire mmio_axi4_adapter_master_xactor_shim_bff_rv$EN; - // register mmio_axi4_adapter_master_xactor_crg_wr_resp_full - reg mmio_axi4_adapter_master_xactor_crg_wr_resp_full; - wire mmio_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN, - mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN; + // register mmio_axi4_adapter_master_xactor_shim_rff_rv + reg [72 : 0] mmio_axi4_adapter_master_xactor_shim_rff_rv; + wire [72 : 0] mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN; + wire mmio_axi4_adapter_master_xactor_shim_rff_rv$EN; - // register mmio_axi4_adapter_master_xactor_rg_rd_addr - reg [96 : 0] mmio_axi4_adapter_master_xactor_rg_rd_addr; - wire [96 : 0] mmio_axi4_adapter_master_xactor_rg_rd_addr$D_IN; - wire mmio_axi4_adapter_master_xactor_rg_rd_addr$EN; + // register mmio_axi4_adapter_master_xactor_shim_wff_rv + reg [74 : 0] mmio_axi4_adapter_master_xactor_shim_wff_rv; + wire [74 : 0] mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN; + wire mmio_axi4_adapter_master_xactor_shim_wff_rv$EN; - // register mmio_axi4_adapter_master_xactor_rg_rd_data - reg [70 : 0] mmio_axi4_adapter_master_xactor_rg_rd_data; - wire [70 : 0] mmio_axi4_adapter_master_xactor_rg_rd_data$D_IN; - wire mmio_axi4_adapter_master_xactor_rg_rd_data$EN; - - // register mmio_axi4_adapter_master_xactor_rg_wr_addr - reg [96 : 0] mmio_axi4_adapter_master_xactor_rg_wr_addr; - wire [96 : 0] mmio_axi4_adapter_master_xactor_rg_wr_addr$D_IN; - wire mmio_axi4_adapter_master_xactor_rg_wr_addr$EN; - - // register mmio_axi4_adapter_master_xactor_rg_wr_data - reg [76 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data; - wire [76 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN; - wire mmio_axi4_adapter_master_xactor_rg_wr_data$EN; - - // register mmio_axi4_adapter_master_xactor_rg_wr_resp - reg [5 : 0] mmio_axi4_adapter_master_xactor_rg_wr_resp; - wire [5 : 0] mmio_axi4_adapter_master_xactor_rg_wr_resp$D_IN; - wire mmio_axi4_adapter_master_xactor_rg_wr_resp$EN; + // register mmio_axi4_adapter_read_req_addr + reg [63 : 0] mmio_axi4_adapter_read_req_addr; + wire [63 : 0] mmio_axi4_adapter_read_req_addr$D_IN; + wire mmio_axi4_adapter_read_req_addr$EN; // register propDstData_0_rl reg [72 : 0] propDstData_0_rl; wire [72 : 0] propDstData_0_rl$D_IN; wire propDstData_0_rl$EN; - // register propDstData_0_rl_1 - reg [64 : 0] propDstData_0_rl_1; - wire [64 : 0] propDstData_0_rl_1$D_IN; - wire propDstData_0_rl_1$EN; - // register propDstData_1_0_rl - reg [579 : 0] propDstData_1_0_rl; - wire [579 : 0] propDstData_1_0_rl$D_IN; + reg [583 : 0] propDstData_1_0_rl; + wire [583 : 0] propDstData_1_0_rl$D_IN; wire propDstData_1_0_rl$EN; // register propDstData_1_1_rl - reg [579 : 0] propDstData_1_1_rl; - wire [579 : 0] propDstData_1_1_rl$D_IN; + reg [583 : 0] propDstData_1_1_rl; + wire [583 : 0] propDstData_1_1_rl$D_IN; wire propDstData_1_1_rl$EN; // register propDstData_1_rl @@ -1155,10 +1505,6 @@ module mkProc(CLK, reg propDstIdx_0_rl; wire propDstIdx_0_rl$D_IN, propDstIdx_0_rl$EN; - // register propDstIdx_0_rl_1 - reg propDstIdx_0_rl_1; - wire propDstIdx_0_rl_1$D_IN, propDstIdx_0_rl_1$EN; - // register propDstIdx_1_0_rl reg propDstIdx_1_0_rl; wire propDstIdx_1_0_rl$D_IN, propDstIdx_1_0_rl$EN; @@ -1180,16 +1526,23 @@ module mkProc(CLK, wire srcRR_1_0$D_IN, srcRR_1_0$EN; // ports of submodule core_0 - reg [66 : 0] core_0$mmioToPlatform_pRs_enq_x; + reg [130 : 0] core_0$mmioToPlatform_pRs_enq_x; reg [38 : 0] core_0$mmioToPlatform_pRq_enq_x; - wire [582 : 0] core_0$dCacheToParent_fromP_enq_x, + wire [586 : 0] core_0$dCacheToParent_fromP_enq_x, core_0$iCacheToParent_fromP_enq_x; - wire [578 : 0] core_0$dCacheToParent_rsToP_first, + wire [582 : 0] core_0$dCacheToParent_rsToP_first, core_0$iCacheToParent_rsToP_first; - wire [141 : 0] core_0$mmioToPlatform_cRq_first; + wire [214 : 0] core_0$mmioToPlatform_cRq_first; + wire [76 : 0] core_0$hart0_csr_mem_server_request_put; wire [71 : 0] core_0$dCacheToParent_rqToP_first, core_0$iCacheToParent_rqToP_first; - wire [64 : 0] core_0$tlbToMem_memReq_first, core_0$tlbToMem_respLd_enq_x; + wire [69 : 0] core_0$hart0_fpr_mem_server_request_put, + core_0$hart0_gpr_mem_server_request_put; + wire [64 : 0] core_0$hart0_csr_mem_server_response_get, + core_0$hart0_fpr_mem_server_response_get, + core_0$hart0_gpr_mem_server_response_get, + core_0$tlbToMem_memReq_first, + core_0$tlbToMem_respLd_enq_x; wire [63 : 0] core_0$coreReq_start_fromHostAddr, core_0$coreReq_start_startpc, core_0$coreReq_start_toHostAddr, @@ -1212,6 +1565,14 @@ module mkProc(CLK, core_0$EN_deadlock_iCachePRqStuck_get, core_0$EN_deadlock_renameCorrectPathStuck_get, core_0$EN_deadlock_renameInstStuck_get, + core_0$EN_hart0_csr_mem_server_request_put, + core_0$EN_hart0_csr_mem_server_response_get, + core_0$EN_hart0_fpr_mem_server_request_put, + core_0$EN_hart0_fpr_mem_server_response_get, + core_0$EN_hart0_gpr_mem_server_request_put, + core_0$EN_hart0_gpr_mem_server_response_get, + core_0$EN_hart0_run_halt_server_request_put, + core_0$EN_hart0_run_halt_server_response_get, core_0$EN_iCacheToParent_fromP_enq, core_0$EN_iCacheToParent_rqToP_deq, core_0$EN_iCacheToParent_rsToP_deq, @@ -1223,7 +1584,6 @@ module mkProc(CLK, core_0$EN_recvDoStats, core_0$EN_renameDebug_renameErr_get, core_0$EN_sendDoStats, - core_0$EN_setDEIP, core_0$EN_setMEIP, core_0$EN_setSEIP, core_0$EN_tlbToMem_memReq_deq, @@ -1243,6 +1603,14 @@ module mkProc(CLK, core_0$RDY_deadlock_iCachePRqStuck_get, core_0$RDY_deadlock_renameCorrectPathStuck_get, core_0$RDY_deadlock_renameInstStuck_get, + core_0$RDY_hart0_csr_mem_server_request_put, + core_0$RDY_hart0_csr_mem_server_response_get, + core_0$RDY_hart0_fpr_mem_server_request_put, + core_0$RDY_hart0_fpr_mem_server_response_get, + core_0$RDY_hart0_gpr_mem_server_request_put, + core_0$RDY_hart0_gpr_mem_server_response_get, + core_0$RDY_hart0_run_halt_server_request_put, + core_0$RDY_hart0_run_halt_server_response_get, core_0$RDY_iCacheToParent_fromP_enq, core_0$RDY_iCacheToParent_rqToP_deq, core_0$RDY_iCacheToParent_rqToP_first, @@ -1259,67 +1627,21 @@ module mkProc(CLK, core_0$RDY_tlbToMem_memReq_deq, core_0$RDY_tlbToMem_memReq_first, core_0$RDY_tlbToMem_respLd_enq, + core_0$hart0_run_halt_server_request_put, + core_0$hart0_run_halt_server_response_get, core_0$mmioToPlatform_cRq_notEmpty, core_0$mmioToPlatform_cRs_first, core_0$recvDoStats_x, core_0$sendDoStats, - core_0$setDEIP_v, core_0$setMEIP_v, core_0$setSEIP_v; - // ports of submodule enqDst_0_dummy2_0 - wire enqDst_0_dummy2_0$D_IN, enqDst_0_dummy2_0$EN, enqDst_0_dummy2_0$Q_OUT; - - // ports of submodule enqDst_0_dummy2_0_1 - wire enqDst_0_dummy2_0_1$D_IN, - enqDst_0_dummy2_0_1$EN, - enqDst_0_dummy2_0_1$Q_OUT; - - // ports of submodule enqDst_0_dummy2_1 - wire enqDst_0_dummy2_1$D_IN, enqDst_0_dummy2_1$EN, enqDst_0_dummy2_1$Q_OUT; - - // ports of submodule enqDst_0_dummy2_1_1 - wire enqDst_0_dummy2_1_1$D_IN, - enqDst_0_dummy2_1_1$EN, - enqDst_0_dummy2_1_1$Q_OUT; - - // ports of submodule enqDst_1_0_dummy2_0 - wire enqDst_1_0_dummy2_0$D_IN, - enqDst_1_0_dummy2_0$EN, - enqDst_1_0_dummy2_0$Q_OUT; - - // ports of submodule enqDst_1_0_dummy2_1 - wire enqDst_1_0_dummy2_1$D_IN, - enqDst_1_0_dummy2_1$EN, - enqDst_1_0_dummy2_1$Q_OUT; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_trace_data - wire [361 : 0] f_trace_data$D_IN, f_trace_data$D_OUT; - wire f_trace_data$CLR, - f_trace_data$DEQ, - f_trace_data$EMPTY_N, - f_trace_data$ENQ; - // ports of submodule llc - wire [644 : 0] llc$dma_memReq_enq_x; - wire [640 : 0] llc$to_mem_toM_first; - wire [583 : 0] llc$to_child_toC_first; - wire [579 : 0] llc$to_child_rsFromC_enq_x; - wire [516 : 0] llc$dma_respLd_first, llc$to_mem_rsFromM_enq_x; + reg [648 : 0] llc$dma_memReq_enq_x; + wire [644 : 0] llc$to_mem_toM_first; + wire [587 : 0] llc$to_child_toC_first; + wire [583 : 0] llc$to_child_rsFromC_enq_x; + wire [520 : 0] llc$dma_respLd_first, llc$to_mem_rsFromM_enq_x; wire [72 : 0] llc$to_child_rqFromC_enq_x; wire [4 : 0] llc$dma_respSt_first; wire [3 : 0] llc$perf_req_r; @@ -1358,87 +1680,23 @@ module mkProc(CLK, llc_axi4_adapter_f_pending_reads$ENQ, llc_axi4_adapter_f_pending_reads$FULL_N; - // ports of submodule llc_axi4_adapter_f_pending_writes - wire [639 : 0] llc_axi4_adapter_f_pending_writes$D_IN; - wire llc_axi4_adapter_f_pending_writes$CLR, - llc_axi4_adapter_f_pending_writes$DEQ, - llc_axi4_adapter_f_pending_writes$EMPTY_N, - llc_axi4_adapter_f_pending_writes$ENQ, - llc_axi4_adapter_f_pending_writes$FULL_N; + // ports of submodule llc_mem_server_f_dword_in_line + wire [2 : 0] llc_mem_server_f_dword_in_line$D_IN; + wire llc_mem_server_f_dword_in_line$CLR, + llc_mem_server_f_dword_in_line$DEQ, + llc_mem_server_f_dword_in_line$ENQ; - // ports of submodule mmioPlatform_fromHostQ_clearReq_dummy2_0 - wire mmioPlatform_fromHostQ_clearReq_dummy2_0$D_IN, - mmioPlatform_fromHostQ_clearReq_dummy2_0$EN; - - // ports of submodule mmioPlatform_fromHostQ_clearReq_dummy2_1 - wire mmioPlatform_fromHostQ_clearReq_dummy2_1$D_IN, - mmioPlatform_fromHostQ_clearReq_dummy2_1$EN, - mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule mmioPlatform_fromHostQ_deqReq_dummy2_0 - wire mmioPlatform_fromHostQ_deqReq_dummy2_0$D_IN, - mmioPlatform_fromHostQ_deqReq_dummy2_0$EN; - - // ports of submodule mmioPlatform_fromHostQ_deqReq_dummy2_1 - wire mmioPlatform_fromHostQ_deqReq_dummy2_1$D_IN, - mmioPlatform_fromHostQ_deqReq_dummy2_1$EN; - - // ports of submodule mmioPlatform_fromHostQ_deqReq_dummy2_2 - wire mmioPlatform_fromHostQ_deqReq_dummy2_2$D_IN, - mmioPlatform_fromHostQ_deqReq_dummy2_2$EN, - mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule mmioPlatform_fromHostQ_enqReq_dummy2_0 - wire mmioPlatform_fromHostQ_enqReq_dummy2_0$D_IN, - mmioPlatform_fromHostQ_enqReq_dummy2_0$EN; - - // ports of submodule mmioPlatform_fromHostQ_enqReq_dummy2_1 - wire mmioPlatform_fromHostQ_enqReq_dummy2_1$D_IN, - mmioPlatform_fromHostQ_enqReq_dummy2_1$EN; - - // ports of submodule mmioPlatform_fromHostQ_enqReq_dummy2_2 - wire mmioPlatform_fromHostQ_enqReq_dummy2_2$D_IN, - mmioPlatform_fromHostQ_enqReq_dummy2_2$EN, - mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT; - - // ports of submodule mmioPlatform_toHostQ_clearReq_dummy2_0 - wire mmioPlatform_toHostQ_clearReq_dummy2_0$D_IN, - mmioPlatform_toHostQ_clearReq_dummy2_0$EN; - - // ports of submodule mmioPlatform_toHostQ_clearReq_dummy2_1 - wire mmioPlatform_toHostQ_clearReq_dummy2_1$D_IN, - mmioPlatform_toHostQ_clearReq_dummy2_1$EN, - mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT; - - // ports of submodule mmioPlatform_toHostQ_deqReq_dummy2_0 - wire mmioPlatform_toHostQ_deqReq_dummy2_0$D_IN, - mmioPlatform_toHostQ_deqReq_dummy2_0$EN; - - // ports of submodule mmioPlatform_toHostQ_deqReq_dummy2_1 - wire mmioPlatform_toHostQ_deqReq_dummy2_1$D_IN, - mmioPlatform_toHostQ_deqReq_dummy2_1$EN; - - // ports of submodule mmioPlatform_toHostQ_deqReq_dummy2_2 - wire mmioPlatform_toHostQ_deqReq_dummy2_2$D_IN, - mmioPlatform_toHostQ_deqReq_dummy2_2$EN, - mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT; - - // ports of submodule mmioPlatform_toHostQ_enqReq_dummy2_0 - wire mmioPlatform_toHostQ_enqReq_dummy2_0$D_IN, - mmioPlatform_toHostQ_enqReq_dummy2_0$EN; - - // ports of submodule mmioPlatform_toHostQ_enqReq_dummy2_1 - wire mmioPlatform_toHostQ_enqReq_dummy2_1$D_IN, - mmioPlatform_toHostQ_enqReq_dummy2_1$EN; - - // ports of submodule mmioPlatform_toHostQ_enqReq_dummy2_2 - wire mmioPlatform_toHostQ_enqReq_dummy2_2$D_IN, - mmioPlatform_toHostQ_enqReq_dummy2_2$EN, - mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT; + // ports of submodule llc_mem_server_tlbQ + wire [64 : 0] llc_mem_server_tlbQ$D_IN, llc_mem_server_tlbQ$D_OUT; + wire llc_mem_server_tlbQ$CLR, + llc_mem_server_tlbQ$DEQ, + llc_mem_server_tlbQ$EMPTY_N, + llc_mem_server_tlbQ$ENQ, + llc_mem_server_tlbQ$FULL_N; // ports of submodule mmio_axi4_adapter_f_reqs_from_core - reg [141 : 0] mmio_axi4_adapter_f_reqs_from_core$D_IN; - wire [141 : 0] mmio_axi4_adapter_f_reqs_from_core$D_OUT; + reg [214 : 0] mmio_axi4_adapter_f_reqs_from_core$D_IN; + wire [214 : 0] mmio_axi4_adapter_f_reqs_from_core$D_OUT; wire mmio_axi4_adapter_f_reqs_from_core$CLR, mmio_axi4_adapter_f_reqs_from_core$DEQ, mmio_axi4_adapter_f_reqs_from_core$EMPTY_N, @@ -1446,123 +1704,78 @@ module mkProc(CLK, mmio_axi4_adapter_f_reqs_from_core$FULL_N; // ports of submodule mmio_axi4_adapter_f_rsps_to_core - wire [64 : 0] mmio_axi4_adapter_f_rsps_to_core$D_IN, - mmio_axi4_adapter_f_rsps_to_core$D_OUT; + reg [129 : 0] mmio_axi4_adapter_f_rsps_to_core$D_IN; + wire [129 : 0] mmio_axi4_adapter_f_rsps_to_core$D_OUT; wire mmio_axi4_adapter_f_rsps_to_core$CLR, mmio_axi4_adapter_f_rsps_to_core$DEQ, mmio_axi4_adapter_f_rsps_to_core$EMPTY_N, mmio_axi4_adapter_f_rsps_to_core$ENQ, mmio_axi4_adapter_f_rsps_to_core$FULL_N; - // ports of submodule propDstData_0_dummy2_0 - wire propDstData_0_dummy2_0$D_IN, propDstData_0_dummy2_0$EN; - - // ports of submodule propDstData_0_dummy2_0_1 - wire propDstData_0_dummy2_0_1$D_IN, propDstData_0_dummy2_0_1$EN; - - // ports of submodule propDstData_0_dummy2_1 - wire propDstData_0_dummy2_1$D_IN, - propDstData_0_dummy2_1$EN, - propDstData_0_dummy2_1$Q_OUT; - - // ports of submodule propDstData_0_dummy2_1_1 - wire propDstData_0_dummy2_1_1$D_IN, - propDstData_0_dummy2_1_1$EN, - propDstData_0_dummy2_1_1$Q_OUT; - - // ports of submodule propDstData_1_0_dummy2_0 - wire propDstData_1_0_dummy2_0$D_IN, propDstData_1_0_dummy2_0$EN; - - // ports of submodule propDstData_1_0_dummy2_1 - wire propDstData_1_0_dummy2_1$D_IN, - propDstData_1_0_dummy2_1$EN, - propDstData_1_0_dummy2_1$Q_OUT; - - // ports of submodule propDstData_1_1_dummy2_0 - wire propDstData_1_1_dummy2_0$D_IN, propDstData_1_1_dummy2_0$EN; - - // ports of submodule propDstData_1_1_dummy2_1 - wire propDstData_1_1_dummy2_1$D_IN, - propDstData_1_1_dummy2_1$EN, - propDstData_1_1_dummy2_1$Q_OUT; - - // ports of submodule propDstData_1_dummy2_0 - wire propDstData_1_dummy2_0$D_IN, propDstData_1_dummy2_0$EN; - - // ports of submodule propDstData_1_dummy2_1 - wire propDstData_1_dummy2_1$D_IN, - propDstData_1_dummy2_1$EN, - propDstData_1_dummy2_1$Q_OUT; - - // ports of submodule propDstIdx_0_dummy2_0 - wire propDstIdx_0_dummy2_0$D_IN, - propDstIdx_0_dummy2_0$EN, - propDstIdx_0_dummy2_0$Q_OUT; - - // ports of submodule propDstIdx_0_dummy2_0_1 - wire propDstIdx_0_dummy2_0_1$D_IN, - propDstIdx_0_dummy2_0_1$EN, - propDstIdx_0_dummy2_0_1$Q_OUT; - - // ports of submodule propDstIdx_0_dummy2_1 - wire propDstIdx_0_dummy2_1$D_IN, - propDstIdx_0_dummy2_1$EN, - propDstIdx_0_dummy2_1$Q_OUT; - - // ports of submodule propDstIdx_0_dummy2_1_1 - wire propDstIdx_0_dummy2_1_1$D_IN, - propDstIdx_0_dummy2_1_1$EN, - propDstIdx_0_dummy2_1_1$Q_OUT; - - // ports of submodule propDstIdx_1_0_dummy2_0 - wire propDstIdx_1_0_dummy2_0$D_IN, - propDstIdx_1_0_dummy2_0$EN, - propDstIdx_1_0_dummy2_0$Q_OUT; - - // ports of submodule propDstIdx_1_0_dummy2_1 - wire propDstIdx_1_0_dummy2_1$D_IN, - propDstIdx_1_0_dummy2_1$EN, - propDstIdx_1_0_dummy2_1$Q_OUT; - - // ports of submodule propDstIdx_1_1_dummy2_0 - wire propDstIdx_1_1_dummy2_0$D_IN, - propDstIdx_1_1_dummy2_0$EN, - propDstIdx_1_1_dummy2_0$Q_OUT; - - // ports of submodule propDstIdx_1_1_dummy2_1 - wire propDstIdx_1_1_dummy2_1$D_IN, - propDstIdx_1_1_dummy2_1$EN, - propDstIdx_1_1_dummy2_1$Q_OUT; - - // ports of submodule propDstIdx_1_dummy2_0 - wire propDstIdx_1_dummy2_0$D_IN, - propDstIdx_1_dummy2_0$EN, - propDstIdx_1_dummy2_0$Q_OUT; - - // ports of submodule propDstIdx_1_dummy2_1 - wire propDstIdx_1_dummy2_1$D_IN, - propDstIdx_1_dummy2_1$EN, - propDstIdx_1_dummy2_1$Q_OUT; - - // ports of submodule tlbQ - wire [64 : 0] tlbQ$D_IN, tlbQ$D_OUT; - wire tlbQ$CLR, tlbQ$DEQ, tlbQ$EMPTY_N, tlbQ$ENQ, tlbQ$FULL_N; + // ports of submodule mmio_axi4_adapter_soc_map + wire [63 : 0] mmio_axi4_adapter_soc_map$m_is_IO_addr_addr, + mmio_axi4_adapter_soc_map$m_is_mem_addr_addr, + mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr; + wire mmio_axi4_adapter_soc_map$m_is_IO_addr; // rule scheduling signals wire CAN_FIRE_RL_broadcastStats, CAN_FIRE_RL_doEnq, CAN_FIRE_RL_doEnq_1, - CAN_FIRE_RL_doEnq_2, CAN_FIRE_RL_dstSelectSrc, CAN_FIRE_RL_dstSelectSrc_1, - CAN_FIRE_RL_dstSelectSrc_2, CAN_FIRE_RL_enqDst_0_canon, - CAN_FIRE_RL_enqDst_0_canon_1, CAN_FIRE_RL_enqDst_1_0_canon, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut, + CAN_FIRE_RL_llc_mem_server_doEnq, + CAN_FIRE_RL_llc_mem_server_dstSelectSrc, + CAN_FIRE_RL_llc_mem_server_enqDst_0_canon, + CAN_FIRE_RL_llc_mem_server_propDstData_0_canon, + CAN_FIRE_RL_llc_mem_server_propDstIdx_0_canon, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss, + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req, + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req, + CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb, + CAN_FIRE_RL_llc_mem_server_sendStRespToTlb, + CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC, + CAN_FIRE_RL_llc_mem_server_srcPropose, CAN_FIRE_RL_mmioPlatform_fromHostQ_canonicalize, CAN_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon, CAN_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon, @@ -1590,18 +1803,30 @@ module mkProc(CLK, CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone, CAN_FIRE_RL_mmioPlatform_waitMTimeDone, CAN_FIRE_RL_mmioPlatform_waitTimerInterruptDone, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek, + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp, CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St, CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req, CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps, CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req, CAN_FIRE_RL_propDstData_0_canon, - CAN_FIRE_RL_propDstData_0_canon_1, CAN_FIRE_RL_propDstData_1_0_canon, CAN_FIRE_RL_propDstData_1_1_canon, CAN_FIRE_RL_propDstData_1_canon, CAN_FIRE_RL_propDstIdx_0_canon, - CAN_FIRE_RL_propDstIdx_0_canon_1, CAN_FIRE_RL_propDstIdx_1_0_canon, CAN_FIRE_RL_propDstIdx_1_1_canon, CAN_FIRE_RL_propDstIdx_1_canon, @@ -1615,24 +1840,21 @@ module mkProc(CLK, CAN_FIRE_RL_rl_dummy7, CAN_FIRE_RL_rl_dummy8, CAN_FIRE_RL_rl_dummy9, - CAN_FIRE_RL_rl_reset, CAN_FIRE_RL_rl_terminate, CAN_FIRE_RL_rl_tohost, - CAN_FIRE_RL_sendLdRespToMemLoader, - CAN_FIRE_RL_sendLdRespToTlb, CAN_FIRE_RL_sendPRq, CAN_FIRE_RL_sendPRq_1, CAN_FIRE_RL_sendPRs, CAN_FIRE_RL_sendPRs_1, - CAN_FIRE_RL_sendStRespToMemLoader, - CAN_FIRE_RL_sendStRespToTlb, - CAN_FIRE_RL_sendTlbReqToLLC, CAN_FIRE_RL_srcPropose, CAN_FIRE_RL_srcPropose_1, CAN_FIRE_RL_srcPropose_2, CAN_FIRE_RL_srcPropose_3, - CAN_FIRE_RL_srcPropose_4, - CAN_FIRE_debug_external_interrupt_req, + CAN_FIRE_debug_module_mem_server_ar_arflit, + CAN_FIRE_debug_module_mem_server_aw_awflit, + CAN_FIRE_debug_module_mem_server_b_bready, + CAN_FIRE_debug_module_mem_server_r_rready, + CAN_FIRE_debug_module_mem_server_w_wflit, CAN_FIRE_hart0_csr_mem_server_request_put, CAN_FIRE_hart0_csr_mem_server_response_get, CAN_FIRE_hart0_fpr_mem_server_request_put, @@ -1640,40 +1862,80 @@ module mkProc(CLK, CAN_FIRE_hart0_gpr_mem_server_request_put, CAN_FIRE_hart0_gpr_mem_server_response_get, CAN_FIRE_hart0_put_other_req_put, - CAN_FIRE_hart0_server_reset_request_put, - CAN_FIRE_hart0_server_reset_response_get, - CAN_FIRE_hart0_server_run_halt_request_put, - CAN_FIRE_hart0_server_run_halt_response_get, + CAN_FIRE_hart0_run_halt_server_request_put, + CAN_FIRE_hart0_run_halt_server_response_get, CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_master0_m_arready, - CAN_FIRE_master0_m_awready, - CAN_FIRE_master0_m_bvalid, - CAN_FIRE_master0_m_rvalid, - CAN_FIRE_master0_m_wready, - CAN_FIRE_master1_m_arready, - CAN_FIRE_master1_m_awready, - CAN_FIRE_master1_m_bvalid, - CAN_FIRE_master1_m_rvalid, - CAN_FIRE_master1_m_wready, + CAN_FIRE_master0_ar_arready, + CAN_FIRE_master0_aw_awready, + CAN_FIRE_master0_b_bflit, + CAN_FIRE_master0_r_rflit, + CAN_FIRE_master0_w_wready, + CAN_FIRE_master1_ar_arready, + CAN_FIRE_master1_aw_awready, + CAN_FIRE_master1_b_bflit, + CAN_FIRE_master1_r_rflit, + CAN_FIRE_master1_w_wready, CAN_FIRE_non_maskable_interrupt_req, CAN_FIRE_s_external_interrupt_req, CAN_FIRE_set_verbosity, CAN_FIRE_start, - CAN_FIRE_trace_data_out_get, WILL_FIRE_RL_broadcastStats, WILL_FIRE_RL_doEnq, WILL_FIRE_RL_doEnq_1, - WILL_FIRE_RL_doEnq_2, WILL_FIRE_RL_dstSelectSrc, WILL_FIRE_RL_dstSelectSrc_1, - WILL_FIRE_RL_dstSelectSrc_2, WILL_FIRE_RL_enqDst_0_canon, - WILL_FIRE_RL_enqDst_0_canon_1, WILL_FIRE_RL_enqDst_1_0_canon, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut, + WILL_FIRE_RL_llc_mem_server_doEnq, + WILL_FIRE_RL_llc_mem_server_dstSelectSrc, + WILL_FIRE_RL_llc_mem_server_enqDst_0_canon, + WILL_FIRE_RL_llc_mem_server_propDstData_0_canon, + WILL_FIRE_RL_llc_mem_server_propDstIdx_0_canon, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss, + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req, + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req, + WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb, + WILL_FIRE_RL_llc_mem_server_sendStRespToTlb, + WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC, + WILL_FIRE_RL_llc_mem_server_srcPropose, WILL_FIRE_RL_mmioPlatform_fromHostQ_canonicalize, WILL_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon, WILL_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon, @@ -1701,18 +1963,30 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone, WILL_FIRE_RL_mmioPlatform_waitMTimeDone, WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek, + WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req, WILL_FIRE_RL_propDstData_0_canon, - WILL_FIRE_RL_propDstData_0_canon_1, WILL_FIRE_RL_propDstData_1_0_canon, WILL_FIRE_RL_propDstData_1_1_canon, WILL_FIRE_RL_propDstData_1_canon, WILL_FIRE_RL_propDstIdx_0_canon, - WILL_FIRE_RL_propDstIdx_0_canon_1, WILL_FIRE_RL_propDstIdx_1_0_canon, WILL_FIRE_RL_propDstIdx_1_1_canon, WILL_FIRE_RL_propDstIdx_1_canon, @@ -1726,24 +2000,21 @@ module mkProc(CLK, WILL_FIRE_RL_rl_dummy7, WILL_FIRE_RL_rl_dummy8, WILL_FIRE_RL_rl_dummy9, - WILL_FIRE_RL_rl_reset, WILL_FIRE_RL_rl_terminate, WILL_FIRE_RL_rl_tohost, - WILL_FIRE_RL_sendLdRespToMemLoader, - WILL_FIRE_RL_sendLdRespToTlb, WILL_FIRE_RL_sendPRq, WILL_FIRE_RL_sendPRq_1, WILL_FIRE_RL_sendPRs, WILL_FIRE_RL_sendPRs_1, - WILL_FIRE_RL_sendStRespToMemLoader, - WILL_FIRE_RL_sendStRespToTlb, - WILL_FIRE_RL_sendTlbReqToLLC, WILL_FIRE_RL_srcPropose, WILL_FIRE_RL_srcPropose_1, WILL_FIRE_RL_srcPropose_2, WILL_FIRE_RL_srcPropose_3, - WILL_FIRE_RL_srcPropose_4, - WILL_FIRE_debug_external_interrupt_req, + WILL_FIRE_debug_module_mem_server_ar_arflit, + WILL_FIRE_debug_module_mem_server_aw_awflit, + WILL_FIRE_debug_module_mem_server_b_bready, + WILL_FIRE_debug_module_mem_server_r_rready, + WILL_FIRE_debug_module_mem_server_w_wflit, WILL_FIRE_hart0_csr_mem_server_request_put, WILL_FIRE_hart0_csr_mem_server_response_get, WILL_FIRE_hart0_fpr_mem_server_request_put, @@ -1751,57 +2022,62 @@ module mkProc(CLK, WILL_FIRE_hart0_gpr_mem_server_request_put, WILL_FIRE_hart0_gpr_mem_server_response_get, WILL_FIRE_hart0_put_other_req_put, - WILL_FIRE_hart0_server_reset_request_put, - WILL_FIRE_hart0_server_reset_response_get, - WILL_FIRE_hart0_server_run_halt_request_put, - WILL_FIRE_hart0_server_run_halt_response_get, + WILL_FIRE_hart0_run_halt_server_request_put, + WILL_FIRE_hart0_run_halt_server_response_get, WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_master0_m_arready, - WILL_FIRE_master0_m_awready, - WILL_FIRE_master0_m_bvalid, - WILL_FIRE_master0_m_rvalid, - WILL_FIRE_master0_m_wready, - WILL_FIRE_master1_m_arready, - WILL_FIRE_master1_m_awready, - WILL_FIRE_master1_m_bvalid, - WILL_FIRE_master1_m_rvalid, - WILL_FIRE_master1_m_wready, + WILL_FIRE_master0_ar_arready, + WILL_FIRE_master0_aw_awready, + WILL_FIRE_master0_b_bflit, + WILL_FIRE_master0_r_rflit, + WILL_FIRE_master0_w_wready, + WILL_FIRE_master1_ar_arready, + WILL_FIRE_master1_aw_awready, + WILL_FIRE_master1_b_bflit, + WILL_FIRE_master1_r_rflit, + WILL_FIRE_master1_w_wready, WILL_FIRE_non_maskable_interrupt_req, WILL_FIRE_s_external_interrupt_req, WILL_FIRE_set_verbosity, - WILL_FIRE_start, - WILL_FIRE_trace_data_out_get; + WILL_FIRE_start; // inputs to muxes for submodule ports reg [1 : 0] MUX_mmioPlatform_state$write_1__VAL_3, MUX_mmioPlatform_state$write_1__VAL_4; - wire [582 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1, + wire [648 : 0] MUX_llc$dma_memReq_enq_1__VAL_1, + MUX_llc$dma_memReq_enq_1__VAL_2, + MUX_llc$dma_memReq_enq_1__VAL_3, + MUX_llc$dma_memReq_enq_1__VAL_4; + wire [586 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1, MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2; - wire [141 : 0] MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1, + wire [515 : 0] MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1; + wire [214 : 0] MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4; - wire [66 : 0] MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1, - MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10, - MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2, - MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3, - MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4, - MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5, - MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6, - MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7, - MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8, - MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9, - MUX_mmioPlatform_curReq$write_1__VAL_1, + wire [130 : 0] MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1, + MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10, + MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2, + MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3, + MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4, + MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5, + MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6, + MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7, + MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8, + MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9; + wire [129 : 0] MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1, + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3; + wire [128 : 0] MUX_mmioPlatform_amoResp$write_1__VAL_1, + MUX_mmioPlatform_amoResp$write_1__VAL_2; + wire [66 : 0] MUX_mmioPlatform_curReq$write_1__VAL_1, MUX_mmioPlatform_curReq$write_1__VAL_2; - wire [64 : 0] MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2; - wire [63 : 0] MUX_mmioPlatform_amoResp$write_1__VAL_1, - MUX_mmioPlatform_amoResp$write_1__VAL_2, - MUX_mmioPlatform_mtime$write_1__VAL_2; + wire [63 : 0] MUX_mmioPlatform_mtime$write_1__VAL_2; wire [38 : 0] MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2, MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3, MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4; + wire [9 : 0] MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2; wire [6 : 0] MUX_mmioPlatform_cycle$write_1__VAL_1; - wire [1 : 0] MUX_mmioPlatform_state$write_1__VAL_1, + wire [1 : 0] MUX_mmioPlatform_instSel$write_1__VAL_2, + MUX_mmioPlatform_state$write_1__VAL_1, MUX_mmioPlatform_state$write_1__VAL_2, MUX_mmioPlatform_state$write_1__VAL_5; wire MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1, @@ -1812,529 +2088,578 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4, - MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5, + MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6, + MUX_llc$dma_memReq_enq_1__SEL_1, + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2, + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3, MUX_mmioPlatform_amoResp$write_1__SEL_1, MUX_mmioPlatform_amoResp$write_1__SEL_2, MUX_mmioPlatform_curReq$write_1__SEL_1, MUX_mmioPlatform_fetchingWay$write_1__SEL_1, MUX_mmioPlatform_fetchingWay$write_1__VAL_2, - MUX_mmioPlatform_instSel$write_1__VAL_2, MUX_mmioPlatform_mtip_0$write_1__VAL_2, MUX_mmioPlatform_state$write_1__SEL_6, MUX_mmioPlatform_state$write_1__SEL_7, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1, - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1; + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1, + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1, + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h4198; - reg [31 : 0] v__h4371; - reg [31 : 0] v__h4635; - reg [31 : 0] v__h6674; - reg [31 : 0] v__h2474; - reg [31 : 0] v__h6975; - reg [31 : 0] v__h7468; - reg [31 : 0] v__h7631; - reg [31 : 0] v__h111433; - reg [31 : 0] v__h111600; - reg [31 : 0] v__h113703; - reg [31 : 0] v__h131049; - reg [31 : 0] v__h110814; - reg [31 : 0] v__h137744; - reg [31 : 0] v__h138252; - reg [31 : 0] v__h2468; - reg [31 : 0] v__h4192; - reg [31 : 0] v__h4365; - reg [31 : 0] v__h4629; - reg [31 : 0] v__h6668; - reg [31 : 0] v__h6969; - reg [31 : 0] v__h7462; - reg [31 : 0] v__h7625; - reg [31 : 0] v__h110808; - reg [31 : 0] v__h111427; - reg [31 : 0] v__h111594; - reg [31 : 0] v__h113697; - reg [31 : 0] v__h131043; - reg [31 : 0] v__h137738; - reg [31 : 0] v__h138246; + reg [31 : 0] v__h198549; + reg [31 : 0] v__h198090; + reg [31 : 0] v__h11334; + reg [31 : 0] v__h15872; + reg [31 : 0] v__h16015; + reg [31 : 0] v__h4355; + reg [31 : 0] v__h7976; + reg [31 : 0] v__h19401; + reg [31 : 0] v__h18404; + reg [31 : 0] v__h18934; + reg [31 : 0] v__h10395; + reg [31 : 0] v__h10590; + reg [31 : 0] v__h175741; + reg [31 : 0] v__h189450; + reg [31 : 0] v__h167720; + reg [31 : 0] v__h197076; + reg [31 : 0] v__h168309; + reg [31 : 0] v__h168495; + reg [31 : 0] v__h4349; + reg [31 : 0] v__h7970; + reg [31 : 0] v__h10389; + reg [31 : 0] v__h10584; + reg [31 : 0] v__h11328; + reg [31 : 0] v__h15866; + reg [31 : 0] v__h16009; + reg [31 : 0] v__h18398; + reg [31 : 0] v__h18928; + reg [31 : 0] v__h19395; + reg [31 : 0] v__h167714; + reg [31 : 0] v__h168303; + reg [31 : 0] v__h168489; + reg [31 : 0] v__h175735; + reg [31 : 0] v__h189444; + reg [31 : 0] v__h197070; + reg [31 : 0] v__h198084; + reg [31 : 0] v__h198543; // synopsys translate_on // remaining internal signals - reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5, - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6, + reg [63 : 0] CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1, + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2, + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3, + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4, + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q10, + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, - CASE_x7379_0_n__read_addr7557_1_n__read_addr76_ETC__q26, - CASE_x8756_0_n__read_addr8938_1_n__read_addr90_ETC__q15, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909, - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876, - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844, - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846, - data64__h124873, - ld_data__h108607, - w1__h45356, - w1__h45361, - w2__h45357, - w2__h45363, - x__h45352; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944; - reg [7 : 0] strb8__h124874; - reg [5 : 0] IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442; - reg [2 : 0] x__h59070; - reg [1 : 0] CASE_x7379_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, - CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14; - reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, - CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11, - CASE_x7379_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - CASE_x8756_0_propDstData_0_dummy2_1_read__057__ETC__q12, - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050, - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319, - x__h59077, - x__h79795; - wire [579 : 0] IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1270; - wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418; - wire [513 : 0] IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1269; - wire [511 : 0] IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411, - new_cline__h111736; - wire [383 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394; - wire [255 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360; - wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366; - wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645; - wire [64 : 0] IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d684; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1241, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837, - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538, - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d676, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603, - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155, - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193, - data__h29445, - failed_testnum__h139642, - mem_req_rd_addr_araddr__h111034, - mem_req_wr_addr_awaddr__h124958, - mmioPlatform_fromHostQ_data_0__h40146, - mmioPlatform_mtime__h34759, - mmioPlatform_reqData__h45948, - n__read_addr__h58938, - n__read_addr__h59023, - n__read_addr__h77557, - n__read_addr__h77636, - n__read_snd_addr__h91728, - newData__h29526, - newData__h32456, - op_result__h45964, - op_result__h46494, - op_result__h46499, - op_result__h46504, - op_result__h46509, - op_result__h46515, - op_result__h46522, - op_result__h46528, - result__h45407, - result__h45531, - result__h45559, - result__h45587, - result__h45615, - result__h45643, - result__h45671, - result__h45699, - result__h45727, - result__h45772, - result__h45800, - result__h45828, - result__h45856, - result__h45897, - result__h45925, - result__h46051, - result__h46078, - result__h46105, - result__h46132, - result__h46159, - result__h46186, - result__h46213, - result__h46240, - result__h46284, - result__h46311, - result__h46338, - result__h46365, - result__h46405, - result__h46432, - result__h46549, - result__h46615, - result__h46681, - result__h46747, - result__h46813, - result__h46879, - result__h46945, - result__h47007, - result__h47052, - result__h47118, - result__h47184, - result__h47242, - result__h47287, - w1___1__h45466, - w2___1__h45467, - x1_avValue_data__h37818, - x1_avValue_data__h42285, - x__h29637, - x__h32547, - x__h34907, - x__h38336, - x__h38347, - x__h40356, - x__h40367, - x__h47464; - wire [47 : 0] IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d671; - wire [31 : 0] IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d666, - IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d952, - mmioPlatform_mtime_BITS_31_TO_0__q4, - mmioPlatform_mtime_BITS_63_TO_32__q3, - mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2, - mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1, - v__h29238, - v__h29275, - w15356_BITS_31_TO_0__q7, - w25357_BITS_31_TO_0__q8, - x_data__h28028; - wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121; - wire [5 : 0] x__h111069, x__h124983; - wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120; - wire [3 : 0] b__h110741, b__h2368; - wire [2 : 0] n__read_id__h58942, n__read_id__h59027; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246, - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073, - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083, - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160, - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198, - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077, - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087; - wire IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520, - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417, - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515, - IF_NOT_propDstIdx_0_dummy2_1_read__019_020_OR__ETC___d1054, - IF_NOT_propDstIdx_1_0_dummy2_1_read__278_279_O_ETC___d1323, - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_ETC___d1126, - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_A_ETC___d1423, - IF_enqDst_0_lat_0_1_whas__482_THEN_enqDst_0_la_ETC___d1487, - IF_enqDst_0_lat_0_whas__95_THEN_enqDst_0_lat_0_ETC___d1000, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1231, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1251, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267, - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418, - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165, - IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461, - IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d931, - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181, - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219, - IF_propDstIdx_0_lat_0_1_whas__467_THEN_propDst_ETC___d1470, - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969, - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138, - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145, - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976, - NOT_enqDst_0_dummy2_0_1_read__513_514_OR_NOT_e_ETC___d1520, - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056, - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325, - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d707, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d720, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d730, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d921, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d934, - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283, - NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304, - NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609, - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205, - NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226, - NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338, - NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340, - NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053, - NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322, - mmioPlatform_cycle_12_ULT_99___d313, - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936, - mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296, - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577, - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322, - mmioPlatform_reqBE_BIT_0___h27653, - mmioPlatform_reqBE_BIT_4___h27613, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597, - mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218, - n__read_child__h58943, - n__read_child__h59028, - n__read_child__h77560, - n__read_child__h77639, - n__read_snd_id__h91729, - propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093, - propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097, - x__h58756, - x__h72308, - x__h77379; - - // action method hart0_server_reset_request_put - assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_hart0_server_reset_request_put = - EN_hart0_server_reset_request_put ; - - // action method hart0_server_reset_response_get - assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_hart0_server_reset_response_get = - EN_hart0_server_reset_response_get ; + CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q22, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q32, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q33, + CASE_x7352_0_IF_propDstData_1_0_lat_0_whas__26_ETC__q37, + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1053, + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1062, + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917, + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d930, + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970, + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d982, + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029, + IF_mmioPlatform_reqSz_87_EQ_0b0_88_THEN_IF_mmi_ETC___d1070, + IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d997, + IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d999, + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677, + dword__h124791, + ld_data__h162613, + v_wdata__h189758, + w1__h63698, + w1__h63703, + w2__h63699, + w2__h63705; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1099; + reg [7 : 0] v_wstrb__h189759; + reg [5 : 0] IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d587; + reg [2 : 0] x__h75450; + reg [1 : 0] CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q20, + CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q21, + CASE_x7352_0_IF_propDstData_1_0_lat_0_whas__26_ETC__q35; + reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q14, + CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q15, + CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q19, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q34, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q36, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__121_THEN_p_ETC___d1185, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__254_THEN_ETC___d1418, + v_wuser__h189761, + x__h102087, + x__h75451; + wire [583 : 0] IF_enqDst_1_0_lat_1_whas__342_THEN_enqDst_1_0__ETC___d1389; + wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1538; + wire [517 : 0] IF_enqDst_1_0_lat_1_whas__342_THEN_enqDst_1_0__ETC___d1388; + wire [515 : 0] IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1380, + IF_llc_axi4_adapter_rg_rd_rsp_beat_950_BIT_0_9_ETC___d1992, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1533; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d1725, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1515; + wire [128 : 0] amoExec___d626, + amoExec___d703, + amoExec___d765, + amoExec___d807; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1481, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1498, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1532, + _0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213; + wire [97 : 0] llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42, + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40; + wire [96 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18, + mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16; + wire [73 : 0] llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q41, + mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q17; + wire [72 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39; + wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511; + wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__80_ETC___d1811; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1360, + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d938, + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d990, + IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d686, + IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d751, + IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d661, + IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d724, + IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d828, + IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_1_ETC___d687, + IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_1_ETC___d752, + IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1274, + IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1312, + addr1__h66416, + data__h115067, + failed_testnum__h198133, + line_addr__h114500, + line_addr__h124608, + line_addr__h167856, + mmioPlatform_mtime__h46207, + newData__h37921, + newData__h42646, + op_result__h64476, + op_result__h65203, + op_result__h65208, + op_result__h65213, + op_result__h65218, + op_result__h65224, + op_result__h65231, + op_result__h65237, + result__h63749, + result__h64057, + result__h64084, + result__h64111, + result__h64138, + result__h64165, + result__h64192, + result__h64219, + result__h64246, + result__h64290, + result__h64317, + result__h64344, + result__h64371, + result__h64411, + result__h64438, + result__h64563, + result__h64787, + result__h64814, + result__h64841, + result__h64868, + result__h64895, + result__h64922, + result__h64949, + result__h64993, + result__h65020, + result__h65047, + result__h65074, + result__h65114, + result__h65141, + result__h65258, + result__h65324, + result__h65390, + result__h65456, + result__h65522, + result__h65588, + result__h65654, + result__h65716, + result__h65761, + result__h65827, + result__h65893, + result__h65951, + result__h65996, + v_awaddr__h189347, + w1___1__h63992, + w2___1__h63993, + x__h46418, + x__h51369, + x__h54059; + wire [47 : 0] IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d653, + IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d719, + IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d823; + wire [31 : 0] IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d644, + IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d714, + IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d818, + IF_mmio_axi4_adapter_f_rsps_to_core_first__69__ETC___d1106, + mmioPlatform_mtime_BITS_31_TO_0__q8, + mmioPlatform_mtime_BITS_63_TO_32__q7, + mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6, + mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5, + v__h37337, + v__h37374, + w13698_BITS_31_TO_0__q11, + w23699_BITS_31_TO_0__q12, + x_data__h35020; + wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__135_THEN__ETC___d1241; + wire [7 : 0] mmioPlatform_reqFunc_46_BITS_3_TO_0_85_CONCAT__ETC___d622; + wire [6 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q38; + wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__135_THEN__ETC___d1240; + wire [3 : 0] b__h167647, b__h4255; + wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1456, + v_awsize_val__h15184; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1365, + IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1279, + IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1317; + wire IF_IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4__ETC___d668, + IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d562, + IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663, + IF_enqDst_0_lat_0_whas__150_THEN_enqDst_0_lat__ETC___d1155, + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1350, + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1370, + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1386, + IF_llc_mem_server_enqDst_0_lat_0_whas__816_THE_ETC___d1821, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__801_ETC___d1804, + IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d735, + IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d563, + IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_2_ETC___d832, + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334, + IF_mmioPlatform_waitLowerMSIPCRs_98_THEN_core__ETC___d606, + IF_mmio_axi4_adapter_f_rsps_to_core_first__69__ETC___d1084, + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225, + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53, + IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1300, + IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1338, + IF_propDstIdx_0_lat_0_whas__121_THEN_NOT_propD_ETC___d1187, + IF_propDstIdx_0_lat_0_whas__121_THEN_propDstId_ETC___d1124, + IF_propDstIdx_1_0_lat_0_whas__254_THEN_NOT_pro_ETC___d1420, + IF_propDstIdx_1_0_lat_0_whas__254_THEN_propDst_ETC___d1257, + IF_propDstIdx_1_1_lat_0_whas__261_THEN_propDst_ETC___d1264, + IF_propDstIdx_1_lat_0_whas__128_THEN_propDstId_ETC___d1131, + NOT_enqDst_0_rl_153_BIT_73_154_159_AND_SEL_ARR_ETC___d1247, + NOT_enqDst_1_0_rl_348_BIT_584_349_354_AND_SEL__ETC___d1544, + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946, + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d2025, + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d2028, + NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d1074, + NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d1087, + NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d859, + NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d867, + NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d872, + NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d882, + NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480, + NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d596, + NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d694, + NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d758, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__121_THEN_p_ETC___d1189, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__254_THEN_ETC___d1422, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d1957, + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d1741, + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1642, + mmioPlatform_cycle_57_ULT_99___d458, + mmioPlatform_fetchingWay_079_ULT_mmioPlatform__ETC___d1089, + mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726, + mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467, + mmioPlatform_reqBE_BIT_0___h34176, + mmioPlatform_reqBE_BIT_4___h34136, + mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d573, + mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d680, + mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d746, + x__h75250, + x__h90788, + x__h97352; // action method start - assign RDY_start = CAN_FIRE_start ; + assign RDY_start = mmioPlatform_state == 2'd0 ; assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; assign WILL_FIRE_start = EN_start ; - // value method master0_m_awvalid - assign master0_awvalid = llc_axi4_adapter_master_xactor_crg_wr_addr_full ; + // value method master0_aw_awid + assign master0_awid = + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[97:93] ; - // value method master0_m_awid - assign master0_awid = llc_axi4_adapter_master_xactor_rg_wr_addr[96:93] ; + // value method master0_aw_awaddr + assign master0_awaddr = + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[92:29] ; - // value method master0_m_awaddr - assign master0_awaddr = llc_axi4_adapter_master_xactor_rg_wr_addr[92:29] ; + // value method master0_aw_awlen + assign master0_awlen = + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[28:21] ; - // value method master0_m_awlen - assign master0_awlen = llc_axi4_adapter_master_xactor_rg_wr_addr[28:21] ; + // value method master0_aw_awsize + assign master0_awsize = + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[20:18] ; - // value method master0_m_awsize - assign master0_awsize = llc_axi4_adapter_master_xactor_rg_wr_addr[20:18] ; + // value method master0_aw_awburst + assign master0_awburst = + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[17:16] ; - // value method master0_m_awburst - assign master0_awburst = llc_axi4_adapter_master_xactor_rg_wr_addr[17:16] ; + // value method master0_aw_awlock + assign master0_awlock = + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[15] ; - // value method master0_m_awlock - assign master0_awlock = llc_axi4_adapter_master_xactor_rg_wr_addr[15] ; + // value method master0_aw_awcache + assign master0_awcache = + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[14:11] ; - // value method master0_m_awcache - assign master0_awcache = llc_axi4_adapter_master_xactor_rg_wr_addr[14:11] ; + // value method master0_aw_awprot + assign master0_awprot = + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[10:8] ; - // value method master0_m_awprot - assign master0_awprot = llc_axi4_adapter_master_xactor_rg_wr_addr[10:8] ; + // value method master0_aw_awqos + assign master0_awqos = + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[7:4] ; - // value method master0_m_awqos - assign master0_awqos = llc_axi4_adapter_master_xactor_rg_wr_addr[7:4] ; + // value method master0_aw_awregion + assign master0_awregion = + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[3:0] ; - // value method master0_m_awregion - assign master0_awregion = llc_axi4_adapter_master_xactor_rg_wr_addr[3:0] ; + // value method master0_aw_awvalid + assign master0_awvalid = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; - // action method master0_m_awready - assign CAN_FIRE_master0_m_awready = 1'd1 ; - assign WILL_FIRE_master0_m_awready = 1'd1 ; + // action method master0_aw_awready + assign CAN_FIRE_master0_aw_awready = 1'd1 ; + assign WILL_FIRE_master0_aw_awready = 1'd1 ; - // value method master0_m_wvalid - assign master0_wvalid = llc_axi4_adapter_master_xactor_crg_wr_data_full ; + // value method master0_w_wdata + assign master0_wdata = + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q41[73:10] ; - // value method master0_m_wid - assign master0_wid = llc_axi4_adapter_master_xactor_rg_wr_data[76:73] ; + // value method master0_w_wstrb + assign master0_wstrb = + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q41[9:2] ; - // value method master0_m_wdata - assign master0_wdata = llc_axi4_adapter_master_xactor_rg_wr_data[72:9] ; + // value method master0_w_wlast + assign master0_wlast = + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q41[1] ; - // value method master0_m_wstrb - assign master0_wstrb = llc_axi4_adapter_master_xactor_rg_wr_data[8:1] ; + // value method master0_w_wuser + assign master0_wuser = + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q41[0] ; - // value method master0_m_wlast - assign master0_wlast = llc_axi4_adapter_master_xactor_rg_wr_data[0] ; + // value method master0_w_wvalid + assign master0_wvalid = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; - // action method master0_m_wready - assign CAN_FIRE_master0_m_wready = 1'd1 ; - assign WILL_FIRE_master0_m_wready = 1'd1 ; + // action method master0_w_wready + assign CAN_FIRE_master0_w_wready = 1'd1 ; + assign WILL_FIRE_master0_w_wready = 1'd1 ; - // action method master0_m_bvalid - assign CAN_FIRE_master0_m_bvalid = 1'd1 ; - assign WILL_FIRE_master0_m_bvalid = 1'd1 ; + // action method master0_b_bflit + assign CAN_FIRE_master0_b_bflit = 1'd1 ; + assign WILL_FIRE_master0_b_bflit = master0_bvalid ; - // value method master0_m_bready - assign master0_bready = - !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; + // value method master0_b_bready + assign master0_bready = !llc_axi4_adapter_master_xactor_shim_bff_rv[7] ; - // value method master0_m_arvalid - assign master0_arvalid = llc_axi4_adapter_master_xactor_crg_rd_addr_full ; + // value method master0_ar_arid + assign master0_arid = + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[97:93] ; - // value method master0_m_arid - assign master0_arid = llc_axi4_adapter_master_xactor_rg_rd_addr[96:93] ; + // value method master0_ar_araddr + assign master0_araddr = + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[92:29] ; - // value method master0_m_araddr - assign master0_araddr = llc_axi4_adapter_master_xactor_rg_rd_addr[92:29] ; + // value method master0_ar_arlen + assign master0_arlen = + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[28:21] ; - // value method master0_m_arlen - assign master0_arlen = llc_axi4_adapter_master_xactor_rg_rd_addr[28:21] ; + // value method master0_ar_arsize + assign master0_arsize = + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[20:18] ; - // value method master0_m_arsize - assign master0_arsize = llc_axi4_adapter_master_xactor_rg_rd_addr[20:18] ; + // value method master0_ar_arburst + assign master0_arburst = + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[17:16] ; - // value method master0_m_arburst - assign master0_arburst = llc_axi4_adapter_master_xactor_rg_rd_addr[17:16] ; + // value method master0_ar_arlock + assign master0_arlock = + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[15] ; - // value method master0_m_arlock - assign master0_arlock = llc_axi4_adapter_master_xactor_rg_rd_addr[15] ; + // value method master0_ar_arcache + assign master0_arcache = + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[14:11] ; - // value method master0_m_arcache - assign master0_arcache = llc_axi4_adapter_master_xactor_rg_rd_addr[14:11] ; + // value method master0_ar_arprot + assign master0_arprot = + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[10:8] ; - // value method master0_m_arprot - assign master0_arprot = llc_axi4_adapter_master_xactor_rg_rd_addr[10:8] ; + // value method master0_ar_arqos + assign master0_arqos = + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[7:4] ; - // value method master0_m_arqos - assign master0_arqos = llc_axi4_adapter_master_xactor_rg_rd_addr[7:4] ; + // value method master0_ar_arregion + assign master0_arregion = + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[3:0] ; - // value method master0_m_arregion - assign master0_arregion = llc_axi4_adapter_master_xactor_rg_rd_addr[3:0] ; + // value method master0_ar_arvalid + assign master0_arvalid = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; - // action method master0_m_arready - assign CAN_FIRE_master0_m_arready = 1'd1 ; - assign WILL_FIRE_master0_m_arready = 1'd1 ; + // action method master0_ar_arready + assign CAN_FIRE_master0_ar_arready = 1'd1 ; + assign WILL_FIRE_master0_ar_arready = 1'd1 ; - // action method master0_m_rvalid - assign CAN_FIRE_master0_m_rvalid = 1'd1 ; - assign WILL_FIRE_master0_m_rvalid = 1'd1 ; + // action method master0_r_rflit + assign CAN_FIRE_master0_r_rflit = 1'd1 ; + assign WILL_FIRE_master0_r_rflit = master0_rvalid ; - // value method master0_m_rready - assign master0_rready = - !llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ; + // value method master0_r_rready + assign master0_rready = !llc_axi4_adapter_master_xactor_shim_rff_rv[73] ; - // value method master1_m_awvalid - assign master1_awvalid = mmio_axi4_adapter_master_xactor_crg_wr_addr_full ; + // value method master1_aw_awid + assign master1_awid = + mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[96:93] ; - // value method master1_m_awid - assign master1_awid = mmio_axi4_adapter_master_xactor_rg_wr_addr[96:93] ; + // value method master1_aw_awaddr + assign master1_awaddr = + mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[92:29] ; - // value method master1_m_awaddr - assign master1_awaddr = mmio_axi4_adapter_master_xactor_rg_wr_addr[92:29] ; + // value method master1_aw_awlen + assign master1_awlen = + mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[28:21] ; - // value method master1_m_awlen - assign master1_awlen = mmio_axi4_adapter_master_xactor_rg_wr_addr[28:21] ; + // value method master1_aw_awsize + assign master1_awsize = + mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[20:18] ; - // value method master1_m_awsize - assign master1_awsize = mmio_axi4_adapter_master_xactor_rg_wr_addr[20:18] ; + // value method master1_aw_awburst + assign master1_awburst = + mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[17:16] ; - // value method master1_m_awburst - assign master1_awburst = mmio_axi4_adapter_master_xactor_rg_wr_addr[17:16] ; + // value method master1_aw_awlock + assign master1_awlock = + mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[15] ; - // value method master1_m_awlock - assign master1_awlock = mmio_axi4_adapter_master_xactor_rg_wr_addr[15] ; + // value method master1_aw_awcache + assign master1_awcache = + mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[14:11] ; - // value method master1_m_awcache - assign master1_awcache = mmio_axi4_adapter_master_xactor_rg_wr_addr[14:11] ; + // value method master1_aw_awprot + assign master1_awprot = + mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[10:8] ; - // value method master1_m_awprot - assign master1_awprot = mmio_axi4_adapter_master_xactor_rg_wr_addr[10:8] ; + // value method master1_aw_awqos + assign master1_awqos = + mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[7:4] ; - // value method master1_m_awqos - assign master1_awqos = mmio_axi4_adapter_master_xactor_rg_wr_addr[7:4] ; + // value method master1_aw_awregion + assign master1_awregion = + mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[3:0] ; - // value method master1_m_awregion - assign master1_awregion = mmio_axi4_adapter_master_xactor_rg_wr_addr[3:0] ; + // value method master1_aw_awvalid + assign master1_awvalid = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; - // action method master1_m_awready - assign CAN_FIRE_master1_m_awready = 1'd1 ; - assign WILL_FIRE_master1_m_awready = 1'd1 ; + // action method master1_aw_awready + assign CAN_FIRE_master1_aw_awready = 1'd1 ; + assign WILL_FIRE_master1_aw_awready = 1'd1 ; - // value method master1_m_wvalid - assign master1_wvalid = mmio_axi4_adapter_master_xactor_crg_wr_data_full ; + // value method master1_w_wdata + assign master1_wdata = + mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q17[73:10] ; - // value method master1_m_wid - assign master1_wid = mmio_axi4_adapter_master_xactor_rg_wr_data[76:73] ; + // value method master1_w_wstrb + assign master1_wstrb = + mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q17[9:2] ; - // value method master1_m_wdata - assign master1_wdata = mmio_axi4_adapter_master_xactor_rg_wr_data[72:9] ; + // value method master1_w_wlast + assign master1_wlast = + mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q17[1] ; - // value method master1_m_wstrb - assign master1_wstrb = mmio_axi4_adapter_master_xactor_rg_wr_data[8:1] ; + // value method master1_w_wuser + assign master1_wuser = + mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q17[0] ; - // value method master1_m_wlast - assign master1_wlast = mmio_axi4_adapter_master_xactor_rg_wr_data[0] ; + // value method master1_w_wvalid + assign master1_wvalid = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; - // action method master1_m_wready - assign CAN_FIRE_master1_m_wready = 1'd1 ; - assign WILL_FIRE_master1_m_wready = 1'd1 ; + // action method master1_w_wready + assign CAN_FIRE_master1_w_wready = 1'd1 ; + assign WILL_FIRE_master1_w_wready = 1'd1 ; - // action method master1_m_bvalid - assign CAN_FIRE_master1_m_bvalid = 1'd1 ; - assign WILL_FIRE_master1_m_bvalid = 1'd1 ; + // action method master1_b_bflit + assign CAN_FIRE_master1_b_bflit = 1'd1 ; + assign WILL_FIRE_master1_b_bflit = master1_bvalid ; - // value method master1_m_bready - assign master1_bready = - !mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; + // value method master1_b_bready + assign master1_bready = !mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ; - // value method master1_m_arvalid - assign master1_arvalid = mmio_axi4_adapter_master_xactor_crg_rd_addr_full ; + // value method master1_ar_arid + assign master1_arid = + mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[96:93] ; - // value method master1_m_arid - assign master1_arid = mmio_axi4_adapter_master_xactor_rg_rd_addr[96:93] ; + // value method master1_ar_araddr + assign master1_araddr = + mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[92:29] ; - // value method master1_m_araddr - assign master1_araddr = mmio_axi4_adapter_master_xactor_rg_rd_addr[92:29] ; + // value method master1_ar_arlen + assign master1_arlen = + mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[28:21] ; - // value method master1_m_arlen - assign master1_arlen = mmio_axi4_adapter_master_xactor_rg_rd_addr[28:21] ; + // value method master1_ar_arsize + assign master1_arsize = + mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[20:18] ; - // value method master1_m_arsize - assign master1_arsize = mmio_axi4_adapter_master_xactor_rg_rd_addr[20:18] ; + // value method master1_ar_arburst + assign master1_arburst = + mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[17:16] ; - // value method master1_m_arburst - assign master1_arburst = mmio_axi4_adapter_master_xactor_rg_rd_addr[17:16] ; + // value method master1_ar_arlock + assign master1_arlock = + mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[15] ; - // value method master1_m_arlock - assign master1_arlock = mmio_axi4_adapter_master_xactor_rg_rd_addr[15] ; + // value method master1_ar_arcache + assign master1_arcache = + mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[14:11] ; - // value method master1_m_arcache - assign master1_arcache = mmio_axi4_adapter_master_xactor_rg_rd_addr[14:11] ; + // value method master1_ar_arprot + assign master1_arprot = + mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[10:8] ; - // value method master1_m_arprot - assign master1_arprot = mmio_axi4_adapter_master_xactor_rg_rd_addr[10:8] ; + // value method master1_ar_arqos + assign master1_arqos = + mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[7:4] ; - // value method master1_m_arqos - assign master1_arqos = mmio_axi4_adapter_master_xactor_rg_rd_addr[7:4] ; + // value method master1_ar_arregion + assign master1_arregion = + mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[3:0] ; - // value method master1_m_arregion - assign master1_arregion = mmio_axi4_adapter_master_xactor_rg_rd_addr[3:0] ; + // value method master1_ar_arvalid + assign master1_arvalid = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; - // action method master1_m_arready - assign CAN_FIRE_master1_m_arready = 1'd1 ; - assign WILL_FIRE_master1_m_arready = 1'd1 ; + // action method master1_ar_arready + assign CAN_FIRE_master1_ar_arready = 1'd1 ; + assign WILL_FIRE_master1_ar_arready = 1'd1 ; - // action method master1_m_rvalid - assign CAN_FIRE_master1_m_rvalid = 1'd1 ; - assign WILL_FIRE_master1_m_rvalid = 1'd1 ; + // action method master1_r_rflit + assign CAN_FIRE_master1_r_rflit = 1'd1 ; + assign WILL_FIRE_master1_r_rflit = master1_rvalid ; - // value method master1_m_rready - assign master1_rready = - !mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ; + // value method master1_r_rready + assign master1_rready = !mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ; // action method m_external_interrupt_req assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; @@ -2344,10 +2669,6 @@ module mkProc(CLK, assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - // action method debug_external_interrupt_req - assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ; - // action method non_maskable_interrupt_req assign CAN_FIRE_non_maskable_interrupt_req = 1'd1 ; assign WILL_FIRE_non_maskable_interrupt_req = 1'd1 ; @@ -2357,69 +2678,154 @@ module mkProc(CLK, assign CAN_FIRE_set_verbosity = 1'd1 ; assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - // actionvalue method trace_data_out_get - assign trace_data_out_get = f_trace_data$D_OUT ; - assign RDY_trace_data_out_get = f_trace_data$EMPTY_N ; - assign CAN_FIRE_trace_data_out_get = f_trace_data$EMPTY_N ; - assign WILL_FIRE_trace_data_out_get = EN_trace_data_out_get ; + // action method debug_module_mem_server_aw_awflit + assign CAN_FIRE_debug_module_mem_server_aw_awflit = 1'd1 ; + assign WILL_FIRE_debug_module_mem_server_aw_awflit = + debug_module_mem_server_awvalid ; - // action method hart0_server_run_halt_request_put - assign RDY_hart0_server_run_halt_request_put = 1'd1 ; - assign CAN_FIRE_hart0_server_run_halt_request_put = 1'd1 ; - assign WILL_FIRE_hart0_server_run_halt_request_put = - EN_hart0_server_run_halt_request_put ; + // value method debug_module_mem_server_aw_awready + assign debug_module_mem_server_awready = + !llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] ; - // actionvalue method hart0_server_run_halt_response_get - assign hart0_server_run_halt_response_get = 1'h0 ; - assign RDY_hart0_server_run_halt_response_get = 1'd1 ; - assign CAN_FIRE_hart0_server_run_halt_response_get = 1'd1 ; - assign WILL_FIRE_hart0_server_run_halt_response_get = - EN_hart0_server_run_halt_response_get ; + // action method debug_module_mem_server_w_wflit + assign CAN_FIRE_debug_module_mem_server_w_wflit = 1'd1 ; + assign WILL_FIRE_debug_module_mem_server_w_wflit = + debug_module_mem_server_wvalid ; + + // value method debug_module_mem_server_w_wready + assign debug_module_mem_server_wready = + !llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] ; + + // value method debug_module_mem_server_b_bid + assign debug_module_mem_server_bid = + llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q38[6:2] ; + + // value method debug_module_mem_server_b_bresp + assign debug_module_mem_server_bresp = + llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q38[1:0] ; + + // value method debug_module_mem_server_b_bvalid + assign debug_module_mem_server_bvalid = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek ; + + // action method debug_module_mem_server_b_bready + assign CAN_FIRE_debug_module_mem_server_b_bready = 1'd1 ; + assign WILL_FIRE_debug_module_mem_server_b_bready = 1'd1 ; + + // action method debug_module_mem_server_ar_arflit + assign CAN_FIRE_debug_module_mem_server_ar_arflit = 1'd1 ; + assign WILL_FIRE_debug_module_mem_server_ar_arflit = + debug_module_mem_server_arvalid ; + + // value method debug_module_mem_server_ar_arready + assign debug_module_mem_server_arready = + !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; + + // value method debug_module_mem_server_r_rid + assign debug_module_mem_server_rid = + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39[72:68] ; + + // value method debug_module_mem_server_r_rdata + assign debug_module_mem_server_rdata = + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39[67:4] ; + + // value method debug_module_mem_server_r_rresp + assign debug_module_mem_server_rresp = + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39[3:2] ; + + // value method debug_module_mem_server_r_rlast + assign debug_module_mem_server_rlast = + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39[1] ; + + // value method debug_module_mem_server_r_ruser + assign debug_module_mem_server_ruser = + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39[0] ; + + // value method debug_module_mem_server_r_rvalid + assign debug_module_mem_server_rvalid = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek ; + + // action method debug_module_mem_server_r_rready + assign CAN_FIRE_debug_module_mem_server_r_rready = 1'd1 ; + assign WILL_FIRE_debug_module_mem_server_r_rready = 1'd1 ; + + // action method hart0_run_halt_server_request_put + assign RDY_hart0_run_halt_server_request_put = + core_0$RDY_hart0_run_halt_server_request_put ; + assign CAN_FIRE_hart0_run_halt_server_request_put = + core_0$RDY_hart0_run_halt_server_request_put ; + assign WILL_FIRE_hart0_run_halt_server_request_put = + EN_hart0_run_halt_server_request_put ; + + // actionvalue method hart0_run_halt_server_response_get + assign hart0_run_halt_server_response_get = + core_0$hart0_run_halt_server_response_get ; + assign RDY_hart0_run_halt_server_response_get = + core_0$RDY_hart0_run_halt_server_response_get ; + assign CAN_FIRE_hart0_run_halt_server_response_get = + core_0$RDY_hart0_run_halt_server_response_get ; + assign WILL_FIRE_hart0_run_halt_server_response_get = + EN_hart0_run_halt_server_response_get ; + + // action method hart0_gpr_mem_server_request_put + assign RDY_hart0_gpr_mem_server_request_put = + core_0$RDY_hart0_gpr_mem_server_request_put ; + assign CAN_FIRE_hart0_gpr_mem_server_request_put = + core_0$RDY_hart0_gpr_mem_server_request_put ; + assign WILL_FIRE_hart0_gpr_mem_server_request_put = + EN_hart0_gpr_mem_server_request_put ; + + // actionvalue method hart0_gpr_mem_server_response_get + assign hart0_gpr_mem_server_response_get = + core_0$hart0_gpr_mem_server_response_get ; + assign RDY_hart0_gpr_mem_server_response_get = + core_0$RDY_hart0_gpr_mem_server_response_get ; + assign CAN_FIRE_hart0_gpr_mem_server_response_get = + core_0$RDY_hart0_gpr_mem_server_response_get ; + assign WILL_FIRE_hart0_gpr_mem_server_response_get = + EN_hart0_gpr_mem_server_response_get ; + + // action method hart0_fpr_mem_server_request_put + assign RDY_hart0_fpr_mem_server_request_put = + core_0$RDY_hart0_fpr_mem_server_request_put ; + assign CAN_FIRE_hart0_fpr_mem_server_request_put = + core_0$RDY_hart0_fpr_mem_server_request_put ; + assign WILL_FIRE_hart0_fpr_mem_server_request_put = + EN_hart0_fpr_mem_server_request_put ; + + // actionvalue method hart0_fpr_mem_server_response_get + assign hart0_fpr_mem_server_response_get = + core_0$hart0_fpr_mem_server_response_get ; + assign RDY_hart0_fpr_mem_server_response_get = + core_0$RDY_hart0_fpr_mem_server_response_get ; + assign CAN_FIRE_hart0_fpr_mem_server_response_get = + core_0$RDY_hart0_fpr_mem_server_response_get ; + assign WILL_FIRE_hart0_fpr_mem_server_response_get = + EN_hart0_fpr_mem_server_response_get ; + + // action method hart0_csr_mem_server_request_put + assign RDY_hart0_csr_mem_server_request_put = + core_0$RDY_hart0_csr_mem_server_request_put ; + assign CAN_FIRE_hart0_csr_mem_server_request_put = + core_0$RDY_hart0_csr_mem_server_request_put ; + assign WILL_FIRE_hart0_csr_mem_server_request_put = + EN_hart0_csr_mem_server_request_put ; + + // actionvalue method hart0_csr_mem_server_response_get + assign hart0_csr_mem_server_response_get = + core_0$hart0_csr_mem_server_response_get ; + assign RDY_hart0_csr_mem_server_response_get = + core_0$RDY_hart0_csr_mem_server_response_get ; + assign CAN_FIRE_hart0_csr_mem_server_response_get = + core_0$RDY_hart0_csr_mem_server_response_get ; + assign WILL_FIRE_hart0_csr_mem_server_response_get = + EN_hart0_csr_mem_server_response_get ; // action method hart0_put_other_req_put assign RDY_hart0_put_other_req_put = 1'd1 ; assign CAN_FIRE_hart0_put_other_req_put = 1'd1 ; assign WILL_FIRE_hart0_put_other_req_put = EN_hart0_put_other_req_put ; - // action method hart0_gpr_mem_server_request_put - assign RDY_hart0_gpr_mem_server_request_put = 1'd1 ; - assign CAN_FIRE_hart0_gpr_mem_server_request_put = 1'd1 ; - assign WILL_FIRE_hart0_gpr_mem_server_request_put = - EN_hart0_gpr_mem_server_request_put ; - - // actionvalue method hart0_gpr_mem_server_response_get - assign hart0_gpr_mem_server_response_get = 65'h0AAAAAAAAAAAAAAAA ; - assign RDY_hart0_gpr_mem_server_response_get = 1'd1 ; - assign CAN_FIRE_hart0_gpr_mem_server_response_get = 1'd1 ; - assign WILL_FIRE_hart0_gpr_mem_server_response_get = - EN_hart0_gpr_mem_server_response_get ; - - // action method hart0_fpr_mem_server_request_put - assign RDY_hart0_fpr_mem_server_request_put = 1'd1 ; - assign CAN_FIRE_hart0_fpr_mem_server_request_put = 1'd1 ; - assign WILL_FIRE_hart0_fpr_mem_server_request_put = - EN_hart0_fpr_mem_server_request_put ; - - // actionvalue method hart0_fpr_mem_server_response_get - assign hart0_fpr_mem_server_response_get = 65'h0AAAAAAAAAAAAAAAA ; - assign RDY_hart0_fpr_mem_server_response_get = 1'd1 ; - assign CAN_FIRE_hart0_fpr_mem_server_response_get = 1'd1 ; - assign WILL_FIRE_hart0_fpr_mem_server_response_get = - EN_hart0_fpr_mem_server_response_get ; - - // action method hart0_csr_mem_server_request_put - assign RDY_hart0_csr_mem_server_request_put = 1'd1 ; - assign CAN_FIRE_hart0_csr_mem_server_request_put = 1'd1 ; - assign WILL_FIRE_hart0_csr_mem_server_request_put = - EN_hart0_csr_mem_server_request_put ; - - // actionvalue method hart0_csr_mem_server_response_get - assign hart0_csr_mem_server_response_get = 65'h0AAAAAAAAAAAAAAAA ; - assign RDY_hart0_csr_mem_server_response_get = 1'd1 ; - assign CAN_FIRE_hart0_csr_mem_server_response_get = 1'd1 ; - assign WILL_FIRE_hart0_csr_mem_server_response_get = - EN_hart0_csr_mem_server_response_get ; - // submodule core_0 mkCore core_0(.CLK(CLK), .RST_N(RST_N), @@ -2429,12 +2835,15 @@ module mkProc(CLK, .coreReq_start_startpc(core_0$coreReq_start_startpc), .coreReq_start_toHostAddr(core_0$coreReq_start_toHostAddr), .dCacheToParent_fromP_enq_x(core_0$dCacheToParent_fromP_enq_x), + .hart0_csr_mem_server_request_put(core_0$hart0_csr_mem_server_request_put), + .hart0_fpr_mem_server_request_put(core_0$hart0_fpr_mem_server_request_put), + .hart0_gpr_mem_server_request_put(core_0$hart0_gpr_mem_server_request_put), + .hart0_run_halt_server_request_put(core_0$hart0_run_halt_server_request_put), .iCacheToParent_fromP_enq_x(core_0$iCacheToParent_fromP_enq_x), .mmioToPlatform_pRq_enq_x(core_0$mmioToPlatform_pRq_enq_x), .mmioToPlatform_pRs_enq_x(core_0$mmioToPlatform_pRs_enq_x), .mmioToPlatform_setTime_t(core_0$mmioToPlatform_setTime_t), .recvDoStats_x(core_0$recvDoStats_x), - .setDEIP_v(core_0$setDEIP_v), .setMEIP_v(core_0$setMEIP_v), .setSEIP_v(core_0$setSEIP_v), .tlbToMem_respLd_enq_x(core_0$tlbToMem_respLd_enq_x), @@ -2469,7 +2878,14 @@ module mkProc(CLK, .EN_renameDebug_renameErr_get(core_0$EN_renameDebug_renameErr_get), .EN_setMEIP(core_0$EN_setMEIP), .EN_setSEIP(core_0$EN_setSEIP), - .EN_setDEIP(core_0$EN_setDEIP), + .EN_hart0_run_halt_server_request_put(core_0$EN_hart0_run_halt_server_request_put), + .EN_hart0_run_halt_server_response_get(core_0$EN_hart0_run_halt_server_response_get), + .EN_hart0_gpr_mem_server_request_put(core_0$EN_hart0_gpr_mem_server_request_put), + .EN_hart0_gpr_mem_server_response_get(core_0$EN_hart0_gpr_mem_server_response_get), + .EN_hart0_fpr_mem_server_request_put(core_0$EN_hart0_fpr_mem_server_request_put), + .EN_hart0_fpr_mem_server_response_get(core_0$EN_hart0_fpr_mem_server_response_get), + .EN_hart0_csr_mem_server_request_put(core_0$EN_hart0_csr_mem_server_request_put), + .EN_hart0_csr_mem_server_response_get(core_0$EN_hart0_csr_mem_server_response_get), .RDY_coreReq_start(), .RDY_coreReq_perfReq(), .coreIndInv_perfResp(), @@ -2550,72 +2966,18 @@ module mkProc(CLK, .RDY_renameDebug_renameErr_get(core_0$RDY_renameDebug_renameErr_get), .RDY_setMEIP(), .RDY_setSEIP(), - .RDY_setDEIP()); - - // submodule enqDst_0_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_0(.CLK(CLK), - .D_IN(enqDst_0_dummy2_0$D_IN), - .EN(enqDst_0_dummy2_0$EN), - .Q_OUT(enqDst_0_dummy2_0$Q_OUT)); - - // submodule enqDst_0_dummy2_0_1 - RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_0_1(.CLK(CLK), - .D_IN(enqDst_0_dummy2_0_1$D_IN), - .EN(enqDst_0_dummy2_0_1$EN), - .Q_OUT(enqDst_0_dummy2_0_1$Q_OUT)); - - // submodule enqDst_0_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_1(.CLK(CLK), - .D_IN(enqDst_0_dummy2_1$D_IN), - .EN(enqDst_0_dummy2_1$EN), - .Q_OUT(enqDst_0_dummy2_1$Q_OUT)); - - // submodule enqDst_0_dummy2_1_1 - RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_1_1(.CLK(CLK), - .D_IN(enqDst_0_dummy2_1_1$D_IN), - .EN(enqDst_0_dummy2_1_1$EN), - .Q_OUT(enqDst_0_dummy2_1_1$Q_OUT)); - - // submodule enqDst_1_0_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) enqDst_1_0_dummy2_0(.CLK(CLK), - .D_IN(enqDst_1_0_dummy2_0$D_IN), - .EN(enqDst_1_0_dummy2_0$EN), - .Q_OUT(enqDst_1_0_dummy2_0$Q_OUT)); - - // submodule enqDst_1_0_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) enqDst_1_0_dummy2_1(.CLK(CLK), - .D_IN(enqDst_1_0_dummy2_1$D_IN), - .EN(enqDst_1_0_dummy2_1$EN), - .Q_OUT(enqDst_1_0_dummy2_1$Q_OUT)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_trace_data - FIFO2 #(.width(32'd362), .guarded(32'd1)) f_trace_data(.RST(RST_N), - .CLK(CLK), - .D_IN(f_trace_data$D_IN), - .ENQ(f_trace_data$ENQ), - .DEQ(f_trace_data$DEQ), - .CLR(f_trace_data$CLR), - .D_OUT(f_trace_data$D_OUT), - .FULL_N(), - .EMPTY_N(f_trace_data$EMPTY_N)); + .RDY_hart0_run_halt_server_request_put(core_0$RDY_hart0_run_halt_server_request_put), + .hart0_run_halt_server_response_get(core_0$hart0_run_halt_server_response_get), + .RDY_hart0_run_halt_server_response_get(core_0$RDY_hart0_run_halt_server_response_get), + .RDY_hart0_gpr_mem_server_request_put(core_0$RDY_hart0_gpr_mem_server_request_put), + .hart0_gpr_mem_server_response_get(core_0$hart0_gpr_mem_server_response_get), + .RDY_hart0_gpr_mem_server_response_get(core_0$RDY_hart0_gpr_mem_server_response_get), + .RDY_hart0_fpr_mem_server_request_put(core_0$RDY_hart0_fpr_mem_server_request_put), + .hart0_fpr_mem_server_response_get(core_0$hart0_fpr_mem_server_response_get), + .RDY_hart0_fpr_mem_server_response_get(core_0$RDY_hart0_fpr_mem_server_response_get), + .RDY_hart0_csr_mem_server_request_put(core_0$RDY_hart0_csr_mem_server_request_put), + .hart0_csr_mem_server_response_get(core_0$hart0_csr_mem_server_response_get), + .RDY_hart0_csr_mem_server_response_get(core_0$RDY_hart0_csr_mem_server_response_get)); // submodule llc mkLLCache llc(.CLK(CLK), @@ -2691,132 +3053,31 @@ module mkProc(CLK, .FULL_N(llc_axi4_adapter_f_pending_reads$FULL_N), .EMPTY_N(llc_axi4_adapter_f_pending_reads$EMPTY_N)); - // submodule llc_axi4_adapter_f_pending_writes - FIFO2 #(.width(32'd640), - .guarded(32'd1)) llc_axi4_adapter_f_pending_writes(.RST(RST_N), - .CLK(CLK), - .D_IN(llc_axi4_adapter_f_pending_writes$D_IN), - .ENQ(llc_axi4_adapter_f_pending_writes$ENQ), - .DEQ(llc_axi4_adapter_f_pending_writes$DEQ), - .CLR(llc_axi4_adapter_f_pending_writes$CLR), - .D_OUT(), - .FULL_N(llc_axi4_adapter_f_pending_writes$FULL_N), - .EMPTY_N(llc_axi4_adapter_f_pending_writes$EMPTY_N)); + // submodule llc_mem_server_f_dword_in_line + FIFO2 #(.width(32'd3), + .guarded(32'd1)) llc_mem_server_f_dword_in_line(.RST(RST_N), + .CLK(CLK), + .D_IN(llc_mem_server_f_dword_in_line$D_IN), + .ENQ(llc_mem_server_f_dword_in_line$ENQ), + .DEQ(llc_mem_server_f_dword_in_line$DEQ), + .CLR(llc_mem_server_f_dword_in_line$CLR), + .D_OUT(), + .FULL_N(), + .EMPTY_N()); - // submodule mmioPlatform_fromHostQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_fromHostQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(mmioPlatform_fromHostQ_clearReq_dummy2_0$D_IN), - .EN(mmioPlatform_fromHostQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmioPlatform_fromHostQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_fromHostQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(mmioPlatform_fromHostQ_clearReq_dummy2_1$D_IN), - .EN(mmioPlatform_fromHostQ_clearReq_dummy2_1$EN), - .Q_OUT(mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT)); - - // submodule mmioPlatform_fromHostQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_fromHostQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(mmioPlatform_fromHostQ_deqReq_dummy2_0$D_IN), - .EN(mmioPlatform_fromHostQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmioPlatform_fromHostQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_fromHostQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(mmioPlatform_fromHostQ_deqReq_dummy2_1$D_IN), - .EN(mmioPlatform_fromHostQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmioPlatform_fromHostQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_fromHostQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(mmioPlatform_fromHostQ_deqReq_dummy2_2$D_IN), - .EN(mmioPlatform_fromHostQ_deqReq_dummy2_2$EN), - .Q_OUT(mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT)); - - // submodule mmioPlatform_fromHostQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_fromHostQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(mmioPlatform_fromHostQ_enqReq_dummy2_0$D_IN), - .EN(mmioPlatform_fromHostQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmioPlatform_fromHostQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_fromHostQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(mmioPlatform_fromHostQ_enqReq_dummy2_1$D_IN), - .EN(mmioPlatform_fromHostQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmioPlatform_fromHostQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_fromHostQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(mmioPlatform_fromHostQ_enqReq_dummy2_2$D_IN), - .EN(mmioPlatform_fromHostQ_enqReq_dummy2_2$EN), - .Q_OUT(mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT)); - - // submodule mmioPlatform_toHostQ_clearReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_toHostQ_clearReq_dummy2_0(.CLK(CLK), - .D_IN(mmioPlatform_toHostQ_clearReq_dummy2_0$D_IN), - .EN(mmioPlatform_toHostQ_clearReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmioPlatform_toHostQ_clearReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_toHostQ_clearReq_dummy2_1(.CLK(CLK), - .D_IN(mmioPlatform_toHostQ_clearReq_dummy2_1$D_IN), - .EN(mmioPlatform_toHostQ_clearReq_dummy2_1$EN), - .Q_OUT(mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT)); - - // submodule mmioPlatform_toHostQ_deqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_toHostQ_deqReq_dummy2_0(.CLK(CLK), - .D_IN(mmioPlatform_toHostQ_deqReq_dummy2_0$D_IN), - .EN(mmioPlatform_toHostQ_deqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmioPlatform_toHostQ_deqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_toHostQ_deqReq_dummy2_1(.CLK(CLK), - .D_IN(mmioPlatform_toHostQ_deqReq_dummy2_1$D_IN), - .EN(mmioPlatform_toHostQ_deqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmioPlatform_toHostQ_deqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_toHostQ_deqReq_dummy2_2(.CLK(CLK), - .D_IN(mmioPlatform_toHostQ_deqReq_dummy2_2$D_IN), - .EN(mmioPlatform_toHostQ_deqReq_dummy2_2$EN), - .Q_OUT(mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT)); - - // submodule mmioPlatform_toHostQ_enqReq_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_toHostQ_enqReq_dummy2_0(.CLK(CLK), - .D_IN(mmioPlatform_toHostQ_enqReq_dummy2_0$D_IN), - .EN(mmioPlatform_toHostQ_enqReq_dummy2_0$EN), - .Q_OUT()); - - // submodule mmioPlatform_toHostQ_enqReq_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_toHostQ_enqReq_dummy2_1(.CLK(CLK), - .D_IN(mmioPlatform_toHostQ_enqReq_dummy2_1$D_IN), - .EN(mmioPlatform_toHostQ_enqReq_dummy2_1$EN), - .Q_OUT()); - - // submodule mmioPlatform_toHostQ_enqReq_dummy2_2 - RevertReg #(.width(32'd1), - .init(1'd1)) mmioPlatform_toHostQ_enqReq_dummy2_2(.CLK(CLK), - .D_IN(mmioPlatform_toHostQ_enqReq_dummy2_2$D_IN), - .EN(mmioPlatform_toHostQ_enqReq_dummy2_2$EN), - .Q_OUT(mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT)); + // submodule llc_mem_server_tlbQ + FIFO2 #(.width(32'd65), .guarded(32'd1)) llc_mem_server_tlbQ(.RST(RST_N), + .CLK(CLK), + .D_IN(llc_mem_server_tlbQ$D_IN), + .ENQ(llc_mem_server_tlbQ$ENQ), + .DEQ(llc_mem_server_tlbQ$DEQ), + .CLR(llc_mem_server_tlbQ$CLR), + .D_OUT(llc_mem_server_tlbQ$D_OUT), + .FULL_N(llc_mem_server_tlbQ$FULL_N), + .EMPTY_N(llc_mem_server_tlbQ$EMPTY_N)); // submodule mmio_axi4_adapter_f_reqs_from_core - FIFO2 #(.width(32'd142), + FIFO2 #(.width(32'd215), .guarded(32'd1)) mmio_axi4_adapter_f_reqs_from_core(.RST(RST_N), .CLK(CLK), .D_IN(mmio_axi4_adapter_f_reqs_from_core$D_IN), @@ -2828,7 +3089,7 @@ module mkProc(CLK, .EMPTY_N(mmio_axi4_adapter_f_reqs_from_core$EMPTY_N)); // submodule mmio_axi4_adapter_f_rsps_to_core - FIFO2 #(.width(32'd65), + FIFO2 #(.width(32'd130), .guarded(32'd1)) mmio_axi4_adapter_f_rsps_to_core(.RST(RST_N), .CLK(CLK), .D_IN(mmio_axi4_adapter_f_rsps_to_core$D_IN), @@ -2839,151 +3100,42 @@ module mkProc(CLK, .FULL_N(mmio_axi4_adapter_f_rsps_to_core$FULL_N), .EMPTY_N(mmio_axi4_adapter_f_rsps_to_core$EMPTY_N)); - // submodule propDstData_0_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_0(.CLK(CLK), - .D_IN(propDstData_0_dummy2_0$D_IN), - .EN(propDstData_0_dummy2_0$EN), - .Q_OUT()); - - // submodule propDstData_0_dummy2_0_1 - RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_0_1(.CLK(CLK), - .D_IN(propDstData_0_dummy2_0_1$D_IN), - .EN(propDstData_0_dummy2_0_1$EN), - .Q_OUT()); - - // submodule propDstData_0_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_1(.CLK(CLK), - .D_IN(propDstData_0_dummy2_1$D_IN), - .EN(propDstData_0_dummy2_1$EN), - .Q_OUT(propDstData_0_dummy2_1$Q_OUT)); - - // submodule propDstData_0_dummy2_1_1 - RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_1_1(.CLK(CLK), - .D_IN(propDstData_0_dummy2_1_1$D_IN), - .EN(propDstData_0_dummy2_1_1$EN), - .Q_OUT(propDstData_0_dummy2_1_1$Q_OUT)); - - // submodule propDstData_1_0_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_0_dummy2_0(.CLK(CLK), - .D_IN(propDstData_1_0_dummy2_0$D_IN), - .EN(propDstData_1_0_dummy2_0$EN), - .Q_OUT()); - - // submodule propDstData_1_0_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_0_dummy2_1(.CLK(CLK), - .D_IN(propDstData_1_0_dummy2_1$D_IN), - .EN(propDstData_1_0_dummy2_1$EN), - .Q_OUT(propDstData_1_0_dummy2_1$Q_OUT)); - - // submodule propDstData_1_1_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_1_dummy2_0(.CLK(CLK), - .D_IN(propDstData_1_1_dummy2_0$D_IN), - .EN(propDstData_1_1_dummy2_0$EN), - .Q_OUT()); - - // submodule propDstData_1_1_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_1_dummy2_1(.CLK(CLK), - .D_IN(propDstData_1_1_dummy2_1$D_IN), - .EN(propDstData_1_1_dummy2_1$EN), - .Q_OUT(propDstData_1_1_dummy2_1$Q_OUT)); - - // submodule propDstData_1_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_dummy2_0(.CLK(CLK), - .D_IN(propDstData_1_dummy2_0$D_IN), - .EN(propDstData_1_dummy2_0$EN), - .Q_OUT()); - - // submodule propDstData_1_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_dummy2_1(.CLK(CLK), - .D_IN(propDstData_1_dummy2_1$D_IN), - .EN(propDstData_1_dummy2_1$EN), - .Q_OUT(propDstData_1_dummy2_1$Q_OUT)); - - // submodule propDstIdx_0_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_0(.CLK(CLK), - .D_IN(propDstIdx_0_dummy2_0$D_IN), - .EN(propDstIdx_0_dummy2_0$EN), - .Q_OUT(propDstIdx_0_dummy2_0$Q_OUT)); - - // submodule propDstIdx_0_dummy2_0_1 - RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_0_1(.CLK(CLK), - .D_IN(propDstIdx_0_dummy2_0_1$D_IN), - .EN(propDstIdx_0_dummy2_0_1$EN), - .Q_OUT(propDstIdx_0_dummy2_0_1$Q_OUT)); - - // submodule propDstIdx_0_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_1(.CLK(CLK), - .D_IN(propDstIdx_0_dummy2_1$D_IN), - .EN(propDstIdx_0_dummy2_1$EN), - .Q_OUT(propDstIdx_0_dummy2_1$Q_OUT)); - - // submodule propDstIdx_0_dummy2_1_1 - RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_1_1(.CLK(CLK), - .D_IN(propDstIdx_0_dummy2_1_1$D_IN), - .EN(propDstIdx_0_dummy2_1_1$EN), - .Q_OUT(propDstIdx_0_dummy2_1_1$Q_OUT)); - - // submodule propDstIdx_1_0_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_0_dummy2_0(.CLK(CLK), - .D_IN(propDstIdx_1_0_dummy2_0$D_IN), - .EN(propDstIdx_1_0_dummy2_0$EN), - .Q_OUT(propDstIdx_1_0_dummy2_0$Q_OUT)); - - // submodule propDstIdx_1_0_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_0_dummy2_1(.CLK(CLK), - .D_IN(propDstIdx_1_0_dummy2_1$D_IN), - .EN(propDstIdx_1_0_dummy2_1$EN), - .Q_OUT(propDstIdx_1_0_dummy2_1$Q_OUT)); - - // submodule propDstIdx_1_1_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_1_dummy2_0(.CLK(CLK), - .D_IN(propDstIdx_1_1_dummy2_0$D_IN), - .EN(propDstIdx_1_1_dummy2_0$EN), - .Q_OUT(propDstIdx_1_1_dummy2_0$Q_OUT)); - - // submodule propDstIdx_1_1_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_1_dummy2_1(.CLK(CLK), - .D_IN(propDstIdx_1_1_dummy2_1$D_IN), - .EN(propDstIdx_1_1_dummy2_1$EN), - .Q_OUT(propDstIdx_1_1_dummy2_1$Q_OUT)); - - // submodule propDstIdx_1_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_dummy2_0(.CLK(CLK), - .D_IN(propDstIdx_1_dummy2_0$D_IN), - .EN(propDstIdx_1_dummy2_0$EN), - .Q_OUT(propDstIdx_1_dummy2_0$Q_OUT)); - - // submodule propDstIdx_1_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_dummy2_1(.CLK(CLK), - .D_IN(propDstIdx_1_dummy2_1$D_IN), - .EN(propDstIdx_1_dummy2_1$EN), - .Q_OUT(propDstIdx_1_dummy2_1$Q_OUT)); - - // submodule tlbQ - FIFO2 #(.width(32'd65), .guarded(32'd1)) tlbQ(.RST(RST_N), - .CLK(CLK), - .D_IN(tlbQ$D_IN), - .ENQ(tlbQ$ENQ), - .DEQ(tlbQ$DEQ), - .CLR(tlbQ$CLR), - .D_OUT(tlbQ$D_OUT), - .FULL_N(tlbQ$FULL_N), - .EMPTY_N(tlbQ$EMPTY_N)); + // submodule mmio_axi4_adapter_soc_map + mkSoC_Map mmio_axi4_adapter_soc_map(.CLK(CLK), + .RST_N(RST_N), + .m_is_IO_addr_addr(mmio_axi4_adapter_soc_map$m_is_IO_addr_addr), + .m_is_mem_addr_addr(mmio_axi4_adapter_soc_map$m_is_mem_addr_addr), + .m_is_near_mem_IO_addr_addr(mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr), + .m_plic_addr_range(), + .m_near_mem_io_addr_range(), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), + .m_mem0_controller_addr_range(), + .m_is_mem_addr(), + .m_is_IO_addr(mmio_axi4_adapter_soc_map$m_is_IO_addr), + .m_is_near_mem_IO_addr(), + .m_pc_reset_value(), + .m_mtvec_reset_value(), + .m_nmivec_reset_value()); // rule RL_srcPropose assign CAN_FIRE_RL_srcPropose = core_0$RDY_dCacheToParent_rqToP_first && core_0$RDY_dCacheToParent_rqToP_deq && - (!propDstIdx_0_dummy2_0$Q_OUT || !propDstIdx_0_dummy2_1$Q_OUT || - !propDstIdx_0_rl) ; + !propDstIdx_0_rl ; assign WILL_FIRE_RL_srcPropose = CAN_FIRE_RL_srcPropose ; // rule RL_srcPropose_1 assign CAN_FIRE_RL_srcPropose_1 = core_0$RDY_iCacheToParent_rqToP_first && core_0$RDY_iCacheToParent_rqToP_deq && - (!propDstIdx_1_dummy2_0$Q_OUT || !propDstIdx_1_dummy2_1$Q_OUT || - !propDstIdx_1_rl) ; + !propDstIdx_1_rl ; assign WILL_FIRE_RL_srcPropose_1 = CAN_FIRE_RL_srcPropose_1 ; // rule RL_dstSelectSrc @@ -2992,26 +3144,22 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = - llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT && - IF_enqDst_0_lat_0_whas__95_THEN_enqDst_0_lat_0_ETC___d1000 ; + llc$RDY_to_child_rqFromC_enq && + IF_enqDst_0_lat_0_whas__150_THEN_enqDst_0_lat__ETC___d1155 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 assign CAN_FIRE_RL_srcPropose_2 = core_0$RDY_dCacheToParent_rsToP_first && core_0$RDY_dCacheToParent_rsToP_deq && - (!propDstIdx_1_0_dummy2_0$Q_OUT || - !propDstIdx_1_0_dummy2_1$Q_OUT || - !propDstIdx_1_0_rl) ; + !propDstIdx_1_0_rl ; assign WILL_FIRE_RL_srcPropose_2 = CAN_FIRE_RL_srcPropose_2 ; // rule RL_srcPropose_3 assign CAN_FIRE_RL_srcPropose_3 = core_0$RDY_iCacheToParent_rsToP_first && core_0$RDY_iCacheToParent_rsToP_deq && - (!propDstIdx_1_1_dummy2_0$Q_OUT || - !propDstIdx_1_1_dummy2_1$Q_OUT || - !propDstIdx_1_1_rl) ; + !propDstIdx_1_1_rl ; assign WILL_FIRE_RL_srcPropose_3 = CAN_FIRE_RL_srcPropose_3 ; // rule RL_dstSelectSrc_1 @@ -3020,93 +3168,46 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = - llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT && - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1231 ; + llc$RDY_to_child_rsFromC_enq && + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1350 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && - !llc$to_child_toC_first[583] && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && + !llc$to_child_toC_first[587] && !llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ; // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && - llc$to_child_toC_first[583] && - !llc$to_child_toC_first[516] ; + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && + llc$to_child_toC_first[587] && + !llc$to_child_toC_first[520] ; assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ; // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && - !llc$to_child_toC_first[583] && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && + !llc$to_child_toC_first[587] && llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ; // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && - llc$to_child_toC_first[583] && - llc$to_child_toC_first[516] ; + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && + llc$to_child_toC_first[587] && + llc$to_child_toC_first[520] ; assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ; - // rule RL_srcPropose_4 - assign CAN_FIRE_RL_srcPropose_4 = - core_0$RDY_tlbToMem_memReq_first && - core_0$RDY_tlbToMem_memReq_deq && - (!propDstIdx_0_dummy2_0_1$Q_OUT || - !propDstIdx_0_dummy2_1_1$Q_OUT || - !propDstIdx_0_rl_1) ; - assign WILL_FIRE_RL_srcPropose_4 = CAN_FIRE_RL_srcPropose_4 ; - - // rule RL_dstSelectSrc_2 - assign CAN_FIRE_RL_dstSelectSrc_2 = 1'd1 ; - assign WILL_FIRE_RL_dstSelectSrc_2 = 1'd1 ; - - // rule RL_doEnq_2 - assign CAN_FIRE_RL_doEnq_2 = - tlbQ$FULL_N && enqDst_0_dummy2_1_1$Q_OUT && - IF_enqDst_0_lat_0_1_whas__482_THEN_enqDst_0_la_ETC___d1487 ; - assign WILL_FIRE_RL_doEnq_2 = CAN_FIRE_RL_doEnq_2 ; - - // rule RL_sendTlbReqToLLC - assign CAN_FIRE_RL_sendTlbReqToLLC = - llc$RDY_dma_memReq_enq && tlbQ$EMPTY_N ; - assign WILL_FIRE_RL_sendTlbReqToLLC = CAN_FIRE_RL_sendTlbReqToLLC ; - - // rule RL_sendLdRespToMemLoader - assign CAN_FIRE_RL_sendLdRespToMemLoader = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && - !llc$dma_respLd_first[4] ; - assign WILL_FIRE_RL_sendLdRespToMemLoader = - CAN_FIRE_RL_sendLdRespToMemLoader ; - - // rule RL_sendLdRespToTlb - assign CAN_FIRE_RL_sendLdRespToTlb = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && - core_0$RDY_tlbToMem_respLd_enq && - llc$dma_respLd_first[4] ; - assign WILL_FIRE_RL_sendLdRespToTlb = CAN_FIRE_RL_sendLdRespToTlb ; - - // rule RL_sendStRespToMemLoader - assign CAN_FIRE_RL_sendStRespToMemLoader = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && - !llc$dma_respSt_first[4] ; - assign WILL_FIRE_RL_sendStRespToMemLoader = - CAN_FIRE_RL_sendStRespToMemLoader ; - - // rule RL_sendStRespToTlb - assign CAN_FIRE_RL_sendStRespToTlb = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && - llc$dma_respSt_first[4] ; - assign WILL_FIRE_RL_sendStRespToTlb = CAN_FIRE_RL_sendStRespToTlb ; - // rule RL_broadcastStats assign CAN_FIRE_RL_broadcastStats = core_0$RDY_sendDoStats ; assign WILL_FIRE_RL_broadcastStats = core_0$RDY_sendDoStats ; @@ -3162,49 +3263,148 @@ module mkProc(CLK, assign CAN_FIRE_RL_rl_tohost = !mmioPlatform_toHostQ_empty ; assign WILL_FIRE_RL_rl_tohost = CAN_FIRE_RL_rl_tohost ; - // rule RL_mmio_axi4_adapter_rl_handle_read_rsps - assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = - mmio_axi4_adapter_master_xactor_crg_rd_data_full && - mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; - // rule RL_mmio_axi4_adapter_rl_handle_write_req assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = - !mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read && - !mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read && mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd2 ; + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd2 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; // rule RL_mmio_axi4_adapter_rl_handle_read_req assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = - !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read && mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2368 == 4'd0 ; + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd1 && + b__h4255 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; - // rule RL_mmio_axi4_adapter_rl_discard_write_rsp - assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2368 != 4'd0 && - mmio_axi4_adapter_master_xactor_crg_wr_resp_full && - (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || - mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; - // rule RL_mmio_axi4_adapter_rl_handle_non_Ld_St assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St = mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd1 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd2 ; + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd1 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd2 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St ; + // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = + mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; + + // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = + mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas && + !mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop ; + + // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = + mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] && + mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ; + + // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek = + mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; + + // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = + mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas && + !mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop ; + + // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop = + mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && + mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop ; + + // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = + mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas && + mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut ; + + // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut = + !mmio_axi4_adapter_master_xactor_shim_bff_rv[6] && + mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut ; + + // rule RL_mmio_axi4_adapter_rl_discard_write_rsp + assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = + !mmio_axi4_adapter_master_xactor_clearing && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[6] && + b__h4255 != 4'd0 && + (mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0 || + mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; + assign WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = + CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; + + // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = + mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; + + // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = + mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas && + !mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop ; + + // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = + mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] && + mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ; + + // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = + mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas && + mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut ; + + // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut = + !mmio_axi4_adapter_master_xactor_shim_rff_rv[72] && + mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut ; + + // rule RL_mmio_axi4_adapter_rl_handle_read_rsps + assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = + !mmio_axi4_adapter_master_xactor_clearing && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72] && + mmio_axi4_adapter_f_rsps_to_core$FULL_N ; + assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; + + // rule RL_mmio_axi4_adapter_master_xactor_do_clear + assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear = + mmio_axi4_adapter_master_xactor_clearing ; + assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear = + mmio_axi4_adapter_master_xactor_clearing ; + // rule RL_mmioPlatform_propagateTime assign CAN_FIRE_RL_mmioPlatform_propagateTime = mmioPlatform_state != 2'd0 ; assign WILL_FIRE_RL_mmioPlatform_propagateTime = @@ -3213,23 +3413,23 @@ module mkProc(CLK, // rule RL_mmioPlatform_incCycle assign CAN_FIRE_RL_mmioPlatform_incCycle = mmioPlatform_state != 2'd0 && - mmioPlatform_cycle_12_ULT_99___d313 ; + mmioPlatform_cycle_57_ULT_99___d458 ; assign WILL_FIRE_RL_mmioPlatform_incCycle = CAN_FIRE_RL_mmioPlatform_incCycle ; // rule RL_mmioPlatform_incTime assign CAN_FIRE_RL_mmioPlatform_incTime = mmioPlatform_state == 2'd1 && - !mmioPlatform_cycle_12_ULT_99___d313 ; + !mmioPlatform_cycle_57_ULT_99___d458 ; assign WILL_FIRE_RL_mmioPlatform_incTime = CAN_FIRE_RL_mmioPlatform_incTime ; // rule RL_mmioPlatform_selectReq assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335 && + NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3246,7 +3446,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418 && + IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d563 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3255,7 +3455,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461 && + IF_mmioPlatform_waitLowerMSIPCRs_98_THEN_core__ETC___d606 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3263,7 +3463,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMTimeCmp assign CAN_FIRE_RL_mmioPlatform_processMTimeCmp = - CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 && + CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q14 && mmioPlatform_curReq[66:64] == 3'd3 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMTimeCmp = @@ -3280,7 +3480,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMTime assign CAN_FIRE_RL_mmioPlatform_processMTime = - CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 && + CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q15 && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd4 ; assign WILL_FIRE_RL_mmioPlatform_processMTime = @@ -3301,7 +3501,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h40356 == 64'd0 || + x__h54059 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3319,7 +3519,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d707 ; + NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d859 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3327,14 +3527,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715 ; + NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d867 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d720 ; + NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d872 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; @@ -3342,24 +3542,24 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || + (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d730 ; + NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d882 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d921 ; + NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d1074 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d931 && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d934 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__69__ETC___d1084 && + NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d1087 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3435,70 +3635,390 @@ module mkProc(CLK, assign CAN_FIRE_RL_enqDst_1_0_canon = 1'd1 ; assign WILL_FIRE_RL_enqDst_1_0_canon = 1'd1 ; - // rule RL_propDstIdx_0_canon_1 - assign CAN_FIRE_RL_propDstIdx_0_canon_1 = 1'd1 ; - assign WILL_FIRE_RL_propDstIdx_0_canon_1 = 1'd1 ; + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay = + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + llc_mem_server_rg_cacheline_cache_dirty_delay != 10'd0 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay ; - // rule RL_propDstData_0_canon_1 - assign CAN_FIRE_RL_propDstData_0_canon_1 = 1'd1 ; - assign WILL_FIRE_RL_propDstData_0_canon_1 = 1'd1 ; + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && + !llc$dma_respSt_first[4] && + llc_mem_server_rg_cacheline_cache_state == 3'd1 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; - // rule RL_enqDst_0_canon_1 - assign CAN_FIRE_RL_enqDst_0_canon_1 = 1'd1 ; - assign WILL_FIRE_RL_enqDst_0_canon_1 = 1'd1 ; + // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = + llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && + !llc$dma_respLd_first[4] && + llc_mem_server_rg_cacheline_cache_state == 3'd2 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; - // rule RL_llc_axi4_adapter_rl_handle_read_rsps - assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = - llc_axi4_adapter_master_xactor_crg_rd_data_full && - (llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 || - llc$RDY_to_mem_rsFromM_enq && - llc_axi4_adapter_f_pending_reads$EMPTY_N) ; - assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = - CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; + // rule RL_llc_mem_server_srcPropose + assign CAN_FIRE_RL_llc_mem_server_srcPropose = + core_0$RDY_tlbToMem_memReq_first && + core_0$RDY_tlbToMem_memReq_deq && + !llc_mem_server_propDstIdx_0_rl ; + assign WILL_FIRE_RL_llc_mem_server_srcPropose = + CAN_FIRE_RL_llc_mem_server_srcPropose ; + + // rule RL_llc_mem_server_dstSelectSrc + assign CAN_FIRE_RL_llc_mem_server_dstSelectSrc = 1'd1 ; + assign WILL_FIRE_RL_llc_mem_server_dstSelectSrc = 1'd1 ; + + // rule RL_llc_mem_server_doEnq + assign CAN_FIRE_RL_llc_mem_server_doEnq = + llc_mem_server_tlbQ$FULL_N && + IF_llc_mem_server_enqDst_0_lat_0_whas__816_THE_ETC___d1821 ; + assign WILL_FIRE_RL_llc_mem_server_doEnq = + CAN_FIRE_RL_llc_mem_server_doEnq ; + + // rule RL_llc_mem_server_sendLdRespToTlb + assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = + core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_first && + llc$dma_respLd_first[4] ; + assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = + CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; + + // rule RL_llc_mem_server_sendStRespToTlb + assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && + llc$dma_respSt_first[4] ; + assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = + CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; + + // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut = + llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas && + llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut ; + + // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut = + !llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] && + llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut ; + + // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut = + llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas && + llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut ; + + // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut = + !llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] && + llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut ; + + // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut = + llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas && + llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut ; + + // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut = + !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] && + llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut ; + + // rule RL_llc_mem_server_rl_handle_MemLoader_ld_req + assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = + !llc_mem_server_axi4_slave_xactor_clearing && + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && + !llc_mem_server_axi4_slave_xactor_shim_rff_rv[73] && + (llc_mem_server_rg_cacheline_cache_state == 3'd3 || + llc_mem_server_rg_cacheline_cache_state == 3'd4) && + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d1741 ; + assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; + + // rule RL_llc_mem_server_rl_handle_MemLoader_st_req + assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = + !llc_mem_server_axi4_slave_xactor_clearing && + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[74] && + !llc_mem_server_axi4_slave_xactor_shim_bff_rv[7] && + (llc_mem_server_rg_cacheline_cache_state == 3'd3 || + llc_mem_server_rg_cacheline_cache_state == 3'd4) && + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1642 ; + assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged = + llc$RDY_dma_memReq_enq && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + llc_mem_server_rg_cacheline_cache_dirty_delay == 10'd0 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = + llc$RDY_dma_memReq_enq && + !llc_mem_server_axi4_slave_xactor_clearing && + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1642 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = + llc$RDY_dma_memReq_enq && + !llc_mem_server_axi4_slave_xactor_clearing && + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d1741 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_req_st + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = + !llc_mem_server_axi4_slave_xactor_clearing && + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && + llc$RDY_dma_memReq_enq && + llc_mem_server_rg_cacheline_cache_state == 3'd3 && + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1642 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_req_ld + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = + !llc_mem_server_axi4_slave_xactor_clearing && + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && + llc$RDY_dma_memReq_enq && + llc_mem_server_rg_cacheline_cache_state == 3'd3 && + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d1741 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; + + // rule RL_llc_mem_server_sendTlbReqToLLC + assign CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC = + llc$RDY_dma_memReq_enq && llc_mem_server_tlbQ$EMPTY_N ; + assign WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC = + CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + + // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek = + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek ; + + // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop = + llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas && + !llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop ; + + // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop = + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] && + llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop ; + + // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek = + llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek ; + + // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop = + llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas && + !llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop ; + + // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop = + llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] && + llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop ; + + // rule RL_llc_mem_server_axi4_slave_xactor_do_clear + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear = + llc_mem_server_axi4_slave_xactor_clearing ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear = + llc_mem_server_axi4_slave_xactor_clearing ; + + // rule RL_llc_mem_server_propDstIdx_0_canon + assign CAN_FIRE_RL_llc_mem_server_propDstIdx_0_canon = 1'd1 ; + assign WILL_FIRE_RL_llc_mem_server_propDstIdx_0_canon = 1'd1 ; + + // rule RL_llc_mem_server_propDstData_0_canon + assign CAN_FIRE_RL_llc_mem_server_propDstData_0_canon = 1'd1 ; + assign WILL_FIRE_RL_llc_mem_server_propDstData_0_canon = 1'd1 ; + + // rule RL_llc_mem_server_enqDst_0_canon + assign CAN_FIRE_RL_llc_mem_server_enqDst_0_canon = 1'd1 ; + assign WILL_FIRE_RL_llc_mem_server_enqDst_0_canon = 1'd1 ; // rule RL_llc_axi4_adapter_rl_handle_write_req assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req = - !llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read && - !llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read && + !llc_axi4_adapter_master_xactor_clearing && llc$RDY_to_mem_toM_first && + !llc_axi4_adapter_master_xactor_shim_wff_rv[74] && (llc_axi4_adapter_rg_wr_req_beat != 3'd0 || - llc_axi4_adapter_f_pending_writes$FULL_N) && + !llc_axi4_adapter_master_xactor_shim_awff_rv[98]) && (llc_axi4_adapter_rg_wr_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && - llc$to_mem_toM_first[640] ; + llc$to_mem_toM_first[644] ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // rule RL_llc_axi4_adapter_rl_handle_read_req assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = - !llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read && + !llc_axi4_adapter_master_xactor_clearing && + llc$RDY_to_mem_toM_deq && llc$RDY_to_mem_toM_first && - (llc_axi4_adapter_rg_rd_req_beat != 3'd0 || - llc_axi4_adapter_f_pending_reads$FULL_N) && - (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || - llc$RDY_to_mem_toM_deq) && - !llc$to_mem_toM_first[640] && - b__h110741 == 4'd0 ; + !llc_axi4_adapter_master_xactor_shim_arff_rv[98] && + llc_axi4_adapter_f_pending_reads$FULL_N && + !llc$to_mem_toM_first[644] && + b__h167647 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; + // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = + llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; + + // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = + llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas && + !llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop ; + + // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = + llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] && + llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ; + + // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek = + llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; + + // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = + llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas && + !llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop ; + + // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop = + llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && + llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop ; + + // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = + llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas && + llc_axi4_adapter_master_xactor_shim_bff_rv[7] ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut ; + + // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut = + !llc_axi4_adapter_master_xactor_shim_bff_rv[7] && + llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut ; + // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h110741 != 4'd0 && - llc_axi4_adapter_master_xactor_crg_wr_resp_full && - (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || - llc_axi4_adapter_f_pending_writes$EMPTY_N) ; + !llc_axi4_adapter_master_xactor_clearing && + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[7] && + b__h167647 != 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; + // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = + llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; + + // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = + llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas && + !llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop ; + + // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = + llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] && + llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ; + + // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = + llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas && + llc_axi4_adapter_master_xactor_shim_rff_rv[73] ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut ; + + // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut = + !llc_axi4_adapter_master_xactor_shim_rff_rv[73] && + llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut ; + + // rule RL_llc_axi4_adapter_rl_handle_read_rsps + assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = + !llc_axi4_adapter_master_xactor_clearing && + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d1957 ; + assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = + CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; + + // rule RL_llc_axi4_adapter_master_xactor_do_clear + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear = + llc_axi4_adapter_master_xactor_clearing ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear = + llc_axi4_adapter_master_xactor_clearing ; // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 ; + mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -3506,26 +4026,36 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 ; + NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d694 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d758 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 ; + mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d573 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 ; + mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d680 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 ; + mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d746 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 || - !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = + (!mmioPlatform_fetchingWay_079_ULT_mmioPlatform__ETC___d1089 || + !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ; + assign MUX_llc$dma_memReq_enq_1__SEL_1 = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; + assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; assign MUX_mmioPlatform_amoResp$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -3537,12 +4067,12 @@ module mkProc(CLK, assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || @@ -3560,120 +4090,179 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && - mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ; + mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ; + assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1 = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req || + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1 = + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1 && + !mmio_axi4_adapter_soc_map$m_is_IO_addr ; + assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] == 2'b0 ; + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == + 2'd0 ; assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 = - { 1'd0, llc$to_child_toC_first[582:1] } ; + { 1'd0, llc$to_child_toC_first[586:1] } ; assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 = { 1'd1, - llc$to_child_toC_first[582:517], - llc$to_child_toC_first[515:0] } ; + llc$to_child_toC_first[586:521], + llc$to_child_toC_first[519:0] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442, + IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d587, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h28028 } ; + x_data__h35020 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1 = - { mmioPlatform_reqFunc[5:4] != 2'd0, - (mmioPlatform_reqFunc[5:4] == 2'd0) ? - 66'h155555554AAAAAAAA : - 66'h0AAAAAAAAAAAAAAAA } ; + (mmioPlatform_reqFunc[5:4] == 2'd0) ? + 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : + 131'h4AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2 = - { mmioPlatform_reqFunc[5:4] != 2'd0, - (mmioPlatform_reqFunc[5:4] == 2'd0) ? - 66'h155555554AAAAAAAA : - { 2'h1, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539 } } ; + (mmioPlatform_reqFunc[5:4] == 2'd0) ? + 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : + { 67'h60000000000000000, + IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_1_ETC___d687 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 = - { mmioPlatform_reqFunc[5:4] != 2'd0, - (mmioPlatform_reqFunc[5:4] == 2'd0) ? - 66'h155555554AAAAAAAA : - { 2'h1, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603 } } ; + (mmioPlatform_reqFunc[5:4] == 2'd0) ? + 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : + { 67'h60000000000000000, + IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_1_ETC___d752 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = - { 1'd0, - mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && + { 65'h0AAAAAAAAAAAAAAAA, + mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944, - mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1099, + mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmioPlatform_fetchingWay, - IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d952 } ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__69__ETC___d1106 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = - { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29445 } ; + { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = + { 2'd3, mmioPlatform_amoResp } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = - { mmioPlatform_reqFunc[5:4] != 2'd0, - (mmioPlatform_reqFunc[5:4] == 2'd0) ? - 66'h155555554AAAAAAAA : - DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645 } ; + { 67'h60000000000000000, + mmioPlatform_waitLowerMSIPCRs ? + { 63'd0, core_0$mmioToPlatform_cRs_first } : + { v__h37337, 32'd0 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? - 66'h155555554AAAAAAAA : - { 1'h0, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d684 } } ; + 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : + { (mmioPlatform_reqFunc[5:4] == 2'd2) ? + mmioPlatform_toHostQ_empty : + mmioPlatform_reqFunc[5:4] == 2'd1, + 65'd0, + mmioPlatform_toHostQ_empty ? + 64'd0 : + mmioPlatform_toHostQ_data_0 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = - { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; + { mmioPlatform_reqFunc[5:4] != 2'd0, + (mmioPlatform_reqFunc[5:4] == 2'd0) ? + 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : + { IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_2_ETC___d832, + 65'd0, + mmioPlatform_fromHostQ_empty ? + 64'd0 : + mmioPlatform_fromHostQ_data_0 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = - { 2'd2, - mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] } : - mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; + mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? + { 2'd3, mmio_axi4_adapter_f_rsps_to_core$D_OUT[128:0] } : + { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; + assign MUX_llc$dma_memReq_enq_1__VAL_1 = + { llc_mem_server_rg_cacheline_cache_addr, + 64'hFFFFFFFFFFFFFFFF, + llc_mem_server_rg_cacheline_cache_data, + 5'd10 } ; + assign MUX_llc$dma_memReq_enq_1__VAL_2 = + { line_addr__h114500, + 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; + assign MUX_llc$dma_memReq_enq_1__VAL_3 = + { line_addr__h124608, + 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; + assign MUX_llc$dma_memReq_enq_1__VAL_4 = + { llc_mem_server_tlbQ$D_OUT[64:1], + 581'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555, + llc_mem_server_tlbQ$D_OUT[0], + llc_mem_server_tlbQ$D_OUT[6:4] } ; + assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = + { llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] != + 2'd3 && + llc_mem_server_rg_cacheline_cache_data[515], + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] != + 2'd2 && + llc_mem_server_rg_cacheline_cache_data[514], + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] != + 2'd1 && + llc_mem_server_rg_cacheline_cache_data[513], + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] != + 2'd0 && + llc_mem_server_rg_cacheline_cache_data[512], + IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d1725, + (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == + 3'd1) ? + data__h115067 : + llc_mem_server_rg_cacheline_cache_data[127:64], + (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == + 3'd0) ? + data__h115067 : + llc_mem_server_rg_cacheline_cache_data[63:0] } ; + assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = + llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_1 = - (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? - mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 ; + { 65'd0, + (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? + mmioPlatform_mtimecmp_0 : + IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d686 } ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = - (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? - mmioPlatform_mtime : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 ; + { 65'd0, + (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? + mmioPlatform_mtime : + IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d751 } ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) ? + mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) ? 67'h1AAAAAAAAAAAAAAAA : - ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd33554432 && - core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554433) ? + ((core_0$mmioToPlatform_cRq_first[214:154] >= 61'd33554432 && + core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554433) ? 67'h2AAAAAAAAAAAAAAAA : - ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd33556480 && - core_0$mmioToPlatform_cRq_first[141:81] < 61'd33556481) ? + ((core_0$mmioToPlatform_cRq_first[214:154] >= + 61'd33556480 && + core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556481) ? 67'h3AAAAAAAAAAAAAAAA : - ((core_0$mmioToPlatform_cRq_first[141:81] == + ((core_0$mmioToPlatform_cRq_first[214:154] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366))) ; + IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511))) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, - mmioPlatform_instSel ? + (mmioPlatform_instSel == 2'd3) ? mmioPlatform_curReq[63:0] + 64'd8 : mmioPlatform_curReq[63:0] } ; assign MUX_mmioPlatform_cycle$write_1__VAL_1 = mmioPlatform_cycle + 7'd1 ; assign MUX_mmioPlatform_fetchingWay$write_1__VAL_2 = mmioPlatform_fetchingWay + 1'd1 ; assign MUX_mmioPlatform_instSel$write_1__VAL_2 = - mmioPlatform_instSel + 1'd1 ; + mmioPlatform_instSel + 2'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) ? + mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_2 = @@ -3684,254 +4273,494 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 or + IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_3 = - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 or + mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end assign MUX_mmioPlatform_state$write_1__VAL_5 = - mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - (mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 ? + mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? + (mmioPlatform_fetchingWay_079_ULT_mmioPlatform__ETC___d1089 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h45352 } ; + 65'd0, + IF_mmioPlatform_reqSz_87_EQ_0b0_88_THEN_IF_mmi_ETC___d1070 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442, + IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d587, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = - { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; + { mmioPlatform_curReq[63:0], + 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h47464, 78'h1AAAAAAAAAAAAAAAAAAA } ; - assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = - { mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] == 2'b0, - mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; + { addr1__h66416, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = + { 66'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] } ; + assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = + { mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == + 2'd0, + 1'd0, + _0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213 } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40356 } ; + assign mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget = + { master1_bid, master1_bresp } ; + assign mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas = + master1_bvalid && + !mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ; + assign mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget = + { master1_rid, + master1_rdata, + master1_rresp, + master1_rlast, + master1_ruser } ; + assign mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas = + master1_rvalid && + !mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h54059 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h40356 != 64'd0 ; + x__h54059 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38336 == 64'd0 ; - assign propDstIdx_0_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_ETC___d1126 ; + x__h51369 == 64'd0 ; assign propDstIdx_1_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 && - x__h58756 ; + !enqDst_0_rl[73] && + SEL_ARR_IF_propDstIdx_0_lat_0_whas__121_THEN_p_ETC___d1189 && + x__h75250 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x8756_0_n__read_addr8938_1_n__read_addr90_ETC__q15, - SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121 } ; - assign propDstIdx_1_0_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_A_ETC___d1423 ; + CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q22, + SEL_ARR_IF_propDstData_0_lat_0_whas__135_THEN__ETC___d1241 } ; + assign enqDst_0_lat_0$whas = + !enqDst_0_rl[73] && + SEL_ARR_IF_propDstIdx_0_lat_0_whas__121_THEN_p_ETC___d1189 ; assign propDstIdx_1_1_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 && - x__h77379 ; + !enqDst_1_0_rl[584] && + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__254_THEN_ETC___d1422 && + x__h97352 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x7379_0_n__read_addr7557_1_n__read_addr76_ETC__q26, - SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418 } ; - assign enqDst_0_lat_0_1$wget = - { 1'd1, n__read_snd_addr__h91728, n__read_snd_id__h91729 } ; - assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = - mmio_axi4_adapter_master_xactor_crg_wr_addr_full && + CASE_x7352_0_IF_propDstData_1_0_lat_0_whas__26_ETC__q37, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1538 } ; + assign enqDst_1_0_lat_0$whas = + !enqDst_1_0_rl[584] && + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__254_THEN_ETC___d1422 ; + assign llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget = + { debug_module_mem_server_awid, + debug_module_mem_server_awaddr, + debug_module_mem_server_awlen, + debug_module_mem_server_awsize, + debug_module_mem_server_awburst, + debug_module_mem_server_awlock, + debug_module_mem_server_awcache, + debug_module_mem_server_awprot, + debug_module_mem_server_awqos, + debug_module_mem_server_awregion } ; + assign llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas = + debug_module_mem_server_awvalid && + !llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] ; + assign llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget = + { debug_module_mem_server_wdata, + debug_module_mem_server_wstrb, + debug_module_mem_server_wlast, + debug_module_mem_server_wuser } ; + assign llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas = + debug_module_mem_server_wvalid && + !llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] ; + assign llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget = + { debug_module_mem_server_arid, + debug_module_mem_server_araddr, + debug_module_mem_server_arlen, + debug_module_mem_server_arsize, + debug_module_mem_server_arburst, + debug_module_mem_server_arlock, + debug_module_mem_server_arcache, + debug_module_mem_server_arprot, + debug_module_mem_server_arqos, + debug_module_mem_server_arregion } ; + assign llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas = + debug_module_mem_server_arvalid && + !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; + assign llc_mem_server_propDstIdx_0_lat_1$whas = + !llc_mem_server_enqDst_0_rl[65] && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__801_ETC___d1804 ; + assign llc_mem_server_enqDst_0_lat_0$wget = + { 1'd1, + IF_llc_mem_server_propDstData_0_lat_0_whas__80_ETC___d1811 } ; + assign llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget = + { master0_bid, master0_bresp } ; + assign llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas = + master0_bvalid && + !llc_axi4_adapter_master_xactor_shim_bff_rv[7] ; + assign llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget = + { master0_rid, + master0_rdata, + master0_rresp, + master0_rlast, + master0_ruser } ; + assign llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas = + master0_rvalid && + !llc_axi4_adapter_master_xactor_shim_rff_rv[73] ; + assign mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas = + mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] && master1_awready ; - assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read = - !mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write && - mmio_axi4_adapter_master_xactor_crg_wr_addr_full ; - assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req || - mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read ; - assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write = - mmio_axi4_adapter_master_xactor_crg_wr_data_full && + assign mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas = + mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && master1_wready ; - assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read = - !mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write && - mmio_axi4_adapter_master_xactor_crg_wr_data_full ; - assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$port3__read = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req || - mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read ; - assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read = - !WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_crg_wr_resp_full ; - assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write = - master1_bvalid && - !mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; - assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read = - mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write || - mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; - assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write = - mmio_axi4_adapter_master_xactor_crg_rd_addr_full && + assign mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas = + mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] && master1_arready ; - assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read = - !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write && - mmio_axi4_adapter_master_xactor_crg_rd_addr_full ; - assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req || - mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read ; - assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read = - !CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_master_xactor_crg_rd_data_full ; - assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write = - master1_rvalid && - !mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ; - assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$port3__read = - mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write || - mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ; + assign llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas = + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] && + debug_module_mem_server_bready ; + assign llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas = + llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] && + debug_module_mem_server_rready ; + assign llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas = + llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] && + master0_awready ; + assign llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas = + llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && + master0_wready ; + assign llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas = + llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] && + master0_arready ; + assign mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; + assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 = + { 5'd16, + mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], + 8'd0, + v_awsize_val__h15184, + 18'd65536 } ; + assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read = + mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write ? + mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 : + mmio_axi4_adapter_master_xactor_shim_awff_rv ; + assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read ; + assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read = + mmio_axi4_adapter_master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read ; + assign mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; + assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, + mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], + mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129], + 2'd2 } ; + assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read = + mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write ? + mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 : + mmio_axi4_adapter_master_xactor_shim_wff_rv ; + assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop ? + 75'h2AAAAAAAAAAAAAAAAAA : + mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read ; + assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read = + mmio_axi4_adapter_master_xactor_clearing ? + 75'h2AAAAAAAAAAAAAAAAAA : + mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read ; + assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, + mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget } ; + assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut ? + mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 : + mmio_axi4_adapter_master_xactor_shim_bff_rv ; + assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read = + WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? + 7'd42 : + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read ; + assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read = + mmio_axi4_adapter_master_xactor_clearing ? + 7'd42 : + mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read ; + assign mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; + assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 = + { 5'd16, + mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], + 29'd851968 } ; + assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read = + mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write ? + mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 : + mmio_axi4_adapter_master_xactor_shim_arff_rv ; + assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read ; + assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read = + mmio_axi4_adapter_master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read ; + assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, + mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget } ; + assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut ? + mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 : + mmio_axi4_adapter_master_xactor_shim_rff_rv ; + assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ? + 73'h0AAAAAAAAAAAAAAAAAA : + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read ; + assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read = + mmio_axi4_adapter_master_xactor_clearing ? + 73'h0AAAAAAAAAAAAAAAAAA : + mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read ; + assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2368 - 4'd1 ; + b__h4255 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2368 ; - assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - CAN_FIRE_RL_rl_reset ? - 4'd0 : - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; - assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = - llc_axi4_adapter_master_xactor_crg_wr_addr_full && - master0_awready ; - assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read = - !llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write && - llc_axi4_adapter_master_xactor_crg_wr_addr_full ; - assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read = - CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req || - llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read ; - assign llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write = - llc_axi4_adapter_master_xactor_crg_wr_data_full && - master0_wready ; - assign llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read = - !llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write && - llc_axi4_adapter_master_xactor_crg_wr_data_full ; - assign llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read = - CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req || - llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read ; - assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read = - !CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - llc_axi4_adapter_master_xactor_crg_wr_resp_full ; - assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write = - master0_bvalid && - !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; - assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read = - llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write || - llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; - assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write = - llc_axi4_adapter_master_xactor_crg_rd_addr_full && - master0_arready ; - assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read = - !llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write && - llc_axi4_adapter_master_xactor_crg_rd_addr_full ; - assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read = - CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req || - llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read ; - assign llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read = - !CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_crg_rd_data_full ; - assign llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write = - master0_rvalid && - !llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ; - assign llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read = - llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write || - llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ; + b__h4255 ; + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port0__write_1 = + { 1'd1, + llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget } ; + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut ? + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port0__write_1 : + llc_mem_server_axi4_slave_xactor_shim_awff_rv ; + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read ; + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port3__read = + llc_mem_server_axi4_slave_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read ; + assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, + llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget } ; + assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut ? + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1 : + llc_mem_server_axi4_slave_xactor_shim_wff_rv ; + assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? + 75'h2AAAAAAAAAAAAAAAAAA : + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read ; + assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port3__read = + llc_mem_server_axi4_slave_xactor_clearing ? + 75'h2AAAAAAAAAAAAAAAAAA : + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read ; + assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? + 8'd128 : + llc_mem_server_axi4_slave_xactor_shim_bff_rv ; + assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop ? + 8'd42 : + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read ; + assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port3__read = + llc_mem_server_axi4_slave_xactor_clearing ? + 8'd42 : + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read ; + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port0__write_1 = + { 1'd1, + llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget } ; + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut ? + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port0__write_1 : + llc_mem_server_axi4_slave_xactor_shim_arff_rv ; + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read ; + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port3__read = + llc_mem_server_axi4_slave_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port2__read ; + assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1 = + { 6'd32, dword__h124791, 4'd2 } ; + assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ? + llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1 : + llc_mem_server_axi4_slave_xactor_shim_rff_rv ; + assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port2__read = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop ? + 74'h0AAAAAAAAAAAAAAAAAA : + llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read ; + assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port3__read = + llc_mem_server_axi4_slave_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + llc_mem_server_axi4_slave_xactor_shim_rff_rv$port2__read ; + assign llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write = + WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_rg_wr_req_beat == 3'd0 ; + assign llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 = + { 6'd32, v_awaddr__h189347, 29'd15532032 } ; + assign llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read = + llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write ? + llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 : + llc_axi4_adapter_master_xactor_shim_awff_rv ; + assign llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read ; + assign llc_axi4_adapter_master_xactor_shim_awff_rv$port3__read = + llc_axi4_adapter_master_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read ; + assign llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, + v_wdata__h189758, + v_wstrb__h189759, + llc_axi4_adapter_rg_wr_req_beat == 3'd7, + v_wuser__h189761 } ; + assign llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? + llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 : + llc_axi4_adapter_master_xactor_shim_wff_rv ; + assign llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop ? + 75'h2AAAAAAAAAAAAAAAAAA : + llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read ; + assign llc_axi4_adapter_master_xactor_shim_wff_rv$port3__read = + llc_axi4_adapter_master_xactor_clearing ? + 75'h2AAAAAAAAAAAAAAAAAA : + llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read ; + assign llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, + llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget } ; + assign llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut ? + llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 : + llc_axi4_adapter_master_xactor_shim_bff_rv ; + assign llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? + 8'd42 : + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read ; + assign llc_axi4_adapter_master_xactor_shim_bff_rv$port3__read = + llc_axi4_adapter_master_xactor_clearing ? + 8'd42 : + llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read ; + assign llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 = + { 6'd32, line_addr__h167856, 29'd15532032 } ; + assign llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read = + CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ? + llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 : + llc_axi4_adapter_master_xactor_shim_arff_rv ; + assign llc_axi4_adapter_master_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read ; + assign llc_axi4_adapter_master_xactor_shim_arff_rv$port3__read = + llc_axi4_adapter_master_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + llc_axi4_adapter_master_xactor_shim_arff_rv$port2__read ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, + llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget } ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut ? + llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 : + llc_axi4_adapter_master_xactor_shim_rff_rv ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv$port2__read = + CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ? + 74'h0AAAAAAAAAAAAAAAAAA : + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv$port3__read = + llc_axi4_adapter_master_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + llc_axi4_adapter_master_xactor_shim_rff_rv$port2__read ; + assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write = + WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_rg_wr_req_beat == 3'd0 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h110741 - 4'd1 ; + b__h167647 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h110741 ; - assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - CAN_FIRE_RL_rl_reset ? - 4'd0 : - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; + b__h167647 ; // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; + assign cfg_verbosity$D_IN = + EN_hart0_put_other_req_put ? + hart0_put_other_req_put : + set_verbosity_verbosity ; + assign cfg_verbosity$EN = EN_hart0_put_other_req_put || EN_set_verbosity ; // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__95_THEN_enqDst_0_lat_0_ETC___d1000, + IF_enqDst_0_lat_0_whas__150_THEN_enqDst_0_lat__ETC___d1155, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ? + (enqDst_0_lat_0$whas ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0]) } ; assign enqDst_0_rl$EN = 1'd1 ; - // register enqDst_0_rl_1 - assign enqDst_0_rl_1$D_IN = - { !CAN_FIRE_RL_doEnq_2 && - IF_enqDst_0_lat_0_1_whas__482_THEN_enqDst_0_la_ETC___d1487, - CAN_FIRE_RL_doEnq_2 ? - 65'h0AAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_1_read__513_514_OR_NOT_e_ETC___d1520 ? - enqDst_0_lat_0_1$wget[64:0] : - enqDst_0_rl_1[64:0]) } ; - assign enqDst_0_rl_1$EN = 1'd1 ; - // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1231, - IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1270 } ; + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1350, + IF_enqDst_1_0_lat_1_whas__342_THEN_enqDst_1_0__ETC___d1389 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -3940,74 +4769,48 @@ module mkProc(CLK, // register llc_axi4_adapter_ctr_wr_rsps_pending_crg assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN = - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read ; + llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ; - // register llc_axi4_adapter_master_xactor_crg_rd_addr_full - assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN = - llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read ; - assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN = 1'b1 ; + // register llc_axi4_adapter_master_xactor_clearing + assign llc_axi4_adapter_master_xactor_clearing$D_IN = 1'd0 ; + assign llc_axi4_adapter_master_xactor_clearing$EN = + llc_axi4_adapter_master_xactor_clearing ; - // register llc_axi4_adapter_master_xactor_crg_rd_data_full - assign llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN = - llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read ; - assign llc_axi4_adapter_master_xactor_crg_rd_data_full$EN = 1'b1 ; + // register llc_axi4_adapter_master_xactor_shim_arff_rv + assign llc_axi4_adapter_master_xactor_shim_arff_rv$D_IN = + llc_axi4_adapter_master_xactor_shim_arff_rv$port3__read ; + assign llc_axi4_adapter_master_xactor_shim_arff_rv$EN = 1'b1 ; - // register llc_axi4_adapter_master_xactor_crg_wr_addr_full - assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN = - llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read ; - assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN = 1'b1 ; + // register llc_axi4_adapter_master_xactor_shim_awff_rv + assign llc_axi4_adapter_master_xactor_shim_awff_rv$D_IN = + llc_axi4_adapter_master_xactor_shim_awff_rv$port3__read ; + assign llc_axi4_adapter_master_xactor_shim_awff_rv$EN = 1'b1 ; - // register llc_axi4_adapter_master_xactor_crg_wr_data_full - assign llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN = - llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read ; - assign llc_axi4_adapter_master_xactor_crg_wr_data_full$EN = 1'b1 ; + // register llc_axi4_adapter_master_xactor_shim_bff_rv + assign llc_axi4_adapter_master_xactor_shim_bff_rv$D_IN = + llc_axi4_adapter_master_xactor_shim_bff_rv$port3__read ; + assign llc_axi4_adapter_master_xactor_shim_bff_rv$EN = 1'b1 ; - // register llc_axi4_adapter_master_xactor_crg_wr_resp_full - assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN = - llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read ; - assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN = 1'b1 ; + // register llc_axi4_adapter_master_xactor_shim_rff_rv + assign llc_axi4_adapter_master_xactor_shim_rff_rv$D_IN = + llc_axi4_adapter_master_xactor_shim_rff_rv$port3__read ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv$EN = 1'b1 ; - // register llc_axi4_adapter_master_xactor_rg_rd_addr - assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h111034, 29'd851968 } ; - assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = - CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; - - // register llc_axi4_adapter_master_xactor_rg_rd_data - assign llc_axi4_adapter_master_xactor_rg_rd_data$D_IN = - { master0_rid, master0_rdata, master0_rresp, master0_rlast } ; - assign llc_axi4_adapter_master_xactor_rg_rd_data$EN = 1'd1 ; - - // register llc_axi4_adapter_master_xactor_rg_wr_addr - assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h124958, 29'd851968 } ; - assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = - CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; - - // register llc_axi4_adapter_master_xactor_rg_wr_data - assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, data64__h124873, strb8__h124874, 1'd1 } ; - assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = - CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; - - // register llc_axi4_adapter_master_xactor_rg_wr_resp - assign llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN = - { master0_bid, master0_bresp } ; - assign llc_axi4_adapter_master_xactor_rg_wr_resp$EN = - master0_bvalid && - !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; + // register llc_axi4_adapter_master_xactor_shim_wff_rv + assign llc_axi4_adapter_master_xactor_shim_wff_rv$D_IN = + llc_axi4_adapter_master_xactor_shim_wff_rv$port3__read ; + assign llc_axi4_adapter_master_xactor_shim_wff_rv$EN = 1'b1 ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h111736 ; + assign llc_axi4_adapter_rg_cline$D_IN = + IF_llc_axi4_adapter_rg_rd_rsp_beat_950_BIT_0_9_ETC___d1992 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; // register llc_axi4_adapter_rg_rd_req_beat - assign llc_axi4_adapter_rg_rd_req_beat$D_IN = - llc_axi4_adapter_rg_rd_req_beat + 3'd1 ; - assign llc_axi4_adapter_rg_rd_req_beat$EN = - CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; + assign llc_axi4_adapter_rg_rd_req_beat$D_IN = 3'h0 ; + assign llc_axi4_adapter_rg_rd_req_beat$EN = 1'b0 ; // register llc_axi4_adapter_rg_rd_rsp_beat assign llc_axi4_adapter_rg_rd_rsp_beat$D_IN = @@ -4021,11 +4824,113 @@ module mkProc(CLK, assign llc_axi4_adapter_rg_wr_req_beat$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; - // register llc_axi4_adapter_rg_wr_rsp_beat - assign llc_axi4_adapter_rg_wr_rsp_beat$D_IN = - llc_axi4_adapter_rg_wr_rsp_beat + 3'd1 ; - assign llc_axi4_adapter_rg_wr_rsp_beat$EN = - CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; + // register llc_mem_server_axi4_slave_xactor_clearing + assign llc_mem_server_axi4_slave_xactor_clearing$D_IN = 1'd0 ; + assign llc_mem_server_axi4_slave_xactor_clearing$EN = + llc_mem_server_axi4_slave_xactor_clearing ; + + // register llc_mem_server_axi4_slave_xactor_shim_arff_rv + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$D_IN = + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port3__read ; + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$EN = 1'b1 ; + + // register llc_mem_server_axi4_slave_xactor_shim_awff_rv + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$D_IN = + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port3__read ; + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$EN = 1'b1 ; + + // register llc_mem_server_axi4_slave_xactor_shim_bff_rv + assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$D_IN = + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port3__read ; + assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$EN = 1'b1 ; + + // register llc_mem_server_axi4_slave_xactor_shim_rff_rv + assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$D_IN = + llc_mem_server_axi4_slave_xactor_shim_rff_rv$port3__read ; + assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$EN = 1'b1 ; + + // register llc_mem_server_axi4_slave_xactor_shim_wff_rv + assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$D_IN = + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port3__read ; + assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$EN = 1'b1 ; + + // register llc_mem_server_enqDst_0_rl + assign llc_mem_server_enqDst_0_rl$D_IN = + { !CAN_FIRE_RL_llc_mem_server_doEnq && + IF_llc_mem_server_enqDst_0_lat_0_whas__816_THE_ETC___d1821, + CAN_FIRE_RL_llc_mem_server_doEnq ? + 65'h0AAAAAAAAAAAAAAAA : + (llc_mem_server_propDstIdx_0_lat_1$whas ? + llc_mem_server_enqDst_0_lat_0$wget[64:0] : + llc_mem_server_enqDst_0_rl[64:0]) } ; + assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; + + // register llc_mem_server_propDstData_0_rl + assign llc_mem_server_propDstData_0_rl$D_IN = + IF_llc_mem_server_propDstData_0_lat_0_whas__80_ETC___d1811 ; + assign llc_mem_server_propDstData_0_rl$EN = 1'd1 ; + + // register llc_mem_server_propDstIdx_0_rl + assign llc_mem_server_propDstIdx_0_rl$D_IN = + !llc_mem_server_propDstIdx_0_lat_1$whas && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__801_ETC___d1804 ; + assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; + + // register llc_mem_server_rg_cacheline_cache_addr + assign llc_mem_server_rg_cacheline_cache_addr$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? + line_addr__h114500 : + line_addr__h124608 ; + assign llc_mem_server_rg_cacheline_cache_addr$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; + + // register llc_mem_server_rg_cacheline_cache_data + assign llc_mem_server_rg_cacheline_cache_data$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? + MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 : + llc$dma_respLd_first[520:5] ; + assign llc_mem_server_rg_cacheline_cache_data$EN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; + + // register llc_mem_server_rg_cacheline_cache_dirty_delay + assign llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? + 10'd1023 : + MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 ; + assign llc_mem_server_rg_cacheline_cache_dirty_delay$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay || + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // register llc_mem_server_rg_cacheline_cache_state + always@(MUX_llc$dma_memReq_enq_1__SEL_1 or + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 or + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 or + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req) + begin + case (1'b1) // synopsys parallel_case + MUX_llc$dma_memReq_enq_1__SEL_1: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd1; + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd2; + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd3; + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd4; + default: llc_mem_server_rg_cacheline_cache_state$D_IN = + 3'b010 /* unspecified value */ ; + endcase + end + assign llc_mem_server_rg_cacheline_cache_state$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish || + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; // register mmioPlatform_amoResp assign mmioPlatform_amoResp$D_IN = @@ -4048,8 +4953,8 @@ module mkProc(CLK, assign mmioPlatform_curReq$EN = MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 ; + mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && + mmioPlatform_fetchingWay_079_ULT_mmioPlatform__ETC___d1089 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4062,11 +4967,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1099 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 && + mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && + mmioPlatform_fetchingWay_079_ULT_mmioPlatform__ETC___d1089 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4076,11 +4981,11 @@ module mkProc(CLK, assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 ; + mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && + mmioPlatform_fetchingWay_079_ULT_mmioPlatform__ETC___d1089 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4094,8 +4999,7 @@ module mkProc(CLK, assign mmioPlatform_fromHostQ_data_0$D_IN = mmioPlatform_fromHostQ_enqReq_rl[63:0] ; assign mmioPlatform_fromHostQ_data_0$EN = - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 && - mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && + !mmioPlatform_fromHostQ_clearReq_rl && mmioPlatform_fromHostQ_enqReq_rl[64] ; // register mmioPlatform_fromHostQ_deqReq_rl @@ -4104,9 +5008,11 @@ module mkProc(CLK, // register mmioPlatform_fromHostQ_empty assign mmioPlatform_fromHostQ_empty$D_IN = - mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT && mmioPlatform_fromHostQ_clearReq_rl || - NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304 ; + !mmioPlatform_fromHostQ_enqReq_rl[64] && + (mmioPlatform_fromHostQ_deqReq_lat_0$whas || + mmioPlatform_fromHostQ_deqReq_rl || + mmioPlatform_fromHostQ_empty) ; assign mmioPlatform_fromHostQ_empty$EN = 1'd1 ; // register mmioPlatform_fromHostQ_enqReq_rl @@ -4115,28 +5021,31 @@ module mkProc(CLK, // register mmioPlatform_fromHostQ_full assign mmioPlatform_fromHostQ_full$D_IN = - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 && - mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296 ; + !mmioPlatform_fromHostQ_clearReq_rl && + (mmioPlatform_fromHostQ_enqReq_rl[64] || + !mmioPlatform_fromHostQ_deqReq_lat_0$whas && + !mmioPlatform_fromHostQ_deqReq_rl && + mmioPlatform_fromHostQ_full) ; assign mmioPlatform_fromHostQ_full$EN = 1'd1 ; // register mmioPlatform_instSel assign mmioPlatform_instSel$D_IN = MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ? - core_0$mmioToPlatform_cRq_first[80] : + core_0$mmioToPlatform_cRq_first[154:153] : MUX_mmioPlatform_instSel$write_1__VAL_2 ; assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 ; + mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && + mmioPlatform_fetchingWay_079_ULT_mmioPlatform__ETC___d1089 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h32456 : + newData__h42646 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4145,7 +5054,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h29526 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h37921 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4155,38 +5064,39 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 ; + NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d694 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = - (core_0$mmioToPlatform_cRq_first[77:76] != 2'd0 && - core_0$mmioToPlatform_cRq_first[77:76] != 2'd1 && - core_0$mmioToPlatform_cRq_first[77:76] != 2'd2) ? - core_0$mmioToPlatform_cRq_first[75:72] : + (core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && + core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && + core_0$mmioToPlatform_cRq_first[150:149] != 2'd2) ? + core_0$mmioToPlatform_cRq_first[148:145] : 4'd9 ; assign mmioPlatform_reqAmofunc$EN = MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; // register mmioPlatform_reqBE - assign mmioPlatform_reqBE$D_IN = core_0$mmioToPlatform_cRq_first[71:64] ; + assign mmioPlatform_reqBE$D_IN = core_0$mmioToPlatform_cRq_first[144:129] ; assign mmioPlatform_reqBE$EN = MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; // register mmioPlatform_reqData - assign mmioPlatform_reqData$D_IN = core_0$mmioToPlatform_cRq_first[63:0] ; + assign mmioPlatform_reqData$D_IN = core_0$mmioToPlatform_cRq_first[128:0] ; assign mmioPlatform_reqData$EN = MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; // register mmioPlatform_reqFunc always@(core_0$mmioToPlatform_cRq_first) begin - case (core_0$mmioToPlatform_cRq_first[77:76]) + case (core_0$mmioToPlatform_cRq_first[150:149]) 2'd0, 2'd1, 2'd2: - mmioPlatform_reqFunc$D_IN = core_0$mmioToPlatform_cRq_first[77:72]; + mmioPlatform_reqFunc$D_IN = + core_0$mmioToPlatform_cRq_first[150:145]; 2'd3: mmioPlatform_reqFunc$D_IN = - { 2'd3, core_0$mmioToPlatform_cRq_first[75:72] }; + { 2'd3, core_0$mmioToPlatform_cRq_first[148:145] }; endcase end assign mmioPlatform_reqFunc$EN = @@ -4259,9 +5169,8 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_lat_0$wget[63:0] : mmioPlatform_toHostQ_enqReq_rl[63:0] ; assign mmioPlatform_toHostQ_data_0$EN = - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 && - mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 ; + !mmioPlatform_toHostQ_clearReq_rl && + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 ; // register mmioPlatform_toHostQ_deqReq_rl assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ; @@ -4269,9 +5178,10 @@ module mkProc(CLK, // register mmioPlatform_toHostQ_empty assign mmioPlatform_toHostQ_empty$D_IN = - mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT && mmioPlatform_toHostQ_clearReq_rl || - NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226 ; + (mmioPlatform_toHostQ_enqReq_lat_0$whas ? + !mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : + !mmioPlatform_toHostQ_enqReq_rl[64]) ; assign mmioPlatform_toHostQ_empty$EN = 1'd1 ; // register mmioPlatform_toHostQ_enqReq_rl @@ -4280,8 +5190,11 @@ module mkProc(CLK, // register mmioPlatform_toHostQ_full assign mmioPlatform_toHostQ_full$D_IN = - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 && - mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218 ; + !mmioPlatform_toHostQ_clearReq_rl && + (IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 || + !(!mmioPlatform_toHostQ_empty) && + !mmioPlatform_toHostQ_deqReq_rl && + mmioPlatform_toHostQ_full) ; assign mmioPlatform_toHostQ_full$EN = 1'd1 ; // register mmioPlatform_waitLowerMSIPCRs @@ -4291,7 +5204,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 ; + NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d596 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -4299,15 +5212,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d758 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 ; + NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d596 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -4315,70 +5228,45 @@ module mkProc(CLK, // register mmio_axi4_adapter_ctr_wr_rsps_pending_crg assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN = - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read ; + mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ; - // register mmio_axi4_adapter_master_xactor_crg_rd_addr_full - assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN = - mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read ; - assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN = 1'b1 ; + // register mmio_axi4_adapter_master_xactor_clearing + assign mmio_axi4_adapter_master_xactor_clearing$D_IN = 1'd0 ; + assign mmio_axi4_adapter_master_xactor_clearing$EN = + mmio_axi4_adapter_master_xactor_clearing ; - // register mmio_axi4_adapter_master_xactor_crg_rd_data_full - assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$D_IN = - mmio_axi4_adapter_master_xactor_crg_rd_data_full$port3__read ; - assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN = 1'b1 ; + // register mmio_axi4_adapter_master_xactor_shim_arff_rv + assign mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN = + mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read ; + assign mmio_axi4_adapter_master_xactor_shim_arff_rv$EN = 1'b1 ; - // register mmio_axi4_adapter_master_xactor_crg_wr_addr_full - assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN = - mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read ; - assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN = 1'b1 ; + // register mmio_axi4_adapter_master_xactor_shim_awff_rv + assign mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN = + mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read ; + assign mmio_axi4_adapter_master_xactor_shim_awff_rv$EN = 1'b1 ; - // register mmio_axi4_adapter_master_xactor_crg_wr_data_full - assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$D_IN = - mmio_axi4_adapter_master_xactor_crg_wr_data_full$port3__read ; - assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN = 1'b1 ; + // register mmio_axi4_adapter_master_xactor_shim_bff_rv + assign mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN = + mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read ; + assign mmio_axi4_adapter_master_xactor_shim_bff_rv$EN = 1'b1 ; - // register mmio_axi4_adapter_master_xactor_crg_wr_resp_full - assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN = - mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read ; - assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN = 1'b1 ; + // register mmio_axi4_adapter_master_xactor_shim_rff_rv + assign mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN = + mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read ; + assign mmio_axi4_adapter_master_xactor_shim_rff_rv$EN = 1'b1 ; - // register mmio_axi4_adapter_master_xactor_rg_rd_addr - assign mmio_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78], - 29'd851968 } ; - assign mmio_axi4_adapter_master_xactor_rg_rd_addr$EN = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; + // register mmio_axi4_adapter_master_xactor_shim_wff_rv + assign mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN = + mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read ; + assign mmio_axi4_adapter_master_xactor_shim_wff_rv$EN = 1'b1 ; - // register mmio_axi4_adapter_master_xactor_rg_rd_data - assign mmio_axi4_adapter_master_xactor_rg_rd_data$D_IN = - { master1_rid, master1_rdata, master1_rresp, master1_rlast } ; - assign mmio_axi4_adapter_master_xactor_rg_rd_data$EN = 1'd1 ; - - // register mmio_axi4_adapter_master_xactor_rg_wr_addr - assign mmio_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78], - 29'd851968 } ; - assign mmio_axi4_adapter_master_xactor_rg_wr_addr$EN = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; - - // register mmio_axi4_adapter_master_xactor_rg_wr_data - assign mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], - mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:64], - 1'd1 } ; - assign mmio_axi4_adapter_master_xactor_rg_wr_data$EN = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; - - // register mmio_axi4_adapter_master_xactor_rg_wr_resp - assign mmio_axi4_adapter_master_xactor_rg_wr_resp$D_IN = - { master1_bid, master1_bresp } ; - assign mmio_axi4_adapter_master_xactor_rg_wr_resp$EN = - master1_bvalid && - !mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; + // register mmio_axi4_adapter_read_req_addr + assign mmio_axi4_adapter_read_req_addr$D_IN = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] ; + assign mmio_axi4_adapter_read_req_addr$EN = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; // register propDstData_0_rl assign propDstData_0_rl$D_IN = @@ -4387,37 +5275,30 @@ module mkProc(CLK, propDstData_0_rl ; assign propDstData_0_rl$EN = 1'd1 ; - // register propDstData_0_rl_1 - assign propDstData_0_rl_1$D_IN = - CAN_FIRE_RL_srcPropose_4 ? - core_0$tlbToMem_memReq_first : - propDstData_0_rl_1 ; - assign propDstData_0_rl_1$EN = 1'd1 ; - // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155, - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160, + { IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1274, + IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1279, CAN_FIRE_RL_srcPropose_2 ? - propDstData_1_0_lat_0$wget[513] : - propDstData_1_0_rl[513], + propDstData_1_0_lat_0$wget[517] : + propDstData_1_0_rl[517], CAN_FIRE_RL_srcPropose_2 ? - propDstData_1_0_lat_0$wget[512:1] : - propDstData_1_0_rl[512:1], - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181 } ; + propDstData_1_0_lat_0$wget[516:1] : + propDstData_1_0_rl[516:1], + IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1300 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193, - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198, + { IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1312, + IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1317, CAN_FIRE_RL_srcPropose_3 ? - propDstData_1_1_lat_0$wget[513] : - propDstData_1_1_rl[513], + propDstData_1_1_lat_0$wget[517] : + propDstData_1_1_rl[517], CAN_FIRE_RL_srcPropose_3 ? - propDstData_1_1_lat_0$wget[512:1] : - propDstData_1_1_rl[512:1], - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219 } ; + propDstData_1_1_lat_0$wget[516:1] : + propDstData_1_1_rl[516:1], + IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1338 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -4429,43 +5310,35 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = - !propDstIdx_0_lat_1$whas && - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 ; + !NOT_enqDst_0_rl_153_BIT_73_154_159_AND_SEL_ARR_ETC___d1247 && + IF_propDstIdx_0_lat_0_whas__121_THEN_propDstId_ETC___d1124 ; assign propDstIdx_0_rl$EN = 1'd1 ; - // register propDstIdx_0_rl_1 - assign propDstIdx_0_rl_1$D_IN = - !NOT_enqDst_0_dummy2_0_1_read__513_514_OR_NOT_e_ETC___d1520 && - IF_propDstIdx_0_lat_0_1_whas__467_THEN_propDst_ETC___d1470 ; - assign propDstIdx_0_rl_1$EN = 1'd1 ; - // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = - !propDstIdx_1_0_lat_1$whas && - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 ; + !NOT_enqDst_1_0_rl_348_BIT_584_349_354_AND_SEL__ETC___d1544 && + IF_propDstIdx_1_0_lat_0_whas__254_THEN_propDst_ETC___d1257 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145 ; + IF_propDstIdx_1_1_lat_0_whas__261_THEN_propDst_ETC___d1264 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976 ; + IF_propDstIdx_1_lat_0_whas__128_THEN_propDstId_ETC___d1131 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 assign srcRR_0$D_IN = srcRR_0 + 1'd1 ; - assign srcRR_0$EN = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ; + assign srcRR_0$EN = enqDst_0_lat_0$whas ; // register srcRR_1_0 assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ; - assign srcRR_1_0$EN = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ; + assign srcRR_1_0$EN = enqDst_1_0_lat_0$whas ; // submodule core_0 assign core_0$coreReq_perfReq_loc = 4'h0 ; @@ -4477,6 +5350,14 @@ module mkProc(CLK, WILL_FIRE_RL_sendPRq ? MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; + assign core_0$hart0_csr_mem_server_request_put = + hart0_csr_mem_server_request_put ; + assign core_0$hart0_fpr_mem_server_request_put = + hart0_fpr_mem_server_request_put ; + assign core_0$hart0_gpr_mem_server_request_put = + hart0_gpr_mem_server_request_put ; + assign core_0$hart0_run_halt_server_request_put = + hart0_run_halt_server_request_put ; assign core_0$iCacheToParent_fromP_enq_x = WILL_FIRE_RL_sendPRq_1 ? MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : @@ -4513,15 +5394,15 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 or MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 or - MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 or - MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 or - WILL_FIRE_RL_mmioPlatform_waitMSIPDone or - MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 or - WILL_FIRE_RL_mmioPlatform_processToHost or - MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 or - WILL_FIRE_RL_mmioPlatform_processFromHost or - MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 or WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp or + MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 or + MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6 or + MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 or + WILL_FIRE_RL_mmioPlatform_waitMSIPDone or + MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 or + WILL_FIRE_RL_mmioPlatform_processToHost or + MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 or + WILL_FIRE_RL_mmioPlatform_processFromHost or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 or WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10) @@ -4539,35 +5420,34 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4; - MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5: + WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5; - WILL_FIRE_RL_mmioPlatform_waitMSIPDone: + MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6; - WILL_FIRE_RL_mmioPlatform_processToHost: + WILL_FIRE_RL_mmioPlatform_waitMSIPDone: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7; - WILL_FIRE_RL_mmioPlatform_processFromHost: + WILL_FIRE_RL_mmioPlatform_processToHost: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8; - WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp: + WILL_FIRE_RL_mmioPlatform_processFromHost: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9; WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10; default: core_0$mmioToPlatform_pRs_enq_x = - 67'h2AAAAAAAAAAAAAAAA /* unspecified value */ ; + 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign core_0$mmioToPlatform_setTime_t = mmioPlatform_mtime ; assign core_0$recvDoStats_x = core_0$sendDoStats ; - assign core_0$setDEIP_v = debug_external_interrupt_req_set_not_clear ; assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h108607, llc$dma_respLd_first[3] } ; + { ld_data__h162613, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -4580,38 +5460,40 @@ module mkProc(CLK, assign core_0$EN_iCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose_1 ; assign core_0$EN_iCacheToParent_fromP_enq = WILL_FIRE_RL_sendPRq_1 || WILL_FIRE_RL_sendPRs_1 ; - assign core_0$EN_tlbToMem_memReq_deq = CAN_FIRE_RL_srcPropose_4 ; - assign core_0$EN_tlbToMem_respLd_enq = CAN_FIRE_RL_sendLdRespToTlb ; + assign core_0$EN_tlbToMem_memReq_deq = + CAN_FIRE_RL_llc_mem_server_srcPropose ; + assign core_0$EN_tlbToMem_respLd_enq = + CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; assign core_0$EN_mmioToPlatform_cRq_deq = MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; assign core_0$EN_mmioToPlatform_pRs_enq = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 || + mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d573 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 || + mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d680 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 || + mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d746 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 || - !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) || + (!mmioPlatform_fetchingWay_079_ULT_mmioPlatform__ETC___d1089 || + !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) || + WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || WILL_FIRE_RL_mmioPlatform_waitMSIPDone || WILL_FIRE_RL_mmioPlatform_processToHost || WILL_FIRE_RL_mmioPlatform_processFromHost || - WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 || + NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d694 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d758 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -4646,71 +5528,60 @@ module mkProc(CLK, core_0$RDY_renameDebug_renameErr_get ; assign core_0$EN_setMEIP = 1'd1 ; assign core_0$EN_setSEIP = 1'd1 ; - assign core_0$EN_setDEIP = 1'd1 ; - - // submodule enqDst_0_dummy2_0 - assign enqDst_0_dummy2_0$D_IN = 1'd1 ; - assign enqDst_0_dummy2_0$EN = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ; - - // submodule enqDst_0_dummy2_0_1 - assign enqDst_0_dummy2_0_1$D_IN = 1'd1 ; - assign enqDst_0_dummy2_0_1$EN = - NOT_enqDst_0_dummy2_0_1_read__513_514_OR_NOT_e_ETC___d1520 ; - - // submodule enqDst_0_dummy2_1 - assign enqDst_0_dummy2_1$D_IN = 1'd1 ; - assign enqDst_0_dummy2_1$EN = CAN_FIRE_RL_doEnq ; - - // submodule enqDst_0_dummy2_1_1 - assign enqDst_0_dummy2_1_1$D_IN = 1'd1 ; - assign enqDst_0_dummy2_1_1$EN = CAN_FIRE_RL_doEnq_2 ; - - // submodule enqDst_1_0_dummy2_0 - assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ; - assign enqDst_1_0_dummy2_0$EN = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ; - - // submodule enqDst_1_0_dummy2_1 - assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ; - assign enqDst_1_0_dummy2_1$EN = CAN_FIRE_RL_doEnq_1 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_reset ; - assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_trace_data - assign f_trace_data$D_IN = 362'h0 ; - assign f_trace_data$ENQ = 1'b0 ; - assign f_trace_data$DEQ = EN_trace_data_out_get ; - assign f_trace_data$CLR = 1'b0 ; + assign core_0$EN_hart0_run_halt_server_request_put = + EN_hart0_run_halt_server_request_put ; + assign core_0$EN_hart0_run_halt_server_response_get = + EN_hart0_run_halt_server_response_get ; + assign core_0$EN_hart0_gpr_mem_server_request_put = + EN_hart0_gpr_mem_server_request_put ; + assign core_0$EN_hart0_gpr_mem_server_response_get = + EN_hart0_gpr_mem_server_response_get ; + assign core_0$EN_hart0_fpr_mem_server_request_put = + EN_hart0_fpr_mem_server_request_put ; + assign core_0$EN_hart0_fpr_mem_server_response_get = + EN_hart0_fpr_mem_server_response_get ; + assign core_0$EN_hart0_csr_mem_server_request_put = + EN_hart0_csr_mem_server_request_put ; + assign core_0$EN_hart0_csr_mem_server_response_get = + EN_hart0_csr_mem_server_response_get ; // submodule llc - assign llc$dma_memReq_enq_x = - { tlbQ$D_OUT[64:1], - 577'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555, - tlbQ$D_OUT[0], - tlbQ$D_OUT[6:4] } ; + always@(MUX_llc$dma_memReq_enq_1__SEL_1 or + MUX_llc$dma_memReq_enq_1__VAL_1 or + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st or + MUX_llc$dma_memReq_enq_1__VAL_2 or + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld or + MUX_llc$dma_memReq_enq_1__VAL_3 or + WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC or + MUX_llc$dma_memReq_enq_1__VAL_4) + begin + case (1'b1) // synopsys parallel_case + MUX_llc$dma_memReq_enq_1__SEL_1: + llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_1; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st: + llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_2; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld: + llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_3; + WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC: + llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_4; + default: llc$dma_memReq_enq_x = + 649'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end assign llc$perf_req_r = 4'h0 ; assign llc$perf_setStatus_doStats = core_0$sendDoStats ; assign llc$to_child_rqFromC_enq_x = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ? + enqDst_0_lat_0$whas ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1241, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1251, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267 } ; + { IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1360, + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1365, + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1370, + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1380, + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1386 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h111736, + { IF_llc_axi4_adapter_rg_rd_rsp_beat_950_BIT_0_9_ETC___d1992, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -4718,18 +5589,23 @@ module mkProc(CLK, WILL_FIRE_RL_sendPRs_1 || WILL_FIRE_RL_sendPRq_1 || WILL_FIRE_RL_sendPRs || WILL_FIRE_RL_sendPRq ; - assign llc$EN_dma_memReq_enq = CAN_FIRE_RL_sendTlbReqToLLC ; + assign llc$EN_dma_memReq_enq = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || + WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC ; assign llc$EN_dma_respLd_deq = - WILL_FIRE_RL_sendLdRespToTlb || - WILL_FIRE_RL_sendLdRespToMemLoader ; + WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; assign llc$EN_dma_respSt_deq = - WILL_FIRE_RL_sendStRespToTlb || - WILL_FIRE_RL_sendStRespToMemLoader ; + WILL_FIRE_RL_llc_mem_server_sendStRespToTlb || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; assign llc$EN_to_mem_toM_deq = - WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_rg_rd_req_beat == 3'd7 || WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - llc_axi4_adapter_rg_wr_req_beat == 3'd7 ; + llc_axi4_adapter_rg_wr_req_beat == 3'd7 || + WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; assign llc$EN_to_mem_rsFromM_enq = WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ; @@ -4741,89 +5617,27 @@ module mkProc(CLK, // submodule llc_axi4_adapter_f_pending_reads assign llc_axi4_adapter_f_pending_reads$D_IN = llc$to_mem_toM_first[68:0] ; assign llc_axi4_adapter_f_pending_reads$ENQ = - WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_rg_rd_req_beat == 3'd0 ; + CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; assign llc_axi4_adapter_f_pending_reads$DEQ = WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ; assign llc_axi4_adapter_f_pending_reads$CLR = 1'b0 ; - // submodule llc_axi4_adapter_f_pending_writes - assign llc_axi4_adapter_f_pending_writes$D_IN = - llc$to_mem_toM_first[639:0] ; - assign llc_axi4_adapter_f_pending_writes$ENQ = - WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - llc_axi4_adapter_rg_wr_req_beat == 3'd0 ; - assign llc_axi4_adapter_f_pending_writes$DEQ = - WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - llc_axi4_adapter_rg_wr_rsp_beat == 3'd7 ; - assign llc_axi4_adapter_f_pending_writes$CLR = 1'b0 ; + // submodule llc_mem_server_f_dword_in_line + assign llc_mem_server_f_dword_in_line$D_IN = 3'h0 ; + assign llc_mem_server_f_dword_in_line$ENQ = 1'b0 ; + assign llc_mem_server_f_dword_in_line$DEQ = 1'b0 ; + assign llc_mem_server_f_dword_in_line$CLR = 1'b0 ; - // submodule mmioPlatform_fromHostQ_clearReq_dummy2_0 - assign mmioPlatform_fromHostQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign mmioPlatform_fromHostQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule mmioPlatform_fromHostQ_clearReq_dummy2_1 - assign mmioPlatform_fromHostQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign mmioPlatform_fromHostQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule mmioPlatform_fromHostQ_deqReq_dummy2_0 - assign mmioPlatform_fromHostQ_deqReq_dummy2_0$D_IN = 1'd1 ; - assign mmioPlatform_fromHostQ_deqReq_dummy2_0$EN = - mmioPlatform_fromHostQ_deqReq_lat_0$whas ; - - // submodule mmioPlatform_fromHostQ_deqReq_dummy2_1 - assign mmioPlatform_fromHostQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign mmioPlatform_fromHostQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmioPlatform_fromHostQ_deqReq_dummy2_2 - assign mmioPlatform_fromHostQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign mmioPlatform_fromHostQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmioPlatform_fromHostQ_enqReq_dummy2_0 - assign mmioPlatform_fromHostQ_enqReq_dummy2_0$D_IN = 1'b0 ; - assign mmioPlatform_fromHostQ_enqReq_dummy2_0$EN = 1'b0 ; - - // submodule mmioPlatform_fromHostQ_enqReq_dummy2_1 - assign mmioPlatform_fromHostQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign mmioPlatform_fromHostQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmioPlatform_fromHostQ_enqReq_dummy2_2 - assign mmioPlatform_fromHostQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign mmioPlatform_fromHostQ_enqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmioPlatform_toHostQ_clearReq_dummy2_0 - assign mmioPlatform_toHostQ_clearReq_dummy2_0$D_IN = 1'b0 ; - assign mmioPlatform_toHostQ_clearReq_dummy2_0$EN = 1'b0 ; - - // submodule mmioPlatform_toHostQ_clearReq_dummy2_1 - assign mmioPlatform_toHostQ_clearReq_dummy2_1$D_IN = 1'd1 ; - assign mmioPlatform_toHostQ_clearReq_dummy2_1$EN = 1'd1 ; - - // submodule mmioPlatform_toHostQ_deqReq_dummy2_0 - assign mmioPlatform_toHostQ_deqReq_dummy2_0$D_IN = 1'd1 ; - assign mmioPlatform_toHostQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_rl_tohost ; - - // submodule mmioPlatform_toHostQ_deqReq_dummy2_1 - assign mmioPlatform_toHostQ_deqReq_dummy2_1$D_IN = 1'b0 ; - assign mmioPlatform_toHostQ_deqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmioPlatform_toHostQ_deqReq_dummy2_2 - assign mmioPlatform_toHostQ_deqReq_dummy2_2$D_IN = 1'd1 ; - assign mmioPlatform_toHostQ_deqReq_dummy2_2$EN = 1'd1 ; - - // submodule mmioPlatform_toHostQ_enqReq_dummy2_0 - assign mmioPlatform_toHostQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign mmioPlatform_toHostQ_enqReq_dummy2_0$EN = - mmioPlatform_toHostQ_enqReq_lat_0$whas ; - - // submodule mmioPlatform_toHostQ_enqReq_dummy2_1 - assign mmioPlatform_toHostQ_enqReq_dummy2_1$D_IN = 1'b0 ; - assign mmioPlatform_toHostQ_enqReq_dummy2_1$EN = 1'b0 ; - - // submodule mmioPlatform_toHostQ_enqReq_dummy2_2 - assign mmioPlatform_toHostQ_enqReq_dummy2_2$D_IN = 1'd1 ; - assign mmioPlatform_toHostQ_enqReq_dummy2_2$EN = 1'd1 ; + // submodule llc_mem_server_tlbQ + assign llc_mem_server_tlbQ$D_IN = + llc_mem_server_propDstIdx_0_lat_1$whas ? + llc_mem_server_enqDst_0_lat_0$wget[64:0] : + llc_mem_server_enqDst_0_rl[64:0] ; + assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; + assign llc_mem_server_tlbQ$DEQ = + WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC ; + assign llc_mem_server_tlbQ$CLR = 1'b0 ; // submodule mmio_axi4_adapter_f_reqs_from_core always@(MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1 or @@ -4849,12 +5663,12 @@ module mkProc(CLK, mmio_axi4_adapter_f_reqs_from_core$D_IN = MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4; default: mmio_axi4_adapter_f_reqs_from_core$D_IN = - 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign mmio_axi4_adapter_f_reqs_from_core$ENQ = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && - mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || + mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req || WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req || WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; @@ -4865,13 +5679,33 @@ module mkProc(CLK, assign mmio_axi4_adapter_f_reqs_from_core$CLR = 1'b0 ; // submodule mmio_axi4_adapter_f_rsps_to_core - assign mmio_axi4_adapter_f_rsps_to_core$D_IN = - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1 ? - 65'h10000000000000000 : - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 ; + always@(MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1 or + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 or + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 or + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps or + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1: + mmio_axi4_adapter_f_rsps_to_core$D_IN = + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1; + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2: + mmio_axi4_adapter_f_rsps_to_core$D_IN = + 130'h200000000000000000000000000000000; + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps: + mmio_axi4_adapter_f_rsps_to_core$D_IN = + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3; + default: mmio_axi4_adapter_f_rsps_to_core$D_IN = + 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end assign mmio_axi4_adapter_f_rsps_to_core$ENQ = + (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req || + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req) && + !mmio_axi4_adapter_soc_map$m_is_IO_addr || WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] == 2'b0 || + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == + 2'd0 || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; assign mmio_axi4_adapter_f_rsps_to_core$DEQ = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp || @@ -4879,265 +5713,184 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; assign mmio_axi4_adapter_f_rsps_to_core$CLR = 1'b0 ; - // submodule propDstData_0_dummy2_0 - assign propDstData_0_dummy2_0$D_IN = 1'd1 ; - assign propDstData_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose ; - - // submodule propDstData_0_dummy2_0_1 - assign propDstData_0_dummy2_0_1$D_IN = 1'd1 ; - assign propDstData_0_dummy2_0_1$EN = CAN_FIRE_RL_srcPropose_4 ; - - // submodule propDstData_0_dummy2_1 - assign propDstData_0_dummy2_1$D_IN = 1'b0 ; - assign propDstData_0_dummy2_1$EN = 1'b0 ; - - // submodule propDstData_0_dummy2_1_1 - assign propDstData_0_dummy2_1_1$D_IN = 1'b0 ; - assign propDstData_0_dummy2_1_1$EN = 1'b0 ; - - // submodule propDstData_1_0_dummy2_0 - assign propDstData_1_0_dummy2_0$D_IN = 1'd1 ; - assign propDstData_1_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose_2 ; - - // submodule propDstData_1_0_dummy2_1 - assign propDstData_1_0_dummy2_1$D_IN = 1'b0 ; - assign propDstData_1_0_dummy2_1$EN = 1'b0 ; - - // submodule propDstData_1_1_dummy2_0 - assign propDstData_1_1_dummy2_0$D_IN = 1'd1 ; - assign propDstData_1_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_3 ; - - // submodule propDstData_1_1_dummy2_1 - assign propDstData_1_1_dummy2_1$D_IN = 1'b0 ; - assign propDstData_1_1_dummy2_1$EN = 1'b0 ; - - // submodule propDstData_1_dummy2_0 - assign propDstData_1_dummy2_0$D_IN = 1'd1 ; - assign propDstData_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_1 ; - - // submodule propDstData_1_dummy2_1 - assign propDstData_1_dummy2_1$D_IN = 1'b0 ; - assign propDstData_1_dummy2_1$EN = 1'b0 ; - - // submodule propDstIdx_0_dummy2_0 - assign propDstIdx_0_dummy2_0$D_IN = 1'd1 ; - assign propDstIdx_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose ; - - // submodule propDstIdx_0_dummy2_0_1 - assign propDstIdx_0_dummy2_0_1$D_IN = 1'd1 ; - assign propDstIdx_0_dummy2_0_1$EN = CAN_FIRE_RL_srcPropose_4 ; - - // submodule propDstIdx_0_dummy2_1 - assign propDstIdx_0_dummy2_1$D_IN = 1'd1 ; - assign propDstIdx_0_dummy2_1$EN = propDstIdx_0_lat_1$whas ; - - // submodule propDstIdx_0_dummy2_1_1 - assign propDstIdx_0_dummy2_1_1$D_IN = 1'd1 ; - assign propDstIdx_0_dummy2_1_1$EN = - NOT_enqDst_0_dummy2_0_1_read__513_514_OR_NOT_e_ETC___d1520 ; - - // submodule propDstIdx_1_0_dummy2_0 - assign propDstIdx_1_0_dummy2_0$D_IN = 1'd1 ; - assign propDstIdx_1_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose_2 ; - - // submodule propDstIdx_1_0_dummy2_1 - assign propDstIdx_1_0_dummy2_1$D_IN = 1'd1 ; - assign propDstIdx_1_0_dummy2_1$EN = propDstIdx_1_0_lat_1$whas ; - - // submodule propDstIdx_1_1_dummy2_0 - assign propDstIdx_1_1_dummy2_0$D_IN = 1'd1 ; - assign propDstIdx_1_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_3 ; - - // submodule propDstIdx_1_1_dummy2_1 - assign propDstIdx_1_1_dummy2_1$D_IN = 1'd1 ; - assign propDstIdx_1_1_dummy2_1$EN = propDstIdx_1_1_lat_1$whas ; - - // submodule propDstIdx_1_dummy2_0 - assign propDstIdx_1_dummy2_0$D_IN = 1'd1 ; - assign propDstIdx_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_1 ; - - // submodule propDstIdx_1_dummy2_1 - assign propDstIdx_1_dummy2_1$D_IN = 1'd1 ; - assign propDstIdx_1_dummy2_1$EN = propDstIdx_1_lat_1$whas ; - - // submodule tlbQ - assign tlbQ$D_IN = - NOT_enqDst_0_dummy2_0_1_read__513_514_OR_NOT_e_ETC___d1520 ? - enqDst_0_lat_0_1$wget[64:0] : - enqDst_0_rl_1[64:0] ; - assign tlbQ$ENQ = CAN_FIRE_RL_doEnq_2 ; - assign tlbQ$DEQ = CAN_FIRE_RL_sendTlbReqToLLC ; - assign tlbQ$CLR = 1'b0 ; + // submodule mmio_axi4_adapter_soc_map + assign mmio_axi4_adapter_soc_map$m_is_IO_addr_addr = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] ; + assign mmio_axi4_adapter_soc_map$m_is_mem_addr_addr = 64'h0 ; + assign mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals - module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27613 && - mmioPlatform_reqBE_BIT_0___h27653, - 2'd0 }), - .amoExec_current_data(x__h34907), - .amoExec_in_data(mmioPlatform_reqData__h45948), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27613 && - !mmioPlatform_reqBE_BIT_0___h27653), - .amoExec(x__h29637)); - module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27613 && - mmioPlatform_reqBE_BIT_0___h27653, - 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h34759), - .amoExec_in_data(mmioPlatform_reqData__h45948), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27613 && - !mmioPlatform_reqBE_BIT_0___h27653), - .amoExec(x__h32547)); - module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27613 && - mmioPlatform_reqBE_BIT_0___h27653, - 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40146), - .amoExec_in_data(mmioPlatform_reqData__h45948), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27613 && - !mmioPlatform_reqBE_BIT_0___h27653), - .amoExec(x__h38347)); - module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27613 && - mmioPlatform_reqBE_BIT_0___h27653, - 2'd0 }), - .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h45948), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27613 && - !mmioPlatform_reqBE_BIT_0___h27653), - .amoExec(x__h40367)); - assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645 = - { 1'h0, - (mmioPlatform_reqFunc[5:4] == 2'd2) ? - { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : - { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h37818 } } ; - assign IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520 = - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_46_BITS_3_TO_0_85_CONCAT__ETC___d622), + .amoExec_wordIdx({ 1'd0, + mmioPlatform_reqBE_BIT_4___h34136 && + !mmioPlatform_reqBE_BIT_0___h34176 }), + .amoExec_current({ 65'd0, x__h46418 }), + .amoExec_inpt(mmioPlatform_reqData), + .amoExec(amoExec___d626)); + module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_46_BITS_3_TO_0_85_CONCAT__ETC___d622), + .amoExec_wordIdx({ 1'd0, + mmioPlatform_reqBE_BIT_4___h34136 && + !mmioPlatform_reqBE_BIT_0___h34176 }), + .amoExec_current({ 65'd0, + mmioPlatform_mtime__h46207 }), + .amoExec_inpt(mmioPlatform_reqData), + .amoExec(amoExec___d703)); + module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_46_BITS_3_TO_0_85_CONCAT__ETC___d622), + .amoExec_wordIdx({ 1'd0, + mmioPlatform_reqBE_BIT_4___h34136 && + !mmioPlatform_reqBE_BIT_0___h34176 }), + .amoExec_current(129'd0), + .amoExec_inpt(mmioPlatform_reqData), + .amoExec(amoExec___d765)); + module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_46_BITS_3_TO_0_85_CONCAT__ETC___d622), + .amoExec_wordIdx({ 1'd0, + mmioPlatform_reqBE_BIT_4___h34136 && + !mmioPlatform_reqBE_BIT_0___h34176 }), + .amoExec_current({ 65'd0, + mmioPlatform_fromHostQ_data_0 }), + .amoExec_inpt(mmioPlatform_reqData), + .amoExec(amoExec___d807)); + assign IF_IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4__ETC___d668 = + (IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417 = + assign IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d562 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 = - newData__h29526 <= mmioPlatform_mtime ; - assign IF_NOT_propDstIdx_0_dummy2_1_read__019_020_OR__ETC___d1054 = - NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053 ? - propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976 : - propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 ; - assign IF_NOT_propDstIdx_1_0_dummy2_1_read__278_279_O_ETC___d1323 = - NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322 ? - propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145 : - propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 ; - assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_ETC___d1126 = - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 ? - !srcRR_0 : - propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 ; - assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_A_ETC___d1423 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 ? - !srcRR_1_0 : - propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 ; - assign IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366 = - (core_0$mmioToPlatform_cRq_first[141:81] == + assign IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 = + newData__h37921 <= mmioPlatform_mtime ; + assign IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511 = + (core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_toHostAddr) ? 67'h5AAAAAAAAAAAAAAAA : - ((core_0$mmioToPlatform_cRq_first[141:81] == + ((core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : - { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_1_whas__482_THEN_enqDst_0_la_ETC___d1487 = - NOT_enqDst_0_dummy2_0_1_read__513_514_OR_NOT_e_ETC___d1520 ? - enqDst_0_lat_0_1$wget[65] : - enqDst_0_rl_1[65] ; - assign IF_enqDst_0_lat_0_whas__95_THEN_enqDst_0_lat_0_ETC___d1000 = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ? - enqDst_0_lat_0$wget[73] : - enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1231 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? - enqDst_1_0_lat_0$wget[580] : - enqDst_1_0_rl[580] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1241 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? - enqDst_1_0_lat_0$wget[579:516] : - enqDst_1_0_rl[579:516] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? - enqDst_1_0_lat_0$wget[515:514] : - enqDst_1_0_rl[515:514] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1251 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? - enqDst_1_0_lat_0$wget[513] : - enqDst_1_0_rl[513] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? - enqDst_1_0_lat_0$wget[512:1] : - enqDst_1_0_rl[512:1] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? + { 3'd7, core_0$mmioToPlatform_cRq_first[214:151] }) ; + assign IF_enqDst_0_lat_0_whas__150_THEN_enqDst_0_lat__ETC___d1155 = + enqDst_0_lat_0$whas ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; + assign IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1350 = + enqDst_1_0_lat_0$whas ? + enqDst_1_0_lat_0$wget[584] : + enqDst_1_0_rl[584] ; + assign IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1360 = + enqDst_1_0_lat_0$whas ? + enqDst_1_0_lat_0$wget[583:520] : + enqDst_1_0_rl[583:520] ; + assign IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1365 = + enqDst_1_0_lat_0$whas ? + enqDst_1_0_lat_0$wget[519:518] : + enqDst_1_0_rl[519:518] ; + assign IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1370 = + enqDst_1_0_lat_0$whas ? + enqDst_1_0_lat_0$wget[517] : + enqDst_1_0_rl[517] ; + assign IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1380 = + enqDst_1_0_lat_0$whas ? + enqDst_1_0_lat_0$wget[516:1] : + enqDst_1_0_rl[516:1] ; + assign IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1386 = + enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1269 = + assign IF_enqDst_1_0_lat_1_whas__342_THEN_enqDst_1_0__ETC___d1388 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1251, + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1370, CAN_FIRE_RL_doEnq_1 ? - 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, - x__h72308 } ; - assign IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1270 = + 516'h555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1380, + x__h90788 } ; + assign IF_enqDst_1_0_lat_1_whas__342_THEN_enqDst_1_0__ETC___d1389 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1241, + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1360, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246, - IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1269 } ; - assign IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786 = + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1365, + IF_enqDst_1_0_lat_1_whas__342_THEN_enqDst_1_0__ETC___d1388 } ; + assign IF_llc_axi4_adapter_rg_rd_rsp_beat_950_BIT_0_9_ETC___d1992 = + { llc_axi4_adapter_rg_rd_rsp_beat[0] ? + llc_axi4_adapter_rg_cline[515:512] : + { llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], + llc_axi4_adapter_rg_cline[515:513] }, + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4], + llc_axi4_adapter_rg_cline[511:64] } ; + assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d1725 = + { (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == + 3'd7) ? + data__h115067 : + llc_mem_server_rg_cacheline_cache_data[511:448], + (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == + 3'd6) ? + data__h115067 : + llc_mem_server_rg_cacheline_cache_data[447:384], + (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == + 3'd5) ? + data__h115067 : + llc_mem_server_rg_cacheline_cache_data[383:320], + (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == + 3'd4) ? + data__h115067 : + llc_mem_server_rg_cacheline_cache_data[319:256], + (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == + 3'd3) ? + data__h115067 : + llc_mem_server_rg_cacheline_cache_data[255:192], + (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == + 3'd2) ? + data__h115067 : + llc_mem_server_rg_cacheline_cache_data[191:128] } ; + assign IF_llc_mem_server_enqDst_0_lat_0_whas__816_THE_ETC___d1821 = + llc_mem_server_propDstIdx_0_lat_1$whas ? + llc_mem_server_enqDst_0_lat_0$wget[65] : + llc_mem_server_enqDst_0_rl[65] ; + assign IF_llc_mem_server_propDstData_0_lat_0_whas__80_ETC___d1811 = + CAN_FIRE_RL_llc_mem_server_srcPropose ? + core_0$tlbToMem_memReq_first : + llc_mem_server_propDstData_0_rl ; + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__801_ETC___d1804 = + CAN_FIRE_RL_llc_mem_server_srcPropose || + llc_mem_server_propDstIdx_0_rl ; + assign IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d938 = (mmioPlatform_curReq[2:0] == 3'h0) ? - mmioPlatform_reqData : + mmioPlatform_reqData[63:0] : 64'd0 ; - assign IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837 = + assign IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d990 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] : 64'd0 ; - assign IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586 = - ((mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + assign IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d735 = + ((mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 = + assign IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d686 = mmioPlatform_reqBE[4] ? - { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1[31]}}, - mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 } : - { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2[31]}}, - mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 } ; - assign IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 = + { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5[31]}}, + mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 } : + { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6[31]}}, + mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 } ; + assign IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d751 = mmioPlatform_reqBE[4] ? - { {32{mmioPlatform_mtime_BITS_63_TO_32__q3[31]}}, - mmioPlatform_mtime_BITS_63_TO_32__q3 } : - { {32{mmioPlatform_mtime_BITS_31_TO_0__q4[31]}}, - mmioPlatform_mtime_BITS_31_TO_0__q4 } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496 = + { {32{mmioPlatform_mtime_BITS_63_TO_32__q7[31]}}, + mmioPlatform_mtime_BITS_63_TO_32__q7 } : + { {32{mmioPlatform_mtime_BITS_31_TO_0__q8[31]}}, + mmioPlatform_mtime_BITS_31_TO_0__q8 } ; + assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d644 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtimecmp_0[63:56], @@ -5150,23 +5903,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496, + assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d653 = + { IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d644, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtimecmp_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505, + assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d661 = + { IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d653, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtimecmp_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565 = + assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d714 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtime[63:56], @@ -5179,23 +5932,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565, + assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d719 = + { IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d714, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtime[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570, + assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d724 = + { IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d719, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtime[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtime[7:0] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d666 = + assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d818 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_fromHostQ_data_0[63:56], @@ -5208,49 +5961,47 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d671 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d666, + assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d823 = + { IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d818, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_fromHostQ_data_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d676 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d671, + assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d828 = + { IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d823, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_fromHostQ_data_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418 = + assign IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d563 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539 = + IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d562 ; + assign IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_1_ETC___d687 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603 = + IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d686 ; + assign IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_1_ETC___d752 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d684 = + IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d751 ; + assign IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_2_ETC___d832 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? - { mmioPlatform_fromHostQ_empty ? - x__h40356 == 64'd0 : - x__h38336 == 64'd0, - 64'hAAAAAAAAAAAAAAAA } : - { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h42285 } ; - assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 = + (mmioPlatform_fromHostQ_empty ? + x__h54059 == 64'd0 : + x__h51369 == 64'd0) : + mmioPlatform_reqFunc[5:4] == 2'd1 ; + assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461 = + assign IF_mmioPlatform_waitLowerMSIPCRs_98_THEN_core__ETC___d606 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -5258,95 +6009,111 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d931 = - mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__69__ETC___d1084 = + mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d952 = - mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__69__ETC___d1106 = + mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? (mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944) : + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1099) : mmioPlatform_fetchedInsts_0 ; - assign IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073 = - propDstData_0_dummy2_1$Q_OUT ? - (CAN_FIRE_RL_srcPropose ? - propDstData_0_lat_0$wget[8:7] : - propDstData_0_rl[8:7]) : - 2'd0 ; - assign IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083 = - propDstData_0_dummy2_1$Q_OUT ? - (CAN_FIRE_RL_srcPropose ? - propDstData_0_lat_0$wget[6:5] : - propDstData_0_rl[6:5]) : - 2'd0 ; - assign IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155 = + assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225 = + mmio_axi4_adapter_soc_map$m_is_IO_addr ? + !mmio_axi4_adapter_master_xactor_clearing && + !mmio_axi4_adapter_master_xactor_shim_awff_rv[97] && + !mmio_axi4_adapter_master_xactor_shim_wff_rv[74] : + mmio_axi4_adapter_f_rsps_to_core$FULL_N ; + assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53 = + mmio_axi4_adapter_soc_map$m_is_IO_addr ? + !mmio_axi4_adapter_master_xactor_clearing && + !mmio_axi4_adapter_master_xactor_shim_arff_rv[97] : + mmio_axi4_adapter_f_rsps_to_core$FULL_N ; + assign IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1274 = CAN_FIRE_RL_srcPropose_2 ? - propDstData_1_0_lat_0$wget[579:516] : - propDstData_1_0_rl[579:516] ; - assign IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160 = + propDstData_1_0_lat_0$wget[583:520] : + propDstData_1_0_rl[583:520] ; + assign IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1279 = CAN_FIRE_RL_srcPropose_2 ? - propDstData_1_0_lat_0$wget[515:514] : - propDstData_1_0_rl[515:514] ; - assign IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181 = + propDstData_1_0_lat_0$wget[519:518] : + propDstData_1_0_rl[519:518] ; + assign IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1300 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193 = + assign IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1312 = CAN_FIRE_RL_srcPropose_3 ? - propDstData_1_1_lat_0$wget[579:516] : - propDstData_1_1_rl[579:516] ; - assign IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198 = + propDstData_1_1_lat_0$wget[583:520] : + propDstData_1_1_rl[583:520] ; + assign IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1317 = CAN_FIRE_RL_srcPropose_3 ? - propDstData_1_1_lat_0$wget[515:514] : - propDstData_1_1_rl[515:514] ; - assign IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219 = + propDstData_1_1_lat_0$wget[519:518] : + propDstData_1_1_rl[519:518] ; + assign IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1338 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077 = - propDstData_1_dummy2_1$Q_OUT ? - (CAN_FIRE_RL_srcPropose_1 ? - propDstData_1_lat_0$wget[8:7] : - propDstData_1_rl[8:7]) : - 2'd0 ; - assign IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087 = - propDstData_1_dummy2_1$Q_OUT ? - (CAN_FIRE_RL_srcPropose_1 ? - propDstData_1_lat_0$wget[6:5] : - propDstData_1_rl[6:5]) : - 2'd0 ; - assign IF_propDstIdx_0_lat_0_1_whas__467_THEN_propDst_ETC___d1470 = - CAN_FIRE_RL_srcPropose_4 || propDstIdx_0_rl_1 ; - assign IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 = + assign IF_propDstIdx_0_lat_0_whas__121_THEN_NOT_propD_ETC___d1187 = + !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; + assign IF_propDstIdx_0_lat_0_whas__121_THEN_propDstId_ETC___d1124 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 = + assign IF_propDstIdx_1_0_lat_0_whas__254_THEN_NOT_pro_ETC___d1420 = + !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; + assign IF_propDstIdx_1_0_lat_0_whas__254_THEN_propDst_ETC___d1257 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145 = + assign IF_propDstIdx_1_1_lat_0_whas__261_THEN_propDst_ETC___d1264 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976 = + assign IF_propDstIdx_1_lat_0_whas__128_THEN_propDstId_ETC___d1131 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_1_read__513_514_OR_NOT_e_ETC___d1520 = - (!enqDst_0_dummy2_0_1$Q_OUT || !enqDst_0_dummy2_1_1$Q_OUT || - !enqDst_0_rl_1[65]) && - propDstIdx_0_dummy2_1_1$Q_OUT && - IF_propDstIdx_0_lat_0_1_whas__467_THEN_propDst_ETC___d1470 ; - assign NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 = - (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || - !enqDst_0_rl[73]) && - (SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 || - IF_NOT_propDstIdx_0_dummy2_1_read__019_020_OR__ETC___d1054) ; - assign NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 = - (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT || - !enqDst_1_0_rl[580]) && - (SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 || - IF_NOT_propDstIdx_1_0_dummy2_1_read__278_279_O_ETC___d1323) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616 = + assign NOT_enqDst_0_rl_153_BIT_73_154_159_AND_SEL_ARR_ETC___d1247 = + !enqDst_0_rl[73] && + SEL_ARR_IF_propDstIdx_0_lat_0_whas__121_THEN_p_ETC___d1189 && + (SEL_ARR_IF_propDstIdx_0_lat_0_whas__121_THEN_p_ETC___d1185 ? + !srcRR_0 : + IF_propDstIdx_0_lat_0_whas__121_THEN_propDstId_ETC___d1124) ; + assign NOT_enqDst_1_0_rl_348_BIT_584_349_354_AND_SEL__ETC___d1544 = + !enqDst_1_0_rl[584] && + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__254_THEN_ETC___d1422 && + (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__254_THEN_ETC___d1418 ? + !srcRR_1_0 : + IF_propDstIdx_1_0_lat_0_whas__254_THEN_propDst_ETC___d1257) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d707 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d2025 = + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + !llc_axi4_adapter_rg_cline[515] : + !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d2028 = + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + llc_axi4_adapter_rg_cline[515] : + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; + assign NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d1074 = + mmioPlatform_curReq[66:64] != 3'd0 && + mmioPlatform_curReq[66:64] != 3'd1 && + mmioPlatform_curReq[66:64] != 3'd2 && + mmioPlatform_curReq[66:64] != 3'd3 && + mmioPlatform_curReq[66:64] != 3'd4 && + mmioPlatform_curReq[66:64] != 3'd5 && + mmioPlatform_curReq[66:64] != 3'd6 && + mmioPlatform_state == 2'd2 && + mmioPlatform_reqFunc[5:4] == 2'd0 ; + assign NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d1087 = + mmioPlatform_curReq[66:64] != 3'd0 && + mmioPlatform_curReq[66:64] != 3'd1 && + mmioPlatform_curReq[66:64] != 3'd2 && + mmioPlatform_curReq[66:64] != 3'd3 && + mmioPlatform_curReq[66:64] != 3'd4 && + mmioPlatform_curReq[66:64] != 3'd5 && + mmioPlatform_curReq[66:64] != 3'd6 && + mmioPlatform_state == 2'd3 && + mmioPlatform_reqFunc[5:4] == 2'd0 ; + assign NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d859 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5357,7 +6124,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715 = + assign NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d867 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5368,7 +6135,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d720 = + assign NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d872 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5380,7 +6147,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d730 = + assign NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d882 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5392,414 +6159,339 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d921 = - mmioPlatform_curReq[66:64] != 3'd0 && - mmioPlatform_curReq[66:64] != 3'd1 && - mmioPlatform_curReq[66:64] != 3'd2 && - mmioPlatform_curReq[66:64] != 3'd3 && - mmioPlatform_curReq[66:64] != 3'd4 && - mmioPlatform_curReq[66:64] != 3'd5 && - mmioPlatform_curReq[66:64] != 3'd6 && - mmioPlatform_state == 2'd2 && - mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d934 = - mmioPlatform_curReq[66:64] != 3'd0 && - mmioPlatform_curReq[66:64] != 3'd1 && - mmioPlatform_curReq[66:64] != 3'd2 && - mmioPlatform_curReq[66:64] != 3'd3 && - mmioPlatform_curReq[66:64] != 3'd4 && - mmioPlatform_curReq[66:64] != 3'd5 && - mmioPlatform_curReq[66:64] != 3'd6 && - mmioPlatform_state == 2'd3 && - mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 = - !mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT || - !mmioPlatform_fromHostQ_clearReq_rl ; - assign NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304 = - (!mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT || - !mmioPlatform_fromHostQ_enqReq_rl[64]) && - (mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT && - (mmioPlatform_fromHostQ_deqReq_lat_0$whas || - mmioPlatform_fromHostQ_deqReq_rl) || - mmioPlatform_fromHostQ_empty) ; - assign NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335 = + assign NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 = + assign NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d596 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 = + assign NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d694 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 = + assign NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d758 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 = - !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT || - !mmioPlatform_toHostQ_clearReq_rl ; - assign NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226 = - (!mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT || - (mmioPlatform_toHostQ_enqReq_lat_0$whas ? - !mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : - !mmioPlatform_toHostQ_enqReq_rl[64])) && - (mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT && - (!mmioPlatform_toHostQ_empty || - mmioPlatform_toHostQ_deqReq_rl) || - mmioPlatform_toHostQ_empty) ; - assign NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338 = - !propDstData_1_0_dummy2_1$Q_OUT || - (CAN_FIRE_RL_srcPropose_2 ? - !propDstData_1_0_lat_0$wget[513] : - !propDstData_1_0_rl[513]) ; - assign NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340 = - !propDstData_1_1_dummy2_1$Q_OUT || - (CAN_FIRE_RL_srcPropose_3 ? - !propDstData_1_1_lat_0$wget[513] : - !propDstData_1_1_rl[513]) ; - assign NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053 = - !propDstIdx_0_dummy2_1$Q_OUT || - !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322 = - !propDstIdx_1_0_dummy2_1$Q_OUT || - !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121 = - { CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, - CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14, - SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120 } ; - assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418 = - { CASE_x7379_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - !CASE_x7379_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411, - x__h79795 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360 = - { CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; - assign SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120 = - { CASE_x8756_0_propDstData_0_dummy2_1_read__057__ETC__q12, - x__h59070, - x__h59077 } ; - assign b__h110741 = - CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? + assign SEL_ARR_IF_propDstData_0_lat_0_whas__135_THEN__ETC___d1240 = + { CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q19, + x__h75450, + x__h75451 } ; + assign SEL_ARR_IF_propDstData_0_lat_0_whas__135_THEN__ETC___d1241 = + { CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q20, + CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q21, + SEL_ARR_IF_propDstData_0_lat_0_whas__135_THEN__ETC___d1240 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1456 = + { CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1481 = + { CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1498 = + { CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1515 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1481, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1498, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1532 = + { CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q32, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q33 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1533 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1456, + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q34, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1515, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1532 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1538 = + { CASE_x7352_0_IF_propDstData_1_0_lat_0_whas__26_ETC__q35, + !CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q36, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__269_THE_ETC___d1533, + x__h102087 } ; + assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__121_THEN_p_ETC___d1189 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__121_THEN_p_ETC___d1185 || + (IF_propDstIdx_0_lat_0_whas__121_THEN_NOT_propD_ETC___d1187 ? + IF_propDstIdx_1_lat_0_whas__128_THEN_propDstId_ETC___d1131 : + IF_propDstIdx_0_lat_0_whas__121_THEN_propDstId_ETC___d1124) ; + assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__254_THEN_ETC___d1422 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__254_THEN_ETC___d1418 || + (IF_propDstIdx_1_0_lat_0_whas__254_THEN_NOT_pro_ETC___d1420 ? + IF_propDstIdx_1_1_lat_0_whas__261_THEN_propDst_ETC___d1264 : + IF_propDstIdx_1_0_lat_0_whas__254_THEN_propDst_ETC___d1257) ; + assign _0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213 = + { 64'd0, + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4] } << + (mmio_axi4_adapter_read_req_addr[3] ? 32'd64 : 32'd0) ; + assign addr1__h66416 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign b__h167647 = + llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2368 = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ? + assign b__h4255 = + mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h29445 = - mmioPlatform_waitLowerMSIPCRs ? - { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h29238, 32'd0 } ; - assign failed_testnum__h139642 = + assign data__h115067 = + { llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[9] ? + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[73:66] : + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677[63:56], + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[8] ? + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[65:58] : + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677[55:48], + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[7] ? + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[57:50] : + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677[47:40], + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[6] ? + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[49:42] : + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677[39:32], + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[5] ? + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[41:34] : + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677[31:24], + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[4] ? + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[33:26] : + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677[23:16], + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[3] ? + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[25:18] : + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677[15:8], + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[2] ? + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[17:10] : + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677[7:0] } ; + assign failed_testnum__h198133 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign mem_req_rd_addr_araddr__h111034 = - { llc$to_mem_toM_first[68:11], x__h111069 } ; - assign mem_req_wr_addr_awaddr__h124958 = - { llc$to_mem_toM_first[639:582], x__h124983 } ; - assign mmioPlatform_cycle_12_ULT_99___d313 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 = + assign line_addr__h114500 = + { llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[92:35], + 6'b0 } ; + assign line_addr__h124608 = + { llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[92:35], + 6'b0 } ; + assign line_addr__h167856 = { llc$to_mem_toM_first[68:11], 6'h0 } ; + assign llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42 = + llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97:0] ; + assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40 = + llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97:0] ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d1957 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] && + (llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 || + llc$RDY_to_mem_rsFromM_enq && + llc_axi4_adapter_f_pending_reads$EMPTY_N) ; + assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q41 = + llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d1741 = + line_addr__h124608 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1642 = + line_addr__h114500 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q38 = + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[6:0] ; + assign llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39 = + llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[72:0] ; + assign mmioPlatform_cycle_57_ULT_99___d458 = mmioPlatform_cycle < 7'd99 ; + assign mmioPlatform_fetchingWay_079_ULT_mmioPlatform__ETC___d1089 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h40146 = - mmioPlatform_fromHostQ_data_0 ; - assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296 = - mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && - mmioPlatform_fromHostQ_enqReq_rl[64] || - (!mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT || - !mmioPlatform_fromHostQ_deqReq_lat_0$whas && - !mmioPlatform_fromHostQ_deqReq_rl) && - mmioPlatform_fromHostQ_full ; - assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ; - assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h34759 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 = - mmioPlatform_mtimecmp_0 <= newData__h32456 ; - assign mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 = + assign mmioPlatform_mtime_BITS_31_TO_0__q8 = mmioPlatform_mtime[31:0] ; + assign mmioPlatform_mtime_BITS_63_TO_32__q7 = mmioPlatform_mtime[63:32] ; + assign mmioPlatform_mtime__h46207 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 = + mmioPlatform_mtimecmp_0 <= newData__h42646 ; + assign mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 = + assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 = mmioPlatform_mtimecmp_0[31:0] ; - assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 = + assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h27653 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h27613 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h45948 = mmioPlatform_reqData ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 = + assign mmioPlatform_reqBE_BIT_0___h34176 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h34136 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqFunc_46_BITS_3_TO_0_85_CONCAT__ETC___d622 = + { mmioPlatform_reqFunc[3:0], + (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? 2'd1 : 2'd2, + 2'd0 } ; + assign mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d573 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 = + assign mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d680 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 || + (!IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 || + (IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 = + assign mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d746 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + (!mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218 = - mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 || - (!mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT || - !(!mmioPlatform_toHostQ_empty) && - !mmioPlatform_toHostQ_deqReq_rl) && - mmioPlatform_toHostQ_full ; - assign n__read_addr__h58938 = - propDstData_0_dummy2_1$Q_OUT ? - (CAN_FIRE_RL_srcPropose ? - propDstData_0_lat_0$wget[72:9] : - propDstData_0_rl[72:9]) : - 64'd0 ; - assign n__read_addr__h59023 = - propDstData_1_dummy2_1$Q_OUT ? - (CAN_FIRE_RL_srcPropose_1 ? - propDstData_1_lat_0$wget[72:9] : - propDstData_1_rl[72:9]) : - 64'd0 ; - assign n__read_addr__h77557 = - propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155 : - 64'd0 ; - assign n__read_addr__h77636 = - propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193 : - 64'd0 ; - assign n__read_child__h58943 = - propDstData_0_dummy2_1$Q_OUT && - (CAN_FIRE_RL_srcPropose ? - propDstData_0_lat_0$wget[0] : - propDstData_0_rl[0]) ; - assign n__read_child__h59028 = - propDstData_1_dummy2_1$Q_OUT && - (CAN_FIRE_RL_srcPropose_1 ? - propDstData_1_lat_0$wget[0] : - propDstData_1_rl[0]) ; - assign n__read_child__h77560 = - propDstData_1_0_dummy2_1$Q_OUT && - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181 ; - assign n__read_child__h77639 = - propDstData_1_1_dummy2_1$Q_OUT && - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219 ; - assign n__read_id__h58942 = - propDstData_0_dummy2_1$Q_OUT ? - (CAN_FIRE_RL_srcPropose ? - propDstData_0_lat_0$wget[3:1] : - propDstData_0_rl[3:1]) : - 3'd0 ; - assign n__read_id__h59027 = - propDstData_1_dummy2_1$Q_OUT ? - (CAN_FIRE_RL_srcPropose_1 ? - propDstData_1_lat_0$wget[3:1] : - propDstData_1_rl[3:1]) : - 3'd0 ; - assign n__read_snd_addr__h91728 = - propDstData_0_dummy2_1_1$Q_OUT ? - (CAN_FIRE_RL_srcPropose_4 ? - core_0$tlbToMem_memReq_first[64:1] : - propDstData_0_rl_1[64:1]) : - 64'd0 ; - assign n__read_snd_id__h91729 = - propDstData_0_dummy2_1_1$Q_OUT && - (CAN_FIRE_RL_srcPropose_4 ? - core_0$tlbToMem_memReq_first[0] : - propDstData_0_rl_1[0]) ; - assign newData__h29526 = + assign mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18 = + mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[96:0] ; + assign mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16 = + mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[96:0] ; + assign mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q17 = + mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; + assign newData__h37921 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h29637 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513 ; - assign newData__h32456 = + amoExec___d626[63:0] : + IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d661 ; + assign newData__h42646 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32547 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575 ; - assign new_cline__h111736 = - { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], - llc_axi4_adapter_rg_cline[511:64] } ; - assign op_result__h45964 = - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 + - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ; - assign op_result__h46494 = w1__h45361 ^ w2__h45363 ; - assign op_result__h46499 = w1__h45361 & w2__h45363 ; - assign op_result__h46504 = w1__h45361 | w2__h45363 ; - assign op_result__h46509 = - (w1__h45361 < w2__h45363) ? w1__h45361 : w2__h45363 ; - assign op_result__h46515 = - (w1__h45361 <= w2__h45363) ? w2__h45363 : w1__h45361 ; - assign op_result__h46522 = - ((IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 ^ + amoExec___d703[63:0] : + IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d724 ; + assign op_result__h64476 = + IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d997 + + IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d999 ; + assign op_result__h65203 = w1__h63703 ^ w2__h63705 ; + assign op_result__h65208 = w1__h63703 & w2__h63705 ; + assign op_result__h65213 = w1__h63703 | w2__h63705 ; + assign op_result__h65218 = + (w1__h63703 < w2__h63705) ? w1__h63703 : w2__h63705 ; + assign op_result__h65224 = + (w1__h63703 <= w2__h63705) ? w2__h63705 : w1__h63703 ; + assign op_result__h65231 = + ((IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d997 ^ 64'h8000000000000000) < - (IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ^ + (IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d999 ^ 64'h8000000000000000)) ? - w1__h45361 : - w2__h45363 ; - assign op_result__h46528 = - ((IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 ^ + w1__h63703 : + w2__h63705 ; + assign op_result__h65237 = + ((IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d997 ^ 64'h8000000000000000) <= - (IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ^ + (IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d999 ^ 64'h8000000000000000)) ? - w2__h45363 : - w1__h45361 ; - assign propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093 = - propDstData_0_dummy2_1$Q_OUT && - (CAN_FIRE_RL_srcPropose ? - propDstData_0_lat_0$wget[4] : - propDstData_0_rl[4]) ; - assign propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097 = - propDstData_1_dummy2_1$Q_OUT && - (CAN_FIRE_RL_srcPropose_1 ? - propDstData_1_lat_0$wget[4] : - propDstData_1_rl[4]) ; - assign result__h45407 = + w2__h63705 : + w1__h63703 ; + assign result__h63749 = { mmioPlatform_reqData[63:8], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0] } ; - assign result__h45531 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h45559 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h45587 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h45615 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h45643 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h45671 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h45699 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h45727 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h45772 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h45800 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h45828 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h45856 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h45897 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h45925 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h46051 = + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[7:0] } ; + assign result__h64057 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h64084 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h64111 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h64138 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h64165 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h64192 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h64219 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h64246 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h64290 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h64317 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h64344 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h64371 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h64411 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h64438 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h64563 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h46078 = + assign result__h64787 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h46105 = + assign result__h64814 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h46132 = + assign result__h64841 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h46159 = + assign result__h64868 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h46186 = + assign result__h64895 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h46213 = + assign result__h64922 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h46240 = + assign result__h64949 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h46284 = + assign result__h64993 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h46311 = + assign result__h65020 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h46338 = + assign result__h65047 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h46365 = + assign result__h65074 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h46405 = + assign result__h65114 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h46432 = + assign result__h65141 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h46549 = + assign result__h65258 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h46615 = + assign result__h65324 = { mmioPlatform_reqData[63:24], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h46681 = + assign result__h65390 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h46747 = + assign result__h65456 = { mmioPlatform_reqData[63:40], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h46813 = + assign result__h65522 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h46879 = + assign result__h65588 = { mmioPlatform_reqData[63:56], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h46945 = - { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + assign result__h65654 = + { IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h47007 = + assign result__h65716 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0] } ; - assign result__h47052 = + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[15:0] } ; + assign result__h65761 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h47118 = + assign result__h65827 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h47184 = - { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], + assign result__h65893 = + { IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h47242 = + assign result__h65951 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[31:0] } ; - assign result__h47287 = - { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[31:0], + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[31:0] } ; + assign result__h65996 = + { IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h29238 = mmioPlatform_waitUpperMSIPCRs ? v__h29275 : 32'd0 ; - assign v__h29275 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w15356_BITS_31_TO_0__q7 = w1__h45356[31:0] ; - assign w1___1__h45466 = { 32'd0, w1__h45356[31:0] } ; - assign w25357_BITS_31_TO_0__q8 = w2__h45357[31:0] ; - assign w2___1__h45467 = { 32'd0, w2__h45357[31:0] } ; - assign x1_avValue_data__h37818 = - mmioPlatform_toHostQ_empty ? - 64'd0 : - mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h42285 = - mmioPlatform_fromHostQ_empty ? - 64'd0 : - mmioPlatform_fromHostQ_data_0 ; - assign x__h111069 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h124983 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h34907 = mmioPlatform_mtimecmp_0 ; - assign x__h38336 = + assign v__h37337 = mmioPlatform_waitUpperMSIPCRs ? v__h37374 : 32'd0 ; + assign v__h37374 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign v_awaddr__h189347 = { llc$to_mem_toM_first[643:586], 6'h0 } ; + assign v_awsize_val__h15184 = + (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:133] == 4'd0 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[132:129] == 4'd0) ? + 3'b010 : + 3'b011 ; + assign w13698_BITS_31_TO_0__q11 = w1__h63698[31:0] ; + assign w1___1__h63992 = { 32'd0, w1__h63698[31:0] } ; + assign w23699_BITS_31_TO_0__q12 = w2__h63699[31:0] ; + assign w2___1__h63993 = { 32'd0, w2__h63699[31:0] } ; + assign x__h46418 = mmioPlatform_mtimecmp_0 ; + assign x__h51369 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h38347 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d676 ; - assign x__h40356 = + amoExec___d807[63:0] : + IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d828 ; + assign x__h54059 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40367 : + amoExec___d765[63:0] : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -5808,792 +6500,1045 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h47464 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h58756 = - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 ? + assign x__h75250 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__121_THEN_p_ETC___d1185 ? srcRR_0 : - NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053 ; - assign x__h72308 = + IF_propDstIdx_0_lat_0_whas__121_THEN_NOT_propD_ETC___d1187 ; + assign x__h90788 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267 ; - assign x__h77379 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 ? + IF_enqDst_1_0_lat_0_whas__345_THEN_enqDst_1_0__ETC___d1386 ; + assign x__h97352 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__254_THEN_ETC___d1418 ? srcRR_1_0 : - NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322 ; - assign x_data__h28028 = { 31'd0, mmioPlatform_reqData[0] } ; + IF_propDstIdx_1_0_lat_0_whas__254_THEN_NOT_pro_ETC___d1420 ; + assign x_data__h35020 = { 31'd0, mmioPlatform_reqData[0] } ; always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h108607 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h108607 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h108607 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h108607 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h108607 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h108607 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h108607 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h108607 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h162613 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h162613 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h162613 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h162613 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h162613 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h162613 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h162613 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h162613 = llc$dma_respLd_first[516:453]; + endcase + end + always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) + begin + case (llc_axi4_adapter_rg_wr_req_beat[0]) + 1'd0: + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1 = + llc$to_mem_toM_first[63:0]; + 1'd1: + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1 = + llc$to_mem_toM_first[127:64]; + endcase + end + always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) + begin + case (llc_axi4_adapter_rg_wr_req_beat[0]) + 1'd0: + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2 = + llc$to_mem_toM_first[191:128]; + 1'd1: + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2 = + llc$to_mem_toM_first[255:192]; + endcase + end + always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) + begin + case (llc_axi4_adapter_rg_wr_req_beat[0]) + 1'd0: + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3 = + llc$to_mem_toM_first[319:256]; + 1'd1: + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3 = + llc$to_mem_toM_first[383:320]; + endcase + end + always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) + begin + case (llc_axi4_adapter_rg_wr_req_beat[0]) + 1'd0: + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4 = + llc$to_mem_toM_first[447:384]; + 1'd1: + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4 = + llc$to_mem_toM_first[511:448]; + endcase + end + always@(llc_axi4_adapter_rg_wr_req_beat or + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1 or + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2 or + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3 or + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4) + begin + case (llc_axi4_adapter_rg_wr_req_beat[2:1]) + 2'd0: + v_wdata__h189758 = + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1; + 2'd1: + v_wdata__h189758 = + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2; + 2'd2: + v_wdata__h189758 = + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3; + 2'd3: + v_wdata__h189758 = + CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h124873 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h124873 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h124873 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h124873 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h124873 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h124873 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h124873 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h124873 = llc$to_mem_toM_first[511:448]; + 3'd0: v_wstrb__h189759 = llc$to_mem_toM_first[523:516]; + 3'd1: v_wstrb__h189759 = llc$to_mem_toM_first[531:524]; + 3'd2: v_wstrb__h189759 = llc$to_mem_toM_first[539:532]; + 3'd3: v_wstrb__h189759 = llc$to_mem_toM_first[547:540]; + 3'd4: v_wstrb__h189759 = llc$to_mem_toM_first[555:548]; + 3'd5: v_wstrb__h189759 = llc$to_mem_toM_first[563:556]; + 3'd6: v_wstrb__h189759 = llc$to_mem_toM_first[571:564]; + 3'd7: v_wstrb__h189759 = llc$to_mem_toM_first[579:572]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin - case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h124874 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h124874 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h124874 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h124874 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h124874 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h124874 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h124874 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h124874 = llc$to_mem_toM_first[575:568]; + case (llc_axi4_adapter_rg_wr_req_beat[2:1]) + 2'd0: v_wuser__h189761 = llc$to_mem_toM_first[512]; + 2'd1: v_wuser__h189761 = llc$to_mem_toM_first[513]; + 2'd2: v_wuser__h189761 = llc$to_mem_toM_first[514]; + 2'd3: v_wuser__h189761 = llc$to_mem_toM_first[515]; endcase end always@(mmioPlatform_curReq or - result__h45531 or - result__h45559 or - result__h45587 or - result__h45615 or - result__h45643 or - result__h45671 or result__h45699 or result__h45727) + result__h64290 or + result__h64317 or result__h64344 or result__h64371) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45531; - 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45559; + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d930 = + result__h64290; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45587; - 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45615; + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d930 = + result__h64317; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45643; - 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45671; + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d930 = + result__h64344; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45699; - 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45727; - endcase - end - always@(mmioPlatform_curReq or - result__h45772 or - result__h45800 or result__h45828 or result__h45856) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45772; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45800; - 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45828; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45856; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - 64'd0; - endcase - end - always@(mmioPlatform_curReq or result__h45897 or result__h45925) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h45897; - 3'h4: - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h45925; - default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0; - endcase - end - always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 or - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) - begin - case (mmioPlatform_reqSz) - 2'b0: - w2__h45357 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766; - 2'b01: - w2__h45357 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; - 2'b10: - w2__h45357 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; - 2'b11: - w2__h45357 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; - endcase - end - always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 or - w2___1__h45467 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) - begin - case (mmioPlatform_reqSz) - 2'b0: - w2__h45363 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766; - 2'b01: - w2__h45363 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; - 2'b10: w2__h45363 = w2___1__h45467; - 2'b11: - w2__h45363 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; - endcase - end - always@(mmioPlatform_curReq or - result__h46284 or - result__h46311 or result__h46338 or result__h46365) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46284; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46311; - 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46338; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46365; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d930 = + result__h64371; + default: IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d930 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h46051 or - result__h46078 or - result__h46105 or - result__h46132 or - result__h46159 or - result__h46186 or result__h46213 or result__h46240) + result__h64057 or + result__h64084 or + result__h64111 or + result__h64138 or + result__h64165 or + result__h64192 or result__h64219 or result__h64246) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46051; + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917 = + result__h64057; 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46078; + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917 = + result__h64084; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46105; + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917 = + result__h64111; 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46132; + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917 = + result__h64138; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46159; + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917 = + result__h64165; 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46186; + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917 = + result__h64192; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46213; + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917 = + result__h64219; 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46240; + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917 = + result__h64246; endcase end - always@(mmioPlatform_curReq or result__h46405 or result__h46432) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h46405; - 3'h4: - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h46432; - default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0; - endcase - end - always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 or - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837) - begin - case (mmioPlatform_reqSz) - 2'b0: - w1__h45356 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818; - 2'b01: - w1__h45356 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; - 2'b10: - w1__h45356 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; - 2'b11: - w1__h45356 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; - endcase - end - always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 or - w1___1__h45466 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837) - begin - case (mmioPlatform_reqSz) - 2'b0: - w1__h45361 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818; - 2'b01: - w1__h45361 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; - 2'b10: w1__h45361 = w1___1__h45466; - 2'b11: - w1__h45361 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; - endcase - end - always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 or - w15356_BITS_31_TO_0__q7 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837) - begin - case (mmioPlatform_reqSz) - 2'b0: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818; - 2'b01: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; - 2'b10: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - { {32{w15356_BITS_31_TO_0__q7[31]}}, w15356_BITS_31_TO_0__q7 }; - 2'b11: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; - endcase - end - always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 or - w25357_BITS_31_TO_0__q8 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) - begin - case (mmioPlatform_reqSz) - 2'b0: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766; - 2'b01: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; - 2'b10: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - { {32{w25357_BITS_31_TO_0__q8[31]}}, w25357_BITS_31_TO_0__q8 }; - 2'b11: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; - endcase - end - always@(mmioPlatform_reqAmofunc or - op_result__h46528 or - w2__h45363 or - op_result__h45964 or - op_result__h46494 or - op_result__h46499 or - op_result__h46504 or - op_result__h46522 or op_result__h46509 or op_result__h46515) - begin - case (mmioPlatform_reqAmofunc) - 4'd0: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - w2__h45363; - 4'd1: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h45964; - 4'd2: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46494; - 4'd3: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46499; - 4'd4: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46504; - 4'd5: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46522; - 4'd7: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46509; - 4'd8: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46515; - default: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46528; - endcase - end - always@(mmioPlatform_curReq or - result__h47007 or - result__h47052 or result__h47118 or result__h47184) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47007; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47052; - 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47118; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47184; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - 64'd0; - endcase - end - always@(mmioPlatform_curReq or - result__h45407 or - result__h46549 or - result__h46615 or - result__h46681 or - result__h46747 or - result__h46813 or result__h46879 or result__h46945) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h45407; - 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46549; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46615; - 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46681; - 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46747; - 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46813; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46879; - 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46945; - endcase - end - always@(mmioPlatform_curReq or result__h47242 or result__h47287) + always@(mmioPlatform_curReq or result__h64411 or result__h64438) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h47242; + result__h64411; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h47287; + result__h64438; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d930 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d938) begin case (mmioPlatform_reqSz) 2'b0: - x__h45352 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900; + w2__h63699 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917; 2'b01: - x__h45352 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909; + w2__h63699 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d930; 2'b10: - x__h45352 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; + w2__h63699 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; 2'b11: - x__h45352 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; + w2__h63699 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d938; + endcase + end + always@(mmioPlatform_reqSz or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d930 or + w2___1__h63993 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d938) + begin + case (mmioPlatform_reqSz) + 2'b0: + w2__h63705 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917; + 2'b01: + w2__h63705 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d930; + 2'b10: w2__h63705 = w2___1__h63993; + 2'b11: + w2__h63705 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d938; + endcase + end + always@(mmioPlatform_curReq or + result__h64993 or + result__h65020 or result__h65047 or result__h65074) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d982 = + result__h64993; + 3'h2: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d982 = + result__h65020; + 3'h4: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d982 = + result__h65047; + 3'h6: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d982 = + result__h65074; + default: IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d982 = + 64'd0; + endcase + end + always@(mmioPlatform_curReq or + result__h64563 or + result__h64787 or + result__h64814 or + result__h64841 or + result__h64868 or + result__h64895 or result__h64922 or result__h64949) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970 = + result__h64563; + 3'h1: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970 = + result__h64787; + 3'h2: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970 = + result__h64814; + 3'h3: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970 = + result__h64841; + 3'h4: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970 = + result__h64868; + 3'h5: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970 = + result__h64895; + 3'h6: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970 = + result__h64922; + 3'h7: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970 = + result__h64949; + endcase + end + always@(mmioPlatform_curReq or result__h65114 or result__h65141) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q10 = + result__h65114; + 3'h4: + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q10 = + result__h65141; + default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q10 = + 64'd0; + endcase + end + always@(mmioPlatform_reqSz or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d982 or + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q10 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d990) + begin + case (mmioPlatform_reqSz) + 2'b0: + w1__h63698 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970; + 2'b01: + w1__h63698 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d982; + 2'b10: + w1__h63698 = + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q10; + 2'b11: + w1__h63698 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d990; + endcase + end + always@(mmioPlatform_reqSz or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d982 or + w1___1__h63992 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d990) + begin + case (mmioPlatform_reqSz) + 2'b0: + w1__h63703 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970; + 2'b01: + w1__h63703 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d982; + 2'b10: w1__h63703 = w1___1__h63992; + 2'b11: + w1__h63703 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d990; + endcase + end + always@(mmioPlatform_reqSz or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d982 or + w13698_BITS_31_TO_0__q11 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d990) + begin + case (mmioPlatform_reqSz) + 2'b0: + IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d997 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d970; + 2'b01: + IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d997 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d982; + 2'b10: + IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d997 = + { {32{w13698_BITS_31_TO_0__q11[31]}}, + w13698_BITS_31_TO_0__q11 }; + 2'b11: + IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d997 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d990; + endcase + end + always@(mmioPlatform_reqSz or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d930 or + w23699_BITS_31_TO_0__q12 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d938) + begin + case (mmioPlatform_reqSz) + 2'b0: + IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d999 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d917; + 2'b01: + IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d999 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d930; + 2'b10: + IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d999 = + { {32{w23699_BITS_31_TO_0__q12[31]}}, + w23699_BITS_31_TO_0__q12 }; + 2'b11: + IF_mmioPlatform_reqSz_87_EQ_0b10_94_THEN_SEXT__ETC___d999 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d938; + endcase + end + always@(mmioPlatform_reqAmofunc or + op_result__h65237 or + w2__h63705 or + op_result__h64476 or + op_result__h65203 or + op_result__h65208 or + op_result__h65213 or + op_result__h65231 or op_result__h65218 or op_result__h65224) + begin + case (mmioPlatform_reqAmofunc) + 4'd0: + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029 = + w2__h63705; + 4'd1: + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029 = + op_result__h64476; + 4'd2: + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029 = + op_result__h65203; + 4'd3: + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029 = + op_result__h65208; + 4'd4: + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029 = + op_result__h65213; + 4'd5: + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029 = + op_result__h65231; + 4'd7: + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029 = + op_result__h65218; + 4'd8: + IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029 = + op_result__h65224; + default: IF_mmioPlatform_reqAmofunc_92_EQ_0_93_THEN_IF__ETC___d1029 = + op_result__h65237; + endcase + end + always@(mmioPlatform_curReq or + result__h65716 or + result__h65761 or result__h65827 or result__h65893) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1062 = + result__h65716; + 3'h2: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1062 = + result__h65761; + 3'h4: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1062 = + result__h65827; + 3'h6: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1062 = + result__h65893; + default: IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1062 = + 64'd0; + endcase + end + always@(mmioPlatform_curReq or + result__h63749 or + result__h65258 or + result__h65324 or + result__h65390 or + result__h65456 or + result__h65522 or result__h65588 or result__h65654) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1053 = + result__h63749; + 3'h1: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1053 = + result__h65258; + 3'h2: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1053 = + result__h65324; + 3'h3: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1053 = + result__h65390; + 3'h4: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1053 = + result__h65456; + 3'h5: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1053 = + result__h65522; + 3'h6: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1053 = + result__h65588; + 3'h7: + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1053 = + result__h65654; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442 = + IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d587 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442 = + IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d587 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end always@(mmioPlatform_instSel or mmio_axi4_adapter_f_rsps_to_core$D_OUT) begin case (mmioPlatform_instSel) - 1'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944 = + 2'd0: + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1099 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; - 1'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944 = + 2'd1: + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1099 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; + 2'd2: + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1099 = + mmio_axi4_adapter_f_rsps_to_core$D_OUT[95:64]; + 2'd3: + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1099 = + mmio_axi4_adapter_f_rsps_to_core$D_OUT[127:96]; + endcase + end + always@(mmioPlatform_curReq or result__h65951 or result__h65996) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = + result__h65951; + 3'h4: + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = + result__h65996; + default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = + 64'd0; + endcase + end + always@(mmioPlatform_reqSz or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1053 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1062 or + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 or + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d938) + begin + case (mmioPlatform_reqSz) + 2'b0: + IF_mmioPlatform_reqSz_87_EQ_0b0_88_THEN_IF_mmi_ETC___d1070 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1053; + 2'b01: + IF_mmioPlatform_reqSz_87_EQ_0b0_88_THEN_IF_mmi_ETC___d1070 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d1062; + 2'b10: + IF_mmioPlatform_reqSz_87_EQ_0b0_88_THEN_IF_mmi_ETC___d1070 = + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; + 2'b11: + IF_mmioPlatform_reqSz_87_EQ_0b0_88_THEN_IF_mmi_ETC___d1070 = + IF_mmioPlatform_curReq_41_BITS_2_TO_0_89_EQ_0x_ETC___d938; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520 or + IF_IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4__ETC___d668 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1: - CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = + CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q14 = core_0$RDY_mmioToPlatform_pRs_enq; - default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = - IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520; + default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q14 = + IF_IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4__ETC___d668; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586 or + IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d735 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1: - CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 = + CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q15 = core_0$RDY_mmioToPlatform_pRs_enq; - default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 = - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586; + default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q15 = + IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d735; endcase end always@(srcRR_0 or - propDstIdx_0_dummy2_1$Q_OUT or - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 or - propDstIdx_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976) + IF_propDstIdx_0_lat_0_whas__121_THEN_propDstId_ETC___d1124 or + IF_propDstIdx_1_lat_0_whas__128_THEN_propDstId_ETC___d1131) begin case (srcRR_0) 1'd0: - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 = - propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__121_THEN_p_ETC___d1185 = + IF_propDstIdx_0_lat_0_whas__121_THEN_propDstId_ETC___d1124; 1'd1: - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 = - propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__121_THEN_p_ETC___d1185 = + IF_propDstIdx_1_lat_0_whas__128_THEN_propDstId_ETC___d1131; endcase end always@(srcRR_1_0 or - propDstIdx_1_0_dummy2_1$Q_OUT or - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 or - propDstIdx_1_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145) + IF_propDstIdx_1_0_lat_0_whas__254_THEN_propDst_ETC___d1257 or + IF_propDstIdx_1_1_lat_0_whas__261_THEN_propDst_ETC___d1264) begin case (srcRR_1_0) 1'd0: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 = - propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__254_THEN_ETC___d1418 = + IF_propDstIdx_1_0_lat_0_whas__254_THEN_propDst_ETC___d1257; 1'd1: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 = - propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__254_THEN_ETC___d1418 = + IF_propDstIdx_1_1_lat_0_whas__261_THEN_propDst_ETC___d1264; endcase end - always@(x__h58756 or n__read_id__h58942 or n__read_id__h59027) + always@(x__h75250 or + CAN_FIRE_RL_srcPropose or + propDstData_0_lat_0$wget or + propDstData_0_rl or + CAN_FIRE_RL_srcPropose_1 or + propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h58756) - 1'd0: x__h59070 = n__read_id__h58942; - 1'd1: x__h59070 = n__read_id__h59027; - endcase - end - always@(x__h58756 or n__read_child__h58943 or n__read_child__h59028) - begin - case (x__h58756) - 1'd0: x__h59077 = n__read_child__h58943; - 1'd1: x__h59077 = n__read_child__h59028; - endcase - end - always@(x__h58756 or - propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093 or - propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097) - begin - case (x__h58756) + case (x__h75250) 1'd0: - CASE_x8756_0_propDstData_0_dummy2_1_read__057__ETC__q12 = - propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093; + x__h75450 = + CAN_FIRE_RL_srcPropose ? + propDstData_0_lat_0$wget[3:1] : + propDstData_0_rl[3:1]; 1'd1: - CASE_x8756_0_propDstData_0_dummy2_1_read__057__ETC__q12 = - propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097; + x__h75450 = + CAN_FIRE_RL_srcPropose_1 ? + propDstData_1_lat_0$wget[3:1] : + propDstData_1_rl[3:1]; endcase end - always@(x__h58756 or - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073 or - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077) + always@(x__h75250 or + CAN_FIRE_RL_srcPropose or + propDstData_0_lat_0$wget or + propDstData_0_rl or + CAN_FIRE_RL_srcPropose_1 or + propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h58756) + case (x__h75250) 1'd0: - CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073; + x__h75451 = + CAN_FIRE_RL_srcPropose ? + propDstData_0_lat_0$wget[0] : + propDstData_0_rl[0]; 1'd1: - CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077; + x__h75451 = + CAN_FIRE_RL_srcPropose_1 ? + propDstData_1_lat_0$wget[0] : + propDstData_1_rl[0]; endcase end - always@(x__h58756 or - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083 or - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087) + always@(x__h75250 or + CAN_FIRE_RL_srcPropose or + propDstData_0_lat_0$wget or + propDstData_0_rl or + CAN_FIRE_RL_srcPropose_1 or + propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h58756) + case (x__h75250) 1'd0: - CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083; + CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q19 = + CAN_FIRE_RL_srcPropose ? + propDstData_0_lat_0$wget[4] : + propDstData_0_rl[4]; 1'd1: - CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087; + CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q19 = + CAN_FIRE_RL_srcPropose_1 ? + propDstData_1_lat_0$wget[4] : + propDstData_1_rl[4]; endcase end - always@(x__h58756 or n__read_addr__h58938 or n__read_addr__h59023) + always@(x__h75250 or + CAN_FIRE_RL_srcPropose or + propDstData_0_lat_0$wget or + propDstData_0_rl or + CAN_FIRE_RL_srcPropose_1 or + propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h58756) + case (x__h75250) 1'd0: - CASE_x8756_0_n__read_addr8938_1_n__read_addr90_ETC__q15 = - n__read_addr__h58938; + CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q20 = + CAN_FIRE_RL_srcPropose ? + propDstData_0_lat_0$wget[8:7] : + propDstData_0_rl[8:7]; 1'd1: - CASE_x8756_0_n__read_addr8938_1_n__read_addr90_ETC__q15 = - n__read_addr__h59023; + CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q20 = + CAN_FIRE_RL_srcPropose_1 ? + propDstData_1_lat_0$wget[8:7] : + propDstData_1_rl[8:7]; endcase end - always@(x__h77379 or n__read_child__h77560 or n__read_child__h77639) + always@(x__h75250 or + CAN_FIRE_RL_srcPropose or + propDstData_0_lat_0$wget or + propDstData_0_rl or + CAN_FIRE_RL_srcPropose_1 or + propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h77379) - 1'd0: x__h79795 = n__read_child__h77560; - 1'd1: x__h79795 = n__read_child__h77639; + case (x__h75250) + 1'd0: + CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q21 = + CAN_FIRE_RL_srcPropose ? + propDstData_0_lat_0$wget[6:5] : + propDstData_0_rl[6:5]; + 1'd1: + CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q21 = + CAN_FIRE_RL_srcPropose_1 ? + propDstData_1_lat_0$wget[6:5] : + propDstData_1_rl[6:5]; endcase end - always@(x__h77379 or + always@(x__h75250 or + CAN_FIRE_RL_srcPropose or + propDstData_0_lat_0$wget or + propDstData_0_rl or + CAN_FIRE_RL_srcPropose_1 or + propDstData_1_lat_0$wget or propDstData_1_rl) + begin + case (x__h75250) + 1'd0: + CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q22 = + CAN_FIRE_RL_srcPropose ? + propDstData_0_lat_0$wget[72:9] : + propDstData_0_rl[72:9]; + 1'd1: + CASE_x5250_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q22 = + CAN_FIRE_RL_srcPropose_1 ? + propDstData_1_lat_0$wget[72:9] : + propDstData_1_rl[72:9]; + endcase + end + always@(x__h97352 or + IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1300 or + IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1338) + begin + case (x__h97352) + 1'd0: + x__h102087 = + IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1300; + 1'd1: + x__h102087 = + IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1338; + endcase + end + always@(x__h97352 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77379) + case (x__h97352) 1'd0: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h77379 or + always@(x__h97352 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77379) + case (x__h97352) 1'd0: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h77379 or + always@(x__h97352 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77379) + case (x__h97352) 1'd0: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CAN_FIRE_RL_srcPropose_2 ? + propDstData_1_0_lat_0$wget[516] : + propDstData_1_0_rl[516]; + 1'd1: + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CAN_FIRE_RL_srcPropose_3 ? + propDstData_1_1_lat_0$wget[516] : + propDstData_1_1_rl[516]; + endcase + end + always@(x__h97352 or + CAN_FIRE_RL_srcPropose_2 or + propDstData_1_0_lat_0$wget or + propDstData_1_0_rl or + CAN_FIRE_RL_srcPropose_3 or + propDstData_1_1_lat_0$wget or propDstData_1_1_rl) + begin + case (x__h97352) + 1'd0: + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CAN_FIRE_RL_srcPropose_2 ? + propDstData_1_0_lat_0$wget[515] : + propDstData_1_0_rl[515]; + 1'd1: + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CAN_FIRE_RL_srcPropose_3 ? + propDstData_1_1_lat_0$wget[515] : + propDstData_1_1_rl[515]; + endcase + end + always@(x__h97352 or + CAN_FIRE_RL_srcPropose_2 or + propDstData_1_0_lat_0$wget or + propDstData_1_0_rl or + CAN_FIRE_RL_srcPropose_3 or + propDstData_1_1_lat_0$wget or propDstData_1_1_rl) + begin + case (x__h97352) + 1'd0: + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CAN_FIRE_RL_srcPropose_2 ? + propDstData_1_0_lat_0$wget[514] : + propDstData_1_0_rl[514]; + 1'd1: + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CAN_FIRE_RL_srcPropose_3 ? + propDstData_1_1_lat_0$wget[514] : + propDstData_1_1_rl[514]; + endcase + end + always@(x__h97352 or + CAN_FIRE_RL_srcPropose_2 or + propDstData_1_0_lat_0$wget or + propDstData_1_0_rl or + CAN_FIRE_RL_srcPropose_3 or + propDstData_1_1_lat_0$wget or propDstData_1_1_rl) + begin + case (x__h97352) + 1'd0: + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h77379 or + always@(x__h97352 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77379) + case (x__h97352) 1'd0: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h77379 or + always@(x__h97352 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77379) + case (x__h97352) 1'd0: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h77379 or + always@(x__h97352 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77379) + case (x__h97352) 1'd0: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h77379 or + always@(x__h97352 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77379) + case (x__h97352) 1'd0: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q32 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q32 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h77379 or + always@(x__h97352 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77379) + case (x__h97352) 1'd0: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q33 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q33 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h77379 or - propDstData_1_0_dummy2_1$Q_OUT or - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160 or - propDstData_1_1_dummy2_1$Q_OUT or - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198) + always@(x__h97352 or + CAN_FIRE_RL_srcPropose_2 or + propDstData_1_0_lat_0$wget or + propDstData_1_0_rl or + CAN_FIRE_RL_srcPropose_3 or + propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77379) + case (x__h97352) 1'd0: - CASE_x7379_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = - propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160 : - 2'd0; + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q34 = + CAN_FIRE_RL_srcPropose_2 ? + propDstData_1_0_lat_0$wget[513] : + propDstData_1_0_rl[513]; 1'd1: - CASE_x7379_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = - propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198 : - 2'd0; + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q34 = + CAN_FIRE_RL_srcPropose_3 ? + propDstData_1_1_lat_0$wget[513] : + propDstData_1_1_rl[513]; endcase end - always@(x__h77379 or - NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338 or - NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340) + always@(x__h97352 or + IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1279 or + IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1317) begin - case (x__h77379) + case (x__h97352) 1'd0: - CASE_x7379_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = - NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338; + CASE_x7352_0_IF_propDstData_1_0_lat_0_whas__26_ETC__q35 = + IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1279; 1'd1: - CASE_x7379_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = - NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340; + CASE_x7352_0_IF_propDstData_1_0_lat_0_whas__26_ETC__q35 = + IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1317; endcase end - always@(x__h77379 or n__read_addr__h77557 or n__read_addr__h77636) + always@(x__h97352 or + CAN_FIRE_RL_srcPropose_2 or + propDstData_1_0_lat_0$wget or + propDstData_1_0_rl or + CAN_FIRE_RL_srcPropose_3 or + propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77379) + case (x__h97352) 1'd0: - CASE_x7379_0_n__read_addr7557_1_n__read_addr76_ETC__q26 = - n__read_addr__h77557; + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q36 = + CAN_FIRE_RL_srcPropose_2 ? + !propDstData_1_0_lat_0$wget[517] : + !propDstData_1_0_rl[517]; 1'd1: - CASE_x7379_0_n__read_addr7557_1_n__read_addr76_ETC__q26 = - n__read_addr__h77636; + CASE_x7352_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q36 = + CAN_FIRE_RL_srcPropose_3 ? + !propDstData_1_1_lat_0$wget[517] : + !propDstData_1_1_rl[517]; + endcase + end + always@(x__h97352 or + IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1274 or + IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1312) + begin + case (x__h97352) + 1'd0: + CASE_x7352_0_IF_propDstData_1_0_lat_0_whas__26_ETC__q37 = + IF_propDstData_1_0_lat_0_whas__269_THEN_propDs_ETC___d1274; + 1'd1: + CASE_x7352_0_IF_propDstData_1_0_lat_0_whas__26_ETC__q37 = + IF_propDstData_1_1_lat_0_whas__307_THEN_propDs_ETC___d1312; + endcase + end + always@(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read or + llc_mem_server_rg_cacheline_cache_data) + begin + case (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32]) + 3'd0: + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677 = + llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677 = + llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677 = + llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677 = + llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677 = + llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677 = + llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677 = + llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1677 = + llc_mem_server_rg_cacheline_cache_data[511:448]; + endcase + end + always@(llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read or + llc_mem_server_rg_cacheline_cache_data) + begin + case (llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[34:32]) + 3'd0: dword__h124791 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h124791 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h124791 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h124791 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h124791 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h124791 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h124791 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h124791 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -6605,26 +7550,46 @@ module mkProc(CLK, begin cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY 74'h0AAAAAAAAAAAAAAAAAA; - enqDst_0_rl_1 <= `BSV_ASSIGNMENT_DELAY 66'h0AAAAAAAAAAAAAAAA; enqDst_1_0_rl <= `BSV_ASSIGNMENT_DELAY - 581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 585'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; llc_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; llc_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; - llc_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - 1'd0; - llc_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - 1'd0; - llc_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - 1'd0; - llc_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - 1'd0; - llc_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - 1'd0; + llc_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + llc_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + llc_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + llc_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + 8'd42; + llc_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; + llc_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 75'h2AAAAAAAAAAAAAAAAAA; llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0; llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0; llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0; - llc_axi4_adapter_rg_wr_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0; + llc_mem_server_axi4_slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + 1'd0; + llc_mem_server_axi4_slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + llc_mem_server_axi4_slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + llc_mem_server_axi4_slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + 8'd42; + llc_mem_server_axi4_slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; + llc_mem_server_axi4_slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 75'h2AAAAAAAAAAAAAAAAAA; + llc_mem_server_enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY + 66'h0AAAAAAAAAAAAAAAA; + llc_mem_server_propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY + 65'h0AAAAAAAAAAAAAAAA; + llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; + llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY 64'd1; + llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY + 10'd0; + llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY 3'd3; mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY 7'd0; mmioPlatform_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0; mmioPlatform_fromHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -6636,7 +7601,7 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; mmioPlatform_mtime <= `BSV_ASSIGNMENT_DELAY 64'd0; mmioPlatform_mtimecmp_0 <= `BSV_ASSIGNMENT_DELAY 64'd0; - mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY 1'd1; mmioPlatform_state <= `BSV_ASSIGNMENT_DELAY 2'd0; mmioPlatform_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0; mmioPlatform_toHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -6649,25 +7614,25 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; - mmio_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - 1'd0; - mmio_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - 1'd0; - mmio_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - 1'd0; - mmio_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - 1'd0; - mmio_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + mmio_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + 7'd42; + mmio_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 73'h0AAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 75'h2AAAAAAAAAAAAAAAAAA; propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA; - propDstData_0_rl_1 <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA; propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY - 580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; propDstData_1_1_rl <= `BSV_ASSIGNMENT_DELAY - 580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; propDstData_1_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA; propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - propDstIdx_0_rl_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; propDstIdx_1_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; propDstIdx_1_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; propDstIdx_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -6680,8 +7645,6 @@ module mkProc(CLK, cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; if (enqDst_0_rl$EN) enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY enqDst_0_rl$D_IN; - if (enqDst_0_rl_1$EN) - enqDst_0_rl_1 <= `BSV_ASSIGNMENT_DELAY enqDst_0_rl_1$D_IN; if (enqDst_1_0_rl$EN) enqDst_1_0_rl <= `BSV_ASSIGNMENT_DELAY enqDst_1_0_rl$D_IN; if (llc_axi4_adapter_cfg_verbosity$EN) @@ -6690,21 +7653,24 @@ module mkProc(CLK, if (llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN) llc_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN; - if (llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN) - llc_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN; - if (llc_axi4_adapter_master_xactor_crg_rd_data_full$EN) - llc_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN; - if (llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN) - llc_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN; - if (llc_axi4_adapter_master_xactor_crg_wr_data_full$EN) - llc_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN; - if (llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN) - llc_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN; + if (llc_axi4_adapter_master_xactor_clearing$EN) + llc_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + llc_axi4_adapter_master_xactor_clearing$D_IN; + if (llc_axi4_adapter_master_xactor_shim_arff_rv$EN) + llc_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + llc_axi4_adapter_master_xactor_shim_arff_rv$D_IN; + if (llc_axi4_adapter_master_xactor_shim_awff_rv$EN) + llc_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + llc_axi4_adapter_master_xactor_shim_awff_rv$D_IN; + if (llc_axi4_adapter_master_xactor_shim_bff_rv$EN) + llc_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + llc_axi4_adapter_master_xactor_shim_bff_rv$D_IN; + if (llc_axi4_adapter_master_xactor_shim_rff_rv$EN) + llc_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + llc_axi4_adapter_master_xactor_shim_rff_rv$D_IN; + if (llc_axi4_adapter_master_xactor_shim_wff_rv$EN) + llc_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + llc_axi4_adapter_master_xactor_shim_wff_rv$D_IN; if (llc_axi4_adapter_rg_rd_req_beat$EN) llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_rg_rd_req_beat$D_IN; @@ -6714,9 +7680,42 @@ module mkProc(CLK, if (llc_axi4_adapter_rg_wr_req_beat$EN) llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_rg_wr_req_beat$D_IN; - if (llc_axi4_adapter_rg_wr_rsp_beat$EN) - llc_axi4_adapter_rg_wr_rsp_beat <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_rg_wr_rsp_beat$D_IN; + if (llc_mem_server_axi4_slave_xactor_clearing$EN) + llc_mem_server_axi4_slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_axi4_slave_xactor_clearing$D_IN; + if (llc_mem_server_axi4_slave_xactor_shim_arff_rv$EN) + llc_mem_server_axi4_slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_axi4_slave_xactor_shim_arff_rv$D_IN; + if (llc_mem_server_axi4_slave_xactor_shim_awff_rv$EN) + llc_mem_server_axi4_slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_axi4_slave_xactor_shim_awff_rv$D_IN; + if (llc_mem_server_axi4_slave_xactor_shim_bff_rv$EN) + llc_mem_server_axi4_slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_axi4_slave_xactor_shim_bff_rv$D_IN; + if (llc_mem_server_axi4_slave_xactor_shim_rff_rv$EN) + llc_mem_server_axi4_slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_axi4_slave_xactor_shim_rff_rv$D_IN; + if (llc_mem_server_axi4_slave_xactor_shim_wff_rv$EN) + llc_mem_server_axi4_slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_axi4_slave_xactor_shim_wff_rv$D_IN; + if (llc_mem_server_enqDst_0_rl$EN) + llc_mem_server_enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_enqDst_0_rl$D_IN; + if (llc_mem_server_propDstData_0_rl$EN) + llc_mem_server_propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_propDstData_0_rl$D_IN; + if (llc_mem_server_propDstIdx_0_rl$EN) + llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_propDstIdx_0_rl$D_IN; + if (llc_mem_server_rg_cacheline_cache_addr$EN) + llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_addr$D_IN; + if (llc_mem_server_rg_cacheline_cache_dirty_delay$EN) + llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN; + if (llc_mem_server_rg_cacheline_cache_state$EN) + llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_state$D_IN; if (mmioPlatform_cycle$EN) mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY mmioPlatform_cycle$D_IN; if (mmioPlatform_fromHostAddr$EN) @@ -6777,25 +7776,26 @@ module mkProc(CLK, if (mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN) mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN; - if (mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN) - mmio_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN; - if (mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN) - mmio_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_crg_rd_data_full$D_IN; - if (mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN) - mmio_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN; - if (mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN) - mmio_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_crg_wr_data_full$D_IN; - if (mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN) - mmio_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN; + if (mmio_axi4_adapter_master_xactor_clearing$EN) + mmio_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_master_xactor_clearing$D_IN; + if (mmio_axi4_adapter_master_xactor_shim_arff_rv$EN) + mmio_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN; + if (mmio_axi4_adapter_master_xactor_shim_awff_rv$EN) + mmio_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN; + if (mmio_axi4_adapter_master_xactor_shim_bff_rv$EN) + mmio_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN; + if (mmio_axi4_adapter_master_xactor_shim_rff_rv$EN) + mmio_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN; + if (mmio_axi4_adapter_master_xactor_shim_wff_rv$EN) + mmio_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN; if (propDstData_0_rl$EN) propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_0_rl$D_IN; - if (propDstData_0_rl_1$EN) - propDstData_0_rl_1 <= `BSV_ASSIGNMENT_DELAY propDstData_0_rl_1$D_IN; if (propDstData_1_0_rl$EN) propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_0_rl$D_IN; if (propDstData_1_1_rl$EN) @@ -6804,8 +7804,6 @@ module mkProc(CLK, propDstData_1_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_rl$D_IN; if (propDstIdx_0_rl$EN) propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_0_rl$D_IN; - if (propDstIdx_0_rl_1$EN) - propDstIdx_0_rl_1 <= `BSV_ASSIGNMENT_DELAY propDstIdx_0_rl_1$D_IN; if (propDstIdx_1_0_rl$EN) propDstIdx_1_0_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_0_rl$D_IN; if (propDstIdx_1_1_rl$EN) @@ -6815,24 +7813,12 @@ module mkProc(CLK, if (srcRR_0$EN) srcRR_0 <= `BSV_ASSIGNMENT_DELAY srcRR_0$D_IN; if (srcRR_1_0$EN) srcRR_1_0 <= `BSV_ASSIGNMENT_DELAY srcRR_1_0$D_IN; end - if (llc_axi4_adapter_master_xactor_rg_rd_addr$EN) - llc_axi4_adapter_master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN; - if (llc_axi4_adapter_master_xactor_rg_rd_data$EN) - llc_axi4_adapter_master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_master_xactor_rg_rd_data$D_IN; - if (llc_axi4_adapter_master_xactor_rg_wr_addr$EN) - llc_axi4_adapter_master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN; - if (llc_axi4_adapter_master_xactor_rg_wr_data$EN) - llc_axi4_adapter_master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_master_xactor_rg_wr_data$D_IN; - if (llc_axi4_adapter_master_xactor_rg_wr_resp$EN) - llc_axi4_adapter_master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN; if (llc_axi4_adapter_rg_cline$EN) llc_axi4_adapter_rg_cline <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_rg_cline$D_IN; + if (llc_mem_server_rg_cacheline_cache_data$EN) + llc_mem_server_rg_cacheline_cache_data <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_data$D_IN; if (mmioPlatform_amoResp$EN) mmioPlatform_amoResp <= `BSV_ASSIGNMENT_DELAY mmioPlatform_amoResp$D_IN; if (mmioPlatform_curReq$EN) @@ -6865,21 +7851,9 @@ module mkProc(CLK, if (mmioPlatform_waitUpperMSIPCRs$EN) mmioPlatform_waitUpperMSIPCRs <= `BSV_ASSIGNMENT_DELAY mmioPlatform_waitUpperMSIPCRs$D_IN; - if (mmio_axi4_adapter_master_xactor_rg_rd_addr$EN) - mmio_axi4_adapter_master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_rg_rd_addr$D_IN; - if (mmio_axi4_adapter_master_xactor_rg_rd_data$EN) - mmio_axi4_adapter_master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_rg_rd_data$D_IN; - if (mmio_axi4_adapter_master_xactor_rg_wr_addr$EN) - mmio_axi4_adapter_master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_rg_wr_addr$D_IN; - if (mmio_axi4_adapter_master_xactor_rg_wr_data$EN) - mmio_axi4_adapter_master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN; - if (mmio_axi4_adapter_master_xactor_rg_wr_resp$EN) - mmio_axi4_adapter_master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_rg_wr_resp$D_IN; + if (mmio_axi4_adapter_read_req_addr$EN) + mmio_axi4_adapter_read_req_addr <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_read_req_addr$D_IN; end // synopsys translate_off @@ -6889,28 +7863,40 @@ module mkProc(CLK, begin cfg_verbosity = 4'hA; enqDst_0_rl = 74'h2AAAAAAAAAAAAAAAAAA; - enqDst_0_rl_1 = 66'h2AAAAAAAAAAAAAAAA; enqDst_1_0_rl = - 581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 585'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; llc_axi4_adapter_cfg_verbosity = 4'hA; llc_axi4_adapter_ctr_wr_rsps_pending_crg = 4'hA; - llc_axi4_adapter_master_xactor_crg_rd_addr_full = 1'h0; - llc_axi4_adapter_master_xactor_crg_rd_data_full = 1'h0; - llc_axi4_adapter_master_xactor_crg_wr_addr_full = 1'h0; - llc_axi4_adapter_master_xactor_crg_wr_data_full = 1'h0; - llc_axi4_adapter_master_xactor_crg_wr_resp_full = 1'h0; - llc_axi4_adapter_master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - llc_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - llc_axi4_adapter_master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - llc_axi4_adapter_master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; - llc_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A; + llc_axi4_adapter_master_xactor_clearing = 1'h0; + llc_axi4_adapter_master_xactor_shim_arff_rv = + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + llc_axi4_adapter_master_xactor_shim_awff_rv = + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + llc_axi4_adapter_master_xactor_shim_bff_rv = 8'hAA; + llc_axi4_adapter_master_xactor_shim_rff_rv = 74'h2AAAAAAAAAAAAAAAAAA; + llc_axi4_adapter_master_xactor_shim_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA; llc_axi4_adapter_rg_cline = - 512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; llc_axi4_adapter_rg_rd_req_beat = 3'h2; llc_axi4_adapter_rg_rd_rsp_beat = 3'h2; llc_axi4_adapter_rg_wr_req_beat = 3'h2; - llc_axi4_adapter_rg_wr_rsp_beat = 3'h2; - mmioPlatform_amoResp = 64'hAAAAAAAAAAAAAAAA; + llc_mem_server_axi4_slave_xactor_clearing = 1'h0; + llc_mem_server_axi4_slave_xactor_shim_arff_rv = + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + llc_mem_server_axi4_slave_xactor_shim_awff_rv = + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + llc_mem_server_axi4_slave_xactor_shim_bff_rv = 8'hAA; + llc_mem_server_axi4_slave_xactor_shim_rff_rv = 74'h2AAAAAAAAAAAAAAAAAA; + llc_mem_server_axi4_slave_xactor_shim_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA; + llc_mem_server_enqDst_0_rl = 66'h2AAAAAAAAAAAAAAAA; + llc_mem_server_propDstData_0_rl = 65'h0AAAAAAAAAAAAAAAA; + llc_mem_server_propDstIdx_0_rl = 1'h0; + llc_mem_server_rg_cacheline_cache_addr = 64'hAAAAAAAAAAAAAAAA; + llc_mem_server_rg_cacheline_cache_data = + 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + llc_mem_server_rg_cacheline_cache_dirty_delay = 10'h2AA; + llc_mem_server_rg_cacheline_cache_state = 3'h2; + mmioPlatform_amoResp = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmioPlatform_curReq = 67'h2AAAAAAAAAAAAAAAA; mmioPlatform_cycle = 7'h2A; mmioPlatform_fetchedInsts_0 = 32'hAAAAAAAA; @@ -6922,13 +7908,13 @@ module mkProc(CLK, mmioPlatform_fromHostQ_empty = 1'h0; mmioPlatform_fromHostQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA; mmioPlatform_fromHostQ_full = 1'h0; - mmioPlatform_instSel = 1'h0; + mmioPlatform_instSel = 2'h2; mmioPlatform_mtime = 64'hAAAAAAAAAAAAAAAA; mmioPlatform_mtimecmp_0 = 64'hAAAAAAAAAAAAAAAA; mmioPlatform_mtip_0 = 1'h0; mmioPlatform_reqAmofunc = 4'hA; - mmioPlatform_reqBE = 8'hAA; - mmioPlatform_reqData = 64'hAAAAAAAAAAAAAAAA; + mmioPlatform_reqBE = 16'hAAAA; + mmioPlatform_reqData = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; mmioPlatform_reqFunc = 6'h2A; mmioPlatform_reqSz = 2'h2; mmioPlatform_state = 2'h2; @@ -6944,27 +7930,22 @@ module mkProc(CLK, mmioPlatform_waitUpperMSIPCRs = 1'h0; mmio_axi4_adapter_cfg_verbosity = 4'hA; mmio_axi4_adapter_ctr_wr_rsps_pending_crg = 4'hA; - mmio_axi4_adapter_master_xactor_crg_rd_addr_full = 1'h0; - mmio_axi4_adapter_master_xactor_crg_rd_data_full = 1'h0; - mmio_axi4_adapter_master_xactor_crg_wr_addr_full = 1'h0; - mmio_axi4_adapter_master_xactor_crg_wr_data_full = 1'h0; - mmio_axi4_adapter_master_xactor_crg_wr_resp_full = 1'h0; - mmio_axi4_adapter_master_xactor_rg_rd_addr = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_rg_wr_addr = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A; + mmio_axi4_adapter_master_xactor_clearing = 1'h0; + mmio_axi4_adapter_master_xactor_shim_arff_rv = + 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_master_xactor_shim_awff_rv = + 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_master_xactor_shim_bff_rv = 7'h2A; + mmio_axi4_adapter_master_xactor_shim_rff_rv = 73'h0AAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_master_xactor_shim_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_read_req_addr = 64'hAAAAAAAAAAAAAAAA; propDstData_0_rl = 73'h0AAAAAAAAAAAAAAAAAA; - propDstData_0_rl_1 = 65'h0AAAAAAAAAAAAAAAA; propDstData_1_0_rl = - 580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; propDstData_1_1_rl = - 580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + 584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; propDstData_1_rl = 73'h0AAAAAAAAAAAAAAAAAA; propDstIdx_0_rl = 1'h0; - propDstIdx_0_rl_1 = 1'h0; propDstIdx_1_0_rl = 1'h0; propDstIdx_1_1_rl = 1'h0; propDstIdx_1_rl = 1'h0; @@ -6982,7 +7963,15 @@ module mkProc(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (EN_start) - $display("Proc.start: startpc = 0x%0h, tohostAddr = 0x%0h, fromhostAddr = %0h", + begin + v__h198549 = $stime; + #0; + end + v__h198543 = v__h198549 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_start) + $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", + v__h198543, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -6991,7 +7980,15 @@ module mkProc(CLK, $display("Core %d terminated", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) - $display("mmioPlatform.rl_tohost: 0x%0x (= %0d)", + begin + v__h198090 = $stime; + #0; + end + v__h198084 = v__h198090 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_tohost) + $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", + v__h198084, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -7001,203 +7998,22 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h139642); + $display("FAIL %0d", failed_testnum__h198133); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - begin - v__h4198 = $stime; - #0; - end - v__h4192 = v__h4198 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4192); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - begin - v__h4371 = $stime; - #0; - end - v__h4365 = v__h4371 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsp: fabric response error", - v__h4365); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 && - !mmio_axi4_adapter_master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" Response MMIO to core: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("MMIODataPRs { ", "valid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] == 2'b0) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_rg_rd_data[66:3], - " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4635 = $stime; + v__h11334 = $stime; #0; end - v__h4629 = v__h4635 / 32'd10; + v__h11328 = v__h11334 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: MMIO_AXI4_Adapter.rl_handle_write_req: St request:", - v__h4629); + $display("%d: %m.rl_handle_write_req: St request:", v__h11328); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7209,7 +8025,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]); + $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7233,12 +8049,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[64]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[129]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[64]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[129]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -7247,12 +8063,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[65]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[130]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[65]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[130]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -7261,12 +8077,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[66]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[131]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[66]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[131]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -7275,12 +8091,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[67]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[132]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[67]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[132]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -7289,12 +8105,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[68]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[133]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[68]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[133]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -7303,12 +8119,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[69]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[134]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[69]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[134]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -7317,12 +8133,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[70]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[135]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[70]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[135]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -7331,12 +8147,124 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[71]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[136]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[71]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[136]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[137]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[137]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[138]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[138]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[139]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[139]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[140]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[140]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[141]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[141]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[142]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[142]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[143]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[143]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[144]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -7357,184 +8285,488 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " }"); + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h6674 = $stime; + v__h15872 = $stime; #0; end - v__h6668 = v__h6674 / 32'd10; + v__h15866 = v__h15872 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h6668); + $display("%0d: ERROR: CreditCounter: overflow", v__h15866); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" To fabric: "); + begin + v__h16015 = $stime; + #0; + end + v__h16009 = v__h16015 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); + $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", + v__h16009); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 4'd0); + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); + $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]); + $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); + $write(", ", "func: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 8'd0); + $write("tagged St ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); + $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 3'b011); + $write(", ", "byteEn: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2474 = $stime; + v__h4355 = $stime; #0; end - v__h2468 = v__h2474 / 32'd10; + v__h4349 = v__h4355 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_req: Ld request", - v__h2468); + $display("%0d: %m.rl_handle_read_req: Ld request", v__h4349); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7546,7 +8778,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]); + $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7570,12 +8802,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[64]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[129]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[64]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[129]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && @@ -7584,12 +8816,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[65]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[130]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[65]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[130]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && @@ -7598,12 +8830,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[66]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[131]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[66]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[131]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && @@ -7612,12 +8844,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[67]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[132]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[67]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[132]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && @@ -7626,12 +8858,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[68]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[133]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[68]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[133]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && @@ -7640,12 +8872,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[69]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[134]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[69]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[134]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && @@ -7654,12 +8886,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[70]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[135]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[70]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[135]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && @@ -7668,12 +8900,124 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[71]) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[136]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_f_reqs_from_core$D_OUT[71]) + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[136]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[137]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[137]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[138]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[138]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[139]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[139]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[140]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[140]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[141]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[141]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[142]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[142]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[143]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[143]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[144]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && @@ -7694,211 +9038,593 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " }"); + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]); + $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 3'b011); + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", 3'b011, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 2'b01); + $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 1'b0); + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 1'h0, " }"); + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h6975 = $stime; + v__h7976 = $stime; #0; end - v__h6969 = v__h6975 / 32'd10; + v__h7970 = v__h7976 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6969); + $display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response", + v__h7970); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); + $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", mmio_axi4_adapter_master_xactor_rg_wr_resp[5:2]); + $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); + $write(", ", "func: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0]); + $write("tagged Ld ", ""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "buser: "); + $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); + $write(", ", "byteEn: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_f_reqs_from_core$D_OUT[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - begin - v__h7468 = $stime; - #0; - end - v__h7462 = v__h7468 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h7462); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", mmio_axi4_adapter_master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h7631 = $stime; + v__h19401 = $stime; #0; end - v__h7625 = v__h7631 / 32'd10; + v__h19395 = v__h19401 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) - $display("%0d: ERROR: MMIO_AXI4_Adapter.rl_handle_non_Ld_St", - v__h7625); + $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", + v__h19395); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -7906,81 +9632,81 @@ module mkProc(CLK, $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) - $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]); + $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(", ", "func: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd0) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd0) $write("tagged Inst ", "'h%h", - mmio_axi4_adapter_f_reqs_from_core$D_OUT[72]); + mmio_axi4_adapter_f_reqs_from_core$D_OUT[145]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0) $write("tagged Amo "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd0) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd0) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd0) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd0) $write("Swap"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd1) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd1) $write("Add"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd2) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd2) $write("Xor"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd3) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd3) $write("And"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd4) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd4) $write("Or"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd5) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd5) $write("Min"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd6) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd6) $write("Max"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd7) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd7) $write("Minu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd8) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd8) $write("Maxu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd1 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd2 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd3 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd4 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd5 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd6 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd7 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd8) + mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd0 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd1 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd2 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd3 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd4 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd5 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd6 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd7 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd8) $write("None"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) @@ -7989,81 +9715,161 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h111433 = $stime; + v__h18404 = $stime; #0; end - v__h111427 = v__h111433 / 32'd10; + v__h18398 = v__h18404 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h111427, - llc_axi4_adapter_rg_rd_rsp_beat); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_discard_write_rsp", v__h18398); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("AXI4_Rd_Data { ", "rid: "); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("AXI4_BFlit { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[5:2]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "rdata: "); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == + 2'd0) + $write("OKAY"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "rresp: "); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == + 2'd1) + $write("EXOKAY"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == + 2'd2) + $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "rlast: "); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0 && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd1 && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd2) + $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616 && - llc_axi4_adapter_master_xactor_rg_rd_data[0]) - $write("True"); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616 && - !llc_axi4_adapter_master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0) begin - v__h111600 = $stime; + v__h18934 = $stime; #0; end - v__h111594 = v__h111600 / 32'd10; + v__h18928 = v__h18934 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h111594); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0) + $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", + v__h18928); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write("AXI4_Rd_Data { ", "rid: "); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0) + $write("AXI4_BFlit { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0) + $write("'h%h", + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[5:2]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write(", ", "rdata: "); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0) + $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == + 2'd1) + $write("EXOKAY"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write(", ", "rresp: "); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == + 2'd2) + $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0 && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd1 && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd2) + $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write(", ", "rlast: "); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0) + $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 && - llc_axi4_adapter_master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 && - !llc_axi4_adapter_master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(" Response to LLC: "); + if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("MemRsMsg { ", "data: "); + if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(""); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == + 2'd2) + $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "child: "); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd1 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd2) + $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(""); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("LdMemRqId { ", "refill: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616 && - llc_axi4_adapter_f_pending_reads$D_OUT[4]) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("True"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616 && - !llc_axi4_adapter_f_pending_reads$D_OUT[4]) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "mshrIdx: "); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], + " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0) + begin + v__h10590 = $stime; + #0; + end + v__h10584 = v__h10590 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0) + $display("%0d: %m.rl_handle_read_rsp: fabric response error", + v__h10584); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0) + $write("'h%h", + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[71:68]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0) + $write("'h%h", + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == + 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == + 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd1 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0 && + !mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0) + $write("'h%h", + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], + " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" Response MMIO to core: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("MMIODataPRs { ", "valid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == + 2'd0) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) $write(" }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h113703 = $stime; + v__h175741 = $stime; #0; end - v__h113697 = v__h113703 / 32'd10; + v__h175735 = v__h175741 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h113697); + v__h175735); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -8366,7 +10400,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) - $write("'h%h", llc$to_mem_toM_first[639:576]); + $write("'h%h", llc$to_mem_toM_first[643:580]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -8377,74 +10411,11 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(" >"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write("CLine { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(" >"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_cfg_verbosity != 4'd0 && + llc_axi4_adapter_rg_wr_req_beat == 3'd0) + $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -9547,179 +11839,38 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h131049 = $stime; + v__h189450 = $stime; #0; end - v__h131043 = v__h131049 / 32'd10; + v__h189444 = v__h189450 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h131043); + $display("%0d: ERROR: CreditCounter: overflow", v__h189444); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && + llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", mem_req_wr_addr_awaddr__h124958); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", data64__h124873); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", strb8__h124874); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h110814 = $stime; + v__h167720 = $stime; #0; end - v__h110808 = v__h110814 / 32'd10; + v__h167714 = v__h167720 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h110808, + v__h167714, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -9790,195 +11941,669 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("AXI4_Rd_Addr { ", "arid: "); + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 4'd0); + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("'h%h", 5'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", mem_req_rd_addr_araddr__h111034); + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("'h%h", line_addr__h167856); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 8'd0); + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("'h%h", 8'd7); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 3'b011); + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("'h%h", 3'b011, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 2'b01); + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 1'b0); + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 1'h0, " }"); + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) begin - v__h137744 = $stime; + v__h197076 = $stime; #0; end - v__h137738 = v__h137744 / 32'd10; + v__h197070 = v__h197076 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h137738, - llc_axi4_adapter_rg_wr_rsp_beat); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - begin - v__h138252 = $stime; - #0; - end - v__h138246 = v__h138252 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h138246); + v__h197070); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("AXI4_Wr_Resp { ", "bid: "); + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("AXI4_BFlit { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("'h%h", + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[6:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd1) + $write("EXOKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd0 && + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != + 2'd1 && + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) + llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $finish(32'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + begin + v__h168309 = $stime; + #0; + end + v__h168303 = v__h168309 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", + v__h168303, + llc_axi4_adapter_rg_rd_rsp_beat); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("'h%h", + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72:68]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("'h%h", + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd1 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946 && + !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("'h%h", + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], + " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) + begin + v__h168495 = $stime; + #0; + end + v__h168489 = v__h168495 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) + $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", + v__h168489); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) + $write("'h%h", + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72:68]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) + $write("'h%h", + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd1 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != + 2'd0 && + !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) + $write("'h%h", + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], + " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) + $finish(32'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(" Response to LLC: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("MemRsMsg { ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("CLine { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(" >"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(", ", "child: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(", ", "id: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("LdMemRqId { ", "refill: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946 && + llc_axi4_adapter_f_pending_reads$D_OUT[4]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946 && + !llc_axi4_adapter_f_pending_reads$D_OUT[4]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(", ", "mshrIdx: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && + llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && + NOT_llc_axi4_adapter_cfg_verbosity_read__928_U_ETC___d1946) + $write("\n"); end // synopsys translate_on endmodule // mkProc diff --git a/src_SSITH_P3/Verilog_RTL/mkTagController.v b/src_SSITH_P3/Verilog_RTL/mkTagController.v new file mode 100644 index 0000000..eb9b254 --- /dev/null +++ b/src_SSITH_P3/Verilog_RTL/mkTagController.v @@ -0,0 +1,18520 @@ +// +// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// +// On Fri Jun 5 13:58:22 BST 2020 +// +// +// Ports: +// Name I/O size props +// cache_request_canPut O 1 +// RDY_cache_request_put O 1 +// cache_response_canGet O 1 +// cache_response_peek O 77 +// RDY_cache_response_peek O 1 const +// cache_response_get O 77 +// RDY_cache_response_get O 1 +// memory_request_canGet O 1 +// memory_request_peek O 141 +// RDY_memory_request_peek O 1 +// memory_request_get O 141 +// RDY_memory_request_get O 1 +// memory_response_canPut O 1 +// RDY_memory_response_put O 1 +// CLK I 1 clock +// RST_N I 1 reset +// cache_request_put_val I 141 +// memory_response_put_val I 77 +// EN_cache_request_put I 1 +// EN_memory_response_put I 1 +// EN_cache_response_get I 1 +// EN_memory_request_get I 1 +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkTagController(CLK, + RST_N, + + cache_request_canPut, + + cache_request_put_val, + EN_cache_request_put, + RDY_cache_request_put, + + cache_response_canGet, + + cache_response_peek, + RDY_cache_response_peek, + + EN_cache_response_get, + cache_response_get, + RDY_cache_response_get, + + memory_request_canGet, + + memory_request_peek, + RDY_memory_request_peek, + + EN_memory_request_get, + memory_request_get, + RDY_memory_request_get, + + memory_response_canPut, + + memory_response_put_val, + EN_memory_response_put, + RDY_memory_response_put); + input CLK; + input RST_N; + + // value method cache_request_canPut + output cache_request_canPut; + + // action method cache_request_put + input [140 : 0] cache_request_put_val; + input EN_cache_request_put; + output RDY_cache_request_put; + + // value method cache_response_canGet + output cache_response_canGet; + + // value method cache_response_peek + output [76 : 0] cache_response_peek; + output RDY_cache_response_peek; + + // actionvalue method cache_response_get + input EN_cache_response_get; + output [76 : 0] cache_response_get; + output RDY_cache_response_get; + + // value method memory_request_canGet + output memory_request_canGet; + + // value method memory_request_peek + output [140 : 0] memory_request_peek; + output RDY_memory_request_peek; + + // actionvalue method memory_request_get + input EN_memory_request_get; + output [140 : 0] memory_request_get; + output RDY_memory_request_get; + + // value method memory_response_canPut + output memory_response_canPut; + + // action method memory_response_put + input [76 : 0] memory_response_put_val; + input EN_memory_response_put; + output RDY_memory_response_put; + + // signals for module outputs + wire [140 : 0] memory_request_get, memory_request_peek; + wire [76 : 0] cache_response_get, cache_response_peek; + wire RDY_cache_request_put, + RDY_cache_response_get, + RDY_cache_response_peek, + RDY_memory_request_get, + RDY_memory_request_peek, + RDY_memory_response_put, + cache_request_canPut, + cache_response_canGet, + memory_request_canGet, + memory_response_canPut; + + // inlined wires + wire [232 : 0] tagLookup_tagCache_resps$wget; + wire [141 : 0] tagLookup_tagCache_newReq$wget; + wire [58 : 0] tagLookup_tagCache_orderer_mastReqs_insertItem$wget, + tagLookup_tagCache_orderer_slaveReqs_insertItem$wget; + wire [41 : 0] tagLookup_tagCache_orderer_mastLines_insertItem$wget, + tagLookup_tagCache_orderer_slaveAddrs_insertItem$wget; + wire [35 : 0] tagLookup_tagCache_orderer_slaveAddrs_removeItem$wget; + wire [17 : 0] lookupRsp_insertItem$wget; + wire [15 : 0] addrFrame_insertItem$wget, + tagLookup_tagCache_req_commits_rf$port0__write_1, + tagLookup_tagCache_req_commits_rf$port1__read; + wire [12 : 0] tagLookup_tagCache_orderer_slaveDeps_insertItem$wget, + tagLookup_tagCache_orderer_slaveDeps_updateItem$wget; + wire [6 : 0] lookupRsp_removeItem$wget, + tagLookup_tagCache_orderer_mastReqs_removeItem$wget, + tagLookup_tagCache_retryReqs_removeItem$wget; + wire [4 : 0] tagLookup_tagCache_req_commits_level$port0__write_1, + tagLookup_tagCache_req_commits_level$port1__write_1, + tagLookup_tagCache_req_commits_level$port2__read; + wire lookupRsp_removeItem$whas, + tagLookup_getReq$whas, + tagLookup_readReqs_ff_full$EN_port1__write, + tagLookup_readReqs_ff_full$port1__read, + tagLookup_readReqs_ff_full$port2__read, + tagLookup_tagCache_missedResp$wget, + tagLookup_tagCache_missedResp$whas, + tagLookup_tagCache_orderer_mastReqs_insertItem$whas, + tagLookup_tagCache_orderer_mastReqs_removeItem$whas, + tagLookup_tagCache_orderer_slaveDeps_updateItem$whas, + tagLookup_tagCache_respsReady$wget; + + // register addrFrame_bag + reg [15 : 0] addrFrame_bag; + wire [15 : 0] addrFrame_bag$D_IN; + wire addrFrame_bag$EN; + + // register frame + reg [2 : 0] frame; + wire [2 : 0] frame$D_IN; + wire frame$EN; + + // register lookupRsp_bag + reg [17 : 0] lookupRsp_bag; + wire [17 : 0] lookupRsp_bag$D_IN; + wire lookupRsp_bag$EN; + + // register mReqs_ff_lhead + reg [1 : 0] mReqs_ff_lhead; + wire [1 : 0] mReqs_ff_lhead$D_IN; + wire mReqs_ff_lhead$EN; + + // register mReqs_ff_ltail + reg [1 : 0] mReqs_ff_ltail; + wire [1 : 0] mReqs_ff_ltail$D_IN; + wire mReqs_ff_ltail$EN; + + // register mRsps_ff_lhead + reg [5 : 0] mRsps_ff_lhead; + wire [5 : 0] mRsps_ff_lhead$D_IN; + wire mRsps_ff_lhead$EN; + + // register mRsps_ff_ltail + reg [5 : 0] mRsps_ff_ltail; + wire [5 : 0] mRsps_ff_ltail$D_IN; + wire mRsps_ff_ltail$EN; + + // register nextId + reg [4 : 0] nextId; + wire [4 : 0] nextId$D_IN; + wire nextId$EN; + + // register tagLookup_currentDepth + reg [1 : 0] tagLookup_currentDepth; + wire [1 : 0] tagLookup_currentDepth$D_IN; + wire tagLookup_currentDepth$EN; + + // register tagLookup_lookupRsp_ff_lhead + reg tagLookup_lookupRsp_ff_lhead; + wire tagLookup_lookupRsp_ff_lhead$D_IN, tagLookup_lookupRsp_ff_lhead$EN; + + // register tagLookup_lookupRsp_ff_ltail + reg tagLookup_lookupRsp_ff_ltail; + wire tagLookup_lookupRsp_ff_ltail$D_IN, tagLookup_lookupRsp_ff_ltail$EN; + + // register tagLookup_lookupRsp_ff_rf + reg [3 : 0] tagLookup_lookupRsp_ff_rf; + wire [3 : 0] tagLookup_lookupRsp_ff_rf$D_IN; + wire tagLookup_lookupRsp_ff_rf$EN; + + // register tagLookup_mReqs_ff_lhead + reg [3 : 0] tagLookup_mReqs_ff_lhead; + wire [3 : 0] tagLookup_mReqs_ff_lhead$D_IN; + wire tagLookup_mReqs_ff_lhead$EN; + + // register tagLookup_mReqs_ff_ltail + reg [3 : 0] tagLookup_mReqs_ff_ltail; + wire [3 : 0] tagLookup_mReqs_ff_ltail$D_IN; + wire tagLookup_mReqs_ff_ltail$EN; + + // register tagLookup_mRsps_ff_lhead + reg [1 : 0] tagLookup_mRsps_ff_lhead; + wire [1 : 0] tagLookup_mRsps_ff_lhead$D_IN; + wire tagLookup_mRsps_ff_lhead$EN; + + // register tagLookup_mRsps_ff_ltail + reg [1 : 0] tagLookup_mRsps_ff_ltail; + wire [1 : 0] tagLookup_mRsps_ff_ltail$D_IN; + wire tagLookup_mRsps_ff_ltail$EN; + + // register tagLookup_oldTags_0 + reg [63 : 0] tagLookup_oldTags_0; + reg [63 : 0] tagLookup_oldTags_0$D_IN; + wire tagLookup_oldTags_0$EN; + + // register tagLookup_oldTags_1 + reg [63 : 0] tagLookup_oldTags_1; + reg [63 : 0] tagLookup_oldTags_1$D_IN; + wire tagLookup_oldTags_1$EN; + + // register tagLookup_pendingCapEnable + reg tagLookup_pendingCapEnable; + wire tagLookup_pendingCapEnable$D_IN, tagLookup_pendingCapEnable$EN; + + // register tagLookup_pendingCapNumber + reg [35 : 0] tagLookup_pendingCapNumber; + wire [35 : 0] tagLookup_pendingCapNumber$D_IN; + wire tagLookup_pendingCapNumber$EN; + + // register tagLookup_pendingTags + reg tagLookup_pendingTags; + wire tagLookup_pendingTags$D_IN, tagLookup_pendingTags$EN; + + // register tagLookup_readReqs_ff_dataReg + reg tagLookup_readReqs_ff_dataReg; + wire tagLookup_readReqs_ff_dataReg$D_IN, tagLookup_readReqs_ff_dataReg$EN; + + // register tagLookup_readReqs_ff_full + reg tagLookup_readReqs_ff_full; + wire tagLookup_readReqs_ff_full$D_IN, tagLookup_readReqs_ff_full$EN; + + // register tagLookup_reqeustId + reg [5 : 0] tagLookup_reqeustId; + wire [5 : 0] tagLookup_reqeustId$D_IN; + wire tagLookup_reqeustId$EN; + + // register tagLookup_state + reg [2 : 0] tagLookup_state; + reg [2 : 0] tagLookup_state$D_IN; + wire tagLookup_state$EN; + + // register tagLookup_tagCacheReq_ff_lhead + reg tagLookup_tagCacheReq_ff_lhead; + reg tagLookup_tagCacheReq_ff_lhead$D_IN; + wire tagLookup_tagCacheReq_ff_lhead$EN; + + // register tagLookup_tagCacheReq_ff_ltail + reg tagLookup_tagCacheReq_ff_ltail; + wire tagLookup_tagCacheReq_ff_ltail$D_IN, tagLookup_tagCacheReq_ff_ltail$EN; + + // register tagLookup_tagCacheReq_ff_rf + reg [140 : 0] tagLookup_tagCacheReq_ff_rf; + reg [140 : 0] tagLookup_tagCacheReq_ff_rf$D_IN; + wire tagLookup_tagCacheReq_ff_rf$EN; + + // register tagLookup_tagCache_cacheState + reg tagLookup_tagCache_cacheState; + wire tagLookup_tagCache_cacheState$D_IN, tagLookup_tagCache_cacheState$EN; + + // register tagLookup_tagCache_cts + reg [278 : 0] tagLookup_tagCache_cts; + wire [278 : 0] tagLookup_tagCache_cts$D_IN; + wire tagLookup_tagCache_cts$EN; + + // register tagLookup_tagCache_data_0_readAddr + reg [9 : 0] tagLookup_tagCache_data_0_readAddr; + wire [9 : 0] tagLookup_tagCache_data_0_readAddr$D_IN; + wire tagLookup_tagCache_data_0_readAddr$EN; + + // register tagLookup_tagCache_data_0_writeAddr + reg [9 : 0] tagLookup_tagCache_data_0_writeAddr; + wire [9 : 0] tagLookup_tagCache_data_0_writeAddr$D_IN; + wire tagLookup_tagCache_data_0_writeAddr$EN; + + // register tagLookup_tagCache_data_0_writeData + reg [63 : 0] tagLookup_tagCache_data_0_writeData; + wire [63 : 0] tagLookup_tagCache_data_0_writeData$D_IN; + wire tagLookup_tagCache_data_0_writeData$EN; + + // register tagLookup_tagCache_data_1_readAddr + reg [9 : 0] tagLookup_tagCache_data_1_readAddr; + wire [9 : 0] tagLookup_tagCache_data_1_readAddr$D_IN; + wire tagLookup_tagCache_data_1_readAddr$EN; + + // register tagLookup_tagCache_data_1_writeAddr + reg [9 : 0] tagLookup_tagCache_data_1_writeAddr; + wire [9 : 0] tagLookup_tagCache_data_1_writeAddr$D_IN; + wire tagLookup_tagCache_data_1_writeAddr$EN; + + // register tagLookup_tagCache_data_1_writeData + reg [63 : 0] tagLookup_tagCache_data_1_writeData; + wire [63 : 0] tagLookup_tagCache_data_1_writeData$D_IN; + wire tagLookup_tagCache_data_1_writeData$EN; + + // register tagLookup_tagCache_delayedInvalidates_ff_lhead + reg [3 : 0] tagLookup_tagCache_delayedInvalidates_ff_lhead; + wire [3 : 0] tagLookup_tagCache_delayedInvalidates_ff_lhead$D_IN; + wire tagLookup_tagCache_delayedInvalidates_ff_lhead$EN; + + // register tagLookup_tagCache_delayedInvalidates_ff_ltail + reg [3 : 0] tagLookup_tagCache_delayedInvalidates_ff_ltail; + wire [3 : 0] tagLookup_tagCache_delayedInvalidates_ff_ltail$D_IN; + wire tagLookup_tagCache_delayedInvalidates_ff_ltail$EN; + + // register tagLookup_tagCache_initCount + reg [7 : 0] tagLookup_tagCache_initCount; + wire [7 : 0] tagLookup_tagCache_initCount$D_IN; + wire tagLookup_tagCache_initCount$EN; + + // register tagLookup_tagCache_invalidateWritebackWriteBank + reg [1 : 0] tagLookup_tagCache_invalidateWritebackWriteBank; + wire [1 : 0] tagLookup_tagCache_invalidateWritebackWriteBank$D_IN; + wire tagLookup_tagCache_invalidateWritebackWriteBank$EN; + + // register tagLookup_tagCache_invalidatesDone_ff_lhead + reg [5 : 0] tagLookup_tagCache_invalidatesDone_ff_lhead; + wire [5 : 0] tagLookup_tagCache_invalidatesDone_ff_lhead$D_IN; + wire tagLookup_tagCache_invalidatesDone_ff_lhead$EN; + + // register tagLookup_tagCache_invalidatesDone_ff_ltail + reg [5 : 0] tagLookup_tagCache_invalidatesDone_ff_ltail; + wire [5 : 0] tagLookup_tagCache_invalidatesDone_ff_ltail$D_IN; + wire tagLookup_tagCache_invalidatesDone_ff_ltail$EN; + + // register tagLookup_tagCache_invalidates_ff_lhead + reg [2 : 0] tagLookup_tagCache_invalidates_ff_lhead; + wire [2 : 0] tagLookup_tagCache_invalidates_ff_lhead$D_IN; + wire tagLookup_tagCache_invalidates_ff_lhead$EN; + + // register tagLookup_tagCache_invalidates_ff_ltail + reg [2 : 0] tagLookup_tagCache_invalidates_ff_ltail; + wire [2 : 0] tagLookup_tagCache_invalidates_ff_ltail$D_IN; + wire tagLookup_tagCache_invalidates_ff_ltail$EN; + + // register tagLookup_tagCache_nextEmpty + reg tagLookup_tagCache_nextEmpty; + wire tagLookup_tagCache_nextEmpty$D_IN, tagLookup_tagCache_nextEmpty$EN; + + // register tagLookup_tagCache_nextWay + reg tagLookup_tagCache_nextWay; + wire tagLookup_tagCache_nextWay$D_IN, tagLookup_tagCache_nextWay$EN; + + // register tagLookup_tagCache_orderer_lookupState + reg [12 : 0] tagLookup_tagCache_orderer_lookupState; + wire [12 : 0] tagLookup_tagCache_orderer_lookupState$D_IN; + wire tagLookup_tagCache_orderer_lookupState$EN; + + // register tagLookup_tagCache_orderer_mastLines_bag + reg [671 : 0] tagLookup_tagCache_orderer_mastLines_bag; + wire [671 : 0] tagLookup_tagCache_orderer_mastLines_bag$D_IN; + wire tagLookup_tagCache_orderer_mastLines_bag$EN; + + // register tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + reg [3 : 0] tagLookup_tagCache_orderer_mastLines_nextValidKeyReg; + wire [3 : 0] tagLookup_tagCache_orderer_mastLines_nextValidKeyReg$D_IN; + wire tagLookup_tagCache_orderer_mastLines_nextValidKeyReg$EN; + + // register tagLookup_tagCache_orderer_mastReqIds_lhead + reg [4 : 0] tagLookup_tagCache_orderer_mastReqIds_lhead; + wire [4 : 0] tagLookup_tagCache_orderer_mastReqIds_lhead$D_IN; + wire tagLookup_tagCache_orderer_mastReqIds_lhead$EN; + + // register tagLookup_tagCache_orderer_mastReqIds_rf + reg [79 : 0] tagLookup_tagCache_orderer_mastReqIds_rf; + wire [79 : 0] tagLookup_tagCache_orderer_mastReqIds_rf$D_IN; + wire tagLookup_tagCache_orderer_mastReqIds_rf$EN; + + // register tagLookup_tagCache_orderer_mastReqs_bag + reg [943 : 0] tagLookup_tagCache_orderer_mastReqs_bag; + wire [943 : 0] tagLookup_tagCache_orderer_mastReqs_bag$D_IN; + wire tagLookup_tagCache_orderer_mastReqs_bag$EN; + + // register tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + reg [3 : 0] tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg; + wire [3 : 0] tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg$D_IN; + wire tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg$EN; + + // register tagLookup_tagCache_orderer_mastRespState + reg [12 : 0] tagLookup_tagCache_orderer_mastRespState; + wire [12 : 0] tagLookup_tagCache_orderer_mastRespState$D_IN; + wire tagLookup_tagCache_orderer_mastRespState$EN; + + // register tagLookup_tagCache_orderer_slaveAddrs_bag + reg [41 : 0] tagLookup_tagCache_orderer_slaveAddrs_bag; + wire [41 : 0] tagLookup_tagCache_orderer_slaveAddrs_bag$D_IN; + wire tagLookup_tagCache_orderer_slaveAddrs_bag$EN; + + // register tagLookup_tagCache_orderer_slaveDeps_bag + reg [12 : 0] tagLookup_tagCache_orderer_slaveDeps_bag; + wire [12 : 0] tagLookup_tagCache_orderer_slaveDeps_bag$D_IN; + wire tagLookup_tagCache_orderer_slaveDeps_bag$EN; + + // register tagLookup_tagCache_orderer_slaveReqs_bag + reg [58 : 0] tagLookup_tagCache_orderer_slaveReqs_bag; + wire [58 : 0] tagLookup_tagCache_orderer_slaveReqs_bag$D_IN; + wire tagLookup_tagCache_orderer_slaveReqs_bag$EN; + + // register tagLookup_tagCache_orderer_slaveRespState + reg [12 : 0] tagLookup_tagCache_orderer_slaveRespState; + wire [12 : 0] tagLookup_tagCache_orderer_slaveRespState$D_IN; + wire tagLookup_tagCache_orderer_slaveRespState$EN; + + // register tagLookup_tagCache_orderer_waitingSlaveReq_lhead + reg [1 : 0] tagLookup_tagCache_orderer_waitingSlaveReq_lhead; + wire [1 : 0] tagLookup_tagCache_orderer_waitingSlaveReq_lhead$D_IN; + wire tagLookup_tagCache_orderer_waitingSlaveReq_lhead$EN; + + // register tagLookup_tagCache_orderer_waitingSlaveReq_ltail + reg [1 : 0] tagLookup_tagCache_orderer_waitingSlaveReq_ltail; + wire [1 : 0] tagLookup_tagCache_orderer_waitingSlaveReq_ltail$D_IN; + wire tagLookup_tagCache_orderer_waitingSlaveReq_ltail$EN; + + // register tagLookup_tagCache_readReqReg + reg [66 : 0] tagLookup_tagCache_readReqReg; + wire [66 : 0] tagLookup_tagCache_readReqReg$D_IN; + wire tagLookup_tagCache_readReqReg$EN; + + // register tagLookup_tagCache_readReqs_bag + reg [72 : 0] tagLookup_tagCache_readReqs_bag; + wire [72 : 0] tagLookup_tagCache_readReqs_bag$D_IN; + wire tagLookup_tagCache_readReqs_bag$EN; + + // register tagLookup_tagCache_req_commits_head + reg [3 : 0] tagLookup_tagCache_req_commits_head; + wire [3 : 0] tagLookup_tagCache_req_commits_head$D_IN; + wire tagLookup_tagCache_req_commits_head$EN; + + // register tagLookup_tagCache_req_commits_level + reg [4 : 0] tagLookup_tagCache_req_commits_level; + wire [4 : 0] tagLookup_tagCache_req_commits_level$D_IN; + wire tagLookup_tagCache_req_commits_level$EN; + + // register tagLookup_tagCache_req_commits_rf + reg [15 : 0] tagLookup_tagCache_req_commits_rf; + wire [15 : 0] tagLookup_tagCache_req_commits_rf$D_IN; + wire tagLookup_tagCache_req_commits_rf$EN; + + // register tagLookup_tagCache_req_commits_tail + reg [3 : 0] tagLookup_tagCache_req_commits_tail; + wire [3 : 0] tagLookup_tagCache_req_commits_tail$D_IN; + wire tagLookup_tagCache_req_commits_tail$EN; + + // register tagLookup_tagCache_retryReqs_bag + reg [147 : 0] tagLookup_tagCache_retryReqs_bag; + wire [147 : 0] tagLookup_tagCache_retryReqs_bag$D_IN; + wire tagLookup_tagCache_retryReqs_bag$EN; + + // register tagLookup_tagCache_tags_0_readAddr + reg [7 : 0] tagLookup_tagCache_tags_0_readAddr; + wire [7 : 0] tagLookup_tagCache_tags_0_readAddr$D_IN; + wire tagLookup_tagCache_tags_0_readAddr$EN; + + // register tagLookup_tagCache_tags_0_readAddrB + reg [7 : 0] tagLookup_tagCache_tags_0_readAddrB; + wire [7 : 0] tagLookup_tagCache_tags_0_readAddrB$D_IN; + wire tagLookup_tagCache_tags_0_readAddrB$EN; + + // register tagLookup_tagCache_tags_0_writeAddr + reg [7 : 0] tagLookup_tagCache_tags_0_writeAddr; + wire [7 : 0] tagLookup_tagCache_tags_0_writeAddr$D_IN; + wire tagLookup_tagCache_tags_0_writeAddr$EN; + + // register tagLookup_tagCache_tags_0_writeData + reg [40 : 0] tagLookup_tagCache_tags_0_writeData; + wire [40 : 0] tagLookup_tagCache_tags_0_writeData$D_IN; + wire tagLookup_tagCache_tags_0_writeData$EN; + + // register tagLookup_tagCache_tags_1_readAddr + reg [7 : 0] tagLookup_tagCache_tags_1_readAddr; + wire [7 : 0] tagLookup_tagCache_tags_1_readAddr$D_IN; + wire tagLookup_tagCache_tags_1_readAddr$EN; + + // register tagLookup_tagCache_tags_1_readAddrB + reg [7 : 0] tagLookup_tagCache_tags_1_readAddrB; + wire [7 : 0] tagLookup_tagCache_tags_1_readAddrB$D_IN; + wire tagLookup_tagCache_tags_1_readAddrB$EN; + + // register tagLookup_tagCache_tags_1_writeAddr + reg [7 : 0] tagLookup_tagCache_tags_1_writeAddr; + wire [7 : 0] tagLookup_tagCache_tags_1_writeAddr$D_IN; + wire tagLookup_tagCache_tags_1_writeAddr$EN; + + // register tagLookup_tagCache_tags_1_writeData + reg [40 : 0] tagLookup_tagCache_tags_1_writeData; + wire [40 : 0] tagLookup_tagCache_tags_1_writeData$D_IN; + wire tagLookup_tagCache_tags_1_writeData$EN; + + // register tagLookup_tagCache_writeResps_ff_lhead + reg [1 : 0] tagLookup_tagCache_writeResps_ff_lhead; + wire [1 : 0] tagLookup_tagCache_writeResps_ff_lhead$D_IN; + wire tagLookup_tagCache_writeResps_ff_lhead$EN; + + // register tagLookup_tagCache_writeResps_ff_ltail + reg [1 : 0] tagLookup_tagCache_writeResps_ff_ltail; + wire [1 : 0] tagLookup_tagCache_writeResps_ff_ltail$D_IN; + wire tagLookup_tagCache_writeResps_ff_ltail$EN; + + // register tagLookup_tagCache_writebackWriteBank + reg [1 : 0] tagLookup_tagCache_writebackWriteBank; + wire [1 : 0] tagLookup_tagCache_writebackWriteBank$D_IN; + wire tagLookup_tagCache_writebackWriteBank$EN; + + // register tagLookup_tagCache_writethroughNext_ff_lhead + reg [1 : 0] tagLookup_tagCache_writethroughNext_ff_lhead; + wire [1 : 0] tagLookup_tagCache_writethroughNext_ff_lhead$D_IN; + wire tagLookup_tagCache_writethroughNext_ff_lhead$EN; + + // register tagLookup_tagCache_writethroughNext_ff_ltail + reg [1 : 0] tagLookup_tagCache_writethroughNext_ff_ltail; + wire [1 : 0] tagLookup_tagCache_writethroughNext_ff_ltail$D_IN; + wire tagLookup_tagCache_writethroughNext_ff_ltail$EN; + + // register tagLookup_transNum + reg [4 : 0] tagLookup_transNum; + reg [4 : 0] tagLookup_transNum$D_IN; + wire tagLookup_transNum$EN; + + // register tagLookup_useNextRsp_ff_lhead + reg [2 : 0] tagLookup_useNextRsp_ff_lhead; + reg [2 : 0] tagLookup_useNextRsp_ff_lhead$D_IN; + wire tagLookup_useNextRsp_ff_lhead$EN; + + // register tagLookup_useNextRsp_ff_ltail + reg [2 : 0] tagLookup_useNextRsp_ff_ltail; + wire [2 : 0] tagLookup_useNextRsp_ff_ltail$D_IN; + wire tagLookup_useNextRsp_ff_ltail$EN; + + // register tagLookup_zeroAddr + reg [39 : 0] tagLookup_zeroAddr; + wire [39 : 0] tagLookup_zeroAddr$D_IN; + wire tagLookup_zeroAddr$EN; + + // register tagOnlyReads_lhead + reg tagOnlyReads_lhead; + wire tagOnlyReads_lhead$D_IN, tagOnlyReads_lhead$EN; + + // register tagOnlyReads_ltail + reg tagOnlyReads_ltail; + wire tagOnlyReads_ltail$D_IN, tagOnlyReads_ltail$EN; + + // register tagOnlyReads_rf + reg [5 : 0] tagOnlyReads_rf; + wire [5 : 0] tagOnlyReads_rf$D_IN; + wire tagOnlyReads_rf$EN; + + // register writeBuffer_ff_lhead + reg [4 : 0] writeBuffer_ff_lhead; + wire [4 : 0] writeBuffer_ff_lhead$D_IN; + wire writeBuffer_ff_lhead$EN; + + // register writeBuffer_ff_ltail + reg [4 : 0] writeBuffer_ff_ltail; + wire [4 : 0] writeBuffer_ff_ltail$D_IN; + wire writeBuffer_ff_ltail$EN; + + // ports of submodule mReqs_ff_rf + wire [140 : 0] mReqs_ff_rf$D_IN, mReqs_ff_rf$D_OUT_1; + wire mReqs_ff_rf$ADDR_1, + mReqs_ff_rf$ADDR_2, + mReqs_ff_rf$ADDR_3, + mReqs_ff_rf$ADDR_4, + mReqs_ff_rf$ADDR_5, + mReqs_ff_rf$ADDR_IN, + mReqs_ff_rf$WE; + + // ports of submodule mRsps_ff_rf + wire [76 : 0] mRsps_ff_rf$D_IN, mRsps_ff_rf$D_OUT_1; + wire [4 : 0] mRsps_ff_rf$ADDR_1, + mRsps_ff_rf$ADDR_2, + mRsps_ff_rf$ADDR_3, + mRsps_ff_rf$ADDR_4, + mRsps_ff_rf$ADDR_5, + mRsps_ff_rf$ADDR_IN; + wire mRsps_ff_rf$WE; + + // ports of submodule tagLookup_mReqs_ff_rf + wire [140 : 0] tagLookup_mReqs_ff_rf$D_IN, tagLookup_mReqs_ff_rf$D_OUT_1; + wire [2 : 0] tagLookup_mReqs_ff_rf$ADDR_1, + tagLookup_mReqs_ff_rf$ADDR_2, + tagLookup_mReqs_ff_rf$ADDR_3, + tagLookup_mReqs_ff_rf$ADDR_4, + tagLookup_mReqs_ff_rf$ADDR_5, + tagLookup_mReqs_ff_rf$ADDR_IN; + wire tagLookup_mReqs_ff_rf$WE; + + // ports of submodule tagLookup_mRsps_ff_rf + wire [76 : 0] tagLookup_mRsps_ff_rf$D_IN, tagLookup_mRsps_ff_rf$D_OUT_1; + wire tagLookup_mRsps_ff_rf$ADDR_1, + tagLookup_mRsps_ff_rf$ADDR_2, + tagLookup_mRsps_ff_rf$ADDR_3, + tagLookup_mRsps_ff_rf$ADDR_4, + tagLookup_mRsps_ff_rf$ADDR_5, + tagLookup_mRsps_ff_rf$ADDR_IN, + tagLookup_mRsps_ff_rf$WE; + + // ports of submodule tagLookup_tagCache_data_0_bram_bram + wire [63 : 0] tagLookup_tagCache_data_0_bram_bram$DIA, + tagLookup_tagCache_data_0_bram_bram$DIB, + tagLookup_tagCache_data_0_bram_bram$DOA; + wire [9 : 0] tagLookup_tagCache_data_0_bram_bram$ADDRA, + tagLookup_tagCache_data_0_bram_bram$ADDRB; + wire tagLookup_tagCache_data_0_bram_bram$ENA, + tagLookup_tagCache_data_0_bram_bram$ENB, + tagLookup_tagCache_data_0_bram_bram$WEA, + tagLookup_tagCache_data_0_bram_bram$WEB; + + // ports of submodule tagLookup_tagCache_data_1_bram_bram + wire [63 : 0] tagLookup_tagCache_data_1_bram_bram$DIA, + tagLookup_tagCache_data_1_bram_bram$DIB, + tagLookup_tagCache_data_1_bram_bram$DOA; + wire [9 : 0] tagLookup_tagCache_data_1_bram_bram$ADDRA, + tagLookup_tagCache_data_1_bram_bram$ADDRB; + wire tagLookup_tagCache_data_1_bram_bram$ENA, + tagLookup_tagCache_data_1_bram_bram$ENB, + tagLookup_tagCache_data_1_bram_bram$WEA, + tagLookup_tagCache_data_1_bram_bram$WEB; + + // ports of submodule tagLookup_tagCache_delayedInvalidates_ff_rf + wire [36 : 0] tagLookup_tagCache_delayedInvalidates_ff_rf$D_IN; + wire [2 : 0] tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_1, + tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_2, + tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_3, + tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_4, + tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_5, + tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_IN; + wire tagLookup_tagCache_delayedInvalidates_ff_rf$WE; + + // ports of submodule tagLookup_tagCache_invalidateWritebacks + wire [88 : 0] tagLookup_tagCache_invalidateWritebacks$D_IN; + wire tagLookup_tagCache_invalidateWritebacks$CLR, + tagLookup_tagCache_invalidateWritebacks$DEQ, + tagLookup_tagCache_invalidateWritebacks$EMPTY_N, + tagLookup_tagCache_invalidateWritebacks$ENQ; + + // ports of submodule tagLookup_tagCache_invalidatesDone_ff_rf + wire [4 : 0] tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_1, + tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_2, + tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_3, + tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_4, + tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_5, + tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_IN; + wire tagLookup_tagCache_invalidatesDone_ff_rf$D_IN, + tagLookup_tagCache_invalidatesDone_ff_rf$WE; + + // ports of submodule tagLookup_tagCache_invalidates_ff_rf + wire [39 : 0] tagLookup_tagCache_invalidates_ff_rf$D_IN; + wire [1 : 0] tagLookup_tagCache_invalidates_ff_rf$ADDR_1, + tagLookup_tagCache_invalidates_ff_rf$ADDR_2, + tagLookup_tagCache_invalidates_ff_rf$ADDR_3, + tagLookup_tagCache_invalidates_ff_rf$ADDR_4, + tagLookup_tagCache_invalidates_ff_rf$ADDR_5, + tagLookup_tagCache_invalidates_ff_rf$ADDR_IN; + wire tagLookup_tagCache_invalidates_ff_rf$WE; + + // ports of submodule tagLookup_tagCache_orderer_waitingSlaveReq_rf + wire [5 : 0] tagLookup_tagCache_orderer_waitingSlaveReq_rf$D_IN; + wire tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_1, + tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_2, + tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_3, + tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_4, + tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_5, + tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_IN, + tagLookup_tagCache_orderer_waitingSlaveReq_rf$WE; + + // ports of submodule tagLookup_tagCache_tags_0_bramA_bram + wire [40 : 0] tagLookup_tagCache_tags_0_bramA_bram$DIA, + tagLookup_tagCache_tags_0_bramA_bram$DIB, + tagLookup_tagCache_tags_0_bramA_bram$DOA; + wire [7 : 0] tagLookup_tagCache_tags_0_bramA_bram$ADDRA, + tagLookup_tagCache_tags_0_bramA_bram$ADDRB; + wire tagLookup_tagCache_tags_0_bramA_bram$ENA, + tagLookup_tagCache_tags_0_bramA_bram$ENB, + tagLookup_tagCache_tags_0_bramA_bram$WEA, + tagLookup_tagCache_tags_0_bramA_bram$WEB; + + // ports of submodule tagLookup_tagCache_tags_0_bramB_bram + wire [40 : 0] tagLookup_tagCache_tags_0_bramB_bram$DIA, + tagLookup_tagCache_tags_0_bramB_bram$DIB; + wire [7 : 0] tagLookup_tagCache_tags_0_bramB_bram$ADDRA, + tagLookup_tagCache_tags_0_bramB_bram$ADDRB; + wire tagLookup_tagCache_tags_0_bramB_bram$ENA, + tagLookup_tagCache_tags_0_bramB_bram$ENB, + tagLookup_tagCache_tags_0_bramB_bram$WEA, + tagLookup_tagCache_tags_0_bramB_bram$WEB; + + // ports of submodule tagLookup_tagCache_tags_1_bramA_bram + wire [40 : 0] tagLookup_tagCache_tags_1_bramA_bram$DIA, + tagLookup_tagCache_tags_1_bramA_bram$DIB, + tagLookup_tagCache_tags_1_bramA_bram$DOA; + wire [7 : 0] tagLookup_tagCache_tags_1_bramA_bram$ADDRA, + tagLookup_tagCache_tags_1_bramA_bram$ADDRB; + wire tagLookup_tagCache_tags_1_bramA_bram$ENA, + tagLookup_tagCache_tags_1_bramA_bram$ENB, + tagLookup_tagCache_tags_1_bramA_bram$WEA, + tagLookup_tagCache_tags_1_bramA_bram$WEB; + + // ports of submodule tagLookup_tagCache_tags_1_bramB_bram + wire [40 : 0] tagLookup_tagCache_tags_1_bramB_bram$DIA, + tagLookup_tagCache_tags_1_bramB_bram$DIB; + wire [7 : 0] tagLookup_tagCache_tags_1_bramB_bram$ADDRA, + tagLookup_tagCache_tags_1_bramB_bram$ADDRB; + wire tagLookup_tagCache_tags_1_bramB_bram$ENA, + tagLookup_tagCache_tags_1_bramB_bram$ENB, + tagLookup_tagCache_tags_1_bramB_bram$WEA, + tagLookup_tagCache_tags_1_bramB_bram$WEB; + + // ports of submodule tagLookup_tagCache_writeResps_ff_rf + wire [7 : 0] tagLookup_tagCache_writeResps_ff_rf$D_IN; + wire tagLookup_tagCache_writeResps_ff_rf$ADDR_1, + tagLookup_tagCache_writeResps_ff_rf$ADDR_2, + tagLookup_tagCache_writeResps_ff_rf$ADDR_3, + tagLookup_tagCache_writeResps_ff_rf$ADDR_4, + tagLookup_tagCache_writeResps_ff_rf$ADDR_5, + tagLookup_tagCache_writeResps_ff_rf$ADDR_IN, + tagLookup_tagCache_writeResps_ff_rf$WE; + + // ports of submodule tagLookup_tagCache_writebacks + wire [88 : 0] tagLookup_tagCache_writebacks$D_IN, + tagLookup_tagCache_writebacks$D_OUT; + wire tagLookup_tagCache_writebacks$CLR, + tagLookup_tagCache_writebacks$DEQ, + tagLookup_tagCache_writebacks$EMPTY_N, + tagLookup_tagCache_writebacks$ENQ; + + // ports of submodule tagLookup_useNextRsp_ff_rf + reg tagLookup_useNextRsp_ff_rf$D_IN; + wire [1 : 0] tagLookup_useNextRsp_ff_rf$ADDR_1, + tagLookup_useNextRsp_ff_rf$ADDR_2, + tagLookup_useNextRsp_ff_rf$ADDR_3, + tagLookup_useNextRsp_ff_rf$ADDR_4, + tagLookup_useNextRsp_ff_rf$ADDR_5, + tagLookup_useNextRsp_ff_rf$ADDR_IN; + wire tagLookup_useNextRsp_ff_rf$D_OUT_1, tagLookup_useNextRsp_ff_rf$WE; + + // ports of submodule writeBuffer_ff_rf + wire [140 : 0] writeBuffer_ff_rf$D_IN, writeBuffer_ff_rf$D_OUT_1; + wire [3 : 0] writeBuffer_ff_rf$ADDR_1, + writeBuffer_ff_rf$ADDR_2, + writeBuffer_ff_rf$ADDR_3, + writeBuffer_ff_rf$ADDR_4, + writeBuffer_ff_rf$ADDR_5, + writeBuffer_ff_rf$ADDR_IN; + wire writeBuffer_ff_rf$WE; + + // rule scheduling signals + wire CAN_FIRE_RL_addrFrame_updateBag, + CAN_FIRE_RL_drainWritebuffer, + CAN_FIRE_RL_forwardLookupReqs, + CAN_FIRE_RL_getTagLookupResponse, + CAN_FIRE_RL_lookupRsp_updateBag, + CAN_FIRE_RL_mReqs_ff_doDisplayPanic, + CAN_FIRE_RL_mRsps_displayDeqPanic, + CAN_FIRE_RL_mRsps_displayEnqPanic, + CAN_FIRE_RL_mRsps_ff_doDisplayPanic, + CAN_FIRE_RL_tagLookup_doLookup, + CAN_FIRE_RL_tagLookup_drainMemRsp, + CAN_FIRE_RL_tagLookup_feedTagCache, + CAN_FIRE_RL_tagLookup_initialise, + CAN_FIRE_RL_tagLookup_lookupRsp_displayDeqPanic, + CAN_FIRE_RL_tagLookup_lookupRsp_displayEnqPanic, + CAN_FIRE_RL_tagLookup_lookupRsp_ff_doDisplayPanic, + CAN_FIRE_RL_tagLookup_mReqs_displayDeqPanic, + CAN_FIRE_RL_tagLookup_mReqs_displayEnqPanic, + CAN_FIRE_RL_tagLookup_mReqs_ff_doDisplayPanic, + CAN_FIRE_RL_tagLookup_mRsps_displayDeqPanic, + CAN_FIRE_RL_tagLookup_mRsps_displayEnqPanic, + CAN_FIRE_RL_tagLookup_mRsps_ff_doDisplayPanic, + CAN_FIRE_RL_tagLookup_stuffCommits, + CAN_FIRE_RL_tagLookup_tagCacheReq_ff_doDisplayPanic, + CAN_FIRE_RL_tagLookup_tagCache_catchResponse, + CAN_FIRE_RL_tagLookup_tagCache_commonStateUpdate, + CAN_FIRE_RL_tagLookup_tagCache_delayedInvalidates_displayDeqPanic, + CAN_FIRE_RL_tagLookup_tagCache_delayedInvalidates_displayEnqPanic, + CAN_FIRE_RL_tagLookup_tagCache_delayedInvalidates_ff_doDisplayPanic, + CAN_FIRE_RL_tagLookup_tagCache_finishLookup, + CAN_FIRE_RL_tagLookup_tagCache_initialize, + CAN_FIRE_RL_tagLookup_tagCache_invalidatesDone_displayDeqPanic, + CAN_FIRE_RL_tagLookup_tagCache_invalidatesDone_displayEnqPanic, + CAN_FIRE_RL_tagLookup_tagCache_invalidatesDone_ff_doDisplayPanic, + CAN_FIRE_RL_tagLookup_tagCache_invalidates_displayDeqPanic, + CAN_FIRE_RL_tagLookup_tagCache_invalidates_displayEnqPanic, + CAN_FIRE_RL_tagLookup_tagCache_invalidates_ff_doDisplayPanic, + CAN_FIRE_RL_tagLookup_tagCache_orderer_mastLines_updateBag, + CAN_FIRE_RL_tagLookup_tagCache_orderer_mastReqIds_updateRf, + CAN_FIRE_RL_tagLookup_tagCache_orderer_mastReqs_updateBag, + CAN_FIRE_RL_tagLookup_tagCache_orderer_slaveAddrs_updateBag, + CAN_FIRE_RL_tagLookup_tagCache_orderer_slaveDeps_updateBag, + CAN_FIRE_RL_tagLookup_tagCache_orderer_slaveReqs_updateBag, + CAN_FIRE_RL_tagLookup_tagCache_orderer_waitingSlaveReq_doDisplayPanic, + CAN_FIRE_RL_tagLookup_tagCache_readReqs_updateBag, + CAN_FIRE_RL_tagLookup_tagCache_retryReqs_updateBag, + CAN_FIRE_RL_tagLookup_tagCache_startLookup, + CAN_FIRE_RL_tagLookup_tagCache_writeNextEmpty, + CAN_FIRE_RL_tagLookup_tagCache_writeResps_displayDeqPanic, + CAN_FIRE_RL_tagLookup_tagCache_writeResps_displayEnqPanic, + CAN_FIRE_RL_tagLookup_tagCache_writeResps_ff_doDisplayPanic, + CAN_FIRE_RL_tagLookup_tagCache_writethroughNext_displayDeqPanic, + CAN_FIRE_RL_tagLookup_tagCache_writethroughNext_displayEnqPanic, + CAN_FIRE_RL_tagLookup_tagCache_writethroughNext_ff_doDisplayPanic, + CAN_FIRE_RL_tagLookup_useNextRsp_displayDeqPanic, + CAN_FIRE_RL_tagLookup_useNextRsp_displayEnqPanic, + CAN_FIRE_RL_tagLookup_useNextRsp_ff_doDisplayPanic, + CAN_FIRE_RL_tagOnlyReads_doDisplayPanic, + CAN_FIRE_RL_writeBuffer_ff_doDisplayPanic, + CAN_FIRE_cache_request_put, + CAN_FIRE_cache_response_get, + CAN_FIRE_memory_request_get, + CAN_FIRE_memory_response_put, + WILL_FIRE_RL_addrFrame_updateBag, + WILL_FIRE_RL_drainWritebuffer, + WILL_FIRE_RL_forwardLookupReqs, + WILL_FIRE_RL_getTagLookupResponse, + WILL_FIRE_RL_lookupRsp_updateBag, + WILL_FIRE_RL_mReqs_ff_doDisplayPanic, + WILL_FIRE_RL_mRsps_displayDeqPanic, + WILL_FIRE_RL_mRsps_displayEnqPanic, + WILL_FIRE_RL_mRsps_ff_doDisplayPanic, + WILL_FIRE_RL_tagLookup_doLookup, + WILL_FIRE_RL_tagLookup_drainMemRsp, + WILL_FIRE_RL_tagLookup_feedTagCache, + WILL_FIRE_RL_tagLookup_initialise, + WILL_FIRE_RL_tagLookup_lookupRsp_displayDeqPanic, + WILL_FIRE_RL_tagLookup_lookupRsp_displayEnqPanic, + WILL_FIRE_RL_tagLookup_lookupRsp_ff_doDisplayPanic, + WILL_FIRE_RL_tagLookup_mReqs_displayDeqPanic, + WILL_FIRE_RL_tagLookup_mReqs_displayEnqPanic, + WILL_FIRE_RL_tagLookup_mReqs_ff_doDisplayPanic, + WILL_FIRE_RL_tagLookup_mRsps_displayDeqPanic, + WILL_FIRE_RL_tagLookup_mRsps_displayEnqPanic, + WILL_FIRE_RL_tagLookup_mRsps_ff_doDisplayPanic, + WILL_FIRE_RL_tagLookup_stuffCommits, + WILL_FIRE_RL_tagLookup_tagCacheReq_ff_doDisplayPanic, + WILL_FIRE_RL_tagLookup_tagCache_catchResponse, + WILL_FIRE_RL_tagLookup_tagCache_commonStateUpdate, + WILL_FIRE_RL_tagLookup_tagCache_delayedInvalidates_displayDeqPanic, + WILL_FIRE_RL_tagLookup_tagCache_delayedInvalidates_displayEnqPanic, + WILL_FIRE_RL_tagLookup_tagCache_delayedInvalidates_ff_doDisplayPanic, + WILL_FIRE_RL_tagLookup_tagCache_finishLookup, + WILL_FIRE_RL_tagLookup_tagCache_initialize, + WILL_FIRE_RL_tagLookup_tagCache_invalidatesDone_displayDeqPanic, + WILL_FIRE_RL_tagLookup_tagCache_invalidatesDone_displayEnqPanic, + WILL_FIRE_RL_tagLookup_tagCache_invalidatesDone_ff_doDisplayPanic, + WILL_FIRE_RL_tagLookup_tagCache_invalidates_displayDeqPanic, + WILL_FIRE_RL_tagLookup_tagCache_invalidates_displayEnqPanic, + WILL_FIRE_RL_tagLookup_tagCache_invalidates_ff_doDisplayPanic, + WILL_FIRE_RL_tagLookup_tagCache_orderer_mastLines_updateBag, + WILL_FIRE_RL_tagLookup_tagCache_orderer_mastReqIds_updateRf, + WILL_FIRE_RL_tagLookup_tagCache_orderer_mastReqs_updateBag, + WILL_FIRE_RL_tagLookup_tagCache_orderer_slaveAddrs_updateBag, + WILL_FIRE_RL_tagLookup_tagCache_orderer_slaveDeps_updateBag, + WILL_FIRE_RL_tagLookup_tagCache_orderer_slaveReqs_updateBag, + WILL_FIRE_RL_tagLookup_tagCache_orderer_waitingSlaveReq_doDisplayPanic, + WILL_FIRE_RL_tagLookup_tagCache_readReqs_updateBag, + WILL_FIRE_RL_tagLookup_tagCache_retryReqs_updateBag, + WILL_FIRE_RL_tagLookup_tagCache_startLookup, + WILL_FIRE_RL_tagLookup_tagCache_writeNextEmpty, + WILL_FIRE_RL_tagLookup_tagCache_writeResps_displayDeqPanic, + WILL_FIRE_RL_tagLookup_tagCache_writeResps_displayEnqPanic, + WILL_FIRE_RL_tagLookup_tagCache_writeResps_ff_doDisplayPanic, + WILL_FIRE_RL_tagLookup_tagCache_writethroughNext_displayDeqPanic, + WILL_FIRE_RL_tagLookup_tagCache_writethroughNext_displayEnqPanic, + WILL_FIRE_RL_tagLookup_tagCache_writethroughNext_ff_doDisplayPanic, + WILL_FIRE_RL_tagLookup_useNextRsp_displayDeqPanic, + WILL_FIRE_RL_tagLookup_useNextRsp_displayEnqPanic, + WILL_FIRE_RL_tagLookup_useNextRsp_ff_doDisplayPanic, + WILL_FIRE_RL_tagOnlyReads_doDisplayPanic, + WILL_FIRE_RL_writeBuffer_ff_doDisplayPanic, + WILL_FIRE_cache_request_put, + WILL_FIRE_cache_response_get, + WILL_FIRE_memory_request_get, + WILL_FIRE_memory_response_put; + + // inputs to muxes for submodule ports + reg [7 : 0] MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_2__VAL_1; + reg [2 : 0] MUX_tagLookup_state$write_1__VAL_3; + wire [140 : 0] MUX_mReqs_ff_rf$upd_2__VAL_1, + MUX_mReqs_ff_rf$upd_2__VAL_2, + MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_1, + MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_2, + MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_3, + MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_4; + wire [40 : 0] MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_3__VAL_1; + wire [7 : 0] MUX_tagLookup_tagCache_writeResps_ff_rf$upd_2__VAL_1; + wire [4 : 0] MUX_tagLookup_transNum$write_1__VAL_1; + wire [2 : 0] MUX_tagLookup_state$write_1__VAL_2, + MUX_tagLookup_useNextRsp_ff_lhead$write_1__VAL_1; + wire [1 : 0] MUX_mReqs_ff_lhead$write_1__VAL_1, + MUX_tagLookup_currentDepth$write_1__VAL_1, + MUX_tagLookup_tagCache_writeResps_ff_lhead$write_1__VAL_1; + wire MUX_mReqs_ff_lhead$write_1__SEL_1, + MUX_tagLookup_currentDepth$write_1__SEL_1, + MUX_tagLookup_currentDepth$write_1__SEL_2, + MUX_tagLookup_currentDepth$write_1__SEL_3, + MUX_tagLookup_pendingCapEnable$write_1__VAL_1, + MUX_tagLookup_pendingTags$write_1__VAL_1, + MUX_tagLookup_readReqs_ff_dataReg$write_1__SEL_1, + MUX_tagLookup_readReqs_ff_dataReg$write_1__SEL_2, + MUX_tagLookup_readReqs_ff_dataReg$write_1__VAL_1, + MUX_tagLookup_readReqs_ff_dataReg$write_1__VAL_2, + MUX_tagLookup_reqeustId$write_1__SEL_1, + MUX_tagLookup_state$write_1__SEL_1, + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_1, + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_4, + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__VAL_1, + MUX_tagLookup_tagCache_missedResp$wset_1__SEL_1, + MUX_tagLookup_tagCache_missedResp$wset_1__VAL_1, + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_1__SEL_1, + MUX_tagLookup_tagCache_tags_1_bramA_bram$b_put_1__SEL_1, + MUX_tagLookup_tagCache_writeResps_ff_lhead$write_1__SEL_1, + MUX_tagLookup_useNextRsp_ff_rf$upd_2__VAL_4; + + // declarations used by system tasks + // synopsys translate_off + reg [63 : 0] v__h87525; + reg [63 : 0] v__h90845; + reg [63 : 0] v__h93102; + reg [63 : 0] v__h94582; + reg [63 : 0] v__h95973; + reg [63 : 0] v__h97474; + reg [63 : 0] v__h99940; + // synopsys translate_on + + // remaining internal signals + reg [93 : 0] IF_cache_request_put_val_BITS_93_TO_92_997_EQ__ETC___d6049; + reg [63 : 0] CASE_tagLookup_currentDepth_0_tagLookup_oldTag_ETC__q17, + cacheResp_data_data__h284964; + reg [36 : 0] CASE_tagLookup_currentDepth_0_535821840_1_5358_ETC__q12, + CASE_tagLookup_currentDepth_338_MINUS_1_481_0__ETC__q14; + reg [31 : 0] CASE_tagLookup_currentDepth_0_0_1_6_DONTCARE__q3, + CASE_tagLookup_currentDepth_0_4294967293_1_3_D_ETC__q2, + CASE_tagLookup_currentDepth_338_MINUS_1_481_0__ETC__q13; + reg [26 : 0] CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q25, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q34, + x_addr_tag__h102720; + reg [12 : 0] CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q24; + reg [7 : 0] IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4490, + x1_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_d_key__h278782; + reg [5 : 0] CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q27, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q29, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_1__ETC__q22, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_1__ETC__q33; + reg [4 : 0] x__h284335; + reg [3 : 0] CASE_memory_response_put_val_BITS_68_TO_67_0_m_ETC__q41, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4642; + reg [2 : 0] CASE_tagLookup_currentDepth_0_1_1_1_tagLookup__ETC__q38, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q26; + reg [1 : 0] CASE_mReqs_ff_rfD_OUT_1_BITS_93_TO_92_0_mReqs_ETC__q1, + CASE_tagLookup_mReqs_ff_rfD_OUT_1_BITS_93_TO__ETC__q18, + CASE_tagLookup_tagCacheReq_ff_rf_BITS_93_TO_92_ETC__q19, + CASE_tagLookup_tagCache_cts_BITS_229_TO_228_0__ETC__q36, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q32; + reg CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42, + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43, + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44, + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45, + CASE_tagLookup_tagCache_cts_BITS_100_TO_99_0_t_ETC__q16, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q21, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q23, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q28, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q30, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q31, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q35, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q46, + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q10, + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q11, + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q5, + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q6, + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q7, + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q8, + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q9, + CASE_x30808_0_lookupRsp_bag_BIT_0_1_lookupRsp__ETC__q15, + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139, + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3496, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4047, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4538, + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455, + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d4540, + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200, + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337, + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029, + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166, + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395, + SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d3614, + SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d4542, + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195, + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335, + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024, + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164, + x__h121243, + x__h284313; + wire [140 : 0] IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3048; + wire [99 : 0] IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3047; + wire [93 : 0] IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d3752, + IF_IF_tagLookup_tagCache_newReq_whas__787_AND__ETC___d3045, + IF_IF_tagLookup_tagCache_newReq_whas__787_AND__ETC___d3046, + IF_NOT_writeBuffer_ff_rf_sub_writeBuffer_ff_lt_ETC___d5977, + IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5701, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d3753, + _0_CONCAT_DONTCARE_CONCAT_IF_tagLookup_tagCache_ETC___d3035, + _1_CONCAT_IF_tagLookup_tagCache_newReq_whas__78_ETC___d3040, + _2_CONCAT_DONTCARE_CONCAT_IF_tagLookup_tagCache_ETC___d3044; + wire [79 : 0] IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3130; + wire [64 : 0] IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6171, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5036; + wire [63 : 0] IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5697, + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5696, + _theResult___snd_snd_fst_data_data__h330561, + _theResult___snd_snd_fst_data_data__h330563, + data_data__h307593, + maskedWrite_data__h117949, + tagLookup_tagCache_respswget_BITS_219_TO_156__q37, + wdata_data__h307591, + wdata_data__h307595, + wdata_data__h307597, + wdata_data__h321116, + x1_avValue_data__h86313, + x1_avValue_data__h86372; + wire [58 : 0] IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d492, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d516, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d540, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d566, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d592, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d620, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d648, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d678, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d708, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d740, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d772, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d806, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d840, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d876, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d907, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d912, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d915, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d919, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d922, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d926, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d929, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d933, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d936, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d940, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d943, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d947, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d950, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d954, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d957, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d961, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d964; + wire [57 : 0] IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4944; + wire [51 : 0] tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3769; + wire [50 : 0] IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4943; + wire [43 : 0] IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4942; + wire [41 : 0] IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1663, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1687, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1711, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1737, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1763, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1791, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1819, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1849, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1879, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1911, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1943, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1977, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d2011, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d2047, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d2078, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2083, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2086, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2090, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2093, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2097, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2100, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2104, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2107, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2111, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2114, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2118, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2121, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2125, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2128, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2132, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2135; + wire [40 : 0] IF_tagLookup_tagCache_writebacks_i_notEmpty__8_ETC___d3127; + wire [39 : 0] IF_NOT_tagLookup_currentDepth_338_EQ_0_339_363_ETC___d5495, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3689, + IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5498, + IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5497, + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5496, + IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3054, + IF_tagLookup_tagCache_writebacks_i_notEmpty__8_ETC___d3055, + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493, + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354, + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490, + _0_CONCAT_writeBuffer_ff_rf_sub_writeBuffer_ff__ETC___d5950, + cache_request_put_val_BITS_140_TO_101_012_MINU_ETC___d6067, + tagLookup_tagCache_newReqwget_BITS_140_TO_101__q20, + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5942; + wire [36 : 0] x1_avValue_fst_addr_lineNumber__h114874, + x__h117048, + x_lineNumber__h292967, + y_avValue_fst_addr_lineNumber__h114872; + wire [35 : 0] x__h303703, x__h303814; + wire [31 : 0] IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2175, + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2177, + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2179, + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2181, + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2183, + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2185, + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1004, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1006, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1008, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1010, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1012, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1014, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016; + wire [26 : 0] IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4296, + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4302, + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4265, + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4267, + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4783, + IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d4286, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4295, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4301, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4786, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4293, + IF_NOT_tagLookup_tagCache_cts_read__795_BIT_22_ETC___d4304, + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4283, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4284, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4285, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4294, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4306, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4785, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4788, + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4299, + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4263, + _theResult_____1_tag__h121522, + x1_avValue_snd_addr_tag__h74941, + x1_avValue_snd_writebackTag_tag__h81268, + x1_avValue_tag__h84378, + x1_avValue_tag__h84438, + y_avValue_snd_snd_snd_newTag_tag__h121536; + wire [14 : 0] IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5078; + wire [13 : 0] IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4811; + wire [12 : 0] IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4800, + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4801, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4805, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4804, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4807, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4643, + NOT_tagLookup_tagCache_orderer_slaveDeps_remov_ETC___d264; + wire [10 : 0] IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3767; + wire [9 : 0] IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3980, + IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d2892, + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d3979, + IF_tagLookup_tagCache_writebacks_i_notEmpty__8_ETC___d2893, + memReqFifoSpace__h2403; + wire [8 : 0] IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d3739, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3740; + wire [7 : 0] IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4384, + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4385, + IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4486, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4484, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4482, + IF_tagLookup_currentDepth_338_EQ_1_466_THEN_0__ETC___d5648, + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4387, + IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5666, + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5665, + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5682, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4481, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4483, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4487, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5077, + IF_tagLookup_tagCache_cts_read__795_BIT_217_18_ETC___d4187, + IF_tagLookup_tagCache_cts_read__795_BIT_218_17_ETC___d4180, + IF_tagLookup_tagCache_cts_read__795_BIT_219_16_ETC___d4172, + IF_tagLookup_tagCache_cts_read__795_BIT_220_15_ETC___d4165, + IF_tagLookup_tagCache_cts_read__795_BIT_221_15_ETC___d4157, + IF_tagLookup_tagCache_cts_read__795_BIT_222_14_ETC___d4150, + IF_tagLookup_tagCache_cts_read__795_BIT_223_13_ETC___d4142, + IF_tagLookup_tagCache_cts_read__795_BIT_224_12_ETC___d4135, + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4386, + _1_SL_tagLookup_pendingCapNumber_343_BITS_2_TO__ETC___d5671, + _theResult_____1_snd__h307206, + _theResult_____1_snd__h307357, + _theResult_____3_snd_snd_snd_snd_snd_d_key__h278742, + bitEnable__h303972, + bitEnable__h303984, + bitEnable__h303992, + wbitE__h303269, + x1_avValue_snd_addr_key__h74942, + x1_avValue_snd_fst_key__h121113, + x1_avValue_snd_snd_snd_d_key__h278330, + x1_avValue_snd_snd_snd_snd_d_key__h278635, + x1_avValue_snd_snd_snd_snd_snd_d_key__h278771, + x1_avValue_snd_snd_snd_snd_snd_snd_d_key__h278644, + x1_avValue_snd_snd_snd_snd_snd_snd_d_key__h278653, + x1_avValue_snd_snd_snd_snd_snd_snd_fst_dataKey_key__h98516, + x__h118925, + x__h119258, + x__h119397, + x__h119536, + x__h119675, + x__h119814, + x__h119953, + x__h120092, + x__h306917, + x__h307116, + x__h308249, + x__h320966, + x__h321179, + x__h323598, + x__h72111, + y__h118926, + y__h119151, + y__h119259, + y__h119398, + y__h119537, + y__h119676, + y__h119815, + y__h119954, + y__h120093, + y__h307071, + y_avValue_snd_fst_key__h121088; + wire [5 : 0] IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d3737, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4687, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4769, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d5043, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d5044, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4686, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4689, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4768, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4771, + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3349, + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2829, + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2873, + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d5042, + IF_tagOnlyReads_lhead_read__990_MINUS_tagOnlyR_ETC___d6187, + i__h301909, + idx__h296159, + level__h314581, + x__h308227, + x__h308368, + x__h308607, + x__h321366; + wire [4 : 0] IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2639, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2643, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2648, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2652, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2657, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2661, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2666, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2670, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2675, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2679, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2684, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2688, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2693, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2697, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2702, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2706, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4718, + _theResult___snd_snd_fst_transactionID__h330323, + level__h313914, + newHead___1__h49394, + newHead___1__h49407, + newHead__h48716, + x1_avValue_snd_snd_snd_snd_d_inId_transactionID__h278681, + x1_avValue_snd_snd_snd_snd_snd_snd_d_inId_transactionID__h278683, + x1_avValue_snd_snd_snd_snd_snd_snd_d_inId_transactionID__h278685, + x1_avValue_snd_snd_snd_snd_snd_snd_fst_req_transactionID__h98351, + x1_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_fst_d_inId_transactionID__h278689, + x__h330335, + x__h78979, + x_mastReqsSpaces__h53162, + x_port1__read__h92294, + x_remaining__h53145; + wire [3 : 0] IF_IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff__ETC___d6137, + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4527, + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4530, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2317, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2318, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2319, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2320, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2321, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2322, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2323, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2324, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2325, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2326, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2327, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2328, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2329, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2330, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1146, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1147, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1148, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1149, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1150, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1151, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1152, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1153, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1154, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1155, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1156, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1157, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1158, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1159, + IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4638, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4636, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4634, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d5033, + IF_NOT_tagLookup_tagCache_cts_read__795_BIT_22_ETC___d4590, + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4532, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4633, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4635, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4640, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5032, + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4531, + _theResult_____1__h31534, + _theResult_____1__h43323, + idx__h31676, + idx__h31792, + idx__h31908, + idx__h32024, + idx__h32140, + idx__h32256, + idx__h32372, + idx__h32488, + idx__h32604, + idx__h32720, + idx__h32836, + idx__h32952, + idx__h33068, + idx__h33184, + idx__h33300, + idx__h43465, + idx__h43581, + idx__h43697, + idx__h43813, + idx__h43929, + idx__h44045, + idx__h44161, + idx__h44277, + idx__h44393, + idx__h44509, + idx__h44625, + idx__h44741, + idx__h44857, + idx__h44973, + idx__h45089, + level__h1012, + x__h102652; + wire [2 : 0] IF_CAN_FIRE_RL_tagLookup_feedTagCache_AND_tagL_ETC__q39, + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4937, + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4864, + IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d3762, + IF_NOT_tagLookup_currentDepth_338_EQ_0_339_363_ETC___d5731, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3763, + IF_SEL_ARR_tagLookup_oldTags_0_714_tagLookup_o_ETC___d5733, + IF_tagLookup_currentDepth_338_EQ_0_339_THEN_1__ETC___d5726, + IF_tagLookup_currentDepth_338_EQ_0_339_THEN_IF_ETC___d5730, + IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5736, + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5735, + IF_tagLookup_tagCacheReq_ff_rf_BITS_93_TO_92_E_ETC__q40, + IF_tagLookup_tagCache_cts_BITS_229_TO_228_EQ_0_ETC__q4, + level__h1913, + nodeOffset__h304386, + nodeOffset__h304822, + x__h332332, + y__h304733; + wire [1 : 0] IF_IF_tagLookup_tagCache_newReq_whas__787_AND__ETC___d2980, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4935, + IF_NOT_tagLookup_mRsps_ff_lhead_read__894_MINU_ETC___d3019, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4996, + IF_NOT_tagLookup_tagCache_orderer_slaveReqs_ba_ETC___d5004, + IF_SEL_ARR_tagLookup_oldTags_0_714_tagLookup_o_ETC___d5721, + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6119, + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6128, + IF_tagLookup_currentDepth_338_EQ_0_339_THEN_IF_ETC___d5713, + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5723, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4934, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4994, + IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3020, + IF_tagLookup_tagCache_newReq_whas__787_THEN_ta_ETC___d2826, + IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2857, + IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2870, + IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2890, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3251, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3252, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3253, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3254, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3255, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3256, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3257, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3258, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3259, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3260, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3261, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3262, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3263, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3264, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3333, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3334, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3335, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3336, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3337, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3338, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3339, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3340, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3341, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3342, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3343, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3344, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3345, + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3346, + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3265, + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2820, + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2825, + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2855, + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2865, + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2869, + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d5005, + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d2856, + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4363, + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4511, + level__h1463, + level__h314247, + level__h8616, + tagLookup_currentDepth_338_MINUS_1___d5481, + x__h122813, + x__h135259, + x__h330808; + wire IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2227, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2233, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2239, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2245, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2251, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2257, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2263, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2269, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2275, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2281, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2287, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2293, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2299, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2305, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2311, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1056, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1062, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1068, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1074, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1080, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1086, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1092, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1098, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1104, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1110, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1116, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1122, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1128, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1134, + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1140, + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4849, + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4851, + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4853, + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4855, + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4857, + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4859, + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4861, + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4117, + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4219, + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4246, + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4337, + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4503, + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4571, + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4576, + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4582, + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4587, + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4729, + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4494, + IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d3728, + IF_IF_tagLookup_tagCache_newReq_whas__787_AND__ETC___d3067, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2479, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2490, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2505, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2514, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2535, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2547, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2574, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2589, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2622, + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2626, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1308, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1319, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1334, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1343, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1364, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1376, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1403, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1418, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1451, + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1455, + IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4339, + IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4505, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4218, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4245, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4336, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4396, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4406, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4417, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4427, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4438, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4448, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4459, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4469, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4502, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4570, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4575, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4581, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4586, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4597, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4606, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4616, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4625, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4668, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4757, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4777, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4793, + IF_NOT_tagLookup_mRsps_ff_lhead_read__894_MINU_ETC___d4775, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3568, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3607, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3640, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3724, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3749, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4105, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4115, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4233, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4334, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4394, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4398, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4404, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4408, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4415, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4419, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4425, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4429, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4436, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4440, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4446, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4450, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4457, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4461, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4467, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4471, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4500, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4595, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4599, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4604, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4608, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4614, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4618, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4623, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4627, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4715, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4723, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4727, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4959, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d5017, + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4210, + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4924, + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4925, + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4926, + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4927, + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4928, + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4929, + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4930, + IF_lookupRsp_bag_748_BIT_17_761_AND_lookupRsp__ETC___d6168, + IF_lookupRsp_insertItem_whas__738_AND_lookupRs_ETC___d5763, + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6108, + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6121, + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6134, + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6179, + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6180, + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6185, + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971, + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193, + IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5367, + IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5477, + IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5366, + IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5476, + IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5706, + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5365, + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5475, + IF_tagLookup_tagCache_cts_read__795_BITS_100_T_ETC___d4547, + IF_tagLookup_tagCache_cts_read__795_BITS_100_T_ETC___d4551, + IF_tagLookup_tagCache_cts_read__795_BITS_100_T_ETC___d4556, + IF_tagLookup_tagCache_cts_read__795_BITS_100_T_ETC___d4560, + IF_tagLookup_tagCache_cts_read__795_BITS_143_T_ETC___d3628, + IF_tagLookup_tagCache_cts_read__795_BITS_224_T_ETC___d4544, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3604, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3637, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3639, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4102, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4104, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4112, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4217, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4230, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4238, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4241, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4243, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4322, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4335, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4391, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4393, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4395, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4401, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4403, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4405, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4412, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4414, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4416, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4422, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4424, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4426, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4433, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4435, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4437, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4443, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4445, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4447, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4454, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4456, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4458, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4464, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4466, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4468, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4497, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4498, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4501, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4592, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4594, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4596, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4601, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4603, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4605, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4611, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4613, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4615, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4620, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4622, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4624, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4670, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4739, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4759, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4776, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4779, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4792, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4795, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d5000, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5052, + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4567, + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4568, + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4573, + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4579, + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4584, + IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d2975, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2201, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2315, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2338, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2369, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2383, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2408, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2419, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2438, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2446, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2459, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2464, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2471, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2473, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2478, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2483, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2496, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2504, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2523, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2534, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2559, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2573, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2604, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2621, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1030, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1144, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1167, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1198, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1212, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1237, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1248, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1267, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1275, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1288, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1293, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1300, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1302, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1307, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1312, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1325, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1333, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1352, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1363, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1388, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1402, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1433, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1450, + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3266, + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3272, + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d4762, + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d5022, + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d5028, + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3274, + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3503, + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3561, + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3599, + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3744, + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d4248, + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d4658, + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d3970, + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4192, + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4311, + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4665, + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4710, + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d5013, + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3465, + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3468, + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3471, + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3474, + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4050, + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4058, + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4067, + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4075, + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3431, + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3434, + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3437, + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3440, + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4053, + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4061, + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4070, + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4078, + IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358, + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5922, + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941, + NOT_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead__ETC___d4007, + NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read__351_ETC___d4092, + NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read__351_ETC___d4107, + NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read__351_ETC___d4676, + NOT_SEL_ARR_IF_tagLookup_tagCache_tags_0_readA_ETC___d3563, + NOT_SEL_ARR_IF_tagLookup_tagCache_tags_0_readA_ETC___d4234, + NOT_SEL_ARR_NOT_tagLookup_tagCache_req_commits_ETC___d4094, + NOT_SEL_ARR_NOT_tagLookup_tagCache_req_commits_ETC___d4124, + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3151, + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964, + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d4203, + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d4698, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d3297, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d3953, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4354, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4356, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4359, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4361, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4368, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4372, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4377, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4381, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4661, + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3522, + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3534, + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3537, + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3548, + NOT_tagLookup_tagCache_cts_read__795_BITS_143__ETC___d3627, + NOT_tagLookup_tagCache_cts_read__795_BITS_143__ETC___d4951, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3492, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3516, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4010, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4013, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4017, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4214, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4250, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4324, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4697, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4705, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4712, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4756, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4991, + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d5015, + NOT_tagLookup_tagCache_cts_read__795_BITS_278__ETC___d4253, + NOT_tagLookup_tagCache_cts_read__795_BIT_136_0_ETC___d3625, + NOT_tagLookup_tagCache_cts_read__795_BIT_226_5_ETC___d4121, + NOT_tagLookup_tagCache_missedResp_whas__080_08_ETC___d5095, + NOT_tagLookup_tagCache_missedResp_whas__080_08_ETC___d5111, + NOT_tagLookup_tagCache_missedResp_whas__080_08_ETC___d5137, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1580, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1582, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1584, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1586, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1588, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1590, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1592, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d2951, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d2955, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d2959, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d2961, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5058, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5060, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5064, + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5066, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2144, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2146, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2148, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2150, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2152, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2154, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2156, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2158, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2160, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2162, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2164, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2166, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2168, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2170, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2172, + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2198, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1777, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1804, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1833, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1862, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1893, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1924, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1957, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1963, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1968, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1990, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1996, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2002, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2025, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2031, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2038, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2053, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2059, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2069, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2511, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2520, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2530, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2541, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2553, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2566, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2580, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2586, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2595, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2601, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2611, + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2617, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3841, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3843, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3845, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3847, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3849, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3851, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3853, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3855, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d389, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d391, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d393, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d395, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d397, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d399, + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d401, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1001, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1027, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d973, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d975, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d977, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d979, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d981, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d983, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d985, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d987, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d989, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d991, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d993, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d995, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d997, + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d999, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1340, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1349, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1359, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1370, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1382, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1395, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1409, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1415, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1424, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1430, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1440, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1446, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d606, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d633, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d662, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d691, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d722, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d753, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d786, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d792, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d797, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d819, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d825, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d831, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d854, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d860, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d867, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d882, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d888, + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d898, + NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d3016, + NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d4279, + NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d5021, + NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d5176, + NOT_tagLookup_tagCache_readReqReg_read__136_BI_ETC___d3284, + NOT_tagLookup_tagCache_readReqReg_read__136_BI_ETC___d3960, + NOT_tagLookup_tagCache_readReqReg_read__136_BI_ETC___d4954, + NOT_tagLookup_tagCache_respsReady_whas__145_31_ETC___d5317, + NOT_tagLookup_tagCache_writebacks_i_notEmpty___ETC___d3076, + NOT_writeBuffer_ff_lhead_read__893_MINUS_write_ETC___d5925, + NOT_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_ETC___d5939, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3601, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3746, + _0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3553, + _0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617, + _0_CONCAT_tagLookup_tagCache_orderer_mastLines__ETC___d2188, + _0_CONCAT_tagLookup_tagCache_orderer_mastReqs_n_ETC___d1017, + _0_OR_NOT_tagLookup_tagCache_cts_read__795_BIT__ETC___d4563, + _16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3557, + _16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619, + _dfoo1, + _dfoo9, + _theResult_____21__h86422, + _theResult_____23__h86225, + _theResult_____3_way__h74739, + _theResult___snd_snd_fst_masterID__h330322, + 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tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5499, + tagLookup_tagCacheReq_ff_lhead_read__179_MINUS_ETC___d5181, + tagLookup_tagCache_cts_read__795_BITS_100_TO_9_ETC___d3499, + tagLookup_tagCache_cts_read__795_BITS_100_TO_9_ETC___d3501, + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427, + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461, + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3572, + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3575, + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3578, + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3583, + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3632, + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3676, + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4288, + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326, + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4733, + tagLookup_tagCache_cts_read__795_BITS_143_TO_1_ETC___d3991, + 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tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d470, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d471, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d494, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d495, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d517, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d518, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d542, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d543, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d567, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d568, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d594, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d595, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d621, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d622, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d650, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d651, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d679, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d680, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d710, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d711, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d741, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d742, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d774, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d775, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d807, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d808, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d842, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d843, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d891, + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d893, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1303, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1306, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1311, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1317, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1324, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1332, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1341, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1351, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1362, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1374, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1387, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1401, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1416, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1432, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1449, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1453, + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1022, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1173, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1179, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1189, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1195, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1204, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1210, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1218, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1224, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1231, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1243, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1254, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1264, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1273, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1281, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d747, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d780, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d813, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d848, + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2810, + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2849, + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2850, + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2963, + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3268, + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3269, + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3511, + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4086, + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348, + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4708, + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4724, + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4732, + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4740, + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145, + tagLookup_tagCache_readReqReg_read__136_BITS_5_ETC___d3164, + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141, + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3283, + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3299, + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3942, + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3948, + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3956, + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d4989, + tagLookup_tagCache_readReqReg_read__136_BIT_57_ETC___d3162, + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5155, + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334, + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5377, + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403, + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413, + tagLookup_zeroAddr_211_ULT_4286574718___d5212, + tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992, + way__h98147, + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5907, + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5909, + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5911, + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5912, + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5920, + x1_avValue_snd_fst_way__h121115, + x1_avValue_snd_fst_way__h121202, + x1_avValue_snd_snd_snd_snd_d_inId_masterID__h278680, + x1_avValue_snd_snd_snd_snd_d_oldWay__h278641, + x1_avValue_snd_snd_snd_snd_snd_snd_d_inId_masterID__h278682, + x1_avValue_snd_snd_snd_snd_snd_snd_d_inId_masterID__h278684, + x1_avValue_snd_snd_snd_snd_snd_snd_d_oldWay__h278650, + x1_avValue_snd_snd_snd_snd_snd_snd_fst_req_masterID__h98350, + x1_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_fst_d_inId_masterID__h278688, + x1_avValue_snd_way__h121184, + x1_avValue_way__h74757, + x__h330273, + x__h78976, + y_avValue_snd_fst__h98183, + y_avValue_snd_fst_way__h121090; + + // value method cache_request_canPut + assign cache_request_canPut = + tagLookup_state_read__216_EQ_1_370_AND_NOT_tag_ETC___d5989 && + !tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 && + !addrFrame_bag[15] ; + + // action method cache_request_put + assign RDY_cache_request_put = + tagLookup_state_read__216_EQ_1_370_AND_NOT_tag_ETC___d5989 && + !tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 && + !addrFrame_bag[15] && + level__h313914 != 5'd16 && + !tagLookup_readReqs_ff_full$port1__read ; + assign CAN_FIRE_cache_request_put = RDY_cache_request_put ; + assign WILL_FIRE_cache_request_put = EN_cache_request_put ; + + // value method cache_response_canGet + assign cache_response_canGet = RDY_cache_response_get ; + + // value method cache_response_peek + assign cache_response_peek = cache_response_get ; + assign RDY_cache_response_peek = 1'd1 ; + + // actionvalue method cache_response_get + assign cache_response_get = + { x__h330273, + x__h330335, + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6119, + IF_IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff__ETC___d6137, + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6171 } ; + assign RDY_cache_response_get = + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6108 || + level__h314581 != 6'd0 && mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 ; + assign CAN_FIRE_cache_response_get = RDY_cache_response_get ; + assign WILL_FIRE_cache_response_get = EN_cache_response_get ; + + // value method memory_request_canGet + assign memory_request_canGet = level__h314247 != 2'd0 ; + + // value method memory_request_peek + assign memory_request_peek = + { mReqs_ff_rf$D_OUT_1[140:94], + CASE_mReqs_ff_rfD_OUT_1_BITS_93_TO_92_0_mReqs_ETC__q1, + mReqs_ff_rf$D_OUT_1[91:0] } ; + assign RDY_memory_request_peek = level__h314247 != 2'd0 ; + + // actionvalue method memory_request_get + assign memory_request_get = + { mReqs_ff_rf$D_OUT_1[140:94], + CASE_mReqs_ff_rfD_OUT_1_BITS_93_TO_92_0_mReqs_ETC__q1, + mReqs_ff_rf$D_OUT_1[91:0] } ; + assign RDY_memory_request_get = level__h314247 != 2'd0 ; + assign CAN_FIRE_memory_request_get = level__h314247 != 2'd0 ; + assign WILL_FIRE_memory_request_get = EN_memory_request_get ; + + // value method memory_response_canPut + assign memory_response_canPut = + level__h314581 != 6'd32 && level__h1463 != 2'd2 ; + + // action method memory_response_put + assign RDY_memory_response_put = level__h1463 != 2'd2 ; + assign CAN_FIRE_memory_response_put = level__h1463 != 2'd2 ; + assign WILL_FIRE_memory_response_put = EN_memory_response_put ; + + // submodule mReqs_ff_rf + RegFile #(.addr_width(32'd1), + .data_width(32'd141), + .lo(1'h0), + .hi(1'd1)) mReqs_ff_rf(.CLK(CLK), + .ADDR_1(mReqs_ff_rf$ADDR_1), + .ADDR_2(mReqs_ff_rf$ADDR_2), + .ADDR_3(mReqs_ff_rf$ADDR_3), + .ADDR_4(mReqs_ff_rf$ADDR_4), + .ADDR_5(mReqs_ff_rf$ADDR_5), + .ADDR_IN(mReqs_ff_rf$ADDR_IN), + .D_IN(mReqs_ff_rf$D_IN), + .WE(mReqs_ff_rf$WE), + .D_OUT_1(mReqs_ff_rf$D_OUT_1), + .D_OUT_2(), + .D_OUT_3(), + .D_OUT_4(), + .D_OUT_5()); + + // submodule mRsps_ff_rf + RegFile #(.addr_width(32'd5), + .data_width(32'd77), + .lo(5'h0), + .hi(5'd31)) mRsps_ff_rf(.CLK(CLK), + .ADDR_1(mRsps_ff_rf$ADDR_1), + .ADDR_2(mRsps_ff_rf$ADDR_2), + .ADDR_3(mRsps_ff_rf$ADDR_3), + .ADDR_4(mRsps_ff_rf$ADDR_4), + .ADDR_5(mRsps_ff_rf$ADDR_5), + .ADDR_IN(mRsps_ff_rf$ADDR_IN), + .D_IN(mRsps_ff_rf$D_IN), + .WE(mRsps_ff_rf$WE), + .D_OUT_1(mRsps_ff_rf$D_OUT_1), + .D_OUT_2(), + .D_OUT_3(), + .D_OUT_4(), + .D_OUT_5()); + + // submodule tagLookup_mReqs_ff_rf + RegFile #(.addr_width(32'd3), + .data_width(32'd141), + .lo(3'h0), + .hi(3'd7)) tagLookup_mReqs_ff_rf(.CLK(CLK), + .ADDR_1(tagLookup_mReqs_ff_rf$ADDR_1), + .ADDR_2(tagLookup_mReqs_ff_rf$ADDR_2), + .ADDR_3(tagLookup_mReqs_ff_rf$ADDR_3), + .ADDR_4(tagLookup_mReqs_ff_rf$ADDR_4), + .ADDR_5(tagLookup_mReqs_ff_rf$ADDR_5), + .ADDR_IN(tagLookup_mReqs_ff_rf$ADDR_IN), + .D_IN(tagLookup_mReqs_ff_rf$D_IN), + .WE(tagLookup_mReqs_ff_rf$WE), + .D_OUT_1(tagLookup_mReqs_ff_rf$D_OUT_1), + .D_OUT_2(), + .D_OUT_3(), + .D_OUT_4(), + .D_OUT_5()); + + // submodule tagLookup_mRsps_ff_rf + RegFile #(.addr_width(32'd1), + .data_width(32'd77), + .lo(1'h0), + .hi(1'd1)) tagLookup_mRsps_ff_rf(.CLK(CLK), + .ADDR_1(tagLookup_mRsps_ff_rf$ADDR_1), + .ADDR_2(tagLookup_mRsps_ff_rf$ADDR_2), + .ADDR_3(tagLookup_mRsps_ff_rf$ADDR_3), + .ADDR_4(tagLookup_mRsps_ff_rf$ADDR_4), + .ADDR_5(tagLookup_mRsps_ff_rf$ADDR_5), + .ADDR_IN(tagLookup_mRsps_ff_rf$ADDR_IN), + .D_IN(tagLookup_mRsps_ff_rf$D_IN), + .WE(tagLookup_mRsps_ff_rf$WE), + .D_OUT_1(tagLookup_mRsps_ff_rf$D_OUT_1), + .D_OUT_2(), + .D_OUT_3(), + .D_OUT_4(), + .D_OUT_5()); + + // submodule tagLookup_tagCache_data_0_bram_bram + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd10), + .DATA_WIDTH(32'd64), + .MEMSIZE(11'd1024)) tagLookup_tagCache_data_0_bram_bram(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(tagLookup_tagCache_data_0_bram_bram$ADDRA), + .ADDRB(tagLookup_tagCache_data_0_bram_bram$ADDRB), + .DIA(tagLookup_tagCache_data_0_bram_bram$DIA), + .DIB(tagLookup_tagCache_data_0_bram_bram$DIB), + .WEA(tagLookup_tagCache_data_0_bram_bram$WEA), + .WEB(tagLookup_tagCache_data_0_bram_bram$WEB), + .ENA(tagLookup_tagCache_data_0_bram_bram$ENA), + .ENB(tagLookup_tagCache_data_0_bram_bram$ENB), + .DOA(tagLookup_tagCache_data_0_bram_bram$DOA), + .DOB()); + + // submodule tagLookup_tagCache_data_1_bram_bram + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd10), + .DATA_WIDTH(32'd64), + .MEMSIZE(11'd1024)) tagLookup_tagCache_data_1_bram_bram(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(tagLookup_tagCache_data_1_bram_bram$ADDRA), + .ADDRB(tagLookup_tagCache_data_1_bram_bram$ADDRB), + .DIA(tagLookup_tagCache_data_1_bram_bram$DIA), + .DIB(tagLookup_tagCache_data_1_bram_bram$DIB), + .WEA(tagLookup_tagCache_data_1_bram_bram$WEA), + .WEB(tagLookup_tagCache_data_1_bram_bram$WEB), + .ENA(tagLookup_tagCache_data_1_bram_bram$ENA), + .ENB(tagLookup_tagCache_data_1_bram_bram$ENB), + .DOA(tagLookup_tagCache_data_1_bram_bram$DOA), + .DOB()); + + // submodule tagLookup_tagCache_delayedInvalidates_ff_rf + RegFile #(.addr_width(32'd3), + .data_width(32'd37), + .lo(3'h0), + .hi(3'd7)) tagLookup_tagCache_delayedInvalidates_ff_rf(.CLK(CLK), + .ADDR_1(tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_1), + .ADDR_2(tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_2), + .ADDR_3(tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_3), + .ADDR_4(tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_4), + .ADDR_5(tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_5), + .ADDR_IN(tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_IN), + .D_IN(tagLookup_tagCache_delayedInvalidates_ff_rf$D_IN), + .WE(tagLookup_tagCache_delayedInvalidates_ff_rf$WE), + .D_OUT_1(), + .D_OUT_2(), + .D_OUT_3(), + .D_OUT_4(), + .D_OUT_5()); + + // submodule tagLookup_tagCache_invalidateWritebacks + FIFO1 #(.width(32'd89), + .guarded(32'd0)) tagLookup_tagCache_invalidateWritebacks(.RST(RST_N), + .CLK(CLK), + .D_IN(tagLookup_tagCache_invalidateWritebacks$D_IN), + .ENQ(tagLookup_tagCache_invalidateWritebacks$ENQ), + .DEQ(tagLookup_tagCache_invalidateWritebacks$DEQ), + .CLR(tagLookup_tagCache_invalidateWritebacks$CLR), + .D_OUT(), + .FULL_N(), + .EMPTY_N(tagLookup_tagCache_invalidateWritebacks$EMPTY_N)); + + // submodule tagLookup_tagCache_invalidatesDone_ff_rf + RegFile #(.addr_width(32'd5), + .data_width(32'd1), + .lo(5'h0), + .hi(5'd31)) tagLookup_tagCache_invalidatesDone_ff_rf(.CLK(CLK), + .ADDR_1(tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_1), + .ADDR_2(tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_2), + .ADDR_3(tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_3), + .ADDR_4(tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_4), + .ADDR_5(tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_5), + .ADDR_IN(tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_IN), + .D_IN(tagLookup_tagCache_invalidatesDone_ff_rf$D_IN), + .WE(tagLookup_tagCache_invalidatesDone_ff_rf$WE), + .D_OUT_1(), + .D_OUT_2(), + .D_OUT_3(), + .D_OUT_4(), + .D_OUT_5()); + + // submodule tagLookup_tagCache_invalidates_ff_rf + RegFile #(.addr_width(32'd2), + .data_width(32'd40), + .lo(2'h0), + .hi(2'd3)) tagLookup_tagCache_invalidates_ff_rf(.CLK(CLK), + .ADDR_1(tagLookup_tagCache_invalidates_ff_rf$ADDR_1), + .ADDR_2(tagLookup_tagCache_invalidates_ff_rf$ADDR_2), + .ADDR_3(tagLookup_tagCache_invalidates_ff_rf$ADDR_3), + .ADDR_4(tagLookup_tagCache_invalidates_ff_rf$ADDR_4), + .ADDR_5(tagLookup_tagCache_invalidates_ff_rf$ADDR_5), + .ADDR_IN(tagLookup_tagCache_invalidates_ff_rf$ADDR_IN), + .D_IN(tagLookup_tagCache_invalidates_ff_rf$D_IN), + .WE(tagLookup_tagCache_invalidates_ff_rf$WE), + .D_OUT_1(), + .D_OUT_2(), + .D_OUT_3(), + .D_OUT_4(), + .D_OUT_5()); + + // submodule tagLookup_tagCache_orderer_waitingSlaveReq_rf + RegFile #(.addr_width(32'd1), + .data_width(32'd6), + .lo(1'h0), + .hi(1'd1)) tagLookup_tagCache_orderer_waitingSlaveReq_rf(.CLK(CLK), + .ADDR_1(tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_1), + .ADDR_2(tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_2), + .ADDR_3(tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_3), + .ADDR_4(tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_4), + .ADDR_5(tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_5), + .ADDR_IN(tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_IN), + .D_IN(tagLookup_tagCache_orderer_waitingSlaveReq_rf$D_IN), + .WE(tagLookup_tagCache_orderer_waitingSlaveReq_rf$WE), + .D_OUT_1(), + .D_OUT_2(), + .D_OUT_3(), + .D_OUT_4(), + .D_OUT_5()); + + // submodule tagLookup_tagCache_tags_0_bramA_bram + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd8), + .DATA_WIDTH(32'd41), + .MEMSIZE(9'd256)) tagLookup_tagCache_tags_0_bramA_bram(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(tagLookup_tagCache_tags_0_bramA_bram$ADDRA), + .ADDRB(tagLookup_tagCache_tags_0_bramA_bram$ADDRB), + .DIA(tagLookup_tagCache_tags_0_bramA_bram$DIA), + .DIB(tagLookup_tagCache_tags_0_bramA_bram$DIB), + .WEA(tagLookup_tagCache_tags_0_bramA_bram$WEA), + .WEB(tagLookup_tagCache_tags_0_bramA_bram$WEB), + .ENA(tagLookup_tagCache_tags_0_bramA_bram$ENA), + .ENB(tagLookup_tagCache_tags_0_bramA_bram$ENB), + .DOA(tagLookup_tagCache_tags_0_bramA_bram$DOA), + .DOB()); + + // submodule tagLookup_tagCache_tags_0_bramB_bram + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd8), + .DATA_WIDTH(32'd41), + .MEMSIZE(9'd256)) tagLookup_tagCache_tags_0_bramB_bram(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(tagLookup_tagCache_tags_0_bramB_bram$ADDRA), + .ADDRB(tagLookup_tagCache_tags_0_bramB_bram$ADDRB), + .DIA(tagLookup_tagCache_tags_0_bramB_bram$DIA), + .DIB(tagLookup_tagCache_tags_0_bramB_bram$DIB), + .WEA(tagLookup_tagCache_tags_0_bramB_bram$WEA), + .WEB(tagLookup_tagCache_tags_0_bramB_bram$WEB), + .ENA(tagLookup_tagCache_tags_0_bramB_bram$ENA), + .ENB(tagLookup_tagCache_tags_0_bramB_bram$ENB), + .DOA(), + .DOB()); + + // submodule tagLookup_tagCache_tags_1_bramA_bram + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd8), + .DATA_WIDTH(32'd41), + .MEMSIZE(9'd256)) tagLookup_tagCache_tags_1_bramA_bram(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(tagLookup_tagCache_tags_1_bramA_bram$ADDRA), + .ADDRB(tagLookup_tagCache_tags_1_bramA_bram$ADDRB), + .DIA(tagLookup_tagCache_tags_1_bramA_bram$DIA), + .DIB(tagLookup_tagCache_tags_1_bramA_bram$DIB), + .WEA(tagLookup_tagCache_tags_1_bramA_bram$WEA), + .WEB(tagLookup_tagCache_tags_1_bramA_bram$WEB), + .ENA(tagLookup_tagCache_tags_1_bramA_bram$ENA), + .ENB(tagLookup_tagCache_tags_1_bramA_bram$ENB), + .DOA(tagLookup_tagCache_tags_1_bramA_bram$DOA), + .DOB()); + + // submodule tagLookup_tagCache_tags_1_bramB_bram + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd8), + .DATA_WIDTH(32'd41), + .MEMSIZE(9'd256)) tagLookup_tagCache_tags_1_bramB_bram(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(tagLookup_tagCache_tags_1_bramB_bram$ADDRA), + .ADDRB(tagLookup_tagCache_tags_1_bramB_bram$ADDRB), + .DIA(tagLookup_tagCache_tags_1_bramB_bram$DIA), + .DIB(tagLookup_tagCache_tags_1_bramB_bram$DIB), + .WEA(tagLookup_tagCache_tags_1_bramB_bram$WEA), + .WEB(tagLookup_tagCache_tags_1_bramB_bram$WEB), + .ENA(tagLookup_tagCache_tags_1_bramB_bram$ENA), + .ENB(tagLookup_tagCache_tags_1_bramB_bram$ENB), + .DOA(), + .DOB()); + + // submodule tagLookup_tagCache_writeResps_ff_rf + RegFile #(.addr_width(32'd1), + .data_width(32'd8), + .lo(1'h0), + .hi(1'd1)) tagLookup_tagCache_writeResps_ff_rf(.CLK(CLK), + .ADDR_1(tagLookup_tagCache_writeResps_ff_rf$ADDR_1), + .ADDR_2(tagLookup_tagCache_writeResps_ff_rf$ADDR_2), + .ADDR_3(tagLookup_tagCache_writeResps_ff_rf$ADDR_3), + .ADDR_4(tagLookup_tagCache_writeResps_ff_rf$ADDR_4), + .ADDR_5(tagLookup_tagCache_writeResps_ff_rf$ADDR_5), + .ADDR_IN(tagLookup_tagCache_writeResps_ff_rf$ADDR_IN), + .D_IN(tagLookup_tagCache_writeResps_ff_rf$D_IN), + .WE(tagLookup_tagCache_writeResps_ff_rf$WE), + .D_OUT_1(), + .D_OUT_2(), + .D_OUT_3(), + .D_OUT_4(), + .D_OUT_5()); + + // submodule tagLookup_tagCache_writebacks + FIFO1 #(.width(32'd89), + .guarded(32'd0)) tagLookup_tagCache_writebacks(.RST(RST_N), + .CLK(CLK), + .D_IN(tagLookup_tagCache_writebacks$D_IN), + .ENQ(tagLookup_tagCache_writebacks$ENQ), + .DEQ(tagLookup_tagCache_writebacks$DEQ), + .CLR(tagLookup_tagCache_writebacks$CLR), + .D_OUT(tagLookup_tagCache_writebacks$D_OUT), + .FULL_N(), + .EMPTY_N(tagLookup_tagCache_writebacks$EMPTY_N)); + + // submodule tagLookup_useNextRsp_ff_rf + RegFile #(.addr_width(32'd2), + .data_width(32'd1), + .lo(2'h0), + .hi(2'd3)) tagLookup_useNextRsp_ff_rf(.CLK(CLK), + .ADDR_1(tagLookup_useNextRsp_ff_rf$ADDR_1), + .ADDR_2(tagLookup_useNextRsp_ff_rf$ADDR_2), + .ADDR_3(tagLookup_useNextRsp_ff_rf$ADDR_3), + .ADDR_4(tagLookup_useNextRsp_ff_rf$ADDR_4), + .ADDR_5(tagLookup_useNextRsp_ff_rf$ADDR_5), + .ADDR_IN(tagLookup_useNextRsp_ff_rf$ADDR_IN), + .D_IN(tagLookup_useNextRsp_ff_rf$D_IN), + .WE(tagLookup_useNextRsp_ff_rf$WE), + .D_OUT_1(tagLookup_useNextRsp_ff_rf$D_OUT_1), + .D_OUT_2(), + .D_OUT_3(), + .D_OUT_4(), + .D_OUT_5()); + + // submodule writeBuffer_ff_rf + RegFile #(.addr_width(32'd4), + .data_width(32'd141), + .lo(4'h0), + .hi(4'd15)) writeBuffer_ff_rf(.CLK(CLK), + .ADDR_1(writeBuffer_ff_rf$ADDR_1), + .ADDR_2(writeBuffer_ff_rf$ADDR_2), + .ADDR_3(writeBuffer_ff_rf$ADDR_3), + .ADDR_4(writeBuffer_ff_rf$ADDR_4), + .ADDR_5(writeBuffer_ff_rf$ADDR_5), + .ADDR_IN(writeBuffer_ff_rf$ADDR_IN), + .D_IN(writeBuffer_ff_rf$D_IN), + .WE(writeBuffer_ff_rf$WE), + .D_OUT_1(writeBuffer_ff_rf$D_OUT_1), + .D_OUT_2(), + .D_OUT_3(), + .D_OUT_4(), + .D_OUT_5()); + + // rule RL_forwardLookupReqs + assign CAN_FIRE_RL_forwardLookupReqs = + level__h1012 != 4'd0 && level__h314247 != 2'd2 ; + assign WILL_FIRE_RL_forwardLookupReqs = CAN_FIRE_RL_forwardLookupReqs ; + + // rule RL_getTagLookupResponse + assign CAN_FIRE_RL_getTagLookupResponse = + (!tagLookup_readReqs_ff_dataReg || + tagLookup_lookupRsp_ff_lhead_read__318_MINUS_t_ETC___d5320) && + tagLookup_readReqs_ff_full ; + assign WILL_FIRE_RL_getTagLookupResponse = + CAN_FIRE_RL_getTagLookupResponse ; + + // rule RL_drainWritebuffer + assign CAN_FIRE_RL_drainWritebuffer = + tagLookup_state == 3'd1 && + NOT_writeBuffer_ff_lhead_read__893_MINUS_write_ETC___d5925 && + !MUX_tagLookup_reqeustId$write_1__SEL_1 ; + assign WILL_FIRE_RL_drainWritebuffer = + CAN_FIRE_RL_drainWritebuffer && !EN_cache_request_put ; + + // rule RL_tagLookup_initialise + assign CAN_FIRE_RL_tagLookup_initialise = + (!tagLookup_zeroAddr_211_ULT_4286574718___d5212 || + !tagLookup_tagCacheReq_ff_lhead_read__179_MINUS_ETC___d5181) && + tagLookup_state == 3'd0 ; + assign WILL_FIRE_RL_tagLookup_initialise = + CAN_FIRE_RL_tagLookup_initialise ; + + // rule RL_tagLookup_stuffCommits + assign CAN_FIRE_RL_tagLookup_stuffCommits = + tagLookup_tagCache_req_commits_level != 5'd16 ; + assign WILL_FIRE_RL_tagLookup_stuffCommits = + CAN_FIRE_RL_tagLookup_stuffCommits ; + + // rule RL_tagLookup_lookupRsp_displayEnqPanic + assign CAN_FIRE_RL_tagLookup_lookupRsp_displayEnqPanic = 1'b0 ; + assign WILL_FIRE_RL_tagLookup_lookupRsp_displayEnqPanic = 1'b0 ; + + // rule RL_tagLookup_lookupRsp_displayDeqPanic + assign CAN_FIRE_RL_tagLookup_lookupRsp_displayDeqPanic = 1'b0 ; + assign WILL_FIRE_RL_tagLookup_lookupRsp_displayDeqPanic = 1'b0 ; + + // rule RL_tagLookup_lookupRsp_ff_doDisplayPanic + assign CAN_FIRE_RL_tagLookup_lookupRsp_ff_doDisplayPanic = 1'b0 ; + assign WILL_FIRE_RL_tagLookup_lookupRsp_ff_doDisplayPanic = 1'b0 ; + + // rule RL_tagLookup_mReqs_displayDeqPanic + assign CAN_FIRE_RL_tagLookup_mReqs_displayDeqPanic = 1'b0 ; + assign WILL_FIRE_RL_tagLookup_mReqs_displayDeqPanic = 1'b0 ; + + // rule RL_tagLookup_mRsps_displayEnqPanic + assign CAN_FIRE_RL_tagLookup_mRsps_displayEnqPanic = + CAN_FIRE_RL_tagLookup_mRsps_ff_doDisplayPanic ; + assign WILL_FIRE_RL_tagLookup_mRsps_displayEnqPanic = + CAN_FIRE_RL_tagLookup_mRsps_ff_doDisplayPanic ; + + // rule RL_tagLookup_mRsps_displayDeqPanic + assign CAN_FIRE_RL_tagLookup_mRsps_displayDeqPanic = 1'b0 ; + assign WILL_FIRE_RL_tagLookup_mRsps_displayDeqPanic = 1'b0 ; + + // rule RL_tagLookup_mRsps_ff_doDisplayPanic + assign CAN_FIRE_RL_tagLookup_mRsps_ff_doDisplayPanic = + EN_memory_response_put && memory_response_put_val[76] && + level__h1463 == 2'd2 ; + assign WILL_FIRE_RL_tagLookup_mRsps_ff_doDisplayPanic = + CAN_FIRE_RL_tagLookup_mRsps_ff_doDisplayPanic ; + + // rule RL_tagLookup_useNextRsp_displayEnqPanic + assign CAN_FIRE_RL_tagLookup_useNextRsp_displayEnqPanic = + WILL_FIRE_RL_tagLookup_initialise && + tagLookup_zeroAddr_211_ULT_4286574718___d5212 && + level__h1913 == 3'd4 || + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 && + level__h1913 == 3'd4 || + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 && + level__h1913 == 3'd4 ; + assign WILL_FIRE_RL_tagLookup_useNextRsp_displayEnqPanic = + CAN_FIRE_RL_tagLookup_useNextRsp_displayEnqPanic ; + + // rule RL_tagLookup_useNextRsp_ff_doDisplayPanic + assign CAN_FIRE_RL_tagLookup_useNextRsp_ff_doDisplayPanic = + WILL_FIRE_RL_tagLookup_initialise && + tagLookup_zeroAddr_211_ULT_4286574718___d5212 && + level__h1913 == 3'd4 || + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 && + level__h1913 == 3'd4 || + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 && + level__h1913 == 3'd4 ; + assign WILL_FIRE_RL_tagLookup_useNextRsp_ff_doDisplayPanic = + CAN_FIRE_RL_tagLookup_useNextRsp_ff_doDisplayPanic ; + + // rule RL_tagLookup_tagCache_initialize + assign CAN_FIRE_RL_tagLookup_tagCache_initialize = + !tagLookup_tagCache_cacheState ; + assign WILL_FIRE_RL_tagLookup_tagCache_initialize = + CAN_FIRE_RL_tagLookup_tagCache_initialize ; + + // rule RL_tagLookup_tagCache_writeNextEmpty + assign CAN_FIRE_RL_tagLookup_tagCache_writeNextEmpty = 1'd1 ; + assign WILL_FIRE_RL_tagLookup_tagCache_writeNextEmpty = 1'd1 ; + + // rule RL_tagLookup_tagCache_finishLookup + assign CAN_FIRE_RL_tagLookup_tagCache_finishLookup = + tagLookup_tagCache_cacheState ; + assign WILL_FIRE_RL_tagLookup_tagCache_finishLookup = + tagLookup_tagCache_cacheState ; + + // rule RL_tagLookup_doLookup + assign CAN_FIRE_RL_tagLookup_doLookup = + ((tagLookup_state != 3'd2 || + NOT_tagLookup_tagCache_respsReady_whas__145_31_ETC___d5317 || + tagLookup_lookupRsp_ff_lhead_read__318_MINUS_t_ETC___d5320) && + (tagLookup_state != 3'd3 || + NOT_tagLookup_tagCache_respsReady_whas__145_31_ETC___d5317) && + (tagLookup_state != 3'd4 || + NOT_tagLookup_tagCache_respsReady_whas__145_31_ETC___d5317) && + tagLookup_state != 3'd5 || + IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5367 || + !tagLookup_tagCacheReq_ff_lhead_read__179_MINUS_ETC___d5181) && + tagLookup_state != 3'd1 && + tagLookup_state != 3'd0 && + level__h1913 != 3'd4 ; + assign WILL_FIRE_RL_tagLookup_doLookup = CAN_FIRE_RL_tagLookup_doLookup ; + + // rule RL_tagLookup_drainMemRsp + assign CAN_FIRE_RL_tagLookup_drainMemRsp = + (tagLookup_tagCache_cacheState && + tagLookup_tagCache_respsReady$wget || + level__h8616 != 2'd0) && + (tagLookup_getReq$whas || !tagLookup_useNextRsp_ff_rf$D_OUT_1) ; + assign WILL_FIRE_RL_tagLookup_drainMemRsp = + CAN_FIRE_RL_tagLookup_drainMemRsp ; + + // rule RL_tagLookup_mReqs_displayEnqPanic + assign CAN_FIRE_RL_tagLookup_mReqs_displayEnqPanic = + CAN_FIRE_RL_tagLookup_mReqs_ff_doDisplayPanic ; + assign WILL_FIRE_RL_tagLookup_mReqs_displayEnqPanic = + CAN_FIRE_RL_tagLookup_mReqs_ff_doDisplayPanic ; + + // rule RL_tagLookup_mReqs_ff_doDisplayPanic + assign CAN_FIRE_RL_tagLookup_mReqs_ff_doDisplayPanic = + tagLookup_tagCache_cacheState && + (tagLookup_tagCache_cts[278:277] == 2'd1 && + level__h1012 == 4'd8 || + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3668) ; + assign WILL_FIRE_RL_tagLookup_mReqs_ff_doDisplayPanic = + CAN_FIRE_RL_tagLookup_mReqs_ff_doDisplayPanic ; + + // rule RL_tagLookup_useNextRsp_displayDeqPanic + assign CAN_FIRE_RL_tagLookup_useNextRsp_displayDeqPanic = + WILL_FIRE_RL_tagLookup_drainMemRsp && level__h1913 == 3'd0 ; + assign WILL_FIRE_RL_tagLookup_useNextRsp_displayDeqPanic = + CAN_FIRE_RL_tagLookup_useNextRsp_displayDeqPanic ; + + // rule RL_tagLookup_tagCache_catchResponse + assign CAN_FIRE_RL_tagLookup_tagCache_catchResponse = + !CAN_FIRE_RL_tagLookup_drainMemRsp ; + assign WILL_FIRE_RL_tagLookup_tagCache_catchResponse = + CAN_FIRE_RL_tagLookup_tagCache_catchResponse && + !WILL_FIRE_RL_tagLookup_drainMemRsp ; + + // rule RL_tagLookup_tagCache_commonStateUpdate + assign CAN_FIRE_RL_tagLookup_tagCache_commonStateUpdate = 1'd1 ; + assign WILL_FIRE_RL_tagLookup_tagCache_commonStateUpdate = 1'd1 ; + + // rule RL_tagLookup_feedTagCache + assign CAN_FIRE_RL_tagLookup_feedTagCache = + NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d5176 && + !tagLookup_tagCache_writebacks$EMPTY_N && + !tagLookup_tagCache_invalidateWritebacks$EMPTY_N && + tagLookup_tagCacheReq_ff_lhead_read__179_MINUS_ETC___d5181 ; + assign WILL_FIRE_RL_tagLookup_feedTagCache = + CAN_FIRE_RL_tagLookup_feedTagCache ; + + // rule RL_tagLookup_tagCache_startLookup + assign CAN_FIRE_RL_tagLookup_tagCache_startLookup = + tagLookup_tagCache_cacheState ; + assign WILL_FIRE_RL_tagLookup_tagCache_startLookup = + tagLookup_tagCache_cacheState ; + + // rule RL_tagLookup_tagCacheReq_ff_doDisplayPanic + assign CAN_FIRE_RL_tagLookup_tagCacheReq_ff_doDisplayPanic = + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5471 && + IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5477 && + tagLookup_tagCacheReq_ff_lhead_read__179_MINUS_ETC___d5181 || + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 && + tagLookup_tagCacheReq_ff_lhead_read__179_MINUS_ETC___d5181 || + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 && + tagLookup_tagCacheReq_ff_lhead_read__179_MINUS_ETC___d5181 ; + assign WILL_FIRE_RL_tagLookup_tagCacheReq_ff_doDisplayPanic = + CAN_FIRE_RL_tagLookup_tagCacheReq_ff_doDisplayPanic ; + + // rule RL_tagLookup_tagCache_retryReqs_updateBag + assign CAN_FIRE_RL_tagLookup_tagCache_retryReqs_updateBag = 1'd1 ; + assign WILL_FIRE_RL_tagLookup_tagCache_retryReqs_updateBag = 1'd1 ; + + // rule RL_tagLookup_tagCache_writeResps_displayEnqPanic + assign CAN_FIRE_RL_tagLookup_tagCache_writeResps_displayEnqPanic = 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_writeResps_displayEnqPanic = 1'b0 ; + + // rule RL_tagLookup_tagCache_writeResps_displayDeqPanic + assign CAN_FIRE_RL_tagLookup_tagCache_writeResps_displayDeqPanic = 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_writeResps_displayDeqPanic = 1'b0 ; + + // rule RL_tagLookup_tagCache_writeResps_ff_doDisplayPanic + assign CAN_FIRE_RL_tagLookup_tagCache_writeResps_ff_doDisplayPanic = 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_writeResps_ff_doDisplayPanic = 1'b0 ; + + // rule RL_tagLookup_tagCache_invalidates_displayEnqPanic + assign CAN_FIRE_RL_tagLookup_tagCache_invalidates_displayEnqPanic = 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_invalidates_displayEnqPanic = 1'b0 ; + + // rule RL_tagLookup_tagCache_invalidates_displayDeqPanic + assign CAN_FIRE_RL_tagLookup_tagCache_invalidates_displayDeqPanic = 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_invalidates_displayDeqPanic = 1'b0 ; + + // rule RL_tagLookup_tagCache_invalidates_ff_doDisplayPanic + assign CAN_FIRE_RL_tagLookup_tagCache_invalidates_ff_doDisplayPanic = 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_invalidates_ff_doDisplayPanic = + 1'b0 ; + + // rule RL_tagLookup_tagCache_delayedInvalidates_displayEnqPanic + assign CAN_FIRE_RL_tagLookup_tagCache_delayedInvalidates_displayEnqPanic = + 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_delayedInvalidates_displayEnqPanic = + 1'b0 ; + + // rule RL_tagLookup_tagCache_delayedInvalidates_displayDeqPanic + assign CAN_FIRE_RL_tagLookup_tagCache_delayedInvalidates_displayDeqPanic = + 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_delayedInvalidates_displayDeqPanic = + 1'b0 ; + + // rule RL_tagLookup_tagCache_delayedInvalidates_ff_doDisplayPanic + assign CAN_FIRE_RL_tagLookup_tagCache_delayedInvalidates_ff_doDisplayPanic = + 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_delayedInvalidates_ff_doDisplayPanic = + 1'b0 ; + + // rule RL_tagLookup_tagCache_invalidatesDone_displayEnqPanic + assign CAN_FIRE_RL_tagLookup_tagCache_invalidatesDone_displayEnqPanic = + 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_invalidatesDone_displayEnqPanic = + 1'b0 ; + + // rule RL_tagLookup_tagCache_invalidatesDone_displayDeqPanic + assign CAN_FIRE_RL_tagLookup_tagCache_invalidatesDone_displayDeqPanic = + 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_invalidatesDone_displayDeqPanic = + 1'b0 ; + + // rule RL_tagLookup_tagCache_invalidatesDone_ff_doDisplayPanic + assign CAN_FIRE_RL_tagLookup_tagCache_invalidatesDone_ff_doDisplayPanic = + 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_invalidatesDone_ff_doDisplayPanic = + 1'b0 ; + + // rule RL_tagLookup_tagCache_writethroughNext_displayEnqPanic + assign CAN_FIRE_RL_tagLookup_tagCache_writethroughNext_displayEnqPanic = + 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_writethroughNext_displayEnqPanic = + 1'b0 ; + + // rule RL_tagLookup_tagCache_writethroughNext_displayDeqPanic + assign CAN_FIRE_RL_tagLookup_tagCache_writethroughNext_displayDeqPanic = + 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_writethroughNext_displayDeqPanic = + 1'b0 ; + + // rule RL_tagLookup_tagCache_writethroughNext_ff_doDisplayPanic + assign CAN_FIRE_RL_tagLookup_tagCache_writethroughNext_ff_doDisplayPanic = + 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_writethroughNext_ff_doDisplayPanic = + 1'b0 ; + + // rule RL_tagLookup_tagCache_orderer_slaveReqs_updateBag + assign CAN_FIRE_RL_tagLookup_tagCache_orderer_slaveReqs_updateBag = 1'd1 ; + assign WILL_FIRE_RL_tagLookup_tagCache_orderer_slaveReqs_updateBag = 1'd1 ; + + // rule RL_tagLookup_tagCache_orderer_slaveAddrs_updateBag + assign CAN_FIRE_RL_tagLookup_tagCache_orderer_slaveAddrs_updateBag = 1'd1 ; + assign WILL_FIRE_RL_tagLookup_tagCache_orderer_slaveAddrs_updateBag = 1'd1 ; + + // rule RL_tagLookup_tagCache_orderer_slaveDeps_updateBag + assign CAN_FIRE_RL_tagLookup_tagCache_orderer_slaveDeps_updateBag = 1'd1 ; + assign WILL_FIRE_RL_tagLookup_tagCache_orderer_slaveDeps_updateBag = 1'd1 ; + + // rule RL_tagLookup_tagCache_orderer_waitingSlaveReq_doDisplayPanic + assign CAN_FIRE_RL_tagLookup_tagCache_orderer_waitingSlaveReq_doDisplayPanic = + 1'b0 ; + assign WILL_FIRE_RL_tagLookup_tagCache_orderer_waitingSlaveReq_doDisplayPanic = + 1'b0 ; + + // rule RL_tagLookup_tagCache_orderer_mastReqs_updateBag + assign CAN_FIRE_RL_tagLookup_tagCache_orderer_mastReqs_updateBag = 1'd1 ; + assign WILL_FIRE_RL_tagLookup_tagCache_orderer_mastReqs_updateBag = 1'd1 ; + + // rule RL_tagLookup_tagCache_orderer_mastLines_updateBag + assign CAN_FIRE_RL_tagLookup_tagCache_orderer_mastLines_updateBag = 1'd1 ; + assign WILL_FIRE_RL_tagLookup_tagCache_orderer_mastLines_updateBag = 1'd1 ; + + // rule RL_tagLookup_tagCache_orderer_mastReqIds_updateRf + assign CAN_FIRE_RL_tagLookup_tagCache_orderer_mastReqIds_updateRf = 1'd1 ; + assign WILL_FIRE_RL_tagLookup_tagCache_orderer_mastReqIds_updateRf = 1'd1 ; + + // rule RL_tagLookup_tagCache_readReqs_updateBag + assign CAN_FIRE_RL_tagLookup_tagCache_readReqs_updateBag = 1'd1 ; + assign WILL_FIRE_RL_tagLookup_tagCache_readReqs_updateBag = 1'd1 ; + + // rule RL_lookupRsp_updateBag + assign CAN_FIRE_RL_lookupRsp_updateBag = 1'd1 ; + assign WILL_FIRE_RL_lookupRsp_updateBag = 1'd1 ; + + // rule RL_addrFrame_updateBag + assign CAN_FIRE_RL_addrFrame_updateBag = 1'd1 ; + assign WILL_FIRE_RL_addrFrame_updateBag = 1'd1 ; + + // rule RL_tagOnlyReads_doDisplayPanic + assign CAN_FIRE_RL_tagOnlyReads_doDisplayPanic = + EN_cache_request_put && cache_request_put_val[93:92] == 2'd0 && + cache_request_put_val[6] && + tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 ; + assign WILL_FIRE_RL_tagOnlyReads_doDisplayPanic = + CAN_FIRE_RL_tagOnlyReads_doDisplayPanic ; + + // rule RL_writeBuffer_ff_doDisplayPanic + assign CAN_FIRE_RL_writeBuffer_ff_doDisplayPanic = + EN_cache_request_put && cache_request_put_val[93:92] == 2'd1 && + level__h313914 == 5'd16 ; + assign WILL_FIRE_RL_writeBuffer_ff_doDisplayPanic = + CAN_FIRE_RL_writeBuffer_ff_doDisplayPanic ; + + // rule RL_mReqs_ff_doDisplayPanic + assign CAN_FIRE_RL_mReqs_ff_doDisplayPanic = + EN_cache_request_put && + (cache_request_put_val[93:92] != 2'd0 || + !cache_request_put_val[6]) && + level__h314247 == 2'd2 ; + assign WILL_FIRE_RL_mReqs_ff_doDisplayPanic = + CAN_FIRE_RL_mReqs_ff_doDisplayPanic ; + + // rule RL_mRsps_displayEnqPanic + assign CAN_FIRE_RL_mRsps_displayEnqPanic = + CAN_FIRE_RL_mRsps_ff_doDisplayPanic ; + assign WILL_FIRE_RL_mRsps_displayEnqPanic = + CAN_FIRE_RL_mRsps_ff_doDisplayPanic ; + + // rule RL_mRsps_displayDeqPanic + assign CAN_FIRE_RL_mRsps_displayDeqPanic = + EN_cache_response_get && + (!tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 || + frame != 3'd0) && + level__h314581 == 6'd0 ; + assign WILL_FIRE_RL_mRsps_displayDeqPanic = + CAN_FIRE_RL_mRsps_displayDeqPanic ; + + // rule RL_mRsps_ff_doDisplayPanic + assign CAN_FIRE_RL_mRsps_ff_doDisplayPanic = + EN_memory_response_put && !memory_response_put_val[76] && + level__h314581 == 6'd32 ; + assign WILL_FIRE_RL_mRsps_ff_doDisplayPanic = + CAN_FIRE_RL_mRsps_ff_doDisplayPanic ; + + // inputs to muxes for submodule ports + assign MUX_mReqs_ff_lhead$write_1__SEL_1 = + EN_cache_request_put && + (cache_request_put_val[93:92] != 2'd0 || + !cache_request_put_val[6]) ; + assign MUX_tagLookup_currentDepth$write_1__SEL_1 = + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5471 ; + assign MUX_tagLookup_currentDepth$write_1__SEL_2 = + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 ; + assign MUX_tagLookup_currentDepth$write_1__SEL_3 = + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 ; + assign MUX_tagLookup_readReqs_ff_dataReg$write_1__SEL_1 = + WILL_FIRE_RL_drainWritebuffer && + writeBuffer_ff_rf$D_OUT_1[93:92] == 2'd0 ; + assign MUX_tagLookup_readReqs_ff_dataReg$write_1__SEL_2 = + EN_cache_request_put && cache_request_put_val[93:92] == 2'd0 ; + assign MUX_tagLookup_reqeustId$write_1__SEL_1 = + EN_cache_request_put && cache_request_put_val[93:92] != 2'd1 ; + assign MUX_tagLookup_state$write_1__SEL_1 = + WILL_FIRE_RL_tagLookup_initialise && + !tagLookup_zeroAddr_211_ULT_4286574718___d5212 ; + assign MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_1 = + WILL_FIRE_RL_tagLookup_initialise && + tagLookup_zeroAddr_211_ULT_4286574718___d5212 ; + assign MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_4 = + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5471 && + IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5477 ; + assign MUX_tagLookup_tagCache_missedResp$wset_1__SEL_1 = + WILL_FIRE_RL_tagLookup_drainMemRsp && level__h8616 != 2'd0 ; + assign MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_1__SEL_1 = + tagLookup_tagCache_cacheState && x__h121243 == 1'd0 && + NOT_tagLookup_tagCache_cts_read__795_BITS_278__ETC___d4253 ; + assign MUX_tagLookup_tagCache_tags_1_bramA_bram$b_put_1__SEL_1 = + tagLookup_tagCache_cacheState && x__h121243 == 1'd1 && + NOT_tagLookup_tagCache_cts_read__795_BITS_278__ETC___d4253 ; + assign MUX_tagLookup_tagCache_writeResps_ff_lhead$write_1__SEL_1 = + WILL_FIRE_RL_tagLookup_tagCache_catchResponse && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5155 ; + assign MUX_mReqs_ff_lhead$write_1__VAL_1 = mReqs_ff_lhead + 2'd1 ; + assign MUX_mReqs_ff_rf$upd_2__VAL_1 = + { cache_request_put_val[140:94], + IF_cache_request_put_val_BITS_93_TO_92_997_EQ__ETC___d6049 } ; + assign MUX_mReqs_ff_rf$upd_2__VAL_2 = + { tagLookup_mReqs_ff_rf$D_OUT_1[140:94], + CASE_tagLookup_mReqs_ff_rfD_OUT_1_BITS_93_TO__ETC__q18, + tagLookup_mReqs_ff_rf$D_OUT_1[91:0] } ; + assign MUX_tagLookup_currentDepth$write_1__VAL_1 = + (tagLookup_state == 3'd2 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 && + !tagLookup_lookupRsp_ff_lhead_read__318_MINUS_t_ETC___d5320 || + tagLookup_state == 3'd3 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + tagLookup_currentDepth_338_MINUS_1___d5481 : + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5723 ; + assign MUX_tagLookup_pendingCapEnable$write_1__VAL_1 = + writeBuffer_ff_rf$D_OUT_1[93:92] == 2'd1 && + writeBuffer_ff_rf$D_OUT_1[88:81] != 8'd0 ; + assign MUX_tagLookup_pendingTags$write_1__VAL_1 = + writeBuffer_ff_rf$D_OUT_1[93:92] == 2'd1 && + writeBuffer_ff_rf$D_OUT_1[72] ; + assign MUX_tagLookup_readReqs_ff_dataReg$write_1__VAL_1 = + (writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5907 || + !writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5909) && + !writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5911 && + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5912 ; + assign MUX_tagLookup_readReqs_ff_dataReg$write_1__VAL_2 = + (cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6013 || + !cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6014) && + cache_request_put_val[140:101] >= 40'h00C0000000 && + cache_request_put_val[140:101] < 40'h00FFFFC000 ; + assign MUX_tagLookup_state$write_1__VAL_2 = + (tagLookup_state == 3'd2 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 && + !tagLookup_lookupRsp_ff_lhead_read__318_MINUS_t_ETC___d5320) ? + IF_tagLookup_currentDepth_338_EQ_0_339_THEN_1__ETC___d5726 : + IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5736 ; + always@(writeBuffer_ff_rf$D_OUT_1) + begin + case (writeBuffer_ff_rf$D_OUT_1[93:92]) + 2'd0: MUX_tagLookup_state$write_1__VAL_3 = 3'd2; + 2'd1: + MUX_tagLookup_state$write_1__VAL_3 = + (writeBuffer_ff_rf$D_OUT_1[88:81] == 8'd0) ? + 3'd1 : + (writeBuffer_ff_rf$D_OUT_1[72] ? 3'd3 : 3'd4); + default: MUX_tagLookup_state$write_1__VAL_3 = 3'd1; + endcase + end + assign MUX_tagLookup_tagCacheReq_ff_lhead$write_1__VAL_1 = + tagLookup_tagCacheReq_ff_lhead + 1'd1 ; + assign MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_1 = + { tagLookup_zeroAddr, + 1'd1, + tagLookup_transNum, + 95'h19FFFE0000000000000000AA } ; + assign MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_2 = + { _0_CONCAT_writeBuffer_ff_rf_sub_writeBuffer_ff__ETC___d5950, + 1'd1, + tagLookup_transNum, + 1'd0, + IF_NOT_writeBuffer_ff_rf_sub_writeBuffer_ff_lt_ETC___d5977 } ; + assign MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_3 = + { { 13'd0, + cache_request_put_val_BITS_140_TO_101_012_MINU_ETC___d6067[39:13] } + + 40'h00FF7DF080, + 1'd1, + tagLookup_transNum, + 95'h055555555555555555555403 } ; + assign MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_4 = + { IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5498, + 1'd1, + tagLookup_transNum, + 1'd0, + IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5701 } ; + assign MUX_tagLookup_tagCache_missedResp$wset_1__VAL_1 = + tagLookup_tagCache_cacheState && + tagLookup_tagCache_respsReady$wget && + (!tagLookup_tagCache_cacheState || + tagLookup_tagCache_resps$wget[224:223] != 2'd1 || + level__h8616 == 2'd2) && + (!tagLookup_tagCache_cacheState || + tagLookup_tagCache_resps$wget[224:223] == 2'd0 || + tagLookup_tagCache_resps$wget[224:223] == 2'd1 || + level__h8616 == 2'd2) ; + always@(tagLookup_tagCache_cts or x1_avValue_snd_fst_key__h121113) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd1: + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_2__VAL_1 = + tagLookup_tagCache_cts[108:101]; + 2'd2: + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_2__VAL_1 = + x1_avValue_snd_fst_key__h121113; + default: MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_2__VAL_1 = + tagLookup_tagCache_cts[108:101]; + endcase + end + assign MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_3__VAL_1 = + { CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q34, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q35, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4643 } ; + assign MUX_tagLookup_tagCache_writeResps_ff_lhead$write_1__VAL_1 = + tagLookup_tagCache_writeResps_ff_lhead + 2'd1 ; + assign MUX_tagLookup_tagCache_writeResps_ff_rf$upd_2__VAL_1 = + { tagLookup_tagCache_resps$wget[232:227], + (tagLookup_tagCache_resps$wget[224:223] == 2'd1) ? + 2'd0 : + { 1'd1, tagLookup_tagCache_resps$wget[221] } } ; + assign MUX_tagLookup_transNum$write_1__VAL_1 = tagLookup_transNum + 5'd1 ; + assign MUX_tagLookup_useNextRsp_ff_lhead$write_1__VAL_1 = + tagLookup_useNextRsp_ff_lhead + 3'd1 ; + assign MUX_tagLookup_useNextRsp_ff_rf$upd_2__VAL_4 = + (tagLookup_state == 3'd2 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 && + !tagLookup_lookupRsp_ff_lhead_read__318_MINUS_t_ETC___d5320) ? + tagLookup_currentDepth != 2'd0 && + IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 : + IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5706 ; + + // inlined wires + assign tagLookup_tagCache_newReq$wget = + { 1'd1, + tagLookup_tagCacheReq_ff_rf[140:94], + CASE_tagLookup_tagCacheReq_ff_rf_BITS_93_TO_92_ETC__q19, + tagLookup_tagCacheReq_ff_rf[91:0] } ; + assign tagLookup_tagCache_retryReqs_removeItem$wget = + { 1'd1, tagLookup_tagCache_resps$wget[14:9] } ; + assign tagLookup_tagCache_resps$wget = + { x__h284313, + x__h284335, + tagLookup_tagCache_cts[1:0], + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d5033, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5036, + tagLookup_tagCache_cts[276:230], + CASE_tagLookup_tagCache_cts_BITS_229_TO_228_0__ETC__q36, + tagLookup_tagCache_cts[227:136], + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5078 } ; + assign tagLookup_tagCache_respsReady$wget = + tagLookup_tagCache_cts[278:277] != 2'd1 && + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5052 ; + assign tagLookup_tagCache_missedResp$wget = + MUX_tagLookup_tagCache_missedResp$wset_1__SEL_1 ? + MUX_tagLookup_tagCache_missedResp$wset_1__VAL_1 : + MUX_tagLookup_tagCache_missedResp$wset_1__VAL_1 ; + assign tagLookup_tagCache_missedResp$whas = + WILL_FIRE_RL_tagLookup_drainMemRsp && level__h8616 != 2'd0 || + WILL_FIRE_RL_tagLookup_tagCache_catchResponse ; + assign tagLookup_tagCache_orderer_slaveReqs_insertItem$wget = + { 1'd1, + tagLookup_tagCacheReq_ff_rf[100:95], + tagLookup_tagCacheReq_ff_rf[100:95], + tagLookup_tagCacheReq_ff_rf[140:104], + tagLookup_tagCacheReq_ff_rf[105:104] + + IF_tagLookup_tagCacheReq_ff_rf_BITS_93_TO_92_E_ETC__q40[1:0], + tagLookup_tagCache_orderer_slaveAddrs_bag[41] && + tagLookup_tagCache_orderer_slaveAddrs_bag[40:6] == + tagLookup_tagCacheReq_ff_rf[140:106], + tagLookup_tagCache_orderer_slaveAddrs_bag[5:0] } ; + assign tagLookup_tagCache_orderer_slaveAddrs_insertItem$wget = + { 1'd1, + tagLookup_tagCacheReq_ff_rf[140:106], + tagLookup_tagCacheReq_ff_rf[100:95] } ; + assign tagLookup_tagCache_orderer_slaveAddrs_removeItem$wget = + { 1'd1, tagLookup_tagCache_orderer_slaveReqs_bag[45:11] } ; + assign tagLookup_tagCache_orderer_slaveDeps_insertItem$wget = + { 1'd1, tagLookup_tagCacheReq_ff_rf[100:95], 6'd63 } ; + assign tagLookup_tagCache_orderer_slaveDeps_updateItem$wget = + { 1'd1, + tagLookup_tagCache_orderer_slaveAddrs_bag[5:0], + tagLookup_tagCacheReq_ff_rf[100:95] } ; + assign tagLookup_tagCache_orderer_slaveDeps_updateItem$whas = + WILL_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_orderer_slaveAddrs_bag[41] && + tagLookup_tagCache_orderer_slaveAddrs_bag[40:6] == + tagLookup_tagCacheReq_ff_rf[140:106] ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem$wget = + { 1'd1, + tagLookup_tagCache_cts[278:277] == 2'd1 || + tagLookup_tagCache_cts[236], + tagLookup_tagCache_orderer_mastReqIds_rf[4:0], + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3769 } ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem$whas = + tagLookup_tagCache_cacheState && + (tagLookup_tagCache_cts[278:277] == 2'd1 || + tagLookup_tagCache_cts[278:277] == 2'd0 && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3516 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 && + x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem$wget = + { 1'd1, tagLookup_mRsps_ff_rf$D_OUT_1[76:71] } ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem$whas = + tagLookup_tagCache_cacheState && + (tagLookup_tagCache_cts[278:277] == 2'd1 && + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3151 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 || + tagLookup_tagCache_cts[278:277] != 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3303) ; + assign tagLookup_tagCache_orderer_mastLines_insertItem$wget = + { 1'd1, + tagLookup_tagCache_cts[278:277] == 2'd1 || + tagLookup_tagCache_cts[236], + tagLookup_tagCache_orderer_mastReqIds_rf[4:0], + (tagLookup_tagCache_cts[278:277] == 2'd1) ? + tagLookup_tagCache_cts[135:101] : + x__h117048[36:2] } ; + assign lookupRsp_insertItem$wget = + { 1'd1, + tagLookup_reqeustId, + tagLookup_reqeustId, + tagLookup_readReqs_ff_dataReg, + tagLookup_lookupRsp_ff_rf } ; + assign lookupRsp_removeItem$wget = + { 1'd1, + (level__h314581 == 6'd0) ? + IF_tagOnlyReads_lhead_read__990_MINUS_tagOnlyR_ETC___d6187 : + mRsps_ff_rf$D_OUT_1[76:71] } ; + assign lookupRsp_removeItem$whas = + EN_cache_response_get && + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6185 ; + assign addrFrame_insertItem$wget = + { 1'd1, + cache_request_put_val[100:95], + cache_request_put_val[6], + cache_request_put_val[105:104], + cache_request_put_val[100:95] } ; + assign tagLookup_getReq$whas = + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5381 ; + assign tagLookup_readReqs_ff_full$port1__read = + !CAN_FIRE_RL_getTagLookupResponse && tagLookup_readReqs_ff_full ; + assign tagLookup_readReqs_ff_full$EN_port1__write = + WILL_FIRE_RL_drainWritebuffer && + writeBuffer_ff_rf$D_OUT_1[93:92] == 2'd0 || + EN_cache_request_put && cache_request_put_val[93:92] == 2'd0 ; + assign tagLookup_readReqs_ff_full$port2__read = + tagLookup_readReqs_ff_full$EN_port1__write ? + 1'd1 : + tagLookup_readReqs_ff_full$port1__read ; + assign tagLookup_tagCache_req_commits_level$port0__write_1 = + tagLookup_tagCache_req_commits_level + 5'd1 ; + assign tagLookup_tagCache_req_commits_level$port1__write_1 = + x_port1__read__h92294 - 5'd1 ; + assign tagLookup_tagCache_req_commits_level$port2__read = + NOT_tagLookup_tagCache_missedResp_whas__080_08_ETC___d5137 ? + tagLookup_tagCache_req_commits_level$port1__write_1 : + x_port1__read__h92294 ; + assign tagLookup_tagCache_req_commits_rf$port0__write_1 = + { tagLookup_tagCache_req_commits_head == 4'd15 || + tagLookup_tagCache_req_commits_rf[15], + tagLookup_tagCache_req_commits_head == 4'd14 || + tagLookup_tagCache_req_commits_rf[14], + tagLookup_tagCache_req_commits_head == 4'd13 || + tagLookup_tagCache_req_commits_rf[13], + tagLookup_tagCache_req_commits_head == 4'd12 || + tagLookup_tagCache_req_commits_rf[12], + tagLookup_tagCache_req_commits_head == 4'd11 || + tagLookup_tagCache_req_commits_rf[11], + tagLookup_tagCache_req_commits_head == 4'd10 || + tagLookup_tagCache_req_commits_rf[10], + tagLookup_tagCache_req_commits_head == 4'd9 || + tagLookup_tagCache_req_commits_rf[9], + tagLookup_tagCache_req_commits_head == 4'd8 || + tagLookup_tagCache_req_commits_rf[8], + tagLookup_tagCache_req_commits_head == 4'd7 || + tagLookup_tagCache_req_commits_rf[7], + tagLookup_tagCache_req_commits_head == 4'd6 || + tagLookup_tagCache_req_commits_rf[6], + tagLookup_tagCache_req_commits_head == 4'd5 || + tagLookup_tagCache_req_commits_rf[5], + tagLookup_tagCache_req_commits_head == 4'd4 || + tagLookup_tagCache_req_commits_rf[4], + tagLookup_tagCache_req_commits_head == 4'd3 || + tagLookup_tagCache_req_commits_rf[3], + tagLookup_tagCache_req_commits_head == 4'd2 || + tagLookup_tagCache_req_commits_rf[2], + tagLookup_tagCache_req_commits_head == 4'd1 || + tagLookup_tagCache_req_commits_rf[1], + tagLookup_tagCache_req_commits_head == 4'd0 || + tagLookup_tagCache_req_commits_rf[0] } ; + assign tagLookup_tagCache_req_commits_rf$port1__read = + (tagLookup_tagCache_req_commits_level != 5'd16) ? + tagLookup_tagCache_req_commits_rf$port0__write_1 : + tagLookup_tagCache_req_commits_rf ; + + // register addrFrame_bag + assign addrFrame_bag$D_IN = + (MUX_tagLookup_readReqs_ff_dataReg$write_1__SEL_2 && + addrFrame_insertItem$wget[15]) ? + { MUX_tagLookup_readReqs_ff_dataReg$write_1__SEL_2, + addrFrame_insertItem$wget[14:0] } : + { (!lookupRsp_removeItem$whas || + !lookupRsp_removeItem$wget[6] || + addrFrame_bag[14] != lookupRsp_removeItem$wget[5] || + addrFrame_bag[13:9] != lookupRsp_removeItem$wget[4:0]) && + addrFrame_bag[15], + addrFrame_bag[14:0] } ; + assign addrFrame_bag$EN = 1'd1 ; + + // register frame + assign frame$D_IN = + (IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6121 && + (level__h314581 == 6'd0 || + mRsps_ff_rf$D_OUT_1[68:67] == 2'd0)) ? + ((IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6179 || + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6180) ? + 3'd0 : + x__h332332) : + 3'd0 ; + assign frame$EN = EN_cache_response_get ; + + // register lookupRsp_bag + assign lookupRsp_bag$D_IN = + { IF_lookupRsp_insertItem_whas__738_AND_lookupRs_ETC___d5763, + (CAN_FIRE_RL_getTagLookupResponse && + lookupRsp_insertItem$wget[17]) ? + lookupRsp_insertItem$wget[16:11] : + lookupRsp_bag[16:11], + (CAN_FIRE_RL_getTagLookupResponse && + lookupRsp_insertItem$wget[17]) ? + lookupRsp_insertItem$wget[10:5] : + lookupRsp_bag[10:5], + (CAN_FIRE_RL_getTagLookupResponse && + lookupRsp_insertItem$wget[17]) ? + lookupRsp_insertItem$wget[4] : + lookupRsp_bag[4], + (CAN_FIRE_RL_getTagLookupResponse && + lookupRsp_insertItem$wget[17]) ? + lookupRsp_insertItem$wget[3:0] : + lookupRsp_bag[3:0] } ; + assign lookupRsp_bag$EN = 1'd1 ; + + // register mReqs_ff_lhead + assign mReqs_ff_lhead$D_IN = + MUX_mReqs_ff_lhead$write_1__SEL_1 ? + MUX_mReqs_ff_lhead$write_1__VAL_1 : + MUX_mReqs_ff_lhead$write_1__VAL_1 ; + assign mReqs_ff_lhead$EN = + EN_cache_request_put && + (cache_request_put_val[93:92] != 2'd0 || + !cache_request_put_val[6]) || + WILL_FIRE_RL_forwardLookupReqs ; + + // register mReqs_ff_ltail + assign mReqs_ff_ltail$D_IN = mReqs_ff_ltail + 2'd1 ; + assign mReqs_ff_ltail$EN = EN_memory_request_get ; + + // register mRsps_ff_lhead + assign mRsps_ff_lhead$D_IN = mRsps_ff_lhead + 6'd1 ; + assign mRsps_ff_lhead$EN = + EN_memory_response_put && !memory_response_put_val[76] ; + + // register mRsps_ff_ltail + assign mRsps_ff_ltail$D_IN = mRsps_ff_ltail + 6'd1 ; + assign mRsps_ff_ltail$EN = + EN_cache_response_get && + (level__h314581 != 6'd0 || + !tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 || + frame != 3'd0) ; + + // register nextId + assign nextId$D_IN = nextId + 5'd1 ; + assign nextId$EN = + EN_cache_request_put && cache_request_put_val[93:92] == 2'd1 ; + + // register tagLookup_currentDepth + assign tagLookup_currentDepth$D_IN = + MUX_tagLookup_currentDepth$write_1__SEL_1 ? + MUX_tagLookup_currentDepth$write_1__VAL_1 : + 2'd1 ; + assign tagLookup_currentDepth$EN = + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5471 || + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 || + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 ; + + // register tagLookup_lookupRsp_ff_lhead + assign tagLookup_lookupRsp_ff_lhead$D_IN = + tagLookup_lookupRsp_ff_lhead + 1'd1 ; + assign tagLookup_lookupRsp_ff_lhead$EN = + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5382 ; + + // register tagLookup_lookupRsp_ff_ltail + assign tagLookup_lookupRsp_ff_ltail$D_IN = + tagLookup_lookupRsp_ff_ltail + 1'd1 ; + assign tagLookup_lookupRsp_ff_ltail$EN = + WILL_FIRE_RL_getTagLookupResponse && + tagLookup_readReqs_ff_dataReg ; + + // register tagLookup_lookupRsp_ff_rf + assign tagLookup_lookupRsp_ff_rf$D_IN = + (tagLookup_currentDepth == 2'd0) ? + { CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42, + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43, + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44, + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 } : + 4'd0 ; + assign tagLookup_lookupRsp_ff_rf$EN = + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5382 ; + + // register tagLookup_mReqs_ff_lhead + assign tagLookup_mReqs_ff_lhead$D_IN = tagLookup_mReqs_ff_lhead + 4'd1 ; + assign tagLookup_mReqs_ff_lhead$EN = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas ; + + // register tagLookup_mReqs_ff_ltail + assign tagLookup_mReqs_ff_ltail$D_IN = tagLookup_mReqs_ff_ltail + 4'd1 ; + assign tagLookup_mReqs_ff_ltail$EN = CAN_FIRE_RL_forwardLookupReqs ; + + // register tagLookup_mRsps_ff_lhead + assign tagLookup_mRsps_ff_lhead$D_IN = tagLookup_mRsps_ff_lhead + 2'd1 ; + assign tagLookup_mRsps_ff_lhead$EN = + EN_memory_response_put && memory_response_put_val[76] ; + + // register tagLookup_mRsps_ff_ltail + assign tagLookup_mRsps_ff_ltail$D_IN = tagLookup_mRsps_ff_ltail + 2'd1 ; + assign tagLookup_mRsps_ff_ltail$EN = + tagLookup_tagCache_cacheState && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3292 ; + + // register tagLookup_oldTags_0 + always@(tagLookup_currentDepth or tagLookup_tagCache_resps$wget) + begin + case (tagLookup_currentDepth) + 2'd0: tagLookup_oldTags_0$D_IN = tagLookup_tagCache_resps$wget[219:156]; + 2'd1: tagLookup_oldTags_0$D_IN = 64'd0; + default: tagLookup_oldTags_0$D_IN = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign tagLookup_oldTags_0$EN = 1'b0 ; + + // register tagLookup_oldTags_1 + always@(tagLookup_currentDepth or tagLookup_tagCache_resps$wget) + begin + case (tagLookup_currentDepth) + 2'd0: tagLookup_oldTags_1$D_IN = tagLookup_tagCache_resps$wget[219:156]; + 2'd1: tagLookup_oldTags_1$D_IN = 64'd0; + default: tagLookup_oldTags_1$D_IN = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign tagLookup_oldTags_1$EN = + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_currentDepth == 2'd1 && + tagLookup_state == 3'd4 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 && + IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 ; + + // register tagLookup_pendingCapEnable + assign tagLookup_pendingCapEnable$D_IN = + MUX_tagLookup_currentDepth$write_1__SEL_2 && + MUX_tagLookup_pendingCapEnable$write_1__VAL_1 ; + assign tagLookup_pendingCapEnable$EN = + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 || + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 ; + + // register tagLookup_pendingCapNumber + assign tagLookup_pendingCapNumber$D_IN = + MUX_tagLookup_currentDepth$write_1__SEL_2 ? + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5942[39:4] : + cache_request_put_val_BITS_140_TO_101_012_MINU_ETC___d6067[39:4] ; + assign tagLookup_pendingCapNumber$EN = + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 || + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 ; + + // register tagLookup_pendingTags + assign tagLookup_pendingTags$D_IN = + MUX_tagLookup_currentDepth$write_1__SEL_2 && + MUX_tagLookup_pendingTags$write_1__VAL_1 ; + assign tagLookup_pendingTags$EN = + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 || + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 ; + + // register tagLookup_readReqs_ff_dataReg + assign tagLookup_readReqs_ff_dataReg$D_IN = + MUX_tagLookup_readReqs_ff_dataReg$write_1__SEL_1 ? + MUX_tagLookup_readReqs_ff_dataReg$write_1__VAL_1 : + MUX_tagLookup_readReqs_ff_dataReg$write_1__VAL_2 ; + assign tagLookup_readReqs_ff_dataReg$EN = + WILL_FIRE_RL_drainWritebuffer && + writeBuffer_ff_rf$D_OUT_1[93:92] == 2'd0 || + EN_cache_request_put && cache_request_put_val[93:92] == 2'd0 ; + + // register tagLookup_readReqs_ff_full + assign tagLookup_readReqs_ff_full$D_IN = + tagLookup_readReqs_ff_full$port2__read ; + assign tagLookup_readReqs_ff_full$EN = 1'b1 ; + + // register tagLookup_reqeustId + assign tagLookup_reqeustId$D_IN = + MUX_tagLookup_reqeustId$write_1__SEL_1 ? + cache_request_put_val[100:95] : + writeBuffer_ff_rf$D_OUT_1[100:95] ; + assign tagLookup_reqeustId$EN = + EN_cache_request_put && cache_request_put_val[93:92] != 2'd1 || + WILL_FIRE_RL_drainWritebuffer ; + + // register tagLookup_state + always@(MUX_tagLookup_state$write_1__SEL_1 or + MUX_tagLookup_currentDepth$write_1__SEL_1 or + MUX_tagLookup_state$write_1__VAL_2 or + MUX_tagLookup_currentDepth$write_1__SEL_2 or + MUX_tagLookup_state$write_1__VAL_3 or + MUX_tagLookup_currentDepth$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_tagLookup_state$write_1__SEL_1: tagLookup_state$D_IN = 3'd1; + MUX_tagLookup_currentDepth$write_1__SEL_1: + tagLookup_state$D_IN = MUX_tagLookup_state$write_1__VAL_2; + MUX_tagLookup_currentDepth$write_1__SEL_2: + tagLookup_state$D_IN = MUX_tagLookup_state$write_1__VAL_3; + MUX_tagLookup_currentDepth$write_1__SEL_3: tagLookup_state$D_IN = 3'd2; + default: tagLookup_state$D_IN = 3'b010 /* unspecified value */ ; + endcase + end + assign tagLookup_state$EN = + WILL_FIRE_RL_tagLookup_initialise && + !tagLookup_zeroAddr_211_ULT_4286574718___d5212 || + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5471 || + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 || + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 ; + + // register tagLookup_tagCacheReq_ff_lhead + always@(MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_1 or + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__VAL_1 or + MUX_tagLookup_currentDepth$write_1__SEL_2 or + MUX_tagLookup_currentDepth$write_1__SEL_3 or + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_4) + begin + case (1'b1) // synopsys parallel_case + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_1: + tagLookup_tagCacheReq_ff_lhead$D_IN = + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__VAL_1; + MUX_tagLookup_currentDepth$write_1__SEL_2: + tagLookup_tagCacheReq_ff_lhead$D_IN = + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__VAL_1; + MUX_tagLookup_currentDepth$write_1__SEL_3: + tagLookup_tagCacheReq_ff_lhead$D_IN = + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__VAL_1; + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_4: + tagLookup_tagCacheReq_ff_lhead$D_IN = + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__VAL_1; + default: tagLookup_tagCacheReq_ff_lhead$D_IN = + 1'b0 /* unspecified value */ ; + endcase + end + assign tagLookup_tagCacheReq_ff_lhead$EN = + WILL_FIRE_RL_tagLookup_initialise && + tagLookup_zeroAddr_211_ULT_4286574718___d5212 || + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 || + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 || + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5471 && + IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5477 ; + + // register tagLookup_tagCacheReq_ff_ltail + assign tagLookup_tagCacheReq_ff_ltail$D_IN = + tagLookup_tagCacheReq_ff_ltail + 1'd1 ; + assign tagLookup_tagCacheReq_ff_ltail$EN = + CAN_FIRE_RL_tagLookup_feedTagCache ; + + // register tagLookup_tagCacheReq_ff_rf + always@(MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_1 or + MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_1 or + MUX_tagLookup_currentDepth$write_1__SEL_2 or + MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_2 or + MUX_tagLookup_currentDepth$write_1__SEL_3 or + MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_3 or + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_4 or + MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_4) + begin + case (1'b1) // synopsys parallel_case + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_1: + tagLookup_tagCacheReq_ff_rf$D_IN = + MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_1; + MUX_tagLookup_currentDepth$write_1__SEL_2: + tagLookup_tagCacheReq_ff_rf$D_IN = + MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_2; + MUX_tagLookup_currentDepth$write_1__SEL_3: + tagLookup_tagCacheReq_ff_rf$D_IN = + MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_3; + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_4: + tagLookup_tagCacheReq_ff_rf$D_IN = + MUX_tagLookup_tagCacheReq_ff_rf$write_1__VAL_4; + default: tagLookup_tagCacheReq_ff_rf$D_IN = + 141'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign tagLookup_tagCacheReq_ff_rf$EN = + WILL_FIRE_RL_tagLookup_initialise && + tagLookup_zeroAddr_211_ULT_4286574718___d5212 || + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 || + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 || + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5471 && + IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5477 ; + + // register tagLookup_tagCache_cacheState + assign tagLookup_tagCache_cacheState$D_IN = 1'd1 ; + assign tagLookup_tagCache_cacheState$EN = + WILL_FIRE_RL_tagLookup_tagCache_initialize && + tagLookup_tagCache_initCount == 8'd255 ; + + // register tagLookup_tagCache_cts + assign tagLookup_tagCache_cts$D_IN = + { tagLookup_tagCache_writebacks$EMPTY_N ? + 2'd1 : + IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3020, + IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3048, + IF_tagLookup_tagCache_writebacks_i_notEmpty__8_ETC___d3055, + tagLookup_tagCache_cts[95:93], + IF_tagLookup_tagCache_writebacks_i_notEmpty__8_ETC___d2893, + newCt_way__h74804, + !tagLookup_tagCache_writebacks$EMPTY_N || + tagLookup_tagCache_writebackWriteBank == 2'd3, + NOT_tagLookup_tagCache_writebacks_i_notEmpty___ETC___d3076, + IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3130 } ; + assign tagLookup_tagCache_cts$EN = tagLookup_tagCache_cacheState ; + + // register tagLookup_tagCache_data_0_readAddr + assign tagLookup_tagCache_data_0_readAddr$D_IN = + IF_tagLookup_tagCache_writebacks_i_notEmpty__8_ETC___d2893 ; + assign tagLookup_tagCache_data_0_readAddr$EN = + tagLookup_tagCache_cacheState ; + + // register tagLookup_tagCache_data_0_writeAddr + assign tagLookup_tagCache_data_0_writeAddr$D_IN = + (way__h98147 == 1'd0 && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3974) ? + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3980 : + tagLookup_tagCache_cts[108:99] ; + assign tagLookup_tagCache_data_0_writeAddr$EN = + tagLookup_tagCache_cacheState && _dfoo9 ; + + // register tagLookup_tagCache_data_0_writeData + assign tagLookup_tagCache_data_0_writeData$D_IN = + (way__h98147 == 1'd0 && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3974) ? + tagLookup_mRsps_ff_rf$D_OUT_1[63:0] : + maskedWrite_data__h117949 ; + assign tagLookup_tagCache_data_0_writeData$EN = + tagLookup_tagCache_cacheState && _dfoo9 ; + + // register tagLookup_tagCache_data_1_readAddr + assign tagLookup_tagCache_data_1_readAddr$D_IN = + IF_tagLookup_tagCache_writebacks_i_notEmpty__8_ETC___d2893 ; + assign tagLookup_tagCache_data_1_readAddr$EN = + tagLookup_tagCache_cacheState ; + + // register tagLookup_tagCache_data_1_writeAddr + assign tagLookup_tagCache_data_1_writeAddr$D_IN = + (way__h98147 == 1'd1 && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3974) ? + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3980 : + tagLookup_tagCache_cts[108:99] ; + assign tagLookup_tagCache_data_1_writeAddr$EN = + tagLookup_tagCache_cacheState && _dfoo1 ; + + // register tagLookup_tagCache_data_1_writeData + assign tagLookup_tagCache_data_1_writeData$D_IN = + (way__h98147 == 1'd1 && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3974) ? + tagLookup_mRsps_ff_rf$D_OUT_1[63:0] : + maskedWrite_data__h117949 ; + assign tagLookup_tagCache_data_1_writeData$EN = + tagLookup_tagCache_cacheState && _dfoo1 ; + + // register tagLookup_tagCache_delayedInvalidates_ff_lhead + assign tagLookup_tagCache_delayedInvalidates_ff_lhead$D_IN = 4'h0 ; + assign tagLookup_tagCache_delayedInvalidates_ff_lhead$EN = 1'b0 ; + + // register tagLookup_tagCache_delayedInvalidates_ff_ltail + assign tagLookup_tagCache_delayedInvalidates_ff_ltail$D_IN = 4'h0 ; + assign tagLookup_tagCache_delayedInvalidates_ff_ltail$EN = 1'b0 ; + + // register tagLookup_tagCache_initCount + assign tagLookup_tagCache_initCount$D_IN = + (tagLookup_tagCache_initCount == 8'd255) ? 8'd0 : x__h72111 ; + assign tagLookup_tagCache_initCount$EN = + CAN_FIRE_RL_tagLookup_tagCache_initialize ; + + // register tagLookup_tagCache_invalidateWritebackWriteBank + assign tagLookup_tagCache_invalidateWritebackWriteBank$D_IN = 2'h0 ; + assign tagLookup_tagCache_invalidateWritebackWriteBank$EN = 1'b0 ; + + // register tagLookup_tagCache_invalidatesDone_ff_lhead + assign tagLookup_tagCache_invalidatesDone_ff_lhead$D_IN = 6'h0 ; + assign tagLookup_tagCache_invalidatesDone_ff_lhead$EN = 1'b0 ; + + // register tagLookup_tagCache_invalidatesDone_ff_ltail + assign tagLookup_tagCache_invalidatesDone_ff_ltail$D_IN = 6'h0 ; + assign tagLookup_tagCache_invalidatesDone_ff_ltail$EN = 1'b0 ; + + // register tagLookup_tagCache_invalidates_ff_lhead + assign tagLookup_tagCache_invalidates_ff_lhead$D_IN = 3'h0 ; + assign tagLookup_tagCache_invalidates_ff_lhead$EN = 1'b0 ; + + // register tagLookup_tagCache_invalidates_ff_ltail + assign tagLookup_tagCache_invalidates_ff_ltail$D_IN = 3'h0 ; + assign tagLookup_tagCache_invalidates_ff_ltail$EN = 1'b0 ; + + // register tagLookup_tagCache_nextEmpty + assign tagLookup_tagCache_nextEmpty$D_IN = + !tagLookup_tagCache_orderer_slaveReqs_bag[58] ; + assign tagLookup_tagCache_nextEmpty$EN = 1'd1 ; + + // register tagLookup_tagCache_nextWay + assign tagLookup_tagCache_nextWay$D_IN = tagLookup_tagCache_nextWay + 1'd1 ; + assign tagLookup_tagCache_nextWay$EN = + tagLookup_tagCache_cacheState && + tagLookup_tagCache_cts[278:277] == 2'd0 && + NOT_SEL_ARR_NOT_tagLookup_tagCache_req_commits_ETC___d4094 ; + + // register tagLookup_tagCache_orderer_lookupState + assign tagLookup_tagCache_orderer_lookupState$D_IN = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + { tagLookup_tagCache_newReqwget_BITS_140_TO_101__q20[4:3] != + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2820, + tagLookup_tagCache_newReq$wget[100:95], + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2829 } : + { IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2857 != + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2865, + tagLookup_tagCache_cts[236:231], + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2873 } ; + assign tagLookup_tagCache_orderer_lookupState$EN = + tagLookup_tagCache_cacheState && + tagLookup_tagCache_newReq_whas__787_AND_tagLoo_ETC___d2799 ; + + // register tagLookup_tagCache_orderer_mastLines_bag + assign tagLookup_tagCache_orderer_mastLines_bag$D_IN = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + { 1'd1, + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 ? + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] : + tagLookup_tagCache_orderer_mastLines_bag[670:630], + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1663, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1687, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1711, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1737, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1763, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1791, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1819, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1849, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1879, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1911, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1943, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1977, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d2011, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d2047, + IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d2078 } : + { IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2083, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2086, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2090, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2093, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2097, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2100, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2104, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2107, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2111, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2114, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2118, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2121, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2125, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2128, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2132, + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2135 } ; + assign tagLookup_tagCache_orderer_mastLines_bag$EN = 1'd1 ; + + // register tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + assign tagLookup_tagCache_orderer_mastLines_nextValidKeyReg$D_IN = + _theResult_____1__h43323 ; + assign tagLookup_tagCache_orderer_mastLines_nextValidKeyReg$EN = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2201 ; + + // register tagLookup_tagCache_orderer_mastReqIds_lhead + assign tagLookup_tagCache_orderer_mastReqIds_lhead$D_IN = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas ? + newHead___1__h49394 : + newHead__h48716 ; + assign tagLookup_tagCache_orderer_mastReqIds_lhead$EN = 1'd1 ; + + // register tagLookup_tagCache_orderer_mastReqIds_rf + assign tagLookup_tagCache_orderer_mastReqIds_rf$D_IN = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas ? + { IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2639, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2643, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2648, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2652, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2657, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2661, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2666, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2670, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2675, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2679, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2684, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2688, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2693, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2697, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2702, + IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2706 } : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + { 5'd0, tagLookup_tagCache_orderer_mastReqIds_rf[79:5] } : + tagLookup_tagCache_orderer_mastReqIds_rf) ; + assign tagLookup_tagCache_orderer_mastReqIds_rf$EN = 1'd1 ; + + // register tagLookup_tagCache_orderer_mastReqs_bag + assign tagLookup_tagCache_orderer_mastReqs_bag$D_IN = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + { 1'd1, + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 ? + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] : + tagLookup_tagCache_orderer_mastReqs_bag[942:885], + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d492, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d516, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d540, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d566, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d592, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d620, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d648, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d678, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d708, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d740, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d772, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d806, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d840, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d876, + IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d907 } : + { IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d912, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d915, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d919, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d922, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d926, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d929, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d933, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d936, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d940, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d943, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d947, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d950, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d954, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d957, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d961, + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d964 } ; + assign tagLookup_tagCache_orderer_mastReqs_bag$EN = 1'd1 ; + + // register tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + assign tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg$D_IN = + _theResult_____1__h31534 ; + assign tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg$EN = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1030 ; + + // register tagLookup_tagCache_orderer_mastRespState + assign tagLookup_tagCache_orderer_mastRespState$D_IN = + { tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0 && + !tagLookup_mRsps_ff_rf$D_OUT_1[66], + tagLookup_tagCache_orderer_mastRespState[12] ? + tagLookup_tagCache_orderer_mastRespState[11:6] : + tagLookup_mRsps_ff_rf$D_OUT_1[76:71], + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3349 } ; + assign tagLookup_tagCache_orderer_mastRespState$EN = + tagLookup_tagCache_cacheState && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3292 ; + + // register tagLookup_tagCache_orderer_slaveAddrs_bag + assign tagLookup_tagCache_orderer_slaveAddrs_bag$D_IN = + { CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_orderer_slaveAddrs_insertItem$wget[41] || + (!NOT_tagLookup_tagCache_missedResp_whas__080_08_ETC___d5111 || + !tagLookup_tagCache_orderer_slaveAddrs_removeItem$wget[35] || + tagLookup_tagCache_orderer_slaveAddrs_bag[40:6] != + tagLookup_tagCache_orderer_slaveAddrs_removeItem$wget[34:0]) && + tagLookup_tagCache_orderer_slaveAddrs_bag[41], + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_orderer_slaveAddrs_insertItem$wget[41]) ? + tagLookup_tagCache_orderer_slaveAddrs_insertItem$wget[40:0] : + tagLookup_tagCache_orderer_slaveAddrs_bag[40:0] } ; + assign tagLookup_tagCache_orderer_slaveAddrs_bag$EN = 1'd1 ; + + // register tagLookup_tagCache_orderer_slaveDeps_bag + assign tagLookup_tagCache_orderer_slaveDeps_bag$D_IN = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_orderer_slaveDeps_insertItem$wget[12]) ? + { CAN_FIRE_RL_tagLookup_feedTagCache, + tagLookup_tagCache_orderer_slaveDeps_insertItem$wget[11:0] } : + NOT_tagLookup_tagCache_orderer_slaveDeps_remov_ETC___d264 ; + assign tagLookup_tagCache_orderer_slaveDeps_bag$EN = 1'd1 ; + + // register tagLookup_tagCache_orderer_slaveReqs_bag + assign tagLookup_tagCache_orderer_slaveReqs_bag$D_IN = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_orderer_slaveReqs_insertItem$wget[58]) ? + { CAN_FIRE_RL_tagLookup_feedTagCache, + tagLookup_tagCache_orderer_slaveReqs_insertItem$wget[57:0] } : + { (!NOT_tagLookup_tagCache_missedResp_whas__080_08_ETC___d5095 || + !tagLookup_tagCache_retryReqs_removeItem$wget[6] || + tagLookup_tagCache_orderer_slaveReqs_bag[57] != + tagLookup_tagCache_retryReqs_removeItem$wget[5] || + tagLookup_tagCache_orderer_slaveReqs_bag[56:52] != + tagLookup_tagCache_retryReqs_removeItem$wget[4:0]) && + tagLookup_tagCache_orderer_slaveReqs_bag[58], + tagLookup_tagCache_orderer_slaveReqs_bag[57:0] } ; + assign tagLookup_tagCache_orderer_slaveReqs_bag$EN = 1'd1 ; + + // register tagLookup_tagCache_orderer_slaveRespState + assign tagLookup_tagCache_orderer_slaveRespState$D_IN = + { tagLookup_tagCache_resps$wget[224:223] == 2'd0 && + !tagLookup_tagCache_resps$wget[222], + tagLookup_tagCache_orderer_slaveRespState[12] ? + tagLookup_tagCache_orderer_slaveRespState[11:6] : + tagLookup_tagCache_resps$wget[14:9], + tagLookup_tagCache_orderer_slaveRespState[12] ? + tagLookup_tagCache_orderer_slaveRespState[5:4] : + tagLookup_tagCache_orderer_slaveReqs_bag[10:9], + tagLookup_tagCache_orderer_slaveRespState[12] ? + tagLookup_tagCache_orderer_slaveRespState[3:2] : + tagLookup_tagCache_orderer_slaveReqs_bag[8:7], + (tagLookup_tagCache_orderer_slaveRespState[12] ? + tagLookup_tagCache_orderer_slaveRespState[1:0] : + tagLookup_tagCache_orderer_slaveReqs_bag[10:9]) + + 2'd1 } ; + assign tagLookup_tagCache_orderer_slaveRespState$EN = + (!tagLookup_tagCache_missedResp$whas || + !tagLookup_tagCache_missedResp$wget) && + tagLookup_tagCache_cacheState && + tagLookup_tagCache_resps$wget[8] ; + + // register tagLookup_tagCache_orderer_waitingSlaveReq_lhead + assign tagLookup_tagCache_orderer_waitingSlaveReq_lhead$D_IN = 2'h0 ; + assign tagLookup_tagCache_orderer_waitingSlaveReq_lhead$EN = 1'b0 ; + + // register tagLookup_tagCache_orderer_waitingSlaveReq_ltail + assign tagLookup_tagCache_orderer_waitingSlaveReq_ltail$D_IN = 2'h0 ; + assign tagLookup_tagCache_orderer_waitingSlaveReq_ltail$EN = 1'b0 ; + + // register tagLookup_tagCache_readReqReg + assign tagLookup_tagCache_readReqReg$D_IN = + { CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q46, + x1_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_d_key__h278782, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4944 } ; + assign tagLookup_tagCache_readReqReg$EN = tagLookup_tagCache_cacheState ; + + // register tagLookup_tagCache_readReqs_bag + assign tagLookup_tagCache_readReqs_bag$D_IN = + tagLookup_tagCache_readReqs_bag ; + assign tagLookup_tagCache_readReqs_bag$EN = 1'd1 ; + + // register tagLookup_tagCache_req_commits_head + assign tagLookup_tagCache_req_commits_head$D_IN = + tagLookup_tagCache_req_commits_head + 4'd1 ; + assign tagLookup_tagCache_req_commits_head$EN = + CAN_FIRE_RL_tagLookup_stuffCommits ; + + // register tagLookup_tagCache_req_commits_level + assign tagLookup_tagCache_req_commits_level$D_IN = + tagLookup_tagCache_req_commits_level$port2__read ; + assign tagLookup_tagCache_req_commits_level$EN = 1'b1 ; + + // register tagLookup_tagCache_req_commits_rf + assign tagLookup_tagCache_req_commits_rf$D_IN = + tagLookup_tagCache_req_commits_rf$port1__read ; + assign tagLookup_tagCache_req_commits_rf$EN = 1'b1 ; + + // register tagLookup_tagCache_req_commits_tail + assign tagLookup_tagCache_req_commits_tail$D_IN = + tagLookup_tagCache_req_commits_tail + 4'd1 ; + assign tagLookup_tagCache_req_commits_tail$EN = + NOT_tagLookup_tagCache_missedResp_whas__080_08_ETC___d5137 ; + + // register tagLookup_tagCache_retryReqs_bag + assign tagLookup_tagCache_retryReqs_bag$D_IN = + { (!NOT_tagLookup_tagCache_missedResp_whas__080_08_ETC___d5095 || + !tagLookup_tagCache_retryReqs_removeItem$wget[6] || + tagLookup_tagCache_retryReqs_bag[146] != + tagLookup_tagCache_retryReqs_removeItem$wget[5] || + tagLookup_tagCache_retryReqs_bag[145:141] != + tagLookup_tagCache_retryReqs_removeItem$wget[4:0]) && + tagLookup_tagCache_retryReqs_bag[147], + tagLookup_tagCache_retryReqs_bag[146:94], + (tagLookup_tagCache_retryReqs_bag[93:92] == 2'd0) ? + { 85'h02AAAAAAAAAAAAAAAAAAAA, + tagLookup_tagCache_retryReqs_bag[8:0] } : + ((tagLookup_tagCache_retryReqs_bag[93:92] == 2'd1) ? + { 2'd1, tagLookup_tagCache_retryReqs_bag[91:0] } : + { 86'h2AAAAAAAAAAAAAAAAAAAAA, + tagLookup_tagCache_retryReqs_bag[7:0] }) } ; + assign tagLookup_tagCache_retryReqs_bag$EN = 1'd1 ; + + // register tagLookup_tagCache_tags_0_readAddr + assign tagLookup_tagCache_tags_0_readAddr$D_IN = + tagLookup_tagCache_tags_0_bramA_bram$ADDRA ; + assign tagLookup_tagCache_tags_0_readAddr$EN = + tagLookup_tagCache_cacheState ; + + // register tagLookup_tagCache_tags_0_readAddrB + assign tagLookup_tagCache_tags_0_readAddrB$D_IN = 8'h0 ; + assign tagLookup_tagCache_tags_0_readAddrB$EN = 1'b0 ; + + // register tagLookup_tagCache_tags_0_writeAddr + assign tagLookup_tagCache_tags_0_writeAddr$D_IN = + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_1__SEL_1 ? + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_2__VAL_1 : + tagLookup_tagCache_initCount ; + assign tagLookup_tagCache_tags_0_writeAddr$EN = + tagLookup_tagCache_cacheState && x__h121243 == 1'd0 && + NOT_tagLookup_tagCache_cts_read__795_BITS_278__ETC___d4253 || + WILL_FIRE_RL_tagLookup_tagCache_initialize ; + + // register tagLookup_tagCache_tags_0_writeData + assign tagLookup_tagCache_tags_0_writeData$D_IN = + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_1__SEL_1 ? + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_3__VAL_1 : + 41'd0 ; + assign tagLookup_tagCache_tags_0_writeData$EN = + tagLookup_tagCache_cacheState && x__h121243 == 1'd0 && + NOT_tagLookup_tagCache_cts_read__795_BITS_278__ETC___d4253 || + WILL_FIRE_RL_tagLookup_tagCache_initialize ; + + // register tagLookup_tagCache_tags_1_readAddr + assign tagLookup_tagCache_tags_1_readAddr$D_IN = + tagLookup_tagCache_tags_0_bramA_bram$ADDRA ; + assign tagLookup_tagCache_tags_1_readAddr$EN = + tagLookup_tagCache_cacheState ; + + // register tagLookup_tagCache_tags_1_readAddrB + assign tagLookup_tagCache_tags_1_readAddrB$D_IN = 8'h0 ; + assign tagLookup_tagCache_tags_1_readAddrB$EN = 1'b0 ; + + // register tagLookup_tagCache_tags_1_writeAddr + assign tagLookup_tagCache_tags_1_writeAddr$D_IN = + MUX_tagLookup_tagCache_tags_1_bramA_bram$b_put_1__SEL_1 ? + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_2__VAL_1 : + tagLookup_tagCache_initCount ; + assign tagLookup_tagCache_tags_1_writeAddr$EN = + tagLookup_tagCache_cacheState && x__h121243 == 1'd1 && + NOT_tagLookup_tagCache_cts_read__795_BITS_278__ETC___d4253 || + WILL_FIRE_RL_tagLookup_tagCache_initialize ; + + // register tagLookup_tagCache_tags_1_writeData + assign tagLookup_tagCache_tags_1_writeData$D_IN = + MUX_tagLookup_tagCache_tags_1_bramA_bram$b_put_1__SEL_1 ? + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_3__VAL_1 : + 41'd0 ; + assign tagLookup_tagCache_tags_1_writeData$EN = + tagLookup_tagCache_cacheState && x__h121243 == 1'd1 && + NOT_tagLookup_tagCache_cts_read__795_BITS_278__ETC___d4253 || + WILL_FIRE_RL_tagLookup_tagCache_initialize ; + + // register tagLookup_tagCache_writeResps_ff_lhead + assign tagLookup_tagCache_writeResps_ff_lhead$D_IN = + MUX_tagLookup_tagCache_writeResps_ff_lhead$write_1__SEL_1 ? + MUX_tagLookup_tagCache_writeResps_ff_lhead$write_1__VAL_1 : + MUX_tagLookup_tagCache_writeResps_ff_lhead$write_1__VAL_1 ; + assign tagLookup_tagCache_writeResps_ff_lhead$EN = + WILL_FIRE_RL_tagLookup_tagCache_catchResponse && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5155 || + WILL_FIRE_RL_tagLookup_drainMemRsp && level__h8616 != 2'd0 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5155 ; + + // register tagLookup_tagCache_writeResps_ff_ltail + assign tagLookup_tagCache_writeResps_ff_ltail$D_IN = + tagLookup_tagCache_writeResps_ff_ltail + 2'd1 ; + assign tagLookup_tagCache_writeResps_ff_ltail$EN = + MUX_tagLookup_tagCache_missedResp$wset_1__SEL_1 ; + + // register tagLookup_tagCache_writebackWriteBank + assign tagLookup_tagCache_writebackWriteBank$D_IN = + (tagLookup_tagCache_writebackWriteBank == 2'd3) ? + 2'd0 : + tagLookup_tagCache_writebackWriteBank + 2'd1 ; + assign tagLookup_tagCache_writebackWriteBank$EN = + tagLookup_tagCache_cacheState && + tagLookup_tagCache_writebacks$EMPTY_N ; + + // register tagLookup_tagCache_writethroughNext_ff_lhead + assign tagLookup_tagCache_writethroughNext_ff_lhead$D_IN = 2'h0 ; + assign tagLookup_tagCache_writethroughNext_ff_lhead$EN = 1'b0 ; + + // register tagLookup_tagCache_writethroughNext_ff_ltail + assign tagLookup_tagCache_writethroughNext_ff_ltail$D_IN = 2'h0 ; + assign tagLookup_tagCache_writethroughNext_ff_ltail$EN = 1'b0 ; + + // register tagLookup_transNum + always@(MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_1 or + MUX_tagLookup_transNum$write_1__VAL_1 or + MUX_tagLookup_currentDepth$write_1__SEL_2 or + MUX_tagLookup_currentDepth$write_1__SEL_3 or + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_4) + begin + case (1'b1) // synopsys parallel_case + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_1: + tagLookup_transNum$D_IN = MUX_tagLookup_transNum$write_1__VAL_1; + MUX_tagLookup_currentDepth$write_1__SEL_2: + tagLookup_transNum$D_IN = MUX_tagLookup_transNum$write_1__VAL_1; + MUX_tagLookup_currentDepth$write_1__SEL_3: + tagLookup_transNum$D_IN = MUX_tagLookup_transNum$write_1__VAL_1; + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_4: + tagLookup_transNum$D_IN = MUX_tagLookup_transNum$write_1__VAL_1; + default: tagLookup_transNum$D_IN = 5'b01010 /* unspecified value */ ; + endcase + end + assign tagLookup_transNum$EN = + WILL_FIRE_RL_tagLookup_initialise && + tagLookup_zeroAddr_211_ULT_4286574718___d5212 || + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 || + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 || + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5471 && + IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5477 ; + + // register tagLookup_useNextRsp_ff_lhead + always@(MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_1 or + MUX_tagLookup_useNextRsp_ff_lhead$write_1__VAL_1 or + MUX_tagLookup_currentDepth$write_1__SEL_2 or + MUX_tagLookup_currentDepth$write_1__SEL_3 or + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_4) + begin + case (1'b1) // synopsys parallel_case + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_1: + tagLookup_useNextRsp_ff_lhead$D_IN = + MUX_tagLookup_useNextRsp_ff_lhead$write_1__VAL_1; + MUX_tagLookup_currentDepth$write_1__SEL_2: + tagLookup_useNextRsp_ff_lhead$D_IN = + MUX_tagLookup_useNextRsp_ff_lhead$write_1__VAL_1; + MUX_tagLookup_currentDepth$write_1__SEL_3: + tagLookup_useNextRsp_ff_lhead$D_IN = + MUX_tagLookup_useNextRsp_ff_lhead$write_1__VAL_1; + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_4: + tagLookup_useNextRsp_ff_lhead$D_IN = + MUX_tagLookup_useNextRsp_ff_lhead$write_1__VAL_1; + default: tagLookup_useNextRsp_ff_lhead$D_IN = + 3'b010 /* unspecified value */ ; + endcase + end + assign tagLookup_useNextRsp_ff_lhead$EN = + WILL_FIRE_RL_tagLookup_initialise && + tagLookup_zeroAddr_211_ULT_4286574718___d5212 || + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 || + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 || + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5471 && + IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5477 ; + + // register tagLookup_useNextRsp_ff_ltail + assign tagLookup_useNextRsp_ff_ltail$D_IN = + tagLookup_useNextRsp_ff_ltail + 3'd1 ; + assign tagLookup_useNextRsp_ff_ltail$EN = + CAN_FIRE_RL_tagLookup_drainMemRsp ; + + // register tagLookup_zeroAddr + assign tagLookup_zeroAddr$D_IN = + { x_lineNumber__h292967, tagLookup_zeroAddr[2:0] } ; + assign tagLookup_zeroAddr$EN = + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_1 ; + + // register tagOnlyReads_lhead + assign tagOnlyReads_lhead$D_IN = tagOnlyReads_lhead + 1'd1 ; + assign tagOnlyReads_lhead$EN = + EN_cache_request_put && cache_request_put_val[93:92] == 2'd0 && + cache_request_put_val[6] ; + + // register tagOnlyReads_ltail + assign tagOnlyReads_ltail$D_IN = tagOnlyReads_ltail + 1'd1 ; + assign tagOnlyReads_ltail$EN = + EN_cache_response_get && + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6121 && + (level__h314581 == 6'd0 || mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) && + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6180 ; + + // register tagOnlyReads_rf + assign tagOnlyReads_rf$D_IN = cache_request_put_val[100:95] ; + assign tagOnlyReads_rf$EN = + EN_cache_request_put && cache_request_put_val[93:92] == 2'd0 && + cache_request_put_val[6] ; + + // register writeBuffer_ff_lhead + assign writeBuffer_ff_lhead$D_IN = writeBuffer_ff_lhead + 5'd1 ; + assign writeBuffer_ff_lhead$EN = + EN_cache_request_put && cache_request_put_val[93:92] == 2'd1 ; + + // register writeBuffer_ff_ltail + assign writeBuffer_ff_ltail$D_IN = writeBuffer_ff_ltail + 5'd1 ; + assign writeBuffer_ff_ltail$EN = WILL_FIRE_RL_drainWritebuffer ; + + // submodule mReqs_ff_rf + assign mReqs_ff_rf$ADDR_1 = mReqs_ff_ltail[0] ; + assign mReqs_ff_rf$ADDR_2 = 1'b0 ; + assign mReqs_ff_rf$ADDR_3 = 1'b0 ; + assign mReqs_ff_rf$ADDR_4 = 1'b0 ; + assign mReqs_ff_rf$ADDR_5 = 1'b0 ; + assign mReqs_ff_rf$ADDR_IN = mReqs_ff_lhead[0] ; + assign mReqs_ff_rf$D_IN = + MUX_mReqs_ff_lhead$write_1__SEL_1 ? + MUX_mReqs_ff_rf$upd_2__VAL_1 : + MUX_mReqs_ff_rf$upd_2__VAL_2 ; + assign mReqs_ff_rf$WE = + EN_cache_request_put && + (cache_request_put_val[93:92] != 2'd0 || + !cache_request_put_val[6]) || + WILL_FIRE_RL_forwardLookupReqs ; + + // submodule mRsps_ff_rf + assign mRsps_ff_rf$ADDR_1 = mRsps_ff_ltail[4:0] ; + assign mRsps_ff_rf$ADDR_2 = 5'h0 ; + assign mRsps_ff_rf$ADDR_3 = 5'h0 ; + assign mRsps_ff_rf$ADDR_4 = 5'h0 ; + assign mRsps_ff_rf$ADDR_5 = 5'h0 ; + assign mRsps_ff_rf$ADDR_IN = mRsps_ff_lhead[4:0] ; + assign mRsps_ff_rf$D_IN = + { memory_response_put_val[76:69], + CASE_memory_response_put_val_BITS_68_TO_67_0_m_ETC__q41, + memory_response_put_val[64:0] } ; + assign mRsps_ff_rf$WE = + EN_memory_response_put && !memory_response_put_val[76] ; + + // submodule tagLookup_mReqs_ff_rf + assign tagLookup_mReqs_ff_rf$ADDR_1 = tagLookup_mReqs_ff_ltail[2:0] ; + assign tagLookup_mReqs_ff_rf$ADDR_2 = 3'h0 ; + assign tagLookup_mReqs_ff_rf$ADDR_3 = 3'h0 ; + assign tagLookup_mReqs_ff_rf$ADDR_4 = 3'h0 ; + assign tagLookup_mReqs_ff_rf$ADDR_5 = 3'h0 ; + assign tagLookup_mReqs_ff_rf$ADDR_IN = tagLookup_mReqs_ff_lhead[2:0] ; + assign tagLookup_mReqs_ff_rf$D_IN = + { (tagLookup_tagCache_cts[278:277] == 2'd1) ? + tagLookup_tagCache_cts[135:96] : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3689, + tagLookup_tagCache_cts[278:277] == 2'd1 || + tagLookup_tagCache_cts[236], + tagLookup_tagCache_orderer_mastReqIds_rf[4:0], + tagLookup_tagCache_cts[230], + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d3753 } ; + assign tagLookup_mReqs_ff_rf$WE = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas ; + + // submodule tagLookup_mRsps_ff_rf + assign tagLookup_mRsps_ff_rf$ADDR_1 = tagLookup_mRsps_ff_ltail[0] ; + assign tagLookup_mRsps_ff_rf$ADDR_2 = 1'b0 ; + assign tagLookup_mRsps_ff_rf$ADDR_3 = 1'b0 ; + assign tagLookup_mRsps_ff_rf$ADDR_4 = 1'b0 ; + assign tagLookup_mRsps_ff_rf$ADDR_5 = 1'b0 ; + assign tagLookup_mRsps_ff_rf$ADDR_IN = tagLookup_mRsps_ff_lhead[0] ; + assign tagLookup_mRsps_ff_rf$D_IN = + { memory_response_put_val[76:69], + CASE_memory_response_put_val_BITS_68_TO_67_0_m_ETC__q41, + memory_response_put_val[64:0] } ; + assign tagLookup_mRsps_ff_rf$WE = + EN_memory_response_put && memory_response_put_val[76] ; + + // submodule tagLookup_tagCache_data_0_bram_bram + assign tagLookup_tagCache_data_0_bram_bram$ADDRA = + IF_tagLookup_tagCache_writebacks_i_notEmpty__8_ETC___d2893 ; + assign tagLookup_tagCache_data_0_bram_bram$ADDRB = + (way__h98147 == 1'd0 && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3974) ? + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3980 : + tagLookup_tagCache_cts[108:99] ; + assign tagLookup_tagCache_data_0_bram_bram$DIA = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + assign tagLookup_tagCache_data_0_bram_bram$DIB = + (way__h98147 == 1'd0 && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3974) ? + tagLookup_mRsps_ff_rf$D_OUT_1[63:0] : + maskedWrite_data__h117949 ; + assign tagLookup_tagCache_data_0_bram_bram$WEA = 1'd0 ; + assign tagLookup_tagCache_data_0_bram_bram$WEB = 1'd1 ; + assign tagLookup_tagCache_data_0_bram_bram$ENA = + tagLookup_tagCache_cacheState ; + assign tagLookup_tagCache_data_0_bram_bram$ENB = + tagLookup_tagCache_cacheState && _dfoo9 ; + + // submodule tagLookup_tagCache_data_1_bram_bram + assign tagLookup_tagCache_data_1_bram_bram$ADDRA = + IF_tagLookup_tagCache_writebacks_i_notEmpty__8_ETC___d2893 ; + assign tagLookup_tagCache_data_1_bram_bram$ADDRB = + (way__h98147 == 1'd1 && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3974) ? + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3980 : + tagLookup_tagCache_cts[108:99] ; + assign tagLookup_tagCache_data_1_bram_bram$DIA = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + assign tagLookup_tagCache_data_1_bram_bram$DIB = + (way__h98147 == 1'd1 && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3974) ? + tagLookup_mRsps_ff_rf$D_OUT_1[63:0] : + maskedWrite_data__h117949 ; + assign tagLookup_tagCache_data_1_bram_bram$WEA = 1'd0 ; + assign tagLookup_tagCache_data_1_bram_bram$WEB = 1'd1 ; + assign tagLookup_tagCache_data_1_bram_bram$ENA = + tagLookup_tagCache_cacheState ; + assign tagLookup_tagCache_data_1_bram_bram$ENB = + tagLookup_tagCache_cacheState && _dfoo1 ; + + // submodule tagLookup_tagCache_delayedInvalidates_ff_rf + assign tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_1 = 3'h0 ; + assign tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_2 = 3'h0 ; + assign tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_3 = 3'h0 ; + assign tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_4 = 3'h0 ; + assign tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_5 = 3'h0 ; + assign tagLookup_tagCache_delayedInvalidates_ff_rf$ADDR_IN = 3'h0 ; + assign tagLookup_tagCache_delayedInvalidates_ff_rf$D_IN = 37'h0 ; + assign tagLookup_tagCache_delayedInvalidates_ff_rf$WE = 1'b0 ; + + // submodule tagLookup_tagCache_invalidateWritebacks + assign tagLookup_tagCache_invalidateWritebacks$D_IN = 89'h0 ; + assign tagLookup_tagCache_invalidateWritebacks$ENQ = 1'b0 ; + assign tagLookup_tagCache_invalidateWritebacks$DEQ = 1'b0 ; + assign tagLookup_tagCache_invalidateWritebacks$CLR = 1'b0 ; + + // submodule tagLookup_tagCache_invalidatesDone_ff_rf + assign tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_1 = 5'h0 ; + assign tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_2 = 5'h0 ; + assign tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_3 = 5'h0 ; + assign tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_4 = 5'h0 ; + assign tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_5 = 5'h0 ; + assign tagLookup_tagCache_invalidatesDone_ff_rf$ADDR_IN = 5'h0 ; + assign tagLookup_tagCache_invalidatesDone_ff_rf$D_IN = 1'b0 ; + assign tagLookup_tagCache_invalidatesDone_ff_rf$WE = 1'b0 ; + + // submodule tagLookup_tagCache_invalidates_ff_rf + assign tagLookup_tagCache_invalidates_ff_rf$ADDR_1 = 2'h0 ; + assign tagLookup_tagCache_invalidates_ff_rf$ADDR_2 = 2'h0 ; + assign tagLookup_tagCache_invalidates_ff_rf$ADDR_3 = 2'h0 ; + assign tagLookup_tagCache_invalidates_ff_rf$ADDR_4 = 2'h0 ; + assign tagLookup_tagCache_invalidates_ff_rf$ADDR_5 = 2'h0 ; + assign tagLookup_tagCache_invalidates_ff_rf$ADDR_IN = 2'h0 ; + assign tagLookup_tagCache_invalidates_ff_rf$D_IN = 40'h0 ; + assign tagLookup_tagCache_invalidates_ff_rf$WE = 1'b0 ; + + // submodule tagLookup_tagCache_orderer_waitingSlaveReq_rf + assign tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_1 = 1'b0 ; + assign tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_2 = 1'b0 ; + assign tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_3 = 1'b0 ; + assign tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_4 = 1'b0 ; + assign tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_5 = 1'b0 ; + assign tagLookup_tagCache_orderer_waitingSlaveReq_rf$ADDR_IN = 1'b0 ; + assign tagLookup_tagCache_orderer_waitingSlaveReq_rf$D_IN = 6'h0 ; + assign tagLookup_tagCache_orderer_waitingSlaveReq_rf$WE = 1'b0 ; + + // submodule tagLookup_tagCache_tags_0_bramA_bram + assign tagLookup_tagCache_tags_0_bramA_bram$ADDRA = + tagLookup_tagCache_writebacks$EMPTY_N ? + tagLookup_tagCache_writebacks$D_OUT[61:54] : + x1_avValue_snd_addr_key__h74942 ; + assign tagLookup_tagCache_tags_0_bramA_bram$ADDRB = + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_1__SEL_1 ? + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_2__VAL_1 : + tagLookup_tagCache_initCount ; + assign tagLookup_tagCache_tags_0_bramA_bram$DIA = + 41'h0AAAAAAAAAA /* unspecified value */ ; + assign tagLookup_tagCache_tags_0_bramA_bram$DIB = + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_1__SEL_1 ? + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_3__VAL_1 : + 41'd0 ; + assign tagLookup_tagCache_tags_0_bramA_bram$WEA = 1'd0 ; + assign tagLookup_tagCache_tags_0_bramA_bram$WEB = 1'd1 ; + assign tagLookup_tagCache_tags_0_bramA_bram$ENA = + tagLookup_tagCache_cacheState ; + assign tagLookup_tagCache_tags_0_bramA_bram$ENB = + tagLookup_tagCache_cacheState && x__h121243 == 1'd0 && + NOT_tagLookup_tagCache_cts_read__795_BITS_278__ETC___d4253 || + WILL_FIRE_RL_tagLookup_tagCache_initialize ; + + // submodule tagLookup_tagCache_tags_0_bramB_bram + assign tagLookup_tagCache_tags_0_bramB_bram$ADDRA = 8'h0 ; + assign tagLookup_tagCache_tags_0_bramB_bram$ADDRB = + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_1__SEL_1 ? + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_2__VAL_1 : + tagLookup_tagCache_initCount ; + assign tagLookup_tagCache_tags_0_bramB_bram$DIA = 41'h0 ; + assign tagLookup_tagCache_tags_0_bramB_bram$DIB = + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_1__SEL_1 ? + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_3__VAL_1 : + 41'd0 ; + assign tagLookup_tagCache_tags_0_bramB_bram$WEA = 1'b0 ; + assign tagLookup_tagCache_tags_0_bramB_bram$WEB = 1'd1 ; + assign tagLookup_tagCache_tags_0_bramB_bram$ENA = 1'b0 ; + assign tagLookup_tagCache_tags_0_bramB_bram$ENB = + tagLookup_tagCache_cacheState && x__h121243 == 1'd0 && + NOT_tagLookup_tagCache_cts_read__795_BITS_278__ETC___d4253 || + WILL_FIRE_RL_tagLookup_tagCache_initialize ; + + // submodule tagLookup_tagCache_tags_1_bramA_bram + assign tagLookup_tagCache_tags_1_bramA_bram$ADDRA = + tagLookup_tagCache_tags_0_bramA_bram$ADDRA ; + assign tagLookup_tagCache_tags_1_bramA_bram$ADDRB = + MUX_tagLookup_tagCache_tags_1_bramA_bram$b_put_1__SEL_1 ? + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_2__VAL_1 : + tagLookup_tagCache_initCount ; + assign tagLookup_tagCache_tags_1_bramA_bram$DIA = + 41'h0AAAAAAAAAA /* unspecified value */ ; + assign tagLookup_tagCache_tags_1_bramA_bram$DIB = + MUX_tagLookup_tagCache_tags_1_bramA_bram$b_put_1__SEL_1 ? + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_3__VAL_1 : + 41'd0 ; + assign tagLookup_tagCache_tags_1_bramA_bram$WEA = 1'd0 ; + assign tagLookup_tagCache_tags_1_bramA_bram$WEB = 1'd1 ; + assign tagLookup_tagCache_tags_1_bramA_bram$ENA = + tagLookup_tagCache_cacheState ; + assign tagLookup_tagCache_tags_1_bramA_bram$ENB = + tagLookup_tagCache_cacheState && x__h121243 == 1'd1 && + NOT_tagLookup_tagCache_cts_read__795_BITS_278__ETC___d4253 || + WILL_FIRE_RL_tagLookup_tagCache_initialize ; + + // submodule tagLookup_tagCache_tags_1_bramB_bram + assign tagLookup_tagCache_tags_1_bramB_bram$ADDRA = 8'h0 ; + assign tagLookup_tagCache_tags_1_bramB_bram$ADDRB = + MUX_tagLookup_tagCache_tags_1_bramA_bram$b_put_1__SEL_1 ? + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_2__VAL_1 : + tagLookup_tagCache_initCount ; + assign tagLookup_tagCache_tags_1_bramB_bram$DIA = 41'h0 ; + assign tagLookup_tagCache_tags_1_bramB_bram$DIB = + MUX_tagLookup_tagCache_tags_1_bramA_bram$b_put_1__SEL_1 ? + MUX_tagLookup_tagCache_tags_0_bramA_bram$b_put_3__VAL_1 : + 41'd0 ; + assign tagLookup_tagCache_tags_1_bramB_bram$WEA = 1'b0 ; + assign tagLookup_tagCache_tags_1_bramB_bram$WEB = 1'd1 ; + assign tagLookup_tagCache_tags_1_bramB_bram$ENA = 1'b0 ; + assign tagLookup_tagCache_tags_1_bramB_bram$ENB = + tagLookup_tagCache_cacheState && x__h121243 == 1'd1 && + NOT_tagLookup_tagCache_cts_read__795_BITS_278__ETC___d4253 || + WILL_FIRE_RL_tagLookup_tagCache_initialize ; + + // submodule tagLookup_tagCache_writeResps_ff_rf + assign tagLookup_tagCache_writeResps_ff_rf$ADDR_1 = 1'b0 ; + assign tagLookup_tagCache_writeResps_ff_rf$ADDR_2 = 1'b0 ; + assign tagLookup_tagCache_writeResps_ff_rf$ADDR_3 = 1'b0 ; + assign tagLookup_tagCache_writeResps_ff_rf$ADDR_4 = 1'b0 ; + assign tagLookup_tagCache_writeResps_ff_rf$ADDR_5 = 1'b0 ; + assign tagLookup_tagCache_writeResps_ff_rf$ADDR_IN = + tagLookup_tagCache_writeResps_ff_lhead[0] ; + assign tagLookup_tagCache_writeResps_ff_rf$D_IN = + MUX_tagLookup_tagCache_writeResps_ff_lhead$write_1__SEL_1 ? + MUX_tagLookup_tagCache_writeResps_ff_rf$upd_2__VAL_1 : + MUX_tagLookup_tagCache_writeResps_ff_rf$upd_2__VAL_1 ; + assign tagLookup_tagCache_writeResps_ff_rf$WE = + WILL_FIRE_RL_tagLookup_tagCache_catchResponse && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5155 || + WILL_FIRE_RL_tagLookup_drainMemRsp && level__h8616 != 2'd0 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5155 ; + + // submodule tagLookup_tagCache_writebacks + assign tagLookup_tagCache_writebacks$D_IN = + { x_addr_tag__h102720, + tagLookup_tagCache_cts[108:99], + 3'd0, + x_addr_tag__h102720, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4047, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080, + _theResult_____21__h86422, + 1'd1, + tagLookup_tagCache_cts[236:231] } ; + assign tagLookup_tagCache_writebacks$ENQ = + tagLookup_tagCache_cacheState && + tagLookup_tagCache_cts[278:277] == 2'd0 && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3516 && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4017 ; + assign tagLookup_tagCache_writebacks$DEQ = + tagLookup_tagCache_cacheState && + tagLookup_tagCache_writebacks$EMPTY_N && + tagLookup_tagCache_writebackWriteBank == 2'd3 ; + assign tagLookup_tagCache_writebacks$CLR = 1'b0 ; + + // submodule tagLookup_useNextRsp_ff_rf + assign tagLookup_useNextRsp_ff_rf$ADDR_1 = + tagLookup_useNextRsp_ff_ltail[1:0] ; + assign tagLookup_useNextRsp_ff_rf$ADDR_2 = 2'h0 ; + assign tagLookup_useNextRsp_ff_rf$ADDR_3 = 2'h0 ; + assign tagLookup_useNextRsp_ff_rf$ADDR_4 = 2'h0 ; + assign tagLookup_useNextRsp_ff_rf$ADDR_5 = 2'h0 ; + assign tagLookup_useNextRsp_ff_rf$ADDR_IN = + tagLookup_useNextRsp_ff_lhead[1:0] ; + always@(MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_4 or + MUX_tagLookup_useNextRsp_ff_rf$upd_2__VAL_4 or + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_1 or + MUX_tagLookup_currentDepth$write_1__SEL_2 or + MUX_tagLookup_currentDepth$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_4: + tagLookup_useNextRsp_ff_rf$D_IN = + MUX_tagLookup_useNextRsp_ff_rf$upd_2__VAL_4; + MUX_tagLookup_tagCacheReq_ff_lhead$write_1__SEL_1: + tagLookup_useNextRsp_ff_rf$D_IN = 1'd0; + MUX_tagLookup_currentDepth$write_1__SEL_2 || + MUX_tagLookup_currentDepth$write_1__SEL_3: + tagLookup_useNextRsp_ff_rf$D_IN = 1'd1; + default: tagLookup_useNextRsp_ff_rf$D_IN = + 1'b0 /* unspecified value */ ; + endcase + end + assign tagLookup_useNextRsp_ff_rf$WE = + WILL_FIRE_RL_tagLookup_initialise && + tagLookup_zeroAddr_211_ULT_4286574718___d5212 || + WILL_FIRE_RL_drainWritebuffer && + IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 || + EN_cache_request_put && + cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 || + WILL_FIRE_RL_tagLookup_doLookup && + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5471 && + IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5477 ; + + // submodule writeBuffer_ff_rf + assign writeBuffer_ff_rf$ADDR_1 = writeBuffer_ff_ltail[3:0] ; + assign writeBuffer_ff_rf$ADDR_2 = 4'h0 ; + assign writeBuffer_ff_rf$ADDR_3 = 4'h0 ; + assign writeBuffer_ff_rf$ADDR_4 = 4'h0 ; + assign writeBuffer_ff_rf$ADDR_5 = 4'h0 ; + assign writeBuffer_ff_rf$ADDR_IN = writeBuffer_ff_lhead[3:0] ; + assign writeBuffer_ff_rf$D_IN = + { cache_request_put_val[140:100], + nextId, + cache_request_put_val[94], + IF_cache_request_put_val_BITS_93_TO_92_997_EQ__ETC___d6049 } ; + assign writeBuffer_ff_rf$WE = + EN_cache_request_put && cache_request_put_val[93:92] == 2'd1 ; + + // remaining internal signals + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2227 = + ({ 28'd0, idx__h43465 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2233 = + ({ 28'd0, idx__h43581 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2239 = + ({ 28'd0, idx__h43697 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2245 = + ({ 28'd0, idx__h43813 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2251 = + ({ 28'd0, idx__h43929 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2257 = + ({ 28'd0, idx__h44045 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2263 = + ({ 28'd0, idx__h44161 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2269 = + ({ 28'd0, idx__h44277 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2275 = + ({ 28'd0, idx__h44393 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2281 = + ({ 28'd0, idx__h44509 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2287 = + ({ 28'd0, idx__h44625 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2293 = + ({ 28'd0, idx__h44741 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2299 = + ({ 28'd0, idx__h44857 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2305 = + ({ 28'd0, idx__h44973 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2311 = + ({ 28'd0, idx__h45089 } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1056 = + ({ 28'd0, idx__h31676 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1062 = + ({ 28'd0, idx__h31792 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1068 = + ({ 28'd0, idx__h31908 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1074 = + ({ 28'd0, idx__h32024 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1080 = + ({ 28'd0, idx__h32140 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1086 = + ({ 28'd0, idx__h32256 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1092 = + ({ 28'd0, idx__h32372 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1098 = + ({ 28'd0, idx__h32488 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1104 = + ({ 28'd0, idx__h32604 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1110 = + ({ 28'd0, idx__h32720 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1116 = + ({ 28'd0, idx__h32836 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1122 = + ({ 28'd0, idx__h32952 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1128 = + ({ 28'd0, idx__h33068 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1134 = + ({ 28'd0, idx__h33184 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 ; + assign IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1140 = + ({ 28'd0, idx__h33300 } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 ; + assign IF_CAN_FIRE_RL_tagLookup_feedTagCache_AND_tagL_ETC__q39 = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[93:92] == 2'd0) ? + tagLookup_tagCache_newReq$wget[5:3] : + 3'd0 ; + assign IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4849 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] == 2'd0 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 == + tagLookup_mRsps_ff_rf$D_OUT_1[66] && + !tagLookup_tagCache_readReqReg[14] : + !tagLookup_tagCache_readReqReg[14]) ? + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4354 : + tagLookup_tagCache_readReqReg[15]) : + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4356 : + tagLookup_tagCache_readReqReg[14]) ; + assign IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4851 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] == 2'd0 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 == + tagLookup_mRsps_ff_rf$D_OUT_1[66] && + !tagLookup_tagCache_readReqReg[13] : + !tagLookup_tagCache_readReqReg[13]) ? + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4849 : + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4359 : + tagLookup_tagCache_readReqReg[13]) ; + assign IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4853 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] == 2'd0 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 == + tagLookup_mRsps_ff_rf$D_OUT_1[66] && + !tagLookup_tagCache_readReqReg[12] : + !tagLookup_tagCache_readReqReg[12]) ? + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4851 : + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4361 : + tagLookup_tagCache_readReqReg[12]) ; + assign IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4855 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] == 2'd0 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 == + tagLookup_mRsps_ff_rf$D_OUT_1[66] && + x__h122813 != 2'd3 && + !tagLookup_tagCache_readReqReg[11] : + !tagLookup_tagCache_readReqReg[11]) ? + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4853 : + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4368 : + tagLookup_tagCache_readReqReg[11]) ; + assign IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4857 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] == 2'd0 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 == + tagLookup_mRsps_ff_rf$D_OUT_1[66] && + x__h122813 != 2'd2 && + !tagLookup_tagCache_readReqReg[10] : + !tagLookup_tagCache_readReqReg[10]) ? + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4855 : + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4372 : + tagLookup_tagCache_readReqReg[10]) ; + assign IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4859 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] == 2'd0 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 == + tagLookup_mRsps_ff_rf$D_OUT_1[66] && + x__h122813 != 2'd1 && + !tagLookup_tagCache_readReqReg[9] : + !tagLookup_tagCache_readReqReg[9]) ? + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4857 : + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4377 : + tagLookup_tagCache_readReqReg[9]) ; + assign IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4861 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] == 2'd0 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 == + tagLookup_mRsps_ff_rf$D_OUT_1[66] && + x__h122813 != 2'd0 && + !tagLookup_tagCache_readReqReg[8] : + !tagLookup_tagCache_readReqReg[8]) ? + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4859 : + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4381 : + tagLookup_tagCache_readReqReg[8]) ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d3752 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3724 ? + { 85'h02AAAAAAAAAAAAAAAAAAAA, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3740 } : + { IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3749 ? + 2'd1 : + 2'd2, + tagLookup_tagCache_cts[227:136] } ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4117 = + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3568 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3607 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3640) ? + NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read__351_ETC___d4107 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4115 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4105 ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4219 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4218 : + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4214 && + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4212 ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4246 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4245 : + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4238 ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4296 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4295 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4293 ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4302 = + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3568 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3607 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3640) ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4301 : + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4299 ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4337 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4336 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4334 ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4503 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4502 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4500 ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4571 = + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3568 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3607 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3640) ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4570 : + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4568 ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4576 = + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3568 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3607 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3640) ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4575 : + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4573 ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4582 = + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3568 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3607 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3640) ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4581 : + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4579 ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4587 = + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3568 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3607 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3640) ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4586 : + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4584 ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4729 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read__351_ETC___d4107 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4727 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4105 ; + assign IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4937 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + { x1_avValue_snd_snd_snd_snd_snd_snd_d_oldWay__h278650, + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4935 } : + tagLookup_tagCache_readReqReg[2:0] ; + assign IF_IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff__ETC___d6137 = + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6121 ? + { 2'd0, + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6128 } : + (IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6134 ? + 4'd6 : + { 2'd2, mRsps_ff_rf$D_OUT_1[66:65] }) ; + assign IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4265 = + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + _theResult_____1_tag__h121522 : + tagLookup_tagCache_readReqReg[43:17] ; + assign IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4267 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4265 : + ((tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + tagLookup_tagCache_readReqReg[43:17] : + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4265) ; + assign IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4384 = + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + { NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4354, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4356, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4359, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4361, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4368, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4372, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4377, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4381 } : + tagLookup_tagCache_readReqReg[15:8] ; + assign IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4385 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4384 : + tagLookup_tagCache_readReqReg[15:8] ; + assign IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4494 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + !tagLookup_mRsps_ff_rf$D_OUT_1[66] && + tagLookup_tagCache_readReqReg[7] : + tagLookup_tagCache_readReqReg[7]) : + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0 && + tagLookup_tagCache_readReqReg[7] ; + assign IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4527 = + { (x__h135259 == 2'd3) ? + tagLookup_mRsps_ff_rf$D_OUT_1[64] : + tagLookup_tagCache_readReqReg[6], + (x__h135259 == 2'd2) ? + tagLookup_mRsps_ff_rf$D_OUT_1[64] : + tagLookup_tagCache_readReqReg[5], + (x__h135259 == 2'd1) ? + tagLookup_mRsps_ff_rf$D_OUT_1[64] : + tagLookup_tagCache_readReqReg[4], + (x__h135259 == 2'd0) ? + tagLookup_mRsps_ff_rf$D_OUT_1[64] : + tagLookup_tagCache_readReqReg[3] } ; + assign IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4530 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4527 : + tagLookup_tagCache_readReqReg[6:3]) : + tagLookup_tagCache_readReqReg[6:3] ; + assign IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4783 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4265 : + tagLookup_tagCache_readReqReg[43:17] ; + assign IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4800 = + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + { NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4354, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4356, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4359, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4361, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4368, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4372, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4377, + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4381, + !tagLookup_mRsps_ff_rf$D_OUT_1[66] && + tagLookup_tagCache_readReqReg[7], + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4527 } : + tagLookup_tagCache_readReqReg[15:3] ; + assign IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4801 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4800 : + tagLookup_tagCache_readReqReg[15:3] ; + assign IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4864 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + { way__h98147, + tagLookup_tagCache_readReqReg[16] && + IF_IF_IF_tagLookup_mRsps_ff_lhead_read__894_MI_ETC___d4861, + tagLookup_tagCache_readReqReg[0] } : + tagLookup_tagCache_readReqReg[2:0] ; + assign IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d3728 = + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 || + NOT_SEL_ARR_IF_tagLookup_tagCache_tags_0_readA_ETC___d3563) ? + ((tagLookup_tagCache_cts[229:228] == 2'd0) ? + tagLookup_tagCache_cts[144] : + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts[226]) : + tagLookup_tagCache_cts[144] ; + assign IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d3737 = + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 || + NOT_SEL_ARR_IF_tagLookup_tagCache_tags_0_readA_ETC___d3563) ? + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 ? + 6'd27 : + { 3'd0, tagLookup_tagCache_cts[138:136] }) : + tagLookup_tagCache_cts[141:136] ; + assign IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d3739 = + { IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d3728, + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 || + NOT_SEL_ARR_IF_tagLookup_tagCache_tags_0_readA_ETC___d3563) ? + tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts[143] : + tagLookup_tagCache_cts[143], + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3601 && + tagLookup_tagCache_cts[142], + IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d3737 } ; + assign IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d3762 = + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 || + NOT_SEL_ARR_IF_tagLookup_tagCache_tags_0_readA_ETC___d3563) ? + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 ? + 3'd3 : + 3'd0) : + tagLookup_tagCache_cts[141:139] ; + assign IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d4286 = + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 ? + tagLookup_tagCache_cts[135:109] : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4285 ; + assign IF_IF_tagLookup_tagCache_newReq_whas__787_AND__ETC___d2980 = + (((CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReq$wget[7:4] : + tagLookup_tagCache_cts[143:140]) == + 4'd8) ? + 2'd2 : + 2'd0 ; + assign IF_IF_tagLookup_tagCache_newReq_whas__787_AND__ETC___d3045 = + ((CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReq$wget[93:92] == 2'd1 : + tagLookup_tagCache_cts[229:228] == 2'd1) ? + _1_CONCAT_IF_tagLookup_tagCache_newReq_whas__78_ETC___d3040 : + _2_CONCAT_DONTCARE_CONCAT_IF_tagLookup_tagCache_ETC___d3044 ; + assign IF_IF_tagLookup_tagCache_newReq_whas__787_AND__ETC___d3046 = + ((CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReq$wget[93:92] == 2'd0 : + tagLookup_tagCache_cts[229:228] == 2'd0) ? + _0_CONCAT_DONTCARE_CONCAT_IF_tagLookup_tagCache_ETC___d3035 : + IF_IF_tagLookup_tagCache_newReq_whas__787_AND__ETC___d3045 ; + assign IF_IF_tagLookup_tagCache_newReq_whas__787_AND__ETC___d3067 = + ((CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReq$wget[0] : + tagLookup_tagCache_cts[136]) ? + x1_avValue_snd_addr_tag__h74941[0] : + tagLookup_tagCache_nextWay ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2317 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2311 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310) ? + idx__h45089 : + (IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2315 ? + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg : + 4'd0) ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2318 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2305 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304) ? + idx__h44973 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2317 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2319 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2299 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298) ? + idx__h44857 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2318 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2320 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2293 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292) ? + idx__h44741 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2319 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2321 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2287 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286) ? + idx__h44625 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2320 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2322 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2281 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280) ? + idx__h44509 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2321 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2323 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2275 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274) ? + idx__h44393 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2322 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2324 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2269 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268) ? + idx__h44277 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2323 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2325 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2263 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262) ? + idx__h44161 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2324 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2326 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2257 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256) ? + idx__h44045 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2325 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2327 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2251 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250) ? + idx__h43929 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2326 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2328 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2245 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244) ? + idx__h43813 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2327 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2329 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2239 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238) ? + idx__h43697 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2328 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2330 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2233 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232) ? + idx__h43581 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2329 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2479 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2473 ? + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 || + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2474 : + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2478 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2490 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + (tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2150) ? + (IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2471 ? + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2479 : + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2483) : + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2488) ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2505 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2459 ? + (IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2464 ? + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2490 : + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2496) : + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2504 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2514 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2452 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2156) ? + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2505 : + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2511 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2512) ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2535 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2438 ? + (IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2446 ? + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2514 : + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2523) : + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2534 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2547 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + (tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2425) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2162) ? + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2535 : + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2541 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2545) ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2574 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2408 ? + (IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2419 ? + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2547 : + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2559) : + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2573 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2589 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2395 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2168) ? + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2574 : + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2586 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2587) ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2622 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2369 ? + (IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2383 ? + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2589 : + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2604) : + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2621 ; + assign IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2626 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + (tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2350) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2193 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2198) ? + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2622 : + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2059 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2069 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2624) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2639 = + (newHead__h48716 == 5'd15) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + 5'd0 : + tagLookup_tagCache_orderer_mastReqIds_rf[79:75]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2643 = + (newHead__h48716 == 5'd14) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[79:75] : + tagLookup_tagCache_orderer_mastReqIds_rf[74:70]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2648 = + (newHead__h48716 == 5'd13) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[74:70] : + tagLookup_tagCache_orderer_mastReqIds_rf[69:65]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2652 = + (newHead__h48716 == 5'd12) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[69:65] : + tagLookup_tagCache_orderer_mastReqIds_rf[64:60]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2657 = + (newHead__h48716 == 5'd11) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[64:60] : + tagLookup_tagCache_orderer_mastReqIds_rf[59:55]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2661 = + (newHead__h48716 == 5'd10) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[59:55] : + tagLookup_tagCache_orderer_mastReqIds_rf[54:50]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2666 = + (newHead__h48716 == 5'd9) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[54:50] : + tagLookup_tagCache_orderer_mastReqIds_rf[49:45]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2670 = + (newHead__h48716 == 5'd8) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[49:45] : + tagLookup_tagCache_orderer_mastReqIds_rf[44:40]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2675 = + (newHead__h48716 == 5'd7) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[44:40] : + tagLookup_tagCache_orderer_mastReqIds_rf[39:35]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2679 = + (newHead__h48716 == 5'd6) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[39:35] : + tagLookup_tagCache_orderer_mastReqIds_rf[34:30]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2684 = + (newHead__h48716 == 5'd5) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[34:30] : + tagLookup_tagCache_orderer_mastReqIds_rf[29:25]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2688 = + (newHead__h48716 == 5'd4) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[29:25] : + tagLookup_tagCache_orderer_mastReqIds_rf[24:20]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2693 = + (newHead__h48716 == 5'd3) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[24:20] : + tagLookup_tagCache_orderer_mastReqIds_rf[19:15]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2697 = + (newHead__h48716 == 5'd2) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[19:15] : + tagLookup_tagCache_orderer_mastReqIds_rf[14:10]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2702 = + (newHead__h48716 == 5'd1) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[14:10] : + tagLookup_tagCache_orderer_mastReqIds_rf[9:5]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqIds_de_ETC___d2706 = + (newHead__h48716 == 5'd0) ? + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] : + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + tagLookup_tagCache_orderer_mastReqIds_rf[9:5] : + tagLookup_tagCache_orderer_mastReqIds_rf[4:0]) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1146 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1140 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139) ? + idx__h33300 : + (IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1144 ? + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg : + 4'd0) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1147 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1134 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133) ? + idx__h33184 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1146 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1148 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1128 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127) ? + idx__h33068 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1147 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1149 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1122 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121) ? + idx__h32952 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1148 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1150 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1116 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115) ? + idx__h32836 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1149 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1151 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1110 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109) ? + idx__h32720 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1150 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1152 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1104 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103) ? + idx__h32604 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1151 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1153 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1098 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097) ? + idx__h32488 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1152 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1154 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1092 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091) ? + idx__h32372 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1153 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1155 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1086 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085) ? + idx__h32256 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1154 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1156 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1080 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079) ? + idx__h32140 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1155 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1157 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1074 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073) ? + idx__h32024 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1156 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1158 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1068 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067) ? + idx__h31908 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1157 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1159 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1062 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061) ? + idx__h31792 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1158 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1308 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1302 ? + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 || + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1303 : + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1307 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1319 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + (tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d979) ? + (IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1300 ? + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1308 : + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1312) : + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1317) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1334 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1288 ? + (IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1293 ? + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1319 : + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1325) : + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1333 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1343 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1281 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d985) ? + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1334 : + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1340 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1341) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1364 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1267 ? + (IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1275 ? + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1343 : + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1352) : + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1363 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1376 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + (tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1254) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d991) ? + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1364 : + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1370 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1374) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1403 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1237 ? + (IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1248 ? + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1376 : + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1388) : + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1402 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1418 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1224 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d997) ? + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1403 : + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1415 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1416) ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1451 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1198 ? + (IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1212 ? + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1418 : + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1433) : + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1450 ; + assign IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1455 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + (tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1179) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1022 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1027) ? + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1451 : + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d888 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d898 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1453) ; + assign IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4339 = + (IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3561 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4117 || + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4219) ? + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4337 : + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4337 ; + assign IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4486 = + (IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3561 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4117 || + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4219) ? + { IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4398, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4408, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4419, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4429, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4440, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4450, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4461, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4471 } : + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4484 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4482) ; + assign IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4505 = + (IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3561 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4117 || + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4219) ? + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4503 : + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4503 ; + assign IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4638 = + (IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3561 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4117 || + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4219) ? + { IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4599, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4608, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4618, + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4627 } : + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4636 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4634) ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4218 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4217 : + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4214 && + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4212 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4245 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4241 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4243 && + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4238 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4295 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4294 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4293 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4301 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566 ? + tagLookup_tagCache_cts[135:109] : + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4299) : + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4299 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4336 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4335 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4334 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4396 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4395 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4394 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4406 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4405 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4404 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4417 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4416 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4415 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4427 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4426 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4425 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4438 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4437 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4436 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4448 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4447 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4446 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4459 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4458 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4457 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4469 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4468 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4467 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4484 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4483 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4482 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4502 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4501 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4500 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4570 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4567 && + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4568 : + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4568 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4575 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4567 && + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4573 : + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4573 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4581 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4567 && + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4579 : + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4579 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4586 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4567 && + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4584 : + IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4584 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4597 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4596 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4595 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4606 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4605 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4604 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4616 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4615 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4614 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4625 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4624 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4623 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4636 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4635 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4634 ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4668 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4667 : + tagLookup_tagCache_readReqReg[66] ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4687 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4686 : + tagLookup_tagCache_readReqReg[57:52] ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4757 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4756 : + tagLookup_tagCache_readReqReg[51] ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4769 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4768 : + tagLookup_tagCache_readReqReg[50:45] ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4777 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4776 : + tagLookup_tagCache_readReqReg[44] ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4786 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4785 : + tagLookup_tagCache_readReqReg[43:17] ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4793 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4792 : + tagLookup_tagCache_readReqReg[16] ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4805 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4804 : + tagLookup_tagCache_readReqReg[15:3] ; + assign IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4935 = + (x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4934 : + tagLookup_tagCache_readReqReg[1:0] ; + assign IF_NOT_tagLookup_currentDepth_338_EQ_0_339_363_ETC___d5495 = + (tagLookup_currentDepth != 2'd0 && + IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358) ? + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490 : + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493 ; + assign IF_NOT_tagLookup_currentDepth_338_EQ_0_339_363_ETC___d5731 = + (tagLookup_currentDepth != 2'd0 && + IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358) ? + tagLookup_state : + IF_tagLookup_currentDepth_338_EQ_0_339_THEN_IF_ETC___d5730 ; + assign IF_NOT_tagLookup_mRsps_ff_lhead_read__894_MINU_ETC___d3019 = + (level__h1463 != 2'd0 && + !tagLookup_tagCache_orderer_slaveRespState[12] || + NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d3016) ? + 2'd2 : + tagLookup_tagCache_cts[278:277] ; + assign IF_NOT_tagLookup_mRsps_ff_lhead_read__894_MINU_ETC___d4775 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + ((IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 : + tagLookup_tagCache_readReqReg[44]) : + tagLookup_tagCache_readReqReg[44] ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3568 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1) ? + tagLookup_tagCache_cts[139:137] != 3'd4 : + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3607 = + ((tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1) ? + tagLookup_tagCache_cts[139:137] == 3'd4 : + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3582 || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3604) || + !tagLookup_tagCache_readReqReg[66] ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3640 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1) ? + tagLookup_tagCache_cts[139:137] != 3'd4 || + tagLookup_tagCache_cts[143:140] == 4'd0 && + tagLookup_tagCache_cts_read__795_BIT_136_060_O_ETC___d3609 || + IF_tagLookup_tagCache_cts_read__795_BITS_143_T_ETC___d3628 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3639 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3568 && + (IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3561 || + tagLookup_tagCache_cts[229:228] == 2'd0) && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3607 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3640 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3689 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3683) ? + tagLookup_tagCache_cts[276:237] : + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 ? + { y_avValue_fst_addr_lineNumber__h114872, 3'd0 } : + tagLookup_tagCache_cts[276:237]) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3724 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3683) ? + tagLookup_tagCache_cts[229:228] == 2'd0 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 || + NOT_SEL_ARR_IF_tagLookup_tagCache_tags_0_readA_ETC___d3563 || + tagLookup_tagCache_cts[229:228] == 2'd0 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3740 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3683) ? + tagLookup_tagCache_cts[144:136] : + IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d3739 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3749 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3683) ? + tagLookup_tagCache_cts[229:228] == 2'd1 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3746 && + tagLookup_tagCache_cts[229:228] == 2'd1 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3763 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3683) ? + tagLookup_tagCache_cts[141:139] : + IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d3762 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3767 = + { IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3689[4:3], + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3724 ? + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3689[4:3] + + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3763[1:0] : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3689[4:3], + 7'h2A } ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4105 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1) ? + tagLookup_tagCache_cts[139:137] != 3'd4 || + tagLookup_tagCache_cts[143:140] == 4'd0 && + tagLookup_tagCache_cts_read__795_BIT_136_060_O_ETC___d3609 || + IF_tagLookup_tagCache_cts_read__795_BITS_143_T_ETC___d3628 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4104 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4115 = + ((tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1) ? + tagLookup_tagCache_cts[139:137] == 3'd4 : + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3582 || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4112) || + !tagLookup_tagCache_readReqReg[66] ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4233 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1) ? + tagLookup_tagCache_cts[139:137] == 3'd4 && + (tagLookup_tagCache_cts[143:140] == 4'd0 || + tagLookup_tagCache_cts[143:140] == 4'd1) && + tagLookup_tagCache_cts_read__795_BIT_136_060_O_ETC___d3609 : + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4232 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4293 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + x_addr_tag__h102720 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4284 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1) ? + tagLookup_tagCache_cts[139:137] != 3'd4 || + (tagLookup_tagCache_cts[143:140] != 4'd0 || + NOT_tagLookup_tagCache_cts_read__795_BIT_136_0_ETC___d3625) && + (tagLookup_tagCache_cts[143:140] != 4'd1 || + NOT_tagLookup_tagCache_cts_read__795_BIT_136_0_ETC___d3625) : + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4324 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4334 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291 || + tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 : + tagLookup_tagCache_cts[229:228] == 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3676 && + !tagLookup_tagCache_cts[225] || + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4394 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4393 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4398 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4396 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4394) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4404 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4403 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4408 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4406 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4404) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4415 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4414 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4419 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4417 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4415) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4425 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4424 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4429 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4427 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4425) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4436 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4435 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4440 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4438 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4436) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4446 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4445 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4450 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4448 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4446) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4457 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4456 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4461 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4459 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4457) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4467 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4466 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4471 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4469 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4467) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4482 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 } : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4481 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4500 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4047 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4497 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4595 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4594 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4599 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4597 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4595) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4604 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4603 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4608 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4606 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4604) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4614 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4613 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4618 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4616 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4614) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4623 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4622 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4627 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4325 && + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4625 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4623) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4634 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291) ? + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 } : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4633 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4715 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_143_TO_1_ETC___d4693 || + level__h1463 == 2'd0) ? + tagLookup_tagCache_cts[236] : + x1_avValue_snd_snd_snd_snd_snd_snd_fst_req_masterID__h98350 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4718 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_143_TO_1_ETC___d4693 || + level__h1463 == 2'd0) ? + tagLookup_tagCache_cts[235:231] : + x1_avValue_snd_snd_snd_snd_snd_snd_fst_req_transactionID__h98351 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4723 = + ((NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4697 || + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d4698) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4705) ? + (NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4712 ? + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4715 == + tagLookup_tagCache_readReqReg[57] && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4718 == + tagLookup_tagCache_readReqReg[56:52] || + tagLookup_tagCache_readReqReg[51] : + tagLookup_tagCache_readReqReg[51]) : + tagLookup_tagCache_readReqReg[51] ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4727 = + ((tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1) ? + tagLookup_tagCache_cts[139:137] == 3'd4 : + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3582 || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4243) || + !tagLookup_tagCache_readReqReg[66] ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4959 = + ((NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4697 || + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d4698) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4705) ? + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4958 : + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1 || + NOT_tagLookup_tagCache_cts_read__795_BITS_143__ETC___d4951) && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4996 = + ((NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4697 || + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d4698) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4705) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4994 : + tagLookup_mRsps_ff_rf$D_OUT_1[66:65] ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d5017 = + ((NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4697 || + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d4698) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4705) ? + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4991 && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d5015 : + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d5015 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d5033 = + (tagLookup_tagCache_cts[278:277] != 2'd1 && + ((tagLookup_tagCache_cts[278:277] == 2'd2) ? + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4959 : + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d4983)) ? + { 2'd0, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q32 } : + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5032 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d5043 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_143_TO_1_ETC___d4693 || + level__h1463 == 2'd0) ? + tagLookup_tagCache_cts[236:231] : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d5042 ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d5044 = + ((NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4697 || + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d4698) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4705) ? + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d5043 : + tagLookup_tagCache_cts[236:231] ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BIT_22_ETC___d4304 = + (!tagLookup_tagCache_cts[225] && + NOT_tagLookup_tagCache_cts_read__795_BIT_226_5_ETC___d4121) ? + y_avValue_snd_snd_snd_newTag_tag__h121536 : + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4233 ? + 27'd0 : + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4302) ; + assign IF_NOT_tagLookup_tagCache_cts_read__795_BIT_22_ETC___d4590 = + (!tagLookup_tagCache_cts[225] && + NOT_tagLookup_tagCache_cts_read__795_BIT_226_5_ETC___d4121) ? + { IF_tagLookup_tagCache_cts_read__795_BITS_100_T_ETC___d4547, + IF_tagLookup_tagCache_cts_read__795_BITS_100_T_ETC___d4551, + IF_tagLookup_tagCache_cts_read__795_BITS_100_T_ETC___d4556, + IF_tagLookup_tagCache_cts_read__795_BITS_100_T_ETC___d4560 } : + { _0_OR_NOT_tagLookup_tagCache_cts_read__795_BIT__ETC___d4563 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4571, + _0_OR_NOT_tagLookup_tagCache_cts_read__795_BIT__ETC___d4563 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4576, + _0_OR_NOT_tagLookup_tagCache_cts_read__795_BIT__ETC___d4563 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4582, + _0_OR_NOT_tagLookup_tagCache_cts_read__795_BIT__ETC___d4563 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4587 } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2175 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2168 ? + 32'd3 : + (NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2170 ? + 32'd2 : + (NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2172 ? + 32'd1 : + 32'd0)) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2177 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2164 ? + 32'd5 : + (NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2166 ? + 32'd4 : + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2175) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2179 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2160 ? + 32'd7 : + (NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2162 ? + 32'd6 : + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2177) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2181 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2156 ? + 32'd9 : + (NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2158 ? + 32'd8 : + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2179) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2183 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2152 ? + 32'd11 : + (NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2154 ? + 32'd10 : + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2181) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2185 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2148 ? + 32'd13 : + (NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2150 ? + 32'd12 : + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2183) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2144 ? + 32'd15 : + (NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2146 ? + 32'd14 : + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2185) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1663 = + (NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654, + tagLookup_tagCache_orderer_mastLines_bag[628:588] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1687 = + (NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678, + tagLookup_tagCache_orderer_mastLines_bag[586:546] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1711 = + (NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702, + tagLookup_tagCache_orderer_mastLines_bag[544:504] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1737 = + (NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728, + tagLookup_tagCache_orderer_mastLines_bag[502:462] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1763 = + (NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754, + tagLookup_tagCache_orderer_mastLines_bag[460:420] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1791 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1777 ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782, + tagLookup_tagCache_orderer_mastLines_bag[418:378] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1819 = + (NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1804) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810, + tagLookup_tagCache_orderer_mastLines_bag[376:336] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1849 = + (NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1833) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840, + tagLookup_tagCache_orderer_mastLines_bag[334:294] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1879 = + (NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1862) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870, + tagLookup_tagCache_orderer_mastLines_bag[292:252] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1911 = + (NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1893) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902, + tagLookup_tagCache_orderer_mastLines_bag[250:210] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1943 = + (NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1924) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934, + tagLookup_tagCache_orderer_mastLines_bag[208:168] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d1977 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1963 ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1968, + tagLookup_tagCache_orderer_mastLines_bag[166:126] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d2011 = + (NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1996) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2002, + tagLookup_tagCache_orderer_mastLines_bag[124:84] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d2047 = + (NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2031) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2038, + tagLookup_tagCache_orderer_mastLines_bag[82:42] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastLines_re_ETC___d2078 = + (NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2059) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2069, + tagLookup_tagCache_orderer_mastLines_bag[40:0] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1004 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d997 ? + 32'd3 : + (NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d999 ? + 32'd2 : + (NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1001 ? + 32'd1 : + 32'd0)) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1006 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d993 ? + 32'd5 : + (NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d995 ? + 32'd4 : + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1004) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1008 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d989 ? + 32'd7 : + (NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d991 ? + 32'd6 : + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1006) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1010 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d985 ? + 32'd9 : + (NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d987 ? + 32'd8 : + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1008) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1012 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d981 ? + 32'd11 : + (NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d983 ? + 32'd10 : + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1010) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1014 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d977 ? + 32'd13 : + (NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d979 ? + 32'd12 : + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1012) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d973 ? + 32'd15 : + (NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d975 ? + 32'd14 : + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1014) ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d492 = + (NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483, + tagLookup_tagCache_orderer_mastReqs_bag[883:826] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d516 = + (NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507, + tagLookup_tagCache_orderer_mastReqs_bag[824:767] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d540 = + (NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531, + tagLookup_tagCache_orderer_mastReqs_bag[765:708] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d566 = + (NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557, + tagLookup_tagCache_orderer_mastReqs_bag[706:649] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d592 = + (NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583, + tagLookup_tagCache_orderer_mastReqs_bag[647:590] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d620 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d606 ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611, + tagLookup_tagCache_orderer_mastReqs_bag[588:531] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d648 = + (NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d633) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639, + tagLookup_tagCache_orderer_mastReqs_bag[529:472] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d678 = + (NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d662) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669, + tagLookup_tagCache_orderer_mastReqs_bag[470:413] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d708 = + (NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d691) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699, + tagLookup_tagCache_orderer_mastReqs_bag[411:354] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d740 = + (NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d722) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731, + tagLookup_tagCache_orderer_mastReqs_bag[352:295] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d772 = + (NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d753) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763, + tagLookup_tagCache_orderer_mastReqs_bag[293:236] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d806 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d792 ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d797, + tagLookup_tagCache_orderer_mastReqs_bag[234:177] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d840 = + (NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d825) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d831, + tagLookup_tagCache_orderer_mastReqs_bag[175:118] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d876 = + (NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d860) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d867, + tagLookup_tagCache_orderer_mastReqs_bag[116:59] } ; + assign IF_NOT_tagLookup_tagCache_orderer_mastReqs_rem_ETC___d907 = + (NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d888) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d898, + tagLookup_tagCache_orderer_mastReqs_bag[57:0] } ; + assign IF_NOT_tagLookup_tagCache_orderer_slaveReqs_ba_ETC___d5004 = + (NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d4279 || + tagLookup_tagCache_writebacks$EMPTY_N || + tagLookup_tagCache_invalidateWritebacks$EMPTY_N) ? + tagLookup_mRsps_ff_rf$D_OUT_1[66:65] : + { IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d5000, + (tagLookup_tagCache_cts[229:228] != 2'd0 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3534 || + tagLookup_tagCache_cts[143]) && + tagLookup_mRsps_ff_rf$D_OUT_1[65] } ; + assign IF_NOT_writeBuffer_ff_rf_sub_writeBuffer_ff_lt_ETC___d5977 = + (writeBuffer_ff_rf$D_OUT_1[93:92] != 2'd1 || + writeBuffer_ff_rf$D_OUT_1[88:81] == 8'd0 || + !writeBuffer_ff_rf$D_OUT_1[72]) ? + 94'h055555555555555555555403 : + { 5'd12, + _0_CONCAT_writeBuffer_ff_rf_sub_writeBuffer_ff__ETC___d5950[2:0] == + 3'd7, + _0_CONCAT_writeBuffer_ff_rf_sub_writeBuffer_ff__ETC___d5950[2:0] == + 3'd6, + _0_CONCAT_writeBuffer_ff_rf_sub_writeBuffer_ff__ETC___d5950[2:0] == + 3'd5, + _0_CONCAT_writeBuffer_ff_rf_sub_writeBuffer_ff__ETC___d5950[2:0] == + 3'd4, + _0_CONCAT_writeBuffer_ff_rf_sub_writeBuffer_ff__ETC___d5950[2:0] == + 3'd3, + _0_CONCAT_writeBuffer_ff_rf_sub_writeBuffer_ff__ETC___d5950[2:0] == + 3'd2, + _0_CONCAT_writeBuffer_ff_rf_sub_writeBuffer_ff__ETC___d5950[2:0] == + 3'd1, + _0_CONCAT_writeBuffer_ff_rf_sub_writeBuffer_ff__ETC___d5950[2:0] == + 3'd0, + x__h320966, + 1'd0, + wdata_data__h321116, + 8'd0 } ; + assign IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4210 = + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 ? + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 : + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488 ; + assign IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4283 = + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 ? + x_addr_tag__h102720 : + 27'd0 ; + assign IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4924 = + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q5 ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027 ; + assign IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4925 = + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q6 ? + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4924 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030 ; + assign IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4926 = + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q7 ? + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4925 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032 ; + assign IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4927 = + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q8 ? + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4926 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035 ; + assign IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4928 = + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q9 ? + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4927 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037 ; + assign IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4929 = + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q10 ? + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4928 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040 ; + assign IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4930 = + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q11 ? + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4929 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 ; + assign IF_SEL_ARR_tagLookup_oldTags_0_714_tagLookup_o_ETC___d5721 = + (CASE_tagLookup_currentDepth_0_tagLookup_oldTag_ETC__q17 == + 64'd0 && + tagLookup_currentDepth == 2'd0) ? + tagLookup_currentDepth + 2'd1 : + tagLookup_currentDepth_338_MINUS_1___d5481 ; + assign IF_SEL_ARR_tagLookup_oldTags_0_714_tagLookup_o_ETC___d5733 = + (CASE_tagLookup_currentDepth_0_tagLookup_oldTag_ETC__q17 == + 64'd0 && + tagLookup_currentDepth == 2'd0) ? + 3'd5 : + 3'd1 ; + assign IF_lookupRsp_bag_748_BIT_17_761_AND_lookupRsp__ETC___d6168 = + (lookupRsp_bag[17] && + lookupRsp_bag_748_BIT_16_749_EQ_mRsps_ff_rf_su_ETC___d6102 && + lookupRsp_bag_748_BITS_15_TO_11_754_EQ_mRsps_f_ETC___d6104 && + lookupRsp_bag[4]) ? + CASE_x30808_0_lookupRsp_bag_BIT_0_1_lookupRsp__ETC__q15 : + !lookupRsp_bag[17] || + !lookupRsp_bag_748_BIT_16_749_EQ_mRsps_ff_rf_su_ETC___d6102 || + !lookupRsp_bag_748_BITS_15_TO_11_754_EQ_mRsps_f_ETC___d6104 || + lookupRsp_bag[4] ; + assign IF_lookupRsp_insertItem_whas__738_AND_lookupRs_ETC___d5763 = + (CAN_FIRE_RL_getTagLookupResponse && + lookupRsp_insertItem$wget[17]) ? + CAN_FIRE_RL_getTagLookupResponse : + (!lookupRsp_removeItem$whas || !lookupRsp_removeItem$wget[6] || + lookupRsp_bag[16] != lookupRsp_removeItem$wget[5] || + lookupRsp_bag[15:11] != lookupRsp_removeItem$wget[4:0]) && + lookupRsp_bag[17] ; + assign IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6108 = + (level__h314581 == 6'd0) ? + tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 && + frame == 3'd0 && + lookupRsp_bag_748_BIT_17_761_AND_lookupRsp_bag_ETC___d6095 : + mRsps_ff_rf$D_OUT_1[68:67] == 2'd0 && lookupRsp_bag[17] && + lookupRsp_bag_748_BIT_16_749_EQ_mRsps_ff_rf_su_ETC___d6102 && + lookupRsp_bag_748_BITS_15_TO_11_754_EQ_mRsps_f_ETC___d6104 ; + assign IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6119 = + (level__h314581 == 6'd0) ? + ((tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 && + frame == 3'd0) ? + 2'd0 : + mRsps_ff_rf$D_OUT_1[70:69]) : + mRsps_ff_rf$D_OUT_1[70:69] ; + assign IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6121 = + (level__h314581 == 6'd0) ? + tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 && + frame == 3'd0 || + mRsps_ff_rf$D_OUT_1[68:67] == 2'd0 : + mRsps_ff_rf$D_OUT_1[68:67] == 2'd0 ; + assign IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6128 = + (level__h314581 == 6'd0) ? + { tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 && + frame == 3'd0 || + mRsps_ff_rf$D_OUT_1[66], + tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 && + frame == 3'd0 || + mRsps_ff_rf$D_OUT_1[65] } : + mRsps_ff_rf$D_OUT_1[66:65] ; + assign IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6134 = + (level__h314581 == 6'd0) ? + (!tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 || + frame != 3'd0) && + mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 : + mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 ; + assign IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6171 = + (level__h314581 == 6'd0) ? + { (!tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 || + frame != 3'd0) && + mRsps_ff_rf$D_OUT_1[64], + _theResult___snd_snd_fst_data_data__h330563 } : + { (mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + IF_lookupRsp_bag_748_BIT_17_761_AND_lookupRsp__ETC___d6168 : + mRsps_ff_rf$D_OUT_1[64], + mRsps_ff_rf$D_OUT_1[63:0] } ; + assign IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6179 = + (level__h314581 == 6'd0) ? + tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 && + frame == 3'd0 || + mRsps_ff_rf$D_OUT_1[66] : + mRsps_ff_rf$D_OUT_1[66] ; + assign IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6180 = + (level__h314581 == 6'd0) ? + tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 && + frame == 3'd0 || + mRsps_ff_rf$D_OUT_1[65] : + mRsps_ff_rf$D_OUT_1[65] ; + assign IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6185 = + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6121 && + (level__h314581 == 6'd0 || mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) && + (IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6179 || + IF_mRsps_ff_lhead_read__082_MINUS_mRsps_ff_lta_ETC___d6180) ; + assign IF_tagLookup_currentDepth_338_EQ_0_339_THEN_1__ETC___d5726 = + (tagLookup_currentDepth == 2'd0) ? + 3'd1 : + (IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 ? + tagLookup_state : + 3'd1) ; + assign IF_tagLookup_currentDepth_338_EQ_0_339_THEN_IF_ETC___d5713 = + (tagLookup_currentDepth == 2'd0) ? + ((tagLookup_tagCache_resps$wget[219:156] == 64'd0 && + !tagLookup_pendingTags) ? + 2'd1 : + tagLookup_currentDepth_338_MINUS_1___d5481) : + tagLookup_currentDepth_338_MINUS_1___d5481 ; + assign IF_tagLookup_currentDepth_338_EQ_0_339_THEN_IF_ETC___d5730 = + (tagLookup_currentDepth == 2'd0) ? + ((tagLookup_tagCache_resps$wget[219:156] == 64'd0 && + !tagLookup_pendingTags) ? + 3'd5 : + 3'd1) : + tagLookup_state ; + assign IF_tagLookup_currentDepth_338_EQ_1_466_THEN_0__ETC___d5648 = + (tagLookup_currentDepth == 2'd1) ? + { _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd7 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304386 == 3'd4 || + nodeOffset__h304386 == 3'd5 || + nodeOffset__h304386 == 3'd6 || + nodeOffset__h304386 == 3'd7), + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd6 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304386 == 3'd3 || + nodeOffset__h304386 == 3'd4 || + nodeOffset__h304386 == 3'd5 || + nodeOffset__h304386 == 3'd6), + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd5 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304386 == 3'd2 || + nodeOffset__h304386 == 3'd3 || + nodeOffset__h304386 == 3'd4 || + nodeOffset__h304386 == 3'd5), + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd4 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304386 == 3'd1 || + nodeOffset__h304386 == 3'd2 || + nodeOffset__h304386 == 3'd3 || + nodeOffset__h304386 == 3'd4), + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd3 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304386 == 3'd0 || + nodeOffset__h304386 == 3'd1 || + nodeOffset__h304386 == 3'd2 || + nodeOffset__h304386 == 3'd3), + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd2 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304386 == 3'd7 || + nodeOffset__h304386 == 3'd0 || + nodeOffset__h304386 == 3'd1 || + nodeOffset__h304386 == 3'd2), + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd1 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304386 == 3'd6 || + nodeOffset__h304386 == 3'd7 || + nodeOffset__h304386 == 3'd0 || + nodeOffset__h304386 == 3'd1), + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd0 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304386 == 3'd5 || + nodeOffset__h304386 == 3'd6 || + nodeOffset__h304386 == 3'd7 || + nodeOffset__h304386 == 3'd0) } : + { _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490[2:0] == + 3'd7 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304822 == 3'd4 || + nodeOffset__h304822 == 3'd5 || + nodeOffset__h304822 == 3'd6 || + nodeOffset__h304822 == 3'd7), + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490[2:0] == + 3'd6 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304822 == 3'd3 || + nodeOffset__h304822 == 3'd4 || + nodeOffset__h304822 == 3'd5 || + nodeOffset__h304822 == 3'd6), + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490[2:0] == + 3'd5 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304822 == 3'd2 || + nodeOffset__h304822 == 3'd3 || + nodeOffset__h304822 == 3'd4 || + nodeOffset__h304822 == 3'd5), + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490[2:0] == + 3'd4 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304822 == 3'd1 || + nodeOffset__h304822 == 3'd2 || + nodeOffset__h304822 == 3'd3 || + nodeOffset__h304822 == 3'd4), + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490[2:0] == + 3'd3 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304822 == 3'd0 || + nodeOffset__h304822 == 3'd1 || + nodeOffset__h304822 == 3'd2 || + nodeOffset__h304822 == 3'd3), + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490[2:0] == + 3'd2 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304822 == 3'd7 || + nodeOffset__h304822 == 3'd0 || + nodeOffset__h304822 == 3'd1 || + nodeOffset__h304822 == 3'd2), + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490[2:0] == + 3'd1 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304822 == 3'd6 || + nodeOffset__h304822 == 3'd7 || + nodeOffset__h304822 == 3'd0 || + nodeOffset__h304822 == 3'd1), + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490[2:0] == + 3'd0 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 && + SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 && + (nodeOffset__h304822 == 3'd5 || + nodeOffset__h304822 == 3'd6 || + nodeOffset__h304822 == 3'd7 || + nodeOffset__h304822 == 3'd0) } ; + assign IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 = + (level__h1463 == 2'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d3970 ; + assign IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3980 = + (level__h1463 == 2'd0) ? + tagLookup_tagCache_cts[92:83] : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d3979 ; + assign IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 = + (level__h1463 == 2'd0) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4047 : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4192 ; + assign IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4387 = + (level__h1463 == 2'd0) ? + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 } : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4386 ; + assign IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4532 = + (level__h1463 == 2'd0) ? + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 } : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4531 ; + assign IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5367 = + (tagLookup_state == 3'd2 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 && + !tagLookup_lookupRsp_ff_lhead_read__318_MINUS_t_ETC___d5320) ? + tagLookup_currentDepth == 2'd0 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 : + IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5366 ; + assign IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5477 = + (tagLookup_state == 3'd2 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 && + !tagLookup_lookupRsp_ff_lhead_read__318_MINUS_t_ETC___d5320) ? + tagLookup_currentDepth != 2'd0 && + IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 : + IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5476 ; + assign IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5498 = + (tagLookup_state == 3'd2 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 && + !tagLookup_lookupRsp_ff_lhead_read__318_MINUS_t_ETC___d5320) ? + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490 : + IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5497 ; + assign IF_tagLookup_state_read__216_EQ_2_311_AND_tagL_ETC___d5701 = + tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5499 ? + 94'h055555555555555555555403 : + { 5'd12, + IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5666, + x__h306917, + 1'd0, + IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5697, + 8'd0 } ; + assign IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5366 = + (tagLookup_state == 3'd3 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + tagLookup_currentDepth == 2'd0 : + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5365 ; + assign IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5476 = + (tagLookup_state == 3'd3 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + tagLookup_currentDepth != 2'd0 : + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5475 ; + assign IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5497 = + (tagLookup_state == 3'd3 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + ((tagLookup_currentDepth == 2'd1) ? + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493 : + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490) : + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5496 ; + assign IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5666 = + (tagLookup_state == 3'd3 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + IF_tagLookup_currentDepth_338_EQ_1_466_THEN_0__ETC___d5648 : + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5665 ; + assign IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5697 = + (tagLookup_state == 3'd3 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + data_data__h307593 : + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5696 ; + assign IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5706 = + (tagLookup_state == 3'd3 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + tagLookup_currentDepth != 2'd0 && + tagLookup_currentDepth != 2'd1 : + tagLookup_state == 3'd4 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 && + tagLookup_currentDepth != 2'd0 && + IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 ; + assign IF_tagLookup_state_read__216_EQ_3_323_AND_tagL_ETC___d5736 = + (tagLookup_state == 3'd3 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + CASE_tagLookup_currentDepth_0_1_1_1_tagLookup__ETC__q38 : + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5735 ; + assign IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5365 = + (tagLookup_state == 3'd4 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + tagLookup_currentDepth != 2'd0 && + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 : + tagLookup_state != 3'd5 ; + assign IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5475 = + (tagLookup_state == 3'd4 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 || + tagLookup_currentDepth == 2'd0 : + tagLookup_state == 3'd5 ; + assign IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5496 = + (tagLookup_state == 3'd4 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + IF_NOT_tagLookup_currentDepth_338_EQ_0_339_363_ETC___d5495 : + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354 ; + assign IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5665 = + (tagLookup_state == 3'd4 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + { _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd7, + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd6, + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd5, + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd4, + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd3, + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd2, + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd1, + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] == + 3'd0 } : + { _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354[2:0] == + 3'd7, + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354[2:0] == + 3'd6, + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354[2:0] == + 3'd5, + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354[2:0] == + 3'd4, + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354[2:0] == + 3'd3, + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354[2:0] == + 3'd2, + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354[2:0] == + 3'd1, + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354[2:0] == + 3'd0 } ; + assign IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5682 = + (tagLookup_state == 3'd4 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + bitEnable__h303992 : + _theResult_____1_snd__h307357 ; + assign IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5696 = + (tagLookup_state == 3'd4 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + wdata_data__h307595 : + wdata_data__h307597 ; + assign IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5723 = + (tagLookup_state == 3'd4 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + IF_tagLookup_currentDepth_338_EQ_0_339_THEN_IF_ETC___d5713 : + ((tagLookup_state == 3'd5) ? + IF_SEL_ARR_tagLookup_oldTags_0_714_tagLookup_o_ETC___d5721 : + tagLookup_currentDepth_338_MINUS_1___d5481) ; + assign IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5735 = + (tagLookup_state == 3'd4 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + ((tagLookup_currentDepth != 2'd0 && + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358) ? + 3'd1 : + IF_NOT_tagLookup_currentDepth_338_EQ_0_339_363_ETC___d5731) : + ((tagLookup_state == 3'd5) ? + IF_SEL_ARR_tagLookup_oldTags_0_714_tagLookup_o_ETC___d5733 : + tagLookup_state) ; + assign IF_tagLookup_tagCacheReq_ff_rf_BITS_93_TO_92_E_ETC__q40 = + (tagLookup_tagCacheReq_ff_rf[93:92] == 2'd0) ? + tagLookup_tagCacheReq_ff_rf[5:3] : + 3'd0 ; + assign IF_tagLookup_tagCache_cts_BITS_229_TO_228_EQ_0_ETC__q4 = + (tagLookup_tagCache_cts[229:228] == 2'd0) ? + tagLookup_tagCache_cts[141:139] : + 3'd0 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_100_T_ETC___d4547 = + (tagLookup_tagCache_cts[100:99] == 2'd3) ? + IF_tagLookup_tagCache_cts_read__795_BITS_224_T_ETC___d4544 : + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_100_T_ETC___d4551 = + (tagLookup_tagCache_cts[100:99] == 2'd2) ? + IF_tagLookup_tagCache_cts_read__795_BITS_224_T_ETC___d4544 : + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_100_T_ETC___d4556 = + (tagLookup_tagCache_cts[100:99] == 2'd1) ? + IF_tagLookup_tagCache_cts_read__795_BITS_224_T_ETC___d4544 : + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_100_T_ETC___d4560 = + (tagLookup_tagCache_cts[100:99] == 2'd0) ? + IF_tagLookup_tagCache_cts_read__795_BITS_224_T_ETC___d4544 : + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_143_T_ETC___d3628 = + (tagLookup_tagCache_cts[143:140] == 4'd1 && + tagLookup_tagCache_cts_read__795_BIT_136_060_O_ETC___d3609) ? + !SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d3614 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 || + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 : + NOT_tagLookup_tagCache_cts_read__795_BITS_143__ETC___d3627 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_224_T_ETC___d4544 = + (tagLookup_tagCache_cts[224:217] == 8'd0) ? + SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d4542 : + tagLookup_tagCache_cts[208] ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 = + (tagLookup_tagCache_cts[229:228] == 2'd0) ? + !tagLookup_tagCache_cts[144] : + tagLookup_tagCache_cts[229:228] == 2'd1 && + !tagLookup_tagCache_cts[226] ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 = + (tagLookup_tagCache_cts[229:228] == 2'd0) ? + tagLookup_tagCache_cts[144] : + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts[226] ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 : + (tagLookup_tagCache_cts[229:228] != 2'd1 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3548 || + tagLookup_tagCache_cts[225]) && + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 || + NOT_SEL_ARR_IF_tagLookup_tagCache_tags_0_readA_ETC___d3563) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3604 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 : + tagLookup_tagCache_cts[229:228] == 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3583 && + !tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3601 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3637 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3632 && + !tagLookup_tagCache_cts[143] || + tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 : + tagLookup_tagCache_cts[229:228] == 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3583 && + !tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 || + NOT_SEL_ARR_IF_tagLookup_tagCache_tags_0_readA_ETC___d3563 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3639 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3572 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530) ? + !SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d3614 || + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 : + tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3575 && + !tagLookup_tagCache_cts[143] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3637 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4102 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3632 && + !tagLookup_tagCache_cts[143] || + tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 : + tagLookup_tagCache_cts[229:228] == 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3583 && + !tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 || + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3553 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3557 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4104 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3572 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530) ? + !SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d3614 || + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 : + tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3575 && + !tagLookup_tagCache_cts[143] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4102 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4112 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 : + tagLookup_tagCache_cts[229:228] == 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3583 && + !tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + (_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3553 || + _16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3557) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4217 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4212 : + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4214 && + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4212 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4230 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3632 && + !tagLookup_tagCache_cts[143]) ? + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 || + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 : + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4229 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4238 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + NOT_SEL_ARR_IF_tagLookup_tagCache_tags_0_readA_ETC___d4234 : + tagLookup_tagCache_cts[229:228] == 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3676 && + !tagLookup_tagCache_cts[225] ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4241 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4238 : + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4238 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4243 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 : + tagLookup_tagCache_cts[229:228] == 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3583 && + !tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3746 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4284 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4283 : + x_addr_tag__h102720 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4285 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3632 && + !tagLookup_tagCache_cts[143]) ? + x_addr_tag__h102720 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4284 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4294 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d4286 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4293 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4306 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + x_addr_tag__h102720 : + (tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4120 ? + IF_NOT_tagLookup_tagCache_cts_read__795_BIT_22_ETC___d4304 : + y_avValue_snd_snd_snd_newTag_tag__h121536) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4322 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3632 && + !tagLookup_tagCache_cts[143]) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + (_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 || + _16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619) : + tagLookup_tagCache_cts[229:228] != 2'd1 || + !tagLookup_tagCache_cts[225] && !tagLookup_tagCache_cts[226] || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 || + _0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 || + _16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4335 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4334 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4391 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025 : + ((tagLookup_tagCache_cts[229:228] == 2'd1) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4393 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4395 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4391 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4394 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4401 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027 : + ((tagLookup_tagCache_cts[229:228] == 2'd1) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4403 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4405 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4401 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4404 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4412 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030 : + ((tagLookup_tagCache_cts[229:228] == 2'd1) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4414 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4416 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4412 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4415 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4422 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032 : + ((tagLookup_tagCache_cts[229:228] == 2'd1) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4424 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4426 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4422 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4425 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4433 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035 : + ((tagLookup_tagCache_cts[229:228] == 2'd1) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4435 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4437 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4433 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4436 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4443 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037 : + ((tagLookup_tagCache_cts[229:228] == 2'd1) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4445 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4447 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4443 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4446 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4454 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040 : + ((tagLookup_tagCache_cts[229:228] == 2'd1) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4456 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4458 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4454 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4457 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4464 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 : + ((tagLookup_tagCache_cts[229:228] == 2'd1) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4466 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4468 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4464 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4467 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4481 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 } : + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 } ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4483 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + { IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4391, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4401, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4412, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4422, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4433, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4443, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4454, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4464 } : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4482 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4487 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 } : + IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4486 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4497 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + (SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4047 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509) : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4047 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4498 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3632 && + !tagLookup_tagCache_cts[143]) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4047 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4497 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4501 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4498 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4500 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4592 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055 : + ((tagLookup_tagCache_cts[229:228] == 2'd1) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4594 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4596 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4592 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4595 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4601 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063 : + ((tagLookup_tagCache_cts[229:228] == 2'd1) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4603 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4605 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4601 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4604 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4611 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072 : + ((tagLookup_tagCache_cts[229:228] == 2'd1) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4613 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4615 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4611 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4614 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4620 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 : + ((tagLookup_tagCache_cts[229:228] == 2'd1) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4622 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4624 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4620 : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4623 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4633 = + (tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) ? + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 } : + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 } ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4635 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + { IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4592, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4601, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4611, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4620 } : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4634 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4640 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 } : + (tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4120 ? + IF_NOT_tagLookup_tagCache_cts_read__795_BIT_22_ETC___d4590 : + IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4638) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4670 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + tagLookup_tagCache_readReqReg[66] : + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4668 : + tagLookup_tagCache_readReqReg[66]) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4686 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + tagLookup_tagCache_cts[236:231] : + tagLookup_tagCache_readReqReg[57:52] ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4689 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + tagLookup_tagCache_readReqReg[57:52] : + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4687 : + tagLookup_tagCache_readReqReg[57:52]) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4739 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4120 ? + !tagLookup_tagCache_cts[225] && !tagLookup_tagCache_cts[226] && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4733 : + tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3676 && + !tagLookup_tagCache_cts[143] || + tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4759 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + tagLookup_tagCache_readReqReg[51] : + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4757 : + tagLookup_tagCache_readReqReg[51]) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4768 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + { tagLookup_tagCache_cts[236], + tagLookup_tagCache_orderer_mastReqIds_rf[4:0] } : + tagLookup_tagCache_readReqReg[50:45] ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4771 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + tagLookup_tagCache_readReqReg[50:45] : + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4769 : + tagLookup_tagCache_readReqReg[50:45]) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4776 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 : + tagLookup_tagCache_readReqReg[44] ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4779 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + tagLookup_tagCache_readReqReg[44] : + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4777 : + tagLookup_tagCache_readReqReg[44]) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4785 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_IF_tagLookup_tagCache_cts_read__795_BITS_22_ETC___d4286 : + tagLookup_tagCache_readReqReg[43:17] ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4788 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + tagLookup_tagCache_readReqReg[43:17] : + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4786 : + tagLookup_tagCache_readReqReg[43:17]) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4792 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 : + tagLookup_tagCache_readReqReg[16] ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4795 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + tagLookup_tagCache_readReqReg[16] : + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4793 : + tagLookup_tagCache_readReqReg[16]) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4804 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + { IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4391, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4401, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4412, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4422, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4433, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4443, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4454, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4464, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4498, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4592, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4601, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4611, + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4620 } : + tagLookup_tagCache_readReqReg[15:3] ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4807 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + tagLookup_tagCache_readReqReg[15:3] : + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + IF_NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read___ETC___d4805 : + tagLookup_tagCache_readReqReg[15:3]) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4934 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4930, + tagLookup_tagCache_cts[229:228] == 2'd1 } : + tagLookup_tagCache_readReqReg[1:0] ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4994 = + { tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4956 ? + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4712 : + tagLookup_mRsps_ff_rf$D_OUT_1[66], + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4991 && + tagLookup_mRsps_ff_rf$D_OUT_1[65] } ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d5000 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3676 && + !tagLookup_tagCache_cts[143]) ? + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4708 : + tagLookup_mRsps_ff_rf$D_OUT_1[66] ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d3753 = + (tagLookup_tagCache_cts[278:277] == 2'd1) ? + { 21'd851967, + CASE_tagLookup_tagCache_cts_BITS_100_TO_99_0_t_ETC__q16, + cacheResp_data_data__h284964, + 8'd0 } : + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d3752 ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4643 = + { IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4490, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q21, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4642 } ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4811 = + { CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q23, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q24 } ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4942 = + { CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q25, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4811, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q26 } ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4943 = + { CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q27, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q28, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4942 } ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4944 = + { CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q29, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q30, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4943 } ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5032 = + ((tagLookup_tagCache_cts[278:277] == 2'd2) ? + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d5017 : + tagLookup_tagCache_cts[278:277] != 2'd0 || + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d5022) ? + 4'd6 : + { 3'd4, + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q31 } ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5036 = + (tagLookup_tagCache_cts[278:277] == 2'd2) ? + tagLookup_mRsps_ff_rf$D_OUT_1[64:0] : + { SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d4542, + cacheResp_data_data__h284964 } ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5052 = + (tagLookup_tagCache_cts[278:277] == 2'd2) ? + (NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4991 || + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d4698) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4705 : + tagLookup_tagCache_cts[278:277] == 2'd0 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4732 && + (tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4724 || + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4740) ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5077 = + { CASE_tagLookup_tagCache_cts_BITS_278_TO_277_1__ETC__q22, + tagLookup_tagCache_cts[278:277] != 2'd1 && + ((tagLookup_tagCache_cts[278:277] == 2'd2) ? + (NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4991 || + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d4698) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4705 && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4712 : + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d5072), + tagLookup_tagCache_cts[80] && + tagLookup_tagCache_cts[276:237] == + tagLookup_tagCache_cts[135:96] } ; + assign IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5078 = + { CASE_tagLookup_tagCache_cts_BITS_278_TO_277_1__ETC__q33, + tagLookup_tagCache_cts[278:277] != 2'd1 && + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5052, + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d5077 } ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_217_18_ETC___d4187 = + tagLookup_tagCache_cts[217] ? + x__h120092 | y__h120093 : + cacheResp_data_data__h284964[7:0] ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_218_17_ETC___d4180 = + tagLookup_tagCache_cts[218] ? + x__h119953 | y__h119954 : + cacheResp_data_data__h284964[15:8] ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_219_16_ETC___d4172 = + tagLookup_tagCache_cts[219] ? + x__h119814 | y__h119815 : + cacheResp_data_data__h284964[23:16] ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_220_15_ETC___d4165 = + tagLookup_tagCache_cts[220] ? + x__h119675 | y__h119676 : + cacheResp_data_data__h284964[31:24] ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_221_15_ETC___d4157 = + tagLookup_tagCache_cts[221] ? + x__h119536 | y__h119537 : + cacheResp_data_data__h284964[39:32] ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_222_14_ETC___d4150 = + tagLookup_tagCache_cts[222] ? + x__h119397 | y__h119398 : + cacheResp_data_data__h284964[47:40] ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_223_13_ETC___d4142 = + tagLookup_tagCache_cts[223] ? + x__h119258 | y__h119259 : + cacheResp_data_data__h284964[55:48] ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_224_12_ETC___d4135 = + tagLookup_tagCache_cts[224] ? + x__h118925 | y__h118926 : + cacheResp_data_data__h284964[63:56] ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4299 = + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544) ? + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4283 : + x_addr_tag__h102720 ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4567 = + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 : + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3583 || + !tagLookup_tagCache_cts[226] && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + (_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3553 || + _16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3557) ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4568 = + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055 ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4573 = + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063 ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4579 = + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072 ; + assign IF_tagLookup_tagCache_cts_read__795_BIT_225_54_ETC___d4584 = + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 ; + assign IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d2892 = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReqwget_BITS_140_TO_101__q20[12:3] : + { tagLookup_tagCache_cts[249:242], + IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2890 } ; + assign IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d2975 = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReq$wget[93:92] != 2'd0 && + tagLookup_tagCache_newReq$wget[93:92] != 2'd1 : + tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 ; + assign IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3020 = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141] || + tagLookup_mRsps_ff_lhead_read__894_MINUS_tagLo_ETC___d2965) ? + (IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d2975 ? + IF_IF_tagLookup_tagCache_newReq_whas__787_AND__ETC___d2980 : + 2'd0) : + IF_NOT_tagLookup_mRsps_ff_lhead_read__894_MINU_ETC___d3019 ; + assign IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3047 = + { x__h78979, + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReq$wget[94] : + tagLookup_tagCache_cts[230], + IF_IF_tagLookup_tagCache_newReq_whas__787_AND__ETC___d3046 } ; + assign IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3048 = + { (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReq$wget[140:101] : + tagLookup_tagCache_cts[276:237], + x__h78976, + IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3047 } ; + assign IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3054 = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReq$wget[140:101] : + { tagLookup_tagCache_cts[276:242], + IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2890, + tagLookup_tagCache_cts[239:237] } ; + assign IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3130 = + { tagLookup_tagCache_cts[79:44], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[43], + IF_tagLookup_tagCache_writebacks_i_notEmpty__8_ETC___d3127, + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + 2'd0 : + tagLookup_tagCache_cts[1:0] } ; + assign IF_tagLookup_tagCache_newReq_whas__787_THEN_ta_ETC___d2826 = + tagLookup_tagCache_newReqwget_BITS_140_TO_101__q20[4:3] + 2'd1 ; + assign IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2857 = + (tagLookup_tagCache_orderer_lookupState[12] && + tagLookup_tagCache_cts[236] == + tagLookup_tagCache_orderer_lookupState[11] && + tagLookup_tagCache_cts[235:231] == + tagLookup_tagCache_orderer_lookupState[10:6]) ? + tagLookup_tagCache_orderer_lookupState[1:0] : + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d2856 ; + assign IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2870 = + IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2857 + + 2'd1 ; + assign IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2890 = + (tagLookup_tagCache_orderer_lookupState[12] || + !tagLookup_tagCache_nextEmpty || + tagLookup_tagCache_cts[80]) ? + IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2857 : + tagLookup_tagCache_cts[241:240] ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2083 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1466 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1471) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640, + tagLookup_tagCache_orderer_mastLines_bag[670:630] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2086 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1475 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1478) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654, + tagLookup_tagCache_orderer_mastLines_bag[628:588] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2090 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1482 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1485) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678, + tagLookup_tagCache_orderer_mastLines_bag[586:546] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2093 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1489 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1492) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702, + tagLookup_tagCache_orderer_mastLines_bag[544:504] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2097 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1496 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1499) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728, + tagLookup_tagCache_orderer_mastLines_bag[502:462] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2100 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1503 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1506) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754, + tagLookup_tagCache_orderer_mastLines_bag[460:420] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2104 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1510 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1513) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782, + tagLookup_tagCache_orderer_mastLines_bag[418:378] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2107 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1517 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1520) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810, + tagLookup_tagCache_orderer_mastLines_bag[376:336] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2111 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1524 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1527) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840, + tagLookup_tagCache_orderer_mastLines_bag[334:294] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2114 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1531 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1534) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870, + tagLookup_tagCache_orderer_mastLines_bag[292:252] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2118 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1538 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1541) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902, + tagLookup_tagCache_orderer_mastLines_bag[250:210] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2121 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1545 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1548) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934, + tagLookup_tagCache_orderer_mastLines_bag[208:168] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2125 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1552 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1555) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1968, + tagLookup_tagCache_orderer_mastLines_bag[166:126] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2128 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1559 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1562) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2002, + tagLookup_tagCache_orderer_mastLines_bag[124:84] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2132 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1566 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1569) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2038, + tagLookup_tagCache_orderer_mastLines_bag[82:42] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2135 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1573 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1576) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41], + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40:0] } : + { NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2069, + tagLookup_tagCache_orderer_mastLines_bag[40:0] } ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2201 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + !_0_CONCAT_tagLookup_tagCache_orderer_mastLines__ETC___d2188 && + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 : + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1573 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1576) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2069 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1566 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1569) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2038 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1559 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1562) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2002 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1552 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1555) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1968 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1545 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1548) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1538 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1541) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1531 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1534) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1524 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1527) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1517 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1520) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1510 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1513) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1503 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1506) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1496 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1499) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1489 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1492) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1482 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1485) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1475 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1478) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1466 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1471) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] : + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2315 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + (_0_CONCAT_tagLookup_tagCache_orderer_mastLines__ETC___d2188 ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313) : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2338 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + { 28'd0, _theResult_____1__h43323 } != + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187 && + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 : + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2369 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + (tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2366) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2019 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2172 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2383 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2381 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1984 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2170 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2408 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + (tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2402) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1918 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2166 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2419 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + (tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2414) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1887 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2164 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2438 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + (tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2435) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2160 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2446 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2444 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2158 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2459 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + (tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2154 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2464 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + (tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2152 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2471 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + (tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2148 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2473 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 : + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2146 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2478 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2477 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2483 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2482 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2496 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2495 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2504 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2503 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2523 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2520 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2522 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2534 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2530 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2533 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2559 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2553 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2558 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2573 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2566 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2572 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2604 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2601 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2002 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2603 ; + assign IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2621 = + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2617 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2038 : + tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2620 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3251 = + (tagLookup_tagCache_orderer_mastReqs_bag[176] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3234 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3235) ? + tagLookup_tagCache_orderer_mastReqs_bag[128:127] : + ((tagLookup_tagCache_orderer_mastReqs_bag[117] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3239 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3240) ? + tagLookup_tagCache_orderer_mastReqs_bag[69:68] : + tagLookup_tagCache_orderer_mastReqs_bag[10:9]) ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3252 = + (tagLookup_tagCache_orderer_mastReqs_bag[235] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3229 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3230) ? + tagLookup_tagCache_orderer_mastReqs_bag[187:186] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3251 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3253 = + (tagLookup_tagCache_orderer_mastReqs_bag[294] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3224 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3225) ? + tagLookup_tagCache_orderer_mastReqs_bag[246:245] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3252 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3254 = + (tagLookup_tagCache_orderer_mastReqs_bag[353] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3219 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3220) ? + tagLookup_tagCache_orderer_mastReqs_bag[305:304] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3253 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3255 = + (tagLookup_tagCache_orderer_mastReqs_bag[412] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3214 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3215) ? + tagLookup_tagCache_orderer_mastReqs_bag[364:363] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3254 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3256 = + (tagLookup_tagCache_orderer_mastReqs_bag[471] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3209 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3210) ? + tagLookup_tagCache_orderer_mastReqs_bag[423:422] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3255 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3257 = + (tagLookup_tagCache_orderer_mastReqs_bag[530] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3204 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3205) ? + tagLookup_tagCache_orderer_mastReqs_bag[482:481] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3256 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3258 = + (tagLookup_tagCache_orderer_mastReqs_bag[589] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3199 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3200) ? + tagLookup_tagCache_orderer_mastReqs_bag[541:540] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3257 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3259 = + (tagLookup_tagCache_orderer_mastReqs_bag[648] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3194 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3195) ? + tagLookup_tagCache_orderer_mastReqs_bag[600:599] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3258 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3260 = + (tagLookup_tagCache_orderer_mastReqs_bag[707] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3189 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3190) ? + tagLookup_tagCache_orderer_mastReqs_bag[659:658] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3259 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3261 = + (tagLookup_tagCache_orderer_mastReqs_bag[766] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3184 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3185) ? + tagLookup_tagCache_orderer_mastReqs_bag[718:717] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3260 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3262 = + (tagLookup_tagCache_orderer_mastReqs_bag[825] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3179 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3180) ? + tagLookup_tagCache_orderer_mastReqs_bag[777:776] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3261 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3263 = + (tagLookup_tagCache_orderer_mastReqs_bag[884] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3174 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3175) ? + tagLookup_tagCache_orderer_mastReqs_bag[836:835] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3262 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3264 = + (tagLookup_tagCache_orderer_mastReqs_bag[943] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3169 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3170) ? + tagLookup_tagCache_orderer_mastReqs_bag[895:894] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3263 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3333 = + (tagLookup_tagCache_orderer_mastReqs_bag[176] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3234 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3235) ? + tagLookup_tagCache_orderer_mastReqs_bag[126:125] : + ((tagLookup_tagCache_orderer_mastReqs_bag[117] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3239 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3240) ? + tagLookup_tagCache_orderer_mastReqs_bag[67:66] : + tagLookup_tagCache_orderer_mastReqs_bag[8:7]) ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3334 = + (tagLookup_tagCache_orderer_mastReqs_bag[235] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3229 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3230) ? + tagLookup_tagCache_orderer_mastReqs_bag[185:184] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3333 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3335 = + (tagLookup_tagCache_orderer_mastReqs_bag[294] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3224 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3225) ? + tagLookup_tagCache_orderer_mastReqs_bag[244:243] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3334 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3336 = + (tagLookup_tagCache_orderer_mastReqs_bag[353] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3219 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3220) ? + tagLookup_tagCache_orderer_mastReqs_bag[303:302] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3335 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3337 = + (tagLookup_tagCache_orderer_mastReqs_bag[412] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3214 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3215) ? + tagLookup_tagCache_orderer_mastReqs_bag[362:361] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3336 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3338 = + (tagLookup_tagCache_orderer_mastReqs_bag[471] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3209 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3210) ? + tagLookup_tagCache_orderer_mastReqs_bag[421:420] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3337 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3339 = + (tagLookup_tagCache_orderer_mastReqs_bag[530] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3204 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3205) ? + tagLookup_tagCache_orderer_mastReqs_bag[480:479] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3338 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3340 = + (tagLookup_tagCache_orderer_mastReqs_bag[589] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3199 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3200) ? + tagLookup_tagCache_orderer_mastReqs_bag[539:538] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3339 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3341 = + (tagLookup_tagCache_orderer_mastReqs_bag[648] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3194 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3195) ? + tagLookup_tagCache_orderer_mastReqs_bag[598:597] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3340 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3342 = + (tagLookup_tagCache_orderer_mastReqs_bag[707] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3189 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3190) ? + tagLookup_tagCache_orderer_mastReqs_bag[657:656] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3341 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3343 = + (tagLookup_tagCache_orderer_mastReqs_bag[766] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3184 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3185) ? + tagLookup_tagCache_orderer_mastReqs_bag[716:715] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3342 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3344 = + (tagLookup_tagCache_orderer_mastReqs_bag[825] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3179 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3180) ? + tagLookup_tagCache_orderer_mastReqs_bag[775:774] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3343 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3345 = + (tagLookup_tagCache_orderer_mastReqs_bag[884] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3174 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3175) ? + tagLookup_tagCache_orderer_mastReqs_bag[834:833] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3344 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3346 = + (tagLookup_tagCache_orderer_mastReqs_bag[943] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3169 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3170) ? + tagLookup_tagCache_orderer_mastReqs_bag[893:892] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3345 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1030 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + !_0_CONCAT_tagLookup_tagCache_orderer_mastReqs_n_ETC___d1017 && + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 : + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d382 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d385) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d898 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d375 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d378) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d867 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d368 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d371) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d831 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d361 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d364) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d797 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d354 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d357) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d347 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d350) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d340 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d343) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d333 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d336) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d326 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d329) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d319 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d322) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d312 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d315) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d305 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d308) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d298 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d301) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d291 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d294) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d284 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d287) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d275 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d280) ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] : + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1144 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + (_0_CONCAT_tagLookup_tagCache_orderer_mastReqs_n_ETC___d1017 ? + tagLookup_tagCache_orderer_mastReqs_insertItem$whas : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142) : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1167 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + { 28'd0, _theResult_____1__h31534 } != + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016 && + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 : + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1198 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + (tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1195) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d848 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1001 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1212 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1210 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d813 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d999 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1237 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + (tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1231) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d747 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d995 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1248 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + (tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1243) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d993 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1267 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + (tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1264) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d989 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1275 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1273 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d987 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1288 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + (tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d983 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1293 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + (tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d981 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1300 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + (tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d977 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1302 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 : + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d975 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1307 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1306 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1312 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1311 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1325 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1324 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1333 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1332 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1352 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1349 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1351 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1363 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1359 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1362 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1388 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1382 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1387 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1402 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1395 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1401 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1433 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1430 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d831 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1432 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1450 = + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1446 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d867 : + tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1449 ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d912 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d275 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d280) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469, + tagLookup_tagCache_orderer_mastReqs_bag[942:885] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d915 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d284 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d287) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483, + tagLookup_tagCache_orderer_mastReqs_bag[883:826] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d919 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d291 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d294) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507, + tagLookup_tagCache_orderer_mastReqs_bag[824:767] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d922 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d298 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d301) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531, + tagLookup_tagCache_orderer_mastReqs_bag[765:708] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d926 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d305 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d308) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557, + tagLookup_tagCache_orderer_mastReqs_bag[706:649] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d929 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d312 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d315) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583, + tagLookup_tagCache_orderer_mastReqs_bag[647:590] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d933 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d319 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d322) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611, + tagLookup_tagCache_orderer_mastReqs_bag[588:531] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d936 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d326 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d329) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639, + tagLookup_tagCache_orderer_mastReqs_bag[529:472] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d940 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d333 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d336) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669, + tagLookup_tagCache_orderer_mastReqs_bag[470:413] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d943 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d340 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d343) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699, + tagLookup_tagCache_orderer_mastReqs_bag[411:354] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d947 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d347 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d350) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731, + tagLookup_tagCache_orderer_mastReqs_bag[352:295] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d950 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d354 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d357) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763, + tagLookup_tagCache_orderer_mastReqs_bag[293:236] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d954 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d361 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d364) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d797, + tagLookup_tagCache_orderer_mastReqs_bag[234:177] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d957 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d368 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d371) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d831, + tagLookup_tagCache_orderer_mastReqs_bag[175:118] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d961 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d375 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d378) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d867, + tagLookup_tagCache_orderer_mastReqs_bag[116:59] } ; + assign IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d964 = + (tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d382 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d385) ? + { tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58], + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57:0] } : + { NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d898, + tagLookup_tagCache_orderer_mastReqs_bag[57:0] } ; + assign IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3265 = + tagLookup_tagCache_orderer_mastRespState[12] ? + tagLookup_tagCache_orderer_mastRespState[1:0] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3264 ; + assign IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3266 = + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3265 == + tagLookup_tagCache_orderer_slaveRespState[1:0] ; + assign IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3272 = + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3265 == + tagLookup_tagCache_orderer_slaveReqs_bag[10:9] ; + assign IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3349 = + { tagLookup_tagCache_orderer_mastRespState[12] ? + tagLookup_tagCache_orderer_mastRespState[5:4] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3264, + tagLookup_tagCache_orderer_mastRespState[12] ? + tagLookup_tagCache_orderer_mastRespState[3:2] : + IF_tagLookup_tagCache_orderer_mastReqs_bag_71__ETC___d3346, + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3265 + + 2'd1 } ; + assign IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2820 = + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2810 ? + tagLookup_tagCache_orderer_slaveReqs_bag[8:7] : + tagLookup_tagCache_newReqwget_BITS_140_TO_101__q20[4:3] + + IF_CAN_FIRE_RL_tagLookup_feedTagCache_AND_tagL_ETC__q39[1:0] ; + assign IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2825 = + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2810 ? + tagLookup_tagCache_orderer_slaveReqs_bag[10:9] : + tagLookup_tagCache_newReqwget_BITS_140_TO_101__q20[4:3] ; + assign IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2829 = + { IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2825, + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2820, + (IF_tagLookup_tagCache_newReq_whas__787_THEN_ta_ETC___d2826 <= + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2820) ? + IF_tagLookup_tagCache_newReq_whas__787_THEN_ta_ETC___d2826 : + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2825 } ; + assign IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2855 = + (tagLookup_tagCache_orderer_slaveReqs_bag[58] && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2849 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2850) ? + tagLookup_tagCache_orderer_slaveReqs_bag[10:9] : + tagLookup_tagCache_cts[241:240] ; + assign IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2865 = + (tagLookup_tagCache_orderer_slaveReqs_bag[58] && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2849 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2850) ? + tagLookup_tagCache_orderer_slaveReqs_bag[8:7] : + IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2857 + + IF_tagLookup_tagCache_cts_BITS_229_TO_228_EQ_0_ETC__q4[1:0] ; + assign IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2869 = + (tagLookup_tagCache_orderer_slaveReqs_bag[58] && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2849 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2850) ? + tagLookup_tagCache_orderer_slaveReqs_bag[10:9] : + IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2857 ; + assign IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2873 = + { IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2869, + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2865, + (IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2870 <= + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2865) ? + IF_tagLookup_tagCache_orderer_lookupState_read_ETC___d2870 : + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2869 } ; + assign IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d4762 = + (tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4732 && + (tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4724 || + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4740)) ? + (tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4708 ? + tagLookup_tagCache_cts_read__795_BIT_236_831_E_ETC___d4760 : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4759) : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4759 ; + assign IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d5005 = + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4724 ? + { (tagLookup_tagCache_cts[229:228] == 2'd0) ? + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4708 : + tagLookup_mRsps_ff_rf$D_OUT_1[66], + tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_mRsps_ff_rf$D_OUT_1[65] } : + IF_NOT_tagLookup_tagCache_orderer_slaveReqs_ba_ETC___d5004 ; + assign IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d5022 = + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4724 ? + tagLookup_tagCache_cts[229:228] != 2'd0 && + (tagLookup_tagCache_cts[229:228] != 2'd1 || + !tagLookup_tagCache_cts[225]) : + NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d5021 ; + assign IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d5028 = + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4724 ? + (tagLookup_tagCache_cts[229:228] != 2'd1 || + !tagLookup_tagCache_cts[225]) && + tagLookup_mRsps_ff_rf$D_OUT_1[65] : + tagLookup_mRsps_ff_rf$D_OUT_1[65] ; + assign IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d2856 = + (tagLookup_tagCache_orderer_slaveRespState[12] && + tagLookup_tagCache_cts_read__795_BIT_236_831_E_ETC___d2843 && + tagLookup_tagCache_cts_read__795_BITS_235_TO_2_ETC___d2845) ? + tagLookup_tagCache_orderer_slaveRespState[1:0] : + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d2855 ; + assign IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3274 = + tagLookup_tagCache_orderer_slaveRespState[12] ? + tagLookup_tagCache_readReqReg_read__136_BIT_57_ETC___d3162 && + tagLookup_tagCache_readReqReg_read__136_BITS_5_ETC___d3164 && + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3266 : + tagLookup_tagCache_orderer_slaveReqs_bag[58] && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3268 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3269 && + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3272 ; + assign IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3503 = + tagLookup_tagCache_orderer_slaveRespState[12] ? + tagLookup_tagCache_cts_read__795_BIT_236_831_E_ETC___d2843 && + tagLookup_tagCache_cts_read__795_BITS_235_TO_2_ETC___d2845 && + tagLookup_tagCache_cts_read__795_BITS_100_TO_9_ETC___d3499 : + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2849 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2850 && + tagLookup_tagCache_cts_read__795_BITS_100_TO_9_ETC___d3501 ; + assign IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3561 = + tagLookup_tagCache_orderer_slaveRespState[12] ? + tagLookup_tagCache_cts_read__795_BIT_236_831_E_ETC___d2843 && + tagLookup_tagCache_cts_read__795_BITS_235_TO_2_ETC___d2845 && + tagLookup_tagCache_cts_read__795_BITS_100_TO_9_ETC___d3499 : + tagLookup_tagCache_orderer_slaveReqs_bag[58] && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2849 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2850 && + tagLookup_tagCache_cts_read__795_BITS_100_TO_9_ETC___d3501 ; + assign IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3599 = + tagLookup_tagCache_orderer_slaveRespState[12] ? + !tagLookup_tagCache_cts_read__795_BIT_236_831_E_ETC___d2843 || + !tagLookup_tagCache_cts_read__795_BITS_235_TO_2_ETC___d2845 || + !tagLookup_tagCache_cts_read__795_BITS_100_TO_9_ETC___d3499 : + !tagLookup_tagCache_orderer_slaveReqs_bag[58] || + !tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2849 || + !tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2850 || + !tagLookup_tagCache_cts_read__795_BITS_100_TO_9_ETC___d3501 ; + assign IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3744 = + tagLookup_tagCache_orderer_slaveRespState[12] ? + !tagLookup_tagCache_cts_read__795_BIT_236_831_E_ETC___d2843 || + !tagLookup_tagCache_cts_read__795_BITS_235_TO_2_ETC___d2845 || + !tagLookup_tagCache_cts_read__795_BITS_100_TO_9_ETC___d3499 : + !tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2849 || + !tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2850 || + !tagLookup_tagCache_cts_read__795_BITS_100_TO_9_ETC___d3501 ; + assign IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d4248 = + (IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3561 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4117 || + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4219) && + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4233 || + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4246) ; + assign IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d4658 = + tagLookup_tagCache_orderer_slaveRespState[12] ? + !tagLookup_tagCache_readReqReg_read__136_BIT_57_ETC___d3162 || + !tagLookup_tagCache_readReqReg_read__136_BITS_5_ETC___d3164 || + !IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3266 : + !tagLookup_tagCache_orderer_slaveReqs_bag[58] || + !tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3268 || + !tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3269 || + !IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3272 ; + assign IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d3970 = + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66]) ? + tagLookup_tagCache_readReqReg[44] : + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 ; + assign IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d3979 = + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66]) ? + { tagLookup_tagCache_readReqReg[65:58], + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3265 } : + tagLookup_tagCache_cts[92:83] ; + assign IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4192 = + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66]) ? + tagLookup_tagCache_readReqReg[7] : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4047 ; + assign IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4263 = + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66]) ? + tagLookup_tagCache_readReqReg[43:17] : + x_addr_tag__h102720 ; + assign IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4311 = + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66]) ? + tagLookup_tagCache_readReqReg[16] : + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 ; + assign IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4363 = + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66]) ? + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3265 : + tagLookup_tagCache_cts[100:99] ; + assign IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4386 = + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66]) ? + tagLookup_tagCache_readReqReg[15:8] : + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 } ; + assign IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4511 = + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66]) ? + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3265 : + tagLookup_tagCache_cts[84:83] ; + assign IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4531 = + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66]) ? + tagLookup_tagCache_readReqReg[6:3] : + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 } ; + assign IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4665 = + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66]) ? + ((tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + !tagLookup_mRsps_ff_rf$D_OUT_1[66] : + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4661 && + tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps_ff_l_ETC___d4662) : + tagLookup_tagCache_readReqReg[66] ; + assign IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4710 = + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66]) ? + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 || + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 || + tagLookup_mRsps_ff_rf$D_OUT_1[66] : + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4708 ; + assign IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d5013 = + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66]) ? + ((tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0 || + tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps_ff_l_ETC___d3946) ? + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 : + tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps_ff_l_ETC___d4662 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1) : + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 ; + assign IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d5042 = + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66]) ? + tagLookup_tagCache_readReqReg[57:52] : + tagLookup_tagCache_cts[236:231] ; + assign IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3465 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[5] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[5] ; + assign IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3468 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[6] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[6] ; + assign IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3471 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[7] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[7] ; + assign IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3474 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[8] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[8] ; + assign IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4050 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[3] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[3] ; + assign IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4058 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[2] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[2] ; + assign IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4067 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[1] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[1] ; + assign IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4075 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[0] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[0] ; + assign IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3431 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[5] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[5] ; + assign IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3434 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[6] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[6] ; + assign IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3437 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[7] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[7] ; + assign IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3440 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[8] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[8] ; + assign IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4053 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[3] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[3] ; + assign IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4061 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[2] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[2] ; + assign IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4070 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[1] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[1] ; + assign IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4078 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[0] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[0] ; + assign IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[i__h301909] ; + assign IF_tagLookup_tagCache_writebacks_i_notEmpty__8_ETC___d2893 = + tagLookup_tagCache_writebacks$EMPTY_N ? + { tagLookup_tagCache_writebacks$D_OUT[61:54], + tagLookup_tagCache_writebackWriteBank } : + IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d2892 ; + assign IF_tagLookup_tagCache_writebacks_i_notEmpty__8_ETC___d3055 = + tagLookup_tagCache_writebacks$EMPTY_N ? + { tagLookup_tagCache_writebacks$D_OUT[88:54], + tagLookup_tagCache_writebackWriteBank, + tagLookup_tagCache_writebacks$D_OUT[51:49] } : + IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d3054 ; + assign IF_tagLookup_tagCache_writebacks_i_notEmpty__8_ETC___d3127 = + tagLookup_tagCache_writebacks$EMPTY_N ? + tagLookup_tagCache_writebacks$D_OUT[48:8] : + { x1_avValue_snd_writebackTag_tag__h81268, + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[15], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[14], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[13], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[12], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[11], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[10], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[9], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[8], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[7], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[6], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[5], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[4], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[3], + (!CAN_FIRE_RL_tagLookup_feedTagCache || + !tagLookup_tagCache_newReq$wget[141]) && + tagLookup_tagCache_cts[2] } ; + assign IF_tagOnlyReads_lhead_read__990_MINUS_tagOnlyR_ETC___d6187 = + (tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 && + frame == 3'd0) ? + tagOnlyReads_rf : + mRsps_ff_rf$D_OUT_1[76:71] ; + assign IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5922 = + (writeBuffer_ff_rf$D_OUT_1[93:92] == 2'd0) ? + !writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5907 && + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5909 || + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5911 || + !writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5912 : + writeBuffer_ff_rf$D_OUT_1[93:92] != 2'd1 || + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5920 ; + assign IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5941 = + (writeBuffer_ff_rf$D_OUT_1[93:92] == 2'd0) ? + (writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5907 || + !writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5909) && + !writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5911 && + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5912 : + writeBuffer_ff_rf$D_OUT_1[93:92] == 2'd1 && + NOT_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_ETC___d5939 ; + assign NOT_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead__ETC___d4007 = + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3553 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3557 && + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3561 && + SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d3614 && + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 ; + assign NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read__351_ETC___d4092 = + x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0 && + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 ; + assign NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read__351_ETC___d4107 = + x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0 && + !tagLookup_tagCache_readReqReg[66] && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4105 ; + assign NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read__351_ETC___d4676 = + x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0 && + (IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3561 || + tagLookup_tagCache_cts[229:228] == 2'd0) && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3607 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3640 ; + assign NOT_SEL_ARR_IF_tagLookup_tagCache_tags_0_readA_ETC___d3563 = + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 || + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3553 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3557 && + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3561 ; + assign NOT_SEL_ARR_IF_tagLookup_tagCache_tags_0_readA_ETC___d4234 = + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) ; + assign NOT_SEL_ARR_NOT_tagLookup_tagCache_req_commits_ETC___d4094 = + !SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 && + !tagLookup_tagCache_cts[230] && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4086 && + !tagLookup_tagCache_invalidateWritebacks$EMPTY_N && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 && + NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read__351_ETC___d4092 ; + assign NOT_SEL_ARR_NOT_tagLookup_tagCache_req_commits_ETC___d4124 = + !SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 && + !tagLookup_tagCache_cts[230] && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4086 && + !tagLookup_tagCache_invalidateWritebacks$EMPTY_N && + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4120 && + !tagLookup_tagCache_cts[225] && + NOT_tagLookup_tagCache_cts_read__795_BIT_226_5_ETC___d4121 ; + assign NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3151 = + level__h1463 != 2'd0 && + (!tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 || + !tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 || + !tagLookup_tagCache_readReqReg[66]) ; + assign NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 = + level__h1463 != 2'd0 && + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66] ; + assign NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d4203 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 && + ((IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 : + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 && + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193) ; + assign NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d4698 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 && + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3274 && + !tagLookup_tagCache_readReqReg[51] && + x_port1__read__h92294 != 5'd0 ; + assign NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d3297 = + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 && + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3274 && + !tagLookup_tagCache_readReqReg[51] && + x_port1__read__h92294 != 5'd0 ; + assign NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d3953 = + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd1 && + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3274 && + !tagLookup_tagCache_readReqReg[51] && + x_port1__read__h92294 != 5'd0 ; + assign NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4354 = + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] != 2'd0 || + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 != + (tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 || + tagLookup_mRsps_ff_rf$D_OUT_1[66]) || + tagLookup_tagCache_readReqReg[15] ; + assign NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4356 = + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] != 2'd0 || + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 != + (tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 || + tagLookup_mRsps_ff_rf$D_OUT_1[66]) || + tagLookup_tagCache_readReqReg[14] ; + assign NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4359 = + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] != 2'd0 || + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 != + (tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 || + tagLookup_mRsps_ff_rf$D_OUT_1[66]) || + tagLookup_tagCache_readReqReg[13] ; + assign NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4361 = + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] != 2'd0 || + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 != + (tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 || + tagLookup_mRsps_ff_rf$D_OUT_1[66]) || + tagLookup_tagCache_readReqReg[12] ; + assign NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4368 = + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] != 2'd0 || + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 != + (tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 || + tagLookup_mRsps_ff_rf$D_OUT_1[66]) || + x__h122813 == 2'd3 || + tagLookup_tagCache_readReqReg[11] ; + assign NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4372 = + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] != 2'd0 || + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 != + (tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 || + tagLookup_mRsps_ff_rf$D_OUT_1[66]) || + x__h122813 == 2'd2 || + tagLookup_tagCache_readReqReg[10] ; + assign NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4377 = + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] != 2'd0 || + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 != + (tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 || + tagLookup_mRsps_ff_rf$D_OUT_1[66]) || + x__h122813 == 2'd1 || + tagLookup_tagCache_readReqReg[9] ; + assign NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4381 = + tagLookup_mRsps_ff_rf$D_OUT_1[70:69] != 2'd0 || + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 != + (tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 || + tagLookup_mRsps_ff_rf$D_OUT_1[66]) || + x__h122813 == 2'd0 || + tagLookup_tagCache_readReqReg[8] ; + assign NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4661 = + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd1 || + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d4658 || + tagLookup_tagCache_readReqReg[51] || + x_port1__read__h92294 == 5'd0 ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3522 = + (!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 || + !SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455) && + (!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) || + !tagLookup_tagCache_cts[143] ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3534 = + (!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 || + !SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455) && + (!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) || + tagLookup_tagCache_cts[144] ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3537 = + (!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 || + !SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455) && + (!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) || + !tagLookup_tagCache_cts[144] ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3548 = + (!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 || + !SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455) && + (!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) || + tagLookup_tagCache_cts[226] ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_143__ETC___d3627 = + tagLookup_tagCache_cts[143:140] != 4'd2 || + NOT_tagLookup_tagCache_cts_read__795_BIT_136_0_ETC___d3625 || + !SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d3614 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 || + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_143__ETC___d4951 = + tagLookup_tagCache_cts[143:140] != 4'd8 || + NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d3016 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3496 || + x_port1__read__h92294 == 5'd0 ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3492 = + tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts[136] || + (!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 || + !SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455) && + (!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3516 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts[143:140] == 4'd3 || + tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts[143:140] == 4'd2 || + !SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 && + !tagLookup_tagCache_cts[230]) && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3511 && + !tagLookup_tagCache_writebacks$EMPTY_N && + !tagLookup_tagCache_invalidateWritebacks$EMPTY_N ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 = + (tagLookup_tagCache_cts[229:228] != 2'd0 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3522 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530) && + (tagLookup_tagCache_cts[229:228] != 2'd0 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3534 || + tagLookup_tagCache_cts[143]) && + (tagLookup_tagCache_cts[229:228] != 2'd0 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3537 || + tagLookup_tagCache_cts[143]) ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4010 = + (tagLookup_tagCache_cts[229:228] != 2'd1 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3548 || + tagLookup_tagCache_cts[225]) && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + NOT_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead__ETC___d4007 ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4013 = + (tagLookup_tagCache_cts[229:228] != 2'd0 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3534 || + tagLookup_tagCache_cts[143]) && + (tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4000 || + (tagLookup_tagCache_cts[229:228] != 2'd0 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3537 || + tagLookup_tagCache_cts[143]) && + (tagLookup_tagCache_cts[229:228] != 2'd1 || + !tagLookup_tagCache_cts[225] && + !tagLookup_tagCache_cts[226]) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4010) ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4017 = + tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts[139:137] == 3'd4 && + tagLookup_tagCache_cts[143:140] != 4'd0 && + tagLookup_tagCache_cts_read__795_BITS_143_TO_1_ETC___d3991 || + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + (tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3997 || + (tagLookup_tagCache_cts[229:228] != 2'd0 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3522 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4013) ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4214 = + (tagLookup_tagCache_cts[229:228] != 2'd0 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3522 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530) && + (tagLookup_tagCache_cts[229:228] != 2'd0 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3534 || + tagLookup_tagCache_cts[143]) ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4250 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts[143:140] == 4'd3 || + tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts[143:140] == 4'd2 || + !SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 && + !tagLookup_tagCache_cts[230]) && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3511 && + !tagLookup_tagCache_writebacks$EMPTY_N && + !tagLookup_tagCache_invalidateWritebacks$EMPTY_N && + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d4248 ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4324 = + (tagLookup_tagCache_cts[229:228] != 2'd0 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3522 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530) && + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3575 && + !tagLookup_tagCache_cts[143] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4322) ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4697 = + tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_143_TO_1_ETC___d4693 || + level__h1463 != 2'd0 && + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66] && + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d3297 ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4705 = + tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_143_TO_1_ETC___d4693 || + level__h1463 == 2'd0 || + !tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 || + !tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 || + !tagLookup_tagCache_readReqReg[66] || + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 || + !tagLookup_tagCache_readReqReg[0] ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4712 = + tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_143_TO_1_ETC___d4693 || + ((level__h1463 == 2'd0) ? + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4708 : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4710) ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4756 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3582 || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4243) && + tagLookup_tagCache_readReqReg[51] ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4991 = + tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_143_TO_1_ETC___d4693 || + level__h1463 != 2'd0 && + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d4989 ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d5015 = + tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_143_TO_1_ETC___d4693 || + ((level__h1463 == 2'd0) ? + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d5013) ; + assign NOT_tagLookup_tagCache_cts_read__795_BITS_278__ETC___d4253 = + (tagLookup_tagCache_cts[278:277] == 2'd2) ? + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d4203 : + tagLookup_tagCache_cts[278:277] == 2'd0 && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d4250 ; + assign NOT_tagLookup_tagCache_cts_read__795_BIT_136_0_ETC___d3625 = + !tagLookup_tagCache_cts[136] && + (!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 || + !SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455) && + (!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) ; + assign NOT_tagLookup_tagCache_cts_read__795_BIT_226_5_ETC___d4121 = + !tagLookup_tagCache_cts[226] && + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) ; + assign NOT_tagLookup_tagCache_missedResp_whas__080_08_ETC___d5095 = + (!tagLookup_tagCache_missedResp$whas || + !tagLookup_tagCache_missedResp$wget) && + tagLookup_tagCache_cacheState && + tagLookup_tagCache_resps$wget[8] && + (tagLookup_tagCache_resps$wget[224:223] != 2'd0 || + tagLookup_tagCache_resps$wget[222]) ; + assign NOT_tagLookup_tagCache_missedResp_whas__080_08_ETC___d5111 = + (!tagLookup_tagCache_missedResp$whas || + !tagLookup_tagCache_missedResp$wget) && + tagLookup_tagCache_cacheState && + tagLookup_tagCache_resps$wget[8] && + (tagLookup_tagCache_resps$wget[224:223] != 2'd0 || + tagLookup_tagCache_resps$wget[222]) && + tagLookup_tagCache_orderer_slaveAddrs_bag[41] && + tagLookup_tagCache_orderer_slaveAddrs_bag[5] == + tagLookup_tagCache_resps$wget[14] && + tagLookup_tagCache_orderer_slaveAddrs_bag[4:0] == + tagLookup_tagCache_resps$wget[13:9] ; + assign NOT_tagLookup_tagCache_missedResp_whas__080_08_ETC___d5137 = + (!tagLookup_tagCache_missedResp$whas || + !tagLookup_tagCache_missedResp$wget) && + tagLookup_tagCache_cacheState && + tagLookup_tagCache_resps$wget[1] && + x_port1__read__h92294 != 5'd0 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1580 = + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1559 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1562) && + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1566 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1569) && + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1573 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1576) ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1582 = + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1545 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1548) && + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1552 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1555) && + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1580 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1584 = + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1531 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1534) && + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1538 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1541) && + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1582 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1586 = + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1517 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1520) && + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1524 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1527) && + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1584 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1588 = + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1503 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1506) && + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1510 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1513) && + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1586 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1590 = + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1489 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1492) && + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1496 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1499) && + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1588 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1592 = + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1475 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1478) && + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1482 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1485) && + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1590 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d2951 = + (!tagLookup_tagCache_orderer_mastLines_bag[209] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2933) && + (!tagLookup_tagCache_orderer_mastLines_bag[167] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2936) && + (!tagLookup_tagCache_orderer_mastLines_bag[125] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2939) && + (!tagLookup_tagCache_orderer_mastLines_bag[83] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2942) && + (!tagLookup_tagCache_orderer_mastLines_bag[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2945) ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d2955 = + (!tagLookup_tagCache_orderer_mastLines_bag[377] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2921) && + (!tagLookup_tagCache_orderer_mastLines_bag[335] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2924) && + (!tagLookup_tagCache_orderer_mastLines_bag[293] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2927) && + (!tagLookup_tagCache_orderer_mastLines_bag[251] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2930) && + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d2951 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d2959 = + (!tagLookup_tagCache_orderer_mastLines_bag[545] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2909) && + (!tagLookup_tagCache_orderer_mastLines_bag[503] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2912) && + (!tagLookup_tagCache_orderer_mastLines_bag[461] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2915) && + (!tagLookup_tagCache_orderer_mastLines_bag[419] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2918) && + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d2955 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d2961 = + (!tagLookup_tagCache_orderer_mastLines_bag[629] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2903) && + (!tagLookup_tagCache_orderer_mastLines_bag[587] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2906) && + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d2959 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5058 = + (!tagLookup_tagCache_orderer_mastLines_bag[671] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2900) && + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d2961 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3496 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5060 = + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5058 && + x_port1__read__h92294 != 5'd0 && + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1 || + tagLookup_tagCache_cts[143:140] != 4'd3) && + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1 || + tagLookup_tagCache_cts[143:140] != 4'd2) && + (SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 || + tagLookup_tagCache_cts[230]) ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5064 = + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5060 || + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5058 && + x_port1__read__h92294 != 5'd0 && + !tagLookup_tagCache_writebacks$EMPTY_N && + !tagLookup_tagCache_invalidateWritebacks$EMPTY_N && + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3503 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4729 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5066 = + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5058 && + x_port1__read__h92294 != 5'd0 && + (IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3503 || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509) && + !tagLookup_tagCache_writebacks$EMPTY_N ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2144 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1466 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1471) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2146 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1475 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1478) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2148 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1482 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1485) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2150 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1489 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1492) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2152 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1496 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1499) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2154 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1503 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1506) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2156 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1510 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1513) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2158 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1517 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1520) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2160 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1524 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1527) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2162 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1531 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1534) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2164 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1538 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1541) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1887 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2166 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1545 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1548) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1918 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2168 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1552 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1555) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1951 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2170 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1559 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1562) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1984 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2172 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1566 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1569) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2019 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2198 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1573 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1576) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2193 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1601 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1604) && + tagLookup_tagCache_orderer_mastLines_bag[671] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1641 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1642) && + tagLookup_tagCache_orderer_mastLines_bag[629] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1665 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1666) && + tagLookup_tagCache_orderer_mastLines_bag[587] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1688 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1689) && + tagLookup_tagCache_orderer_mastLines_bag[545] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1713 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1714) && + tagLookup_tagCache_orderer_mastLines_bag[503] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1738 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1739) && + tagLookup_tagCache_orderer_mastLines_bag[461] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1777 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1765 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1766) && + tagLookup_tagCache_orderer_mastLines_bag[419] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1804 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1792 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1793) && + tagLookup_tagCache_orderer_mastLines_bag[377] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1833 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1821 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1822) && + tagLookup_tagCache_orderer_mastLines_bag[335] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1862 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1850 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1851) && + tagLookup_tagCache_orderer_mastLines_bag[293] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1893 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1887 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1881 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1882) && + tagLookup_tagCache_orderer_mastLines_bag[251] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1924 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1918 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1912 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1913) && + tagLookup_tagCache_orderer_mastLines_bag[209] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1957 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1951 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1963 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1957 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1968 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1945 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1946) && + tagLookup_tagCache_orderer_mastLines_bag[167] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1990 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1968 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1984 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1996 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1990 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2002 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1978 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1979) && + tagLookup_tagCache_orderer_mastLines_bag[125] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2025 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1968 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2002 && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2019 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2031 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2025 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2038 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2013 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2014) && + tagLookup_tagCache_orderer_mastLines_bag[83] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2053 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1968 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2002 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2038 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2059 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2053 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2069 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2062 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2064) && + tagLookup_tagCache_orderer_mastLines_bag[41] ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2511 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2520 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2530 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2541 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2553 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2566 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2580 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2586 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2580 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1968 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2595 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1968 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2601 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2595 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2611 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1968 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2002 ; + assign NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2617 = + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 && + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2611 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 = + !tagLookup_tagCache_orderer_mastReqs_bag[58] || + !tagLookup_tagCache_orderer_mastReqs_bag[117] || + !tagLookup_tagCache_orderer_mastReqs_bag[176] || + !tagLookup_tagCache_orderer_mastReqs_bag[235] || + !tagLookup_tagCache_orderer_mastReqs_bag[294] || + !tagLookup_tagCache_orderer_mastReqs_bag[353] || + !tagLookup_tagCache_orderer_mastReqs_bag[412] || + !tagLookup_tagCache_orderer_mastReqs_bag[471] || + !tagLookup_tagCache_orderer_mastReqs_bag[530] || + !tagLookup_tagCache_orderer_mastReqs_bag[589] || + !tagLookup_tagCache_orderer_mastReqs_bag[648] || + !tagLookup_tagCache_orderer_mastReqs_bag[707] || + !tagLookup_tagCache_orderer_mastReqs_bag[766] || + !tagLookup_tagCache_orderer_mastReqs_bag[825] || + !tagLookup_tagCache_orderer_mastReqs_bag[884] || + !tagLookup_tagCache_orderer_mastReqs_bag[943] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3841 = + (!tagLookup_tagCache_orderer_mastReqs_bag[117] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3239 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3240) && + (!tagLookup_tagCache_orderer_mastReqs_bag[58] || + tagLookup_tagCache_orderer_mastReqs_bag[57] != + tagLookup_mRsps_ff_rf$D_OUT_1[76] || + tagLookup_tagCache_orderer_mastReqs_bag[56:52] != + tagLookup_mRsps_ff_rf$D_OUT_1[75:71]) ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3843 = + (!tagLookup_tagCache_orderer_mastReqs_bag[235] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3229 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3230) && + (!tagLookup_tagCache_orderer_mastReqs_bag[176] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3234 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3235) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3841 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3845 = + (!tagLookup_tagCache_orderer_mastReqs_bag[353] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3219 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3220) && + (!tagLookup_tagCache_orderer_mastReqs_bag[294] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3224 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3225) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3843 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3847 = + (!tagLookup_tagCache_orderer_mastReqs_bag[471] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3209 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3210) && + (!tagLookup_tagCache_orderer_mastReqs_bag[412] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3214 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3215) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3845 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3849 = + (!tagLookup_tagCache_orderer_mastReqs_bag[589] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3199 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3200) && + (!tagLookup_tagCache_orderer_mastReqs_bag[530] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3204 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3205) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3847 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3851 = + (!tagLookup_tagCache_orderer_mastReqs_bag[707] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3189 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3190) && + (!tagLookup_tagCache_orderer_mastReqs_bag[648] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3194 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3195) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3849 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3853 = + (!tagLookup_tagCache_orderer_mastReqs_bag[825] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3179 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3180) && + (!tagLookup_tagCache_orderer_mastReqs_bag[766] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3184 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3185) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3851 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3855 = + (!tagLookup_tagCache_orderer_mastReqs_bag[943] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3169 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3170) && + (!tagLookup_tagCache_orderer_mastReqs_bag[884] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3174 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3175) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3853 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d389 = + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d368 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d371) && + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d375 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d378) && + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d382 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d385) ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d391 = + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d354 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d357) && + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d361 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d364) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d389 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d393 = + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d340 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d343) && + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d347 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d350) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d391 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d395 = + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d326 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d329) && + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d333 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d336) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d393 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d397 = + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d312 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d315) && + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d319 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d322) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d395 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d399 = + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d298 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d301) && + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d305 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d308) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d397 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d401 = + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d284 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d287) && + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d291 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d294) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d399 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1001 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d375 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d378) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d848 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1027 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d382 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d385) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1022 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d973 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d275 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d280) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d975 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d284 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d287) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d977 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d291 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d294) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d979 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d298 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d301) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d981 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d305 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d308) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d983 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d312 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d315) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d985 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d319 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d322) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d987 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d326 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d329) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d989 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d333 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d336) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d991 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d340 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d343) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d993 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d347 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d350) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d995 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d354 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d357) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d747 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d997 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d361 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d364) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d780 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d999 = + (!tagLookup_tagCache_orderer_mastReqs_insertItem$whas || + !tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d368 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d371) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d813 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1340 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1349 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1359 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1370 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1382 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1395 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1409 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1415 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1409 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d797 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1424 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d797 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1430 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1424 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1440 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d797 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d831 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1446 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d1440 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d410 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d413) && + tagLookup_tagCache_orderer_mastReqs_bag[943] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d470 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d471) && + tagLookup_tagCache_orderer_mastReqs_bag[884] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d494 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d495) && + tagLookup_tagCache_orderer_mastReqs_bag[825] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d517 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d518) && + tagLookup_tagCache_orderer_mastReqs_bag[766] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d542 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d543) && + tagLookup_tagCache_orderer_mastReqs_bag[707] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d567 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d568) && + tagLookup_tagCache_orderer_mastReqs_bag[648] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d606 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d594 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d595) && + tagLookup_tagCache_orderer_mastReqs_bag[589] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d633 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d621 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d622) && + tagLookup_tagCache_orderer_mastReqs_bag[530] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d662 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d650 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d651) && + tagLookup_tagCache_orderer_mastReqs_bag[471] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d691 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d679 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d680) && + tagLookup_tagCache_orderer_mastReqs_bag[412] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d722 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d710 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d711) && + tagLookup_tagCache_orderer_mastReqs_bag[353] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d753 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d747 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d741 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d742) && + tagLookup_tagCache_orderer_mastReqs_bag[294] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d786 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d780 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d792 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d786 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d797 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d774 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d775) && + tagLookup_tagCache_orderer_mastReqs_bag[235] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d819 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d797 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d813 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d825 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d819 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d831 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d807 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d808) && + tagLookup_tagCache_orderer_mastReqs_bag[176] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d854 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d797 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d831 && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d848 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d860 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d854 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d867 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d842 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d843) && + tagLookup_tagCache_orderer_mastReqs_bag[117] ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d882 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d797 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d831 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d867 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d888 = + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 && + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d882 ; + assign NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d898 = + (!tagLookup_tagCache_orderer_mastReqs_removeItem$whas || + !tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d891 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d893) && + tagLookup_tagCache_orderer_mastReqs_bag[58] ; + assign NOT_tagLookup_tagCache_orderer_slaveDeps_remov_ETC___d264 = + { (!NOT_tagLookup_tagCache_missedResp_whas__080_08_ETC___d5095 || + !tagLookup_tagCache_retryReqs_removeItem$wget[6] || + tagLookup_tagCache_orderer_slaveDeps_bag[11] != + tagLookup_tagCache_retryReqs_removeItem$wget[5] || + tagLookup_tagCache_orderer_slaveDeps_bag[10:6] != + tagLookup_tagCache_retryReqs_removeItem$wget[4:0]) && + tagLookup_tagCache_orderer_slaveDeps_bag[12], + tagLookup_tagCache_orderer_slaveDeps_bag[11:6], + (tagLookup_tagCache_orderer_slaveDeps_updateItem$whas && + tagLookup_tagCache_orderer_slaveDeps_updateItem$wget[12] && + tagLookup_tagCache_orderer_slaveDeps_bag[11] == + tagLookup_tagCache_orderer_slaveDeps_updateItem$wget[11] && + tagLookup_tagCache_orderer_slaveDeps_bag[10:6] == + tagLookup_tagCache_orderer_slaveDeps_updateItem$wget[10:6]) ? + tagLookup_tagCache_orderer_slaveDeps_updateItem$wget[5:0] : + tagLookup_tagCache_orderer_slaveDeps_bag[5:0] } ; + assign NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d3016 = + !tagLookup_tagCache_orderer_slaveReqs_bag[58] || + tagLookup_tagCache_orderer_mastLines_bag[671] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2900 || + tagLookup_tagCache_orderer_mastLines_bag[629] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2903 || + tagLookup_tagCache_orderer_mastLines_bag[587] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2906 || + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d3012 ; + assign NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d4279 = + NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d3016 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3496 || + x_port1__read__h92294 == 5'd0 || + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3599 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 ; + assign NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d5021 = + NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d4279 || + tagLookup_tagCache_writebacks$EMPTY_N || + tagLookup_tagCache_invalidateWritebacks$EMPTY_N || + tagLookup_tagCache_cts[229:228] != 2'd0 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3534 || + tagLookup_tagCache_cts[143] ; + assign NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d5176 = + (!tagLookup_tagCache_orderer_slaveReqs_bag[58] || + NOT_tagLookup_tagCache_missedResp_whas__080_08_ETC___d5095 && + tagLookup_tagCache_retryReqs_removeItem$wget[6]) && + tagLookup_tagCache_cacheState ; + assign NOT_tagLookup_tagCache_readReqReg_read__136_BI_ETC___d3284 = + (!tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 || + !tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 || + !tagLookup_tagCache_readReqReg[66]) && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 ; + assign NOT_tagLookup_tagCache_readReqReg_read__136_BI_ETC___d3960 = + (!tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 || + !tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 || + !tagLookup_tagCache_readReqReg[66]) && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3855 ; + assign NOT_tagLookup_tagCache_readReqReg_read__136_BI_ETC___d4954 = + !tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 || + !tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 || + !tagLookup_tagCache_readReqReg[66] || + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0 || + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d4661 && + tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps_ff_l_ETC___d4662 ; + assign NOT_tagLookup_tagCache_respsReady_whas__145_31_ETC___d5317 = + (!tagLookup_tagCache_cacheState || + !tagLookup_tagCache_respsReady$wget) && + level__h8616 == 2'd0 || + !tagLookup_useNextRsp_ff_rf$D_OUT_1 ; + assign NOT_tagLookup_tagCache_writebacks_i_notEmpty___ETC___d3076 = + !tagLookup_tagCache_writebacks$EMPTY_N && + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141] || + tagLookup_mRsps_ff_lhead_read__894_MINUS_tagLo_ETC___d3074) ; + assign NOT_writeBuffer_ff_lhead_read__893_MINUS_write_ETC___d5925 = + level__h313914 != 5'd0 && + (writeBuffer_ff_rf$D_OUT_1[93:92] != 2'd0 || + !tagLookup_readReqs_ff_full$port1__read) && + (IF_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail__ETC___d5922 || + !tagLookup_tagCacheReq_ff_lhead_read__179_MINUS_ETC___d5181) ; + assign NOT_writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_ETC___d5939 = + writeBuffer_ff_rf$D_OUT_1[88:81] != 8'd0 && + (writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5907 || + !writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5909) && + !writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5911 && + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5912 ; + assign SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3601 = + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + (_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3553 || + _16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3557 || + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3599) ; + assign SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3746 = + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + (_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3553 || + _16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3557 || + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3744) ; + assign _0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3553 = + memReqFifoSpace__h2403 < 10'd5 ; + assign _0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 = + memReqFifoSpace__h2403 < 10'd4 ; + assign _0_CONCAT_DONTCARE_CONCAT_IF_tagLookup_tagCache_ETC___d3035 = + { 85'h02AAAAAAAAAAAAAAAAAAAA, + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReq$wget[8:0] : + tagLookup_tagCache_cts[144:136] } ; + assign _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493 = + { 7'd0, tagLookup_pendingCapNumber[35:3] } + 40'h00FF7FF080 ; + assign _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354 = + { 7'd0, x__h303814[35:3] } + + { CASE_tagLookup_currentDepth_0_535821840_1_5358_ETC__q12, + 3'd0 } ; + assign _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490 = + { 7'd0, x__h303703[35:3] } + + { CASE_tagLookup_currentDepth_338_MINUS_1_481_0__ETC__q14, + 3'd0 } ; + assign _0_CONCAT_tagLookup_tagCache_orderer_mastLines__ETC___d2188 = + { 28'd0, + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg } == + IF_NOT_tagLookup_tagCache_orderer_mastLines_in_ETC___d2187 ; + assign _0_CONCAT_tagLookup_tagCache_orderer_mastReqs_n_ETC___d1017 = + { 28'd0, tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg } == + IF_NOT_tagLookup_tagCache_orderer_mastReqs_ins_ETC___d1016 ; + assign _0_CONCAT_writeBuffer_ff_rf_sub_writeBuffer_ff__ETC___d5950 = + { 13'd0, + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5942[39:13] } + + 40'h00FF7DF080 ; + assign _0_OR_NOT_tagLookup_tagCache_cts_read__795_BIT__ETC___d4563 = + !tagLookup_tagCache_cts[225] && !tagLookup_tagCache_cts[226] || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 || + _0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 || + _16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 ; + assign _16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3557 = + x_mastReqsSpaces__h53162 < 5'd5 ; + assign _16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 = + x_mastReqsSpaces__h53162 < 5'd4 ; + assign _1_CONCAT_IF_tagLookup_tagCache_newReq_whas__78_ETC___d3040 = + { 2'd1, + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReq$wget[91:0] : + tagLookup_tagCache_cts[227:136] } ; + assign _1_SL_tagLookup_pendingCapNumber_343_BITS_2_TO__ETC___d5671 = + 8'd1 << tagLookup_pendingCapNumber[2:0] ; + assign _2_CONCAT_DONTCARE_CONCAT_IF_tagLookup_tagCache_ETC___d3044 = + { 86'h2AAAAAAAAAAAAAAAAAAAAA, + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReq$wget[7:0] : + tagLookup_tagCache_cts[143:136] } ; + assign _dfoo1 = + way__h98147 == 1'd1 && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3974 || + _theResult_____21__h86422 == 1'd1 && + tagLookup_tagCache_cts[278:277] == 2'd0 && + NOT_SEL_ARR_NOT_tagLookup_tagCache_req_commits_ETC___d4124 ; + assign _dfoo9 = + way__h98147 == 1'd0 && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3974 || + _theResult_____21__h86422 == 1'd0 && + tagLookup_tagCache_cts[278:277] == 2'd0 && + NOT_SEL_ARR_NOT_tagLookup_tagCache_req_commits_ETC___d4124 ; + assign _theResult_____1__h31534 = + (tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastReq_ETC___d1056 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055) ? + idx__h31676 : + IF_IF_tagLookup_tagCache_orderer_mastReqs_inse_ETC___d1159 ; + assign _theResult_____1__h43323 = + (tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 ? + IF_0_CONCAT_tagLookup_tagCache_orderer_mastLin_ETC___d2227 : + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226) ? + idx__h43465 : + IF_IF_tagLookup_tagCache_orderer_mastLines_ins_ETC___d2330 ; + assign _theResult_____1_snd__h307206 = wbitE__h303269 | x__h307116 ; + assign _theResult_____1_snd__h307357 = 8'd1 << x__h303814[2:0] ; + assign _theResult_____1_tag__h121522 = + (level__h1463 == 2'd0) ? + x_addr_tag__h102720 : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4263 ; + assign _theResult_____21__h86422 = + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3492 ? + tagLookup_tagCache_cts[82] : + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 ; + assign _theResult_____23__h86225 = + ((!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 || + !SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455) && + (!tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 || + !SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488)) ? + tagLookup_tagCache_cts[82] : + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 ; + assign _theResult_____3_snd_snd_snd_snd_snd_d_key__h278742 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + x1_avValue_snd_snd_snd_d_key__h278330 : + tagLookup_tagCache_readReqReg[65:58] ; + assign _theResult_____3_way__h74739 = + IF_tagLookup_tagCache_newReq_whas__787_AND_tag_ETC___d2975 ? + IF_IF_tagLookup_tagCache_newReq_whas__787_AND__ETC___d3067 : + tagLookup_tagCache_nextWay ; + assign _theResult___snd_snd_fst_data_data__h330561 = + (lookupRsp_bag_748_BIT_17_761_AND_lookupRsp_bag_ETC___d6095 && + lookupRsp_bag[4]) ? + { 60'd0, lookupRsp_bag[3:0] } : + 64'd0 ; + assign _theResult___snd_snd_fst_data_data__h330563 = + (tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 && + frame == 3'd0) ? + _theResult___snd_snd_fst_data_data__h330561 : + mRsps_ff_rf$D_OUT_1[63:0] ; + assign _theResult___snd_snd_fst_masterID__h330322 = + (tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 && + frame == 3'd0) ? + tagOnlyReads_rf[5] : + mRsps_ff_rf$D_OUT_1[76] ; + assign _theResult___snd_snd_fst_transactionID__h330323 = + (tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 && + frame == 3'd0) ? + tagOnlyReads_rf[4:0] : + mRsps_ff_rf$D_OUT_1[75:71] ; + assign bitEnable__h303972 = + (!IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 || + tagLookup_pendingCapEnable) ? + wbitE__h303269 | + _1_SL_tagLookup_pendingCapNumber_343_BITS_2_TO__ETC___d5671 : + wbitE__h303269 & y__h307071 ; + assign bitEnable__h303984 = + (tagLookup_currentDepth == 2'd1) ? + bitEnable__h303972 : + _theResult_____1_snd__h307206 ; + assign bitEnable__h303992 = + tagLookup_pendingCapEnable ? + _1_SL_tagLookup_pendingCapNumber_343_BITS_2_TO__ETC___d5671 : + 8'd0 ; + assign cache_request_put_val_BITS_140_TO_101_012_MINU_ETC___d6067 = + cache_request_put_val[140:101] - 40'h00C0000000 ; + assign cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6013 = + cache_request_put_val[140:101] < 40'h00FF7DF080 ; + assign cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6014 = + cache_request_put_val[140:101] < 40'h00FFFFF000 ; + assign cache_request_put_val_BITS_93_TO_92_997_EQ_0_9_ETC___d6066 = + cache_request_put_val[93:92] == 2'd0 && + (cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6013 || + !cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6014) && + cache_request_put_val[140:101] >= 40'h00C0000000 && + cache_request_put_val[140:101] < 40'h00FFFFC000 ; + assign data_data__h307593 = + (tagLookup_currentDepth == 2'd1) ? + wdata_data__h307595 : + wdata_data__h307591 ; + assign i__h301909 = + { _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354[2:0], + x__h303814[2:0] } ; + assign idx__h296159 = + { 2'd0, + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354[2:0], + x__h303814[2] } ; + assign idx__h31676 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd15 ; + assign idx__h31792 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd14 ; + assign idx__h31908 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd13 ; + assign idx__h32024 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd12 ; + assign idx__h32140 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd11 ; + assign idx__h32256 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd10 ; + assign idx__h32372 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd9 ; + assign idx__h32488 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd8 ; + assign idx__h32604 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd7 ; + assign idx__h32720 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd6 ; + assign idx__h32836 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd5 ; + assign idx__h32952 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd4 ; + assign idx__h33068 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd3 ; + assign idx__h33184 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd2 ; + assign idx__h33300 = + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg + 4'd1 ; + assign idx__h43465 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd15 ; + assign idx__h43581 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd14 ; + assign idx__h43697 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd13 ; + assign idx__h43813 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd12 ; + assign idx__h43929 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd11 ; + assign idx__h44045 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd10 ; + assign idx__h44161 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd9 ; + assign idx__h44277 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd8 ; + assign idx__h44393 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd7 ; + assign idx__h44509 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd6 ; + assign idx__h44625 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd5 ; + assign idx__h44741 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd4 ; + assign idx__h44857 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd3 ; + assign idx__h44973 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd2 ; + assign idx__h45089 = + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg + 4'd1 ; + assign level__h1012 = tagLookup_mReqs_ff_lhead - tagLookup_mReqs_ff_ltail ; + assign level__h1463 = tagLookup_mRsps_ff_lhead - tagLookup_mRsps_ff_ltail ; + assign level__h1913 = + tagLookup_useNextRsp_ff_lhead - tagLookup_useNextRsp_ff_ltail ; + assign level__h313914 = writeBuffer_ff_lhead - writeBuffer_ff_ltail ; + assign level__h314247 = mReqs_ff_lhead - mReqs_ff_ltail ; + assign level__h314581 = mRsps_ff_lhead - mRsps_ff_ltail ; + assign level__h8616 = + tagLookup_tagCache_writeResps_ff_lhead - + tagLookup_tagCache_writeResps_ff_ltail ; + assign lookupRsp_bag_748_BITS_15_TO_11_754_EQ_mRsps_f_ETC___d6104 = + lookupRsp_bag[15:11] == mRsps_ff_rf$D_OUT_1[75:71] ; + assign lookupRsp_bag_748_BIT_16_749_EQ_mRsps_ff_rf_su_ETC___d6102 = + lookupRsp_bag[16] == mRsps_ff_rf$D_OUT_1[76] ; + assign lookupRsp_bag_748_BIT_17_761_AND_lookupRsp_bag_ETC___d6095 = + lookupRsp_bag[17] && lookupRsp_bag[16] == tagOnlyReads_rf[5] && + lookupRsp_bag[15:11] == tagOnlyReads_rf[4:0] ; + assign maskedWrite_data__h117949 = + { IF_tagLookup_tagCache_cts_read__795_BIT_224_12_ETC___d4135, + IF_tagLookup_tagCache_cts_read__795_BIT_223_13_ETC___d4142, + IF_tagLookup_tagCache_cts_read__795_BIT_222_14_ETC___d4150, + IF_tagLookup_tagCache_cts_read__795_BIT_221_15_ETC___d4157, + IF_tagLookup_tagCache_cts_read__795_BIT_220_15_ETC___d4165, + IF_tagLookup_tagCache_cts_read__795_BIT_219_16_ETC___d4172, + IF_tagLookup_tagCache_cts_read__795_BIT_218_17_ETC___d4180, + IF_tagLookup_tagCache_cts_read__795_BIT_217_18_ETC___d4187 } ; + assign memReqFifoSpace__h2403 = { 6'd0, x__h102652 } ; + assign newCt_way__h74804 = + tagLookup_tagCache_writebacks$EMPTY_N ? + tagLookup_tagCache_writebacks$D_OUT[7] : + x1_avValue_way__h74757 ; + assign newHead___1__h49394 = newHead__h48716 + 5'd1 ; + assign newHead___1__h49407 = + tagLookup_tagCache_orderer_mastReqIds_lhead - 5'd1 ; + assign newHead__h48716 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas ? + newHead___1__h49407 : + tagLookup_tagCache_orderer_mastReqIds_lhead ; + assign nodeOffset__h304386 = + _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0] & + y__h304733 ; + assign nodeOffset__h304822 = + _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490[2:0] & + y__h304733 ; + assign tagLookup_currentDepth_338_MINUS_1___d5481 = + tagLookup_currentDepth - 2'd1 ; + assign tagLookup_lookupRsp_ff_lhead_read__318_MINUS_t_ETC___d5320 = + tagLookup_lookupRsp_ff_lhead - tagLookup_lookupRsp_ff_ltail ; + assign tagLookup_mRsps_ff_lhead_read__894_MINUS_tagLo_ETC___d2965 = + (level__h1463 == 2'd0 || + tagLookup_tagCache_orderer_slaveRespState[12]) && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2963 && + (tagLookup_tagCache_orderer_lookupState[12] || + !tagLookup_tagCache_nextEmpty || + tagLookup_tagCache_cts[80]) ; + assign tagLookup_mRsps_ff_lhead_read__894_MINUS_tagLo_ETC___d3074 = + (level__h1463 == 2'd0 || + tagLookup_tagCache_orderer_slaveRespState[12]) && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2963 && + tagLookup_tagCache_orderer_lookupState[12] && + tagLookup_tagCache_cts[80] ; + assign tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps_ff_l_ETC___d3946 = + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 && + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3274 && + !tagLookup_tagCache_readReqReg[51] && + x_port1__read__h92294 != 5'd0 ; + assign tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps_ff_l_ETC___d4662 = + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 || + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d4658 || + tagLookup_tagCache_readReqReg[51] || + x_port1__read__h92294 == 5'd0 ; + assign tagLookup_state_read__216_EQ_1_370_AND_NOT_tag_ETC___d5989 = + tagLookup_state == 3'd1 && + !tagLookup_tagCacheReq_ff_lhead_read__179_MINUS_ETC___d5181 && + level__h1012 == 4'd0 && + level__h314247 != 2'd2 ; + assign tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5381 = + tagLookup_state == 3'd2 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 && + !tagLookup_lookupRsp_ff_lhead_read__318_MINUS_t_ETC___d5320 || + tagLookup_state == 3'd3 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 || + tagLookup_state == 3'd4 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 || + tagLookup_state != 3'd5 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5377 ; + assign tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5382 = + tagLookup_state == 3'd2 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 && + !tagLookup_lookupRsp_ff_lhead_read__318_MINUS_t_ETC___d5320 && + (tagLookup_currentDepth == 2'd0 || + !IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358) ; + assign tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5471 = + tagLookup_state == 3'd2 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 && + !tagLookup_lookupRsp_ff_lhead_read__318_MINUS_t_ETC___d5320 || + tagLookup_state == 3'd3 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 || + tagLookup_state == 3'd4 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 || + tagLookup_state == 3'd5 ; + assign tagLookup_state_read__216_EQ_2_311_AND_tagLook_ETC___d5499 = + tagLookup_state == 3'd2 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 && + !tagLookup_lookupRsp_ff_lhead_read__318_MINUS_t_ETC___d5320 || + tagLookup_state == 3'd4 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 && + tagLookup_currentDepth != 2'd0 && + IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 ; + assign tagLookup_tagCacheReq_ff_lhead_read__179_MINUS_ETC___d5181 = + tagLookup_tagCacheReq_ff_lhead - tagLookup_tagCacheReq_ff_ltail ; + assign tagLookup_tagCache_cts_read__795_BITS_100_TO_9_ETC___d3499 = + tagLookup_tagCache_cts[100:99] == + tagLookup_tagCache_orderer_slaveRespState[1:0] ; + assign tagLookup_tagCache_cts_read__795_BITS_100_TO_9_ETC___d3501 = + tagLookup_tagCache_cts[100:99] == + tagLookup_tagCache_orderer_slaveReqs_bag[10:9] ; + assign tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 = + tagLookup_tagCache_cts[135:109] == x1_avValue_tag__h84438 ; + assign tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 = + tagLookup_tagCache_cts[135:109] == x1_avValue_tag__h84378 ; + assign tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3572 = + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) && + tagLookup_tagCache_cts[143] ; + assign tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3575 = + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) && + !tagLookup_tagCache_cts[144] ; + assign tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3578 = + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) && + tagLookup_tagCache_cts[144] ; + assign tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3583 = + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) && + !tagLookup_tagCache_cts[226] ; + assign tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3632 = + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 ; + assign tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3676 = + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 ; + assign tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4288 = + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) && + (IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544) ; + assign tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4326 = + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) && + !tagLookup_tagCache_cts[143] ; + assign tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4733 = + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488) && + !tagLookup_tagCache_cts[225] ; + assign tagLookup_tagCache_cts_read__795_BITS_143_TO_1_ETC___d3991 = + (tagLookup_tagCache_cts[143:140] == 4'd1 || + tagLookup_tagCache_cts[143:140] == 4'd2) && + tagLookup_tagCache_cts_read__795_BIT_136_060_O_ETC___d3609 && + SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d3614 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 ; + assign tagLookup_tagCache_cts_read__795_BITS_143_TO_1_ETC___d4693 = + tagLookup_tagCache_cts[143:140] == 4'd8 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2963 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3496 && + x_port1__read__h92294 != 5'd0 ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3582 = + tagLookup_tagCache_cts[229:228] == 2'd0 && + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3572 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 || + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3575 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3578) && + !tagLookup_tagCache_cts[143]) ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3681 = + tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3632 && + !tagLookup_tagCache_cts[143] || + tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3676) ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3683 = + tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3572 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 || + tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3676 && + !tagLookup_tagCache_cts[143] || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3681 ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3997 = + tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3572 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d3614 && + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4000 = + (tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3632 && + !tagLookup_tagCache_cts[143] || + tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544)) && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 && + SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d3614 ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4120 = + tagLookup_tagCache_cts[229:228] == 2'd1 && + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3561 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4117 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4212 = + tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3632 && + !tagLookup_tagCache_cts[143] || + tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544) && + IF_SEL_ARR_IF_tagLookup_tagCache_tags_0_readAd_ETC___d4210 ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4229 = + tagLookup_tagCache_cts[229:228] == 2'd1 && + (tagLookup_tagCache_cts[225] || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3544) && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 && + !_0_CONCAT_8_MINUS_tagLookup_mReqs_ff_lhead_read_ETC___d3617 && + !_16_MINUS_16_MINUS_tagLookup_tagCache_orderer_m_ETC___d3619 ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4232 = + tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3572 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 || + (tagLookup_tagCache_cts[229:228] != 2'd0 || + NOT_tagLookup_tagCache_cts_read__795_BITS_135__ETC___d3534 || + tagLookup_tagCache_cts[143]) && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4230 ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 = + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1 || + tagLookup_tagCache_cts[143:140] != 4'd3) && + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1 || + tagLookup_tagCache_cts[143:140] != 4'd2) && + (SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 || + tagLookup_tagCache_cts[230]) || + NOT_tagLookup_tagCache_orderer_slaveReqs_bag_4_ETC___d4279 || + tagLookup_tagCache_writebacks$EMPTY_N || + tagLookup_tagCache_invalidateWritebacks$EMPTY_N ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4291 = + tagLookup_tagCache_cts[229:228] == 2'd0 && + (tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3572 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d4288 && + !tagLookup_tagCache_cts[143]) ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4667 = + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566 || + tagLookup_tagCache_readReqReg[66] ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4956 = + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1 || + NOT_tagLookup_tagCache_cts_read__795_BITS_143__ETC___d4951) && + (level__h1463 == 2'd0 || + NOT_tagLookup_tagCache_readReqReg_read__136_BI_ETC___d4954) ; + assign tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4958 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4956 || + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1 || + NOT_tagLookup_tagCache_cts_read__795_BITS_143__ETC___d4951) && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0 ; + assign tagLookup_tagCache_cts_read__795_BITS_235_TO_2_ETC___d2845 = + tagLookup_tagCache_cts[235:231] == + tagLookup_tagCache_orderer_slaveRespState[10:6] ; + assign tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3290 = + tagLookup_tagCache_cts[278:277] == 2'd2 && + level__h1463 != 2'd0 && + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3283 || + NOT_tagLookup_tagCache_readReqReg_read__136_BI_ETC___d3284) || + tagLookup_tagCache_cts[278:277] == 2'd0 && + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3151 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 ; + assign tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3292 = + tagLookup_tagCache_cts[278:277] == 2'd1 && + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3151 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 || + tagLookup_tagCache_cts[278:277] != 2'd1 && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3290 ; + assign tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3303 = + tagLookup_tagCache_cts[278:277] == 2'd2 && + level__h1463 != 2'd0 && + (tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3299 || + NOT_tagLookup_tagCache_readReqReg_read__136_BI_ETC___d3284) || + tagLookup_tagCache_cts[278:277] == 2'd0 && + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3151 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 ; + assign tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3668 = + tagLookup_tagCache_cts[278:277] == 2'd0 && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3516 && + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 && + x__h102652 != 4'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3660 && + tagLookup_tagCache_orderer_mastReqIds_lhead != 5'd0 && + level__h1012 == 4'd8 ; + assign tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3769 = + { tagLookup_tagCache_cts[278:277] == 2'd1 || + tagLookup_tagCache_cts[236], + tagLookup_tagCache_orderer_mastReqIds_rf[4:0], + 35'h2AAAAAAAA, + (tagLookup_tagCache_cts[278:277] == 2'd1) ? + { tagLookup_tagCache_cts[100:99], + tagLookup_tagCache_cts[100:92] } : + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3767 } ; + assign tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3858 = + tagLookup_tagCache_cts[278:277] == 2'd1 && + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3151 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3855 ; + assign tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3974 = + tagLookup_tagCache_cts[278:277] == 2'd2 && + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 && + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0 ; + assign tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3984 = + tagLookup_tagCache_cts[278:277] == 2'd0 && + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3151 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd1 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3855 ; + assign tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d4983 = + tagLookup_tagCache_cts[278:277] == 2'd0 && + (tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4724 ? + tagLookup_tagCache_cts[229:228] == 2'd0 : + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3511 && + !tagLookup_tagCache_writebacks$EMPTY_N && + !tagLookup_tagCache_invalidateWritebacks$EMPTY_N && + tagLookup_tagCache_cts[229:228] == 2'd0 && + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3676 && + !tagLookup_tagCache_cts[143]) ; + assign tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d5072 = + tagLookup_tagCache_cts[278:277] == 2'd0 && + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5064 && + (NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5060 || + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d5066 && + !tagLookup_tagCache_invalidateWritebacks$EMPTY_N && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4739) && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4708 ; + assign tagLookup_tagCache_cts_read__795_BIT_136_060_O_ETC___d3609 = + tagLookup_tagCache_cts[136] || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3427 && + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 || + tagLookup_tagCache_cts_read__795_BITS_135_TO_1_ETC___d3461 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488 ; + assign tagLookup_tagCache_cts_read__795_BIT_236_831_E_ETC___d2843 = + tagLookup_tagCache_cts[236] == + tagLookup_tagCache_orderer_slaveRespState[11] ; + assign tagLookup_tagCache_cts_read__795_BIT_236_831_E_ETC___d4760 = + tagLookup_tagCache_cts[236] == + x1_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_fst_d_inId_masterID__h278688 && + tagLookup_tagCache_cts[235:231] == + x1_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_fst_d_inId_transactionID__h278689 || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4759 ; + assign tagLookup_tagCache_newReq_whas__787_AND_tagLoo_ETC___d2799 = + CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141] || + tagLookup_tagCache_orderer_lookupState[12] || + !tagLookup_tagCache_nextEmpty || + tagLookup_tagCache_cts[80] ; + assign tagLookup_tagCache_newReqwget_BITS_140_TO_101__q20 = + tagLookup_tagCache_newReq$wget[140:101] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1466 = + tagLookup_tagCache_orderer_mastLines_bag[670] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1471 = + tagLookup_tagCache_orderer_mastLines_bag[669:665] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1475 = + tagLookup_tagCache_orderer_mastLines_bag[628] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1478 = + tagLookup_tagCache_orderer_mastLines_bag[627:623] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1482 = + tagLookup_tagCache_orderer_mastLines_bag[586] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1485 = + tagLookup_tagCache_orderer_mastLines_bag[585:581] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1489 = + tagLookup_tagCache_orderer_mastLines_bag[544] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1492 = + tagLookup_tagCache_orderer_mastLines_bag[543:539] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1496 = + tagLookup_tagCache_orderer_mastLines_bag[502] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1499 = + tagLookup_tagCache_orderer_mastLines_bag[501:497] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1503 = + tagLookup_tagCache_orderer_mastLines_bag[460] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1506 = + tagLookup_tagCache_orderer_mastLines_bag[459:455] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1510 = + tagLookup_tagCache_orderer_mastLines_bag[418] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1513 = + tagLookup_tagCache_orderer_mastLines_bag[417:413] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1517 = + tagLookup_tagCache_orderer_mastLines_bag[376] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1520 = + tagLookup_tagCache_orderer_mastLines_bag[375:371] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1524 = + tagLookup_tagCache_orderer_mastLines_bag[334] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1527 = + tagLookup_tagCache_orderer_mastLines_bag[333:329] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1531 = + tagLookup_tagCache_orderer_mastLines_bag[292] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1534 = + tagLookup_tagCache_orderer_mastLines_bag[291:287] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1538 = + tagLookup_tagCache_orderer_mastLines_bag[250] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1541 = + tagLookup_tagCache_orderer_mastLines_bag[249:245] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1545 = + tagLookup_tagCache_orderer_mastLines_bag[208] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1548 = + tagLookup_tagCache_orderer_mastLines_bag[207:203] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1552 = + tagLookup_tagCache_orderer_mastLines_bag[166] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1555 = + tagLookup_tagCache_orderer_mastLines_bag[165:161] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1559 = + tagLookup_tagCache_orderer_mastLines_bag[124] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1562 = + tagLookup_tagCache_orderer_mastLines_bag[123:119] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1566 = + tagLookup_tagCache_orderer_mastLines_bag[82] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1569 = + tagLookup_tagCache_orderer_mastLines_bag[81:77] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1573 = + tagLookup_tagCache_orderer_mastLines_bag[40] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[40] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1576 = + tagLookup_tagCache_orderer_mastLines_bag[39:35] == + tagLookup_tagCache_orderer_mastLines_insertItem$wget[39:35] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1601 = + tagLookup_tagCache_orderer_mastLines_bag[670] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1604 = + tagLookup_tagCache_orderer_mastLines_bag[669:665] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1641 = + tagLookup_tagCache_orderer_mastLines_bag[628] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1642 = + tagLookup_tagCache_orderer_mastLines_bag[627:623] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1665 = + tagLookup_tagCache_orderer_mastLines_bag[586] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1666 = + tagLookup_tagCache_orderer_mastLines_bag[585:581] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1688 = + tagLookup_tagCache_orderer_mastLines_bag[544] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1689 = + tagLookup_tagCache_orderer_mastLines_bag[543:539] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1713 = + tagLookup_tagCache_orderer_mastLines_bag[502] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1714 = + tagLookup_tagCache_orderer_mastLines_bag[501:497] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1738 = + tagLookup_tagCache_orderer_mastLines_bag[460] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1739 = + tagLookup_tagCache_orderer_mastLines_bag[459:455] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1765 = + tagLookup_tagCache_orderer_mastLines_bag[418] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1766 = + tagLookup_tagCache_orderer_mastLines_bag[417:413] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1792 = + tagLookup_tagCache_orderer_mastLines_bag[376] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1793 = + tagLookup_tagCache_orderer_mastLines_bag[375:371] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1821 = + tagLookup_tagCache_orderer_mastLines_bag[334] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1822 = + tagLookup_tagCache_orderer_mastLines_bag[333:329] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1850 = + tagLookup_tagCache_orderer_mastLines_bag[292] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1851 = + tagLookup_tagCache_orderer_mastLines_bag[291:287] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1881 = + tagLookup_tagCache_orderer_mastLines_bag[250] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1882 = + tagLookup_tagCache_orderer_mastLines_bag[249:245] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1912 = + tagLookup_tagCache_orderer_mastLines_bag[208] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1913 = + tagLookup_tagCache_orderer_mastLines_bag[207:203] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1945 = + tagLookup_tagCache_orderer_mastLines_bag[166] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1946 = + tagLookup_tagCache_orderer_mastLines_bag[165:161] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1978 = + tagLookup_tagCache_orderer_mastLines_bag[124] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1979 = + tagLookup_tagCache_orderer_mastLines_bag[123:119] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2013 = + tagLookup_tagCache_orderer_mastLines_bag[82] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2014 = + tagLookup_tagCache_orderer_mastLines_bag[81:77] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2062 = + tagLookup_tagCache_orderer_mastLines_bag[40] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2064 = + tagLookup_tagCache_orderer_mastLines_bag[39:35] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2900 = + tagLookup_tagCache_orderer_mastLines_bag[664:630] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2903 = + tagLookup_tagCache_orderer_mastLines_bag[622:588] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2906 = + tagLookup_tagCache_orderer_mastLines_bag[580:546] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2909 = + tagLookup_tagCache_orderer_mastLines_bag[538:504] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2912 = + tagLookup_tagCache_orderer_mastLines_bag[496:462] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2915 = + tagLookup_tagCache_orderer_mastLines_bag[454:420] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2918 = + tagLookup_tagCache_orderer_mastLines_bag[412:378] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2921 = + tagLookup_tagCache_orderer_mastLines_bag[370:336] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2924 = + tagLookup_tagCache_orderer_mastLines_bag[328:294] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2927 = + tagLookup_tagCache_orderer_mastLines_bag[286:252] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2930 = + tagLookup_tagCache_orderer_mastLines_bag[244:210] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2933 = + tagLookup_tagCache_orderer_mastLines_bag[202:168] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2936 = + tagLookup_tagCache_orderer_mastLines_bag[160:126] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2939 = + tagLookup_tagCache_orderer_mastLines_bag[118:84] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2942 = + tagLookup_tagCache_orderer_mastLines_bag[76:42] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2945 = + tagLookup_tagCache_orderer_mastLines_bag[34:0] == + tagLookup_tagCache_cts[276:242] ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d3004 = + tagLookup_tagCache_orderer_mastLines_bag[209] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2933 || + tagLookup_tagCache_orderer_mastLines_bag[167] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2936 || + tagLookup_tagCache_orderer_mastLines_bag[125] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2939 || + tagLookup_tagCache_orderer_mastLines_bag[83] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2942 || + tagLookup_tagCache_orderer_mastLines_bag[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2945 ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d3008 = + tagLookup_tagCache_orderer_mastLines_bag[377] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2921 || + tagLookup_tagCache_orderer_mastLines_bag[335] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2924 || + tagLookup_tagCache_orderer_mastLines_bag[293] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2927 || + tagLookup_tagCache_orderer_mastLines_bag[251] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2930 || + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d3004 ; + assign tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d3012 = + tagLookup_tagCache_orderer_mastLines_bag[545] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2909 || + tagLookup_tagCache_orderer_mastLines_bag[503] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2912 || + tagLookup_tagCache_orderer_mastLines_bag[461] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2915 || + tagLookup_tagCache_orderer_mastLines_bag[419] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2918 || + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d3008 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d1594 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + (!tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1466 || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1471) && + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d1592 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2474 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1466 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1471 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1640 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2477 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1475 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1478 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1654 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2482 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1482 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1485 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1678 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2488 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1489 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1492 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1702 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2495 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1496 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1499 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1728 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2503 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1503 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1506 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1754 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2512 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1510 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1513 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1782 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2522 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1517 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1520 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1810 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2533 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1524 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1527 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1840 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2545 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1531 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1534 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1870 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2558 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1538 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1541 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1902 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2572 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1545 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1548 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1934 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2587 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1552 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1555 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d1968 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2603 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1559 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1562 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2002 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2620 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1566 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1569 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2038 ; + assign tagLookup_tagCache_orderer_mastLines_insertIte_ETC___d2624 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastLines_insertItem$wget[41] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1573 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1576 || + NOT_tagLookup_tagCache_orderer_mastLines_remov_ETC___d2069 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1601 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1604 || + !tagLookup_tagCache_orderer_mastLines_bag[671] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1641 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1642 || + !tagLookup_tagCache_orderer_mastLines_bag[629] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1665 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1666 || + !tagLookup_tagCache_orderer_mastLines_bag[587] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1688 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1689 || + !tagLookup_tagCache_orderer_mastLines_bag[545] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1713 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1714 || + !tagLookup_tagCache_orderer_mastLines_bag[503] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1738 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1739 || + !tagLookup_tagCache_orderer_mastLines_bag[461] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1765 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1766 || + !tagLookup_tagCache_orderer_mastLines_bag[419] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1792 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1793 || + !tagLookup_tagCache_orderer_mastLines_bag[377] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1821 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1822 || + !tagLookup_tagCache_orderer_mastLines_bag[335] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1850 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1851 || + !tagLookup_tagCache_orderer_mastLines_bag[293] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1887 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1881 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1882 || + !tagLookup_tagCache_orderer_mastLines_bag[251] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1918 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1912 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1913 || + !tagLookup_tagCache_orderer_mastLines_bag[209] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1951 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1945 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1946 || + !tagLookup_tagCache_orderer_mastLines_bag[167] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1984 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1978 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d1979 || + !tagLookup_tagCache_orderer_mastLines_bag[125] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2019 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2013 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2014 || + !tagLookup_tagCache_orderer_mastLines_bag[83] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2193 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2062 && + tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2064 || + !tagLookup_tagCache_orderer_mastLines_bag[41] ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2344 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1887 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1918 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1951 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1984 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2019 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2350 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2344 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2360 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1887 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1918 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1951 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1984 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2366 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2360 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2375 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1887 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1918 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1951 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2381 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2375 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2389 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1887 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1918 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2395 = + (tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2389) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1951 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2402 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1887 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2414 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2425 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2435 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2444 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 ; + assign tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2452 = + (tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 || + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744) && + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d275 = + tagLookup_tagCache_orderer_mastReqs_bag[942] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d280 = + tagLookup_tagCache_orderer_mastReqs_bag[941:937] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d284 = + tagLookup_tagCache_orderer_mastReqs_bag[883] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d287 = + tagLookup_tagCache_orderer_mastReqs_bag[882:878] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d291 = + tagLookup_tagCache_orderer_mastReqs_bag[824] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d294 = + tagLookup_tagCache_orderer_mastReqs_bag[823:819] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d298 = + tagLookup_tagCache_orderer_mastReqs_bag[765] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d301 = + tagLookup_tagCache_orderer_mastReqs_bag[764:760] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d305 = + tagLookup_tagCache_orderer_mastReqs_bag[706] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d308 = + tagLookup_tagCache_orderer_mastReqs_bag[705:701] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d312 = + tagLookup_tagCache_orderer_mastReqs_bag[647] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d315 = + tagLookup_tagCache_orderer_mastReqs_bag[646:642] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3169 = + tagLookup_tagCache_orderer_mastReqs_bag[942] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3170 = + tagLookup_tagCache_orderer_mastReqs_bag[941:937] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3174 = + tagLookup_tagCache_orderer_mastReqs_bag[883] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3175 = + tagLookup_tagCache_orderer_mastReqs_bag[882:878] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3179 = + tagLookup_tagCache_orderer_mastReqs_bag[824] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3180 = + tagLookup_tagCache_orderer_mastReqs_bag[823:819] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3184 = + tagLookup_tagCache_orderer_mastReqs_bag[765] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3185 = + tagLookup_tagCache_orderer_mastReqs_bag[764:760] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3189 = + tagLookup_tagCache_orderer_mastReqs_bag[706] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d319 = + tagLookup_tagCache_orderer_mastReqs_bag[588] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3190 = + tagLookup_tagCache_orderer_mastReqs_bag[705:701] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3194 = + tagLookup_tagCache_orderer_mastReqs_bag[647] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3195 = + tagLookup_tagCache_orderer_mastReqs_bag[646:642] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3199 = + tagLookup_tagCache_orderer_mastReqs_bag[588] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3200 = + tagLookup_tagCache_orderer_mastReqs_bag[587:583] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3204 = + tagLookup_tagCache_orderer_mastReqs_bag[529] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3205 = + tagLookup_tagCache_orderer_mastReqs_bag[528:524] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3209 = + tagLookup_tagCache_orderer_mastReqs_bag[470] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3210 = + tagLookup_tagCache_orderer_mastReqs_bag[469:465] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3214 = + tagLookup_tagCache_orderer_mastReqs_bag[411] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3215 = + tagLookup_tagCache_orderer_mastReqs_bag[410:406] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3219 = + tagLookup_tagCache_orderer_mastReqs_bag[352] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d322 = + tagLookup_tagCache_orderer_mastReqs_bag[587:583] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3220 = + tagLookup_tagCache_orderer_mastReqs_bag[351:347] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3224 = + tagLookup_tagCache_orderer_mastReqs_bag[293] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3225 = + tagLookup_tagCache_orderer_mastReqs_bag[292:288] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3229 = + tagLookup_tagCache_orderer_mastReqs_bag[234] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3230 = + tagLookup_tagCache_orderer_mastReqs_bag[233:229] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3234 = + tagLookup_tagCache_orderer_mastReqs_bag[175] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3235 = + tagLookup_tagCache_orderer_mastReqs_bag[174:170] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3239 = + tagLookup_tagCache_orderer_mastReqs_bag[116] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3240 = + tagLookup_tagCache_orderer_mastReqs_bag[115:111] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d326 = + tagLookup_tagCache_orderer_mastReqs_bag[529] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d329 = + tagLookup_tagCache_orderer_mastReqs_bag[528:524] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d333 = + tagLookup_tagCache_orderer_mastReqs_bag[470] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d336 = + tagLookup_tagCache_orderer_mastReqs_bag[469:465] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d340 = + tagLookup_tagCache_orderer_mastReqs_bag[411] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d343 = + tagLookup_tagCache_orderer_mastReqs_bag[410:406] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d347 = + tagLookup_tagCache_orderer_mastReqs_bag[352] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d350 = + tagLookup_tagCache_orderer_mastReqs_bag[351:347] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d354 = + tagLookup_tagCache_orderer_mastReqs_bag[293] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d357 = + tagLookup_tagCache_orderer_mastReqs_bag[292:288] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d361 = + tagLookup_tagCache_orderer_mastReqs_bag[234] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d364 = + tagLookup_tagCache_orderer_mastReqs_bag[233:229] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d368 = + tagLookup_tagCache_orderer_mastReqs_bag[175] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d371 = + tagLookup_tagCache_orderer_mastReqs_bag[174:170] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d375 = + tagLookup_tagCache_orderer_mastReqs_bag[116] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d378 = + tagLookup_tagCache_orderer_mastReqs_bag[115:111] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d382 = + tagLookup_tagCache_orderer_mastReqs_bag[57] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[57] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d385 = + tagLookup_tagCache_orderer_mastReqs_bag[56:52] == + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[56:52] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d3938 = + tagLookup_tagCache_orderer_mastReqs_bag[58] && + tagLookup_tagCache_orderer_mastReqs_bag[117] && + tagLookup_tagCache_orderer_mastReqs_bag[176] && + tagLookup_tagCache_orderer_mastReqs_bag[235] && + tagLookup_tagCache_orderer_mastReqs_bag[294] && + tagLookup_tagCache_orderer_mastReqs_bag[353] && + tagLookup_tagCache_orderer_mastReqs_bag[412] && + tagLookup_tagCache_orderer_mastReqs_bag[471] && + tagLookup_tagCache_orderer_mastReqs_bag[530] && + tagLookup_tagCache_orderer_mastReqs_bag[589] && + tagLookup_tagCache_orderer_mastReqs_bag[648] && + tagLookup_tagCache_orderer_mastReqs_bag[707] && + tagLookup_tagCache_orderer_mastReqs_bag[766] && + tagLookup_tagCache_orderer_mastReqs_bag[825] && + tagLookup_tagCache_orderer_mastReqs_bag[884] && + tagLookup_tagCache_orderer_mastReqs_bag[943] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d410 = + tagLookup_tagCache_orderer_mastReqs_bag[942] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d413 = + tagLookup_tagCache_orderer_mastReqs_bag[941:937] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d470 = + tagLookup_tagCache_orderer_mastReqs_bag[883] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d471 = + tagLookup_tagCache_orderer_mastReqs_bag[882:878] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d494 = + tagLookup_tagCache_orderer_mastReqs_bag[824] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d495 = + tagLookup_tagCache_orderer_mastReqs_bag[823:819] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d517 = + tagLookup_tagCache_orderer_mastReqs_bag[765] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d518 = + tagLookup_tagCache_orderer_mastReqs_bag[764:760] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d542 = + tagLookup_tagCache_orderer_mastReqs_bag[706] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d543 = + tagLookup_tagCache_orderer_mastReqs_bag[705:701] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d567 = + tagLookup_tagCache_orderer_mastReqs_bag[647] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d568 = + tagLookup_tagCache_orderer_mastReqs_bag[646:642] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d594 = + tagLookup_tagCache_orderer_mastReqs_bag[588] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d595 = + tagLookup_tagCache_orderer_mastReqs_bag[587:583] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d621 = + tagLookup_tagCache_orderer_mastReqs_bag[529] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d622 = + tagLookup_tagCache_orderer_mastReqs_bag[528:524] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d650 = + tagLookup_tagCache_orderer_mastReqs_bag[470] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d651 = + tagLookup_tagCache_orderer_mastReqs_bag[469:465] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d679 = + tagLookup_tagCache_orderer_mastReqs_bag[411] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d680 = + tagLookup_tagCache_orderer_mastReqs_bag[410:406] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d710 = + tagLookup_tagCache_orderer_mastReqs_bag[352] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d711 = + tagLookup_tagCache_orderer_mastReqs_bag[351:347] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d741 = + tagLookup_tagCache_orderer_mastReqs_bag[293] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d742 = + tagLookup_tagCache_orderer_mastReqs_bag[292:288] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d774 = + tagLookup_tagCache_orderer_mastReqs_bag[234] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d775 = + tagLookup_tagCache_orderer_mastReqs_bag[233:229] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d807 = + tagLookup_tagCache_orderer_mastReqs_bag[175] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d808 = + tagLookup_tagCache_orderer_mastReqs_bag[174:170] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d842 = + tagLookup_tagCache_orderer_mastReqs_bag[116] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d843 = + tagLookup_tagCache_orderer_mastReqs_bag[115:111] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d891 = + tagLookup_tagCache_orderer_mastReqs_bag[57] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[5] ; + assign tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d893 = + tagLookup_tagCache_orderer_mastReqs_bag[56:52] == + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[4:0] ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1303 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d275 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d280 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d469 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1306 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d284 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d287 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d483 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1311 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d291 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d294 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d507 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1317 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d298 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d301 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d531 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1324 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d305 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d308 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d557 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1332 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d312 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d315 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d583 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1341 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d319 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d322 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d611 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1351 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d326 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d329 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d639 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1362 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d333 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d336 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d669 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1374 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d340 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d343 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d699 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1387 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d347 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d350 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d731 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1401 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d354 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d357 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d763 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1416 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d361 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d364 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d797 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1432 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d368 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d371 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d831 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1449 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d375 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d378 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d867 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d1453 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d382 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d385 || + NOT_tagLookup_tagCache_orderer_mastReqs_remove_ETC___d898 ; + assign tagLookup_tagCache_orderer_mastReqs_insertItem_ETC___d403 = + tagLookup_tagCache_orderer_mastReqs_insertItem$whas && + tagLookup_tagCache_orderer_mastReqs_insertItem$wget[58] && + (!tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d275 || + !tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d280) && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d401 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1022 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d891 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d893 || + !tagLookup_tagCache_orderer_mastReqs_bag[58] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1173 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d747 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d780 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d813 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d848 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1179 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1173 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1189 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d747 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d780 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d813 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1195 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1189 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1204 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d747 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d780 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1210 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1204 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1218 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d747 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1224 = + (tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1218) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d780 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1231 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1243 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1254 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1264 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1273 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1281 = + (tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 || + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573) && + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d410 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d413 || + !tagLookup_tagCache_orderer_mastReqs_bag[943] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d470 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d471 || + !tagLookup_tagCache_orderer_mastReqs_bag[884] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d494 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d495 || + !tagLookup_tagCache_orderer_mastReqs_bag[825] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d517 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d518 || + !tagLookup_tagCache_orderer_mastReqs_bag[766] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d542 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d543 || + !tagLookup_tagCache_orderer_mastReqs_bag[707] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d567 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d568 || + !tagLookup_tagCache_orderer_mastReqs_bag[648] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d594 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d595 || + !tagLookup_tagCache_orderer_mastReqs_bag[589] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d621 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d622 || + !tagLookup_tagCache_orderer_mastReqs_bag[530] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d650 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d651 || + !tagLookup_tagCache_orderer_mastReqs_bag[471] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d679 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d680 || + !tagLookup_tagCache_orderer_mastReqs_bag[412] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d710 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d711 || + !tagLookup_tagCache_orderer_mastReqs_bag[353] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d747 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d741 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d742 || + !tagLookup_tagCache_orderer_mastReqs_bag[294] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d780 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d774 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d775 || + !tagLookup_tagCache_orderer_mastReqs_bag[235] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d813 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d807 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d808 || + !tagLookup_tagCache_orderer_mastReqs_bag[176] ; + assign tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d848 = + tagLookup_tagCache_orderer_mastReqs_removeItem$whas && + tagLookup_tagCache_orderer_mastReqs_removeItem$wget[6] && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d842 && + tagLookup_tagCache_orderer_mastReqs_bag_71_BIT_ETC___d843 || + !tagLookup_tagCache_orderer_mastReqs_bag[117] ; + assign tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2810 = + tagLookup_tagCache_orderer_slaveReqs_bag[58] && + tagLookup_tagCache_orderer_slaveReqs_bag[57] == + tagLookup_tagCache_newReq$wget[100] && + tagLookup_tagCache_orderer_slaveReqs_bag[56:52] == + tagLookup_tagCache_newReq$wget[99:95] ; + assign tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2849 = + tagLookup_tagCache_orderer_slaveReqs_bag[57] == + tagLookup_tagCache_cts[236] ; + assign tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2850 = + tagLookup_tagCache_orderer_slaveReqs_bag[56:52] == + tagLookup_tagCache_cts[235:231] ; + assign tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2963 = + tagLookup_tagCache_orderer_slaveReqs_bag[58] && + (!tagLookup_tagCache_orderer_mastLines_bag[671] || + !tagLookup_tagCache_orderer_mastLines_bag_462_B_ETC___d2900) && + NOT_tagLookup_tagCache_orderer_mastLines_bag_4_ETC___d2961 ; + assign tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3268 = + tagLookup_tagCache_orderer_slaveReqs_bag[57] == + tagLookup_tagCache_readReqReg[57] ; + assign tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3269 = + tagLookup_tagCache_orderer_slaveReqs_bag[56:52] == + tagLookup_tagCache_readReqReg[56:52] ; + assign tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3511 = + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2963 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3496 && + x_port1__read__h92294 != 5'd0 && + (IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3503 || + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509) ; + assign tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4086 = + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2963 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3496 && + x_port1__read__h92294 != 5'd0 && + !tagLookup_tagCache_writebacks$EMPTY_N ; + assign tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4348 = + tagLookup_tagCache_orderer_slaveReqs_bag[58] && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3268 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3269 && + tagLookup_tagCache_orderer_slaveReqs_bag[8:7] == + IF_tagLookup_tagCache_orderer_mastRespState_re_ETC___d3265 ; + assign tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4708 = + tagLookup_tagCache_orderer_slaveReqs_bag[58] && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2849 && + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2850 && + tagLookup_tagCache_orderer_slaveReqs_bag[8:7] == + tagLookup_tagCache_cts[100:99] ; + assign tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4724 = + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d2963 && + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3496 && + x_port1__read__h92294 != 5'd0 && + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1 || + tagLookup_tagCache_cts[143:140] != 4'd3) && + (tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1 || + tagLookup_tagCache_cts[143:140] != 4'd2) && + (SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 || + tagLookup_tagCache_cts[230]) ; + assign tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4732 = + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4724 || + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4086 && + !tagLookup_tagCache_invalidateWritebacks$EMPTY_N && + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3503 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4729 ; + assign tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d4740 = + tagLookup_tagCache_orderer_slaveReqs_bag_46_BI_ETC___d3511 && + !tagLookup_tagCache_writebacks$EMPTY_N && + !tagLookup_tagCache_invalidateWritebacks$EMPTY_N && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4739 ; + assign tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 = + tagLookup_tagCache_readReqReg[49:45] == + tagLookup_mRsps_ff_rf$D_OUT_1[75:71] ; + assign tagLookup_tagCache_readReqReg_read__136_BITS_5_ETC___d3164 = + tagLookup_tagCache_readReqReg[56:52] == + tagLookup_tagCache_orderer_slaveRespState[10:6] ; + assign tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 = + tagLookup_tagCache_readReqReg[50] == + tagLookup_mRsps_ff_rf$D_OUT_1[76] ; + assign tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3283 = + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66] && + (tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0 || + IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3274 && + !tagLookup_tagCache_readReqReg[51] && + x_port1__read__h92294 != 5'd0) ; + assign tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3299 = + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66] && + (tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0 && + tagLookup_mRsps_ff_rf$D_OUT_1[66] || + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d3297) ; + assign tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3942 = + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66] && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3855 ; + assign tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3948 = + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66] && + tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps_ff_l_ETC___d3946 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3855 ; + assign tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3956 = + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66] && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 && + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d3953 && + NOT_tagLookup_tagCache_orderer_mastReqs_bag_71_ETC___d3855 ; + assign tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d4989 = + tagLookup_tagCache_readReqReg_read__136_BIT_50_ETC___d3141 && + tagLookup_tagCache_readReqReg_read__136_BITS_4_ETC___d3145 && + tagLookup_tagCache_readReqReg[66] && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] != 2'd0 && + (tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps_ff_l_ETC___d3946 || + NOT_tagLookup_mRsps_ff_rf_sub_tagLookup_mRsps__ETC___d3953) ; + assign tagLookup_tagCache_readReqReg_read__136_BIT_57_ETC___d3162 = + tagLookup_tagCache_readReqReg[57] == + tagLookup_tagCache_orderer_slaveRespState[11] ; + assign tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5155 = + tagLookup_tagCache_cacheState && + tagLookup_tagCache_respsReady$wget && + tagLookup_tagCache_resps$wget[224:223] != 2'd0 && + level__h8616 != 2'd2 ; + assign tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334 = + (tagLookup_tagCache_cacheState && + tagLookup_tagCache_respsReady$wget || + level__h8616 != 2'd0) && + tagLookup_useNextRsp_ff_rf$D_OUT_1 ; + assign tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5377 = + (tagLookup_tagCache_cacheState && + tagLookup_tagCache_respsReady$wget || + level__h8616 != 2'd0) && + !tagLookup_useNextRsp_ff_rf$D_OUT_1 ; + assign tagLookup_tagCache_respswget_BITS_219_TO_156__q37 = + tagLookup_tagCache_resps$wget[219:156] ; + assign tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 = + tagLookup_tagCache_tags_0_readAddr == + tagLookup_tagCache_tags_0_writeAddr ; + assign tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 = + tagLookup_tagCache_tags_1_readAddr == + tagLookup_tagCache_tags_1_writeAddr ; + assign tagLookup_zeroAddr_211_ULT_4286574718___d5212 = + tagLookup_zeroAddr < 40'h00FF7FF07E ; + assign tagOnlyReads_lhead_read__990_MINUS_tagOnlyRead_ETC___d5992 = + tagOnlyReads_lhead - tagOnlyReads_ltail ; + assign way__h98147 = + (level__h1463 == 2'd0) ? + _theResult_____21__h86422 : + y_avValue_snd_fst__h98183 ; + assign wbitE__h303269 = + IF_tagLookup_tagCache_writeResps_ff_lhead_read_ETC___d5358 ? + 8'd0 : + 8'd255 ; + assign wdata_data__h307591 = { 56'd0, x__h307116 } << x__h308227 ; + assign wdata_data__h307595 = { 56'd0, x__h308249 } << x__h308368 ; + assign wdata_data__h307597 = 64'd0 << x__h308607 ; + assign wdata_data__h321116 = { 56'd0, x__h321179 } << x__h321366 ; + assign writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5907 = + writeBuffer_ff_rf$D_OUT_1[140:101] < 40'h00FF7DF080 ; + assign writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5909 = + writeBuffer_ff_rf$D_OUT_1[140:101] < 40'h00FFFFF000 ; + assign writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5911 = + writeBuffer_ff_rf$D_OUT_1[140:101] < 40'h00C0000000 ; + assign writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5912 = + writeBuffer_ff_rf$D_OUT_1[140:101] < 40'h00FFFFC000 ; + assign writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5920 = + writeBuffer_ff_rf$D_OUT_1[88:81] == 8'd0 || + !writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5907 && + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5909 || + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5911 || + !writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5912 ; + assign writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5942 = + writeBuffer_ff_rf$D_OUT_1[140:101] - 40'h00C0000000 ; + assign x1_avValue_data__h86313 = + (tagLookup_tagCache_data_0_readAddr[9:2] == + tagLookup_tagCache_data_0_writeAddr[9:2] && + tagLookup_tagCache_data_0_readAddr[1:0] == + tagLookup_tagCache_data_0_writeAddr[1:0]) ? + tagLookup_tagCache_data_0_writeData : + tagLookup_tagCache_data_0_bram_bram$DOA ; + assign x1_avValue_data__h86372 = + (tagLookup_tagCache_data_1_readAddr[9:2] == + tagLookup_tagCache_data_1_writeAddr[9:2] && + tagLookup_tagCache_data_1_readAddr[1:0] == + tagLookup_tagCache_data_1_writeAddr[1:0]) ? + tagLookup_tagCache_data_1_writeData : + tagLookup_tagCache_data_1_bram_bram$DOA ; + assign x1_avValue_fst_addr_lineNumber__h114874 = + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3509 ? + y_avValue_fst_addr_lineNumber__h114872 : + tagLookup_tagCache_cts[276:240] ; + assign x1_avValue_snd_addr_key__h74942 = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReqwget_BITS_140_TO_101__q20[12:5] : + tagLookup_tagCache_cts[249:242] ; + assign x1_avValue_snd_addr_tag__h74941 = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReqwget_BITS_140_TO_101__q20[39:13] : + tagLookup_tagCache_cts[276:250] ; + assign x1_avValue_snd_fst_key__h121113 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + y_avValue_snd_fst_key__h121088 : + tagLookup_tagCache_cts[108:101] ; + assign x1_avValue_snd_fst_way__h121115 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + y_avValue_snd_fst_way__h121090 : + _theResult_____21__h86422 ; + assign x1_avValue_snd_fst_way__h121202 = + (tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + _theResult_____21__h86422 : + x1_avValue_snd_way__h121184 ; + assign x1_avValue_snd_snd_snd_d_key__h278330 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + y_avValue_snd_fst_key__h121088 : + tagLookup_tagCache_readReqReg[65:58] ; + assign x1_avValue_snd_snd_snd_snd_d_inId_masterID__h278680 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + tagLookup_tagCache_cts[236] : + tagLookup_tagCache_readReqReg[57] ; + assign x1_avValue_snd_snd_snd_snd_d_inId_transactionID__h278681 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + tagLookup_tagCache_cts[235:231] : + tagLookup_tagCache_readReqReg[56:52] ; + assign x1_avValue_snd_snd_snd_snd_d_key__h278635 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + tagLookup_tagCache_cts[108:101] : + tagLookup_tagCache_readReqReg[65:58] ; + assign x1_avValue_snd_snd_snd_snd_d_oldWay__h278641 = + ((tagLookup_tagCache_cts[229:228] == 2'd0 || + tagLookup_tagCache_cts[229:228] == 2'd1) && + NOT_tagLookup_tagCache_cts_read__795_BITS_229__ETC___d3541 && + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d3566) ? + _theResult_____21__h86422 : + tagLookup_tagCache_readReqReg[2] ; + assign x1_avValue_snd_snd_snd_snd_snd_d_key__h278771 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + tagLookup_tagCache_readReqReg[65:58] : + x1_avValue_snd_snd_snd_snd_snd_snd_d_key__h278653 ; + assign x1_avValue_snd_snd_snd_snd_snd_snd_d_inId_masterID__h278682 = + NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read__351_ETC___d4676 ? + x1_avValue_snd_snd_snd_snd_d_inId_masterID__h278680 : + tagLookup_tagCache_readReqReg[57] ; + assign x1_avValue_snd_snd_snd_snd_snd_snd_d_inId_masterID__h278684 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + x1_avValue_snd_snd_snd_snd_snd_snd_d_inId_masterID__h278682 : + tagLookup_tagCache_readReqReg[57] ; + assign x1_avValue_snd_snd_snd_snd_snd_snd_d_inId_transactionID__h278683 = + NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read__351_ETC___d4676 ? + x1_avValue_snd_snd_snd_snd_d_inId_transactionID__h278681 : + tagLookup_tagCache_readReqReg[56:52] ; + assign x1_avValue_snd_snd_snd_snd_snd_snd_d_inId_transactionID__h278685 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + x1_avValue_snd_snd_snd_snd_snd_snd_d_inId_transactionID__h278683 : + tagLookup_tagCache_readReqReg[56:52] ; + assign x1_avValue_snd_snd_snd_snd_snd_snd_d_key__h278644 = + NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read__351_ETC___d4676 ? + x1_avValue_snd_snd_snd_snd_d_key__h278635 : + tagLookup_tagCache_readReqReg[65:58] ; + assign x1_avValue_snd_snd_snd_snd_snd_snd_d_key__h278653 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d3643 ? + x1_avValue_snd_snd_snd_snd_snd_snd_d_key__h278644 : + tagLookup_tagCache_readReqReg[65:58] ; + assign x1_avValue_snd_snd_snd_snd_snd_snd_d_oldWay__h278650 = + NOT_8_MINUS_tagLookup_mReqs_ff_lhead_read__351_ETC___d4676 ? + x1_avValue_snd_snd_snd_snd_d_oldWay__h278641 : + tagLookup_tagCache_readReqReg[2] ; + assign x1_avValue_snd_snd_snd_snd_snd_snd_fst_dataKey_key__h98516 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + tagLookup_tagCache_readReqReg[65:58] : + tagLookup_tagCache_cts[92:85] ; + assign x1_avValue_snd_snd_snd_snd_snd_snd_fst_req_masterID__h98350 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + tagLookup_tagCache_readReqReg[57] : + tagLookup_tagCache_cts[236] ; + assign x1_avValue_snd_snd_snd_snd_snd_snd_fst_req_transactionID__h98351 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + tagLookup_tagCache_readReqReg[56:52] : + tagLookup_tagCache_cts[235:231] ; + assign x1_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_fst_d_inId_masterID__h278688 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + tagLookup_tagCache_readReqReg[57] : + x1_avValue_snd_snd_snd_snd_snd_snd_d_inId_masterID__h278684 ; + assign x1_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_fst_d_inId_transactionID__h278689 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + tagLookup_tagCache_readReqReg[56:52] : + x1_avValue_snd_snd_snd_snd_snd_snd_d_inId_transactionID__h278685 ; + assign x1_avValue_snd_way__h121184 = + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193 ? + way__h98147 : + _theResult_____21__h86422 ; + assign x1_avValue_snd_writebackTag_tag__h81268 = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + 27'd0 : + tagLookup_tagCache_cts[42:16] ; + assign x1_avValue_tag__h84378 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[40:14] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[40:14] ; + assign x1_avValue_tag__h84438 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[40:14] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[40:14] ; + assign x1_avValue_way__h74757 = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141] || + tagLookup_mRsps_ff_lhead_read__894_MINUS_tagLo_ETC___d2965) ? + _theResult_____3_way__h74739 : + tagLookup_tagCache_nextWay ; + assign x__h102652 = 4'd8 - level__h1012 ; + assign x__h117048 = + (tagLookup_tagCache_cts[229:228] != 2'd0 && + tagLookup_tagCache_cts[229:228] != 2'd1 || + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d3683) ? + tagLookup_tagCache_cts[276:240] : + x1_avValue_fst_addr_lineNumber__h114874 ; + assign x__h118925 = + tagLookup_tagCache_cts[207:200] & + tagLookup_tagCache_cts[216:209] ; + assign x__h119258 = + tagLookup_tagCache_cts[199:192] & + tagLookup_tagCache_cts[216:209] ; + assign x__h119397 = + tagLookup_tagCache_cts[191:184] & + tagLookup_tagCache_cts[216:209] ; + assign x__h119536 = + tagLookup_tagCache_cts[183:176] & + tagLookup_tagCache_cts[216:209] ; + assign x__h119675 = + tagLookup_tagCache_cts[175:168] & + tagLookup_tagCache_cts[216:209] ; + assign x__h119814 = + tagLookup_tagCache_cts[167:160] & + tagLookup_tagCache_cts[216:209] ; + assign x__h119953 = + tagLookup_tagCache_cts[159:152] & + tagLookup_tagCache_cts[216:209] ; + assign x__h120092 = + tagLookup_tagCache_cts[151:144] & + tagLookup_tagCache_cts[216:209] ; + assign x__h122813 = + (level__h1463 == 2'd0) ? + tagLookup_tagCache_cts[100:99] : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4363 ; + assign x__h135259 = + (level__h1463 == 2'd0) ? + tagLookup_tagCache_cts[84:83] : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4511 ; + assign x__h303703 = + tagLookup_pendingCapNumber >> + CASE_tagLookup_currentDepth_338_MINUS_1_481_0__ETC__q13 ; + assign x__h303814 = + tagLookup_pendingCapNumber >> + CASE_tagLookup_currentDepth_0_0_1_6_DONTCARE__q3 ; + assign x__h306917 = + (tagLookup_state == 3'd3 && + tagLookup_tagCache_respsReady_whas__145_AND_ta_ETC___d5334) ? + bitEnable__h303984 : + IF_tagLookup_state_read__216_EQ_4_326_AND_tagL_ETC___d5682 ; + assign x__h307116 = 8'd1 << x__h303703[2:0] ; + assign x__h308227 = + { _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5490[2:0], + 3'b0 } ; + assign x__h308249 = + (tagLookup_pendingTags && tagLookup_pendingCapEnable) ? + _1_SL_tagLookup_pendingCapNumber_343_BITS_2_TO__ETC___d5671 : + 8'd0 ; + assign x__h308368 = + { _0_CONCAT_tagLookup_pendingCapNumber_343_BITS_3_ETC___d5493[2:0], + 3'b0 } ; + assign x__h308607 = + { _0_CONCAT_tagLookup_pendingCapNumber_343_SRL_SE_ETC___d5354[2:0], + 3'b0 } ; + assign x__h320966 = + 8'd1 << + writeBuffer_ff_rf_sub_writeBuffer_ff_ltail_rea_ETC___d5942[12:10] ; + assign x__h321179 = + (writeBuffer_ff_rf$D_OUT_1[72] && + writeBuffer_ff_rf$D_OUT_1[88:81] != 8'd0) ? + x__h320966 : + 8'd0 ; + assign x__h321366 = + { _0_CONCAT_writeBuffer_ff_rf_sub_writeBuffer_ff__ETC___d5950[2:0], + 3'b0 } ; + assign x__h323598 = + (cache_request_put_val[93:92] == 2'd1 && + !cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6013 && + cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6014) ? + 8'd0 : + cache_request_put_val[80:73] ; + assign x__h330273 = + (level__h314581 == 6'd0) ? + _theResult___snd_snd_fst_masterID__h330322 : + mRsps_ff_rf$D_OUT_1[76] ; + assign x__h330335 = + (level__h314581 == 6'd0) ? + _theResult___snd_snd_fst_transactionID__h330323 : + mRsps_ff_rf$D_OUT_1[75:71] ; + assign x__h330808 = addrFrame_bag[7:6] + frame[2:1] ; + assign x__h332332 = frame + 3'd1 ; + assign x__h72111 = tagLookup_tagCache_initCount + 8'd1 ; + assign x__h78976 = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReq$wget[100] : + tagLookup_tagCache_cts[236] ; + assign x__h78979 = + (CAN_FIRE_RL_tagLookup_feedTagCache && + tagLookup_tagCache_newReq$wget[141]) ? + tagLookup_tagCache_newReq$wget[99:95] : + tagLookup_tagCache_cts[235:231] ; + assign x_lineNumber__h292967 = tagLookup_zeroAddr[39:3] + 37'd1 ; + assign x_mastReqsSpaces__h53162 = 5'd16 - x_remaining__h53145 ; + assign x_port1__read__h92294 = + (tagLookup_tagCache_req_commits_level != 5'd16) ? + tagLookup_tagCache_req_commits_level$port0__write_1 : + tagLookup_tagCache_req_commits_level ; + assign x_remaining__h53145 = + 5'd16 - tagLookup_tagCache_orderer_mastReqIds_lhead ; + assign y__h118926 = cacheResp_data_data__h284964[63:56] & y__h119151 ; + assign y__h119151 = ~tagLookup_tagCache_cts[216:209] ; + assign y__h119259 = cacheResp_data_data__h284964[55:48] & y__h119151 ; + assign y__h119398 = cacheResp_data_data__h284964[47:40] & y__h119151 ; + assign y__h119537 = cacheResp_data_data__h284964[39:32] & y__h119151 ; + assign y__h119676 = cacheResp_data_data__h284964[31:24] & y__h119151 ; + assign y__h119815 = cacheResp_data_data__h284964[23:16] & y__h119151 ; + assign y__h119954 = cacheResp_data_data__h284964[15:8] & y__h119151 ; + assign y__h120093 = cacheResp_data_data__h284964[7:0] & y__h119151 ; + assign y__h304733 = + 3'd7 << CASE_tagLookup_currentDepth_0_4294967293_1_3_D_ETC__q2 ; + assign y__h307071 = + ~_1_SL_tagLookup_pendingCapNumber_343_BITS_2_TO__ETC___d5671 ; + assign y_avValue_fst_addr_lineNumber__h114872 = + { tagLookup_tagCache_cts[135:101], 2'd0 } ; + assign y_avValue_snd_fst__h98183 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + tagLookup_tagCache_readReqReg[2] : + _theResult_____21__h86422 ; + assign y_avValue_snd_fst_key__h121088 = + (level__h1463 == 2'd0) ? + tagLookup_tagCache_cts[92:85] : + x1_avValue_snd_snd_snd_snd_snd_snd_fst_dataKey_key__h98516 ; + assign y_avValue_snd_fst_way__h121090 = + (IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d3971 && + tagLookup_mRsps_ff_rf$D_OUT_1[68:67] == 2'd0) ? + x1_avValue_snd_way__h121184 : + x1_avValue_snd_fst_way__h121202 ; + assign y_avValue_snd_snd_snd_newTag_tag__h121536 = + (IF_tagLookup_tagCache_orderer_slaveRespState_r_ETC___d3561 && + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4117 || + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4219) ? + (IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4233 ? + 27'd0 : + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4296) : + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4296 ; + always@(mReqs_ff_rf$D_OUT_1) + begin + case (mReqs_ff_rf$D_OUT_1[93:92]) + 2'd0, 2'd1: + CASE_mReqs_ff_rfD_OUT_1_BITS_93_TO_92_0_mReqs_ETC__q1 = + mReqs_ff_rf$D_OUT_1[93:92]; + default: CASE_mReqs_ff_rfD_OUT_1_BITS_93_TO_92_0_mReqs_ETC__q1 = 2'd2; + endcase + end + always@(tagLookup_currentDepth) + begin + case (tagLookup_currentDepth) + 2'd0: + CASE_tagLookup_currentDepth_0_4294967293_1_3_D_ETC__q2 = + 32'hFFFFFFFD; + 2'd1: CASE_tagLookup_currentDepth_0_4294967293_1_3_D_ETC__q2 = 32'd3; + default: CASE_tagLookup_currentDepth_0_4294967293_1_3_D_ETC__q2 = + 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + always@(tagLookup_currentDepth) + begin + case (tagLookup_currentDepth) + 2'd0: CASE_tagLookup_currentDepth_0_0_1_6_DONTCARE__q3 = 32'd0; + 2'd1: CASE_tagLookup_currentDepth_0_0_1_6_DONTCARE__q3 = 32'd6; + default: CASE_tagLookup_currentDepth_0_0_1_6_DONTCARE__q3 = + 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + always@(tagLookup_tagCache_cts or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3431 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3434 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3437 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3440) + begin + case (tagLookup_tagCache_cts[100:99]) + 2'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3431; + 2'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3434; + 2'd2: + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3437; + 2'd3: + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3440; + endcase + end + always@(tagLookup_tagCache_cts or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3465 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3468 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3471 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3474) + begin + case (tagLookup_tagCache_cts[100:99]) + 2'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3465; + 2'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3468; + 2'd2: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3471; + 2'd3: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3474; + endcase + end + always@(_theResult_____23__h86225 or + x1_avValue_data__h86313 or x1_avValue_data__h86372) + begin + case (_theResult_____23__h86225) + 1'd0: cacheResp_data_data__h284964 = x1_avValue_data__h86313; + 1'd1: cacheResp_data_data__h284964 = x1_avValue_data__h86372; + endcase + end + always@(_theResult_____21__h86422 or + x1_avValue_tag__h84378 or x1_avValue_tag__h84438) + begin + case (_theResult_____21__h86422) + 1'd0: x_addr_tag__h102720 = x1_avValue_tag__h84378; + 1'd1: x_addr_tag__h102720 = x1_avValue_tag__h84438; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3496 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + !tagLookup_tagCache_tags_0_writeData[4] : + !tagLookup_tagCache_tags_0_bramA_bram$DOA[4]; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3496 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + !tagLookup_tagCache_tags_1_writeData[4] : + !tagLookup_tagCache_tags_1_bramA_bram$DOA[4]; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[13] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[13]; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[13] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[13]; + endcase + end + always@(_theResult_____21__h86422 or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488 or + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d3614 = + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3488; + 1'd1: + SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d3614 = + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d3455; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[12] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[12]; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[12] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[12]; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[11] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[11]; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[11] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[11]; + endcase + end + always@(_theResult_____21__h86422 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4050 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4053) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4050; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4053; + endcase + end + always@(_theResult_____21__h86422 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4058 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4061) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4058; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4061; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4047 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[4] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[4]; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4047 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[4] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[4]; + endcase + end + always@(tagLookup_tagCache_cts or + _theResult_____21__h86422 or x1_avValue_snd_fst_way__h121115) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd1: x__h121243 = _theResult_____21__h86422; + 2'd2: x__h121243 = x1_avValue_snd_fst_way__h121115; + default: x__h121243 = _theResult_____21__h86422; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[10] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[10]; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[10] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[10]; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + tagLookup_tagCache_tags_0_writeData[9] : + tagLookup_tagCache_tags_0_bramA_bram$DOA[9]; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + tagLookup_tagCache_tags_1_writeData[9] : + tagLookup_tagCache_tags_1_bramA_bram$DOA[9]; + endcase + end + always@(_theResult_____21__h86422 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3474 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3440) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3474; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3440; + endcase + end + always@(_theResult_____21__h86422 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3471 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3437) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3471; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3437; + endcase + end + always@(_theResult_____21__h86422 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3468 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3434) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3468; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3434; + endcase + end + always@(_theResult_____21__h86422 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3465 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3431) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d3465; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d3431; + endcase + end + always@(tagLookup_tagCache_cts or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4075 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4067 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4058 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4050) + begin + case (tagLookup_tagCache_cts[100:99]) + 2'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4538 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4075; + 2'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4538 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4067; + 2'd2: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4538 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4058; + 2'd3: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4538 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4050; + endcase + end + always@(tagLookup_tagCache_cts or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4078 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4070 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4061 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4053) + begin + case (tagLookup_tagCache_cts[100:99]) + 2'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d4540 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4078; + 2'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d4540 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4070; + 2'd2: + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d4540 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4061; + 2'd3: + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d4540 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4053; + endcase + end + always@(_theResult_____21__h86422 or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4538 or + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d4540) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d4542 = + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4538; + 1'd1: + SEL_ARR_SEL_ARR_IF_tagLookup_tagCache_tags_0_r_ETC___d4542 = + SEL_ARR_IF_tagLookup_tagCache_tags_1_readAddr__ETC___d4540; + endcase + end + always@(_theResult_____21__h86422 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4067 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4070) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4067; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4070; + endcase + end + always@(_theResult_____21__h86422 or + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4075 or + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4078) + begin + case (_theResult_____21__h86422) + 1'd0: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 = + IF_tagLookup_tagCache_tags_0_readAddr_read__40_ETC___d4075; + 1'd1: + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 = + IF_tagLookup_tagCache_tags_1_readAddr_read__41_ETC___d4078; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q5 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + !tagLookup_tagCache_tags_0_writeData[11] : + !tagLookup_tagCache_tags_0_bramA_bram$DOA[11]; + 1'd1: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q5 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + !tagLookup_tagCache_tags_1_writeData[11] : + !tagLookup_tagCache_tags_1_bramA_bram$DOA[11]; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q6 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + !tagLookup_tagCache_tags_0_writeData[10] : + !tagLookup_tagCache_tags_0_bramA_bram$DOA[10]; + 1'd1: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q6 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + !tagLookup_tagCache_tags_1_writeData[10] : + !tagLookup_tagCache_tags_1_bramA_bram$DOA[10]; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q7 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + !tagLookup_tagCache_tags_0_writeData[9] : + !tagLookup_tagCache_tags_0_bramA_bram$DOA[9]; + 1'd1: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q7 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + !tagLookup_tagCache_tags_1_writeData[9] : + !tagLookup_tagCache_tags_1_bramA_bram$DOA[9]; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q8 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + !tagLookup_tagCache_tags_0_writeData[8] : + !tagLookup_tagCache_tags_0_bramA_bram$DOA[8]; + 1'd1: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q8 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + !tagLookup_tagCache_tags_1_writeData[8] : + !tagLookup_tagCache_tags_1_bramA_bram$DOA[8]; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q9 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + !tagLookup_tagCache_tags_0_writeData[7] : + !tagLookup_tagCache_tags_0_bramA_bram$DOA[7]; + 1'd1: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q9 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + !tagLookup_tagCache_tags_1_writeData[7] : + !tagLookup_tagCache_tags_1_bramA_bram$DOA[7]; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q10 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + !tagLookup_tagCache_tags_0_writeData[6] : + !tagLookup_tagCache_tags_0_bramA_bram$DOA[6]; + 1'd1: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q10 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + !tagLookup_tagCache_tags_1_writeData[6] : + !tagLookup_tagCache_tags_1_bramA_bram$DOA[6]; + endcase + end + always@(_theResult_____21__h86422 or + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 or + tagLookup_tagCache_tags_0_writeData or + tagLookup_tagCache_tags_0_bramA_bram$DOA or + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 or + tagLookup_tagCache_tags_1_writeData or + tagLookup_tagCache_tags_1_bramA_bram$DOA) + begin + case (_theResult_____21__h86422) + 1'd0: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q11 = + tagLookup_tagCache_tags_0_readAddr_read__401_E_ETC___d3403 ? + !tagLookup_tagCache_tags_0_writeData[5] : + !tagLookup_tagCache_tags_0_bramA_bram$DOA[5]; + 1'd1: + CASE_theResult_____216422_0_IF_tagLookup_tagCa_ETC__q11 = + tagLookup_tagCache_tags_1_readAddr_read__411_E_ETC___d3413 ? + !tagLookup_tagCache_tags_1_writeData[5] : + !tagLookup_tagCache_tags_1_bramA_bram$DOA[5]; + endcase + end + always@(tagLookup_currentDepth) + begin + case (tagLookup_currentDepth) + 2'd0: + CASE_tagLookup_currentDepth_0_535821840_1_5358_ETC__q12 = + 37'd535821840; + 2'd1: + CASE_tagLookup_currentDepth_0_535821840_1_5358_ETC__q12 = + 37'd535805456; + default: CASE_tagLookup_currentDepth_0_535821840_1_5358_ETC__q12 = + 37'h0AAAAAAAAA /* unspecified value */ ; + endcase + end + always@(tagLookup_currentDepth_338_MINUS_1___d5481) + begin + case (tagLookup_currentDepth_338_MINUS_1___d5481) + 2'd0: CASE_tagLookup_currentDepth_338_MINUS_1_481_0__ETC__q13 = 32'd0; + 2'd1: CASE_tagLookup_currentDepth_338_MINUS_1_481_0__ETC__q13 = 32'd6; + default: CASE_tagLookup_currentDepth_338_MINUS_1_481_0__ETC__q13 = + 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + always@(tagLookup_currentDepth) + begin + case (tagLookup_currentDepth) + 2'd0: SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 = 1'd0; + 2'd1: SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 = 1'd1; + default: SEL_ARR_0_1_504_tagLookup_currentDepth_338___d5505 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(tagLookup_currentDepth_338_MINUS_1___d5481) + begin + case (tagLookup_currentDepth_338_MINUS_1___d5481) + 2'd0: + CASE_tagLookup_currentDepth_338_MINUS_1_481_0__ETC__q14 = + 37'd535821840; + 2'd1: + CASE_tagLookup_currentDepth_338_MINUS_1_481_0__ETC__q14 = + 37'd535805456; + default: CASE_tagLookup_currentDepth_338_MINUS_1_481_0__ETC__q14 = + 37'h0AAAAAAAAA /* unspecified value */ ; + endcase + end + always@(x__h330808 or lookupRsp_bag) + begin + case (x__h330808) + 2'd0: + CASE_x30808_0_lookupRsp_bag_BIT_0_1_lookupRsp__ETC__q15 = + lookupRsp_bag[0]; + 2'd1: + CASE_x30808_0_lookupRsp_bag_BIT_0_1_lookupRsp__ETC__q15 = + lookupRsp_bag[1]; + 2'd2: + CASE_x30808_0_lookupRsp_bag_BIT_0_1_lookupRsp__ETC__q15 = + lookupRsp_bag[2]; + 2'd3: + CASE_x30808_0_lookupRsp_bag_BIT_0_1_lookupRsp__ETC__q15 = + lookupRsp_bag[3]; + endcase + end + always@(cache_request_put_val or + cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6013 or + cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6014 or + x__h323598) + begin + case (cache_request_put_val[93:92]) + 2'd0: + IF_cache_request_put_val_BITS_93_TO_92_997_EQ__ETC___d6049 = + cache_request_put_val[93:0]; + 2'd1: + IF_cache_request_put_val_BITS_93_TO_92_997_EQ__ETC___d6049 = + { cache_request_put_val[93:89], + (cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6013 || + !cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6014) && + cache_request_put_val[88], + (cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6013 || + !cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6014) && + cache_request_put_val[87], + (cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6013 || + !cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6014) && + cache_request_put_val[86], + (cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6013 || + !cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6014) && + cache_request_put_val[85], + (cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6013 || + !cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6014) && + cache_request_put_val[84], + (cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6013 || + !cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6014) && + cache_request_put_val[83], + (cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6013 || + !cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6014) && + cache_request_put_val[82], + (cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6013 || + !cache_request_put_val_BITS_140_TO_101_012_ULT__ETC___d6014) && + cache_request_put_val[81], + x__h323598, + cache_request_put_val[72:0] }; + default: IF_cache_request_put_val_BITS_93_TO_92_997_EQ__ETC___d6049 = + { 2'd2, cache_request_put_val[91:0] }; + endcase + end + always@(tagLookup_tagCache_cts) + begin + case (tagLookup_tagCache_cts[100:99]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_100_TO_99_0_t_ETC__q16 = + tagLookup_tagCache_cts[2]; + 2'd1: + CASE_tagLookup_tagCache_cts_BITS_100_TO_99_0_t_ETC__q16 = + tagLookup_tagCache_cts[3]; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_100_TO_99_0_t_ETC__q16 = + tagLookup_tagCache_cts[4]; + 2'd3: + CASE_tagLookup_tagCache_cts_BITS_100_TO_99_0_t_ETC__q16 = + tagLookup_tagCache_cts[5]; + endcase + end + always@(tagLookup_currentDepth or + tagLookup_oldTags_0 or tagLookup_oldTags_1) + begin + case (tagLookup_currentDepth) + 2'd0: + CASE_tagLookup_currentDepth_0_tagLookup_oldTag_ETC__q17 = + tagLookup_oldTags_0; + 2'd1: + CASE_tagLookup_currentDepth_0_tagLookup_oldTag_ETC__q17 = + tagLookup_oldTags_1; + default: CASE_tagLookup_currentDepth_0_tagLookup_oldTag_ETC__q17 = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + always@(tagLookup_mReqs_ff_rf$D_OUT_1) + begin + case (tagLookup_mReqs_ff_rf$D_OUT_1[93:92]) + 2'd0, 2'd1: + CASE_tagLookup_mReqs_ff_rfD_OUT_1_BITS_93_TO__ETC__q18 = + tagLookup_mReqs_ff_rf$D_OUT_1[93:92]; + default: CASE_tagLookup_mReqs_ff_rfD_OUT_1_BITS_93_TO__ETC__q18 = 2'd2; + endcase + end + always@(tagLookup_tagCache_cts or + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4715) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd1: x__h284313 = tagLookup_tagCache_cts[236]; + 2'd2: + x__h284313 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4715; + default: x__h284313 = tagLookup_tagCache_cts[236]; + endcase + end + always@(tagLookup_tagCache_cts or + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4718) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd1: x__h284335 = tagLookup_tagCache_cts[235:231]; + 2'd2: + x__h284335 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4718; + default: x__h284335 = tagLookup_tagCache_cts[235:231]; + endcase + end + always@(tagLookup_tagCacheReq_ff_rf) + begin + case (tagLookup_tagCacheReq_ff_rf[93:92]) + 2'd0, 2'd1: + CASE_tagLookup_tagCacheReq_ff_rf_BITS_93_TO_92_ETC__q19 = + tagLookup_tagCacheReq_ff_rf[93:92]; + default: CASE_tagLookup_tagCacheReq_ff_rf_BITS_93_TO_92_ETC__q19 = 2'd2; + endcase + end + always@(tagLookup_tagCache_req_commits_tail or + tagLookup_tagCache_req_commits_rf$port1__read) + begin + case (tagLookup_tagCache_req_commits_tail) + 4'd0: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[0]; + 4'd1: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[1]; + 4'd2: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[2]; + 4'd3: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[3]; + 4'd4: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[4]; + 4'd5: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[5]; + 4'd6: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[6]; + 4'd7: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[7]; + 4'd8: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[8]; + 4'd9: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[9]; + 4'd10: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[10]; + 4'd11: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[11]; + 4'd12: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[12]; + 4'd13: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[13]; + 4'd14: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[14]; + 4'd15: + SEL_ARR_NOT_tagLookup_tagCache_req_commits_rf__ETC___d3395 = + !tagLookup_tagCache_req_commits_rf$port1__read[15]; + endcase + end + always@(tagLookup_tagCache_cts or + tagLookup_tagCache_readReqReg or + x1_avValue_snd_snd_snd_snd_snd_d_key__h278771 or + _theResult_____3_snd_snd_snd_snd_snd_d_key__h278742) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + x1_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_d_key__h278782 = + x1_avValue_snd_snd_snd_snd_snd_d_key__h278771; + 2'd1, 2'd3: + x1_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_d_key__h278782 = + tagLookup_tagCache_readReqReg[65:58]; + 2'd2: + x1_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd_d_key__h278782 = + _theResult_____3_snd_snd_snd_snd_snd_d_key__h278742; + endcase + end + always@(tagLookup_tagCache_cts or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025 or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027 or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030 or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032 or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035 or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037 or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040 or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 or + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4487 or + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 or + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4385 or + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4387) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4490 = + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4487; + 2'd1, 2'd3: + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4490 = + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4025, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4027, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4030, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4032, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4035, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4037, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4040, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4042 }; + 2'd2: + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4490 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4385 : + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4387; + endcase + end + always@(tagLookup_tagCache_cts or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055 or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063 or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072 or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 or + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4640 or + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 or + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4530 or + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4532) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4642 = + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4640; + 2'd2: + IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4642 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4530 : + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4532; + default: IF_tagLookup_tagCache_cts_read__795_BITS_278_T_ETC___d4642 = + { SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4055, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4063, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4072, + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4080 }; + endcase + end + always@(tagLookup_tagCache_cts or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4047 or + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 or + IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4505 or + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 or + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4494 or + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q21 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4047 : + IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4505; + 2'd1, 2'd3: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q21 = + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d4047; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q21 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4494 : + IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ta_ETC___d4193; + endcase + end + always@(tagLookup_tagCache_cts or + level__h1463 or + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d5042) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd1: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_1__ETC__q22 = + tagLookup_tagCache_cts[236:231]; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_1__ETC__q22 = + (level__h1463 == 2'd0) ? + tagLookup_tagCache_cts[236:231] : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d5042; + default: CASE_tagLookup_tagCache_cts_BITS_278_TO_277_1__ETC__q22 = + tagLookup_tagCache_cts[236:231]; + endcase + end + always@(tagLookup_tagCache_cts or + tagLookup_tagCache_readReqReg or + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4795) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q23 = + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4795; + 2'd1, 2'd2, 2'd3: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q23 = + tagLookup_tagCache_readReqReg[16]; + endcase + end + always@(tagLookup_tagCache_cts or + tagLookup_tagCache_readReqReg or + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4807 or + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 or + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4801) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q24 = + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4807; + 2'd1, 2'd3: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q24 = + tagLookup_tagCache_readReqReg[15:3]; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q24 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4801 : + tagLookup_tagCache_readReqReg[15:3]; + endcase + end + always@(tagLookup_tagCache_cts or + tagLookup_tagCache_readReqReg or + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4788 or + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 or + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4783) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q25 = + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4788; + 2'd1, 2'd3: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q25 = + tagLookup_tagCache_readReqReg[43:17]; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q25 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4783 : + tagLookup_tagCache_readReqReg[43:17]; + endcase + end + always@(tagLookup_tagCache_cts or + tagLookup_tagCache_readReqReg or + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 or + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4937 or + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 or + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4864) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q26 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + tagLookup_tagCache_readReqReg[2:0] : + IF_IF_NOT_tagLookup_tagCache_cts_read__795_BIT_ETC___d4937; + 2'd1, 2'd3: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q26 = + tagLookup_tagCache_readReqReg[2:0]; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q26 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4864 : + tagLookup_tagCache_readReqReg[2:0]; + endcase + end + always@(tagLookup_tagCache_cts or + tagLookup_tagCache_readReqReg or + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4771) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q27 = + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4771; + 2'd1, 2'd2, 2'd3: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q27 = + tagLookup_tagCache_readReqReg[50:45]; + endcase + end + always@(tagLookup_tagCache_cts or + tagLookup_tagCache_readReqReg or + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4779 or + IF_NOT_tagLookup_mRsps_ff_lhead_read__894_MINU_ETC___d4775) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q28 = + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4779; + 2'd1, 2'd3: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q28 = + tagLookup_tagCache_readReqReg[44]; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q28 = + IF_NOT_tagLookup_mRsps_ff_lhead_read__894_MINU_ETC___d4775; + endcase + end + always@(tagLookup_tagCache_cts or + tagLookup_tagCache_readReqReg or + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4689) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q29 = + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4689; + 2'd1, 2'd2, 2'd3: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q29 = + tagLookup_tagCache_readReqReg[57:52]; + endcase + end + always@(tagLookup_tagCache_cts or + tagLookup_tagCache_readReqReg or + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d4762 or + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4723) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q30 = + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d4762; + 2'd1, 2'd3: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q30 = + tagLookup_tagCache_readReqReg[51]; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q30 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4723; + endcase + end + always@(tagLookup_tagCache_cts or + tagLookup_mRsps_ff_rf$D_OUT_1 or + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d5028) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q31 = + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d5028; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q31 = + tagLookup_mRsps_ff_rf$D_OUT_1[65]; + default: CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q31 = + tagLookup_mRsps_ff_rf$D_OUT_1[65]; + endcase + end + always@(tagLookup_tagCache_cts or + tagLookup_mRsps_ff_rf$D_OUT_1 or + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d5005 or + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4996) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q32 = + IF_tagLookup_tagCache_orderer_slaveReqs_bag_46_ETC___d5005; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q32 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d4996; + default: CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q32 = + tagLookup_mRsps_ff_rf$D_OUT_1[66:65]; + endcase + end + always@(tagLookup_tagCache_cts or + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d5044) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd1: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_1__ETC__q33 = + tagLookup_tagCache_cts[236:231]; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_1__ETC__q33 = + IF_NOT_tagLookup_tagCache_cts_read__795_BITS_2_ETC___d5044; + default: CASE_tagLookup_tagCache_cts_BITS_278_TO_277_1__ETC__q33 = + tagLookup_tagCache_cts[236:231]; + endcase + end + always@(tagLookup_tagCache_cts or + x_addr_tag__h102720 or + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4306 or + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 or + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4267 or + _theResult_____1_tag__h121522) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q34 = + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4306; + 2'd1, 2'd3: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q34 = + x_addr_tag__h102720; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q34 = + NOT_tagLookup_mRsps_ff_lhead_read__894_MINUS_t_ETC___d3964 ? + IF_IF_tagLookup_mRsps_ff_lhead_read__894_MINUS_ETC___d4267 : + _theResult_____1_tag__h121522; + endcase + end + always@(tagLookup_tagCache_cts or + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 or + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 or + IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4339 or + level__h1463 or + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4311) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q35 = + tagLookup_tagCache_cts_read__795_BITS_229_TO_2_ETC___d4282 ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 : + IF_IF_tagLookup_tagCache_orderer_slaveRespStat_ETC___d4339; + 2'd1, 2'd3: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q35 = + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q35 = + (level__h1463 == 2'd0) ? + SEL_ARR_IF_tagLookup_tagCache_tags_0_readAddr__ETC___d3530 : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4311; + endcase + end + always@(tagLookup_tagCache_cts) + begin + case (tagLookup_tagCache_cts[229:228]) + 2'd0, 2'd1: + CASE_tagLookup_tagCache_cts_BITS_229_TO_228_0__ETC__q36 = + tagLookup_tagCache_cts[229:228]; + default: CASE_tagLookup_tagCache_cts_BITS_229_TO_228_0__ETC__q36 = 2'd2; + endcase + end + always@(tagLookup_currentDepth or tagLookup_state) + begin + case (tagLookup_currentDepth) + 2'd0, 2'd1: + CASE_tagLookup_currentDepth_0_1_1_1_tagLookup__ETC__q38 = 3'd1; + default: CASE_tagLookup_currentDepth_0_1_1_1_tagLookup__ETC__q38 = + tagLookup_state; + endcase + end + always@(tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1022 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d848 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d813 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d780 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d747 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418) + begin + case (tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg) + 4'd0: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1022; + 4'd1: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d848; + 4'd2: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d813; + 4'd3: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d780; + 4'd4: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d747; + 4'd5: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716; + 4'd6: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685; + 4'd7: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656; + 4'd8: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627; + 4'd9: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600; + 4'd10: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573; + 4'd11: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548; + 4'd12: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523; + 4'd13: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500; + 4'd14: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476; + 4'd15: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1024 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418; + endcase + end + always@(tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1027 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1001 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d999 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d997 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d995 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d993 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d991 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d989 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d987 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d985 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d983 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d981 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d979 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d977 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d975 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d973) + begin + case (tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg) + 4'd0: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1027; + 4'd1: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1001; + 4'd2: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d999; + 4'd3: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d997; + 4'd4: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d995; + 4'd5: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d993; + 4'd6: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d991; + 4'd7: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d989; + 4'd8: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d987; + 4'd9: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d985; + 4'd10: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d983; + 4'd11: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d981; + 4'd12: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d979; + 4'd13: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d977; + 4'd14: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d975; + 4'd15: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1029 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d973; + endcase + end + always@(idx__h31676 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h31676) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1055 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h31792 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h31792) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1061 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h31908 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h31908) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1067 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h32024 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h32024) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1073 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h32140 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h32140) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1079 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h32256 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h32256) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1085 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h32372 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h32372) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1091 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h32488 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h32488) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1097 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h32720 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h32720) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1109 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h32604 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h32604) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1103 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h32836 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h32836) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1115 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h32952 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h32952) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1121 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h33068 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h33068) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1127 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h33184 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h33184) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1133 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(idx__h33300 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (idx__h33300) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1139 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052 or + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053) + begin + case (tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1038; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1039; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1040; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1041; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1042; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1043; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1044; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1045; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1046; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1047; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1048; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1049; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1050; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1051; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1052; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastReqs_ETC___d1142 = + IF_tagLookup_tagCache_orderer_mastReqs_insertI_ETC___d1053; + endcase + end + always@(_theResult_____1__h31534 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1022 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d848 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d813 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d780 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d747 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476 or + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418) + begin + case (_theResult_____1__h31534) + 4'd0: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d1022; + 4'd1: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d848; + 4'd2: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d813; + 4'd3: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d780; + 4'd4: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d747; + 4'd5: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d716; + 4'd6: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d685; + 4'd7: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d656; + 4'd8: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d627; + 4'd9: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d600; + 4'd10: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d573; + 4'd11: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d548; + 4'd12: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d523; + 4'd13: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d500; + 4'd14: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d476; + 4'd15: + SEL_ARR_tagLookup_tagCache_orderer_mastReqs_re_ETC___d1164 = + tagLookup_tagCache_orderer_mastReqs_removeItem_ETC___d418; + endcase + end + always@(_theResult_____1__h31534 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1027 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1001 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d999 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d997 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d995 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d993 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d991 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d989 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d987 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d985 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d983 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d981 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d979 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d977 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d975 or + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d973) + begin + case (_theResult_____1__h31534) + 4'd0: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1027; + 4'd1: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d1001; + 4'd2: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d999; + 4'd3: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d997; + 4'd4: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d995; + 4'd5: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d993; + 4'd6: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d991; + 4'd7: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d989; + 4'd8: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d987; + 4'd9: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d985; + 4'd10: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d983; + 4'd11: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d981; + 4'd12: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d979; + 4'd13: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d977; + 4'd14: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d975; + 4'd15: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastReq_ETC___d1166 = + NOT_tagLookup_tagCache_orderer_mastReqs_insert_ETC___d973; + endcase + end + always@(tagLookup_tagCache_orderer_mastLines_nextValidKeyReg or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2193 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2019 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1984 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1951 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1918 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1887 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609) + begin + case (tagLookup_tagCache_orderer_mastLines_nextValidKeyReg) + 4'd0: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2193; + 4'd1: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2019; + 4'd2: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1984; + 4'd3: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1951; + 4'd4: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1918; + 4'd5: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1887; + 4'd6: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856; + 4'd7: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827; + 4'd8: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798; + 4'd9: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771; + 4'd10: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744; + 4'd11: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719; + 4'd12: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694; + 4'd13: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671; + 4'd14: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647; + 4'd15: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2195 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609; + endcase + end + always@(tagLookup_tagCache_orderer_mastLines_nextValidKeyReg or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2198 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2172 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2170 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2168 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2166 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2164 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2162 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2160 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2158 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2156 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2154 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2152 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2150 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2148 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2146 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2144) + begin + case (tagLookup_tagCache_orderer_mastLines_nextValidKeyReg) + 4'd0: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2198; + 4'd1: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2172; + 4'd2: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2170; + 4'd3: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2168; + 4'd4: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2166; + 4'd5: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2164; + 4'd6: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2162; + 4'd7: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2160; + 4'd8: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2158; + 4'd9: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2156; + 4'd10: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2154; + 4'd11: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2152; + 4'd12: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2150; + 4'd13: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2148; + 4'd14: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2146; + 4'd15: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2200 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2144; + endcase + end + always@(idx__h43465 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h43465) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2226 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h43581 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h43581) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2232 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h43697 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h43697) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2238 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h43813 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h43813) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2244 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h43929 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h43929) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2250 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h44161 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h44161) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2262 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h44045 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h44045) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2256 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h44277 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h44277) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2268 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h44393 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h44393) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2274 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h44509 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h44509) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2280 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h44625 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h44625) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2286 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h44741 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h44741) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2292 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h44857 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h44857) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2298 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h44973 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h44973) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2304 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(idx__h45089 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (idx__h45089) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2310 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(tagLookup_tagCache_orderer_mastLines_nextValidKeyReg or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223 or + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224) + begin + case (tagLookup_tagCache_orderer_mastLines_nextValidKeyReg) + 4'd0: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2209; + 4'd1: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2210; + 4'd2: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2211; + 4'd3: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2212; + 4'd4: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2213; + 4'd5: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2214; + 4'd6: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2215; + 4'd7: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2216; + 4'd8: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2217; + 4'd9: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2218; + 4'd10: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2219; + 4'd11: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2220; + 4'd12: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2221; + 4'd13: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2222; + 4'd14: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2223; + 4'd15: + SEL_ARR_IF_tagLookup_tagCache_orderer_mastLine_ETC___d2313 = + IF_tagLookup_tagCache_orderer_mastLines_insert_ETC___d2224; + endcase + end + always@(_theResult_____1__h43323 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2193 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2019 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1984 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1951 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1918 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1887 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647 or + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609) + begin + case (_theResult_____1__h43323) + 4'd0: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2193; + 4'd1: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d2019; + 4'd2: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1984; + 4'd3: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1951; + 4'd4: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1918; + 4'd5: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1887; + 4'd6: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1856; + 4'd7: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1827; + 4'd8: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1798; + 4'd9: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1771; + 4'd10: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1744; + 4'd11: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1719; + 4'd12: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1694; + 4'd13: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1671; + 4'd14: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1647; + 4'd15: + SEL_ARR_tagLookup_tagCache_orderer_mastLines_r_ETC___d2335 = + tagLookup_tagCache_orderer_mastLines_removeIte_ETC___d1609; + endcase + end + always@(_theResult_____1__h43323 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2198 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2172 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2170 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2168 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2166 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2164 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2162 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2160 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2158 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2156 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2154 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2152 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2150 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2148 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2146 or + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2144) + begin + case (_theResult_____1__h43323) + 4'd0: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2198; + 4'd1: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2172; + 4'd2: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2170; + 4'd3: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2168; + 4'd4: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2166; + 4'd5: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2164; + 4'd6: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2162; + 4'd7: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2160; + 4'd8: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2158; + 4'd9: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2156; + 4'd10: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2154; + 4'd11: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2152; + 4'd12: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2150; + 4'd13: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2148; + 4'd14: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2146; + 4'd15: + SEL_ARR_NOT_tagLookup_tagCache_orderer_mastLin_ETC___d2337 = + NOT_tagLookup_tagCache_orderer_mastLines_inser_ETC___d2144; + endcase + end + always@(memory_response_put_val) + begin + case (memory_response_put_val[68:67]) + 2'd0, 2'd1: + CASE_memory_response_put_val_BITS_68_TO_67_0_m_ETC__q41 = + memory_response_put_val[68:65]; + default: CASE_memory_response_put_val_BITS_68_TO_67_0_m_ETC__q41 = + { 2'd2, memory_response_put_val[66:65] }; + endcase + end + always@(idx__h296159 or tagLookup_tagCache_respswget_BITS_219_TO_156__q37) + begin + case (idx__h296159) + 6'd0: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[3]; + 6'd1: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[7]; + 6'd2: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[11]; + 6'd3: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[15]; + 6'd4: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[19]; + 6'd5: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[23]; + 6'd6: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[27]; + 6'd7: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[31]; + 6'd8: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[35]; + 6'd9: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[39]; + 6'd10: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[43]; + 6'd11: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[47]; + 6'd12: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[51]; + 6'd13: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[55]; + 6'd14: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[59]; + 6'd15: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[63]; + default: CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q42 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(idx__h296159 or tagLookup_tagCache_respswget_BITS_219_TO_156__q37) + begin + case (idx__h296159) + 6'd0: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[2]; + 6'd1: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[6]; + 6'd2: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[10]; + 6'd3: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[14]; + 6'd4: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[18]; + 6'd5: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[22]; + 6'd6: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[26]; + 6'd7: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[30]; + 6'd8: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[34]; + 6'd9: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[38]; + 6'd10: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[42]; + 6'd11: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[46]; + 6'd12: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[50]; + 6'd13: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[54]; + 6'd14: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[58]; + 6'd15: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[62]; + default: CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q43 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(idx__h296159 or tagLookup_tagCache_respswget_BITS_219_TO_156__q37) + begin + case (idx__h296159) + 6'd0: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[1]; + 6'd1: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[5]; + 6'd2: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[9]; + 6'd3: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[13]; + 6'd4: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[17]; + 6'd5: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[21]; + 6'd6: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[25]; + 6'd7: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[29]; + 6'd8: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[33]; + 6'd9: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[37]; + 6'd10: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[41]; + 6'd11: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[45]; + 6'd12: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[49]; + 6'd13: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[53]; + 6'd14: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[57]; + 6'd15: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[61]; + default: CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q44 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(idx__h296159 or tagLookup_tagCache_respswget_BITS_219_TO_156__q37) + begin + case (idx__h296159) + 6'd0: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[0]; + 6'd1: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[4]; + 6'd2: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[8]; + 6'd3: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[12]; + 6'd4: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[16]; + 6'd5: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[20]; + 6'd6: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[24]; + 6'd7: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[28]; + 6'd8: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[32]; + 6'd9: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[36]; + 6'd10: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[40]; + 6'd11: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[44]; + 6'd12: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[48]; + 6'd13: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[52]; + 6'd14: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[56]; + 6'd15: + CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + tagLookup_tagCache_respswget_BITS_219_TO_156__q37[60]; + default: CASE_idx96159_0_tagLookup_tagCache_respswget_B_ETC__q45 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(tagLookup_tagCache_cts or + tagLookup_tagCache_readReqReg or + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4670 or + level__h1463 or + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4665) + begin + case (tagLookup_tagCache_cts[278:277]) + 2'd0: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q46 = + IF_tagLookup_tagCache_cts_read__795_BITS_229_T_ETC___d4670; + 2'd1, 2'd3: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q46 = + tagLookup_tagCache_readReqReg[66]; + 2'd2: + CASE_tagLookup_tagCache_cts_BITS_278_TO_277_0__ETC__q46 = + (level__h1463 == 2'd0) ? + tagLookup_tagCache_readReqReg[66] : + IF_tagLookup_tagCache_readReqReg_read__136_BIT_ETC___d4665; + endcase + end + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + addrFrame_bag <= `BSV_ASSIGNMENT_DELAY 16'd10922; + frame <= `BSV_ASSIGNMENT_DELAY 3'd0; + lookupRsp_bag <= `BSV_ASSIGNMENT_DELAY 18'd43690; + nextId <= `BSV_ASSIGNMENT_DELAY 5'd0; + tagLookup_currentDepth <= `BSV_ASSIGNMENT_DELAY 2'd0; + tagLookup_oldTags_0 <= `BSV_ASSIGNMENT_DELAY 64'd0; + tagLookup_oldTags_1 <= `BSV_ASSIGNMENT_DELAY 64'd0; + tagLookup_pendingCapEnable <= `BSV_ASSIGNMENT_DELAY 1'd0; + tagLookup_pendingCapNumber <= `BSV_ASSIGNMENT_DELAY 36'd0; + tagLookup_pendingTags <= `BSV_ASSIGNMENT_DELAY 1'd0; + tagLookup_readReqs_ff_full <= `BSV_ASSIGNMENT_DELAY 1'd0; + tagLookup_state <= `BSV_ASSIGNMENT_DELAY 3'd0; + tagLookup_tagCache_cacheState <= `BSV_ASSIGNMENT_DELAY 1'd0; + tagLookup_tagCache_cts <= `BSV_ASSIGNMENT_DELAY + 279'h4000000000002AAAAAAAAAAAAAAAAAAAAA83AAAAAAAAAA555255555555400000000002; + tagLookup_tagCache_initCount <= `BSV_ASSIGNMENT_DELAY 8'd0; + tagLookup_tagCache_invalidateWritebackWriteBank <= `BSV_ASSIGNMENT_DELAY + 2'd0; + tagLookup_tagCache_nextWay <= `BSV_ASSIGNMENT_DELAY 1'd0; + tagLookup_tagCache_orderer_lookupState <= `BSV_ASSIGNMENT_DELAY + 13'd2701; + tagLookup_tagCache_orderer_mastLines_bag <= `BSV_ASSIGNMENT_DELAY + 672'h2AAAAAAAAA8AAAAAAAAAA2AAAAAAAAA8AAAAAAAAAA2AAAAAAAAA8AAAAAAAAAA2AAAAAAAAA8AAAAAAAAAA2AAAAAAAAA8AAAAAAAAAA2AAAAAAAAA8AAAAAAAAAA2AAAAAAAAA8AAAAAAAAAA2AAAAAAAAA8AAAAAAAAAA; + tagLookup_tagCache_orderer_mastReqIds_rf <= `BSV_ASSIGNMENT_DELAY + 80'h7B9AC5A928398A418820; + tagLookup_tagCache_orderer_mastReqs_bag <= `BSV_ASSIGNMENT_DELAY + 944'h555555555555554AAAAAAAAAAAAAA9555555555555552AAAAAAAAAAAAAA555555555555554AAAAAAAAAAAAAA9555555555555552AAAAAAAAAAAAAA555555555555554AAAAAAAAAAAAAA9555555555555552AAAAAAAAAAAAAA555555555555554AAAAAAAAAAAAAA9555555555555552AAAAAAAAAAAAAA; + tagLookup_tagCache_orderer_mastRespState <= `BSV_ASSIGNMENT_DELAY + 13'd2701; + tagLookup_tagCache_orderer_slaveAddrs_bag <= `BSV_ASSIGNMENT_DELAY + 42'h0AAAAAAAAAA; + tagLookup_tagCache_orderer_slaveDeps_bag <= `BSV_ASSIGNMENT_DELAY + 13'd2730; + tagLookup_tagCache_orderer_slaveReqs_bag <= `BSV_ASSIGNMENT_DELAY + 59'h2AAAAAAAAAAAAAA; + tagLookup_tagCache_orderer_slaveRespState <= `BSV_ASSIGNMENT_DELAY + 13'd2701; + tagLookup_tagCache_readReqReg <= `BSV_ASSIGNMENT_DELAY + 67'h2AAA7EAAAAAAAAAAA; + tagLookup_tagCache_readReqs_bag <= `BSV_ASSIGNMENT_DELAY + 73'h0AAAAAAAAAAAAAAAAAA; + tagLookup_tagCache_req_commits_head <= `BSV_ASSIGNMENT_DELAY 4'd0; + tagLookup_tagCache_req_commits_level <= `BSV_ASSIGNMENT_DELAY 5'd0; + tagLookup_tagCache_req_commits_rf <= `BSV_ASSIGNMENT_DELAY 16'hAAAA; + tagLookup_tagCache_req_commits_tail <= `BSV_ASSIGNMENT_DELAY 4'd0; + tagLookup_tagCache_retryReqs_bag <= `BSV_ASSIGNMENT_DELAY + 148'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + tagLookup_tagCache_writebackWriteBank <= `BSV_ASSIGNMENT_DELAY 2'd0; + tagLookup_transNum <= `BSV_ASSIGNMENT_DELAY 5'd0; + tagLookup_zeroAddr <= `BSV_ASSIGNMENT_DELAY 40'h00FF7DF080; + end + else + begin + if (addrFrame_bag$EN) + addrFrame_bag <= `BSV_ASSIGNMENT_DELAY addrFrame_bag$D_IN; + if (frame$EN) frame <= `BSV_ASSIGNMENT_DELAY frame$D_IN; + if (lookupRsp_bag$EN) + lookupRsp_bag <= `BSV_ASSIGNMENT_DELAY lookupRsp_bag$D_IN; + if (nextId$EN) nextId <= `BSV_ASSIGNMENT_DELAY nextId$D_IN; + if (tagLookup_currentDepth$EN) + tagLookup_currentDepth <= `BSV_ASSIGNMENT_DELAY + tagLookup_currentDepth$D_IN; + if (tagLookup_oldTags_0$EN) + tagLookup_oldTags_0 <= `BSV_ASSIGNMENT_DELAY + tagLookup_oldTags_0$D_IN; + if (tagLookup_oldTags_1$EN) + tagLookup_oldTags_1 <= `BSV_ASSIGNMENT_DELAY + tagLookup_oldTags_1$D_IN; + if (tagLookup_pendingCapEnable$EN) + tagLookup_pendingCapEnable <= `BSV_ASSIGNMENT_DELAY + tagLookup_pendingCapEnable$D_IN; + if (tagLookup_pendingCapNumber$EN) + tagLookup_pendingCapNumber <= `BSV_ASSIGNMENT_DELAY + tagLookup_pendingCapNumber$D_IN; + if (tagLookup_pendingTags$EN) + tagLookup_pendingTags <= `BSV_ASSIGNMENT_DELAY + tagLookup_pendingTags$D_IN; + if (tagLookup_readReqs_ff_full$EN) + tagLookup_readReqs_ff_full <= `BSV_ASSIGNMENT_DELAY + tagLookup_readReqs_ff_full$D_IN; + if (tagLookup_state$EN) + tagLookup_state <= `BSV_ASSIGNMENT_DELAY tagLookup_state$D_IN; + if (tagLookup_tagCache_cacheState$EN) + tagLookup_tagCache_cacheState <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_cacheState$D_IN; + if (tagLookup_tagCache_cts$EN) + tagLookup_tagCache_cts <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_cts$D_IN; + if (tagLookup_tagCache_initCount$EN) + tagLookup_tagCache_initCount <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_initCount$D_IN; + if (tagLookup_tagCache_invalidateWritebackWriteBank$EN) + tagLookup_tagCache_invalidateWritebackWriteBank <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_invalidateWritebackWriteBank$D_IN; + if (tagLookup_tagCache_nextWay$EN) + tagLookup_tagCache_nextWay <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_nextWay$D_IN; + if (tagLookup_tagCache_orderer_lookupState$EN) + tagLookup_tagCache_orderer_lookupState <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_lookupState$D_IN; + if (tagLookup_tagCache_orderer_mastLines_bag$EN) + tagLookup_tagCache_orderer_mastLines_bag <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_mastLines_bag$D_IN; + if (tagLookup_tagCache_orderer_mastReqIds_rf$EN) + tagLookup_tagCache_orderer_mastReqIds_rf <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_mastReqIds_rf$D_IN; + if (tagLookup_tagCache_orderer_mastReqs_bag$EN) + tagLookup_tagCache_orderer_mastReqs_bag <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_mastReqs_bag$D_IN; + if (tagLookup_tagCache_orderer_mastRespState$EN) + tagLookup_tagCache_orderer_mastRespState <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_mastRespState$D_IN; + if (tagLookup_tagCache_orderer_slaveAddrs_bag$EN) + tagLookup_tagCache_orderer_slaveAddrs_bag <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_slaveAddrs_bag$D_IN; + if (tagLookup_tagCache_orderer_slaveDeps_bag$EN) + tagLookup_tagCache_orderer_slaveDeps_bag <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_slaveDeps_bag$D_IN; + if (tagLookup_tagCache_orderer_slaveReqs_bag$EN) + tagLookup_tagCache_orderer_slaveReqs_bag <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_slaveReqs_bag$D_IN; + if (tagLookup_tagCache_orderer_slaveRespState$EN) + tagLookup_tagCache_orderer_slaveRespState <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_slaveRespState$D_IN; + if (tagLookup_tagCache_readReqReg$EN) + tagLookup_tagCache_readReqReg <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_readReqReg$D_IN; + if (tagLookup_tagCache_readReqs_bag$EN) + tagLookup_tagCache_readReqs_bag <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_readReqs_bag$D_IN; + if (tagLookup_tagCache_req_commits_head$EN) + tagLookup_tagCache_req_commits_head <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_req_commits_head$D_IN; + if (tagLookup_tagCache_req_commits_level$EN) + tagLookup_tagCache_req_commits_level <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_req_commits_level$D_IN; + if (tagLookup_tagCache_req_commits_rf$EN) + tagLookup_tagCache_req_commits_rf <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_req_commits_rf$D_IN; + if (tagLookup_tagCache_req_commits_tail$EN) + tagLookup_tagCache_req_commits_tail <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_req_commits_tail$D_IN; + if (tagLookup_tagCache_retryReqs_bag$EN) + tagLookup_tagCache_retryReqs_bag <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_retryReqs_bag$D_IN; + if (tagLookup_tagCache_writebackWriteBank$EN) + tagLookup_tagCache_writebackWriteBank <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_writebackWriteBank$D_IN; + if (tagLookup_transNum$EN) + tagLookup_transNum <= `BSV_ASSIGNMENT_DELAY tagLookup_transNum$D_IN; + if (tagLookup_zeroAddr$EN) + tagLookup_zeroAddr <= `BSV_ASSIGNMENT_DELAY tagLookup_zeroAddr$D_IN; + end + if (tagLookup_lookupRsp_ff_rf$EN) + tagLookup_lookupRsp_ff_rf <= `BSV_ASSIGNMENT_DELAY + tagLookup_lookupRsp_ff_rf$D_IN; + if (tagLookup_readReqs_ff_dataReg$EN) + tagLookup_readReqs_ff_dataReg <= `BSV_ASSIGNMENT_DELAY + tagLookup_readReqs_ff_dataReg$D_IN; + if (tagLookup_reqeustId$EN) + tagLookup_reqeustId <= `BSV_ASSIGNMENT_DELAY tagLookup_reqeustId$D_IN; + if (tagLookup_tagCacheReq_ff_rf$EN) + tagLookup_tagCacheReq_ff_rf <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCacheReq_ff_rf$D_IN; + if (tagLookup_tagCache_data_0_readAddr$EN) + tagLookup_tagCache_data_0_readAddr <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_data_0_readAddr$D_IN; + if (tagLookup_tagCache_data_0_writeAddr$EN) + tagLookup_tagCache_data_0_writeAddr <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_data_0_writeAddr$D_IN; + if (tagLookup_tagCache_data_0_writeData$EN) + tagLookup_tagCache_data_0_writeData <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_data_0_writeData$D_IN; + if (tagLookup_tagCache_data_1_readAddr$EN) + tagLookup_tagCache_data_1_readAddr <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_data_1_readAddr$D_IN; + if (tagLookup_tagCache_data_1_writeAddr$EN) + tagLookup_tagCache_data_1_writeAddr <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_data_1_writeAddr$D_IN; + if (tagLookup_tagCache_data_1_writeData$EN) + tagLookup_tagCache_data_1_writeData <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_data_1_writeData$D_IN; + if (tagLookup_tagCache_nextEmpty$EN) + tagLookup_tagCache_nextEmpty <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_nextEmpty$D_IN; + if (tagLookup_tagCache_orderer_mastLines_nextValidKeyReg$EN) + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg$D_IN; + if (tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg$EN) + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg$D_IN; + if (tagLookup_tagCache_tags_0_readAddr$EN) + tagLookup_tagCache_tags_0_readAddr <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_tags_0_readAddr$D_IN; + if (tagLookup_tagCache_tags_0_readAddrB$EN) + tagLookup_tagCache_tags_0_readAddrB <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_tags_0_readAddrB$D_IN; + if (tagLookup_tagCache_tags_0_writeAddr$EN) + tagLookup_tagCache_tags_0_writeAddr <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_tags_0_writeAddr$D_IN; + if (tagLookup_tagCache_tags_0_writeData$EN) + tagLookup_tagCache_tags_0_writeData <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_tags_0_writeData$D_IN; + if (tagLookup_tagCache_tags_1_readAddr$EN) + tagLookup_tagCache_tags_1_readAddr <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_tags_1_readAddr$D_IN; + if (tagLookup_tagCache_tags_1_readAddrB$EN) + tagLookup_tagCache_tags_1_readAddrB <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_tags_1_readAddrB$D_IN; + if (tagLookup_tagCache_tags_1_writeAddr$EN) + tagLookup_tagCache_tags_1_writeAddr <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_tags_1_writeAddr$D_IN; + if (tagLookup_tagCache_tags_1_writeData$EN) + tagLookup_tagCache_tags_1_writeData <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_tags_1_writeData$D_IN; + if (tagOnlyReads_rf$EN) + tagOnlyReads_rf <= `BSV_ASSIGNMENT_DELAY tagOnlyReads_rf$D_IN; + end + + always@(posedge CLK or `BSV_RESET_EDGE RST_N) + if (RST_N == `BSV_RESET_VALUE) + begin + mReqs_ff_lhead <= `BSV_ASSIGNMENT_DELAY 2'd0; + mReqs_ff_ltail <= `BSV_ASSIGNMENT_DELAY 2'd0; + mRsps_ff_lhead <= `BSV_ASSIGNMENT_DELAY 6'd0; + mRsps_ff_ltail <= `BSV_ASSIGNMENT_DELAY 6'd0; + tagLookup_lookupRsp_ff_lhead <= `BSV_ASSIGNMENT_DELAY 1'd0; + tagLookup_lookupRsp_ff_ltail <= `BSV_ASSIGNMENT_DELAY 1'd0; + tagLookup_mReqs_ff_lhead <= `BSV_ASSIGNMENT_DELAY 4'd0; + tagLookup_mReqs_ff_ltail <= `BSV_ASSIGNMENT_DELAY 4'd0; + tagLookup_mRsps_ff_lhead <= `BSV_ASSIGNMENT_DELAY 2'd0; + tagLookup_mRsps_ff_ltail <= `BSV_ASSIGNMENT_DELAY 2'd0; + tagLookup_tagCacheReq_ff_lhead <= `BSV_ASSIGNMENT_DELAY 1'd0; + tagLookup_tagCacheReq_ff_ltail <= `BSV_ASSIGNMENT_DELAY 1'd0; + tagLookup_tagCache_delayedInvalidates_ff_lhead <= `BSV_ASSIGNMENT_DELAY + 4'd0; + tagLookup_tagCache_delayedInvalidates_ff_ltail <= `BSV_ASSIGNMENT_DELAY + 4'd0; + tagLookup_tagCache_invalidatesDone_ff_lhead <= `BSV_ASSIGNMENT_DELAY + 6'd0; + tagLookup_tagCache_invalidatesDone_ff_ltail <= `BSV_ASSIGNMENT_DELAY + 6'd0; + tagLookup_tagCache_invalidates_ff_lhead <= `BSV_ASSIGNMENT_DELAY 3'd0; + tagLookup_tagCache_invalidates_ff_ltail <= `BSV_ASSIGNMENT_DELAY 3'd0; + tagLookup_tagCache_orderer_mastReqIds_lhead <= `BSV_ASSIGNMENT_DELAY + 5'd16; + tagLookup_tagCache_orderer_waitingSlaveReq_lhead <= `BSV_ASSIGNMENT_DELAY + 2'd0; + tagLookup_tagCache_orderer_waitingSlaveReq_ltail <= `BSV_ASSIGNMENT_DELAY + 2'd0; + tagLookup_tagCache_writeResps_ff_lhead <= `BSV_ASSIGNMENT_DELAY 2'd0; + tagLookup_tagCache_writeResps_ff_ltail <= `BSV_ASSIGNMENT_DELAY 2'd0; + tagLookup_tagCache_writethroughNext_ff_lhead <= `BSV_ASSIGNMENT_DELAY + 2'd0; + tagLookup_tagCache_writethroughNext_ff_ltail <= `BSV_ASSIGNMENT_DELAY + 2'd0; + tagLookup_useNextRsp_ff_lhead <= `BSV_ASSIGNMENT_DELAY 3'd0; + tagLookup_useNextRsp_ff_ltail <= `BSV_ASSIGNMENT_DELAY 3'd0; + tagOnlyReads_lhead <= `BSV_ASSIGNMENT_DELAY 1'd0; + tagOnlyReads_ltail <= `BSV_ASSIGNMENT_DELAY 1'd0; + writeBuffer_ff_lhead <= `BSV_ASSIGNMENT_DELAY 5'd0; + writeBuffer_ff_ltail <= `BSV_ASSIGNMENT_DELAY 5'd0; + end + else + begin + if (mReqs_ff_lhead$EN) + mReqs_ff_lhead <= `BSV_ASSIGNMENT_DELAY mReqs_ff_lhead$D_IN; + if (mReqs_ff_ltail$EN) + mReqs_ff_ltail <= `BSV_ASSIGNMENT_DELAY mReqs_ff_ltail$D_IN; + if (mRsps_ff_lhead$EN) + mRsps_ff_lhead <= `BSV_ASSIGNMENT_DELAY mRsps_ff_lhead$D_IN; + if (mRsps_ff_ltail$EN) + mRsps_ff_ltail <= `BSV_ASSIGNMENT_DELAY mRsps_ff_ltail$D_IN; + if (tagLookup_lookupRsp_ff_lhead$EN) + tagLookup_lookupRsp_ff_lhead <= `BSV_ASSIGNMENT_DELAY + tagLookup_lookupRsp_ff_lhead$D_IN; + if (tagLookup_lookupRsp_ff_ltail$EN) + tagLookup_lookupRsp_ff_ltail <= `BSV_ASSIGNMENT_DELAY + tagLookup_lookupRsp_ff_ltail$D_IN; + if (tagLookup_mReqs_ff_lhead$EN) + tagLookup_mReqs_ff_lhead <= `BSV_ASSIGNMENT_DELAY + tagLookup_mReqs_ff_lhead$D_IN; + if (tagLookup_mReqs_ff_ltail$EN) + tagLookup_mReqs_ff_ltail <= `BSV_ASSIGNMENT_DELAY + tagLookup_mReqs_ff_ltail$D_IN; + if (tagLookup_mRsps_ff_lhead$EN) + tagLookup_mRsps_ff_lhead <= `BSV_ASSIGNMENT_DELAY + tagLookup_mRsps_ff_lhead$D_IN; + if (tagLookup_mRsps_ff_ltail$EN) + tagLookup_mRsps_ff_ltail <= `BSV_ASSIGNMENT_DELAY + tagLookup_mRsps_ff_ltail$D_IN; + if (tagLookup_tagCacheReq_ff_lhead$EN) + tagLookup_tagCacheReq_ff_lhead <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCacheReq_ff_lhead$D_IN; + if (tagLookup_tagCacheReq_ff_ltail$EN) + tagLookup_tagCacheReq_ff_ltail <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCacheReq_ff_ltail$D_IN; + if (tagLookup_tagCache_delayedInvalidates_ff_lhead$EN) + tagLookup_tagCache_delayedInvalidates_ff_lhead <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_delayedInvalidates_ff_lhead$D_IN; + if (tagLookup_tagCache_delayedInvalidates_ff_ltail$EN) + tagLookup_tagCache_delayedInvalidates_ff_ltail <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_delayedInvalidates_ff_ltail$D_IN; + if (tagLookup_tagCache_invalidatesDone_ff_lhead$EN) + tagLookup_tagCache_invalidatesDone_ff_lhead <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_invalidatesDone_ff_lhead$D_IN; + if (tagLookup_tagCache_invalidatesDone_ff_ltail$EN) + tagLookup_tagCache_invalidatesDone_ff_ltail <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_invalidatesDone_ff_ltail$D_IN; + if (tagLookup_tagCache_invalidates_ff_lhead$EN) + tagLookup_tagCache_invalidates_ff_lhead <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_invalidates_ff_lhead$D_IN; + if (tagLookup_tagCache_invalidates_ff_ltail$EN) + tagLookup_tagCache_invalidates_ff_ltail <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_invalidates_ff_ltail$D_IN; + if (tagLookup_tagCache_orderer_mastReqIds_lhead$EN) + tagLookup_tagCache_orderer_mastReqIds_lhead <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_mastReqIds_lhead$D_IN; + if (tagLookup_tagCache_orderer_waitingSlaveReq_lhead$EN) + tagLookup_tagCache_orderer_waitingSlaveReq_lhead <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_waitingSlaveReq_lhead$D_IN; + if (tagLookup_tagCache_orderer_waitingSlaveReq_ltail$EN) + tagLookup_tagCache_orderer_waitingSlaveReq_ltail <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_orderer_waitingSlaveReq_ltail$D_IN; + if (tagLookup_tagCache_writeResps_ff_lhead$EN) + tagLookup_tagCache_writeResps_ff_lhead <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_writeResps_ff_lhead$D_IN; + if (tagLookup_tagCache_writeResps_ff_ltail$EN) + tagLookup_tagCache_writeResps_ff_ltail <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_writeResps_ff_ltail$D_IN; + if (tagLookup_tagCache_writethroughNext_ff_lhead$EN) + tagLookup_tagCache_writethroughNext_ff_lhead <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_writethroughNext_ff_lhead$D_IN; + if (tagLookup_tagCache_writethroughNext_ff_ltail$EN) + tagLookup_tagCache_writethroughNext_ff_ltail <= `BSV_ASSIGNMENT_DELAY + tagLookup_tagCache_writethroughNext_ff_ltail$D_IN; + if (tagLookup_useNextRsp_ff_lhead$EN) + tagLookup_useNextRsp_ff_lhead <= `BSV_ASSIGNMENT_DELAY + tagLookup_useNextRsp_ff_lhead$D_IN; + if (tagLookup_useNextRsp_ff_ltail$EN) + tagLookup_useNextRsp_ff_ltail <= `BSV_ASSIGNMENT_DELAY + tagLookup_useNextRsp_ff_ltail$D_IN; + if (tagOnlyReads_lhead$EN) + tagOnlyReads_lhead <= `BSV_ASSIGNMENT_DELAY tagOnlyReads_lhead$D_IN; + if (tagOnlyReads_ltail$EN) + tagOnlyReads_ltail <= `BSV_ASSIGNMENT_DELAY tagOnlyReads_ltail$D_IN; + if (writeBuffer_ff_lhead$EN) + writeBuffer_ff_lhead <= `BSV_ASSIGNMENT_DELAY + writeBuffer_ff_lhead$D_IN; + if (writeBuffer_ff_ltail$EN) + writeBuffer_ff_ltail <= `BSV_ASSIGNMENT_DELAY + writeBuffer_ff_ltail$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + addrFrame_bag = 16'hAAAA; + frame = 3'h2; + lookupRsp_bag = 18'h2AAAA; + mReqs_ff_lhead = 2'h2; + mReqs_ff_ltail = 2'h2; + mRsps_ff_lhead = 6'h2A; + mRsps_ff_ltail = 6'h2A; + nextId = 5'h0A; + tagLookup_currentDepth = 2'h2; + tagLookup_lookupRsp_ff_lhead = 1'h0; + tagLookup_lookupRsp_ff_ltail = 1'h0; + tagLookup_lookupRsp_ff_rf = 4'hA; + tagLookup_mReqs_ff_lhead = 4'hA; + tagLookup_mReqs_ff_ltail = 4'hA; + tagLookup_mRsps_ff_lhead = 2'h2; + tagLookup_mRsps_ff_ltail = 2'h2; + tagLookup_oldTags_0 = 64'hAAAAAAAAAAAAAAAA; + tagLookup_oldTags_1 = 64'hAAAAAAAAAAAAAAAA; + tagLookup_pendingCapEnable = 1'h0; + tagLookup_pendingCapNumber = 36'hAAAAAAAAA; + tagLookup_pendingTags = 1'h0; + tagLookup_readReqs_ff_dataReg = 1'h0; + tagLookup_readReqs_ff_full = 1'h0; + tagLookup_reqeustId = 6'h2A; + tagLookup_state = 3'h2; + tagLookup_tagCacheReq_ff_lhead = 1'h0; + tagLookup_tagCacheReq_ff_ltail = 1'h0; + tagLookup_tagCacheReq_ff_rf = 141'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + tagLookup_tagCache_cacheState = 1'h0; + tagLookup_tagCache_cts = + 279'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + tagLookup_tagCache_data_0_readAddr = 10'h2AA; + tagLookup_tagCache_data_0_writeAddr = 10'h2AA; + tagLookup_tagCache_data_0_writeData = 64'hAAAAAAAAAAAAAAAA; + tagLookup_tagCache_data_1_readAddr = 10'h2AA; + tagLookup_tagCache_data_1_writeAddr = 10'h2AA; + tagLookup_tagCache_data_1_writeData = 64'hAAAAAAAAAAAAAAAA; + tagLookup_tagCache_delayedInvalidates_ff_lhead = 4'hA; + tagLookup_tagCache_delayedInvalidates_ff_ltail = 4'hA; + tagLookup_tagCache_initCount = 8'hAA; + tagLookup_tagCache_invalidateWritebackWriteBank = 2'h2; + tagLookup_tagCache_invalidatesDone_ff_lhead = 6'h2A; + tagLookup_tagCache_invalidatesDone_ff_ltail = 6'h2A; + tagLookup_tagCache_invalidates_ff_lhead = 3'h2; + tagLookup_tagCache_invalidates_ff_ltail = 3'h2; + tagLookup_tagCache_nextEmpty = 1'h0; + tagLookup_tagCache_nextWay = 1'h0; + tagLookup_tagCache_orderer_lookupState = 13'h0AAA; + tagLookup_tagCache_orderer_mastLines_bag = + 672'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + tagLookup_tagCache_orderer_mastLines_nextValidKeyReg = 4'hA; + tagLookup_tagCache_orderer_mastReqIds_lhead = 5'h0A; + tagLookup_tagCache_orderer_mastReqIds_rf = 80'hAAAAAAAAAAAAAAAAAAAA; + tagLookup_tagCache_orderer_mastReqs_bag = + 944'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + tagLookup_tagCache_orderer_mastReqs_nextValidKeyReg = 4'hA; + tagLookup_tagCache_orderer_mastRespState = 13'h0AAA; + tagLookup_tagCache_orderer_slaveAddrs_bag = 42'h2AAAAAAAAAA; + tagLookup_tagCache_orderer_slaveDeps_bag = 13'h0AAA; + tagLookup_tagCache_orderer_slaveReqs_bag = 59'h2AAAAAAAAAAAAAA; + tagLookup_tagCache_orderer_slaveRespState = 13'h0AAA; + tagLookup_tagCache_orderer_waitingSlaveReq_lhead = 2'h2; + tagLookup_tagCache_orderer_waitingSlaveReq_ltail = 2'h2; + tagLookup_tagCache_readReqReg = 67'h2AAAAAAAAAAAAAAAA; + tagLookup_tagCache_readReqs_bag = 73'h0AAAAAAAAAAAAAAAAAA; + tagLookup_tagCache_req_commits_head = 4'hA; + tagLookup_tagCache_req_commits_level = 5'h0A; + tagLookup_tagCache_req_commits_rf = 16'hAAAA; + tagLookup_tagCache_req_commits_tail = 4'hA; + tagLookup_tagCache_retryReqs_bag = + 148'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + tagLookup_tagCache_tags_0_readAddr = 8'hAA; + tagLookup_tagCache_tags_0_readAddrB = 8'hAA; + tagLookup_tagCache_tags_0_writeAddr = 8'hAA; + tagLookup_tagCache_tags_0_writeData = 41'h0AAAAAAAAAA; + tagLookup_tagCache_tags_1_readAddr = 8'hAA; + tagLookup_tagCache_tags_1_readAddrB = 8'hAA; + tagLookup_tagCache_tags_1_writeAddr = 8'hAA; + tagLookup_tagCache_tags_1_writeData = 41'h0AAAAAAAAAA; + tagLookup_tagCache_writeResps_ff_lhead = 2'h2; + tagLookup_tagCache_writeResps_ff_ltail = 2'h2; + tagLookup_tagCache_writebackWriteBank = 2'h2; + tagLookup_tagCache_writethroughNext_ff_lhead = 2'h2; + tagLookup_tagCache_writethroughNext_ff_ltail = 2'h2; + tagLookup_transNum = 5'h0A; + tagLookup_useNextRsp_ff_lhead = 3'h2; + tagLookup_useNextRsp_ff_ltail = 3'h2; + tagLookup_zeroAddr = 40'hAAAAAAAAAA; + tagOnlyReads_lhead = 1'h0; + tagOnlyReads_ltail = 1'h0; + tagOnlyReads_rf = 6'h2A; + writeBuffer_ff_lhead = 5'h0A; + writeBuffer_ff_ltail = 5'h0A; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagLookup_mRsps_displayEnqPanic) + $display("Panic! Enqing to a full UGFF %s", "TagLookup_mRsps"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagLookup_mRsps_ff_doDisplayPanic) + $display("Panic! Enqing to a full UGFF!"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagLookup_useNextRsp_displayEnqPanic) + $display("Panic! Enqing to a full UGFF %s", "TagLookup_useNextRsp"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagLookup_useNextRsp_ff_doDisplayPanic) + $display("Panic! Enqing to a full UGFF!"); + if (RST_N != `BSV_RESET_VALUE) + if (tagLookup_tagCache_cacheState && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3858) + begin + v__h87525 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (tagLookup_tagCache_cacheState && + tagLookup_tagCache_cts_read__795_BITS_278_TO_2_ETC___d3858) + $write("