diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v index 3be4a4e..6d4e365 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v @@ -3992,7 +3992,8 @@ module mkCore(CLK, wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_2, MUX_csrf_prv_reg$write_1__VAL_1, MUX_csrf_prv_reg$write_1__VAL_2; - wire MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1, + wire MUX_commitStage_rg_serialnum$write_1__SEL_1, + MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1, MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3, MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1, MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1, @@ -4099,7 +4100,7 @@ module mkCore(CLK, curData__h194242, rVal1__h614837, rVal1__h639141, - trap_val__h705656, + trap_val__h705696, x__h199285; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12, @@ -4266,7 +4267,7 @@ module mkCore(CLK, reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263, - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665; reg [4 : 0] IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d14130, IF_fetchStage_pipelines_1_first__2872_BITS_191_ETC___d14292; reg [3 : 0] CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2891__ETC__q227, @@ -4280,8 +4281,8 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d14133, IF_fetchStage_pipelines_0_first__2863_BIT_68_2_ETC___d13193, IF_fetchStage_pipelines_1_first__2872_BITS_191_ETC___d14293, - i__h704648, - i__h704808; + i__h704688, + i__h704848; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267, @@ -4496,8 +4497,8 @@ module mkCore(CLK, b___1__h607473, b___1__h607924, b__h607311, - base__h707219, - base__h707422, + base__h707259, + base__h707462, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11256, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257, data___1__h478711, @@ -4522,8 +4523,8 @@ module mkCore(CLK, n__read__h617092, n__read__h617283, n__read__h6174, - n__read__h716001, - next_pc__h715242, + n__read__h716026, + next_pc__h715267, q___1__h479718, rVal1__h486080, rVal2__h486081, @@ -4577,7 +4578,7 @@ module mkCore(CLK, x_remainder__h478896, y__h624843, y__h646580, - y__h719172, + y__h719237, y_avValue__h183583, y_avValue__h184302, y_avValue__h483049, @@ -4587,11 +4588,11 @@ module mkCore(CLK, y_avValue__h620115, y_avValue__h639086, y_avValue__h642155, - y_avValue__h705503, - y_avValue__h707256, - y_avValue_snd_snd_snd_snd_snd__h718580, - y_avValue_snd_snd_snd_snd_snd__h719225, - y_avValue_snd_snd_snd_snd_snd__h719254; + y_avValue__h705543, + y_avValue__h707296, + y_avValue_snd_snd_snd_snd_snd__h718631, + y_avValue_snd_snd_snd_snd_snd__h719290, + y_avValue_snd_snd_snd_snd_snd__h719319; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993, r1__read__h617790, @@ -5401,7 +5402,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2172, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15216, x__h184677, - x__h707234; + x__h707274; wire [4 : 0] IF_fetchStage_pipelines_1_first__2872_BITS_194_ETC___d14349, IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15076, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265, @@ -5421,7 +5422,7 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061, checkForException___d13089, checkForException___d13706, - fflags__h719149, + fflags__h719214, res_fflags__h341458, res_fflags__h387160, res_fflags__h432855, @@ -5430,9 +5431,9 @@ module mkCore(CLK, x__h158441, x__h161257, x__h290763, - y_avValue_fst__h718154, - y_avValue_fst__h719068, - y_avValue_fst__h719096; + y_avValue_fst__h718199, + y_avValue_fst__h719133, + y_avValue_fst__h719161; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1877, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1879, @@ -5459,7 +5460,7 @@ module mkCore(CLK, IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, IF_fetchStage_pipelines_0_first__2863_BIT_68_2_ETC___d13312, - cause_code__h704633, + cause_code__h704673, csrf_external_int_en_vec_3_read__1834_AND_csrf_ETC___d12899, vm_mode_reg__read__h618984; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567, @@ -5516,18 +5517,18 @@ module mkCore(CLK, guard__h576048, guard__h585360, guard__h594429, - prv__h720663, - prv__h720707, + prv__h720728, + prv__h720772, r1__read_BITS_13_TO_12___h659469, sbIdx__h158320, v__h608557, v__h608567, v__h609625, - x__h715411, - x__h719396, - y_avValue_snd_snd_snd_fst__h718574, - y_avValue_snd_snd_snd_fst__h719219, - y_avValue_snd_snd_snd_fst__h719248; + x__h715436, + x__h719461, + y_avValue_snd_snd_snd_fst__h718625, + y_avValue_snd_snd_snd_fst__h719284, + y_avValue_snd_snd_snd_fst__h719313; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557, @@ -5829,7 +5830,7 @@ module mkCore(CLK, NOT_csrf_fs_reg_read__1710_EQ_0_3078_3079_OR_N_ETC___d13359, NOT_csrf_fs_reg_read__1710_EQ_0_3078_3079_OR_N_ETC___d13449, NOT_csrf_fs_reg_read__1710_EQ_0_3078_3079_OR_N_ETC___d13731, - NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570, + NOT_csrf_prv_reg_read__2891_ULE_1_4504_4567_OR_ETC___d14571, NOT_fetchStage_pipelines_0_canDeq__2861_2862_O_ETC___d13817, NOT_fetchStage_pipelines_0_canDeq__2861_2862_O_ETC___d13828, NOT_fetchStage_pipelines_0_canDeq__2861_2862_O_ETC___d13867, @@ -5883,9 +5884,9 @@ module mkCore(CLK, NOT_regRenamingTable_rename_0_canRename__3436__ETC___d13861, NOT_regRenamingTable_rename_0_canRename__3436__ETC___d13916, NOT_regRenamingTable_rename_1_canRename__3555__ETC___d13974, - NOT_rob_deqPort_0_canDeq__4878_4879_OR_regRena_ETC___d14917, + NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_RDY_ETC___d14917, NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_deq_ETC___d15070, - NOT_rob_deqPort_0_deq_data__4363_BITS_186_TO_1_ETC___d14674, + NOT_rob_deqPort_0_deq_data__4363_BITS_186_TO_1_ETC___d14675, NOT_rob_deqPort_0_deq_data__4363_BITS_186_TO_1_ETC___d14859, NOT_rob_deqPort_1_deq_data__4885_BIT_25_4886_4_ETC___d14914, NOT_specTagManager_canClaim__3434_3519_OR_NOT__ETC___d13995, @@ -5927,8 +5928,8 @@ module mkCore(CLK, _0_OR_NOT_fetchStage_pipelines_0_first__2863_BI_ETC___d13923, _0_OR_NOT_fetchStage_pipelines_1_first__2872_BI_ETC___d14008, _0_OR_fetchStage_RDY_pipelines_0_first__2860_38_ETC___d13831, - _0b0_CONCAT_csrf_medeleg_15_reg_read__1815_1816_ETC___d14540, - _0b0_CONCAT_csrf_mideleg_11_reg_read__1823_1824_ETC___d14521, + _0b0_CONCAT_csrf_medeleg_15_reg_read__1815_1816_ETC___d14541, + _0b0_CONCAT_csrf_mideleg_11_reg_read__1823_1824_ETC___d14522, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5280, @@ -6101,16 +6102,16 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1275, coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3670, - coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14679, + coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14680, csrf_fs_reg_read__1710_EQ_0_3078_AND_fetchStag_ETC___d13124, csrf_fs_reg_read__1710_EQ_0_3078_AND_fetchStag_ETC___d13528, csrf_fs_reg_read__1710_EQ_0_3078_AND_fetchStag_ETC___d13795, - csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542, - csrf_prv_reg_read__2891_ULE_1___d14503, + csrf_prv_reg_read__2891_ULE_1_4504_AND_IF_comm_ETC___d14543, + csrf_prv_reg_read__2891_ULE_1___d14504, csrf_prv_reg_read__2891_ULT_IF_fetchStage_pipe_ETC___d13121, fetchStage_RDY_pipelines_0_first__2860_AND_NOT_ETC___d13459, - fetchStage_RDY_pipelines_0_first__2860_AND_epo_ETC___d13333, fetchStage_RDY_pipelines_0_first__2860_AND_fet_ETC___d13525, + fetchStage_RDY_pipelines_1_deq__2875_AND_NOT_f_ETC___d14064, fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14006, fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14085, fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14203, @@ -6161,6 +6162,7 @@ module mkCore(CLK, next_deqP___1__h335802, r1__read_BIT_20___h660097, r__h617822, + regRenamingTable_RDY_rename_0_getRename__3324__ETC___d13333, regRenamingTable_RDY_rename_0_getRename__3324__ETC___d13936, regRenamingTable_RDY_rename_1_getRename__3992__ETC___d14010, regRenamingTable_rename_0_canRename__3436_AND__ETC___d13506, @@ -6180,7 +6182,6 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3555_AND__ETC___d14216, regRenamingTable_rename_1_canRename__3555_AND__ETC___d14300, regRenamingTable_rename_1_canRename__3555_AND__ETC___d14310, - rob_RDY_enqPort_1_enq__4056_AND_NOT_fetchStage_ETC___d14064, rob_enqPort_1_canEnq__3735_AND_epochManager_ch_ETC___d13740, rob_enqPort_1_canEnq__3735_AND_epochManager_ch_ETC___d13874, rob_enqPort_1_canEnq__3735_AND_epochManager_ch_ETC___d13891, @@ -9608,8 +9609,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && - rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + epochManager$RDY_incrementEpoch && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[167] && rob$deqPort_0_deq_data[18] ; @@ -9643,7 +9644,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = - coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14679 && + coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14680 && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && @@ -9688,7 +9689,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__4878_4879_OR_regRena_ETC___d14917 && + NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_RDY_ETC___d14917 && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && @@ -10611,10 +10612,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && epochManager$RDY_incrementEpoch && - rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13135 ; assign WILL_FIRE_RL_renameStage_doRenaming_Trap = CAN_FIRE_RL_renameStage_doRenaming_Trap && @@ -10623,8 +10623,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - fetchStage$RDY_pipelines_0_deq && - fetchStage_RDY_pipelines_0_first__2860_AND_epo_ETC___d13333 && + rob$RDY_enqPort_0_enq && + regRenamingTable_RDY_rename_0_getRename__3324__ETC___d13333 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13385 && rob$isEmpty ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -10697,6 +10697,9 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ; // inputs to muxes for submodule ports + assign MUX_commitStage_rg_serialnum$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitTrap_flush || + WILL_FIRE_RL_commitStage_doCommitSystemInst ; assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && @@ -10901,41 +10904,41 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd16 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd29) ; assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd29 ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd0 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd0 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd1 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd2 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd8 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 ; + csrf_prv_reg_read__2891_ULE_1_4504_AND_IF_comm_ETC___d14543 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 ; + NOT_csrf_prv_reg_read__2891_ULE_1_4504_4567_OR_ETC___d14571 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[186:182] == 5'd19 || @@ -11004,7 +11007,7 @@ module mkCore(CLK, assign MUX_commitStage_rg_serialnum$write_1__VAL_1 = commitStage_rg_serialnum + 64'd1 ; assign MUX_commitStage_rg_serialnum$write_1__VAL_2 = - commitStage_rg_serialnum + y__h719172 ; + commitStage_rg_serialnum + y__h719237 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d12981, @@ -11346,11 +11349,11 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_2 = - csrf_fflags_reg | fflags__h719149 ; - always@(IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 or + csrf_fflags_reg | fflags__h719214 ; + always@(IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 or robdeqPort_0_deq_data_BITS_95_TO_32__q262) begin - case (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664) + case (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_1 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_1 = robdeqPort_0_deq_data_BITS_95_TO_32__q262[14:13]; @@ -11358,50 +11361,50 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_2 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd8 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q262[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_2 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18) ? robdeqPort_0_deq_data_BITS_95_TO_32__q262[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h716001 + 64'd1 ; + n__read__h716026 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h716001 + { 62'd0, x__h719396 } ; + n__read__h716026 + { 62'd0, x__h719461 } ; assign MUX_csrf_mpp_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18) ? MUX_csrf_mepc_csr$write_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = - commitStage_commitTrap[4] ? 64'd0 : trap_val__h705656 ; + commitStage_commitTrap[4] ? 64'd0 : trap_val__h705696 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_2 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 != + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 != 6'd8 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 != + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_2 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 != + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd19) ? - x__h715411 : + x__h715436 : csrf_mpp_reg ; assign MUX_csrf_prv_reg$write_1__VAL_2 = - csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 ? + csrf_prv_reg_read__2891_ULE_1_4504_AND_IF_comm_ETC___d14543 ? 2'd1 : 2'd3 ; assign MUX_csrf_sepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; @@ -11411,22 +11414,22 @@ module mkCore(CLK, amoExec___d882[0] ; assign MUX_csrf_spp_reg$write_1__VAL_2 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd8 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_2[8] ; assign MUX_fetchStage$redirect_1__VAL_4 = - csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 ? - y_avValue__h705503 : - y_avValue__h707256 ; + csrf_prv_reg_read__2891_ULE_1_4504_AND_IF_comm_ETC___d14543 ? + y_avValue__h705543 : + y_avValue__h707296 ; always@(rob$deqPort_0_deq_data or - next_pc__h715242 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h715267 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[186:182]) 5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h715242; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h715267; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -11567,7 +11570,7 @@ module mkCore(CLK, assign csrf_minstret_ehr_data_lat_0$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd31 ; assign csrf_minstret_ehr_data_lat_1$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst || @@ -11579,7 +11582,7 @@ module mkCore(CLK, assign csrf_mcycle_ehr_data_lat_0$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd30 ; assign csrInstOrInterruptInflight_lat_1$whas = WILL_FIRE_RL_renameStage_doRenaming_SystemInst && @@ -11868,10 +11871,13 @@ module mkCore(CLK, // register commitStage_rg_serialnum assign commitStage_rg_serialnum$D_IN = - WILL_FIRE_RL_commitStage_doCommitSystemInst ? + MUX_commitStage_rg_serialnum$write_1__SEL_1 ? MUX_commitStage_rg_serialnum$write_1__VAL_1 : MUX_commitStage_rg_serialnum$write_1__VAL_2 ; - assign commitStage_rg_serialnum$EN = csrf_minstret_ehr_data_lat_1$whas ; + assign commitStage_rg_serialnum$EN = + WILL_FIRE_RL_commitStage_doCommitTrap_flush || + WILL_FIRE_RL_commitStage_doCommitSystemInst || + WILL_FIRE_RL_commitStage_doCommitNormalInst ; // register coreFix_doStatsReg assign coreFix_doStatsReg$D_IN = 1'b0 ; @@ -12633,9 +12639,9 @@ module mkCore(CLK, assign csrf_external_int_en_vec_0$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd9 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd22) ; // register csrf_external_int_en_vec_1 @@ -12644,9 +12650,9 @@ module mkCore(CLK, assign csrf_external_int_en_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd9 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd22) ; // register csrf_external_int_en_vec_3 @@ -12655,7 +12661,7 @@ module mkCore(CLK, assign csrf_external_int_en_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd22 ; // register csrf_external_int_pend_vec_0 @@ -12680,7 +12686,7 @@ module mkCore(CLK, assign csrf_external_int_pend_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd29 || EN_setMEIP ; @@ -12692,25 +12698,25 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd0 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && NOT_IF_NOT_rob_deqPort_0_canDeq__4878_4879_OR__ETC___d15094 ; // register csrf_frm_reg assign csrf_frm_reg$D_IN = - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd1) ? csrf_mcycle_ehr_data_lat_0$wget[2:0] : csrf_mcycle_ehr_data_lat_0$wget[7:5] ; assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd1 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd2) ; // register csrf_fs_reg @@ -12728,9 +12734,9 @@ module mkCore(CLK, assign csrf_ie_vec_0$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd8 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18) ; // register csrf_ie_vec_1 @@ -12739,7 +12745,7 @@ module mkCore(CLK, MUX_csrf_ie_vec_1$write_1__VAL_2 ; assign csrf_ie_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 || + csrf_prv_reg_read__2891_ULE_1_4504_AND_IF_comm_ETC___d14543 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_ie_vec_3 @@ -12748,20 +12754,20 @@ module mkCore(CLK, MUX_csrf_ie_vec_3$write_1__VAL_2 ; assign csrf_ie_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 || + NOT_csrf_prv_reg_read__2891_ULE_1_4504_4567_OR_ETC___d14571 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = MUX_csrf_ie_vec_3$write_1__SEL_1 ? - cause_code__h704633 : + cause_code__h704673 : csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 || + NOT_csrf_prv_reg_read__2891_ULE_1_4504_4567_OR_ETC___d14571 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd27 ; // register csrf_mcause_interrupt_reg @@ -12771,10 +12777,10 @@ module mkCore(CLK, csrf_mcycle_ehr_data_lat_0$wget[63] ; assign csrf_mcause_interrupt_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 || + NOT_csrf_prv_reg_read__2891_ULE_1_4504_4567_OR_ETC___d14571 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd27 ; // register csrf_mcounteren_cy_reg @@ -12782,7 +12788,7 @@ module mkCore(CLK, assign csrf_mcounteren_cy_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd24 ; // register csrf_mcounteren_ir_reg @@ -12790,7 +12796,7 @@ module mkCore(CLK, assign csrf_mcounteren_ir_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd24 ; // register csrf_mcounteren_tm_reg @@ -12798,7 +12804,7 @@ module mkCore(CLK, assign csrf_mcounteren_tm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd24 ; // register csrf_mcycle_ehr_data_rl @@ -12811,7 +12817,7 @@ module mkCore(CLK, assign csrf_medeleg_13_11_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd20 ; // register csrf_medeleg_15_reg @@ -12819,7 +12825,7 @@ module mkCore(CLK, assign csrf_medeleg_15_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd20 ; // register csrf_medeleg_9_0_reg @@ -12827,7 +12833,7 @@ module mkCore(CLK, assign csrf_medeleg_9_0_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd20 ; // register csrf_mepc_csr @@ -12837,10 +12843,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] ; assign csrf_mepc_csr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 || + NOT_csrf_prv_reg_read__2891_ULE_1_4504_4567_OR_ETC___d14571 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd26 ; // register csrf_mideleg_11_reg @@ -12848,7 +12854,7 @@ module mkCore(CLK, assign csrf_mideleg_11_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd21 ; // register csrf_mideleg_1_0_reg @@ -12856,7 +12862,7 @@ module mkCore(CLK, assign csrf_mideleg_1_0_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd21 ; // register csrf_mideleg_5_3_reg @@ -12864,7 +12870,7 @@ module mkCore(CLK, assign csrf_mideleg_5_3_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd21 ; // register csrf_mideleg_9_7_reg @@ -12872,7 +12878,7 @@ module mkCore(CLK, assign csrf_mideleg_9_7_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd21 ; // register csrf_minstret_ehr_data_rl @@ -12889,7 +12895,7 @@ module mkCore(CLK, MUX_csrf_mpp_reg$write_1__VAL_2 ; assign csrf_mpp_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 || + NOT_csrf_prv_reg_read__2891_ULE_1_4504_4567_OR_ETC___d14571 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mprv_reg @@ -12897,7 +12903,7 @@ module mkCore(CLK, assign csrf_mprv_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18 ; // register csrf_mscratch_csr @@ -12905,7 +12911,7 @@ module mkCore(CLK, assign csrf_mscratch_csr$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd25 ; // register csrf_mtval_csr @@ -12915,10 +12921,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] ; assign csrf_mtval_csr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 || + NOT_csrf_prv_reg_read__2891_ULE_1_4504_4567_OR_ETC___d14571 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd28 ; // register csrf_mtvec_base_hi_reg @@ -12926,7 +12932,7 @@ module mkCore(CLK, assign csrf_mtvec_base_hi_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd23 ; // register csrf_mtvec_mode_low_reg @@ -12934,7 +12940,7 @@ module mkCore(CLK, assign csrf_mtvec_mode_low_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd23 ; // register csrf_mxr_reg @@ -12942,9 +12948,9 @@ module mkCore(CLK, assign csrf_mxr_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd8 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18) ; // register csrf_ppn_reg @@ -12952,7 +12958,7 @@ module mkCore(CLK, assign csrf_ppn_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -12960,9 +12966,9 @@ module mkCore(CLK, assign csrf_prev_ie_vec_0$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd8 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18) ; // register csrf_prev_ie_vec_1 @@ -12972,7 +12978,7 @@ module mkCore(CLK, MUX_csrf_prev_ie_vec_1$write_1__VAL_2 ; assign csrf_prev_ie_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 || + csrf_prv_reg_read__2891_ULE_1_4504_AND_IF_comm_ETC___d14543 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prev_ie_vec_3 @@ -12982,7 +12988,7 @@ module mkCore(CLK, MUX_csrf_prev_ie_vec_3$write_1__VAL_2 ; assign csrf_prev_ie_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 || + NOT_csrf_prv_reg_read__2891_ULE_1_4504_4567_OR_ETC___d14571 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_prv_reg @@ -12999,14 +13005,14 @@ module mkCore(CLK, // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = MUX_csrf_ie_vec_1$write_1__SEL_1 ? - cause_code__h704633 : + cause_code__h704673 : csrf_mscratch_csr$D_IN[3:0] ; assign csrf_scause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 || + csrf_prv_reg_read__2891_ULE_1_4504_AND_IF_comm_ETC___d14543 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -13016,10 +13022,10 @@ module mkCore(CLK, csrf_mscratch_csr$D_IN[63] ; assign csrf_scause_interrupt_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 || + csrf_prv_reg_read__2891_ULE_1_4504_AND_IF_comm_ETC___d14543 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -13027,7 +13033,7 @@ module mkCore(CLK, assign csrf_scounteren_cy_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -13035,7 +13041,7 @@ module mkCore(CLK, assign csrf_scounteren_ir_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -13043,7 +13049,7 @@ module mkCore(CLK, assign csrf_scounteren_tm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd11 ; // register csrf_sepc_csr @@ -13053,10 +13059,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] ; assign csrf_sepc_csr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 || + csrf_prv_reg_read__2891_ULE_1_4504_AND_IF_comm_ETC___d14543 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd13 ; // register csrf_software_int_en_vec_0 @@ -13064,9 +13070,9 @@ module mkCore(CLK, assign csrf_software_int_en_vec_0$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd9 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd22) ; // register csrf_software_int_en_vec_1 @@ -13074,9 +13080,9 @@ module mkCore(CLK, assign csrf_software_int_en_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd9 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd22) ; // register csrf_software_int_en_vec_3 @@ -13084,7 +13090,7 @@ module mkCore(CLK, assign csrf_software_int_en_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd22 ; // register csrf_software_int_pend_vec_0 @@ -13108,7 +13114,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd1 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd29 ; // register csrf_spp_reg @@ -13118,7 +13124,7 @@ module mkCore(CLK, MUX_csrf_spp_reg$write_1__VAL_2 ; assign csrf_spp_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 || + csrf_prv_reg_read__2891_ULE_1_4504_AND_IF_comm_ETC___d14543 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_sscratch_csr @@ -13126,7 +13132,7 @@ module mkCore(CLK, assign csrf_sscratch_csr$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd12 ; // register csrf_stats_module_doStats @@ -13140,10 +13146,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] ; assign csrf_stval_csr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 || + csrf_prv_reg_read__2891_ULE_1_4504_AND_IF_comm_ETC___d14543 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd15 ; // register csrf_stvec_base_hi_reg @@ -13151,7 +13157,7 @@ module mkCore(CLK, assign csrf_stvec_base_hi_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd10 ; // register csrf_stvec_mode_low_reg @@ -13159,7 +13165,7 @@ module mkCore(CLK, assign csrf_stvec_mode_low_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd10 ; // register csrf_sum_reg @@ -13167,9 +13173,9 @@ module mkCore(CLK, assign csrf_sum_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd8 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18) ; // register csrf_time_reg @@ -13181,9 +13187,9 @@ module mkCore(CLK, assign csrf_timer_int_en_vec_0$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd9 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd22) ; // register csrf_timer_int_en_vec_1 @@ -13191,9 +13197,9 @@ module mkCore(CLK, assign csrf_timer_int_en_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd9 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd22) ; // register csrf_timer_int_en_vec_3 @@ -13201,7 +13207,7 @@ module mkCore(CLK, assign csrf_timer_int_en_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd22 ; // register csrf_timer_int_pend_vec_0 @@ -13225,7 +13231,7 @@ module mkCore(CLK, assign csrf_tsr_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18 ; // register csrf_tvm_reg @@ -13233,7 +13239,7 @@ module mkCore(CLK, assign csrf_tvm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18 ; // register csrf_tw_reg @@ -13241,7 +13247,7 @@ module mkCore(CLK, assign csrf_tw_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18 ; // register csrf_vm_mode_sv39_reg @@ -13249,7 +13255,7 @@ module mkCore(CLK, assign csrf_vm_mode_sv39_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd17 ; // register flush_reservation @@ -13266,7 +13272,7 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[186:182] == 5'd16 || rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -15513,8 +15519,8 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h720707, - prv__h720707 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h720772, + prv__h720772 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -16349,7 +16355,7 @@ module mkCore(CLK, assign csrf_stats_module_writeQ$ENQ = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -16358,7 +16364,7 @@ module mkCore(CLK, assign csrf_terminate_module_terminateQ$ENQ = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -17639,7 +17645,7 @@ module mkCore(CLK, .checkForException_csrState({ x_decodeInfo_frm__h659284, r1__read_BITS_13_TO_12___h659469 != 2'd0, - { prv__h720663, + { prv__h720728, csrf_tvm_reg, { r1__read_BIT_20___h660097, csrf_tsr_reg, @@ -17669,7 +17675,7 @@ module mkCore(CLK, .checkForException_csrState({ x_decodeInfo_frm__h659284, r1__read_BITS_13_TO_12___h659469 != 2'd0, - { prv__h720663, + { prv__h720728, csrf_tvm_reg, { r1__read_BIT_20___h660097, csrf_tsr_reg, @@ -22096,10 +22102,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d13949 = IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d13942 || - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2863_BIT_160__ETC___d14136 = @@ -22133,10 +22139,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2872_BITS_194_ETC___d14029 && IF_fetchStage_RDY_pipelines_1_first__2871_AND__ETC___d13836 && (IF_fetchStage_pipelines_1_first__2872_BITS_194_ETC___d14054 || - fetchStage$RDY_pipelines_1_deq && + rob$RDY_enqPort_1_enq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - rob_RDY_enqPort_1_enq__4056_AND_NOT_fetchStage_ETC___d14064) ; + fetchStage_RDY_pipelines_1_deq__2875_AND_NOT_f_ETC___d14064) ; assign IF_fetchStage_pipelines_1_first__2872_BITS_194_ETC___d14349 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2861_2862_O_ETC___d14284 && @@ -22177,13 +22183,13 @@ module mkCore(CLK, mmio_pRsQ_enqReq_rl[67] ; assign IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d14987 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h718580 : + y_avValue_snd_snd_snd_snd_snd__h718631 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15076 = - rob$deqPort_0_canDeq ? y_avValue_fst__h718154 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_fst__h718199 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15097 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h718574 : + y_avValue_snd_snd_snd_fst__h718625 : 2'd0 ; assign IF_rob_deqPort_1_canDeq__4882_THEN_IF_NOT_rob__ETC___d15089 = rob$deqPort_1_canDeq ? @@ -22310,10 +22316,10 @@ module mkCore(CLK, !checkForException___d13706[4] && NOT_csrf_fs_reg_read__1710_EQ_0_3078_3079_OR_N_ETC___d13731 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__4878_4879_OR__ETC___d15094 = - (fflags__h719149 & csrf_fflags_reg) != fflags__h719149 || + (fflags__h719214 & csrf_fflags_reg) != fflags__h719214 || !r__h617822 && (IF_rob_deqPort_1_canDeq__4882_THEN_IF_NOT_rob__ETC___d15089 || - fflags__h719149 != 5'd0) ; + fflags__h719214 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 = !f2_sfd__h525459[21] && !f2_sfd__h525459[20] && !f2_sfd__h525459[19] && @@ -22436,7 +22442,7 @@ module mkCore(CLK, !f3_sfd__h564763[1] && !f3_sfd__h564763[0] ; assign NOT_IF_rob_deqPort_0_deq_data__4363_BITS_97_TO_ETC___d14849 = - next_pc__h715242 != + next_pc__h715267 != rob_deqPort_0_deq_data__4363_BITS_282_TO_219_4_ETC___d14846 ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13511 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__346_ETC___d13509 && @@ -23063,11 +23069,11 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 = - !csrf_prv_reg_read__2891_ULE_1___d14503 || + assign NOT_csrf_prv_reg_read__2891_ULE_1_4504_4567_OR_ETC___d14571 = + !csrf_prv_reg_read__2891_ULE_1___d14504 || (commitStage_commitTrap[4] ? - !_0b0_CONCAT_csrf_mideleg_11_reg_read__1823_1824_ETC___d14521 : - !_0b0_CONCAT_csrf_medeleg_15_reg_read__1815_1816_ETC___d14540) ; + !_0b0_CONCAT_csrf_mideleg_11_reg_read__1823_1824_ETC___d14522 : + !_0b0_CONCAT_csrf_medeleg_15_reg_read__1815_1816_ETC___d14541) ; assign NOT_fetchStage_pipelines_0_canDeq__2861_2862_O_ETC___d13817 = (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && @@ -23445,10 +23451,10 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || fetchStage_pipelines_1_first__2872_BIT_68_3583_ETC___d13972 ; - assign NOT_rob_deqPort_0_canDeq__4878_4879_OR_regRena_ETC___d14917 = + assign NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_RDY_ETC___d14917 = (!rob$deqPort_0_canDeq || - regRenamingTable$RDY_commit_0_commit && - rob$RDY_deqPort_0_deq) && + rob$RDY_deqPort_0_deq && + regRenamingTable$RDY_commit_0_commit) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && NOT_rob_deqPort_1_deq_data__4885_BIT_25_4886_4_ETC___d14914) ; @@ -23466,12 +23472,12 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] != 5'd19 && rob$deqPort_0_deq_data[186:182] != 5'd20) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__4363_BITS_186_TO_1_ETC___d14674 = + assign NOT_rob_deqPort_0_deq_data__4363_BITS_186_TO_1_ETC___d14675 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 != + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 != + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; assign NOT_rob_deqPort_0_deq_data__4363_BITS_186_TO_1_ETC___d14859 = @@ -23489,7 +23495,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20 || - regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; + rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ; assign NOT_specTagManager_canClaim__3434_3519_OR_NOT__ETC___d13995 = !specTagManager$canClaim || NOT_regRenamingTable_rename_0_canRename__3436__ETC___d13861 || @@ -23965,10 +23971,10 @@ module mkCore(CLK, (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434) ; - assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1815_1816_ETC___d14540 = - medeleg_csr__read__h616107[i__h704648] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1823_1824_ETC___d14521 = - mideleg_csr__read__h616202[i__h704808] ; + assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1815_1816_ETC___d14541 = + medeleg_csr__read__h616107[i__h704688] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1823_1824_ETC___d14522 = + mideleg_csr__read__h616202[i__h704848] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107 = 12'd3074 - { 6'd0, @@ -24579,14 +24585,14 @@ module mkCore(CLK, fetchStage$pipelines_1_first[191:189] != 3'd2 ; assign _dfoo20 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18 || rob$deqPort_0_deq_data[186:182] == 5'd20 ; assign _dfoo26 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd8 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd18) || rob$deqPort_0_deq_data[186:182] == 5'd19 ; assign _dfoo7 = @@ -27462,10 +27468,10 @@ module mkCore(CLK, assign b__h607534 = { {64{b__h607311[63]}}, b__h607311 } ; assign b__h607635 = { 64'd0, a__h607310 } ; assign b__h607647 = { 64'd0, b__h607311 } ; - assign base__h707219 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h707422 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h704633 = - commitStage_commitTrap[4] ? i__h704808 : i__h704648 ; + assign base__h707259 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h707462 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h704673 = + commitStage_commitTrap[4] ? i__h704848 : i__h704688 ; assign coreFix_aluExe_0_bypassWire_0_wget__2326_BITS__ETC___d12328 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -28091,14 +28097,14 @@ module mkCore(CLK, !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && !coreFix_memExe_respLrScAmoQ_deqReq_rl) && coreFix_memExe_respLrScAmoQ_full ; - assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14679 = + assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14680 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + regRenamingTable$RDY_commit_0_commit && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4363_BITS_186_TO_1_ETC___d14674 ; + NOT_rob_deqPort_0_deq_data__4363_BITS_186_TO_1_ETC___d14675 ; assign csrf_external_int_en_vec_3_read__1834_AND_csrf_ETC___d12899 = { csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3, 1'd0, @@ -28146,12 +28152,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 = - csrf_prv_reg_read__2891_ULE_1___d14503 && + assign csrf_prv_reg_read__2891_ULE_1_4504_AND_IF_comm_ETC___d14543 = + csrf_prv_reg_read__2891_ULE_1___d14504 && (commitStage_commitTrap[4] ? - _0b0_CONCAT_csrf_mideleg_11_reg_read__1823_1824_ETC___d14521 : - _0b0_CONCAT_csrf_medeleg_15_reg_read__1815_1816_ETC___d14540) ; - assign csrf_prv_reg_read__2891_ULE_1___d14503 = csrf_prv_reg <= 2'd1 ; + _0b0_CONCAT_csrf_mideleg_11_reg_read__1823_1824_ETC___d14522 : + _0b0_CONCAT_csrf_medeleg_15_reg_read__1815_1816_ETC___d14541) ; + assign csrf_prv_reg_read__2891_ULE_1___d14504 = csrf_prv_reg <= 2'd1 ; assign csrf_prv_reg_read__2891_ULT_IF_fetchStage_pipe_ETC___d13121 = csrf_prv_reg < IF_fetchStage_pipelines_0_first__2863_BIT_173__ETC___d13116[9:8] ; @@ -28244,14 +28250,6 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__2863_BITS_19_ETC___d13456 ; - assign fetchStage_RDY_pipelines_0_first__2860_AND_epo_ETC___d13333 = - fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - rob$RDY_enqPort_0_enq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_RDY_pipelines_0_first__2860_AND_fet_ETC___d13525 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && @@ -28259,6 +28257,12 @@ module mkCore(CLK, !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2860_AND__ETC___d13463 ; + assign fetchStage_RDY_pipelines_1_deq__2875_AND_NOT_f_ETC___d14064 = + fetchStage$RDY_pipelines_1_deq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3434_3519_OR_NOT__ETC___d14060) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14006 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -28461,9 +28465,9 @@ module mkCore(CLK, !epochManager$checkEpoch_1_check || fetchStage$pipelines_0_canDeq && fetchStage_pipelines_0_first__2863_BITS_194_TO_ETC___d13957 ; - assign fflags__h719149 = + assign fflags__h719214 = NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_deq_ETC___d15070 ? - y_avValue_fst__h719096 : + y_avValue_fst__h719161 : IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15076 ; assign fflags_csr__read__h615090 = { 59'd0, csrf_fflags_reg } ; assign frm_csr__read__h615101 = { 61'd0, csrf_frm_reg } ; @@ -28684,7 +28688,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h716001 = + assign n__read__h716026 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; @@ -28702,7 +28706,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; assign next_deqP___1__h332577 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; assign next_deqP___1__h335802 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h715242 = + assign next_pc__h715267 = (rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob_deqPort_0_deq_data__4363_BITS_282_TO_219_4_ETC___d14846 ; @@ -28919,8 +28923,8 @@ module mkCore(CLK, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ; - assign prv__h720663 = csrf_prv_reg ; - assign prv__h720707 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign prv__h720728 = csrf_prv_reg ; + assign prv__h720772 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; assign q___1__h479718 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ; @@ -29048,6 +29052,14 @@ module mkCore(CLK, 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; assign r__h617822 = csrf_fs_reg == 2'b11 ; + assign regRenamingTable_RDY_rename_0_getRename__3324__ETC___d13333 = + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign regRenamingTable_RDY_rename_0_getRename__3324__ETC___d13936 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 && @@ -29469,12 +29481,6 @@ module mkCore(CLK, guard__h585958 } ; assign result__h651528 = w__h651523 & y__h651557 ; assign result__h651579 = ~x__h651578 ; - assign rob_RDY_enqPort_1_enq__4056_AND_NOT_fetchStage_ETC___d14064 = - rob$RDY_enqPort_1_enq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3434_3519_OR_NOT__ETC___d14060) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4363_BITS_282_TO_219_4_ETC___d14846 = rob$deqPort_0_deq_data[282:219] + 64'd4 ; assign rob_enqPort_1_canEnq__3735_AND_epochManager_ch_ETC___d13740 = @@ -29925,11 +29931,11 @@ module mkCore(CLK, rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h707234 = { cause_code__h704633, 2'b0 } ; - assign x__h715411 = { 1'b0, csrf_spp_reg } ; - assign x__h719396 = + assign x__h707274 = { cause_code__h704673, 2'b0 } ; + assign x__h715436 = { 1'b0, csrf_spp_reg } ; + assign x__h719461 = NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_deq_ETC___d15070 ? - y_avValue_snd_snd_snd_fst__h719219 : + y_avValue_snd_snd_snd_fst__h719284 : IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15097 ; assign x__h75587 = mmio_pRqQ_data_0[31:0] ; assign x_addr__h317663 = @@ -29973,9 +29979,9 @@ module mkCore(CLK, 1'd1, ~csrf_mideleg_1_0_reg } ; assign y__h689793 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h719172 = + assign y__h719237 = NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_deq_ETC___d15070 ? - y_avValue_snd_snd_snd_snd_snd__h719225 : + y_avValue_snd_snd_snd_snd_snd__h719290 : IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d14987 ; assign y_avValue__h183583 = NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611 ? @@ -30013,19 +30019,19 @@ module mkCore(CLK, NOT_coreFix_aluExe_0_bypassWire_0_whas__2325_2_ETC___d12382 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__232_ETC___d12569 ; - assign y_avValue__h705503 = + assign y_avValue__h705543 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h707219 + { 58'd0, x__h707234 } : - base__h707219 ; - assign y_avValue__h707256 = + base__h707259 + { 58'd0, x__h707274 } : + base__h707259 ; + assign y_avValue__h707296 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h707422 + { 58'd0, x__h707234 } : - base__h707422 ; + base__h707462 + { 58'd0, x__h707274 } : + base__h707462 ; assign y_avValue_fst__h683177 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? spec_bits__h689780 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h718154 = + assign y_avValue_fst__h718199 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -30039,10 +30045,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h719068 = + assign y_avValue_fst__h719133 = IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15076 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h719096 = + assign y_avValue_fst__h719161 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -30055,7 +30061,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15076 : - y_avValue_fst__h719068 ; + y_avValue_fst__h719133 ; assign y_avValue_snd_fst__h683451 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && @@ -30067,7 +30073,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d13516 ? y_avValue_fst__h683177 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h718574 = + assign y_avValue_snd_snd_snd_fst__h718625 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -30081,7 +30087,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h719219 = + assign y_avValue_snd_snd_snd_fst__h719284 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -30094,11 +30100,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15097 : - y_avValue_snd_snd_snd_fst__h719248 ; - assign y_avValue_snd_snd_snd_fst__h719248 = + y_avValue_snd_snd_snd_fst__h719313 ; + assign y_avValue_snd_snd_snd_fst__h719313 = IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15097 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h718580 = + assign y_avValue_snd_snd_snd_snd_snd__h718631 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -30112,7 +30118,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h719225 = + assign y_avValue_snd_snd_snd_snd_snd__h719290 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -30125,8 +30131,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d14987 : - y_avValue_snd_snd_snd_snd_snd__h719254 ; - assign y_avValue_snd_snd_snd_snd_snd__h719254 = + y_avValue_snd_snd_snd_snd_snd__h719319 ; + assign y_avValue_snd_snd_snd_snd_snd__h719319 = IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d14987 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -30253,8 +30259,8 @@ module mkCore(CLK, always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) - 4'd0, 4'd3: trap_val__h705656 = commitStage_commitTrap[132:69]; - default: trap_val__h705656 = + 4'd0, 4'd3: trap_val__h705696 = commitStage_commitTrap[132:69]; + default: trap_val__h705696 = (commitStage_commitTrap[3:0] != 4'd2 && commitStage_commitTrap[3:0] != 4'd8 && commitStage_commitTrap[3:0] != 4'd9 && @@ -30660,16 +30666,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h704648 = commitStage_commitTrap[3:0]; - default: i__h704648 = 4'd15; + i__h704688 = commitStage_commitTrap[3:0]; + default: i__h704688 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9: - i__h704808 = commitStage_commitTrap[3:0]; - default: i__h704808 = 4'd11; + i__h704848 = commitStage_commitTrap[3:0]; + default: i__h704848 = 4'd11; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -35657,78 +35663,78 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[180:169]) 12'd1: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd0; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd1; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd2; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd8; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd9; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd10; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd11; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd12; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd13; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd14; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd15; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd16; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd17; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd18; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd18; 12'd769: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd19; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd19; 12'd770: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd20; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd20; 12'd771: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd21; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd21; 12'd772: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd22; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd22; 12'd773: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd23; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd23; 12'd774: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd24; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd24; 12'd832: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd25; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd25; 12'd833: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd26; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd26; 12'd834: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd27; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd27; 12'd835: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd28; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd28; 12'd836: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd29; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd29; 12'd2048: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd6; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd7; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd7; 12'd2816: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd30; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd30; 12'd2818: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd31; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd31; 12'd3072: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd3; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd4; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd5; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd32; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd32; 12'd3858: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd33; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd33; 12'd3859: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd34; + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd34; 12'd3860: - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = 6'd35; - default: IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 = + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd35; + default: IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 = 6'd36; endcase end @@ -38385,7 +38391,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == 6'd6) + IF_rob_deqPort_0_deq_data__4363_BIT_181_4591_T_ETC___d14665 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); @@ -38565,7 +38571,7 @@ module mkCore(CLK, if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && !rob$deqPort_0_deq_data[168]) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 815, column 49\nshould have renamed"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 814, column 49\nshould have renamed"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && @@ -38774,7 +38780,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] != 5'd19 && rob$deqPort_1_deq_data[186:182] != 5'd20 && !rob$deqPort_1_deq_data[168]) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 815, column 49\nshould have renamed"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 814, column 49\nshould have renamed"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v index 549c8fb..4bb9ec5 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v @@ -2271,7 +2271,7 @@ module mkCoreW(RST_N_dm_power_on_reset, v__h6484 = v__h6490 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) - $display("%0d: %m.method start: proc.start (pc %0d, tohostAddr %0h, fromhostAddr %0h)", + $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", v__h6484, 64'h0000000000001000, start_tohost_addr, diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v index 2966d6a..259ed8c 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v @@ -1891,8 +1891,8 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h161964; - reg [31 : 0] v__h161528; + reg [31 : 0] v__h161116; + reg [31 : 0] v__h160680; reg [31 : 0] v__h3916; reg [31 : 0] v__h4089; reg [31 : 0] v__h4353; @@ -1901,16 +1901,13 @@ module mkProc(CLK, reg [31 : 0] v__h6690; reg [31 : 0] v__h7183; reg [31 : 0] v__h7346; - reg [31 : 0] v__h99954; - reg [31 : 0] v__h100752; - reg [31 : 0] v__h100901; - reg [31 : 0] v__h133485; - reg [31 : 0] v__h133652; - reg [31 : 0] v__h135755; - reg [31 : 0] v__h153099; - reg [31 : 0] v__h132866; - reg [31 : 0] v__h159793; - reg [31 : 0] v__h160301; + reg [31 : 0] v__h132637; + reg [31 : 0] v__h132804; + reg [31 : 0] v__h134907; + reg [31 : 0] v__h152251; + reg [31 : 0] v__h132018; + reg [31 : 0] v__h158945; + reg [31 : 0] v__h159453; reg [31 : 0] v__h2186; reg [31 : 0] v__h3910; reg [31 : 0] v__h4083; @@ -1919,18 +1916,15 @@ module mkProc(CLK, reg [31 : 0] v__h6684; reg [31 : 0] v__h7177; reg [31 : 0] v__h7340; - reg [31 : 0] v__h99948; - reg [31 : 0] v__h100746; - reg [31 : 0] v__h100895; - reg [31 : 0] v__h132860; - reg [31 : 0] v__h133479; - reg [31 : 0] v__h133646; - reg [31 : 0] v__h135749; - reg [31 : 0] v__h153093; - reg [31 : 0] v__h159787; - reg [31 : 0] v__h160295; - reg [31 : 0] v__h161522; - reg [31 : 0] v__h161958; + reg [31 : 0] v__h132012; + reg [31 : 0] v__h132631; + reg [31 : 0] v__h132798; + reg [31 : 0] v__h134901; + reg [31 : 0] v__h152245; + reg [31 : 0] v__h158939; + reg [31 : 0] v__h159447; + reg [31 : 0] v__h160674; + reg [31 : 0] v__h161110; // synopsys translate_on // remaining internal signals @@ -1956,9 +1950,9 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883, IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851, IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853, - data64__h146925, + data64__h146077, dword__h91879, - ld_data__h131014, + ld_data__h130166, old_dword__h87569, w1__h45436, w1__h45441, @@ -1966,7 +1960,7 @@ module mkProc(CLK, w2__h45443, x__h45432; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d951; - reg [7 : 0] strb8__h146926; + reg [7 : 0] strb8__h146078; reg [5 : 0] IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441; reg [2 : 0] x__h59150; reg [1 : 0] CASE_x7721_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, @@ -1985,10 +1979,10 @@ module mkProc(CLK, wire [513 : 0] IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1281; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1273, SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1423, - new_cline__h133788; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1561, + new_cline__h132940; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1560, SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1406; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1556, + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1555, SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1389; wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1372; wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__42_BITS_14_ETC___d365; @@ -2007,12 +2001,12 @@ module mkProc(CLK, IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1167, IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1205, data__h29160, - failed_testnum__h161571, - line_addr__h100665, - line_addr__h100814, + failed_testnum__h160723, + line_addr__h100029, + line_addr__h99943, mask__h87566, - mem_req_rd_addr_araddr__h133086, - mem_req_wr_addr_awaddr__h147010, + mem_req_rd_addr_araddr__h132238, + mem_req_wr_addr_awaddr__h146162, mmioPlatform_fromHostQ_data_0__h40007, mmioPlatform_mtime__h34474, mmioPlatform_reqData__h46028, @@ -2020,7 +2014,7 @@ module mkProc(CLK, n__read_addr__h59103, n__read_addr__h77899, n__read_addr__h77978, - n__read_snd_addr__h122318, + n__read_snd_addr__h121470, newData__h29241, newData__h32171, new_dword__h87570, @@ -2106,9 +2100,9 @@ module mkProc(CLK, w25437_BITS_31_TO_0__q8, x_data__h27743; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__064_TH_ETC___d1128; - wire [5 : 0] x__h133121, x__h147035; + wire [5 : 0] x__h132273, x__h146187; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__064_AND_I_ETC___d1127; - wire [3 : 0] b__h132793, b__h2086; + wire [3 : 0] b__h131945, b__h2086; wire [2 : 0] n__read_id__h59022, n__read_id__h59107; wire [1 : 0] IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1258, IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1080, @@ -2128,8 +2122,8 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1243, IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1263, IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1279, - IF_llc_mem_server_enqDst_0_lat_0_whas__647_THE_ETC___d1652, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__632_ETC___d1635, + IF_llc_mem_server_enqDst_0_lat_0_whas__640_THE_ETC___d1645, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__625_ETC___d1628, IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585, IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d417, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164, @@ -2143,8 +2137,8 @@ module mkProc(CLK, IF_propDstIdx_1_lat_0_whas__80_THEN_propDstIdx_ETC___d983, NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063, NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337, - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685, + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__671_ETC___d1678, NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714, NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d722, NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d727, @@ -2165,8 +2159,8 @@ module mkProc(CLK, NOT_propDstIdx_1_0_dummy2_1_read__290_291_OR_I_ETC___d1334, NOT_propDstIdx_1_1_dummy2_1_read__308_309_OR_I_ETC___d1441, NOT_propDstIdx_1_dummy2_1_read__039_040_OR_IF__ETC___d1139, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1572, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1494, mmioPlatform_cycle_11_ULT_99___d312, mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d295, @@ -2182,7 +2176,7 @@ module mkProc(CLK, n__read_child__h59108, n__read_child__h77902, n__read_child__h77981, - n__read_snd_id__h122319, + n__read_snd_id__h121471, propDstData_0_dummy2_1_read__064_AND_IF_propDs_ETC___d1100, propDstData_1_dummy2_1_read__069_AND_IF_propDs_ETC___d1104, x__h58836, @@ -3085,16 +3079,16 @@ module mkProc(CLK, // rule RL_srcPropose assign CAN_FIRE_RL_srcPropose = - core_0$RDY_dCacheToParent_rqToP_deq && core_0$RDY_dCacheToParent_rqToP_first && + core_0$RDY_dCacheToParent_rqToP_deq && (!propDstIdx_0_dummy2_0$Q_OUT || !propDstIdx_0_dummy2_1$Q_OUT || !propDstIdx_0_rl) ; assign WILL_FIRE_RL_srcPropose = CAN_FIRE_RL_srcPropose ; // rule RL_srcPropose_1 assign CAN_FIRE_RL_srcPropose_1 = - core_0$RDY_iCacheToParent_rqToP_deq && core_0$RDY_iCacheToParent_rqToP_first && + core_0$RDY_iCacheToParent_rqToP_deq && (!propDstIdx_1_dummy2_0$Q_OUT || !propDstIdx_1_dummy2_1$Q_OUT || !propDstIdx_1_rl) ; assign WILL_FIRE_RL_srcPropose_1 = CAN_FIRE_RL_srcPropose_1 ; @@ -3111,8 +3105,8 @@ module mkProc(CLK, // rule RL_srcPropose_2 assign CAN_FIRE_RL_srcPropose_2 = - core_0$RDY_dCacheToParent_rsToP_deq && core_0$RDY_dCacheToParent_rsToP_first && + core_0$RDY_dCacheToParent_rsToP_deq && (!propDstIdx_1_0_dummy2_0$Q_OUT || !propDstIdx_1_0_dummy2_1$Q_OUT || !propDstIdx_1_0_rl) ; @@ -3120,8 +3114,8 @@ module mkProc(CLK, // rule RL_srcPropose_3 assign CAN_FIRE_RL_srcPropose_3 = - core_0$RDY_iCacheToParent_rsToP_deq && core_0$RDY_iCacheToParent_rsToP_first && + core_0$RDY_iCacheToParent_rsToP_deq && (!propDstIdx_1_1_dummy2_0$Q_OUT || !propDstIdx_1_1_dummy2_1$Q_OUT || !propDstIdx_1_1_rl) ; @@ -3139,32 +3133,36 @@ module mkProc(CLK, // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && !llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ; // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && !llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ; // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ; // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ; @@ -3333,8 +3331,8 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMTimeCmpDone assign CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone = - core_0$RDY_mmioToPlatform_pRs_enq && core_0$RDY_mmioToPlatform_cRs_deq && + core_0$RDY_mmioToPlatform_pRs_enq && mmioPlatform_curReq[66:64] == 3'd3 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone = @@ -3503,7 +3501,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1572 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3521,7 +3519,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1494 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3539,7 +3537,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1494 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3549,7 +3547,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1572 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -3558,7 +3556,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && !llc$dma_respSt_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd1 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = @@ -3569,7 +3567,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1494 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3578,7 +3576,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1572 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -3586,7 +3584,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && !llc$dma_respLd_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd2 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = @@ -3594,8 +3592,8 @@ module mkProc(CLK, // rule RL_llc_mem_server_srcPropose assign CAN_FIRE_RL_llc_mem_server_srcPropose = - core_0$RDY_tlbToMem_memReq_deq && core_0$RDY_tlbToMem_memReq_first && + core_0$RDY_tlbToMem_memReq_deq && (!llc_mem_server_propDstIdx_0_dummy2_0$Q_OUT || !llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT || !llc_mem_server_propDstIdx_0_rl) ; @@ -3610,7 +3608,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__647_THE_ETC___d1652 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__640_THE_ETC___d1645 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -3627,15 +3625,15 @@ module mkProc(CLK, // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && - core_0$RDY_tlbToMem_respLd_enq && + core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_first && llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; @@ -3683,13 +3681,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h132793 == 4'd0 ; + b__h131945 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h132793 != 4'd0 && + b__h131945 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -3852,10 +3850,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h100665, + { line_addr__h99943, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h100814, + { line_addr__h100029, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -3863,7 +3861,7 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1561, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1560, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? new_dword__h87570 : @@ -4024,7 +4022,7 @@ module mkProc(CLK, CASE_x7721_0_n__read_addr7899_1_n__read_addr79_ETC__q26, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__338__ETC___d1430 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h122318, n__read_snd_id__h122319 } ; + { 1'd1, n__read_snd_addr__h121470, n__read_snd_id__h121471 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4126,11 +4124,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h132793 - 4'd1 ; + b__h131945 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h132793 ; + b__h131945 ; // register cfg_verbosity assign cfg_verbosity$D_IN = set_verbosity_verbosity ; @@ -4190,7 +4188,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h133086, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h132238, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4201,13 +4199,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h147010, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h146162, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h146925, strb8__h146926, 1'd1 } ; + { data64__h146077, strb8__h146078, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4219,7 +4217,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h133788 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h132940 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4250,10 +4248,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__647_THE_ETC___d1652, + IF_llc_mem_server_enqDst_0_lat_0_whas__640_THE_ETC___d1645, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__671_ETC___d1678 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4267,15 +4265,15 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__632_ETC___d1635 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__671_ETC___d1678 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__625_ETC___d1628 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h100665 : - line_addr__h100814 ; + line_addr__h99943 : + line_addr__h100029 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4852,7 +4850,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h131014, llc$dma_respLd_first[3] } ; + { ld_data__h130166, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -4988,7 +4986,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1273, IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1279 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h133788, + { new_cline__h132940, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5115,7 +5113,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__671_ETC___d1678 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5145,11 +5143,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__671_ETC___d1678 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__671_ETC___d1678 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5342,15 +5340,6 @@ module mkProc(CLK, assign propDstIdx_1_dummy2_1$EN = propDstIdx_1_lat_1$whas ; // remaining internal signals - module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27328 && - mmioPlatform_reqBE_BIT_0___h27368, - 2'd0 }), - .amoExec_current_data(x__h34622), - .amoExec_in_data(mmioPlatform_reqData__h46028), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27328 && - !mmioPlatform_reqBE_BIT_0___h27368), - .amoExec(x__h29352)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], mmioPlatform_reqBE_BIT_4___h27328 && mmioPlatform_reqBE_BIT_0___h27368, @@ -5360,6 +5349,15 @@ module mkProc(CLK, .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27328 && !mmioPlatform_reqBE_BIT_0___h27368), .amoExec(x__h32262)); + module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], + mmioPlatform_reqBE_BIT_4___h27328 && + mmioPlatform_reqBE_BIT_0___h27368, + 2'd0 }), + .amoExec_current_data(x__h34622), + .amoExec_in_data(mmioPlatform_reqData__h46028), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27328 && + !mmioPlatform_reqBE_BIT_0___h27368), + .amoExec(x__h29352)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], mmioPlatform_reqBE_BIT_4___h27328 && mmioPlatform_reqBE_BIT_0___h27368, @@ -5473,7 +5471,7 @@ module mkProc(CLK, 2'b10 : IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1258, IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1281 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1556 = + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1555 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? new_dword__h87570 : @@ -5490,8 +5488,8 @@ module mkProc(CLK, 3'd4) ? new_dword__h87570 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1561 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1556, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1560 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1555, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? new_dword__h87570 : @@ -5500,11 +5498,11 @@ module mkProc(CLK, 3'd2) ? new_dword__h87570 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__647_THE_ETC___d1652 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__640_THE_ETC___d1645 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__671_ETC___d1678 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__632_ETC___d1635 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__625_ETC___d1628 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; assign IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793 = @@ -5654,12 +5652,12 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_rl[64] ; assign IF_mmioPlatform_waitLowerMSIPCRs_52_THEN_core__ETC___d460 = mmioPlatform_waitLowerMSIPCRs ? - core_0$RDY_mmioToPlatform_cRs_deq && - core_0$RDY_mmioToPlatform_cRs_first : + core_0$RDY_mmioToPlatform_cRs_first && + core_0$RDY_mmioToPlatform_cRs_deq : (!mmioPlatform_waitUpperMSIPCRs || - core_0$RDY_mmioToPlatform_cRs_deq) && + core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || - core_0$RDY_mmioToPlatform_cRs_first) ; + core_0$RDY_mmioToPlatform_cRs_deq) ; assign IF_mmio_axi4_adapter_f_rsps_to_core_first__24__ETC___d938 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < @@ -5739,14 +5737,14 @@ module mkProc(CLK, !enqDst_1_0_rl[580]) && (SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_AND__ETC___d1331 || IF_NOT_propDstIdx_1_0_dummy2_1_read__290_291_O_ETC___d1335) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__671_ETC___d1678 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__632_ETC___d1635 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__625_ETC___d1628 ; assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && @@ -5827,8 +5825,8 @@ module mkProc(CLK, !mmioPlatform_mtip_0 && mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || !core_0$mmioToPlatform_cRq_notEmpty || - core_0$RDY_mmioToPlatform_cRq_deq && - core_0$RDY_mmioToPlatform_cRq_first ; + core_0$RDY_mmioToPlatform_cRq_first && + core_0$RDY_mmioToPlatform_cRq_deq ; assign NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || @@ -5909,7 +5907,7 @@ module mkProc(CLK, { CASE_x8836_0_propDstData_0_dummy2_1_read__064__ETC__q12, x__h59150, x__h59157 } ; - assign b__h132793 = + assign b__h131945 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -5921,18 +5919,18 @@ module mkProc(CLK, mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : { v__h28953, 32'd0 } ; - assign failed_testnum__h161571 = + assign failed_testnum__h160723 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h100665 = - { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], - 6'b0 } ; - assign line_addr__h100814 = + assign line_addr__h100029 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573 = - line_addr__h100814 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495 = - line_addr__h100665 == llc_mem_server_rg_cacheline_cache_addr ; + assign line_addr__h99943 = + { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], + 6'b0 } ; + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1572 = + line_addr__h100029 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1494 = + line_addr__h99943 == llc_mem_server_rg_cacheline_cache_addr ; assign mask__h87566 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : @@ -5958,10 +5956,10 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h133086 = - { llc$to_mem_toM_first[68:11], x__h133121 } ; - assign mem_req_wr_addr_awaddr__h147010 = - { llc$to_mem_toM_first[639:582], x__h147035 } ; + assign mem_req_rd_addr_araddr__h132238 = + { llc$to_mem_toM_first[68:11], x__h132273 } ; + assign mem_req_wr_addr_awaddr__h146162 = + { llc$to_mem_toM_first[639:582], x__h146187 } ; assign mmioPlatform_cycle_11_ULT_99___d312 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; @@ -6062,13 +6060,13 @@ module mkProc(CLK, propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h122318 = + assign n__read_snd_addr__h121470 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h122319 = + assign n__read_snd_id__h121471 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : @@ -6085,7 +6083,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd2) ? x__h32262 : IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d574 ; - assign new_cline__h133788 = + assign new_cline__h132940 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; assign new_dword__h87570 = x__h88732 | y__h88733 ; @@ -6229,8 +6227,8 @@ module mkProc(CLK, mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h133121 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h147035 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h132273 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h146187 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; assign x__h34622 = mmioPlatform_mtimecmp_0 ; assign x__h38197 = (mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -6310,40 +6308,40 @@ module mkProc(CLK, always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h146925 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h146925 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h146925 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h146925 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h146925 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h146925 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h146925 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h146925 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h146077 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h146077 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h146077 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h146077 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h146077 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h146077 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h146077 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h146077 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h131014 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h131014 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h131014 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h131014 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h131014 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h131014 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h131014 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h131014 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h130166 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h130166 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h130166 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h130166 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h130166 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h130166 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h130166 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h130166 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h146926 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h146926 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h146926 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h146926 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h146926 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h146926 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h146926 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h146926 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h146078 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h146078 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h146078 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h146078 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h146078 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h146078 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h146078 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h146078 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or @@ -6367,6 +6365,27 @@ module mkProc(CLK, old_dword__h87569 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end + always@(mmioPlatform_curReq or + result__h45852 or + result__h45880 or result__h45908 or result__h45936) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = + result__h45852; + 3'h2: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = + result__h45880; + 3'h4: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = + result__h45908; + 3'h6: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = + result__h45936; + default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = + 64'd0; + endcase + end always@(mmioPlatform_curReq or result__h45611 or result__h45639 or @@ -6402,27 +6421,6 @@ module mkProc(CLK, result__h45807; endcase end - always@(mmioPlatform_curReq or - result__h45852 or - result__h45880 or result__h45908 or result__h45936) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = - result__h45852; - 3'h2: - IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = - result__h45880; - 3'h4: - IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = - result__h45908; - 3'h6: - IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = - result__h45936; - default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = - 64'd0; - endcase - end always@(mmioPlatform_curReq or result__h45977 or result__h46005) begin case (mmioPlatform_curReq[2:0]) @@ -7516,14 +7514,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h161964 = $stime; + v__h161116 = $stime; #0; end - v__h161958 = v__h161964 / 32'd10; + v__h161110 = v__h161116 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h161958, + v__h161110, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -7593,14 +7591,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h161528 = $stime; + v__h160680 = $stime; #0; end - v__h161522 = v__h161528 / 32'd10; + v__h160674 = v__h160680 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h161522, + v__h160674, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -7610,7 +7608,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h161571); + $display("FAIL %0d", failed_testnum__h160723); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8770,52 +8768,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged) - begin - v__h99954 = $stime; - #0; - end - v__h99948 = v__h99954 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged) - $display("%0d: %m.fa_writeback line at %0h", - v__h99948, - llc_mem_server_rg_cacheline_cache_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged) - $display(" data %0128h", llc_mem_server_rg_cacheline_cache_data); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss) - begin - v__h100752 = $stime; - #0; - end - v__h100746 = v__h100752 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss) - $display("%0d: %m.fa_writeback line at %0h", - v__h100746, - llc_mem_server_rg_cacheline_cache_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss) - $display(" data %0128h", llc_mem_server_rg_cacheline_cache_data); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss) - begin - v__h100901 = $stime; - #0; - end - v__h100895 = v__h100901 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss) - $display("%0d: %m.fa_writeback line at %0h", - v__h100895, - llc_mem_server_rg_cacheline_cache_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss) - $display(" data %0128h", llc_mem_server_rg_cacheline_cache_data); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 && + if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__671_ETC___d1678 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -8829,85 +8782,85 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) begin - v__h133485 = $stime; + v__h132637 = $stime; #0; end - v__h133479 = v__h133485 / 32'd10; + v__h132631 = v__h132637 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h133479, + v__h132631, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769 && + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769 && + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h133652 = $stime; + v__h132804 = $stime; #0; end - v__h133646 = v__h133652 / 32'd10; + v__h132798 = v__h132804 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h133646); + v__h132798); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -8969,135 +8922,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769 && + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769 && + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h135755 = $stime; + v__h134907 = $stime; #0; end - v__h135749 = v__h135755 / 32'd10; + v__h134901 = v__h134907 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h135749); + v__h134901); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -10295,169 +10248,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h153099 = $stime; + v__h152251 = $stime; #0; end - v__h153093 = v__h153099 / 32'd10; + v__h152245 = v__h152251 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h153093); + $display("%0d: ERROR: CreditCounter: overflow", v__h152245); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) - $write("'h%h", mem_req_wr_addr_awaddr__h147010); + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) + $write("'h%h", mem_req_wr_addr_awaddr__h146162); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) - $write("'h%h", data64__h146925); + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) + $write("'h%h", data64__h146077); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) - $write("'h%h", strb8__h146926); + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) + $write("'h%h", strb8__h146078); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h132866 = $stime; + v__h132018 = $stime; #0; end - v__h132860 = v__h132866 / 32'd10; + v__h132012 = v__h132018 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h132860, + v__h132012, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -10528,159 +10481,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) - $write("'h%h", mem_req_rd_addr_araddr__h133086); + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) + $write("'h%h", mem_req_rd_addr_araddr__h132238); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) begin - v__h159793 = $stime; + v__h158945 = $stime; #0; end - v__h159787 = v__h159793 / 32'd10; + v__h158939 = v__h158945 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h159787, + v__h158939, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + NOT_llc_axi4_adapter_cfg_verbosity_read__744_U_ETC___d1761) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h160301 = $stime; + v__h159453 = $stime; #0; end - v__h160295 = v__h160301 / 32'd10; + v__h159447 = v__h159453 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h160295); + v__h159447); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index 05401da..01430d4 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -318,6 +318,12 @@ module mkCoreW #(Reset dm_power_on_reset) AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) dm_master_local = dummy_AXI4_Master_ifc; +`ifdef INCLUDE_TANDEM_VERIF + // TV, no DM: stub out the dm input to TV + Get #(Trace_Data) gs = getstub; + mkConnection (tv_encode.dm_in, gs); +`endif + `endif // for ifdef INCLUDE_GDB_CONTROL diff --git a/src_Core/Core/Trace_Data2_to_Trace_Data.bsv b/src_Core/Core/Trace_Data2_to_Trace_Data.bsv index 56c3758..a02d1ea 100644 --- a/src_Core/Core/Trace_Data2_to_Trace_Data.bsv +++ b/src_Core/Core/Trace_Data2_to_Trace_Data.bsv @@ -45,6 +45,7 @@ endinterface // ================================================================ +(* synthesize *) module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC); Integer verbosity = 0; // for debugging @@ -116,13 +117,14 @@ module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC); rule rl_xform; Trace_Data2 td2 <- pop (f_in); - match { .serialnum, .td } <- fav_xform (td2); - f_out.enq (tuple2 (serialnum, td)); if (verbosity != 0) $display ("%0d: %m.rl_xform: serialnum:%0d PC:0x%0h instr:0x%08h", cur_cycle, td2.serialnum, td2.pc, td2.orig_inst, " iType:", fshow (td2.iType)); + + match { .serialnum, .td } <- fav_xform (td2); + f_out.enq (tuple2 (serialnum, td)); endrule // ================================================================ diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv index ca63625..b69c35c 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv @@ -182,7 +182,6 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); inIfc.v_to_TV [way].put (x); endaction endfunction - `endif // func units @@ -467,10 +466,6 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); }); commitTrap <= commitTrap_val; -`ifdef INCLUDE_TANDEM_VERIF - fa_to_TV (rg_serialnum, x, 0); -`endif - if (verbosity >= 1) begin $display ("instret:%0d PC:0x%0h instr:0x%08h", rg_serialnum, x.pc, x.orig_inst, " iType:", fshow (x.iType), " [doCommitTrap]"); @@ -480,6 +475,11 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); $display ("CommitStage.doCommitTrap_flush: commitTrap: ", fshow (commitTrap_val)); end +`ifdef INCLUDE_TANDEM_VERIF + fa_to_TV (rg_serialnum, x, 0); +`endif + rg_serialnum <= rg_serialnum + 1; + // flush everything. Only increment epoch and stall fetch when we haven // not done it yet (we may have already done them at rename stage) inIfc.killAll; @@ -627,17 +627,17 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); rob.deqPort[0].deq; let x = rob.deqPort[0].deq_data; -`ifdef INCLUDE_TANDEM_VERIF - fa_to_TV (rg_serialnum, x, 0); -`endif - if(verbose) $display("[doCommitSystemInst] ", fshow(x)); if (verbosity >= 1) begin $display("instret:%0d PC:0x%0h instr:0x%08h", rg_serialnum, x.pc, x.orig_inst, " iType:", fshow (x.iType), " [doCommitSystemInst]"); - rg_serialnum <= rg_serialnum + 1; end +`ifdef INCLUDE_TANDEM_VERIF + fa_to_TV (rg_serialnum, x, 0); +`endif + rg_serialnum <= rg_serialnum + 1; + // we claim a phy reg for every inst, so commit its renaming regRenamingTable.commit[0].commit; @@ -795,17 +795,16 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); stop = True; end else begin -`ifdef INCLUDE_TANDEM_VERIF - fa_to_TV (rg_serialnum + instret, x, i); -`endif - if (verbose) $display("[doCommitNormalInst - %d] ", i, fshow(inst_tag), " ; ", fshow(x)); if (verbosity >= 1) begin $display("instret:%0d PC:0x%0h instr:0x%08h", rg_serialnum + instret, x.pc, x.orig_inst, " iType:", fshow (x.iType), " [doCommitNormalInst [%0d]]", i); - instret = instret + 1; end +`ifdef INCLUDE_TANDEM_VERIF + fa_to_TV (rg_serialnum + instret, x, i); +`endif + instret = instret + 1; // inst can be committed, deq it rob.deqPort[i].deq;