From 4a50ae5bc87976b0179f5c81c7378e395b1388e8 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Mon, 14 Jun 2021 15:13:35 +0100 Subject: [PATCH 1/5] Fix some misplaced ifdefs --- src_Core/CPU/CPU_Decode_C.bsv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src_Core/CPU/CPU_Decode_C.bsv b/src_Core/CPU/CPU_Decode_C.bsv index d242c73..56c5a42 100644 --- a/src_Core/CPU/CPU_Decode_C.bsv +++ b/src_Core/CPU/CPU_Decode_C.bsv @@ -146,17 +146,17 @@ function Instr fv_decode_C (MISA misa, Bit #(2) xl, Bool cap_enc, Instr_C instr_ else if (valid_C_SUBW) instr = i_C_SUBW; else if (valid_C_EBREAK) instr = i_C_EBREAK; -`ifdef RV64 else if (valid_C_LDSP) instr = i_C_LDSP; else if (valid_C_SDSP) instr = i_C_SDSP; else if (valid_C_LD) instr = i_C_LD; else if (valid_C_SD) instr = i_C_SD; -`endif +`ifdef RV64 else if (valid_C_LQSP) instr = i_C_LQSP; else if (valid_C_SQSP) instr = i_C_SQSP; else if (valid_C_LQ) instr = i_C_LQ; else if (valid_C_SQ) instr = i_C_SQ; +`endif `ifdef ISA_F else if (valid_C_FLWSP) instr = i_C_FLWSP; From b48a161fdacf2d13d75388d7d8efef6574b497bf Mon Sep 17 00:00:00 2001 From: jon <> Date: Fri, 25 Jun 2021 17:31:10 +0100 Subject: [PATCH 2/5] Experimentally remove repeated write of rg_m_halt_req register. --- src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 2 -- 1 file changed, 2 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index fe02243..081b156 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -324,8 +324,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); ); fetchStage.pipelines[0].deq; `ifdef INCLUDE_GDB_CONTROL - fa_step_check; - if (verbosity >= 1) begin if (firstTrap == tagged Valid (tagged Interrupt intrDebugHalt)) $display ("%0d: %m.renameStage.doRenaming_Trap: intrDebugHalt", cur_cycle); From db6a91e0fd27b1c322c877835d107ff40dac4366 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Tue, 6 Jul 2021 15:19:37 +0100 Subject: [PATCH 3/5] mad Maps flush on reset --- src_Core/RISCY_OOO/procs/lib/Map.bsv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/lib/Map.bsv b/src_Core/RISCY_OOO/procs/lib/Map.bsv index 64ac758..23f10fe 100644 --- a/src_Core/RISCY_OOO/procs/lib/Map.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Map.bsv @@ -70,7 +70,7 @@ Bitwise#(ix), Eq#(ix), Arith#(ix)); Reg#(Bit#(TLog#(as))) wayNext <- mkReg(0); Integer a = valueof(as); - Reg#(Bool) clearReg <- mkReg(False); + Reg#(Bool) clearReg <- mkReg(True); Reg#(ix) clearCount <- mkReg(0); PulseWire didUpdate <- mkPulseWire; rule doClear(clearReg && !didUpdate); @@ -137,7 +137,7 @@ Bitwise#(ix), Eq#(ix), Arith#(ix), PrimIndex#(ix, a__)); Reg#(Bit#(TLog#(as))) wayNext <- mkReg(0); Integer a = valueof(as); - Reg#(Bool) clearReg <- mkReg(False); + Reg#(Bool) clearReg <- mkReg(True); Reg#(ix) clearCount <- mkReg(0); (* fire_when_enabled, no_implicit_conditions *) rule updateCanon; From 994321e527da77ec656d6c7ad1f05967736c6293 Mon Sep 17 00:00:00 2001 From: jon <> Date: Wed, 7 Jul 2021 11:26:34 +0100 Subject: [PATCH 4/5] Potential fix for lockup condition where the (undefined) bits of instruction returned for an invalid fetch (that is, with a valid cause) indicate a 2-fragment instruction but where a second fragment is not available. --- src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index e04b216..44cc2eb 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -624,7 +624,7 @@ module mkFetchStage(FetchStage); doAssert(prev_frag.dii_pid+1 == frag.dii_pid, "Attached fragments with non-contigious DII IDs"); `endif end - end else if (is_16b_inst(frag.inst_frag)) begin // 16-bit instruction + end else if (is_16b_inst(frag.inst_frag) || isValid(frag.cause)) begin // 16-bit instruction new_pick = tagged Valid fetch3_2_instC(frag, fv_decode_C (misa, misa_mxl_64, getFlags(decompressPc(frag.pc))==1, frag.inst_frag), zeroExtend(frag.inst_frag)); From 849d5c57f8f0b56c00a8ee207f3722bdd51a2c9c Mon Sep 17 00:00:00 2001 From: jon <> Date: Wed, 7 Jul 2021 11:30:06 +0100 Subject: [PATCH 5/5] Fix condition where Queue can remain "empty" when there were outstanding indices due to the head-1 element happening to match new requests. This leads to "remove" when empty, leading to being "almostFull" when there are no outstanding users that will remove anything. --- src_Core/RISCY_OOO/procs/lib/IndexedMultiset.bsv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/lib/IndexedMultiset.bsv b/src_Core/RISCY_OOO/procs/lib/IndexedMultiset.bsv index cb16715..a148637 100644 --- a/src_Core/RISCY_OOO/procs/lib/IndexedMultiset.bsv +++ b/src_Core/RISCY_OOO/procs/lib/IndexedMultiset.bsv @@ -146,7 +146,7 @@ module mkIndexedMultisetQueue(IndexedMultiset#(Bit#(idxTSz), datT, remWidth)) Reg#(Bit#(TAdd#(idxTSz,1))) ltail <- mkReg(0); idxT head = truncate(lhead); Bit#(TAdd#(idxTSz,1)) level = lhead - ltail; - //Bool empty = (level==0); + Bool empty = (level==0); Bool full = (level==fromInteger(valueOf(TExp#(idxTSz)))); Bool almostFull = (level>=fromInteger(valueOf(TExp#(idxTSz)))-1); @@ -201,7 +201,7 @@ module mkIndexedMultisetQueue(IndexedMultiset#(Bit#(idxTSz), datT, remWidth)) method ActionValue#(IndexedMultisetIndices#(idxT)) insertAndReserve(datT ins, datT res) if (!almostFull); idxT insIdx = head - 1; // Default, assuming a match. idxT resIdx = head - 1; // Default, assuming a match. - if (recsRead[head - 1]!=ins) begin + if (recsRead[head - 1]!=ins || empty) begin insIdx = head; insertW.wset(ins); // Increment head. if (res!=ins) begin