diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
index 44cc2eb..4b7e306 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
@@ -430,7 +430,7 @@ module mkFetchStage(FetchStage);
     // there is no FIFO between doFetch1 and TLB, when OOO commit stage wait
     // TLB idle to change VM CSR / signal flush TLB, there is no wrong path
     // request afterwards to race with the system code that manage paget table.
-    rule doFetch1(started && !(waitForRedirect[0]) && !(waitForFlush[0]));
+    rule doFetch1(started && !waitForRedirect[0] && !waitForFlush[0]);
         let pc = pc_reg[pc_fetch1_port];
 
         // Grab a chain of predictions from the BTB, which predicts targets for the next
@@ -744,6 +744,9 @@ module mkFetchStage(FetchStage);
                            // same reg: push
                            ras.ras[i].popPush(False, Valid (push_addr));
                         end
+                     end else if (!isValid(nextPc)) begin
+                        // A Jr will jump; if we don't have a record, we should wait to prevent wasted work.
+                        nextPc = Valid (-1); // Dummy value to prevent progress.
                      end
                   end