From c766187368e8aa771a4da6f1252e30f5a27647f6 Mon Sep 17 00:00:00 2001
From: gameboo <alexandre.joannou@gmail.com>
Date: Mon, 8 Jul 2024 17:12:47 +0100
Subject: [PATCH] Use only 20 bits of address on the AXI lite port

---
 src_Core/Core/CoreW.bsv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv
index e013905..aa9234c 100644
--- a/src_Core/Core/CoreW.bsv
+++ b/src_Core/Core/CoreW.bsv
@@ -120,7 +120,7 @@ import DM_CPU_Req_Rsp ::*;
 // The Core module
 
 typedef WindCoreMid #( // AXI lite subordinate control port parameters
-                       21, 32, 0, 0, 0, 0, 0
+                       20, 32, 0, 0, 0, 0, 0
                        // AXI manager 0 port parameters
                      , TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0
                        // AXI manager 1 port parameters