diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv index 87ee0f2..b6a7316 100755 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv @@ -101,8 +101,7 @@ typedef struct { Bool isCompressed; // result CapPipe data; // alu compute result - Maybe#(Data) csrData; // data to write CSR file - Maybe#(CapPipe) scrData; // datat to write to special capability register file. + Maybe#(CapMem) csrData; // data to write CSR file ControlFlow controlFlow; Maybe#(CSR_XCapCause) capException; Maybe#(BoundsCheck) check; @@ -172,8 +171,7 @@ interface AluExeInput; `ifdef INCLUDE_TANDEM_VERIF CapPipe dst_data, `endif - Maybe#(Data) csrData, - Maybe#(CapPipe) scrData, + Maybe#(CapMem) csrData, ControlFlow cf, Maybe#(CSR_XCapCause) capCause `ifdef RVFI @@ -208,8 +206,8 @@ interface AluExePipeline; endinterface module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); - Bool verbose = False; - Integer verbosity = 0; + Bool verbose = True; + Integer verbosity = 2; // alu reservation station ReservationStationAlu rsAlu <- mkReservationStationAlu; @@ -336,6 +334,8 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); inIfc.sendBypass[exeSendBypassPort].send(dst.indx, exec_result.data); end + Bool is_scr_or_csr = (isValid(x.dInst.scr) && x.dInst.iType == Scr) || isValid(x.dInst.csr); + // go to next stage exeToFinQ.enq(ToSpecFifo { data: AluExeToFinish { @@ -345,11 +345,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); dpTrain: x.dpTrain, isCompressed: x.orig_inst[1:0] != 2'b11, data: exec_result.data, - csrData: isValid(x.dInst.csr) ? Valid (exec_result.csrData) : tagged Invalid, - // The above case will never be valid due to assertions above, but the below one will be in the case of CJALR. - // This means that we will have instructions that both write SCR registers and also get mispredictions, unlike - // the CSR file. Given the assertions above, this seems dangerous... - scrData: isValid(x.dInst.scr) && x.dInst.iType == Scr ? Valid (exec_result.scrData) : tagged Invalid, + csrData: is_scr_or_csr ? Valid (exec_result.csrData) : tagged Invalid, capException: exec_result.capException, check: exec_result.boundsCheck, `ifdef RVFI @@ -391,7 +387,6 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); x.data, `endif x.csrData, - x.scrData, x.controlFlow, x.capException `ifdef RVFI diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv index 6531543..02ea6f3 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv @@ -220,7 +220,7 @@ function Maybe#(RVFI_DII_Execution#(DataSz,DataSz)) genRVFI(ToReorderBuffer rot, CapPipe cp = cast(ppc); next_pc = getOffset(cp); end - tagged CSRData .csrdata: data = csrdata; + tagged CSRData .csrdata: if (rot.iType == Csr) data = getAddr(csrdata); endcase end CapPipe pipePc = cast(rot.pc); @@ -883,7 +883,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); let csr_idx = validValue(x.csr); Data csr_data = ?; if(x.ppc_vaddr_csrData matches tagged CSRData .d) begin - csr_data = d; + csr_data = getAddr(d); end else begin doAssert(False, "must have csr data"); @@ -910,8 +910,8 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); // inIfc.commitCsrInstOrInterrupt; // TODO Will there be statcounter for SCRs? // write CSR let scr_idx = validValue(x.scr); - CapPipe scr_data = ?; - if(x.ppc_vaddr_csrData matches tagged SCRData .d) begin + CapMem scr_data = ?; + if(x.ppc_vaddr_csrData matches tagged CSRData .d) begin scr_data = d; end else begin diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv index 59923cc..073a1fd 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv @@ -178,7 +178,7 @@ interface MemExeInput; // ROB method CapMem rob_getPC(InstTag t); method Action rob_setExecuted_doFinishMem(InstTag t, - CapPipe vaddr, + CapMem vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit, Bool non_mmio_st_done `ifdef RVFI @@ -603,7 +603,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); if (x.capException matches tagged Valid .c) cause = Valid(CapException(c)); Bool access_at_commit = !isValid(cause) && (isMMIO || isLrScAmo); Bool non_mmio_st_done = !isValid(cause) && !isMMIO && x.mem_func == St; - inIfc.rob_setExecuted_doFinishMem(x.tag, x.vaddr, store_data, store_data_BE, + inIfc.rob_setExecuted_doFinishMem(x.tag, cast(x.vaddr), store_data, store_data_BE, access_at_commit, non_mmio_st_done `ifdef RVFI , ExtraTraceBundle{ diff --git a/src_Core/RISCY_OOO/procs/lib/Exec.bsv b/src_Core/RISCY_OOO/procs/lib/Exec.bsv index 99a94fb..64a63e5 100755 --- a/src_Core/RISCY_OOO/procs/lib/Exec.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Exec.bsv @@ -355,7 +355,6 @@ endfunction function ExecResult basicExec(DecodedInst dInst, CapPipe rVal1, CapPipe rVal2, CapPipe pcc, CapPipe ppc, Bit #(32) orig_inst); // just data, addr, and control flow CapPipe data = nullCap; - Data csr_data = 0; CapPipe addr = nullCap; Bool newPcc = dInst.iType == CJALR || dInst.iType == CCall; @@ -396,7 +395,7 @@ function ExecResult basicExec(DecodedInst dInst, CapPipe rVal1, CapPipe rVal2, C cf.nextPc = setKind(cf.nextPc, UNSEALED); cf.mispredict = cf.nextPc != ppc; - data = (case (dInst.iType) matches + data = (case (dInst.iType) St : rVal2; Sc : rVal2; Amo : rVal2; @@ -411,15 +410,16 @@ function ExecResult basicExec(DecodedInst dInst, CapPipe rVal1, CapPipe rVal2, C Cap : cap_alu_result; default : nullWithAddr(alu_result); endcase); - csr_data = alu_result; + CapMem csr_data = (case (dInst.iType) + Scr: cast(specialRWALU(fromMaybe(rVal1, capImm), rVal2, dInst.capFunc.CapModify.SpecialRW)); + default: nullWithAddr(alu_result); + endcase); addr = (case (dInst.iType) Ld, St, Lr, Sc, Amo : nullWithAddr(alu_result); default : cf.nextPc; //TODO should this be nullified? endcase); - CapPipe scr_data = specialRWALU(fromMaybe(rVal1, capImm), rVal2, dInst.capFunc.CapModify.SpecialRW); - - return ExecResult{data: data, csrData: csr_data, scrData: scr_data, addr: addr, controlFlow: cf, capException: capException, boundsCheck: boundsCheck}; + return ExecResult{data: data, csrData: csr_data, addr: addr, controlFlow: cf, capException: capException, boundsCheck: boundsCheck}; endfunction (* noinline *) diff --git a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv index 882c386..c64bb22 100755 --- a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv @@ -618,8 +618,7 @@ endfunction typedef struct { CapPipe data; - Data csrData; - CapPipe scrData; + CapMem csrData; CapPipe addr; ControlFlow controlFlow; Maybe#(CapException) capException; diff --git a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv index 44d2cd7..94c39db 100755 --- a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv @@ -62,9 +62,8 @@ import Cur_Cycle :: *; // vaddr is only used by mem inst in page fault typedef union tagged { CapMem PPC; // at default store ppc - CapPipe VAddr; // for mem inst, store vaddr - Data CSRData; // for Csr inst, store csr_data - CapPipe SCRData; // for special capability register store + CapMem VAddr; // for mem inst, store vaddr + CapMem CSRData; // for Csr inst, store csr_data } PPCVAddrCSRData deriving(Bits, FShow); `ifdef RVFI @@ -131,8 +130,7 @@ interface Row_setExecuted_doFinishAlu; `ifdef INCLUDE_TANDEM_VERIF CapPipe dst_data, `endif - Maybe#(Data) csrData, - Maybe#(CapPipe) scrData, + Maybe#(CapMem) csrData, ControlFlow cf, Maybe#(CSR_XCapCause) cause `ifdef RVFI @@ -173,7 +171,7 @@ interface ReorderBufferRowEhr#(numeric type aluExeNum, numeric type fpuMulDivExe // perform), and non-MMIO St can become Executed (NOTE faulting // instructions are not Executed, they are set at deqLSQ time) - method Action setExecuted_doFinishMem(CapPipe vaddr, + method Action setExecuted_doFinishMem(CapMem vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit, Bool non_mmio_st_done `ifdef RVFI @@ -302,8 +300,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p `ifdef INCLUDE_TANDEM_VERIF CapPipe dst_data, `endif - Maybe#(Data) csrData, - Maybe#(CapPipe) scrData, + Maybe#(CapMem) csrData, ControlFlow cf, Maybe#(CSR_XCapCause) cause `ifdef RVFI @@ -320,11 +317,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p // update PPC or csrData (vaddr is always useless for ALU results) if(csrData matches tagged Valid .d) begin ppc_vaddr_csrData[pvc_finishAlu_port(i)] <= CSRData (d); - end - else if(scrData matches tagged Valid .d) begin - ppc_vaddr_csrData[pvc_finishAlu_port(i)] <= SCRData (d); - end - else begin + end else begin ppc_vaddr_csrData[pvc_finishAlu_port(i)] <= PPC (cast(cf.nextPc)); end if (cause matches tagged Valid .exp &&& !isValid(trap[trap_finishAlu_port(i)])) begin @@ -335,7 +328,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p //$display("%t : traceBundle = ", $time(), fshow(tb), " in Row_setExecuted_doFinishAlu for %x", pc); traceBundle[trap_finishAlu_port(i)] <= tb; `endif - doAssert(isValid(csr) == isValid(csrData), "csr valid should match"); + doAssert((isValid(csr) || isValid(scr)) == isValid(csrData), "csr valid should match"); endmethod endinterface); end @@ -380,7 +373,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p interface setExecuted_doFinishFpuMulDiv = fpuMulDivExe; - method Action setExecuted_doFinishMem(CapPipe vaddr, + method Action setExecuted_doFinishMem(CapMem vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit, Bool non_mmio_st_done `ifdef RVFI @@ -594,8 +587,7 @@ interface ROB_setExecuted_doFinishAlu; `ifdef INCLUDE_TANDEM_VERIF Data dst_data, `endif - Maybe#(Data) csrData, - Maybe#(CapPipe) scrData, + Maybe#(CapMem) csrData, ControlFlow cf, Maybe#(CSR_XCapCause) cause `ifdef RVFI @@ -648,7 +640,7 @@ interface SupReorderBuffer#(numeric type aluExeNum, numeric type fpuMulDivExeNum interface Vector#(fpuMulDivExeNum, ROB_setExecuted_doFinishFpuMulDiv) setExecuted_doFinishFpuMulDiv; // doFinishMem, after addr translation method Action setExecuted_doFinishMem(InstTag x, - CapPipe vaddr, + CapMem vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit, Bool non_mmio_st_done `ifdef RVFI @@ -1148,8 +1140,7 @@ module mkSupReorderBuffer#( `ifdef INCLUDE_TANDEM_VERIF Data dst_data, `endif - Maybe#(Data) csrData, - Maybe#(CapPipe) scrData, + Maybe#(CapMem) csrData, ControlFlow cf, Maybe#(CSR_XCapCause) cause `ifdef RVFI @@ -1163,7 +1154,6 @@ module mkSupReorderBuffer#( dst_data, `endif csrData, - scrData, cf, cause `ifdef RVFI @@ -1275,7 +1265,7 @@ module mkSupReorderBuffer#( interface setExecuted_doFinishFpuMulDiv = fpuMulDivSetExeIfc; method Action setExecuted_doFinishMem( - InstTag x, CapPipe vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit, + InstTag x, CapMem vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit, Bool non_mmio_st_done `ifdef RVFI , tb