From c8fde208e99e9a215ba8ea40171dc5ec1b4ab8ea Mon Sep 17 00:00:00 2001 From: rsnikhil Date: Tue, 11 Feb 2020 19:55:26 -0500 Subject: [PATCH] Fixed typo in TV_Encode.bsv; now successfully running with both GDB and Tandem Verif --- src_Core/Core/TV_Encode.bsv | 7 +++++- src_Core/Core/TV_Taps.bsv | 45 +++++++++++++++++++++++-------------- 2 files changed, 34 insertions(+), 18 deletions(-) diff --git a/src_Core/Core/TV_Encode.bsv b/src_Core/Core/TV_Encode.bsv index b8f80b5..40b7752 100644 --- a/src_Core/Core/TV_Encode.bsv +++ b/src_Core/Core/TV_Encode.bsv @@ -70,13 +70,17 @@ module mkTV_Encode (TV_Encode_IFC); // TODO: currently always sending full PC Reg #(WordXL) rg_last_pc <- mkReg (0); + // Superscalar-wide inputs from CPU Vector #(SupSize, FIFOF #(Tuple2 #(Bit #(64), Trace_Data))) v_f_cpu_ins <- replicateM (mkFIFOF); Reg #(Bit #(64)) rg_serialnum <- mkReg (0); + // Input from Debug Module FIFOF #(Trace_Data) f_dm_in <- mkFIFOF; + // Merges CPU and Debug Module inputs FIFOF #(Trace_Data) f_merged <- mkFIFOF; + // Encoded output FIFOF #(Tuple2 #(Bit #(32), TV_Vec_Bytes)) f_out <- mkFIFOF; // ---------------------------------------------------------------- @@ -98,7 +102,8 @@ module mkTV_Encode (TV_Encode_IFC); // f_dm_ins is merged in at any time rule rl_merge_dm_in; - let td <- pop (f_dm_in.first); + // let td <- pop (f_dm_in.first); // Surprise: this gives no type-check error? + let td = f_dm_in.first; f_dm_in.deq; f_merged.enq (td); if (verbosity != 0) begin diff --git a/src_Core/Core/TV_Taps.bsv b/src_Core/Core/TV_Taps.bsv index dedd50a..3c67d79 100644 --- a/src_Core/Core/TV_Taps.bsv +++ b/src_Core/Core/TV_Taps.bsv @@ -1,4 +1,4 @@ -// Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved. +// Copyright (c) 2018-2020 Bluespec, Inc. All Rights Reserved. package TV_Taps; @@ -73,24 +73,35 @@ module mkDM_Mem_Tap (DM_Mem_Tap_IFC); master_xactor.i_wr_data.enq (wr_data); // Tap - Bit #(64) paddr = ?; - Bit #(64) stval = ?; + Bit #(64) paddr = ?; + Bit #(64) stval = ?; + Integer sh = 0; + Fabric_Data mask = 0; + MemReqSize sz = ?; + + case (wr_data.wstrb) `ifdef FABRIC64 - if (wr_data.wstrb == 'h0f) begin - paddr = zeroExtend (wr_addr.awaddr); - stval = (wr_data.wdata & 'h_FFFF_FFFF); - end - else if (wr_data.wstrb == 'hf0) begin - paddr = zeroExtend (wr_addr.awaddr); - stval = ((wr_data.wdata >> 32) & 'h_FFFF_FFFF); - end - else - dynamicAssert(False, "mkDM_Mem_Tap: unsupported byte enables"); -`else + 'hFF: begin sh= 0; mask = 'hFFFF_FFFF_FFFF_FFFF; sz=f3_SIZE_D; end + 'hF0: begin sh=32; mask = 'hFFFF_FFFF; sz=f3_SIZE_W; end + 'hC0: begin sh=48; mask = 'hFFFF; sz=f3_SIZE_H; end + 'h30: begin sh=32; mask = 'hFFFF; sz=f3_SIZE_H; end + 'h80: begin sh=56; mask = 'hFF; sz=f3_SIZE_B; end + 'h40: begin sh=48; mask = 'hFF; sz=f3_SIZE_B; end + 'h20: begin sh=40; mask = 'hFF; sz=f3_SIZE_B; end + 'h10: begin sh=32; mask = 'hFF; sz=f3_SIZE_B; end +`endif + 'hF: begin sh= 0; mask = 'hFFFF_FFFF; sz=f3_SIZE_W; end + 'hC: begin sh=16; mask = 'hFFFF; sz=f3_SIZE_H; end + 'h3: begin sh= 0; mask = 'hFFFF; sz=f3_SIZE_H; end + 'h8: begin sh=24; mask = 'hFF; sz=f3_SIZE_B; end + 'h4: begin sh=16; mask = 'hFF; sz=f3_SIZE_B; end + 'h2: begin sh= 8; mask = 'hFF; sz=f3_SIZE_B; end + 'h1: begin sh= 0; mask = 'hFF; sz=f3_SIZE_B; end + default: dynamicAssert(False, "mkDM_Mem_Tap: unsupported byte enables"); + endcase paddr = zeroExtend (wr_addr.awaddr); - stval = zeroExtend (wr_data.wdata); -`endif - Trace_Data td = mkTrace_MEM_WRITE (f3_SIZE_W, truncate (stval), paddr); + stval = ((zeroExtend (wr_data.wdata) >> sh) & mask); + Trace_Data td = mkTrace_MEM_WRITE (sz, truncate (stval), paddr); f_trace_data.enq (td); endrule