diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
index 907596d..e164744 100755
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
@@ -215,7 +215,7 @@ interface AluExePipeline;
 endinterface
 
 module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
-    Bool verbose = False;
+    Bool verbose = True;
     Integer verbosity = 0;
 
     // alu reservation station
@@ -302,7 +302,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
         let ppc_addr = getAddr(ppc);
         let pc_addr = getAddr(pc);
         EventsTransExe events = unpack(0);
-        if(x.dInst.iType == Br) begin
+        if(x.dInst.iType == Br || x.dInst.iType == CJAL || x.dInst.iType == J) begin
             Bit#(32) imm = fromMaybe(32'h00000000, x.dInst.imm);
             let val = pc_addr + signExtend(imm);
             if((val != ppc_addr) && (ppc_addr != pc_addr + 2) && (ppc_addr != pc_addr + 4)) begin
@@ -312,9 +312,12 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
             end
         end
 
-        else if(x.dInst.iType == CJALR || x.dInst.iType == Jr || x.dInst.iType == CJAL || x.dInst.iType == J) begin
+        
+
+        else if(x.dInst.iType == CJALR || x.dInst.iType == Jr) begin
             let res_targets = inIfc.checkTarget(ppc);
             let res_ret_targets = inIfc.checkReturnTarget(ppc);
+            $display("pc = ", fshow(pc), "res_targets = ", fshow(res_targets), " res_ret_targets = ", fshow(res_ret_targets));
             if(!res_targets && !res_ret_targets && (ppc_addr != pc_addr + 2) && (ppc_addr != pc_addr + 4)) begin
                 $display("Wild indirect jump: pc = ", fshow(pc), " ppc = ", fshow(ppc));
                 events.evt_WILD_JUMP = 1;
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
index 219f5fd..aebd55c 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
@@ -1152,16 +1152,26 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
                         end
                         return res;
                     endfunction
+                    function Bool is_16b_inst (Bit #(n) inst);
+                        return (inst [1:0] != 2'b11);
+                    endfunction
 
                     // update return target
-                    if((x.iType == J || x.iType == CJAL) && linkedR(x.dst)) begin
-                        retTar = tagged Valid x.ppc_vaddr_csrData.PPC;
+                    if(x.iType == J || x.iType == CJAL || x.iType == CJALR || x.iType == Jr) begin
+                        tar = tagged Valid x.ppc_vaddr_csrData.PPC;
+                        $display("BRANCH target added: pc = ", fshow(x.pc), " tar = ", fshow(tar));
+                        if(linkedR(x.dst)) begin
+                            let imm = is_16b_inst(x.orig_inst) ? 2 : 4;
+                            retTar = tagged Valid addPc(x.pc, imm);
+                            $display("RETURN target added: pc = ", fshow(x.pc), " retTar = ", fshow(retTar));
+                        end
                     end
 
                     // update target
-                    if(x.iType == CJALR || x.iType == Jr) begin
+                    /*else if((x.iType == CJALR || x.iType == Jr) && !linkedR(x.dst)) begin
                         tar = tagged Valid x.ppc_vaddr_csrData.PPC;
-                    end
+                        $display("BRANCH target added: pc = ", fshow(x.pc), " ppc = ", fshow(tar));
+                    end*/
 
                     // every inst here should have been renamed, commit renaming
                     regRenamingTable.commit[i].commit;