From ca4e120a6c2c1c9063ce9ce49b8dcb0334695098 Mon Sep 17 00:00:00 2001
From: Jonathan Woodruff <jdw57@cam.ac.uk>
Date: Mon, 22 Jan 2024 12:06:39 +0000
Subject: [PATCH] Use DReg instead of Reg, as intended.

---
 src_Core/RISCY_OOO/procs/lib/ITlb.bsv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src_Core/RISCY_OOO/procs/lib/ITlb.bsv b/src_Core/RISCY_OOO/procs/lib/ITlb.bsv
index ecb12b7..b160f5a 100644
--- a/src_Core/RISCY_OOO/procs/lib/ITlb.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/ITlb.bsv
@@ -43,6 +43,7 @@ import ProcTypes::*;
 import TlbTypes::*;
 import Performance::*;
 import FullAssocTlb::*;
+import DReg::*;
 import ConfigReg::*;
 import Fifos::*;
 import Cntrs::*;
@@ -249,7 +250,7 @@ module mkITlb(ITlb::ITlb);
         no_pending_wire <= !isValid(miss);
     endrule
 
-    Reg#(Bool) vm_info_change <- mkReg(False);
+    Reg#(Bool) vm_info_change <- mkDReg(False);
 
     method Action flush if(!needFlush);
         needFlush <= True;