From cc25ee69d352ebe15ef12becbee543b008bc0ed0 Mon Sep 17 00:00:00 2001
From: Franz Fuchs <franz.fuchs@cl.cam.ac.uk>
Date: Mon, 26 Jul 2021 07:02:21 +0100
Subject: [PATCH] Check in Rename stage for nextPcs of Traps

---
 src_Core/CPU/Core.bsv                              |  2 +-
 src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 11 +++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index f1cf9e7..ff1ddd2 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -1188,7 +1188,7 @@ module mkCore#(CoreId coreId)(Core);
 `ifdef CONTRACTS_VERIFY
      EventsTransExe transExe = renameStage.events;
      SupCnt wildJumps = 0;
-     SupCnt wildExceptions = 0;
+     SupCnt wildExceptions = transExe.evt_WILD_EXCEPTION;
      for(Integer i = 0; i < valueof(AluExeNum); i = i+1) begin
           let alu_events = coreFix.aluExeIfc[i].events;
           wildJumps = wildJumps + alu_events.evt_WILD_JUMP;
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
index 081b156..126b0bb 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
@@ -394,6 +394,17 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
         end
 `endif
 
+`ifdef PERFORMANCE_MONITORING
+`ifdef CONTRACTS_VERIFY
+        let validPc = (x.orig_inst[1:0] != 2'b11) ? addPc(pc,2) : addPc(pc,4);
+        if((ppc != validPc)) begin
+            EventsTransExe events = unpack(0);
+            events.evt_WILD_EXCEPTION = 1;
+            events_reg <= events;
+        end
+`endif
+`endif
+
 `ifdef CHECK_DEADLOCK
         renameCorrectPath.send;
 `endif