diff --git a/src_Core/RISCY_OOO/coherence/src/LLPipe.bsv b/src_Core/RISCY_OOO/coherence/src/LLPipe.bsv
index 1ad59af..b7a4050 100644
--- a/src_Core/RISCY_OOO/coherence/src/LLPipe.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/LLPipe.bsv
@@ -162,9 +162,9 @@ module mkLLPipe(
    Bool verbose = False;
 
     // RAMs
-    Vector#(wayNum, RWBramCore#(indexT, infoT)) infoRam <- replicateM(mkRWBramCore);
+    Vector#(wayNum, RWBramCore#(indexT, infoT)) infoRam <- replicateM(mkRWBramCoreForwarded);
     RWBramCore#(indexT, repT) repRam <- mkRandRepRam;
-    Vector#(wayNum, RWBramCore#(indexT, Line)) dataRam <- replicateM(mkRWBramCore);
+    Vector#(wayNum, RWBramCore#(indexT, Line)) dataRam <- replicateM(mkRWBramCoreForwarded);
 
     // initialize RAM
     Reg#(Bool) initDone <- mkReg(False);