From ccc71952bf02162a0a3422e6cd1c76a39f9045e3 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Thu, 1 Feb 2024 13:44:36 +0000 Subject: [PATCH] Use forwarding BRAMs in L2 Cache. Duh; this is required for the new CCPipe structure. --- src_Core/RISCY_OOO/coherence/src/LLPipe.bsv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src_Core/RISCY_OOO/coherence/src/LLPipe.bsv b/src_Core/RISCY_OOO/coherence/src/LLPipe.bsv index 1ad59af..b7a4050 100644 --- a/src_Core/RISCY_OOO/coherence/src/LLPipe.bsv +++ b/src_Core/RISCY_OOO/coherence/src/LLPipe.bsv @@ -162,9 +162,9 @@ module mkLLPipe( Bool verbose = False; // RAMs - Vector#(wayNum, RWBramCore#(indexT, infoT)) infoRam <- replicateM(mkRWBramCore); + Vector#(wayNum, RWBramCore#(indexT, infoT)) infoRam <- replicateM(mkRWBramCoreForwarded); RWBramCore#(indexT, repT) repRam <- mkRandRepRam; - Vector#(wayNum, RWBramCore#(indexT, Line)) dataRam <- replicateM(mkRWBramCore); + Vector#(wayNum, RWBramCore#(indexT, Line)) dataRam <- replicateM(mkRWBramCoreForwarded); // initialize RAM Reg#(Bool) initDone <- mkReg(False);